diff --git a/.gitignore b/.gitignore index 4de7e1a..ca28689 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,5 @@ * - +!*/ !.gitignore !Makefile !src/ @@ -9,8 +9,10 @@ !sim/ !misc/ !pcb/ +!CCS/** +!CCS/mm/ !**/*.c -!**/*.s +!**/*.st !**/*.h !**/*.md !**/*.ld diff --git a/CCS/mm/.ccsproject b/CCS/mm/.ccsproject new file mode 100644 index 0000000..5f882b9 --- /dev/null +++ b/CCS/mm/.ccsproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + diff --git a/CCS/mm/.cproject b/CCS/mm/.cproject new file mode 100644 index 0000000..52819f2 --- /dev/null +++ b/CCS/mm/.cproject @@ -0,0 +1,249 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CCS/mm/.gitignore b/CCS/mm/.gitignore new file mode 100644 index 0000000..b9035dd --- /dev/null +++ b/CCS/mm/.gitignore @@ -0,0 +1,4 @@ +Release/* +.xdchelp +config/* +/Debug/ diff --git a/CCS/mm/.launches/gpiointerrupt_EK_TM4C123GXL_TI.launch b/CCS/mm/.launches/gpiointerrupt_EK_TM4C123GXL_TI.launch new file mode 100644 index 0000000..b09487a --- /dev/null +++ b/CCS/mm/.launches/gpiointerrupt_EK_TM4C123GXL_TI.launch @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/CCS/mm/.launches/mm.launch b/CCS/mm/.launches/mm.launch new file mode 100644 index 0000000..cad57e2 --- /dev/null +++ b/CCS/mm/.launches/mm.launch @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/CCS/mm/.project b/CCS/mm/.project new file mode 100644 index 0000000..6908e4c --- /dev/null +++ b/CCS/mm/.project @@ -0,0 +1,28 @@ + + + mm + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.rtsc.xdctools.buildDefinitions.XDC.xdcNature + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/CCS/mm/.settings/com.ti.ccstudio.project.core.prefs b/CCS/mm/.settings/com.ti.ccstudio.project.core.prefs new file mode 100644 index 0000000..76e251e --- /dev/null +++ b/CCS/mm/.settings/com.ti.ccstudio.project.core.prefs @@ -0,0 +1,4 @@ +ccsVersionValidationPolicy=warning +compilerVersionValidationPolicy=flexible +eclipse.preferences.version=1 +productVersionsValidationPolicy=flexible diff --git a/CCS/mm/.settings/org.eclipse.cdt.codan.core.prefs b/CCS/mm/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/CCS/mm/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/CCS/mm/.settings/org.eclipse.cdt.debug.core.prefs b/CCS/mm/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000..2adc7b1 --- /dev/null +++ b/CCS/mm/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/CCS/mm/.settings/org.eclipse.core.resources.prefs b/CCS/mm/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..f9d60ad --- /dev/null +++ b/CCS/mm/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,10 @@ +eclipse.preferences.version=1 +encoding//Debug/lib/subdir_rules.mk=UTF-8 +encoding//Debug/lib/subdir_vars.mk=UTF-8 +encoding//Debug/makefile=UTF-8 +encoding//Debug/objects.mk=UTF-8 +encoding//Debug/sources.mk=UTF-8 +encoding//Debug/src/sysbios/subdir_rules.mk=UTF-8 +encoding//Debug/src/sysbios/subdir_vars.mk=UTF-8 +encoding//Debug/subdir_rules.mk=UTF-8 +encoding//Debug/subdir_vars.mk=UTF-8 diff --git a/CCS/mm/Board.h b/CCS/mm/Board.h new file mode 100644 index 0000000..6165f37 --- /dev/null +++ b/CCS/mm/Board.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_H +#define __BOARD_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "EK_TM4C123GXL.h" + +#define Board_initDMA EK_TM4C123GXL_initDMA +#define Board_initGeneral EK_TM4C123GXL_initGeneral +#define Board_initGPIO EK_TM4C123GXL_initGPIO +#define Board_initI2C EK_TM4C123GXL_initI2C +#define Board_initPWM EK_TM4C123GXL_initPWM +#define Board_initSDSPI EK_TM4C123GXL_initSDSPI +#define Board_initSPI EK_TM4C123GXL_initSPI +#define Board_initUART EK_TM4C123GXL_initUART +#define Board_initUSB EK_TM4C123GXL_initUSB +#define Board_initWatchdog EK_TM4C123GXL_initWatchdog +#define Board_initWiFi EK_TM4C123GXL_initWiFi + +#define Board_LED_ON EK_TM4C123GXL_LED_ON +#define Board_LED_OFF EK_TM4C123GXL_LED_OFF +#define Board_LED0 EK_TM4C123GXL_LED_BLUE +#define Board_LED1 EK_TM4C123GXL_LED_GREEN +#define Board_LED2 EK_TM4C123GXL_LED_RED +#define Board_BUTTON0 EK_TM4C123GXL_SW1 +#define Board_BUTTON1 EK_TM4C123GXL_SW2 + +#define Board_I2C0 EK_TM4C123GXL_I2C0 +#define Board_I2C1 EK_TM4C123GXL_I2C3 +#define Board_I2C_TMP EK_TM4C123GXL_I2C3 +#define Board_I2C_NFC EK_TM4C123GXL_I2C3 +#define Board_I2C_TPL0401 EK_TM4C123GXL_I2C3 + +#define Board_PWM0 EK_TM4C123GXL_PWM6 +#define Board_PWM1 EK_TM4C123GXL_PWM7 + +#define Board_SDSPI0 EK_TM4C123GXL_SDSPI0 + +#define Board_SPI0 EK_TM4C123GXL_SPI0 +#define Board_SPI1 EK_TM4C123GXL_SPI3 + +#define Board_USBDEVICE EK_TM4C123GXL_USBDEVICE + +#define Board_UART0 EK_TM4C123GXL_UART0 + +#define Board_WATCHDOG0 EK_TM4C123GXL_WATCHDOG0 + +#define Board_WIFI EK_TM4C123GXL_WIFI +#define Board_WIFI_SPI EK_TM4C123GXL_SPI2 + +/* Board specific I2C addresses */ +#define Board_TMP006_ADDR (0x40) +#define Board_RF430CL330_ADDR (0x28) +#define Board_TPL0401_ADDR (0x40) + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H */ diff --git a/CCS/mm/Debug/EK_TM4C123GXL.asm b/CCS/mm/Debug/EK_TM4C123GXL.asm new file mode 100644 index 0000000..ac9b0a1 --- /dev/null +++ b/CCS/mm/Debug/EK_TM4C123GXL.asm @@ -0,0 +1,32511 @@ +;****************************************************************************** +;* TI ARM G3 C/C++ Codegen PC v18.12.4.LTS * +;* Date/Time created: Sat Sep 19 20:39:24 2020 * +;****************************************************************************** + .compiler_opts --abi=eabi --arm_vmrs_si_workaround=off --code_state=16 --diag_wrap=off --embedded_constants=on --endian=little --float_support=FPv4SPD16 --hll_source=on --object_format=elf --silicon_version=7M4 --symdebug:dwarf --symdebug:dwarf_version=3 --unaligned_access=on + .thumb + +$C$DW$CU .dwtag DW_TAG_compile_unit + .dwattr $C$DW$CU, DW_AT_name("../EK_TM4C123GXL.c") + .dwattr $C$DW$CU, DW_AT_producer("TI TI ARM G3 C/C++ Codegen PC v18.12.4.LTS Copyright (c) 1996-2018 Texas Instruments Incorporated") + .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + .dwattr $C$DW$CU, DW_AT_comp_dir("C:\Users\zachr\workspace_v9\mm\Debug") +dmaControlTable: .usect ".bss:dmaControlTable",512,1024 +$C$DW$1 .dwtag DW_TAG_variable + .dwattr $C$DW$1, DW_AT_name("dmaControlTable") + .dwattr $C$DW$1, DW_AT_TI_symbol_name("dmaControlTable") + .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$964) + .dwattr $C$DW$1, DW_AT_location[DW_OP_addr dmaControlTable] + .dwattr $C$DW$1, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$1, DW_AT_decl_line(0x4d) + .dwattr $C$DW$1, DW_AT_decl_column(0x19) + + .data + .align 1 + .elfsym dmaInitialized,SYM_SIZE(1) +dmaInitialized: + .bits 0,8 + ; dmaInitialized @ 0 + +$C$DW$2 .dwtag DW_TAG_variable + .dwattr $C$DW$2, DW_AT_name("dmaInitialized") + .dwattr $C$DW$2, DW_AT_TI_symbol_name("dmaInitialized") + .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$2, DW_AT_location[DW_OP_addr dmaInitialized] + .dwattr $C$DW$2, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$2, DW_AT_decl_line(0x4e) + .dwattr $C$DW$2, DW_AT_decl_column(0x0d) + +dmaHwiStruct: .usect ".bss:dmaHwiStruct",28,4 +$C$DW$3 .dwtag DW_TAG_variable + .dwattr $C$DW$3, DW_AT_name("dmaHwiStruct") + .dwattr $C$DW$3, DW_AT_TI_symbol_name("dmaHwiStruct") + .dwattr $C$DW$3, DW_AT_type(*$C$DW$T$210) + .dwattr $C$DW$3, DW_AT_location[DW_OP_addr dmaHwiStruct] + .dwattr $C$DW$3, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$3, DW_AT_decl_line(0x51) + .dwattr $C$DW$3, DW_AT_decl_column(0x13) + + .global gpioPinConfigs + .sect ".data:gpioPinConfigs", RW + .align 4 + .elfsym gpioPinConfigs,SYM_SIZE(20) +gpioPinConfigs: + .bits 0x2030510,32 + ; gpioPinConfigs[0] @ 0 + .bits 0x2030501,32 + ; gpioPinConfigs[1] @ 32 + .bits 0x200502,32 + ; gpioPinConfigs[2] @ 64 + .bits 0x200504,32 + ; gpioPinConfigs[3] @ 96 + .bits 0x200508,32 + ; gpioPinConfigs[4] @ 128 + +$C$DW$4 .dwtag DW_TAG_variable + .dwattr $C$DW$4, DW_AT_name("gpioPinConfigs") + .dwattr $C$DW$4, DW_AT_TI_symbol_name("gpioPinConfigs") + .dwattr $C$DW$4, DW_AT_location[DW_OP_addr gpioPinConfigs] + .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$1754) + .dwattr $C$DW$4, DW_AT_external + .dwattr $C$DW$4, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$4, DW_AT_decl_line(0x99) + .dwattr $C$DW$4, DW_AT_decl_column(0x10) + + .global gpioCallbackFunctions + .sect ".data:gpioCallbackFunctions", RW + .align 4 + .elfsym gpioCallbackFunctions,SYM_SIZE(8) +gpioCallbackFunctions: + .bits 0,32 + ; gpioCallbackFunctions[0] @ 0 + .bits 0,32 + ; gpioCallbackFunctions[1] @ 32 + +$C$DW$5 .dwtag DW_TAG_variable + .dwattr $C$DW$5, DW_AT_name("gpioCallbackFunctions") + .dwattr $C$DW$5, DW_AT_TI_symbol_name("gpioCallbackFunctions") + .dwattr $C$DW$5, DW_AT_location[DW_OP_addr gpioCallbackFunctions] + .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$1245) + .dwattr $C$DW$5, DW_AT_external + .dwattr $C$DW$5, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$5, DW_AT_decl_line(0xb0) + .dwattr $C$DW$5, DW_AT_decl_column(0x12) + + .global GPIOTiva_config + .sect ".const:GPIOTiva_config" + .align 4 + .elfsym GPIOTiva_config,SYM_SIZE(20) +GPIOTiva_config: + .bits gpioPinConfigs,32 ; GPIOTiva_config.pinConfigs @ 0 + .bits gpioCallbackFunctions,32 ; GPIOTiva_config.callbacks @ 32 + .bits 0x5,32 + ; GPIOTiva_config.numberOfPinConfigs @ 64 + .bits 0x2,32 + ; GPIOTiva_config.numberOfCallbacks @ 96 + .bits 0xffffffff,32 + ; GPIOTiva_config.intPriority @ 128 + +$C$DW$6 .dwtag DW_TAG_variable + .dwattr $C$DW$6, DW_AT_name("GPIOTiva_config") + .dwattr $C$DW$6, DW_AT_TI_symbol_name("GPIOTiva_config") + .dwattr $C$DW$6, DW_AT_location[DW_OP_addr GPIOTiva_config] + .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$1000) + .dwattr $C$DW$6, DW_AT_external + .dwattr $C$DW$6, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$6, DW_AT_decl_line(0xb6) + .dwattr $C$DW$6, DW_AT_decl_column(0x17) + +$C$DW$7 .dwtag DW_TAG_variable + .dwattr $C$DW$7, DW_AT_name("I2CTiva_fxnTable") + .dwattr $C$DW$7, DW_AT_TI_symbol_name("I2CTiva_fxnTable") + .dwattr $C$DW$7, DW_AT_type(*$C$DW$T$220) + .dwattr $C$DW$7, DW_AT_declaration + .dwattr $C$DW$7, DW_AT_external + .dwattr $C$DW$7, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$7, DW_AT_decl_line(0x5c) + .dwattr $C$DW$7, DW_AT_decl_column(0x1b) + + .global i2cTivaObjects + .common i2cTivaObjects,256,4 +$C$DW$8 .dwtag DW_TAG_variable + .dwattr $C$DW$8, DW_AT_name("i2cTivaObjects") + .dwattr $C$DW$8, DW_AT_TI_symbol_name("i2cTivaObjects") + .dwattr $C$DW$8, DW_AT_location[DW_OP_addr i2cTivaObjects] + .dwattr $C$DW$8, DW_AT_type(*$C$DW$T$1006) + .dwattr $C$DW$8, DW_AT_external + .dwattr $C$DW$8, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$8, DW_AT_decl_line(0xd8) + .dwattr $C$DW$8, DW_AT_decl_column(0x10) + + .global i2cTivaHWAttrs + .sect ".const:i2cTivaHWAttrs" + .align 4 + .elfsym i2cTivaHWAttrs,SYM_SIZE(24) +i2cTivaHWAttrs: + .bits 0x40021000,32 + ; i2cTivaHWAttrs[0].baseAddr @ 0 + .bits 0x35,32 + ; i2cTivaHWAttrs[0].intNum @ 32 + .bits 0xffffffff,32 + ; i2cTivaHWAttrs[0].intPriority @ 64 + .bits 0x40023000,32 + ; i2cTivaHWAttrs[1].baseAddr @ 96 + .bits 0x55,32 + ; i2cTivaHWAttrs[1].intNum @ 128 + .bits 0xffffffff,32 + ; i2cTivaHWAttrs[1].intPriority @ 160 + +$C$DW$9 .dwtag DW_TAG_variable + .dwattr $C$DW$9, DW_AT_name("i2cTivaHWAttrs") + .dwattr $C$DW$9, DW_AT_TI_symbol_name("i2cTivaHWAttrs") + .dwattr $C$DW$9, DW_AT_location[DW_OP_addr i2cTivaHWAttrs] + .dwattr $C$DW$9, DW_AT_type(*$C$DW$T$1003) + .dwattr $C$DW$9, DW_AT_external + .dwattr $C$DW$9, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$9, DW_AT_decl_line(0xda) + .dwattr $C$DW$9, DW_AT_decl_column(0x17) + + .global I2C_config + .sect ".const:I2C_config" + .align 4 + .elfsym I2C_config,SYM_SIZE(36) +I2C_config: + .bits I2CTiva_fxnTable,32 ; I2C_config[0].fxnTablePtr @ 0 + .bits i2cTivaObjects,32 ; I2C_config[0].object @ 32 + .bits i2cTivaHWAttrs,32 ; I2C_config[0].hwAttrs @ 64 + .bits I2CTiva_fxnTable,32 ; I2C_config[1].fxnTablePtr @ 96 + .bits i2cTivaObjects + 128,32 ; I2C_config[1].object @ 128 + .bits i2cTivaHWAttrs + 12,32 ; I2C_config[1].hwAttrs @ 160 + .bits 0,32 + ; I2C_config[2].fxnTablePtr @ 192 + .bits 0,32 + ; I2C_config[2].object @ 224 + .bits 0,32 + ; I2C_config[2].hwAttrs @ 256 + +$C$DW$10 .dwtag DW_TAG_variable + .dwattr $C$DW$10, DW_AT_name("I2C_config") + .dwattr $C$DW$10, DW_AT_TI_symbol_name("I2C_config") + .dwattr $C$DW$10, DW_AT_location[DW_OP_addr I2C_config] + .dwattr $C$DW$10, DW_AT_type(*$C$DW$T$1010) + .dwattr $C$DW$10, DW_AT_external + .dwattr $C$DW$10, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$10, DW_AT_decl_line(0xe7) + .dwattr $C$DW$10, DW_AT_decl_column(0x12) + +$C$DW$11 .dwtag DW_TAG_variable + .dwattr $C$DW$11, DW_AT_name("PWMTiva_fxnTable") + .dwattr $C$DW$11, DW_AT_TI_symbol_name("PWMTiva_fxnTable") + .dwattr $C$DW$11, DW_AT_type(*$C$DW$T$256) + .dwattr $C$DW$11, DW_AT_declaration + .dwattr $C$DW$11, DW_AT_external + .dwattr $C$DW$11, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$11, DW_AT_decl_line(0x98) + .dwattr $C$DW$11, DW_AT_decl_column(0x1b) + + .global pwmTivaObjects + .common pwmTivaObjects,16,4 +$C$DW$12 .dwtag DW_TAG_variable + .dwattr $C$DW$12, DW_AT_name("pwmTivaObjects") + .dwattr $C$DW$12, DW_AT_TI_symbol_name("pwmTivaObjects") + .dwattr $C$DW$12, DW_AT_location[DW_OP_addr pwmTivaObjects] + .dwattr $C$DW$12, DW_AT_type(*$C$DW$T$1016) + .dwattr $C$DW$12, DW_AT_external + .dwattr $C$DW$12, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$12, DW_AT_decl_line(0x12a) + .dwattr $C$DW$12, DW_AT_decl_column(0x10) + + .global pwmTivaHWAttrs + .sect ".const:pwmTivaHWAttrs" + .align 4 + .elfsym pwmTivaHWAttrs,SYM_SIZE(24) +pwmTivaHWAttrs: + .bits 0x40029000,32 + ; pwmTivaHWAttrs[0].baseAddr @ 0 + .bits 0x106,32 + ; pwmTivaHWAttrs[0].pwmOutput @ 32 + .bits 0x4,32 + ; pwmTivaHWAttrs[0].pwmGenOpts @ 64 + .bits 0x40029000,32 + ; pwmTivaHWAttrs[1].baseAddr @ 96 + .bits 0x107,32 + ; pwmTivaHWAttrs[1].pwmOutput @ 128 + .bits 0x4,32 + ; pwmTivaHWAttrs[1].pwmGenOpts @ 160 + +$C$DW$13 .dwtag DW_TAG_variable + .dwattr $C$DW$13, DW_AT_name("pwmTivaHWAttrs") + .dwattr $C$DW$13, DW_AT_TI_symbol_name("pwmTivaHWAttrs") + .dwattr $C$DW$13, DW_AT_location[DW_OP_addr pwmTivaHWAttrs] + .dwattr $C$DW$13, DW_AT_type(*$C$DW$T$1013) + .dwattr $C$DW$13, DW_AT_external + .dwattr $C$DW$13, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$13, DW_AT_decl_line(0x12c) + .dwattr $C$DW$13, DW_AT_decl_column(0x17) + + .global PWM_config + .sect ".const:PWM_config" + .align 4 + .elfsym PWM_config,SYM_SIZE(36) +PWM_config: + .bits PWMTiva_fxnTable,32 ; PWM_config[0].fxnTablePtr @ 0 + .bits pwmTivaObjects,32 ; PWM_config[0].object @ 32 + .bits pwmTivaHWAttrs,32 ; PWM_config[0].hwAttrs @ 64 + .bits PWMTiva_fxnTable,32 ; PWM_config[1].fxnTablePtr @ 96 + .bits pwmTivaObjects + 8,32 ; PWM_config[1].object @ 128 + .bits pwmTivaHWAttrs + 12,32 ; PWM_config[1].hwAttrs @ 160 + .bits 0,32 + ; PWM_config[2].fxnTablePtr @ 192 + .bits 0,32 + ; PWM_config[2].object @ 224 + .bits 0,32 + ; PWM_config[2].hwAttrs @ 256 + +$C$DW$14 .dwtag DW_TAG_variable + .dwattr $C$DW$14, DW_AT_name("PWM_config") + .dwattr $C$DW$14, DW_AT_TI_symbol_name("PWM_config") + .dwattr $C$DW$14, DW_AT_location[DW_OP_addr PWM_config] + .dwattr $C$DW$14, DW_AT_type(*$C$DW$T$1020) + .dwattr $C$DW$14, DW_AT_external + .dwattr $C$DW$14, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$14, DW_AT_decl_line(0x139) + .dwattr $C$DW$14, DW_AT_decl_column(0x12) + +$C$DW$15 .dwtag DW_TAG_variable + .dwattr $C$DW$15, DW_AT_name("SDSPITiva_fxnTable") + .dwattr $C$DW$15, DW_AT_TI_symbol_name("SDSPITiva_fxnTable") + .dwattr $C$DW$15, DW_AT_type(*$C$DW$T$294) + .dwattr $C$DW$15, DW_AT_declaration + .dwattr $C$DW$15, DW_AT_external + .dwattr $C$DW$15, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$15, DW_AT_decl_line(0x67) + .dwattr $C$DW$15, DW_AT_decl_column(0x1d) + + .global sdspiTivaObjects + .common sdspiTivaObjects,576,4 +$C$DW$16 .dwtag DW_TAG_variable + .dwattr $C$DW$16, DW_AT_name("sdspiTivaObjects") + .dwattr $C$DW$16, DW_AT_TI_symbol_name("sdspiTivaObjects") + .dwattr $C$DW$16, DW_AT_location[DW_OP_addr sdspiTivaObjects] + .dwattr $C$DW$16, DW_AT_type(*$C$DW$T$1028) + .dwattr $C$DW$16, DW_AT_external + .dwattr $C$DW$16, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$16, DW_AT_decl_line(0x166) + .dwattr $C$DW$16, DW_AT_decl_column(0x12) + + .global sdspiTivaHWattrs + .sect ".const:sdspiTivaHWattrs" + .align 4 + .elfsym sdspiTivaHWattrs,SYM_SIZE(36) +sdspiTivaHWattrs: + .bits 0x4000a000,32 + ; sdspiTivaHWattrs[0].baseAddr @ 0 + .bits 0x40005000,32 + ; sdspiTivaHWattrs[0].portSCK @ 32 + .bits 0x10,32 + ; sdspiTivaHWattrs[0].pinSCK @ 64 + .bits 0x40005000,32 + ; sdspiTivaHWattrs[0].portMISO @ 96 + .bits 0x40,32 + ; sdspiTivaHWattrs[0].pinMISO @ 128 + .bits 0x40005000,32 + ; sdspiTivaHWattrs[0].portMOSI @ 160 + .bits 0x80,32 + ; sdspiTivaHWattrs[0].pinMOSI @ 192 + .bits 0x40004000,32 + ; sdspiTivaHWattrs[0].portCS @ 224 + .bits 0x20,32 + ; sdspiTivaHWattrs[0].pinCS @ 256 + +$C$DW$17 .dwtag DW_TAG_variable + .dwattr $C$DW$17, DW_AT_name("sdspiTivaHWattrs") + .dwattr $C$DW$17, DW_AT_TI_symbol_name("sdspiTivaHWattrs") + .dwattr $C$DW$17, DW_AT_location[DW_OP_addr sdspiTivaHWattrs] + .dwattr $C$DW$17, DW_AT_type(*$C$DW$T$1025) + .dwattr $C$DW$17, DW_AT_external + .dwattr $C$DW$17, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$17, DW_AT_decl_line(0x168) + .dwattr $C$DW$17, DW_AT_decl_column(0x19) + + .global SDSPI_config + .sect ".const:SDSPI_config" + .align 4 + .elfsym SDSPI_config,SYM_SIZE(24) +SDSPI_config: + .bits SDSPITiva_fxnTable,32 ; SDSPI_config[0].fxnTablePtr @ 0 + .bits sdspiTivaObjects,32 ; SDSPI_config[0].object @ 32 + .bits sdspiTivaHWattrs,32 ; SDSPI_config[0].hwAttrs @ 64 + .bits 0,32 + ; SDSPI_config[1].fxnTablePtr @ 96 + .bits 0,32 + ; SDSPI_config[1].object @ 128 + .bits 0,32 + ; SDSPI_config[1].hwAttrs @ 160 + +$C$DW$18 .dwtag DW_TAG_variable + .dwattr $C$DW$18, DW_AT_name("SDSPI_config") + .dwattr $C$DW$18, DW_AT_TI_symbol_name("SDSPI_config") + .dwattr $C$DW$18, DW_AT_location[DW_OP_addr SDSPI_config] + .dwattr $C$DW$18, DW_AT_type(*$C$DW$T$1034) + .dwattr $C$DW$18, DW_AT_external + .dwattr $C$DW$18, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$18, DW_AT_decl_line(0x177) + .dwattr $C$DW$18, DW_AT_decl_column(0x14) + +$C$DW$19 .dwtag DW_TAG_variable + .dwattr $C$DW$19, DW_AT_name("SPITivaDMA_fxnTable") + .dwattr $C$DW$19, DW_AT_TI_symbol_name("SPITivaDMA_fxnTable") + .dwattr $C$DW$19, DW_AT_type(*$C$DW$T$332) + .dwattr $C$DW$19, DW_AT_declaration + .dwattr $C$DW$19, DW_AT_external + .dwattr $C$DW$19, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$19, DW_AT_decl_line(0xab) + .dwattr $C$DW$19, DW_AT_decl_column(0x1b) + + .global spiTivaDMAObjects + .common spiTivaDMAObjects,228,4 +$C$DW$20 .dwtag DW_TAG_variable + .dwattr $C$DW$20, DW_AT_name("spiTivaDMAObjects") + .dwattr $C$DW$20, DW_AT_TI_symbol_name("spiTivaDMAObjects") + .dwattr $C$DW$20, DW_AT_location[DW_OP_addr spiTivaDMAObjects] + .dwattr $C$DW$20, DW_AT_type(*$C$DW$T$1040) + .dwattr $C$DW$20, DW_AT_external + .dwattr $C$DW$20, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$20, DW_AT_decl_line(0x1af) + .dwattr $C$DW$20, DW_AT_decl_column(0x13) + + .global spiTivaDMAscratchBuf + .common spiTivaDMAscratchBuf,12,32 +$C$DW$21 .dwtag DW_TAG_variable + .dwattr $C$DW$21, DW_AT_name("spiTivaDMAscratchBuf") + .dwattr $C$DW$21, DW_AT_TI_symbol_name("spiTivaDMAscratchBuf") + .dwattr $C$DW$21, DW_AT_location[DW_OP_addr spiTivaDMAscratchBuf] + .dwattr $C$DW$21, DW_AT_type(*$C$DW$T$1758) + .dwattr $C$DW$21, DW_AT_external + .dwattr $C$DW$21, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$21, DW_AT_decl_line(0x1b8) + .dwattr $C$DW$21, DW_AT_decl_column(0x0a) + + .global spiTivaDMAHWAttrs + .sect ".const:spiTivaDMAHWAttrs" + .align 4 + .elfsym spiTivaDMAHWAttrs,SYM_SIZE(120) +spiTivaDMAHWAttrs: + .bits 0x40008000,32 + ; spiTivaDMAHWAttrs[0].baseAddr @ 0 + .bits 0x17,32 + ; spiTivaDMAHWAttrs[0].intNum @ 32 + .bits 0xffffffff,32 + ; spiTivaDMAHWAttrs[0].intPriority @ 64 + .bits spiTivaDMAscratchBuf,32 ; spiTivaDMAHWAttrs[0].scratchBufPtr @ 96 + .bits 0,32 + ; spiTivaDMAHWAttrs[0].defaultTxBufValue @ 128 + .bits 0xa,32 + ; spiTivaDMAHWAttrs[0].rxChannelIndex @ 160 + .bits 0xb,32 + ; spiTivaDMAHWAttrs[0].txChannelIndex @ 192 + .bits uDMAChannelAssign,32 ; spiTivaDMAHWAttrs[0].channelMappingFxn @ 224 + .bits 0xa,32 + ; spiTivaDMAHWAttrs[0].rxChannelMappingFxnArg @ 256 + .bits 0xb,32 + ; spiTivaDMAHWAttrs[0].txChannelMappingFxnArg @ 288 + .bits 0x4000a000,32 + ; spiTivaDMAHWAttrs[1].baseAddr @ 320 + .bits 0x49,32 + ; spiTivaDMAHWAttrs[1].intNum @ 352 + .bits 0xffffffff,32 + ; spiTivaDMAHWAttrs[1].intPriority @ 384 + .bits spiTivaDMAscratchBuf + 4,32 ; spiTivaDMAHWAttrs[1].scratchBufPtr @ 416 + .bits 0,32 + ; spiTivaDMAHWAttrs[1].defaultTxBufValue @ 448 + .bits 0xc,32 + ; spiTivaDMAHWAttrs[1].rxChannelIndex @ 480 + .bits 0xd,32 + ; spiTivaDMAHWAttrs[1].txChannelIndex @ 512 + .bits uDMAChannelAssign,32 ; spiTivaDMAHWAttrs[1].channelMappingFxn @ 544 + .bits 0x2000c,32 + ; spiTivaDMAHWAttrs[1].rxChannelMappingFxnArg @ 576 + .bits 0x2000d,32 + ; spiTivaDMAHWAttrs[1].txChannelMappingFxnArg @ 608 + .bits 0x4000b000,32 + ; spiTivaDMAHWAttrs[2].baseAddr @ 640 + .bits 0x4a,32 + ; spiTivaDMAHWAttrs[2].intNum @ 672 + .bits 0xffffffff,32 + ; spiTivaDMAHWAttrs[2].intPriority @ 704 + .bits spiTivaDMAscratchBuf + 8,32 ; spiTivaDMAHWAttrs[2].scratchBufPtr @ 736 + .bits 0,32 + ; spiTivaDMAHWAttrs[2].defaultTxBufValue @ 768 + .bits 0xe,32 + ; spiTivaDMAHWAttrs[2].rxChannelIndex @ 800 + .bits 0xf,32 + ; spiTivaDMAHWAttrs[2].txChannelIndex @ 832 + .bits uDMAChannelAssign,32 ; spiTivaDMAHWAttrs[2].channelMappingFxn @ 864 + .bits 0x2000e,32 + ; spiTivaDMAHWAttrs[2].rxChannelMappingFxnArg @ 896 + .bits 0x2000f,32 + ; spiTivaDMAHWAttrs[2].txChannelMappingFxnArg @ 928 + +$C$DW$22 .dwtag DW_TAG_variable + .dwattr $C$DW$22, DW_AT_name("spiTivaDMAHWAttrs") + .dwattr $C$DW$22, DW_AT_TI_symbol_name("spiTivaDMAHWAttrs") + .dwattr $C$DW$22, DW_AT_location[DW_OP_addr spiTivaDMAHWAttrs] + .dwattr $C$DW$22, DW_AT_type(*$C$DW$T$1037) + .dwattr $C$DW$22, DW_AT_external + .dwattr $C$DW$22, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$22, DW_AT_decl_line(0x1ba) + .dwattr $C$DW$22, DW_AT_decl_column(0x1a) + + .global SPI_config + .sect ".const:SPI_config" + .align 4 + .elfsym SPI_config,SYM_SIZE(48) +SPI_config: + .bits SPITivaDMA_fxnTable,32 ; SPI_config[0].fxnTablePtr @ 0 + .bits spiTivaDMAObjects,32 ; SPI_config[0].object @ 32 + .bits spiTivaDMAHWAttrs,32 ; SPI_config[0].hwAttrs @ 64 + .bits SPITivaDMA_fxnTable,32 ; SPI_config[1].fxnTablePtr @ 96 + .bits spiTivaDMAObjects + 76,32 ; SPI_config[1].object @ 128 + .bits spiTivaDMAHWAttrs + 40,32 ; SPI_config[1].hwAttrs @ 160 + .bits SPITivaDMA_fxnTable,32 ; SPI_config[2].fxnTablePtr @ 192 + .bits spiTivaDMAObjects + 152,32 ; SPI_config[2].object @ 224 + .bits spiTivaDMAHWAttrs + 80,32 ; SPI_config[2].hwAttrs @ 256 + .bits 0,32 + ; SPI_config[3].fxnTablePtr @ 288 + .bits 0,32 + ; SPI_config[3].object @ 320 + .bits 0,32 + ; SPI_config[3].hwAttrs @ 352 + +$C$DW$23 .dwtag DW_TAG_variable + .dwattr $C$DW$23, DW_AT_name("SPI_config") + .dwattr $C$DW$23, DW_AT_TI_symbol_name("SPI_config") + .dwattr $C$DW$23, DW_AT_location[DW_OP_addr SPI_config] + .dwattr $C$DW$23, DW_AT_type(*$C$DW$T$1046) + .dwattr $C$DW$23, DW_AT_external + .dwattr $C$DW$23, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$23, DW_AT_decl_line(0x1e1) + .dwattr $C$DW$23, DW_AT_decl_column(0x12) + +$C$DW$24 .dwtag DW_TAG_variable + .dwattr $C$DW$24, DW_AT_name("UARTTiva_fxnTable") + .dwattr $C$DW$24, DW_AT_TI_symbol_name("UARTTiva_fxnTable") + .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$385) + .dwattr $C$DW$24, DW_AT_declaration + .dwattr $C$DW$24, DW_AT_external + .dwattr $C$DW$24, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$24, DW_AT_decl_line(0x5d) + .dwattr $C$DW$24, DW_AT_decl_column(0x1c) + + .global uartTivaObjects + .common uartTivaObjects,204,4 +$C$DW$25 .dwtag DW_TAG_variable + .dwattr $C$DW$25, DW_AT_name("uartTivaObjects") + .dwattr $C$DW$25, DW_AT_TI_symbol_name("uartTivaObjects") + .dwattr $C$DW$25, DW_AT_location[DW_OP_addr uartTivaObjects] + .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$1052) + .dwattr $C$DW$25, DW_AT_external + .dwattr $C$DW$25, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$25, DW_AT_decl_line(0x249) + .dwattr $C$DW$25, DW_AT_decl_column(0x11) + + .global uartTivaRingBuffer + .common uartTivaRingBuffer,32,1 +$C$DW$26 .dwtag DW_TAG_variable + .dwattr $C$DW$26, DW_AT_name("uartTivaRingBuffer") + .dwattr $C$DW$26, DW_AT_TI_symbol_name("uartTivaRingBuffer") + .dwattr $C$DW$26, DW_AT_location[DW_OP_addr uartTivaRingBuffer] + .dwattr $C$DW$26, DW_AT_type(*$C$DW$T$1452) + .dwattr $C$DW$26, DW_AT_external + .dwattr $C$DW$26, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$26, DW_AT_decl_line(0x24a) + .dwattr $C$DW$26, DW_AT_decl_column(0x0f) + + .global uartTivaHWAttrs + .sect ".const:uartTivaHWAttrs" + .align 4 + .elfsym uartTivaHWAttrs,SYM_SIZE(24) +uartTivaHWAttrs: + .bits 0x4000c000,32 + ; uartTivaHWAttrs[0].baseAddr @ 0 + .bits 0x15,32 + ; uartTivaHWAttrs[0].intNum @ 32 + .bits 0xffffffff,32 + ; uartTivaHWAttrs[0].intPriority @ 64 + .bits 0,32 + ; uartTivaHWAttrs[0].flowControl @ 96 + .bits uartTivaRingBuffer,32 ; uartTivaHWAttrs[0].ringBufPtr @ 128 + .bits 0x20,32 + ; uartTivaHWAttrs[0].ringBufSize @ 160 + +$C$DW$27 .dwtag DW_TAG_variable + .dwattr $C$DW$27, DW_AT_name("uartTivaHWAttrs") + .dwattr $C$DW$27, DW_AT_TI_symbol_name("uartTivaHWAttrs") + .dwattr $C$DW$27, DW_AT_location[DW_OP_addr uartTivaHWAttrs] + .dwattr $C$DW$27, DW_AT_type(*$C$DW$T$1049) + .dwattr $C$DW$27, DW_AT_external + .dwattr $C$DW$27, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$27, DW_AT_decl_line(0x24d) + .dwattr $C$DW$27, DW_AT_decl_column(0x18) + + .global UART_config + .sect ".const:UART_config" + .align 4 + .elfsym UART_config,SYM_SIZE(24) +UART_config: + .bits UARTTiva_fxnTable,32 ; UART_config[0].fxnTablePtr @ 0 + .bits uartTivaObjects,32 ; UART_config[0].object @ 32 + .bits uartTivaHWAttrs,32 ; UART_config[0].hwAttrs @ 64 + .bits 0,32 + ; UART_config[1].fxnTablePtr @ 96 + .bits 0,32 + ; UART_config[1].object @ 128 + .bits 0,32 + ; UART_config[1].hwAttrs @ 160 + +$C$DW$28 .dwtag DW_TAG_variable + .dwattr $C$DW$28, DW_AT_name("UART_config") + .dwattr $C$DW$28, DW_AT_TI_symbol_name("UART_config") + .dwattr $C$DW$28, DW_AT_location[DW_OP_addr UART_config] + .dwattr $C$DW$28, DW_AT_type(*$C$DW$T$1058) + .dwattr $C$DW$28, DW_AT_external + .dwattr $C$DW$28, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$28, DW_AT_decl_line(0x258) + .dwattr $C$DW$28, DW_AT_decl_column(0x13) + +$C$DW$29 .dwtag DW_TAG_variable + .dwattr $C$DW$29, DW_AT_name("WatchdogTiva_fxnTable") + .dwattr $C$DW$29, DW_AT_TI_symbol_name("WatchdogTiva_fxnTable") + .dwattr $C$DW$29, DW_AT_type(*$C$DW$T$415) + .dwattr $C$DW$29, DW_AT_declaration + .dwattr $C$DW$29, DW_AT_external + .dwattr $C$DW$29, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$29, DW_AT_decl_line(0x82) + .dwattr $C$DW$29, DW_AT_decl_column(0x20) + + .global watchdogTivaObjects + .common watchdogTivaObjects,32,4 +$C$DW$30 .dwtag DW_TAG_variable + .dwattr $C$DW$30, DW_AT_name("watchdogTivaObjects") + .dwattr $C$DW$30, DW_AT_TI_symbol_name("watchdogTivaObjects") + .dwattr $C$DW$30, DW_AT_location[DW_OP_addr watchdogTivaObjects] + .dwattr $C$DW$30, DW_AT_type(*$C$DW$T$1064) + .dwattr $C$DW$30, DW_AT_external + .dwattr $C$DW$30, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$30, DW_AT_decl_line(0x295) + .dwattr $C$DW$30, DW_AT_decl_column(0x15) + + .global watchdogTivaHWAttrs + .sect ".const:watchdogTivaHWAttrs" + .align 4 + .elfsym watchdogTivaHWAttrs,SYM_SIZE(16) +watchdogTivaHWAttrs: + .bits 0x40000000,32 + ; watchdogTivaHWAttrs[0].baseAddr @ 0 + .bits 0x22,32 + ; watchdogTivaHWAttrs[0].intNum @ 32 + .bits 0xffffffff,32 + ; watchdogTivaHWAttrs[0].intPriority @ 64 + .bits 0x4c4b400,32 + ; watchdogTivaHWAttrs[0].reloadValue @ 96 + +$C$DW$31 .dwtag DW_TAG_variable + .dwattr $C$DW$31, DW_AT_name("watchdogTivaHWAttrs") + .dwattr $C$DW$31, DW_AT_TI_symbol_name("watchdogTivaHWAttrs") + .dwattr $C$DW$31, DW_AT_location[DW_OP_addr watchdogTivaHWAttrs] + .dwattr $C$DW$31, DW_AT_type(*$C$DW$T$1061) + .dwattr $C$DW$31, DW_AT_external + .dwattr $C$DW$31, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$31, DW_AT_decl_line(0x297) + .dwattr $C$DW$31, DW_AT_decl_column(0x1c) + + .global Watchdog_config + .sect ".const:Watchdog_config" + .align 4 + .elfsym Watchdog_config,SYM_SIZE(24) +Watchdog_config: + .bits WatchdogTiva_fxnTable,32 ; Watchdog_config[0].fxnTablePtr @ 0 + .bits watchdogTivaObjects,32 ; Watchdog_config[0].object @ 32 + .bits watchdogTivaHWAttrs,32 ; Watchdog_config[0].hwAttrs @ 64 + .bits 0,32 + ; Watchdog_config[1].fxnTablePtr @ 96 + .bits 0,32 + ; Watchdog_config[1].object @ 128 + .bits 0,32 + ; Watchdog_config[1].hwAttrs @ 160 + +$C$DW$32 .dwtag DW_TAG_variable + .dwattr $C$DW$32, DW_AT_name("Watchdog_config") + .dwattr $C$DW$32, DW_AT_TI_symbol_name("Watchdog_config") + .dwattr $C$DW$32, DW_AT_location[DW_OP_addr Watchdog_config] + .dwattr $C$DW$32, DW_AT_type(*$C$DW$T$1068) + .dwattr $C$DW$32, DW_AT_external + .dwattr $C$DW$32, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$32, DW_AT_decl_line(0x2a0) + .dwattr $C$DW$32, DW_AT_decl_column(0x17) + +$C$DW$33 .dwtag DW_TAG_variable + .dwattr $C$DW$33, DW_AT_name("WiFiCC3100_fxnTable") + .dwattr $C$DW$33, DW_AT_TI_symbol_name("WiFiCC3100_fxnTable") + .dwattr $C$DW$33, DW_AT_type(*$C$DW$T$450) + .dwattr $C$DW$33, DW_AT_declaration + .dwattr $C$DW$33, DW_AT_external + .dwattr $C$DW$33, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$33, DW_AT_decl_line(0xa9) + .dwattr $C$DW$33, DW_AT_decl_column(0x1c) + + .global wiFiCC3100Objects + .common wiFiCC3100Objects,48,4 +$C$DW$34 .dwtag DW_TAG_variable + .dwattr $C$DW$34, DW_AT_name("wiFiCC3100Objects") + .dwattr $C$DW$34, DW_AT_TI_symbol_name("wiFiCC3100Objects") + .dwattr $C$DW$34, DW_AT_location[DW_OP_addr wiFiCC3100Objects] + .dwattr $C$DW$34, DW_AT_type(*$C$DW$T$1074) + .dwattr $C$DW$34, DW_AT_external + .dwattr $C$DW$34, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$34, DW_AT_decl_line(0x2cb) + .dwattr $C$DW$34, DW_AT_decl_column(0x13) + + .global wiFiCC3100HWAttrs + .sect ".const:wiFiCC3100HWAttrs" + .align 4 + .elfsym wiFiCC3100HWAttrs,SYM_SIZE(28) +wiFiCC3100HWAttrs: + .bits 0x40005000,32 + ; wiFiCC3100HWAttrs[0].irqPort @ 0 + .bits 0x4,32 + ; wiFiCC3100HWAttrs[0].irqPin @ 32 + .bits 0x11,32 + ; wiFiCC3100HWAttrs[0].irqIntNum @ 64 + .bits 0x40024000,32 + ; wiFiCC3100HWAttrs[0].csPort @ 96 + .bits 0x1,32 + ; wiFiCC3100HWAttrs[0].csPin @ 128 + .bits 0x40024000,32 + ; wiFiCC3100HWAttrs[0].enPort @ 160 + .bits 0x10,32 + ; wiFiCC3100HWAttrs[0].enPin @ 192 + +$C$DW$35 .dwtag DW_TAG_variable + .dwattr $C$DW$35, DW_AT_name("wiFiCC3100HWAttrs") + .dwattr $C$DW$35, DW_AT_TI_symbol_name("wiFiCC3100HWAttrs") + .dwattr $C$DW$35, DW_AT_location[DW_OP_addr wiFiCC3100HWAttrs] + .dwattr $C$DW$35, DW_AT_type(*$C$DW$T$1071) + .dwattr $C$DW$35, DW_AT_external + .dwattr $C$DW$35, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$35, DW_AT_decl_line(0x2cd) + .dwattr $C$DW$35, DW_AT_decl_column(0x1a) + + .global WiFi_config + .sect ".const:WiFi_config" + .align 4 + .elfsym WiFi_config,SYM_SIZE(24) +WiFi_config: + .bits WiFiCC3100_fxnTable,32 ; WiFi_config[0].fxnTablePtr @ 0 + .bits wiFiCC3100Objects,32 ; WiFi_config[0].object @ 32 + .bits wiFiCC3100HWAttrs,32 ; WiFi_config[0].hwAttrs @ 64 + .bits 0,32 + ; WiFi_config[1].fxnTablePtr @ 96 + .bits 0,32 + ; WiFi_config[1].object @ 128 + .bits 0,32 + ; WiFi_config[1].hwAttrs @ 160 + +$C$DW$36 .dwtag DW_TAG_variable + .dwattr $C$DW$36, DW_AT_name("WiFi_config") + .dwattr $C$DW$36, DW_AT_TI_symbol_name("WiFi_config") + .dwattr $C$DW$36, DW_AT_location[DW_OP_addr WiFi_config] + .dwattr $C$DW$36, DW_AT_type(*$C$DW$T$1078) + .dwattr $C$DW$36, DW_AT_external + .dwattr $C$DW$36, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$36, DW_AT_decl_line(0x2db) + .dwattr $C$DW$36, DW_AT_decl_column(0x13) + + +$C$DW$37 .dwtag DW_TAG_subprogram + .dwattr $C$DW$37, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Params__init__S") + .dwattr $C$DW$37, DW_AT_TI_symbol_name("ti_sysbios_family_arm_m3_Hwi_Params__init__S") + .dwattr $C$DW$37, DW_AT_declaration + .dwattr $C$DW$37, DW_AT_external + .dwattr $C$DW$37, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$37, DW_AT_decl_line(0x2ff) + .dwattr $C$DW$37, DW_AT_decl_column(0x13) +$C$DW$38 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$38, DW_AT_type(*$C$DW$T$510) + +$C$DW$39 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$39, DW_AT_type(*$C$DW$T$223) + +$C$DW$40 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$40, DW_AT_type(*$C$DW$T$511) + +$C$DW$41 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$41, DW_AT_type(*$C$DW$T$511) + + .dwendtag $C$DW$37 + + +$C$DW$42 .dwtag DW_TAG_subprogram + .dwattr $C$DW$42, DW_AT_name("xdc_runtime_System_printf__E") + .dwattr $C$DW$42, DW_AT_TI_symbol_name("xdc_runtime_System_printf__E") + .dwattr $C$DW$42, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$42, DW_AT_declaration + .dwattr $C$DW$42, DW_AT_external + .dwattr $C$DW$42, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$42, DW_AT_decl_line(0x11a) + .dwattr $C$DW$42, DW_AT_decl_column(0x12) +$C$DW$43 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$43, DW_AT_type(*$C$DW$T$870) + +$C$DW$44 .dwtag DW_TAG_unspecified_parameters + + .dwendtag $C$DW$42 + + +$C$DW$45 .dwtag DW_TAG_subprogram + .dwattr $C$DW$45, DW_AT_name("uDMAErrorStatusGet") + .dwattr $C$DW$45, DW_AT_TI_symbol_name("uDMAErrorStatusGet") + .dwattr $C$DW$45, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$45, DW_AT_declaration + .dwattr $C$DW$45, DW_AT_external + .dwattr $C$DW$45, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$45, DW_AT_decl_line(0x30c) + .dwattr $C$DW$45, DW_AT_decl_column(0x11) + .dwendtag $C$DW$45 + + +$C$DW$46 .dwtag DW_TAG_subprogram + .dwattr $C$DW$46, DW_AT_name("uDMAErrorStatusClear") + .dwattr $C$DW$46, DW_AT_TI_symbol_name("uDMAErrorStatusClear") + .dwattr $C$DW$46, DW_AT_declaration + .dwattr $C$DW$46, DW_AT_external + .dwattr $C$DW$46, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$46, DW_AT_decl_line(0x30d) + .dwattr $C$DW$46, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$46 + + +$C$DW$47 .dwtag DW_TAG_subprogram + .dwattr $C$DW$47, DW_AT_name("xdc_runtime_System_abort__E") + .dwattr $C$DW$47, DW_AT_TI_symbol_name("xdc_runtime_System_abort__E") + .dwattr $C$DW$47, DW_AT_declaration + .dwattr $C$DW$47, DW_AT_external + .dwattr $C$DW$47, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$47, DW_AT_decl_line(0xe8) + .dwattr $C$DW$47, DW_AT_decl_column(0x13) +$C$DW$48 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$48, DW_AT_type(*$C$DW$T$870) + + .dwendtag $C$DW$47 + + +$C$DW$49 .dwtag DW_TAG_subprogram + .dwattr $C$DW$49, DW_AT_name("xdc_runtime_Error_init__E") + .dwattr $C$DW$49, DW_AT_TI_symbol_name("xdc_runtime_Error_init__E") + .dwattr $C$DW$49, DW_AT_declaration + .dwattr $C$DW$49, DW_AT_external + .dwattr $C$DW$49, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$49, DW_AT_decl_line(0x10f) + .dwattr $C$DW$49, DW_AT_decl_column(0x13) +$C$DW$50 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$50, DW_AT_type(*$C$DW$T$639) + + .dwendtag $C$DW$49 + + +$C$DW$51 .dwtag DW_TAG_subprogram + .dwattr $C$DW$51, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_construct") + .dwattr $C$DW$51, DW_AT_TI_symbol_name("ti_sysbios_family_arm_m3_Hwi_construct") + .dwattr $C$DW$51, DW_AT_declaration + .dwattr $C$DW$51, DW_AT_external + .dwattr $C$DW$51, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$51, DW_AT_decl_line(0x2df) + .dwattr $C$DW$51, DW_AT_decl_column(0x0f) +$C$DW$52 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$52, DW_AT_type(*$C$DW$T$1218) + +$C$DW$53 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$53, DW_AT_type(*$C$DW$T$480) + +$C$DW$54 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$54, DW_AT_type(*$C$DW$T$504) + +$C$DW$55 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$55, DW_AT_type(*$C$DW$T$1221) + +$C$DW$56 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$56, DW_AT_type(*$C$DW$T$639) + + .dwendtag $C$DW$51 + + +$C$DW$57 .dwtag DW_TAG_subprogram + .dwattr $C$DW$57, DW_AT_name("xdc_runtime_Error_check__E") + .dwattr $C$DW$57, DW_AT_TI_symbol_name("xdc_runtime_Error_check__E") + .dwattr $C$DW$57, DW_AT_type(*$C$DW$T$479) + .dwattr $C$DW$57, DW_AT_declaration + .dwattr $C$DW$57, DW_AT_external + .dwattr $C$DW$57, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$57, DW_AT_decl_line(0xf1) + .dwattr $C$DW$57, DW_AT_decl_column(0x13) +$C$DW$58 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$58, DW_AT_type(*$C$DW$T$639) + + .dwendtag $C$DW$57 + + +$C$DW$59 .dwtag DW_TAG_subprogram + .dwattr $C$DW$59, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$59, DW_AT_TI_symbol_name("SysCtlPeripheralEnable") + .dwattr $C$DW$59, DW_AT_declaration + .dwattr $C$DW$59, DW_AT_external + .dwattr $C$DW$59, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/sysctl.h") + .dwattr $C$DW$59, DW_AT_decl_line(0x24e) + .dwattr $C$DW$59, DW_AT_decl_column(0x0d) +$C$DW$60 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$60, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$59 + + +$C$DW$61 .dwtag DW_TAG_subprogram + .dwattr $C$DW$61, DW_AT_name("uDMAEnable") + .dwattr $C$DW$61, DW_AT_TI_symbol_name("uDMAEnable") + .dwattr $C$DW$61, DW_AT_declaration + .dwattr $C$DW$61, DW_AT_external + .dwattr $C$DW$61, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$61, DW_AT_decl_line(0x30a) + .dwattr $C$DW$61, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$61 + + +$C$DW$62 .dwtag DW_TAG_subprogram + .dwattr $C$DW$62, DW_AT_name("uDMAControlBaseSet") + .dwattr $C$DW$62, DW_AT_TI_symbol_name("uDMAControlBaseSet") + .dwattr $C$DW$62, DW_AT_declaration + .dwattr $C$DW$62, DW_AT_external + .dwattr $C$DW$62, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$62, DW_AT_decl_line(0x311) + .dwattr $C$DW$62, DW_AT_decl_column(0x0d) +$C$DW$63 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$63, DW_AT_type(*$C$DW$T$3) + + .dwendtag $C$DW$62 + + +$C$DW$64 .dwtag DW_TAG_subprogram + .dwattr $C$DW$64, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$64, DW_AT_TI_symbol_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$64, DW_AT_declaration + .dwattr $C$DW$64, DW_AT_external + .dwattr $C$DW$64, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$64, DW_AT_decl_line(0xa7) + .dwattr $C$DW$64, DW_AT_decl_column(0x0d) +$C$DW$65 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$65, DW_AT_type(*$C$DW$T$133) + +$C$DW$66 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$66, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$64 + + +$C$DW$67 .dwtag DW_TAG_subprogram + .dwattr $C$DW$67, DW_AT_name("GPIO_init") + .dwattr $C$DW$67, DW_AT_TI_symbol_name("GPIO_init") + .dwattr $C$DW$67, DW_AT_declaration + .dwattr $C$DW$67, DW_AT_external + .dwattr $C$DW$67, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/GPIO.h") + .dwattr $C$DW$67, DW_AT_decl_line(0xd3) + .dwattr $C$DW$67, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$67 + + +$C$DW$68 .dwtag DW_TAG_subprogram + .dwattr $C$DW$68, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$68, DW_AT_TI_symbol_name("GPIOPinConfigure") + .dwattr $C$DW$68, DW_AT_declaration + .dwattr $C$DW$68, DW_AT_external + .dwattr $C$DW$68, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$68, DW_AT_decl_line(0x9f) + .dwattr $C$DW$68, DW_AT_decl_column(0x0d) +$C$DW$69 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$69, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$68 + + +$C$DW$70 .dwtag DW_TAG_subprogram + .dwattr $C$DW$70, DW_AT_name("GPIOPinTypeI2CSCL") + .dwattr $C$DW$70, DW_AT_TI_symbol_name("GPIOPinTypeI2CSCL") + .dwattr $C$DW$70, DW_AT_declaration + .dwattr $C$DW$70, DW_AT_external + .dwattr $C$DW$70, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$70, DW_AT_decl_line(0xab) + .dwattr $C$DW$70, DW_AT_decl_column(0x0d) +$C$DW$71 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$71, DW_AT_type(*$C$DW$T$133) + +$C$DW$72 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$72, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$70 + + +$C$DW$73 .dwtag DW_TAG_subprogram + .dwattr $C$DW$73, DW_AT_name("GPIOPinTypeI2C") + .dwattr $C$DW$73, DW_AT_TI_symbol_name("GPIOPinTypeI2C") + .dwattr $C$DW$73, DW_AT_declaration + .dwattr $C$DW$73, DW_AT_external + .dwattr $C$DW$73, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$73, DW_AT_decl_line(0xaa) + .dwattr $C$DW$73, DW_AT_decl_column(0x0d) +$C$DW$74 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$74, DW_AT_type(*$C$DW$T$133) + +$C$DW$75 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$75, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$73 + + +$C$DW$76 .dwtag DW_TAG_subprogram + .dwattr $C$DW$76, DW_AT_name("I2C_init") + .dwattr $C$DW$76, DW_AT_TI_symbol_name("I2C_init") + .dwattr $C$DW$76, DW_AT_declaration + .dwattr $C$DW$76, DW_AT_external + .dwattr $C$DW$76, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$76, DW_AT_decl_line(0x1be) + .dwattr $C$DW$76, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$76 + + +$C$DW$77 .dwtag DW_TAG_subprogram + .dwattr $C$DW$77, DW_AT_name("GPIOPinTypePWM") + .dwattr $C$DW$77, DW_AT_TI_symbol_name("GPIOPinTypePWM") + .dwattr $C$DW$77, DW_AT_declaration + .dwattr $C$DW$77, DW_AT_external + .dwattr $C$DW$77, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$77, DW_AT_decl_line(0xad) + .dwattr $C$DW$77, DW_AT_decl_column(0x0d) +$C$DW$78 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$78, DW_AT_type(*$C$DW$T$133) + +$C$DW$79 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$79, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$77 + + +$C$DW$80 .dwtag DW_TAG_subprogram + .dwattr $C$DW$80, DW_AT_name("PWM_init") + .dwattr $C$DW$80, DW_AT_TI_symbol_name("PWM_init") + .dwattr $C$DW$80, DW_AT_declaration + .dwattr $C$DW$80, DW_AT_external + .dwattr $C$DW$80, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$80, DW_AT_decl_line(0x1da) + .dwattr $C$DW$80, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$80 + + +$C$DW$81 .dwtag DW_TAG_subprogram + .dwattr $C$DW$81, DW_AT_name("GPIOPadConfigSet") + .dwattr $C$DW$81, DW_AT_TI_symbol_name("GPIOPadConfigSet") + .dwattr $C$DW$81, DW_AT_declaration + .dwattr $C$DW$81, DW_AT_external + .dwattr $C$DW$81, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$81, DW_AT_decl_line(0x93) + .dwattr $C$DW$81, DW_AT_decl_column(0x0d) +$C$DW$82 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$82, DW_AT_type(*$C$DW$T$133) + +$C$DW$83 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$83, DW_AT_type(*$C$DW$T$215) + +$C$DW$84 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$84, DW_AT_type(*$C$DW$T$133) + +$C$DW$85 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$85, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$81 + + +$C$DW$86 .dwtag DW_TAG_subprogram + .dwattr $C$DW$86, DW_AT_name("SDSPI_init") + .dwattr $C$DW$86, DW_AT_TI_symbol_name("SDSPI_init") + .dwattr $C$DW$86, DW_AT_declaration + .dwattr $C$DW$86, DW_AT_external + .dwattr $C$DW$86, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$86, DW_AT_decl_line(0x151) + .dwattr $C$DW$86, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$86 + + +$C$DW$87 .dwtag DW_TAG_subprogram + .dwattr $C$DW$87, DW_AT_name("GPIOPinTypeSSI") + .dwattr $C$DW$87, DW_AT_TI_symbol_name("GPIOPinTypeSSI") + .dwattr $C$DW$87, DW_AT_declaration + .dwattr $C$DW$87, DW_AT_external + .dwattr $C$DW$87, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$87, DW_AT_decl_line(0xaf) + .dwattr $C$DW$87, DW_AT_decl_column(0x0d) +$C$DW$88 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$88, DW_AT_type(*$C$DW$T$133) + +$C$DW$89 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$89, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$87 + + +$C$DW$90 .dwtag DW_TAG_subprogram + .dwattr $C$DW$90, DW_AT_name("SPI_init") + .dwattr $C$DW$90, DW_AT_TI_symbol_name("SPI_init") + .dwattr $C$DW$90, DW_AT_declaration + .dwattr $C$DW$90, DW_AT_external + .dwattr $C$DW$90, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$90, DW_AT_decl_line(0x1f9) + .dwattr $C$DW$90, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$90 + + +$C$DW$91 .dwtag DW_TAG_subprogram + .dwattr $C$DW$91, DW_AT_name("GPIOPinTypeUART") + .dwattr $C$DW$91, DW_AT_TI_symbol_name("GPIOPinTypeUART") + .dwattr $C$DW$91, DW_AT_declaration + .dwattr $C$DW$91, DW_AT_external + .dwattr $C$DW$91, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$91, DW_AT_decl_line(0xb1) + .dwattr $C$DW$91, DW_AT_decl_column(0x0d) +$C$DW$92 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$92, DW_AT_type(*$C$DW$T$133) + +$C$DW$93 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$93, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$91 + + +$C$DW$94 .dwtag DW_TAG_subprogram + .dwattr $C$DW$94, DW_AT_name("UART_init") + .dwattr $C$DW$94, DW_AT_TI_symbol_name("UART_init") + .dwattr $C$DW$94, DW_AT_declaration + .dwattr $C$DW$94, DW_AT_external + .dwattr $C$DW$94, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$94, DW_AT_decl_line(0x271) + .dwattr $C$DW$94, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$94 + + +$C$DW$95 .dwtag DW_TAG_subprogram + .dwattr $C$DW$95, DW_AT_name("SysCtlUSBPLLEnable") + .dwattr $C$DW$95, DW_AT_TI_symbol_name("SysCtlUSBPLLEnable") + .dwattr $C$DW$95, DW_AT_declaration + .dwattr $C$DW$95, DW_AT_external + .dwattr $C$DW$95, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/sysctl.h") + .dwattr $C$DW$95, DW_AT_decl_line(0x278) + .dwattr $C$DW$95, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$95 + + +$C$DW$96 .dwtag DW_TAG_subprogram + .dwattr $C$DW$96, DW_AT_name("GPIOPinTypeUSBAnalog") + .dwattr $C$DW$96, DW_AT_TI_symbol_name("GPIOPinTypeUSBAnalog") + .dwattr $C$DW$96, DW_AT_declaration + .dwattr $C$DW$96, DW_AT_external + .dwattr $C$DW$96, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$96, DW_AT_decl_line(0xb2) + .dwattr $C$DW$96, DW_AT_decl_column(0x0d) +$C$DW$97 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$97, DW_AT_type(*$C$DW$T$133) + +$C$DW$98 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$98, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$96 + + +$C$DW$99 .dwtag DW_TAG_subprogram + .dwattr $C$DW$99, DW_AT_name("Watchdog_init") + .dwattr $C$DW$99, DW_AT_TI_symbol_name("Watchdog_init") + .dwattr $C$DW$99, DW_AT_declaration + .dwattr $C$DW$99, DW_AT_external + .dwattr $C$DW$99, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$99, DW_AT_decl_line(0x192) + .dwattr $C$DW$99, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$99 + + +$C$DW$100 .dwtag DW_TAG_subprogram + .dwattr $C$DW$100, DW_AT_name("GPIOPinTypeGPIOOutput") + .dwattr $C$DW$100, DW_AT_TI_symbol_name("GPIOPinTypeGPIOOutput") + .dwattr $C$DW$100, DW_AT_declaration + .dwattr $C$DW$100, DW_AT_external + .dwattr $C$DW$100, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$100, DW_AT_decl_line(0xa8) + .dwattr $C$DW$100, DW_AT_decl_column(0x0d) +$C$DW$101 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$101, DW_AT_type(*$C$DW$T$133) + +$C$DW$102 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$102, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$100 + + +$C$DW$103 .dwtag DW_TAG_subprogram + .dwattr $C$DW$103, DW_AT_name("GPIOPinWrite") + .dwattr $C$DW$103, DW_AT_TI_symbol_name("GPIOPinWrite") + .dwattr $C$DW$103, DW_AT_declaration + .dwattr $C$DW$103, DW_AT_external + .dwattr $C$DW$103, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$103, DW_AT_decl_line(0x9e) + .dwattr $C$DW$103, DW_AT_decl_column(0x0d) +$C$DW$104 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$104, DW_AT_type(*$C$DW$T$133) + +$C$DW$105 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$105, DW_AT_type(*$C$DW$T$215) + +$C$DW$106 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$106, DW_AT_type(*$C$DW$T$215) + + .dwendtag $C$DW$103 + + +$C$DW$107 .dwtag DW_TAG_subprogram + .dwattr $C$DW$107, DW_AT_name("GPIOIntTypeSet") + .dwattr $C$DW$107, DW_AT_TI_symbol_name("GPIOIntTypeSet") + .dwattr $C$DW$107, DW_AT_declaration + .dwattr $C$DW$107, DW_AT_external + .dwattr $C$DW$107, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h") + .dwattr $C$DW$107, DW_AT_decl_line(0x90) + .dwattr $C$DW$107, DW_AT_decl_column(0x0d) +$C$DW$108 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$108, DW_AT_type(*$C$DW$T$133) + +$C$DW$109 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$109, DW_AT_type(*$C$DW$T$215) + +$C$DW$110 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$110, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$107 + + +$C$DW$111 .dwtag DW_TAG_subprogram + .dwattr $C$DW$111, DW_AT_name("WiFi_init") + .dwattr $C$DW$111, DW_AT_TI_symbol_name("WiFi_init") + .dwattr $C$DW$111, DW_AT_declaration + .dwattr $C$DW$111, DW_AT_external + .dwattr $C$DW$111, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$111, DW_AT_decl_line(0x165) + .dwattr $C$DW$111, DW_AT_decl_column(0x0d) + .dwendtag $C$DW$111 + + +$C$DW$112 .dwtag DW_TAG_subprogram + .dwattr $C$DW$112, DW_AT_name("uDMAChannelAssign") + .dwattr $C$DW$112, DW_AT_TI_symbol_name("uDMAChannelAssign") + .dwattr $C$DW$112, DW_AT_declaration + .dwattr $C$DW$112, DW_AT_external + .dwattr $C$DW$112, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$112, DW_AT_decl_line(0x329) + .dwattr $C$DW$112, DW_AT_decl_column(0x0d) +$C$DW$113 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$113, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$112 + +; C:\ti\ccs930\ccs\tools\compiler\ti-cgt-arm_18.12.4.LTS\bin\armacpia.exe -@C:\\Users\\zachr\\AppData\\Local\\Temp\\{DC59A6BD-63DD-448D-B3B9-EC3F295786FC} + .sect ".text:ti_sysbios_family_arm_m3_Hwi_Params_init" + .clink + .thumbfunc ti_sysbios_family_arm_m3_Hwi_Params_init + .thumb + +$C$DW$114 .dwtag DW_TAG_subprogram + .dwattr $C$DW$114, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Params_init") + .dwattr $C$DW$114, DW_AT_low_pc(ti_sysbios_family_arm_m3_Hwi_Params_init) + .dwattr $C$DW$114, DW_AT_high_pc(0x00) + .dwattr $C$DW$114, DW_AT_TI_symbol_name("ti_sysbios_family_arm_m3_Hwi_Params_init") + .dwattr $C$DW$114, DW_AT_TI_begin_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$114, DW_AT_TI_begin_line(0x43e) + .dwattr $C$DW$114, DW_AT_TI_begin_column(0x14) + .dwattr $C$DW$114, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$114, DW_AT_decl_line(0x43e) + .dwattr $C$DW$114, DW_AT_decl_column(0x14) + .dwattr $C$DW$114, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h",line 1087,column 1,is_stmt,address ti_sysbios_family_arm_m3_Hwi_Params_init,isa 1 + + .dwfde $C$DW$CIE, ti_sysbios_family_arm_m3_Hwi_Params_init +$C$DW$115 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$115, DW_AT_name("prms") + .dwattr $C$DW$115, DW_AT_TI_symbol_name("prms") + .dwattr $C$DW$115, DW_AT_type(*$C$DW$T$1226) + .dwattr $C$DW$115, DW_AT_location[DW_OP_reg0] + +;---------------------------------------------------------------------- +; 1086 | static inline void ti_sysbios_family_arm_m3_Hwi_Params_init( ti_sysbios +; | _family_arm_m3_Hwi_Params *prms ) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: ti_sysbios_family_arm_m3_Hwi_Params_init * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 4 Auto + 4 Save = 8 byte * +;***************************************************************************** +ti_sysbios_family_arm_m3_Hwi_Params_init: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 +$C$DW$116 .dwtag DW_TAG_variable + .dwattr $C$DW$116, DW_AT_name("prms") + .dwattr $C$DW$116, DW_AT_TI_symbol_name("prms") + .dwattr $C$DW$116, DW_AT_type(*$C$DW$T$1226) + .dwattr $C$DW$116, DW_AT_location[DW_OP_breg13 0] + + STR A1, [SP, #0] ; [DPU_V7M3_PIPE] |1087| + .dwpsn file "C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h",line 1088,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 1088 | if (prms) { +;---------------------------------------------------------------------- + LDR A1, [SP, #0] ; [DPU_V7M3_PIPE] |1088| + CBZ A1, ||$C$L1|| ; [] + ; BRANCHCC OCCURS {||$C$L1||} ; [] |1088| +;* --------------------------------------------------------------------------* + .dwpsn file "C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h",line 1089,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 1089 | ti_sysbios_family_arm_m3_Hwi_Params__init__S(prms, 0, sizeof(ti_sysbios +; | _family_arm_m3_Hwi_Params), sizeof(xdc_runtime_IInstance_Params)); +;---------------------------------------------------------------------- + LDR A1, [SP, #0] ; [DPU_V7M3_PIPE] |1089| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |1089| + MOVS A3, #48 ; [DPU_V7M3_PIPE] |1089| + MOVS A4, #8 ; [DPU_V7M3_PIPE] |1089| +$C$DW$117 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$117, DW_AT_low_pc(0x00) + .dwattr $C$DW$117, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Params__init__S") + .dwattr $C$DW$117, DW_AT_TI_call + + BL ti_sysbios_family_arm_m3_Hwi_Params__init__S ; [DPU_V7M3_PIPE] |1089| + ; CALL OCCURS {ti_sysbios_family_arm_m3_Hwi_Params__init__S } ; [] |1089| + .dwpsn file "C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h",line 1091,column 1,is_stmt,isa 1 +;* --------------------------------------------------------------------------* +||$C$L1||: +$C$DW$118 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$118, DW_AT_low_pc(0x00) + .dwattr $C$DW$118, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$114, DW_AT_TI_end_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$114, DW_AT_TI_end_line(0x443) + .dwattr $C$DW$114, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$114 + + .sect ".text:dmaErrorHwi" + .clink + .thumbfunc dmaErrorHwi + .thumb + +$C$DW$119 .dwtag DW_TAG_subprogram + .dwattr $C$DW$119, DW_AT_name("dmaErrorHwi") + .dwattr $C$DW$119, DW_AT_low_pc(dmaErrorHwi) + .dwattr $C$DW$119, DW_AT_high_pc(0x00) + .dwattr $C$DW$119, DW_AT_TI_symbol_name("dmaErrorHwi") + .dwattr $C$DW$119, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$119, DW_AT_TI_begin_line(0x56) + .dwattr $C$DW$119, DW_AT_TI_begin_column(0x0d) + .dwattr $C$DW$119, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$119, DW_AT_decl_line(0x56) + .dwattr $C$DW$119, DW_AT_decl_column(0x0d) + .dwattr $C$DW$119, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 87,column 1,is_stmt,address dmaErrorHwi,isa 1 + + .dwfde $C$DW$CIE, dmaErrorHwi +$C$DW$120 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$120, DW_AT_name("arg") + .dwattr $C$DW$120, DW_AT_TI_symbol_name("arg") + .dwattr $C$DW$120, DW_AT_type(*$C$DW$T$1241) + .dwattr $C$DW$120, DW_AT_location[DW_OP_reg0] + +;---------------------------------------------------------------------- +; 86 | static Void dmaErrorHwi(UArg arg) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: dmaErrorHwi * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 4 Auto + 4 Save = 8 byte * +;***************************************************************************** +dmaErrorHwi: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 +$C$DW$121 .dwtag DW_TAG_variable + .dwattr $C$DW$121, DW_AT_name("arg") + .dwattr $C$DW$121, DW_AT_TI_symbol_name("arg") + .dwattr $C$DW$121, DW_AT_type(*$C$DW$T$1241) + .dwattr $C$DW$121, DW_AT_location[DW_OP_breg13 0] + + STR A1, [SP, #0] ; [DPU_V7M3_PIPE] |87| + .dwpsn file "../EK_TM4C123GXL.c",line 88,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 88 | System_printf("DMA error code: %d\n", uDMAErrorStatusGet()); +;---------------------------------------------------------------------- +$C$DW$122 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$122, DW_AT_low_pc(0x00) + .dwattr $C$DW$122, DW_AT_name("uDMAErrorStatusGet") + .dwattr $C$DW$122, DW_AT_TI_call + + BL uDMAErrorStatusGet ; [DPU_V7M3_PIPE] |88| + ; CALL OCCURS {uDMAErrorStatusGet } ; [] |88| + MOV A2, A1 ; [DPU_V7M3_PIPE] |88| + ADR A1, $C$SL1 ; [DPU_V7M3_PIPE] |88| +$C$DW$123 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$123, DW_AT_low_pc(0x00) + .dwattr $C$DW$123, DW_AT_name("xdc_runtime_System_printf__E") + .dwattr $C$DW$123, DW_AT_TI_call + + BL xdc_runtime_System_printf__E ; [DPU_V7M3_PIPE] |88| + ; CALL OCCURS {xdc_runtime_System_printf__E } ; [] |88| + .dwpsn file "../EK_TM4C123GXL.c",line 89,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 89 | uDMAErrorStatusClear(); +;---------------------------------------------------------------------- +$C$DW$124 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$124, DW_AT_low_pc(0x00) + .dwattr $C$DW$124, DW_AT_name("uDMAErrorStatusClear") + .dwattr $C$DW$124, DW_AT_TI_call + + BL uDMAErrorStatusClear ; [DPU_V7M3_PIPE] |89| + ; CALL OCCURS {uDMAErrorStatusClear } ; [] |89| + .dwpsn file "../EK_TM4C123GXL.c",line 90,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 90 | System_abort("DMA error!!"); +;---------------------------------------------------------------------- + ADR A1, $C$SL2 ; [DPU_V7M3_PIPE] |90| +$C$DW$125 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$125, DW_AT_low_pc(0x00) + .dwattr $C$DW$125, DW_AT_name("xdc_runtime_System_abort__E") + .dwattr $C$DW$125, DW_AT_TI_call + + BL xdc_runtime_System_abort__E ; [DPU_V7M3_PIPE] |90| + ; CALL OCCURS {xdc_runtime_System_abort__E } ; [] |90| + .dwpsn file "../EK_TM4C123GXL.c",line 91,column 1,is_stmt,isa 1 +$C$DW$126 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$126, DW_AT_low_pc(0x00) + .dwattr $C$DW$126, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$119, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$119, DW_AT_TI_end_line(0x5b) + .dwattr $C$DW$119, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$119 + + .sect ".text:EK_TM4C123GXL_initDMA" + .clink + .thumbfunc EK_TM4C123GXL_initDMA + .thumb + .global EK_TM4C123GXL_initDMA + +$C$DW$127 .dwtag DW_TAG_subprogram + .dwattr $C$DW$127, DW_AT_name("EK_TM4C123GXL_initDMA") + .dwattr $C$DW$127, DW_AT_low_pc(EK_TM4C123GXL_initDMA) + .dwattr $C$DW$127, DW_AT_high_pc(0x00) + .dwattr $C$DW$127, DW_AT_TI_symbol_name("EK_TM4C123GXL_initDMA") + .dwattr $C$DW$127, DW_AT_external + .dwattr $C$DW$127, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$127, DW_AT_TI_begin_line(0x60) + .dwattr $C$DW$127, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$127, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$127, DW_AT_decl_line(0x60) + .dwattr $C$DW$127, DW_AT_decl_column(0x06) + .dwattr $C$DW$127, DW_AT_TI_max_frame_size(0x68) + .dwpsn file "../EK_TM4C123GXL.c",line 97,column 1,is_stmt,address EK_TM4C123GXL_initDMA,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initDMA +;---------------------------------------------------------------------- +; 96 | void EK_TM4C123GXL_initDMA(void) +; 98 | Error_Block eb; +; 99 | Hwi_Params hwiParams; +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initDMA * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 4 Args + 96 Auto + 4 Save = 104 byte * +;***************************************************************************** +EK_TM4C123GXL_initDMA: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 4 + .dwcfi save_reg_to_mem, 14, -4 + SUB SP, SP, #100 ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 104 +$C$DW$128 .dwtag DW_TAG_variable + .dwattr $C$DW$128, DW_AT_name("eb") + .dwattr $C$DW$128, DW_AT_TI_symbol_name("eb") + .dwattr $C$DW$128, DW_AT_type(*$C$DW$T$638) + .dwattr $C$DW$128, DW_AT_location[DW_OP_breg13 4] + +$C$DW$129 .dwtag DW_TAG_variable + .dwattr $C$DW$129, DW_AT_name("hwiParams") + .dwattr $C$DW$129, DW_AT_TI_symbol_name("hwiParams") + .dwattr $C$DW$129, DW_AT_type(*$C$DW$T$1219) + .dwattr $C$DW$129, DW_AT_location[DW_OP_breg13 52] + + .dwpsn file "../EK_TM4C123GXL.c",line 101,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 101 | if (!dmaInitialized) { +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |101| + LDRB A1, [A1, #0] ; [DPU_V7M3_PIPE] |101| + CBNZ A1, ||$C$L3|| ; [] + ; BRANCHCC OCCURS {||$C$L3||} ; [] |101| +;* --------------------------------------------------------------------------* + .dwpsn file "../EK_TM4C123GXL.c",line 102,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 102 | Error_init(&eb); +;---------------------------------------------------------------------- + ADD A1, SP, #4 ; [DPU_V7M3_PIPE] |102| +$C$DW$130 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$130, DW_AT_low_pc(0x00) + .dwattr $C$DW$130, DW_AT_name("xdc_runtime_Error_init__E") + .dwattr $C$DW$130, DW_AT_TI_call + + BL xdc_runtime_Error_init__E ; [DPU_V7M3_PIPE] |102| + ; CALL OCCURS {xdc_runtime_Error_init__E } ; [] |102| + .dwpsn file "../EK_TM4C123GXL.c",line 103,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 103 | Hwi_Params_init(&hwiParams); +;---------------------------------------------------------------------- + ADD A1, SP, #52 ; [DPU_V7M3_PIPE] |103| +$C$DW$131 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$131, DW_AT_low_pc(0x00) + .dwattr $C$DW$131, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Params_init") + .dwattr $C$DW$131, DW_AT_TI_call + + BL ti_sysbios_family_arm_m3_Hwi_Params_init ; [DPU_V7M3_PIPE] |103| + ; CALL OCCURS {ti_sysbios_family_arm_m3_Hwi_Params_init } ; [] |103| + .dwpsn file "../EK_TM4C123GXL.c",line 104,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 104 | Hwi_construct(&(dmaHwiStruct), INT_UDMAERR, dmaErrorHwi, +; 105 | &hwiParams, &eb); +;---------------------------------------------------------------------- + ADD A1, SP, #4 ; [DPU_V7M3_PIPE] |104| + STR A1, [SP, #0] ; [DPU_V7M3_PIPE] |104| + LDR A3, $C$CON3 ; [DPU_V7M3_PIPE] |104| + LDR A1, $C$CON2 ; [DPU_V7M3_PIPE] |104| + MOVS A2, #63 ; [DPU_V7M3_PIPE] |104| + ADD A4, SP, #52 ; [DPU_V7M3_PIPE] |104| +$C$DW$132 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$132, DW_AT_low_pc(0x00) + .dwattr $C$DW$132, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_construct") + .dwattr $C$DW$132, DW_AT_TI_call + + BL ti_sysbios_family_arm_m3_Hwi_construct ; [DPU_V7M3_PIPE] |104| + ; CALL OCCURS {ti_sysbios_family_arm_m3_Hwi_construct } ; [] |104| + .dwpsn file "../EK_TM4C123GXL.c",line 106,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 106 | if (Error_check(&eb)) { +;---------------------------------------------------------------------- + ADD A1, SP, #4 ; [DPU_V7M3_PIPE] |106| +$C$DW$133 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$133, DW_AT_low_pc(0x00) + .dwattr $C$DW$133, DW_AT_name("xdc_runtime_Error_check__E") + .dwattr $C$DW$133, DW_AT_TI_call + + BL xdc_runtime_Error_check__E ; [DPU_V7M3_PIPE] |106| + ; CALL OCCURS {xdc_runtime_Error_check__E } ; [] |106| + CBZ A1, ||$C$L2|| ; [] + ; BRANCHCC OCCURS {||$C$L2||} ; [] |106| +;* --------------------------------------------------------------------------* + .dwpsn file "../EK_TM4C123GXL.c",line 107,column 13,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 107 | System_abort("Couldn't construct DMA error hwi"); +;---------------------------------------------------------------------- + ADR A1, $C$SL3 ; [DPU_V7M3_PIPE] |107| +$C$DW$134 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$134, DW_AT_low_pc(0x00) + .dwattr $C$DW$134, DW_AT_name("xdc_runtime_System_abort__E") + .dwattr $C$DW$134, DW_AT_TI_call + + BL xdc_runtime_System_abort__E ; [DPU_V7M3_PIPE] |107| + ; CALL OCCURS {xdc_runtime_System_abort__E } ; [] |107| +;* --------------------------------------------------------------------------* +||$C$L2||: + .dwpsn file "../EK_TM4C123GXL.c",line 110,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 110 | SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); +;---------------------------------------------------------------------- + LDR A1, $C$CON4 ; [DPU_V7M3_PIPE] |110| +$C$DW$135 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$135, DW_AT_low_pc(0x00) + .dwattr $C$DW$135, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$135, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |110| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |110| + .dwpsn file "../EK_TM4C123GXL.c",line 111,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 111 | uDMAEnable(); +;---------------------------------------------------------------------- +$C$DW$136 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$136, DW_AT_low_pc(0x00) + .dwattr $C$DW$136, DW_AT_name("uDMAEnable") + .dwattr $C$DW$136, DW_AT_TI_call + + BL uDMAEnable ; [DPU_V7M3_PIPE] |111| + ; CALL OCCURS {uDMAEnable } ; [] |111| + .dwpsn file "../EK_TM4C123GXL.c",line 112,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 112 | uDMAControlBaseSet(dmaControlTable); +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |112| +$C$DW$137 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$137, DW_AT_low_pc(0x00) + .dwattr $C$DW$137, DW_AT_name("uDMAControlBaseSet") + .dwattr $C$DW$137, DW_AT_TI_call + + BL uDMAControlBaseSet ; [DPU_V7M3_PIPE] |112| + ; CALL OCCURS {uDMAControlBaseSet } ; [] |112| + .dwpsn file "../EK_TM4C123GXL.c",line 114,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 114 | dmaInitialized = true; +;---------------------------------------------------------------------- + LDR A2, $C$CON1 ; [DPU_V7M3_PIPE] |114| + MOVS A1, #1 ; [DPU_V7M3_PIPE] |114| + STRB A1, [A2, #0] ; [DPU_V7M3_PIPE] |114| + .dwpsn file "../EK_TM4C123GXL.c",line 116,column 1,is_stmt,isa 1 +;* --------------------------------------------------------------------------* +||$C$L3||: + ADD SP, SP, #100 ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 4 +$C$DW$138 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$138, DW_AT_low_pc(0x00) + .dwattr $C$DW$138, DW_AT_TI_return + + POP {PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$127, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$127, DW_AT_TI_end_line(0x74) + .dwattr $C$DW$127, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$127 + + .sect ".text:EK_TM4C123GXL_initGeneral" + .clink + .thumbfunc EK_TM4C123GXL_initGeneral + .thumb + .global EK_TM4C123GXL_initGeneral + +$C$DW$139 .dwtag DW_TAG_subprogram + .dwattr $C$DW$139, DW_AT_name("EK_TM4C123GXL_initGeneral") + .dwattr $C$DW$139, DW_AT_low_pc(EK_TM4C123GXL_initGeneral) + .dwattr $C$DW$139, DW_AT_high_pc(0x00) + .dwattr $C$DW$139, DW_AT_TI_symbol_name("EK_TM4C123GXL_initGeneral") + .dwattr $C$DW$139, DW_AT_external + .dwattr $C$DW$139, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$139, DW_AT_TI_begin_line(0x7c) + .dwattr $C$DW$139, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$139, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$139, DW_AT_decl_line(0x7c) + .dwattr $C$DW$139, DW_AT_decl_column(0x06) + .dwattr $C$DW$139, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 125,column 1,is_stmt,address EK_TM4C123GXL_initGeneral,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initGeneral +;---------------------------------------------------------------------- +; 124 | void EK_TM4C123GXL_initGeneral(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initGeneral * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initGeneral: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 126,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 126 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |126| +$C$DW$140 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$140, DW_AT_low_pc(0x00) + .dwattr $C$DW$140, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$140, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |126| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |126| + .dwpsn file "../EK_TM4C123GXL.c",line 127,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 127 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); +;---------------------------------------------------------------------- + LDR A1, $C$CON7 ; [DPU_V7M3_PIPE] |127| +$C$DW$141 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$141, DW_AT_low_pc(0x00) + .dwattr $C$DW$141, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$141, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |127| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |127| + .dwpsn file "../EK_TM4C123GXL.c",line 128,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 128 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); +;---------------------------------------------------------------------- + LDR A1, $C$CON8 ; [DPU_V7M3_PIPE] |128| +$C$DW$142 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$142, DW_AT_low_pc(0x00) + .dwattr $C$DW$142, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$142, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |128| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |128| + .dwpsn file "../EK_TM4C123GXL.c",line 129,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 129 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); +;---------------------------------------------------------------------- + LDR A1, $C$CON9 ; [DPU_V7M3_PIPE] |129| +$C$DW$143 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$143, DW_AT_low_pc(0x00) + .dwattr $C$DW$143, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$143, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |129| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |129| + .dwpsn file "../EK_TM4C123GXL.c",line 130,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 130 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); +;---------------------------------------------------------------------- + LDR A1, $C$CON10 ; [DPU_V7M3_PIPE] |130| +$C$DW$144 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$144, DW_AT_low_pc(0x00) + .dwattr $C$DW$144, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$144, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |130| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |130| + .dwpsn file "../EK_TM4C123GXL.c",line 131,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 131 | SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); +;---------------------------------------------------------------------- + LDR A1, $C$CON11 ; [DPU_V7M3_PIPE] |131| +$C$DW$145 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$145, DW_AT_low_pc(0x00) + .dwattr $C$DW$145, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$145, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |131| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |131| + .dwpsn file "../EK_TM4C123GXL.c",line 132,column 1,is_stmt,isa 1 +$C$DW$146 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$146, DW_AT_low_pc(0x00) + .dwattr $C$DW$146, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$139, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$139, DW_AT_TI_end_line(0x84) + .dwattr $C$DW$139, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$139 + + .sect ".text:EK_TM4C123GXL_initGPIO" + .clink + .thumbfunc EK_TM4C123GXL_initGPIO + .thumb + .global EK_TM4C123GXL_initGPIO + +$C$DW$147 .dwtag DW_TAG_subprogram + .dwattr $C$DW$147, DW_AT_name("EK_TM4C123GXL_initGPIO") + .dwattr $C$DW$147, DW_AT_low_pc(EK_TM4C123GXL_initGPIO) + .dwattr $C$DW$147, DW_AT_high_pc(0x00) + .dwattr $C$DW$147, DW_AT_TI_symbol_name("EK_TM4C123GXL_initGPIO") + .dwattr $C$DW$147, DW_AT_external + .dwattr $C$DW$147, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$147, DW_AT_TI_begin_line(0xc1) + .dwattr $C$DW$147, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$147, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$147, DW_AT_decl_line(0xc1) + .dwattr $C$DW$147, DW_AT_decl_column(0x06) + .dwattr $C$DW$147, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 194,column 1,is_stmt,address EK_TM4C123GXL_initGPIO,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initGPIO +;---------------------------------------------------------------------- +; 193 | void EK_TM4C123GXL_initGPIO(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initGPIO * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initGPIO: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 196,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 196 | HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY; +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |196| + LDR A2, $C$CON12 ; [DPU_V7M3_PIPE] |196| + STR A1, [A2, #0] ; [DPU_V7M3_PIPE] |196| + .dwpsn file "../EK_TM4C123GXL.c",line 197,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 197 | HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= GPIO_PIN_0; +;---------------------------------------------------------------------- + LDR A2, $C$CON14 ; [DPU_V7M3_PIPE] |197| + LDR A1, [A2, #0] ; [DPU_V7M3_PIPE] |197| + ORR A1, A1, #1 ; [DPU_V7M3_PIPE] |197| + STR A1, [A2, #0] ; [DPU_V7M3_PIPE] |197| + .dwpsn file "../EK_TM4C123GXL.c",line 198,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 198 | GPIOPinTypeGPIOInput(GPIO_PORTF_BASE, GPIO_PIN_0); +;---------------------------------------------------------------------- + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |198| + MOVS A2, #1 ; [DPU_V7M3_PIPE] |198| +$C$DW$148 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$148, DW_AT_low_pc(0x00) + .dwattr $C$DW$148, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$148, DW_AT_TI_call + + BL GPIOPinTypeGPIOInput ; [DPU_V7M3_PIPE] |198| + ; CALL OCCURS {GPIOPinTypeGPIOInput } ; [] |198| + .dwpsn file "../EK_TM4C123GXL.c",line 201,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 201 | GPIO_init(); +;---------------------------------------------------------------------- +$C$DW$149 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$149, DW_AT_low_pc(0x00) + .dwattr $C$DW$149, DW_AT_name("GPIO_init") + .dwattr $C$DW$149, DW_AT_TI_call + + BL GPIO_init ; [DPU_V7M3_PIPE] |201| + ; CALL OCCURS {GPIO_init } ; [] |201| + .dwpsn file "../EK_TM4C123GXL.c",line 202,column 1,is_stmt,isa 1 +$C$DW$150 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$150, DW_AT_low_pc(0x00) + .dwattr $C$DW$150, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$147, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$147, DW_AT_TI_end_line(0xca) + .dwattr $C$DW$147, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$147 + + .sect ".text:EK_TM4C123GXL_initI2C" + .clink + .thumbfunc EK_TM4C123GXL_initI2C + .thumb + .global EK_TM4C123GXL_initI2C + +$C$DW$151 .dwtag DW_TAG_subprogram + .dwattr $C$DW$151, DW_AT_name("EK_TM4C123GXL_initI2C") + .dwattr $C$DW$151, DW_AT_low_pc(EK_TM4C123GXL_initI2C) + .dwattr $C$DW$151, DW_AT_high_pc(0x00) + .dwattr $C$DW$151, DW_AT_TI_symbol_name("EK_TM4C123GXL_initI2C") + .dwattr $C$DW$151, DW_AT_external + .dwattr $C$DW$151, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$151, DW_AT_TI_begin_line(0xf8) + .dwattr $C$DW$151, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$151, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$151, DW_AT_decl_line(0xf8) + .dwattr $C$DW$151, DW_AT_decl_column(0x06) + .dwattr $C$DW$151, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 249,column 1,is_stmt,address EK_TM4C123GXL_initI2C,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initI2C +;---------------------------------------------------------------------- +; 248 | void EK_TM4C123GXL_initI2C(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initI2C * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initI2C: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 252,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 252 | SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C1); +;---------------------------------------------------------------------- + LDR A1, $C$CON16 ; [DPU_V7M3_PIPE] |252| +$C$DW$152 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$152, DW_AT_low_pc(0x00) + .dwattr $C$DW$152, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$152, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |252| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |252| + .dwpsn file "../EK_TM4C123GXL.c",line 255,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 255 | GPIOPinConfigure(GPIO_PA6_I2C1SCL); +;---------------------------------------------------------------------- + MOV A1, #6147 ; [DPU_V7M3_PIPE] |255| +$C$DW$153 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$153, DW_AT_low_pc(0x00) + .dwattr $C$DW$153, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$153, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |255| + ; CALL OCCURS {GPIOPinConfigure } ; [] |255| + .dwpsn file "../EK_TM4C123GXL.c",line 256,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 256 | GPIOPinConfigure(GPIO_PA7_I2C1SDA); +;---------------------------------------------------------------------- + MOV A1, #7171 ; [DPU_V7M3_PIPE] |256| +$C$DW$154 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$154, DW_AT_low_pc(0x00) + .dwattr $C$DW$154, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$154, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |256| + ; CALL OCCURS {GPIOPinConfigure } ; [] |256| + .dwpsn file "../EK_TM4C123GXL.c",line 257,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 257 | GPIOPinTypeI2CSCL(GPIO_PORTA_BASE, GPIO_PIN_6); +;---------------------------------------------------------------------- + MOV A1, #1073758208 ; [DPU_V7M3_PIPE] |257| + MOVS A2, #64 ; [DPU_V7M3_PIPE] |257| +$C$DW$155 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$155, DW_AT_low_pc(0x00) + .dwattr $C$DW$155, DW_AT_name("GPIOPinTypeI2CSCL") + .dwattr $C$DW$155, DW_AT_TI_call + + BL GPIOPinTypeI2CSCL ; [DPU_V7M3_PIPE] |257| + ; CALL OCCURS {GPIOPinTypeI2CSCL } ; [] |257| + .dwpsn file "../EK_TM4C123GXL.c",line 258,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 258 | GPIOPinTypeI2C(GPIO_PORTA_BASE, GPIO_PIN_7); +;---------------------------------------------------------------------- + MOV A1, #1073758208 ; [DPU_V7M3_PIPE] |258| + MOVS A2, #128 ; [DPU_V7M3_PIPE] |258| +$C$DW$156 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$156, DW_AT_low_pc(0x00) + .dwattr $C$DW$156, DW_AT_name("GPIOPinTypeI2C") + .dwattr $C$DW$156, DW_AT_TI_call + + BL GPIOPinTypeI2C ; [DPU_V7M3_PIPE] |258| + ; CALL OCCURS {GPIOPinTypeI2C } ; [] |258| + .dwpsn file "../EK_TM4C123GXL.c",line 268,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 268 | SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C3); +;---------------------------------------------------------------------- + LDR A1, $C$CON17 ; [DPU_V7M3_PIPE] |268| +$C$DW$157 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$157, DW_AT_low_pc(0x00) + .dwattr $C$DW$157, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$157, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |268| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |268| + .dwpsn file "../EK_TM4C123GXL.c",line 271,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 271 | GPIOPinConfigure(GPIO_PD0_I2C3SCL); +;---------------------------------------------------------------------- + MOV A1, #196611 ; [DPU_V7M3_PIPE] |271| +$C$DW$158 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$158, DW_AT_low_pc(0x00) + .dwattr $C$DW$158, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$158, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |271| + ; CALL OCCURS {GPIOPinConfigure } ; [] |271| +;* --------------------------------------------------------------------------* + .dwpsn file "../EK_TM4C123GXL.c",line 272,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 272 | GPIOPinConfigure(GPIO_PD1_I2C3SDA); +;---------------------------------------------------------------------- + LDR A1, $C$CON18 ; [DPU_V7M3_PIPE] |272| +$C$DW$159 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$159, DW_AT_low_pc(0x00) + .dwattr $C$DW$159, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$159, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |272| + ; CALL OCCURS {GPIOPinConfigure } ; [] |272| + .dwpsn file "../EK_TM4C123GXL.c",line 273,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 273 | GPIOPinTypeI2CSCL(GPIO_PORTD_BASE, GPIO_PIN_0); +;---------------------------------------------------------------------- + LDR A1, $C$CON19 ; [DPU_V7M3_PIPE] |273| + MOVS A2, #1 ; [DPU_V7M3_PIPE] |273| +$C$DW$160 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$160, DW_AT_low_pc(0x00) + .dwattr $C$DW$160, DW_AT_name("GPIOPinTypeI2CSCL") + .dwattr $C$DW$160, DW_AT_TI_call + + BL GPIOPinTypeI2CSCL ; [DPU_V7M3_PIPE] |273| + ; CALL OCCURS {GPIOPinTypeI2CSCL } ; [] |273| + .dwpsn file "../EK_TM4C123GXL.c",line 274,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 274 | GPIOPinTypeI2C(GPIO_PORTD_BASE, GPIO_PIN_1); +;---------------------------------------------------------------------- + LDR A1, $C$CON19 ; [DPU_V7M3_PIPE] |274| + MOVS A2, #2 ; [DPU_V7M3_PIPE] |274| +$C$DW$161 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$161, DW_AT_low_pc(0x00) + .dwattr $C$DW$161, DW_AT_name("GPIOPinTypeI2C") + .dwattr $C$DW$161, DW_AT_TI_call + + BL GPIOPinTypeI2C ; [DPU_V7M3_PIPE] |274| + ; CALL OCCURS {GPIOPinTypeI2C } ; [] |274| + .dwpsn file "../EK_TM4C123GXL.c",line 280,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 280 | GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_6); +;---------------------------------------------------------------------- + LDR A1, $C$CON20 ; [DPU_V7M3_PIPE] |280| + MOVS A2, #64 ; [DPU_V7M3_PIPE] |280| +$C$DW$162 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$162, DW_AT_low_pc(0x00) + .dwattr $C$DW$162, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$162, DW_AT_TI_call + + BL GPIOPinTypeGPIOInput ; [DPU_V7M3_PIPE] |280| + ; CALL OCCURS {GPIOPinTypeGPIOInput } ; [] |280| + .dwpsn file "../EK_TM4C123GXL.c",line 281,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 281 | GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_7); +;---------------------------------------------------------------------- + LDR A1, $C$CON20 ; [DPU_V7M3_PIPE] |281| + MOVS A2, #128 ; [DPU_V7M3_PIPE] |281| +$C$DW$163 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$163, DW_AT_low_pc(0x00) + .dwattr $C$DW$163, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$163, DW_AT_TI_call + + BL GPIOPinTypeGPIOInput ; [DPU_V7M3_PIPE] |281| + ; CALL OCCURS {GPIOPinTypeGPIOInput } ; [] |281| + .dwpsn file "../EK_TM4C123GXL.c",line 283,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 283 | I2C_init(); +;---------------------------------------------------------------------- +$C$DW$164 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$164, DW_AT_low_pc(0x00) + .dwattr $C$DW$164, DW_AT_name("I2C_init") + .dwattr $C$DW$164, DW_AT_TI_call + + BL I2C_init ; [DPU_V7M3_PIPE] |283| + ; CALL OCCURS {I2C_init } ; [] |283| + .dwpsn file "../EK_TM4C123GXL.c",line 284,column 1,is_stmt,isa 1 +$C$DW$165 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$165, DW_AT_low_pc(0x00) + .dwattr $C$DW$165, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$151, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$151, DW_AT_TI_end_line(0x11c) + .dwattr $C$DW$151, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$151 + + .sect ".text:EK_TM4C123GXL_initPWM" + .clink + .thumbfunc EK_TM4C123GXL_initPWM + .thumb + .global EK_TM4C123GXL_initPWM + +$C$DW$166 .dwtag DW_TAG_subprogram + .dwattr $C$DW$166, DW_AT_name("EK_TM4C123GXL_initPWM") + .dwattr $C$DW$166, DW_AT_low_pc(EK_TM4C123GXL_initPWM) + .dwattr $C$DW$166, DW_AT_high_pc(0x00) + .dwattr $C$DW$166, DW_AT_TI_symbol_name("EK_TM4C123GXL_initPWM") + .dwattr $C$DW$166, DW_AT_external + .dwattr $C$DW$166, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$166, DW_AT_TI_begin_line(0x14a) + .dwattr $C$DW$166, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$166, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$166, DW_AT_decl_line(0x14a) + .dwattr $C$DW$166, DW_AT_decl_column(0x06) + .dwattr $C$DW$166, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 331,column 1,is_stmt,address EK_TM4C123GXL_initPWM,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initPWM +;---------------------------------------------------------------------- +; 330 | void EK_TM4C123GXL_initPWM(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initPWM * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initPWM: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 333,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 333 | SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1); +;---------------------------------------------------------------------- + LDR A1, $C$CON21 ; [DPU_V7M3_PIPE] |333| +$C$DW$167 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$167, DW_AT_low_pc(0x00) + .dwattr $C$DW$167, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$167, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |333| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |333| + .dwpsn file "../EK_TM4C123GXL.c",line 339,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 339 | GPIOPinConfigure(GPIO_PF2_M1PWM6); +;---------------------------------------------------------------------- + LDR A1, $C$CON22 ; [DPU_V7M3_PIPE] |339| +$C$DW$168 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$168, DW_AT_low_pc(0x00) + .dwattr $C$DW$168, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$168, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |339| + ; CALL OCCURS {GPIOPinConfigure } ; [] |339| + .dwpsn file "../EK_TM4C123GXL.c",line 340,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 340 | GPIOPinConfigure(GPIO_PF3_M1PWM7); +;---------------------------------------------------------------------- + LDR A1, $C$CON23 ; [DPU_V7M3_PIPE] |340| +$C$DW$169 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$169, DW_AT_low_pc(0x00) + .dwattr $C$DW$169, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$169, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |340| + ; CALL OCCURS {GPIOPinConfigure } ; [] |340| + .dwpsn file "../EK_TM4C123GXL.c",line 341,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 341 | GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2 |GPIO_PIN_3); +;---------------------------------------------------------------------- + LDR A1, $C$CON24 ; [DPU_V7M3_PIPE] |341| + MOVS A2, #12 ; [DPU_V7M3_PIPE] |341| +$C$DW$170 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$170, DW_AT_low_pc(0x00) + .dwattr $C$DW$170, DW_AT_name("GPIOPinTypePWM") + .dwattr $C$DW$170, DW_AT_TI_call + + BL GPIOPinTypePWM ; [DPU_V7M3_PIPE] |341| + ; CALL OCCURS {GPIOPinTypePWM } ; [] |341| + .dwpsn file "../EK_TM4C123GXL.c",line 343,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 343 | PWM_init(); +;---------------------------------------------------------------------- +$C$DW$171 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$171, DW_AT_low_pc(0x00) + .dwattr $C$DW$171, DW_AT_name("PWM_init") + .dwattr $C$DW$171, DW_AT_TI_call + + BL PWM_init ; [DPU_V7M3_PIPE] |343| + ; CALL OCCURS {PWM_init } ; [] |343| + .dwpsn file "../EK_TM4C123GXL.c",line 344,column 1,is_stmt,isa 1 +$C$DW$172 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$172, DW_AT_low_pc(0x00) + .dwattr $C$DW$172, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$166, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$166, DW_AT_TI_end_line(0x158) + .dwattr $C$DW$166, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$166 + + .sect ".text:EK_TM4C123GXL_initSDSPI" + .clink + .thumbfunc EK_TM4C123GXL_initSDSPI + .thumb + .global EK_TM4C123GXL_initSDSPI + +$C$DW$173 .dwtag DW_TAG_subprogram + .dwattr $C$DW$173, DW_AT_name("EK_TM4C123GXL_initSDSPI") + .dwattr $C$DW$173, DW_AT_low_pc(EK_TM4C123GXL_initSDSPI) + .dwattr $C$DW$173, DW_AT_high_pc(0x00) + .dwattr $C$DW$173, DW_AT_TI_symbol_name("EK_TM4C123GXL_initSDSPI") + .dwattr $C$DW$173, DW_AT_external + .dwattr $C$DW$173, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$173, DW_AT_TI_begin_line(0x183) + .dwattr $C$DW$173, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$173, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$173, DW_AT_decl_line(0x183) + .dwattr $C$DW$173, DW_AT_decl_column(0x06) + .dwattr $C$DW$173, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 388,column 1,is_stmt,address EK_TM4C123GXL_initSDSPI,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initSDSPI +;---------------------------------------------------------------------- +; 387 | void EK_TM4C123GXL_initSDSPI(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initSDSPI * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initSDSPI: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 390,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 390 | SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); +;---------------------------------------------------------------------- + LDR A1, $C$CON25 ; [DPU_V7M3_PIPE] |390| +$C$DW$174 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$174, DW_AT_low_pc(0x00) + .dwattr $C$DW$174, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$174, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |390| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |390| + .dwpsn file "../EK_TM4C123GXL.c",line 393,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 393 | GPIOPadConfigSet(GPIO_PORTB_BASE, +; 394 | GPIO_PIN_4 | GPIO_PIN_7, +; 395 | GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD); +;---------------------------------------------------------------------- + LDR A1, $C$CON26 ; [DPU_V7M3_PIPE] |393| + MOVS A2, #144 ; [DPU_V7M3_PIPE] |393| + MOVS A3, #2 ; [DPU_V7M3_PIPE] |393| + MOVS A4, #8 ; [DPU_V7M3_PIPE] |393| +$C$DW$175 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$175, DW_AT_low_pc(0x00) + .dwattr $C$DW$175, DW_AT_name("GPIOPadConfigSet") + .dwattr $C$DW$175, DW_AT_TI_call + + BL GPIOPadConfigSet ; [DPU_V7M3_PIPE] |393| + ; CALL OCCURS {GPIOPadConfigSet } ; [] |393| + .dwpsn file "../EK_TM4C123GXL.c",line 397,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 397 | GPIOPadConfigSet(GPIO_PORTB_BASE, +; 398 | GPIO_PIN_6, +; 399 | GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU); +;---------------------------------------------------------------------- + LDR A1, $C$CON26 ; [DPU_V7M3_PIPE] |397| + MOVS A2, #64 ; [DPU_V7M3_PIPE] |397| + MOVS A3, #2 ; [DPU_V7M3_PIPE] |397| + MOVS A4, #10 ; [DPU_V7M3_PIPE] |397| +$C$DW$176 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$176, DW_AT_low_pc(0x00) + .dwattr $C$DW$176, DW_AT_name("GPIOPadConfigSet") + .dwattr $C$DW$176, DW_AT_TI_call + + BL GPIOPadConfigSet ; [DPU_V7M3_PIPE] |397| + ; CALL OCCURS {GPIOPadConfigSet } ; [] |397| + .dwpsn file "../EK_TM4C123GXL.c",line 401,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 401 | GPIOPadConfigSet(GPIO_PORTA_BASE, +; 402 | GPIO_PIN_5, +; 403 | GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD); +;---------------------------------------------------------------------- + MOV A1, #1073758208 ; [DPU_V7M3_PIPE] |401| + MOVS A2, #32 ; [DPU_V7M3_PIPE] |401| + MOVS A3, #2 ; [DPU_V7M3_PIPE] |401| + MOVS A4, #8 ; [DPU_V7M3_PIPE] |401| +$C$DW$177 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$177, DW_AT_low_pc(0x00) + .dwattr $C$DW$177, DW_AT_name("GPIOPadConfigSet") + .dwattr $C$DW$177, DW_AT_TI_call + + BL GPIOPadConfigSet ; [DPU_V7M3_PIPE] |401| + ; CALL OCCURS {GPIOPadConfigSet } ; [] |401| + .dwpsn file "../EK_TM4C123GXL.c",line 405,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 405 | GPIOPinConfigure(GPIO_PB4_SSI2CLK); +;---------------------------------------------------------------------- + LDR A1, $C$CON27 ; [DPU_V7M3_PIPE] |405| +$C$DW$178 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$178, DW_AT_low_pc(0x00) + .dwattr $C$DW$178, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$178, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |405| + ; CALL OCCURS {GPIOPinConfigure } ; [] |405| + .dwpsn file "../EK_TM4C123GXL.c",line 406,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 406 | GPIOPinConfigure(GPIO_PB6_SSI2RX); +;---------------------------------------------------------------------- + LDR A1, $C$CON28 ; [DPU_V7M3_PIPE] |406| +$C$DW$179 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$179, DW_AT_low_pc(0x00) + .dwattr $C$DW$179, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$179, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |406| + ; CALL OCCURS {GPIOPinConfigure } ; [] |406| + .dwpsn file "../EK_TM4C123GXL.c",line 407,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 407 | GPIOPinConfigure(GPIO_PB7_SSI2TX); +;---------------------------------------------------------------------- + LDR A1, $C$CON29 ; [DPU_V7M3_PIPE] |407| +$C$DW$180 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$180, DW_AT_low_pc(0x00) + .dwattr $C$DW$180, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$180, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |407| + ; CALL OCCURS {GPIOPinConfigure } ; [] |407| + .dwpsn file "../EK_TM4C123GXL.c",line 413,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 413 | GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_0); +;---------------------------------------------------------------------- + LDR A1, $C$CON30 ; [DPU_V7M3_PIPE] |413| + MOVS A2, #1 ; [DPU_V7M3_PIPE] |413| +$C$DW$181 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$181, DW_AT_low_pc(0x00) + .dwattr $C$DW$181, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$181, DW_AT_TI_call + + BL GPIOPinTypeGPIOInput ; [DPU_V7M3_PIPE] |413| + ; CALL OCCURS {GPIOPinTypeGPIOInput } ; [] |413| + .dwpsn file "../EK_TM4C123GXL.c",line 414,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 414 | GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_1); +;---------------------------------------------------------------------- + LDR A1, $C$CON30 ; [DPU_V7M3_PIPE] |414| + MOVS A2, #2 ; [DPU_V7M3_PIPE] |414| +$C$DW$182 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$182, DW_AT_low_pc(0x00) + .dwattr $C$DW$182, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$182, DW_AT_TI_call + + BL GPIOPinTypeGPIOInput ; [DPU_V7M3_PIPE] |414| + ; CALL OCCURS {GPIOPinTypeGPIOInput } ; [] |414| + .dwpsn file "../EK_TM4C123GXL.c",line 416,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 416 | SDSPI_init(); +;---------------------------------------------------------------------- +$C$DW$183 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$183, DW_AT_low_pc(0x00) + .dwattr $C$DW$183, DW_AT_name("SDSPI_init") + .dwattr $C$DW$183, DW_AT_TI_call + + BL SDSPI_init ; [DPU_V7M3_PIPE] |416| + ; CALL OCCURS {SDSPI_init } ; [] |416| + .dwpsn file "../EK_TM4C123GXL.c",line 417,column 1,is_stmt,isa 1 +$C$DW$184 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$184, DW_AT_low_pc(0x00) + .dwattr $C$DW$184, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$173, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$173, DW_AT_TI_end_line(0x1a1) + .dwattr $C$DW$173, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$173 + + .sect ".text:EK_TM4C123GXL_initSPI" + .clink + .thumbfunc EK_TM4C123GXL_initSPI + .thumb + .global EK_TM4C123GXL_initSPI + +$C$DW$185 .dwtag DW_TAG_subprogram + .dwattr $C$DW$185, DW_AT_name("EK_TM4C123GXL_initSPI") + .dwattr $C$DW$185, DW_AT_low_pc(EK_TM4C123GXL_initSPI) + .dwattr $C$DW$185, DW_AT_high_pc(0x00) + .dwattr $C$DW$185, DW_AT_TI_symbol_name("EK_TM4C123GXL_initSPI") + .dwattr $C$DW$185, DW_AT_external + .dwattr $C$DW$185, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$185, DW_AT_TI_begin_line(0x1f7) + .dwattr $C$DW$185, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$185, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$185, DW_AT_decl_line(0x1f7) + .dwattr $C$DW$185, DW_AT_decl_column(0x06) + .dwattr $C$DW$185, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 504,column 1,is_stmt,address EK_TM4C123GXL_initSPI,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initSPI +;---------------------------------------------------------------------- +; 503 | void EK_TM4C123GXL_initSPI(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initSPI * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initSPI: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 506,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 506 | SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); +;---------------------------------------------------------------------- + LDR A1, $C$CON31 ; [DPU_V7M3_PIPE] |506| +$C$DW$186 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$186, DW_AT_low_pc(0x00) + .dwattr $C$DW$186, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$186, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |506| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |506| + .dwpsn file "../EK_TM4C123GXL.c",line 509,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 509 | GPIOPinConfigure(GPIO_PA2_SSI0CLK); +;---------------------------------------------------------------------- + MOV A1, #2050 ; [DPU_V7M3_PIPE] |509| +$C$DW$187 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$187, DW_AT_low_pc(0x00) + .dwattr $C$DW$187, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$187, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |509| + ; CALL OCCURS {GPIOPinConfigure } ; [] |509| + .dwpsn file "../EK_TM4C123GXL.c",line 510,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 510 | GPIOPinConfigure(GPIO_PA3_SSI0FSS); +;---------------------------------------------------------------------- + MOV A1, #3074 ; [DPU_V7M3_PIPE] |510| +$C$DW$188 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$188, DW_AT_low_pc(0x00) + .dwattr $C$DW$188, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$188, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |510| + ; CALL OCCURS {GPIOPinConfigure } ; [] |510| + .dwpsn file "../EK_TM4C123GXL.c",line 511,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 511 | GPIOPinConfigure(GPIO_PA4_SSI0RX); +;---------------------------------------------------------------------- + MOV A1, #4098 ; [DPU_V7M3_PIPE] |511| +$C$DW$189 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$189, DW_AT_low_pc(0x00) + .dwattr $C$DW$189, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$189, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |511| + ; CALL OCCURS {GPIOPinConfigure } ; [] |511| + .dwpsn file "../EK_TM4C123GXL.c",line 512,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 512 | GPIOPinConfigure(GPIO_PA5_SSI0TX); +;---------------------------------------------------------------------- + MOV A1, #5122 ; [DPU_V7M3_PIPE] |512| +$C$DW$190 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$190, DW_AT_low_pc(0x00) + .dwattr $C$DW$190, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$190, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |512| + ; CALL OCCURS {GPIOPinConfigure } ; [] |512| + .dwpsn file "../EK_TM4C123GXL.c",line 514,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 514 | GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | +; 515 | GPIO_PIN_4 | GPIO_PIN_5); +;---------------------------------------------------------------------- + MOV A1, #1073758208 ; [DPU_V7M3_PIPE] |514| + MOVS A2, #60 ; [DPU_V7M3_PIPE] |514| +$C$DW$191 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$191, DW_AT_low_pc(0x00) + .dwattr $C$DW$191, DW_AT_name("GPIOPinTypeSSI") + .dwattr $C$DW$191, DW_AT_TI_call + + BL GPIOPinTypeSSI ; [DPU_V7M3_PIPE] |514| + ; CALL OCCURS {GPIOPinTypeSSI } ; [] |514| + .dwpsn file "../EK_TM4C123GXL.c",line 518,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 518 | SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); +;---------------------------------------------------------------------- + LDR A1, $C$CON32 ; [DPU_V7M3_PIPE] |518| +$C$DW$192 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$192, DW_AT_low_pc(0x00) + .dwattr $C$DW$192, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$192, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |518| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |518| + .dwpsn file "../EK_TM4C123GXL.c",line 520,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 520 | GPIOPinConfigure(GPIO_PB4_SSI2CLK); +;---------------------------------------------------------------------- + LDR A1, $C$CON33 ; [DPU_V7M3_PIPE] |520| +$C$DW$193 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$193, DW_AT_low_pc(0x00) + .dwattr $C$DW$193, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$193, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |520| + ; CALL OCCURS {GPIOPinConfigure } ; [] |520| + .dwpsn file "../EK_TM4C123GXL.c",line 521,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 521 | GPIOPinConfigure(GPIO_PB5_SSI2FSS); +;---------------------------------------------------------------------- + LDR A1, $C$CON34 ; [DPU_V7M3_PIPE] |521| +$C$DW$194 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$194, DW_AT_low_pc(0x00) + .dwattr $C$DW$194, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$194, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |521| + ; CALL OCCURS {GPIOPinConfigure } ; [] |521| + .dwpsn file "../EK_TM4C123GXL.c",line 522,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 522 | GPIOPinConfigure(GPIO_PB6_SSI2RX); +;---------------------------------------------------------------------- + LDR A1, $C$CON35 ; [DPU_V7M3_PIPE] |522| +$C$DW$195 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$195, DW_AT_low_pc(0x00) + .dwattr $C$DW$195, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$195, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |522| + ; CALL OCCURS {GPIOPinConfigure } ; [] |522| +;* --------------------------------------------------------------------------* + .dwpsn file "../EK_TM4C123GXL.c",line 523,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 523 | GPIOPinConfigure(GPIO_PB7_SSI2TX); +;---------------------------------------------------------------------- + LDR A1, $C$CON36 ; [DPU_V7M3_PIPE] |523| +$C$DW$196 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$196, DW_AT_low_pc(0x00) + .dwattr $C$DW$196, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$196, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |523| + ; CALL OCCURS {GPIOPinConfigure } ; [] |523| + .dwpsn file "../EK_TM4C123GXL.c",line 525,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 525 | GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_5 | +; 526 | GPIO_PIN_6 | GPIO_PIN_7); +;---------------------------------------------------------------------- + LDR A1, $C$CON37 ; [DPU_V7M3_PIPE] |525| + MOVS A2, #240 ; [DPU_V7M3_PIPE] |525| +$C$DW$197 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$197, DW_AT_low_pc(0x00) + .dwattr $C$DW$197, DW_AT_name("GPIOPinTypeSSI") + .dwattr $C$DW$197, DW_AT_TI_call + + BL GPIOPinTypeSSI ; [DPU_V7M3_PIPE] |525| + ; CALL OCCURS {GPIOPinTypeSSI } ; [] |525| + .dwpsn file "../EK_TM4C123GXL.c",line 535,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 535 | SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); +;---------------------------------------------------------------------- + LDR A1, $C$CON38 ; [DPU_V7M3_PIPE] |535| +$C$DW$198 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$198, DW_AT_low_pc(0x00) + .dwattr $C$DW$198, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$198, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |535| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |535| + .dwpsn file "../EK_TM4C123GXL.c",line 537,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 537 | GPIOPinConfigure(GPIO_PD0_SSI3CLK); +;---------------------------------------------------------------------- + LDR A1, $C$CON39 ; [DPU_V7M3_PIPE] |537| +$C$DW$199 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$199, DW_AT_low_pc(0x00) + .dwattr $C$DW$199, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$199, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |537| + ; CALL OCCURS {GPIOPinConfigure } ; [] |537| + .dwpsn file "../EK_TM4C123GXL.c",line 538,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 538 | GPIOPinConfigure(GPIO_PD1_SSI3FSS); +;---------------------------------------------------------------------- + LDR A1, $C$CON40 ; [DPU_V7M3_PIPE] |538| +$C$DW$200 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$200, DW_AT_low_pc(0x00) + .dwattr $C$DW$200, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$200, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |538| + ; CALL OCCURS {GPIOPinConfigure } ; [] |538| + .dwpsn file "../EK_TM4C123GXL.c",line 539,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 539 | GPIOPinConfigure(GPIO_PD2_SSI3RX); +;---------------------------------------------------------------------- + LDR A1, $C$CON41 ; [DPU_V7M3_PIPE] |539| +$C$DW$201 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$201, DW_AT_low_pc(0x00) + .dwattr $C$DW$201, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$201, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |539| + ; CALL OCCURS {GPIOPinConfigure } ; [] |539| + .dwpsn file "../EK_TM4C123GXL.c",line 540,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 540 | GPIOPinConfigure(GPIO_PD3_SSI3TX); +;---------------------------------------------------------------------- + LDR A1, $C$CON42 ; [DPU_V7M3_PIPE] |540| +$C$DW$202 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$202, DW_AT_low_pc(0x00) + .dwattr $C$DW$202, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$202, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |540| + ; CALL OCCURS {GPIOPinConfigure } ; [] |540| + .dwpsn file "../EK_TM4C123GXL.c",line 542,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 542 | GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | +; 543 | GPIO_PIN_2 | GPIO_PIN_3); +;---------------------------------------------------------------------- + LDR A1, $C$CON43 ; [DPU_V7M3_PIPE] |542| + MOVS A2, #15 ; [DPU_V7M3_PIPE] |542| +$C$DW$203 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$203, DW_AT_low_pc(0x00) + .dwattr $C$DW$203, DW_AT_name("GPIOPinTypeSSI") + .dwattr $C$DW$203, DW_AT_TI_call + + BL GPIOPinTypeSSI ; [DPU_V7M3_PIPE] |542| + ; CALL OCCURS {GPIOPinTypeSSI } ; [] |542| + .dwpsn file "../EK_TM4C123GXL.c",line 545,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 545 | EK_TM4C123GXL_initDMA(); +;---------------------------------------------------------------------- +$C$DW$204 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$204, DW_AT_low_pc(0x00) + .dwattr $C$DW$204, DW_AT_name("EK_TM4C123GXL_initDMA") + .dwattr $C$DW$204, DW_AT_TI_call + + BL EK_TM4C123GXL_initDMA ; [DPU_V7M3_PIPE] |545| + ; CALL OCCURS {EK_TM4C123GXL_initDMA } ; [] |545| + .dwpsn file "../EK_TM4C123GXL.c",line 546,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 546 | SPI_init(); +;---------------------------------------------------------------------- +$C$DW$205 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$205, DW_AT_low_pc(0x00) + .dwattr $C$DW$205, DW_AT_name("SPI_init") + .dwattr $C$DW$205, DW_AT_TI_call + + BL SPI_init ; [DPU_V7M3_PIPE] |546| + ; CALL OCCURS {SPI_init } ; [] |546| + .dwpsn file "../EK_TM4C123GXL.c",line 547,column 1,is_stmt,isa 1 +$C$DW$206 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$206, DW_AT_low_pc(0x00) + .dwattr $C$DW$206, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$185, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$185, DW_AT_TI_end_line(0x223) + .dwattr $C$DW$185, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$185 + + .sect ".text:EK_TM4C123GXL_initUART" + .clink + .thumbfunc EK_TM4C123GXL_initUART + .thumb + .global EK_TM4C123GXL_initUART + +$C$DW$207 .dwtag DW_TAG_subprogram + .dwattr $C$DW$207, DW_AT_name("EK_TM4C123GXL_initUART") + .dwattr $C$DW$207, DW_AT_low_pc(EK_TM4C123GXL_initUART) + .dwattr $C$DW$207, DW_AT_high_pc(0x00) + .dwattr $C$DW$207, DW_AT_TI_symbol_name("EK_TM4C123GXL_initUART") + .dwattr $C$DW$207, DW_AT_external + .dwattr $C$DW$207, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$207, DW_AT_TI_begin_line(0x265) + .dwattr $C$DW$207, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$207, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$207, DW_AT_decl_line(0x265) + .dwattr $C$DW$207, DW_AT_decl_column(0x06) + .dwattr $C$DW$207, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 614,column 1,is_stmt,address EK_TM4C123GXL_initUART,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initUART +;---------------------------------------------------------------------- +; 613 | void EK_TM4C123GXL_initUART(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initUART * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initUART: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 616,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 616 | SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); +;---------------------------------------------------------------------- + LDR A1, $C$CON44 ; [DPU_V7M3_PIPE] |616| +$C$DW$208 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$208, DW_AT_low_pc(0x00) + .dwattr $C$DW$208, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$208, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |616| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |616| + .dwpsn file "../EK_TM4C123GXL.c",line 617,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 617 | GPIOPinConfigure(GPIO_PA0_U0RX); +;---------------------------------------------------------------------- + MOVS A1, #1 ; [DPU_V7M3_PIPE] |617| +$C$DW$209 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$209, DW_AT_low_pc(0x00) + .dwattr $C$DW$209, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$209, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |617| + ; CALL OCCURS {GPIOPinConfigure } ; [] |617| + .dwpsn file "../EK_TM4C123GXL.c",line 618,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 618 | GPIOPinConfigure(GPIO_PA1_U0TX); +;---------------------------------------------------------------------- + MOV A1, #1025 ; [DPU_V7M3_PIPE] |618| +$C$DW$210 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$210, DW_AT_low_pc(0x00) + .dwattr $C$DW$210, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$210, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |618| + ; CALL OCCURS {GPIOPinConfigure } ; [] |618| + .dwpsn file "../EK_TM4C123GXL.c",line 619,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 619 | GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); +; 622 | #if TI_DRIVERS_UART_DMA +; 623 | EK_TM4C123GXL_initDMA(); +; 624 | #endif +;---------------------------------------------------------------------- + MOV A1, #1073758208 ; [DPU_V7M3_PIPE] |619| + MOVS A2, #3 ; [DPU_V7M3_PIPE] |619| +$C$DW$211 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$211, DW_AT_low_pc(0x00) + .dwattr $C$DW$211, DW_AT_name("GPIOPinTypeUART") + .dwattr $C$DW$211, DW_AT_TI_call + + BL GPIOPinTypeUART ; [DPU_V7M3_PIPE] |619| + ; CALL OCCURS {GPIOPinTypeUART } ; [] |619| + .dwpsn file "../EK_TM4C123GXL.c",line 625,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 625 | UART_init(); +;---------------------------------------------------------------------- +$C$DW$212 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$212, DW_AT_low_pc(0x00) + .dwattr $C$DW$212, DW_AT_name("UART_init") + .dwattr $C$DW$212, DW_AT_TI_call + + BL UART_init ; [DPU_V7M3_PIPE] |625| + ; CALL OCCURS {UART_init } ; [] |625| + .dwpsn file "../EK_TM4C123GXL.c",line 626,column 1,is_stmt,isa 1 +$C$DW$213 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$213, DW_AT_low_pc(0x00) + .dwattr $C$DW$213, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$207, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$207, DW_AT_TI_end_line(0x272) + .dwattr $C$DW$207, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$207 + + .sect ".text:EK_TM4C123GXL_initUSB" + .clink + .thumbfunc EK_TM4C123GXL_initUSB + .thumb + .global EK_TM4C123GXL_initUSB + +$C$DW$214 .dwtag DW_TAG_subprogram + .dwattr $C$DW$214, DW_AT_name("EK_TM4C123GXL_initUSB") + .dwattr $C$DW$214, DW_AT_low_pc(EK_TM4C123GXL_initUSB) + .dwattr $C$DW$214, DW_AT_high_pc(0x00) + .dwattr $C$DW$214, DW_AT_TI_symbol_name("EK_TM4C123GXL_initUSB") + .dwattr $C$DW$214, DW_AT_external + .dwattr $C$DW$214, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$214, DW_AT_TI_begin_line(0x27b) + .dwattr $C$DW$214, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$214, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$214, DW_AT_decl_line(0x27b) + .dwattr $C$DW$214, DW_AT_decl_column(0x06) + .dwattr $C$DW$214, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 636,column 1,is_stmt,address EK_TM4C123GXL_initUSB,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initUSB +$C$DW$215 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$215, DW_AT_name("usbMode") + .dwattr $C$DW$215, DW_AT_TI_symbol_name("usbMode") + .dwattr $C$DW$215, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$215, DW_AT_location[DW_OP_reg0] + +;---------------------------------------------------------------------- +; 635 | void EK_TM4C123GXL_initUSB(EK_TM4C123GXL_USBMode usbMode) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initUSB * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 4 Auto + 4 Save = 8 byte * +;***************************************************************************** +EK_TM4C123GXL_initUSB: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 +$C$DW$216 .dwtag DW_TAG_variable + .dwattr $C$DW$216, DW_AT_name("usbMode") + .dwattr $C$DW$216, DW_AT_TI_symbol_name("usbMode") + .dwattr $C$DW$216, DW_AT_type(*$C$DW$T$994) + .dwattr $C$DW$216, DW_AT_location[DW_OP_breg13 0] + + STRB A1, [SP, #0] ; [DPU_V7M3_PIPE] |636| + .dwpsn file "../EK_TM4C123GXL.c",line 638,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 638 | SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); +;---------------------------------------------------------------------- + LDR A1, $C$CON45 ; [DPU_V7M3_PIPE] |638| +$C$DW$217 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$217, DW_AT_low_pc(0x00) + .dwattr $C$DW$217, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$217, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |638| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |638| + .dwpsn file "../EK_TM4C123GXL.c",line 639,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 639 | SysCtlUSBPLLEnable(); +;---------------------------------------------------------------------- +$C$DW$218 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$218, DW_AT_low_pc(0x00) + .dwattr $C$DW$218, DW_AT_name("SysCtlUSBPLLEnable") + .dwattr $C$DW$218, DW_AT_TI_call + + BL SysCtlUSBPLLEnable ; [DPU_V7M3_PIPE] |639| + ; CALL OCCURS {SysCtlUSBPLLEnable } ; [] |639| + .dwpsn file "../EK_TM4C123GXL.c",line 642,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 642 | GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); +;---------------------------------------------------------------------- + LDR A1, $C$CON46 ; [DPU_V7M3_PIPE] |642| + MOVS A2, #48 ; [DPU_V7M3_PIPE] |642| +$C$DW$219 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$219, DW_AT_low_pc(0x00) + .dwattr $C$DW$219, DW_AT_name("GPIOPinTypeUSBAnalog") + .dwattr $C$DW$219, DW_AT_TI_call + + BL GPIOPinTypeUSBAnalog ; [DPU_V7M3_PIPE] |642| + ; CALL OCCURS {GPIOPinTypeUSBAnalog } ; [] |642| + .dwpsn file "../EK_TM4C123GXL.c",line 644,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 644 | if (usbMode == EK_TM4C123GXL_USBHOST) { +;---------------------------------------------------------------------- + LDRB A1, [SP, #0] ; [DPU_V7M3_PIPE] |644| + CMP A1, #1 ; [DPU_V7M3_PIPE] |644| + BNE ||$C$L4|| ; [DPU_V7M3_PIPE] |644| + ; BRANCHCC OCCURS {||$C$L4||} ; [] |644| +;* --------------------------------------------------------------------------* + .dwpsn file "../EK_TM4C123GXL.c",line 645,column 9,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 645 | System_abort("USB host not supported\n"); +;---------------------------------------------------------------------- + ADR A1, $C$SL4 ; [DPU_V7M3_PIPE] |645| +$C$DW$220 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$220, DW_AT_low_pc(0x00) + .dwattr $C$DW$220, DW_AT_name("xdc_runtime_System_abort__E") + .dwattr $C$DW$220, DW_AT_TI_call + + BL xdc_runtime_System_abort__E ; [DPU_V7M3_PIPE] |645| + ; CALL OCCURS {xdc_runtime_System_abort__E } ; [] |645| + .dwpsn file "../EK_TM4C123GXL.c",line 647,column 1,is_stmt,isa 1 +;* --------------------------------------------------------------------------* +||$C$L4||: +$C$DW$221 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$221, DW_AT_low_pc(0x00) + .dwattr $C$DW$221, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$214, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$214, DW_AT_TI_end_line(0x287) + .dwattr $C$DW$214, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$214 + + .sect ".text:EK_TM4C123GXL_initWatchdog" + .clink + .thumbfunc EK_TM4C123GXL_initWatchdog + .thumb + .global EK_TM4C123GXL_initWatchdog + +$C$DW$222 .dwtag DW_TAG_subprogram + .dwattr $C$DW$222, DW_AT_name("EK_TM4C123GXL_initWatchdog") + .dwattr $C$DW$222, DW_AT_low_pc(EK_TM4C123GXL_initWatchdog) + .dwattr $C$DW$222, DW_AT_high_pc(0x00) + .dwattr $C$DW$222, DW_AT_TI_symbol_name("EK_TM4C123GXL_initWatchdog") + .dwattr $C$DW$222, DW_AT_external + .dwattr $C$DW$222, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$222, DW_AT_TI_begin_line(0x2b7) + .dwattr $C$DW$222, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$222, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$222, DW_AT_decl_line(0x2b7) + .dwattr $C$DW$222, DW_AT_decl_column(0x06) + .dwattr $C$DW$222, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 696,column 1,is_stmt,address EK_TM4C123GXL_initWatchdog,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initWatchdog +;---------------------------------------------------------------------- +; 695 | void EK_TM4C123GXL_initWatchdog(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initWatchdog * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initWatchdog: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 698,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 698 | SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0); +;---------------------------------------------------------------------- + MOV A1, #-268435456 ; [DPU_V7M3_PIPE] |698| +$C$DW$223 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$223, DW_AT_low_pc(0x00) + .dwattr $C$DW$223, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$223, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |698| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |698| + .dwpsn file "../EK_TM4C123GXL.c",line 700,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 700 | Watchdog_init(); +;---------------------------------------------------------------------- +$C$DW$224 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$224, DW_AT_low_pc(0x00) + .dwattr $C$DW$224, DW_AT_name("Watchdog_init") + .dwattr $C$DW$224, DW_AT_TI_call + + BL Watchdog_init ; [DPU_V7M3_PIPE] |700| + ; CALL OCCURS {Watchdog_init } ; [] |700| + .dwpsn file "../EK_TM4C123GXL.c",line 701,column 1,is_stmt,isa 1 +$C$DW$225 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$225, DW_AT_low_pc(0x00) + .dwattr $C$DW$225, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$222, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$222, DW_AT_TI_end_line(0x2bd) + .dwattr $C$DW$222, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$222 + + .sect ".text:EK_TM4C123GXL_initWiFi" + .clink + .thumbfunc EK_TM4C123GXL_initWiFi + .thumb + .global EK_TM4C123GXL_initWiFi + +$C$DW$226 .dwtag DW_TAG_subprogram + .dwattr $C$DW$226, DW_AT_name("EK_TM4C123GXL_initWiFi") + .dwattr $C$DW$226, DW_AT_low_pc(EK_TM4C123GXL_initWiFi) + .dwattr $C$DW$226, DW_AT_high_pc(0x00) + .dwattr $C$DW$226, DW_AT_TI_symbol_name("EK_TM4C123GXL_initWiFi") + .dwattr $C$DW$226, DW_AT_external + .dwattr $C$DW$226, DW_AT_TI_begin_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$226, DW_AT_TI_begin_line(0x2e7) + .dwattr $C$DW$226, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$226, DW_AT_decl_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$226, DW_AT_decl_line(0x2e7) + .dwattr $C$DW$226, DW_AT_decl_column(0x06) + .dwattr $C$DW$226, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../EK_TM4C123GXL.c",line 744,column 1,is_stmt,address EK_TM4C123GXL_initWiFi,isa 1 + + .dwfde $C$DW$CIE, EK_TM4C123GXL_initWiFi +;---------------------------------------------------------------------- +; 743 | void EK_TM4C123GXL_initWiFi(void) +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: EK_TM4C123GXL_initWiFi * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +EK_TM4C123GXL_initWiFi: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../EK_TM4C123GXL.c",line 746,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 746 | GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_4); +;---------------------------------------------------------------------- + LDR A1, $C$CON47 ; [DPU_V7M3_PIPE] |746| + MOVS A2, #17 ; [DPU_V7M3_PIPE] |746| +$C$DW$227 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$227, DW_AT_low_pc(0x00) + .dwattr $C$DW$227, DW_AT_name("GPIOPinTypeGPIOOutput") + .dwattr $C$DW$227, DW_AT_TI_call + + BL GPIOPinTypeGPIOOutput ; [DPU_V7M3_PIPE] |746| + ; CALL OCCURS {GPIOPinTypeGPIOOutput } ; [] |746| + .dwpsn file "../EK_TM4C123GXL.c",line 747,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 747 | GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, GPIO_PIN_0); +;---------------------------------------------------------------------- + LDR A1, $C$CON47 ; [DPU_V7M3_PIPE] |747| + MOVS A2, #1 ; [DPU_V7M3_PIPE] |747| + MOVS A3, #1 ; [DPU_V7M3_PIPE] |747| +$C$DW$228 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$228, DW_AT_low_pc(0x00) + .dwattr $C$DW$228, DW_AT_name("GPIOPinWrite") + .dwattr $C$DW$228, DW_AT_TI_call + + BL GPIOPinWrite ; [DPU_V7M3_PIPE] |747| + ; CALL OCCURS {GPIOPinWrite } ; [] |747| + .dwpsn file "../EK_TM4C123GXL.c",line 748,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 748 | GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_4, 0); +;---------------------------------------------------------------------- + LDR A1, $C$CON47 ; [DPU_V7M3_PIPE] |748| + MOVS A2, #16 ; [DPU_V7M3_PIPE] |748| + MOVS A3, #0 ; [DPU_V7M3_PIPE] |748| +$C$DW$229 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$229, DW_AT_low_pc(0x00) + .dwattr $C$DW$229, DW_AT_name("GPIOPinWrite") + .dwattr $C$DW$229, DW_AT_TI_call + + BL GPIOPinWrite ; [DPU_V7M3_PIPE] |748| + ; CALL OCCURS {GPIOPinWrite } ; [] |748| + .dwpsn file "../EK_TM4C123GXL.c",line 751,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 751 | SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); +;---------------------------------------------------------------------- + LDR A1, $C$CON48 ; [DPU_V7M3_PIPE] |751| +$C$DW$230 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$230, DW_AT_low_pc(0x00) + .dwattr $C$DW$230, DW_AT_name("SysCtlPeripheralEnable") + .dwattr $C$DW$230, DW_AT_TI_call + + BL SysCtlPeripheralEnable ; [DPU_V7M3_PIPE] |751| + ; CALL OCCURS {SysCtlPeripheralEnable } ; [] |751| + .dwpsn file "../EK_TM4C123GXL.c",line 752,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 752 | GPIOPinConfigure(GPIO_PB4_SSI2CLK); +;---------------------------------------------------------------------- + LDR A1, $C$CON49 ; [DPU_V7M3_PIPE] |752| +$C$DW$231 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$231, DW_AT_low_pc(0x00) + .dwattr $C$DW$231, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$231, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |752| + ; CALL OCCURS {GPIOPinConfigure } ; [] |752| + .dwpsn file "../EK_TM4C123GXL.c",line 753,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 753 | GPIOPinConfigure(GPIO_PB6_SSI2RX); +;---------------------------------------------------------------------- + LDR A1, $C$CON50 ; [DPU_V7M3_PIPE] |753| +$C$DW$232 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$232, DW_AT_low_pc(0x00) + .dwattr $C$DW$232, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$232, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |753| + ; CALL OCCURS {GPIOPinConfigure } ; [] |753| + .dwpsn file "../EK_TM4C123GXL.c",line 754,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 754 | GPIOPinConfigure(GPIO_PB7_SSI2TX); +;---------------------------------------------------------------------- + LDR A1, $C$CON51 ; [DPU_V7M3_PIPE] |754| +$C$DW$233 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$233, DW_AT_low_pc(0x00) + .dwattr $C$DW$233, DW_AT_name("GPIOPinConfigure") + .dwattr $C$DW$233, DW_AT_TI_call + + BL GPIOPinConfigure ; [DPU_V7M3_PIPE] |754| + ; CALL OCCURS {GPIOPinConfigure } ; [] |754| +;* --------------------------------------------------------------------------* + .dwpsn file "../EK_TM4C123GXL.c",line 755,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 755 | GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7); +;---------------------------------------------------------------------- + LDR A1, $C$CON52 ; [DPU_V7M3_PIPE] |755| + MOVS A2, #208 ; [DPU_V7M3_PIPE] |755| +$C$DW$234 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$234, DW_AT_low_pc(0x00) + .dwattr $C$DW$234, DW_AT_name("GPIOPinTypeSSI") + .dwattr $C$DW$234, DW_AT_TI_call + + BL GPIOPinTypeSSI ; [DPU_V7M3_PIPE] |755| + ; CALL OCCURS {GPIOPinTypeSSI } ; [] |755| + .dwpsn file "../EK_TM4C123GXL.c",line 758,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 758 | GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_2); +;---------------------------------------------------------------------- + LDR A1, $C$CON52 ; [DPU_V7M3_PIPE] |758| + MOVS A2, #4 ; [DPU_V7M3_PIPE] |758| +$C$DW$235 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$235, DW_AT_low_pc(0x00) + .dwattr $C$DW$235, DW_AT_name("GPIOPinTypeGPIOInput") + .dwattr $C$DW$235, DW_AT_TI_call + + BL GPIOPinTypeGPIOInput ; [DPU_V7M3_PIPE] |758| + ; CALL OCCURS {GPIOPinTypeGPIOInput } ; [] |758| + .dwpsn file "../EK_TM4C123GXL.c",line 759,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 759 | GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, +; 760 | GPIO_PIN_TYPE_STD_WPD); +;---------------------------------------------------------------------- + LDR A1, $C$CON52 ; [DPU_V7M3_PIPE] |759| + MOVS A2, #4 ; [DPU_V7M3_PIPE] |759| + MOVS A3, #1 ; [DPU_V7M3_PIPE] |759| + MOVS A4, #12 ; [DPU_V7M3_PIPE] |759| +$C$DW$236 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$236, DW_AT_low_pc(0x00) + .dwattr $C$DW$236, DW_AT_name("GPIOPadConfigSet") + .dwattr $C$DW$236, DW_AT_TI_call + + BL GPIOPadConfigSet ; [DPU_V7M3_PIPE] |759| + ; CALL OCCURS {GPIOPadConfigSet } ; [] |759| + .dwpsn file "../EK_TM4C123GXL.c",line 761,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 761 | GPIOIntTypeSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_RISING_EDGE); +;---------------------------------------------------------------------- + LDR A1, $C$CON52 ; [DPU_V7M3_PIPE] |761| + MOVS A2, #4 ; [DPU_V7M3_PIPE] |761| + MOVS A3, #4 ; [DPU_V7M3_PIPE] |761| +$C$DW$237 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$237, DW_AT_low_pc(0x00) + .dwattr $C$DW$237, DW_AT_name("GPIOIntTypeSet") + .dwattr $C$DW$237, DW_AT_TI_call + + BL GPIOIntTypeSet ; [DPU_V7M3_PIPE] |761| + ; CALL OCCURS {GPIOIntTypeSet } ; [] |761| + .dwpsn file "../EK_TM4C123GXL.c",line 763,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 763 | SPI_init(); +;---------------------------------------------------------------------- +$C$DW$238 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$238, DW_AT_low_pc(0x00) + .dwattr $C$DW$238, DW_AT_name("SPI_init") + .dwattr $C$DW$238, DW_AT_TI_call + + BL SPI_init ; [DPU_V7M3_PIPE] |763| + ; CALL OCCURS {SPI_init } ; [] |763| + .dwpsn file "../EK_TM4C123GXL.c",line 764,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 764 | EK_TM4C123GXL_initDMA(); +;---------------------------------------------------------------------- +$C$DW$239 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$239, DW_AT_low_pc(0x00) + .dwattr $C$DW$239, DW_AT_name("EK_TM4C123GXL_initDMA") + .dwattr $C$DW$239, DW_AT_TI_call + + BL EK_TM4C123GXL_initDMA ; [DPU_V7M3_PIPE] |764| + ; CALL OCCURS {EK_TM4C123GXL_initDMA } ; [] |764| + .dwpsn file "../EK_TM4C123GXL.c",line 766,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 766 | WiFi_init(); +;---------------------------------------------------------------------- +$C$DW$240 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$240, DW_AT_low_pc(0x00) + .dwattr $C$DW$240, DW_AT_name("WiFi_init") + .dwattr $C$DW$240, DW_AT_TI_call + + BL WiFi_init ; [DPU_V7M3_PIPE] |766| + ; CALL OCCURS {WiFi_init } ; [] |766| + .dwpsn file "../EK_TM4C123GXL.c",line 767,column 1,is_stmt,isa 1 +$C$DW$241 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$241, DW_AT_low_pc(0x00) + .dwattr $C$DW$241, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$226, DW_AT_TI_end_file("../EK_TM4C123GXL.c") + .dwattr $C$DW$226, DW_AT_TI_end_line(0x2ff) + .dwattr $C$DW$226, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$226 + +;****************************************************************************** +;* STRINGS * +;****************************************************************************** + .sect ".text:dmaErrorHwi" + .align 4 +||$C$SL1||: .string "DMA error code: %d",10,0 + .align 4 +||$C$SL2||: .string "DMA error!!",0 +;****************************************************************************** +;* STRINGS * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initDMA" + .align 4 +||$C$SL3||: .string "Couldn't construct DMA error hwi",0 +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initDMA" + .align 4 +||$C$CON1||: .bits dmaInitialized,32 + .align 4 +||$C$CON2||: .bits dmaHwiStruct,32 + .align 4 +||$C$CON3||: .bits dmaErrorHwi,32 + .align 4 +||$C$CON4||: .bits 0xf0000c00,32 + + .align 4 +||$C$CON5||: .bits dmaControlTable,32 +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initGeneral" + .align 4 +||$C$CON6||: .bits 0xf0000800,32 + + .align 4 +||$C$CON7||: .bits 0xf0000801,32 + + .align 4 +||$C$CON8||: .bits 0xf0000802,32 + + .align 4 +||$C$CON9||: .bits 0xf0000803,32 + + .align 4 +||$C$CON10||: .bits 0xf0000804,32 + + .align 4 +||$C$CON11||: .bits 0xf0000805,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initGPIO" + .align 4 +||$C$CON12||: .bits 0x40025520,32 + + .align 4 +||$C$CON13||: .bits 0x4c4f434b,32 + + .align 4 +||$C$CON14||: .bits 0x40025524,32 + + .align 4 +||$C$CON15||: .bits 0x40025000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initI2C" + .align 4 +||$C$CON16||: .bits 0xf0002001,32 + + .align 4 +||$C$CON17||: .bits 0xf0002003,32 + + .align 4 +||$C$CON18||: .bits 0x30403,32 + + .align 4 +||$C$CON19||: .bits 0x40007000,32 + + .align 4 +||$C$CON20||: .bits 0x40005000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initPWM" + .align 4 +||$C$CON21||: .bits 0xf0004001,32 + + .align 4 +||$C$CON22||: .bits 0x50805,32 + + .align 4 +||$C$CON23||: .bits 0x50c05,32 + + .align 4 +||$C$CON24||: .bits 0x40025000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initSDSPI" + .align 4 +||$C$CON25||: .bits 0xf0001c02,32 + + .align 4 +||$C$CON26||: .bits 0x40005000,32 + + .align 4 +||$C$CON27||: .bits 0x11002,32 + + .align 4 +||$C$CON28||: .bits 0x11802,32 + + .align 4 +||$C$CON29||: .bits 0x11c02,32 + + .align 4 +||$C$CON30||: .bits 0x40007000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initSPI" + .align 4 +||$C$CON31||: .bits 0xf0001c00,32 + + .align 4 +||$C$CON32||: .bits 0xf0001c02,32 + + .align 4 +||$C$CON33||: .bits 0x11002,32 + + .align 4 +||$C$CON34||: .bits 0x11402,32 + + .align 4 +||$C$CON35||: .bits 0x11802,32 + + .align 4 +||$C$CON36||: .bits 0x11c02,32 + + .align 4 +||$C$CON37||: .bits 0x40005000,32 + + .align 4 +||$C$CON38||: .bits 0xf0001c03,32 + + .align 4 +||$C$CON39||: .bits 0x30001,32 + + .align 4 +||$C$CON40||: .bits 0x30401,32 + + .align 4 +||$C$CON41||: .bits 0x30801,32 + + .align 4 +||$C$CON42||: .bits 0x30c01,32 + + .align 4 +||$C$CON43||: .bits 0x40007000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initUART" + .align 4 +||$C$CON44||: .bits 0xf0001800,32 + +;****************************************************************************** +;* STRINGS * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initUSB" + .align 4 +||$C$SL4||: .string "USB host not supported",10,0 +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initUSB" + .align 4 +||$C$CON45||: .bits 0xf0002800,32 + + .align 4 +||$C$CON46||: .bits 0x40007000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:EK_TM4C123GXL_initWiFi" + .align 4 +||$C$CON47||: .bits 0x40024000,32 + + .align 4 +||$C$CON48||: .bits 0xf0001c02,32 + + .align 4 +||$C$CON49||: .bits 0x11002,32 + + .align 4 +||$C$CON50||: .bits 0x11802,32 + + .align 4 +||$C$CON51||: .bits 0x11c02,32 + + .align 4 +||$C$CON52||: .bits 0x40005000,32 + +;***************************************************************************** +;* UNDEFINED EXTERNAL REFERENCES * +;***************************************************************************** + .global I2CTiva_fxnTable + .global PWMTiva_fxnTable + .global SDSPITiva_fxnTable + .global SPITivaDMA_fxnTable + .global UARTTiva_fxnTable + .global WatchdogTiva_fxnTable + .global WiFiCC3100_fxnTable + .global ti_sysbios_family_arm_m3_Hwi_Params__init__S + .global xdc_runtime_System_printf__E + .global uDMAErrorStatusGet + .global uDMAErrorStatusClear + .global xdc_runtime_System_abort__E + .global xdc_runtime_Error_init__E + .global ti_sysbios_family_arm_m3_Hwi_construct + .global xdc_runtime_Error_check__E + .global SysCtlPeripheralEnable + .global uDMAEnable + .global uDMAControlBaseSet + .global GPIOPinTypeGPIOInput + .global GPIO_init + .global GPIOPinConfigure + .global GPIOPinTypeI2CSCL + .global GPIOPinTypeI2C + .global I2C_init + .global GPIOPinTypePWM + .global PWM_init + .global GPIOPadConfigSet + .global SDSPI_init + .global GPIOPinTypeSSI + .global SPI_init + .global GPIOPinTypeUART + .global UART_init + .global SysCtlUSBPLLEnable + .global GPIOPinTypeUSBAnalog + .global Watchdog_init + .global GPIOPinTypeGPIOOutput + .global GPIOPinWrite + .global GPIOIntTypeSet + .global WiFi_init + .global uDMAChannelAssign + +;****************************************************************************** +;* BUILD ATTRIBUTES * +;****************************************************************************** + .battr "aeabi", Tag_File, 1, Tag_ABI_PCS_wchar_t(2) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_rounding(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_denormal(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_exceptions(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_number_model(1) + .battr "aeabi", Tag_File, 1, Tag_ABI_enum_size(1) + .battr "aeabi", Tag_File, 1, Tag_ABI_optimization_goals(5) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_optimization_goals(0) + .battr "TI", Tag_File, 1, Tag_Bitfield_layout(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_VFP_args(3) + .battr "TI", Tag_File, 1, Tag_FP_interface(1) + +;****************************************************************************** +;* TYPE INFORMATION * +;****************************************************************************** + +$C$DW$T$174 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$174, DW_AT_byte_size(0x01) +$C$DW$242 .dwtag DW_TAG_enumerator + .dwattr $C$DW$242, DW_AT_name("RES_OK") + .dwattr $C$DW$242, DW_AT_const_value(0x00) + .dwattr $C$DW$242, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$242, DW_AT_decl_line(0x17) + .dwattr $C$DW$242, DW_AT_decl_column(0x02) + +$C$DW$243 .dwtag DW_TAG_enumerator + .dwattr $C$DW$243, DW_AT_name("RES_ERROR") + .dwattr $C$DW$243, DW_AT_const_value(0x01) + .dwattr $C$DW$243, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$243, DW_AT_decl_line(0x18) + .dwattr $C$DW$243, DW_AT_decl_column(0x02) + +$C$DW$244 .dwtag DW_TAG_enumerator + .dwattr $C$DW$244, DW_AT_name("RES_WRPRT") + .dwattr $C$DW$244, DW_AT_const_value(0x02) + .dwattr $C$DW$244, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$244, DW_AT_decl_line(0x19) + .dwattr $C$DW$244, DW_AT_decl_column(0x02) + +$C$DW$245 .dwtag DW_TAG_enumerator + .dwattr $C$DW$245, DW_AT_name("RES_NOTRDY") + .dwattr $C$DW$245, DW_AT_const_value(0x03) + .dwattr $C$DW$245, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$245, DW_AT_decl_line(0x1a) + .dwattr $C$DW$245, DW_AT_decl_column(0x02) + +$C$DW$246 .dwtag DW_TAG_enumerator + .dwattr $C$DW$246, DW_AT_name("RES_PARERR") + .dwattr $C$DW$246, DW_AT_const_value(0x04) + .dwattr $C$DW$246, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$246, DW_AT_decl_line(0x1b) + .dwattr $C$DW$246, DW_AT_decl_column(0x02) + + .dwattr $C$DW$T$174, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$T$174, DW_AT_decl_line(0x16) + .dwattr $C$DW$T$174, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$174 + +$C$DW$T$175 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$175, DW_AT_name("DRESULT") + .dwattr $C$DW$T$175, DW_AT_type(*$C$DW$T$174) + .dwattr $C$DW$T$175, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$175, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$T$175, DW_AT_decl_line(0x1c) + .dwattr $C$DW$T$175, DW_AT_decl_column(0x03) + + +$C$DW$T$177 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$177, DW_AT_type(*$C$DW$T$175) + .dwattr $C$DW$T$177, DW_AT_language(DW_LANG_C) +$C$DW$247 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$247, DW_AT_type(*$C$DW$T$136) + +$C$DW$248 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$248, DW_AT_type(*$C$DW$T$164) + +$C$DW$249 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$249, DW_AT_type(*$C$DW$T$138) + +$C$DW$250 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$250, DW_AT_type(*$C$DW$T$176) + + .dwendtag $C$DW$T$177 + +$C$DW$T$178 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$178, DW_AT_type(*$C$DW$T$177) + .dwattr $C$DW$T$178, DW_AT_address_class(0x20) + + +$C$DW$T$181 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$181, DW_AT_type(*$C$DW$T$175) + .dwattr $C$DW$T$181, DW_AT_language(DW_LANG_C) +$C$DW$251 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$251, DW_AT_type(*$C$DW$T$136) + +$C$DW$252 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$252, DW_AT_type(*$C$DW$T$180) + +$C$DW$253 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$253, DW_AT_type(*$C$DW$T$138) + +$C$DW$254 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$254, DW_AT_type(*$C$DW$T$176) + + .dwendtag $C$DW$T$181 + +$C$DW$T$182 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$182, DW_AT_type(*$C$DW$T$181) + .dwattr $C$DW$T$182, DW_AT_address_class(0x20) + + +$C$DW$T$183 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$183, DW_AT_type(*$C$DW$T$175) + .dwattr $C$DW$T$183, DW_AT_language(DW_LANG_C) +$C$DW$255 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$255, DW_AT_type(*$C$DW$T$136) + +$C$DW$256 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$256, DW_AT_type(*$C$DW$T$136) + +$C$DW$257 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$257, DW_AT_type(*$C$DW$T$3) + + .dwendtag $C$DW$T$183 + +$C$DW$T$184 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$184, DW_AT_type(*$C$DW$T$183) + .dwattr $C$DW$T$184, DW_AT_address_class(0x20) + + +$C$DW$T$961 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$961, DW_AT_byte_size(0x01) +$C$DW$258 .dwtag DW_TAG_enumerator + .dwattr $C$DW$258, DW_AT_name("FR_OK") + .dwattr $C$DW$258, DW_AT_const_value(0x00) + .dwattr $C$DW$258, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$258, DW_AT_decl_line(0xb9) + .dwattr $C$DW$258, DW_AT_decl_column(0x02) + +$C$DW$259 .dwtag DW_TAG_enumerator + .dwattr $C$DW$259, DW_AT_name("FR_DISK_ERR") + .dwattr $C$DW$259, DW_AT_const_value(0x01) + .dwattr $C$DW$259, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$259, DW_AT_decl_line(0xba) + .dwattr $C$DW$259, DW_AT_decl_column(0x02) + +$C$DW$260 .dwtag DW_TAG_enumerator + .dwattr $C$DW$260, DW_AT_name("FR_INT_ERR") + .dwattr $C$DW$260, DW_AT_const_value(0x02) + .dwattr $C$DW$260, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$260, DW_AT_decl_line(0xbb) + .dwattr $C$DW$260, DW_AT_decl_column(0x02) + +$C$DW$261 .dwtag DW_TAG_enumerator + .dwattr $C$DW$261, DW_AT_name("FR_NOT_READY") + .dwattr $C$DW$261, DW_AT_const_value(0x03) + .dwattr $C$DW$261, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$261, DW_AT_decl_line(0xbc) + .dwattr $C$DW$261, DW_AT_decl_column(0x02) + +$C$DW$262 .dwtag DW_TAG_enumerator + .dwattr $C$DW$262, DW_AT_name("FR_NO_FILE") + .dwattr $C$DW$262, DW_AT_const_value(0x04) + .dwattr $C$DW$262, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$262, DW_AT_decl_line(0xbd) + .dwattr $C$DW$262, DW_AT_decl_column(0x02) + +$C$DW$263 .dwtag DW_TAG_enumerator + .dwattr $C$DW$263, DW_AT_name("FR_NO_PATH") + .dwattr $C$DW$263, DW_AT_const_value(0x05) + .dwattr $C$DW$263, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$263, DW_AT_decl_line(0xbe) + .dwattr $C$DW$263, DW_AT_decl_column(0x02) + +$C$DW$264 .dwtag DW_TAG_enumerator + .dwattr $C$DW$264, DW_AT_name("FR_INVALID_NAME") + .dwattr $C$DW$264, DW_AT_const_value(0x06) + .dwattr $C$DW$264, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$264, DW_AT_decl_line(0xbf) + .dwattr $C$DW$264, DW_AT_decl_column(0x02) + +$C$DW$265 .dwtag DW_TAG_enumerator + .dwattr $C$DW$265, DW_AT_name("FR_DENIED") + .dwattr $C$DW$265, DW_AT_const_value(0x07) + .dwattr $C$DW$265, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$265, DW_AT_decl_line(0xc0) + .dwattr $C$DW$265, DW_AT_decl_column(0x02) + +$C$DW$266 .dwtag DW_TAG_enumerator + .dwattr $C$DW$266, DW_AT_name("FR_EXIST") + .dwattr $C$DW$266, DW_AT_const_value(0x08) + .dwattr $C$DW$266, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$266, DW_AT_decl_line(0xc1) + .dwattr $C$DW$266, DW_AT_decl_column(0x02) + +$C$DW$267 .dwtag DW_TAG_enumerator + .dwattr $C$DW$267, DW_AT_name("FR_INVALID_OBJECT") + .dwattr $C$DW$267, DW_AT_const_value(0x09) + .dwattr $C$DW$267, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$267, DW_AT_decl_line(0xc2) + .dwattr $C$DW$267, DW_AT_decl_column(0x02) + +$C$DW$268 .dwtag DW_TAG_enumerator + .dwattr $C$DW$268, DW_AT_name("FR_WRITE_PROTECTED") + .dwattr $C$DW$268, DW_AT_const_value(0x0a) + .dwattr $C$DW$268, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$268, DW_AT_decl_line(0xc3) + .dwattr $C$DW$268, DW_AT_decl_column(0x02) + +$C$DW$269 .dwtag DW_TAG_enumerator + .dwattr $C$DW$269, DW_AT_name("FR_INVALID_DRIVE") + .dwattr $C$DW$269, DW_AT_const_value(0x0b) + .dwattr $C$DW$269, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$269, DW_AT_decl_line(0xc4) + .dwattr $C$DW$269, DW_AT_decl_column(0x02) + +$C$DW$270 .dwtag DW_TAG_enumerator + .dwattr $C$DW$270, DW_AT_name("FR_NOT_ENABLED") + .dwattr $C$DW$270, DW_AT_const_value(0x0c) + .dwattr $C$DW$270, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$270, DW_AT_decl_line(0xc5) + .dwattr $C$DW$270, DW_AT_decl_column(0x02) + +$C$DW$271 .dwtag DW_TAG_enumerator + .dwattr $C$DW$271, DW_AT_name("FR_NO_FILESYSTEM") + .dwattr $C$DW$271, DW_AT_const_value(0x0d) + .dwattr $C$DW$271, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$271, DW_AT_decl_line(0xc6) + .dwattr $C$DW$271, DW_AT_decl_column(0x02) + +$C$DW$272 .dwtag DW_TAG_enumerator + .dwattr $C$DW$272, DW_AT_name("FR_MKFS_ABORTED") + .dwattr $C$DW$272, DW_AT_const_value(0x0e) + .dwattr $C$DW$272, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$272, DW_AT_decl_line(0xc7) + .dwattr $C$DW$272, DW_AT_decl_column(0x02) + +$C$DW$273 .dwtag DW_TAG_enumerator + .dwattr $C$DW$273, DW_AT_name("FR_TIMEOUT") + .dwattr $C$DW$273, DW_AT_const_value(0x0f) + .dwattr $C$DW$273, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$273, DW_AT_decl_line(0xc8) + .dwattr $C$DW$273, DW_AT_decl_column(0x02) + +$C$DW$274 .dwtag DW_TAG_enumerator + .dwattr $C$DW$274, DW_AT_name("FR_LOCKED") + .dwattr $C$DW$274, DW_AT_const_value(0x10) + .dwattr $C$DW$274, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$274, DW_AT_decl_line(0xc9) + .dwattr $C$DW$274, DW_AT_decl_column(0x02) + +$C$DW$275 .dwtag DW_TAG_enumerator + .dwattr $C$DW$275, DW_AT_name("FR_NOT_ENOUGH_CORE") + .dwattr $C$DW$275, DW_AT_const_value(0x11) + .dwattr $C$DW$275, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$275, DW_AT_decl_line(0xca) + .dwattr $C$DW$275, DW_AT_decl_column(0x02) + +$C$DW$276 .dwtag DW_TAG_enumerator + .dwattr $C$DW$276, DW_AT_name("FR_TOO_MANY_OPEN_FILES") + .dwattr $C$DW$276, DW_AT_const_value(0x12) + .dwattr $C$DW$276, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$276, DW_AT_decl_line(0xcb) + .dwattr $C$DW$276, DW_AT_decl_column(0x02) + +$C$DW$277 .dwtag DW_TAG_enumerator + .dwattr $C$DW$277, DW_AT_name("FR_INVALID_PARAMETER") + .dwattr $C$DW$277, DW_AT_const_value(0x13) + .dwattr $C$DW$277, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$277, DW_AT_decl_line(0xcc) + .dwattr $C$DW$277, DW_AT_decl_column(0x02) + + .dwattr $C$DW$T$961, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$961, DW_AT_decl_line(0xb8) + .dwattr $C$DW$T$961, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$961 + +$C$DW$T$962 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$962, DW_AT_name("FRESULT") + .dwattr $C$DW$T$962, DW_AT_type(*$C$DW$T$961) + .dwattr $C$DW$T$962, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$962, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$962, DW_AT_decl_line(0xcd) + .dwattr $C$DW$T$962, DW_AT_decl_column(0x03) + + +$C$DW$T$135 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$135, DW_AT_byte_size(0x10) +$C$DW$278 .dwtag DW_TAG_member + .dwattr $C$DW$278, DW_AT_type(*$C$DW$T$131) + .dwattr $C$DW$278, DW_AT_name("pvSrcEndAddr") + .dwattr $C$DW$278, DW_AT_TI_symbol_name("pvSrcEndAddr") + .dwattr $C$DW$278, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$278, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$278, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$278, DW_AT_decl_line(0x49) + .dwattr $C$DW$278, DW_AT_decl_column(0x14) + +$C$DW$279 .dwtag DW_TAG_member + .dwattr $C$DW$279, DW_AT_type(*$C$DW$T$131) + .dwattr $C$DW$279, DW_AT_name("pvDstEndAddr") + .dwattr $C$DW$279, DW_AT_TI_symbol_name("pvDstEndAddr") + .dwattr $C$DW$279, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$279, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$279, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$279, DW_AT_decl_line(0x4e) + .dwattr $C$DW$279, DW_AT_decl_column(0x14) + +$C$DW$280 .dwtag DW_TAG_member + .dwattr $C$DW$280, DW_AT_type(*$C$DW$T$134) + .dwattr $C$DW$280, DW_AT_name("ui32Control") + .dwattr $C$DW$280, DW_AT_TI_symbol_name("ui32Control") + .dwattr $C$DW$280, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$280, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$280, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$280, DW_AT_decl_line(0x53) + .dwattr $C$DW$280, DW_AT_decl_column(0x17) + +$C$DW$281 .dwtag DW_TAG_member + .dwattr $C$DW$281, DW_AT_type(*$C$DW$T$134) + .dwattr $C$DW$281, DW_AT_name("ui32Spare") + .dwattr $C$DW$281, DW_AT_TI_symbol_name("ui32Spare") + .dwattr $C$DW$281, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$281, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$281, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$281, DW_AT_decl_line(0x58) + .dwattr $C$DW$281, DW_AT_decl_column(0x17) + + .dwattr $C$DW$T$135, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$T$135, DW_AT_decl_line(0x45) + .dwattr $C$DW$T$135, DW_AT_decl_column(0x01) + .dwendtag $C$DW$T$135 + +$C$DW$T$963 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$963, DW_AT_name("tDMAControlTable") + .dwattr $C$DW$T$963, DW_AT_type(*$C$DW$T$135) + .dwattr $C$DW$T$963, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$963, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/udma.h") + .dwattr $C$DW$T$963, DW_AT_decl_line(0x5a) + .dwattr $C$DW$T$963, DW_AT_decl_column(0x01) + + +$C$DW$T$964 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$964, DW_AT_type(*$C$DW$T$963) + .dwattr $C$DW$T$964, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$964, DW_AT_byte_size(0x200) +$C$DW$282 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$282, DW_AT_upper_bound(0x1f) + + .dwendtag $C$DW$T$964 + + +$C$DW$T$140 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$140, DW_AT_byte_size(0x234) +$C$DW$283 .dwtag DW_TAG_member + .dwattr $C$DW$283, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$283, DW_AT_name("fs_type") + .dwattr $C$DW$283, DW_AT_TI_symbol_name("fs_type") + .dwattr $C$DW$283, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$283, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$283, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$283, DW_AT_decl_line(0x4f) + .dwattr $C$DW$283, DW_AT_decl_column(0x07) + +$C$DW$284 .dwtag DW_TAG_member + .dwattr $C$DW$284, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$284, DW_AT_name("drv") + .dwattr $C$DW$284, DW_AT_TI_symbol_name("drv") + .dwattr $C$DW$284, DW_AT_data_member_location[DW_OP_plus_uconst 0x1] + .dwattr $C$DW$284, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$284, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$284, DW_AT_decl_line(0x50) + .dwattr $C$DW$284, DW_AT_decl_column(0x07) + +$C$DW$285 .dwtag DW_TAG_member + .dwattr $C$DW$285, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$285, DW_AT_name("csize") + .dwattr $C$DW$285, DW_AT_TI_symbol_name("csize") + .dwattr $C$DW$285, DW_AT_data_member_location[DW_OP_plus_uconst 0x2] + .dwattr $C$DW$285, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$285, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$285, DW_AT_decl_line(0x51) + .dwattr $C$DW$285, DW_AT_decl_column(0x07) + +$C$DW$286 .dwtag DW_TAG_member + .dwattr $C$DW$286, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$286, DW_AT_name("n_fats") + .dwattr $C$DW$286, DW_AT_TI_symbol_name("n_fats") + .dwattr $C$DW$286, DW_AT_data_member_location[DW_OP_plus_uconst 0x3] + .dwattr $C$DW$286, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$286, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$286, DW_AT_decl_line(0x52) + .dwattr $C$DW$286, DW_AT_decl_column(0x07) + +$C$DW$287 .dwtag DW_TAG_member + .dwattr $C$DW$287, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$287, DW_AT_name("wflag") + .dwattr $C$DW$287, DW_AT_TI_symbol_name("wflag") + .dwattr $C$DW$287, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$287, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$287, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$287, DW_AT_decl_line(0x53) + .dwattr $C$DW$287, DW_AT_decl_column(0x07) + +$C$DW$288 .dwtag DW_TAG_member + .dwattr $C$DW$288, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$288, DW_AT_name("fsi_flag") + .dwattr $C$DW$288, DW_AT_TI_symbol_name("fsi_flag") + .dwattr $C$DW$288, DW_AT_data_member_location[DW_OP_plus_uconst 0x5] + .dwattr $C$DW$288, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$288, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$288, DW_AT_decl_line(0x54) + .dwattr $C$DW$288, DW_AT_decl_column(0x07) + +$C$DW$289 .dwtag DW_TAG_member + .dwattr $C$DW$289, DW_AT_type(*$C$DW$T$137) + .dwattr $C$DW$289, DW_AT_name("id") + .dwattr $C$DW$289, DW_AT_TI_symbol_name("id") + .dwattr $C$DW$289, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + .dwattr $C$DW$289, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$289, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$289, DW_AT_decl_line(0x55) + .dwattr $C$DW$289, DW_AT_decl_column(0x07) + +$C$DW$290 .dwtag DW_TAG_member + .dwattr $C$DW$290, DW_AT_type(*$C$DW$T$137) + .dwattr $C$DW$290, DW_AT_name("n_rootdir") + .dwattr $C$DW$290, DW_AT_TI_symbol_name("n_rootdir") + .dwattr $C$DW$290, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$290, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$290, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$290, DW_AT_decl_line(0x56) + .dwattr $C$DW$290, DW_AT_decl_column(0x07) + +$C$DW$291 .dwtag DW_TAG_member + .dwattr $C$DW$291, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$291, DW_AT_name("sobj") + .dwattr $C$DW$291, DW_AT_TI_symbol_name("sobj") + .dwattr $C$DW$291, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$291, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$291, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$291, DW_AT_decl_line(0x5b) + .dwattr $C$DW$291, DW_AT_decl_column(0x0a) + +$C$DW$292 .dwtag DW_TAG_member + .dwattr $C$DW$292, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$292, DW_AT_name("last_clust") + .dwattr $C$DW$292, DW_AT_TI_symbol_name("last_clust") + .dwattr $C$DW$292, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$292, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$292, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$292, DW_AT_decl_line(0x5e) + .dwattr $C$DW$292, DW_AT_decl_column(0x08) + +$C$DW$293 .dwtag DW_TAG_member + .dwattr $C$DW$293, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$293, DW_AT_name("free_clust") + .dwattr $C$DW$293, DW_AT_TI_symbol_name("free_clust") + .dwattr $C$DW$293, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$293, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$293, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$293, DW_AT_decl_line(0x5f) + .dwattr $C$DW$293, DW_AT_decl_column(0x08) + +$C$DW$294 .dwtag DW_TAG_member + .dwattr $C$DW$294, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$294, DW_AT_name("n_fatent") + .dwattr $C$DW$294, DW_AT_TI_symbol_name("n_fatent") + .dwattr $C$DW$294, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$294, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$294, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$294, DW_AT_decl_line(0x64) + .dwattr $C$DW$294, DW_AT_decl_column(0x08) + +$C$DW$295 .dwtag DW_TAG_member + .dwattr $C$DW$295, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$295, DW_AT_name("fsize") + .dwattr $C$DW$295, DW_AT_TI_symbol_name("fsize") + .dwattr $C$DW$295, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$295, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$295, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$295, DW_AT_decl_line(0x65) + .dwattr $C$DW$295, DW_AT_decl_column(0x08) + +$C$DW$296 .dwtag DW_TAG_member + .dwattr $C$DW$296, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$296, DW_AT_name("volbase") + .dwattr $C$DW$296, DW_AT_TI_symbol_name("volbase") + .dwattr $C$DW$296, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$296, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$296, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$296, DW_AT_decl_line(0x66) + .dwattr $C$DW$296, DW_AT_decl_column(0x08) + +$C$DW$297 .dwtag DW_TAG_member + .dwattr $C$DW$297, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$297, DW_AT_name("fatbase") + .dwattr $C$DW$297, DW_AT_TI_symbol_name("fatbase") + .dwattr $C$DW$297, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$297, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$297, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$297, DW_AT_decl_line(0x67) + .dwattr $C$DW$297, DW_AT_decl_column(0x08) + +$C$DW$298 .dwtag DW_TAG_member + .dwattr $C$DW$298, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$298, DW_AT_name("dirbase") + .dwattr $C$DW$298, DW_AT_TI_symbol_name("dirbase") + .dwattr $C$DW$298, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$298, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$298, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$298, DW_AT_decl_line(0x68) + .dwattr $C$DW$298, DW_AT_decl_column(0x08) + +$C$DW$299 .dwtag DW_TAG_member + .dwattr $C$DW$299, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$299, DW_AT_name("database") + .dwattr $C$DW$299, DW_AT_TI_symbol_name("database") + .dwattr $C$DW$299, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c] + .dwattr $C$DW$299, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$299, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$299, DW_AT_decl_line(0x69) + .dwattr $C$DW$299, DW_AT_decl_column(0x08) + +$C$DW$300 .dwtag DW_TAG_member + .dwattr $C$DW$300, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$300, DW_AT_name("winsect") + .dwattr $C$DW$300, DW_AT_TI_symbol_name("winsect") + .dwattr $C$DW$300, DW_AT_data_member_location[DW_OP_plus_uconst 0x30] + .dwattr $C$DW$300, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$300, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$300, DW_AT_decl_line(0x6a) + .dwattr $C$DW$300, DW_AT_decl_column(0x08) + +$C$DW$301 .dwtag DW_TAG_member + .dwattr $C$DW$301, DW_AT_type(*$C$DW$T$139) + .dwattr $C$DW$301, DW_AT_name("win") + .dwattr $C$DW$301, DW_AT_TI_symbol_name("win") + .dwattr $C$DW$301, DW_AT_data_member_location[DW_OP_plus_uconst 0x34] + .dwattr $C$DW$301, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$301, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$301, DW_AT_decl_line(0x6b) + .dwattr $C$DW$301, DW_AT_decl_column(0x07) + + .dwattr $C$DW$T$140, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$140, DW_AT_decl_line(0x4e) + .dwattr $C$DW$T$140, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$140 + +$C$DW$T$162 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$162, DW_AT_name("FATFS") + .dwattr $C$DW$T$162, DW_AT_type(*$C$DW$T$140) + .dwattr $C$DW$T$162, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$162, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$162, DW_AT_decl_line(0x6c) + .dwattr $C$DW$T$162, DW_AT_decl_column(0x03) + +$C$DW$T$163 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$163, DW_AT_type(*$C$DW$T$162) + .dwattr $C$DW$T$163, DW_AT_address_class(0x20) + + +$C$DW$T$150 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$150, DW_AT_byte_size(0x02) +$C$DW$302 .dwtag DW_TAG_member + .dwattr $C$DW$302, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$302, DW_AT_name("opened") + .dwattr $C$DW$302, DW_AT_TI_symbol_name("opened") + .dwattr $C$DW$302, DW_AT_bit_offset(0x07) + .dwattr $C$DW$302, DW_AT_bit_size(0x01) + .dwattr $C$DW$302, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$302, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$302, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$302, DW_AT_decl_line(0xbc) + .dwattr $C$DW$302, DW_AT_decl_column(0x1a) + +$C$DW$303 .dwtag DW_TAG_member + .dwattr $C$DW$303, DW_AT_type(*$C$DW$T$143) + .dwattr $C$DW$303, DW_AT_name("readMode") + .dwattr $C$DW$303, DW_AT_TI_symbol_name("readMode") + .dwattr $C$DW$303, DW_AT_bit_offset(0x06) + .dwattr $C$DW$303, DW_AT_bit_size(0x01) + .dwattr $C$DW$303, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$303, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$303, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$303, DW_AT_decl_line(0xbd) + .dwattr $C$DW$303, DW_AT_decl_column(0x1a) + +$C$DW$304 .dwtag DW_TAG_member + .dwattr $C$DW$304, DW_AT_type(*$C$DW$T$143) + .dwattr $C$DW$304, DW_AT_name("writeMode") + .dwattr $C$DW$304, DW_AT_TI_symbol_name("writeMode") + .dwattr $C$DW$304, DW_AT_bit_offset(0x05) + .dwattr $C$DW$304, DW_AT_bit_size(0x01) + .dwattr $C$DW$304, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$304, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$304, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$304, DW_AT_decl_line(0xbe) + .dwattr $C$DW$304, DW_AT_decl_column(0x1a) + +$C$DW$305 .dwtag DW_TAG_member + .dwattr $C$DW$305, DW_AT_type(*$C$DW$T$145) + .dwattr $C$DW$305, DW_AT_name("readDataMode") + .dwattr $C$DW$305, DW_AT_TI_symbol_name("readDataMode") + .dwattr $C$DW$305, DW_AT_bit_offset(0x04) + .dwattr $C$DW$305, DW_AT_bit_size(0x01) + .dwattr $C$DW$305, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$305, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$305, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$305, DW_AT_decl_line(0xbf) + .dwattr $C$DW$305, DW_AT_decl_column(0x1a) + +$C$DW$306 .dwtag DW_TAG_member + .dwattr $C$DW$306, DW_AT_type(*$C$DW$T$145) + .dwattr $C$DW$306, DW_AT_name("writeDataMode") + .dwattr $C$DW$306, DW_AT_TI_symbol_name("writeDataMode") + .dwattr $C$DW$306, DW_AT_bit_offset(0x03) + .dwattr $C$DW$306, DW_AT_bit_size(0x01) + .dwattr $C$DW$306, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$306, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$306, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$306, DW_AT_decl_line(0xc0) + .dwattr $C$DW$306, DW_AT_decl_column(0x1a) + +$C$DW$307 .dwtag DW_TAG_member + .dwattr $C$DW$307, DW_AT_type(*$C$DW$T$147) + .dwattr $C$DW$307, DW_AT_name("readReturnMode") + .dwattr $C$DW$307, DW_AT_TI_symbol_name("readReturnMode") + .dwattr $C$DW$307, DW_AT_bit_offset(0x02) + .dwattr $C$DW$307, DW_AT_bit_size(0x01) + .dwattr $C$DW$307, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$307, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$307, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$307, DW_AT_decl_line(0xc1) + .dwattr $C$DW$307, DW_AT_decl_column(0x1a) + +$C$DW$308 .dwtag DW_TAG_member + .dwattr $C$DW$308, DW_AT_type(*$C$DW$T$149) + .dwattr $C$DW$308, DW_AT_name("readEcho") + .dwattr $C$DW$308, DW_AT_TI_symbol_name("readEcho") + .dwattr $C$DW$308, DW_AT_bit_offset(0x01) + .dwattr $C$DW$308, DW_AT_bit_size(0x01) + .dwattr $C$DW$308, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$308, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$308, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$308, DW_AT_decl_line(0xc2) + .dwattr $C$DW$308, DW_AT_decl_column(0x1a) + +$C$DW$309 .dwtag DW_TAG_member + .dwattr $C$DW$309, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$309, DW_AT_name("bufTimeout") + .dwattr $C$DW$309, DW_AT_TI_symbol_name("bufTimeout") + .dwattr $C$DW$309, DW_AT_bit_offset(0x00) + .dwattr $C$DW$309, DW_AT_bit_size(0x01) + .dwattr $C$DW$309, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$309, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$309, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$309, DW_AT_decl_line(0xc7) + .dwattr $C$DW$309, DW_AT_decl_column(0x1a) + +$C$DW$310 .dwtag DW_TAG_member + .dwattr $C$DW$310, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$310, DW_AT_name("callCallback") + .dwattr $C$DW$310, DW_AT_TI_symbol_name("callCallback") + .dwattr $C$DW$310, DW_AT_bit_offset(0x07) + .dwattr $C$DW$310, DW_AT_bit_size(0x01) + .dwattr $C$DW$310, DW_AT_data_member_location[DW_OP_plus_uconst 0x1] + .dwattr $C$DW$310, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$310, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$310, DW_AT_decl_line(0xcc) + .dwattr $C$DW$310, DW_AT_decl_column(0x1a) + +$C$DW$311 .dwtag DW_TAG_member + .dwattr $C$DW$311, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$311, DW_AT_name("drainByISR") + .dwattr $C$DW$311, DW_AT_TI_symbol_name("drainByISR") + .dwattr $C$DW$311, DW_AT_bit_offset(0x06) + .dwattr $C$DW$311, DW_AT_bit_size(0x01) + .dwattr $C$DW$311, DW_AT_data_member_location[DW_OP_plus_uconst 0x1] + .dwattr $C$DW$311, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$311, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$311, DW_AT_decl_line(0xd1) + .dwattr $C$DW$311, DW_AT_decl_column(0x1a) + +$C$DW$312 .dwtag DW_TAG_member + .dwattr $C$DW$312, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$312, DW_AT_name("rxEnabled") + .dwattr $C$DW$312, DW_AT_TI_symbol_name("rxEnabled") + .dwattr $C$DW$312, DW_AT_bit_offset(0x05) + .dwattr $C$DW$312, DW_AT_bit_size(0x01) + .dwattr $C$DW$312, DW_AT_data_member_location[DW_OP_plus_uconst 0x1] + .dwattr $C$DW$312, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$312, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$312, DW_AT_decl_line(0xd3) + .dwattr $C$DW$312, DW_AT_decl_column(0x1a) + + .dwattr $C$DW$T$150, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr 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DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$314, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$314, DW_AT_decl_line(0x7b) + .dwattr $C$DW$314, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$151, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$151, DW_AT_decl_line(0x79) + .dwattr $C$DW$T$151, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$151 + +$C$DW$T$966 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$966, DW_AT_name("__max_align_t") + .dwattr $C$DW$T$966, DW_AT_type(*$C$DW$T$151) + .dwattr $C$DW$T$966, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$966, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$966, DW_AT_decl_line(0x7c) + .dwattr $C$DW$T$966, DW_AT_decl_column(0x03) + + +$C$DW$T$155 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$155, DW_AT_byte_size(0x08) +$C$DW$315 .dwtag DW_TAG_member + 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DW_AT_decl_column(0x44) + + .dwattr $C$DW$T$155, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$155, DW_AT_decl_line(0x273) + .dwattr $C$DW$T$155, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$155 + +$C$DW$T$967 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$967, DW_AT_name("__ARRAY1_ti_sysbios_family_arm_m3_Hwi_hooks") + .dwattr $C$DW$T$967, DW_AT_type(*$C$DW$T$155) + .dwattr $C$DW$T$967, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$967, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$967, DW_AT_decl_line(0x273) + .dwattr $C$DW$T$967, DW_AT_decl_column(0x4c) + +$C$DW$T$968 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$968, DW_AT_name("__TA_ti_sysbios_family_arm_m3_Hwi_hooks") + .dwattr $C$DW$T$968, DW_AT_type(*$C$DW$T$967) + .dwattr $C$DW$T$968, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$968, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$968, DW_AT_decl_line(0x274) + .dwattr $C$DW$T$968, DW_AT_decl_column(0x35) + +$C$DW$T$969 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$969, DW_AT_name("CT__ti_sysbios_family_arm_m3_Hwi_hooks") + .dwattr $C$DW$T$969, DW_AT_type(*$C$DW$T$968) + .dwattr $C$DW$T$969, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$969, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$969, DW_AT_decl_line(0x275) + .dwattr $C$DW$T$969, DW_AT_decl_column(0x31) + + +$C$DW$T$158 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$158, DW_AT_byte_size(0x08) +$C$DW$317 .dwtag DW_TAG_member + .dwattr $C$DW$317, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$317, DW_AT_name("length") + .dwattr $C$DW$317, DW_AT_TI_symbol_name("length") + .dwattr $C$DW$317, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$317, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$317, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$317, DW_AT_decl_line(0xe2) + .dwattr $C$DW$317, DW_AT_decl_column(0x16) + +$C$DW$318 .dwtag DW_TAG_member + .dwattr $C$DW$318, DW_AT_type(*$C$DW$T$157) + .dwattr $C$DW$318, DW_AT_name("elem") + .dwattr $C$DW$318, DW_AT_TI_symbol_name("elem") + .dwattr $C$DW$318, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$318, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$318, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$318, DW_AT_decl_line(0xe2) + .dwattr $C$DW$318, DW_AT_decl_column(0x3a) + + .dwattr $C$DW$T$158, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$158, DW_AT_decl_line(0xe2) + .dwattr $C$DW$T$158, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$158 + +$C$DW$T$970 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$970, DW_AT_name("__ARRAY1_ti_sysbios_knl_Swi_hooks") + .dwattr $C$DW$T$970, DW_AT_type(*$C$DW$T$158) + .dwattr $C$DW$T$970, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$970, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$970, DW_AT_decl_line(0xe2) + .dwattr $C$DW$T$970, DW_AT_decl_column(0x42) + +$C$DW$T$971 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$971, DW_AT_name("__TA_ti_sysbios_knl_Swi_hooks") + .dwattr $C$DW$T$971, DW_AT_type(*$C$DW$T$970) + .dwattr $C$DW$T$971, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$971, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$971, DW_AT_decl_line(0xe3) + .dwattr $C$DW$T$971, DW_AT_decl_column(0x2b) + +$C$DW$T$972 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$972, DW_AT_name("CT__ti_sysbios_knl_Swi_hooks") + .dwattr $C$DW$T$972, DW_AT_type(*$C$DW$T$971) + .dwattr $C$DW$T$972, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$972, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$972, DW_AT_decl_line(0xe4) + .dwattr $C$DW$T$972, DW_AT_decl_column(0x27) + + +$C$DW$T$161 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$161, DW_AT_byte_size(0x08) +$C$DW$319 .dwtag DW_TAG_member + .dwattr $C$DW$319, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$319, DW_AT_name("length") + .dwattr $C$DW$319, DW_AT_TI_symbol_name("length") + .dwattr $C$DW$319, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$319, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$319, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$319, DW_AT_decl_line(0x1af) + .dwattr $C$DW$319, DW_AT_decl_column(0x16) + +$C$DW$320 .dwtag DW_TAG_member + .dwattr $C$DW$320, DW_AT_type(*$C$DW$T$160) + .dwattr $C$DW$320, DW_AT_name("elem") + .dwattr $C$DW$320, DW_AT_TI_symbol_name("elem") + .dwattr $C$DW$320, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$320, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$320, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$320, DW_AT_decl_line(0x1af) + .dwattr $C$DW$320, DW_AT_decl_column(0x3b) + + .dwattr $C$DW$T$161, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$161, DW_AT_decl_line(0x1af) + .dwattr $C$DW$T$161, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$161 + +$C$DW$T$973 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$973, DW_AT_name("__ARRAY1_ti_sysbios_knl_Task_hooks") + .dwattr $C$DW$T$973, DW_AT_type(*$C$DW$T$161) + .dwattr $C$DW$T$973, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$973, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + 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DW_AT_decl_line(0x74) + .dwattr $C$DW$322, DW_AT_decl_column(0x07) + +$C$DW$323 .dwtag DW_TAG_member + .dwattr $C$DW$323, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$323, DW_AT_name("flag") + .dwattr $C$DW$323, DW_AT_TI_symbol_name("flag") + .dwattr $C$DW$323, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + .dwattr $C$DW$323, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$323, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$323, DW_AT_decl_line(0x75) + .dwattr $C$DW$323, DW_AT_decl_column(0x07) + +$C$DW$324 .dwtag DW_TAG_member + .dwattr $C$DW$324, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$324, DW_AT_name("err") + .dwattr $C$DW$324, DW_AT_TI_symbol_name("err") + .dwattr $C$DW$324, DW_AT_data_member_location[DW_OP_plus_uconst 0x7] + .dwattr $C$DW$324, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$324, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$324, DW_AT_decl_line(0x76) + .dwattr $C$DW$324, DW_AT_decl_column(0x07) + +$C$DW$325 .dwtag DW_TAG_member + .dwattr $C$DW$325, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$325, DW_AT_name("fptr") + .dwattr $C$DW$325, DW_AT_TI_symbol_name("fptr") + .dwattr $C$DW$325, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$325, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$325, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$325, DW_AT_decl_line(0x77) + .dwattr $C$DW$325, DW_AT_decl_column(0x08) + +$C$DW$326 .dwtag DW_TAG_member + .dwattr $C$DW$326, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$326, DW_AT_name("fsize") + .dwattr $C$DW$326, DW_AT_TI_symbol_name("fsize") + .dwattr $C$DW$326, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$326, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$326, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$326, DW_AT_decl_line(0x78) + .dwattr $C$DW$326, DW_AT_decl_column(0x08) + +$C$DW$327 .dwtag DW_TAG_member + .dwattr $C$DW$327, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$327, DW_AT_name("sclust") + .dwattr $C$DW$327, DW_AT_TI_symbol_name("sclust") + .dwattr $C$DW$327, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$327, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$327, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$327, DW_AT_decl_line(0x79) + .dwattr $C$DW$327, DW_AT_decl_column(0x08) + +$C$DW$328 .dwtag DW_TAG_member + .dwattr $C$DW$328, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$328, DW_AT_name("clust") + .dwattr $C$DW$328, DW_AT_TI_symbol_name("clust") + .dwattr $C$DW$328, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$328, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$328, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$328, DW_AT_decl_line(0x7a) + .dwattr $C$DW$328, DW_AT_decl_column(0x08) + +$C$DW$329 .dwtag DW_TAG_member + .dwattr $C$DW$329, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$329, DW_AT_name("dsect") + .dwattr $C$DW$329, DW_AT_TI_symbol_name("dsect") + .dwattr $C$DW$329, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$329, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$329, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$329, DW_AT_decl_line(0x7b) + .dwattr $C$DW$329, DW_AT_decl_column(0x08) + +$C$DW$330 .dwtag DW_TAG_member + .dwattr $C$DW$330, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$330, DW_AT_name("dir_sect") + .dwattr $C$DW$330, DW_AT_TI_symbol_name("dir_sect") + .dwattr $C$DW$330, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$330, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$330, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$330, DW_AT_decl_line(0x7d) + .dwattr $C$DW$330, DW_AT_decl_column(0x08) + +$C$DW$331 .dwtag DW_TAG_member + .dwattr $C$DW$331, DW_AT_type(*$C$DW$T$164) + .dwattr $C$DW$331, DW_AT_name("dir_ptr") + .dwattr $C$DW$331, DW_AT_TI_symbol_name("dir_ptr") + .dwattr $C$DW$331, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$331, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$331, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$331, DW_AT_decl_line(0x7e) + .dwattr $C$DW$331, DW_AT_decl_column(0x08) + +$C$DW$332 .dwtag DW_TAG_member + .dwattr $C$DW$332, DW_AT_type(*$C$DW$T$139) + .dwattr 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DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$336, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$336, DW_AT_decl_line(0x93) + .dwattr $C$DW$336, DW_AT_decl_column(0x08) + +$C$DW$337 .dwtag DW_TAG_member + .dwattr $C$DW$337, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$337, DW_AT_name("clust") + .dwattr $C$DW$337, DW_AT_TI_symbol_name("clust") + .dwattr $C$DW$337, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$337, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$337, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$337, DW_AT_decl_line(0x94) + .dwattr $C$DW$337, DW_AT_decl_column(0x08) + +$C$DW$338 .dwtag DW_TAG_member + .dwattr $C$DW$338, DW_AT_type(*$C$DW$T$138) + .dwattr $C$DW$338, DW_AT_name("sect") + .dwattr $C$DW$338, DW_AT_TI_symbol_name("sect") + .dwattr $C$DW$338, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$338, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$338, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$338, DW_AT_decl_line(0x95) + .dwattr $C$DW$338, DW_AT_decl_column(0x08) + +$C$DW$339 .dwtag DW_TAG_member + .dwattr $C$DW$339, DW_AT_type(*$C$DW$T$164) + .dwattr $C$DW$339, DW_AT_name("dir") + .dwattr $C$DW$339, DW_AT_TI_symbol_name("dir") + .dwattr $C$DW$339, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$339, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$339, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$339, DW_AT_decl_line(0x96) + .dwattr $C$DW$339, DW_AT_decl_column(0x08) + +$C$DW$340 .dwtag DW_TAG_member + .dwattr $C$DW$340, DW_AT_type(*$C$DW$T$164) + .dwattr $C$DW$340, DW_AT_name("fn") + .dwattr $C$DW$340, DW_AT_TI_symbol_name("fn") + .dwattr $C$DW$340, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$340, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$340, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$340, DW_AT_decl_line(0x97) + .dwattr $C$DW$340, DW_AT_decl_column(0x08) + + .dwattr $C$DW$T$166, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$166, DW_AT_decl_line(0x8f) + .dwattr $C$DW$T$166, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$166 + +$C$DW$T$977 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$977, DW_AT_name("DIR") + .dwattr $C$DW$T$977, DW_AT_type(*$C$DW$T$166) + .dwattr $C$DW$T$977, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$977, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$977, DW_AT_decl_line(0xa2) + .dwattr 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$342, DW_AT_decl_line(0xaa) + .dwattr $C$DW$342, DW_AT_decl_column(0x07) + +$C$DW$343 .dwtag DW_TAG_member + .dwattr $C$DW$343, DW_AT_type(*$C$DW$T$137) + .dwattr $C$DW$343, DW_AT_name("ftime") + .dwattr $C$DW$343, DW_AT_TI_symbol_name("ftime") + .dwattr $C$DW$343, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + .dwattr $C$DW$343, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$343, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$343, DW_AT_decl_line(0xab) + .dwattr $C$DW$343, DW_AT_decl_column(0x07) + +$C$DW$344 .dwtag DW_TAG_member + .dwattr $C$DW$344, DW_AT_type(*$C$DW$T$136) + .dwattr $C$DW$344, DW_AT_name("fattrib") + .dwattr $C$DW$344, DW_AT_TI_symbol_name("fattrib") + .dwattr $C$DW$344, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$344, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$344, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$344, DW_AT_decl_line(0xac) + .dwattr $C$DW$344, DW_AT_decl_column(0x07) + +$C$DW$345 .dwtag DW_TAG_member + .dwattr $C$DW$345, DW_AT_type(*$C$DW$T$169) + .dwattr $C$DW$345, DW_AT_name("fname") + .dwattr $C$DW$345, DW_AT_TI_symbol_name("fname") + .dwattr $C$DW$345, DW_AT_data_member_location[DW_OP_plus_uconst 0x9] + .dwattr $C$DW$345, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$345, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$345, DW_AT_decl_line(0xad) + .dwattr $C$DW$345, DW_AT_decl_column(0x08) + + .dwattr $C$DW$T$170, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$170, DW_AT_decl_line(0xa8) + .dwattr $C$DW$T$170, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$170 + +$C$DW$T$978 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$978, DW_AT_name("FILINFO") + .dwattr $C$DW$T$978, DW_AT_type(*$C$DW$T$170) + .dwattr $C$DW$T$978, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$978, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h") + .dwattr $C$DW$T$978, DW_AT_decl_line(0xb2) + .dwattr $C$DW$T$978, DW_AT_decl_column(0x03) + + +$C$DW$T$185 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$185, DW_AT_byte_size(0x14) +$C$DW$346 .dwtag DW_TAG_member + .dwattr $C$DW$346, DW_AT_type(*$C$DW$T$173) + .dwattr $C$DW$346, DW_AT_name("d_init") + .dwattr $C$DW$346, DW_AT_TI_symbol_name("d_init") + .dwattr $C$DW$346, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$346, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$346, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$348, DW_AT_decl_line(0x59) + .dwattr $C$DW$348, DW_AT_decl_column(0x0f) + +$C$DW$349 .dwtag DW_TAG_member + .dwattr $C$DW$349, DW_AT_type(*$C$DW$T$182) + .dwattr $C$DW$349, DW_AT_name("d_write") + .dwattr $C$DW$349, DW_AT_TI_symbol_name("d_write") + .dwattr $C$DW$349, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$349, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$349, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h") + .dwattr $C$DW$349, DW_AT_decl_line(0x5a) + .dwattr $C$DW$349, DW_AT_decl_column(0x0f) + +$C$DW$350 .dwtag DW_TAG_member + .dwattr $C$DW$350, DW_AT_type(*$C$DW$T$184) + .dwattr $C$DW$350, DW_AT_name("d_ioctl") + .dwattr $C$DW$350, DW_AT_TI_symbol_name("d_ioctl") + .dwattr $C$DW$350, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr 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DW_AT_decl_column(0x05) + +$C$DW$354 .dwtag DW_TAG_enumerator + .dwattr $C$DW$354, DW_AT_name("EK_TM4C123GXL_SW2") + .dwattr $C$DW$354, DW_AT_const_value(0x01) + .dwattr $C$DW$354, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$354, DW_AT_decl_line(0x3e) + .dwattr $C$DW$354, DW_AT_decl_column(0x05) + +$C$DW$355 .dwtag DW_TAG_enumerator + .dwattr $C$DW$355, DW_AT_name("EK_TM4C123GXL_LED_RED") + .dwattr $C$DW$355, DW_AT_const_value(0x02) + .dwattr $C$DW$355, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$355, DW_AT_decl_line(0x3f) + .dwattr $C$DW$355, DW_AT_decl_column(0x05) + +$C$DW$356 .dwtag DW_TAG_enumerator + .dwattr $C$DW$356, DW_AT_name("EK_TM4C123GXL_LED_BLUE") + .dwattr $C$DW$356, DW_AT_const_value(0x03) + .dwattr $C$DW$356, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$356, DW_AT_decl_line(0x40) + .dwattr $C$DW$356, DW_AT_decl_column(0x05) + +$C$DW$357 .dwtag DW_TAG_enumerator + .dwattr $C$DW$357, DW_AT_name("EK_TM4C123GXL_LED_GREEN") + .dwattr $C$DW$357, DW_AT_const_value(0x04) + .dwattr $C$DW$357, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$357, DW_AT_decl_line(0x41) + .dwattr $C$DW$357, DW_AT_decl_column(0x05) + +$C$DW$358 .dwtag DW_TAG_enumerator + .dwattr $C$DW$358, DW_AT_name("EK_TM4C123GXL_GPIOCOUNT") + .dwattr $C$DW$358, DW_AT_const_value(0x05) + .dwattr $C$DW$358, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$358, DW_AT_decl_line(0x43) + .dwattr $C$DW$358, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$981, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$981, DW_AT_decl_line(0x3c) + .dwattr $C$DW$T$981, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$981 + +$C$DW$T$982 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$982, DW_AT_name("EK_TM4C123GXL_GPIOName") + .dwattr $C$DW$T$982, DW_AT_type(*$C$DW$T$981) + .dwattr $C$DW$T$982, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$982, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$982, DW_AT_decl_line(0x44) + .dwattr $C$DW$T$982, DW_AT_decl_column(0x03) + + +$C$DW$T$983 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$983, DW_AT_name("EK_TM4C123GXL_I2CName") + .dwattr $C$DW$T$983, DW_AT_byte_size(0x01) +$C$DW$359 .dwtag DW_TAG_enumerator + .dwattr $C$DW$359, DW_AT_name("EK_TM4C123GXL_I2C0") + .dwattr $C$DW$359, DW_AT_const_value(0x00) + .dwattr $C$DW$359, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$359, DW_AT_decl_line(0x4b) + .dwattr $C$DW$359, DW_AT_decl_column(0x05) + +$C$DW$360 .dwtag DW_TAG_enumerator + .dwattr $C$DW$360, DW_AT_name("EK_TM4C123GXL_I2C3") + .dwattr $C$DW$360, DW_AT_const_value(0x01) + .dwattr $C$DW$360, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$360, DW_AT_decl_line(0x4c) + .dwattr $C$DW$360, DW_AT_decl_column(0x05) + +$C$DW$361 .dwtag DW_TAG_enumerator + .dwattr $C$DW$361, DW_AT_name("EK_TM4C123GXL_I2CCOUNT") + .dwattr $C$DW$361, DW_AT_const_value(0x02) + .dwattr $C$DW$361, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$361, DW_AT_decl_line(0x4e) + .dwattr $C$DW$361, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$983, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$983, DW_AT_decl_line(0x4a) + .dwattr $C$DW$T$983, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$983 + +$C$DW$T$984 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$984, DW_AT_name("EK_TM4C123GXL_I2CName") + .dwattr $C$DW$T$984, DW_AT_type(*$C$DW$T$983) + .dwattr $C$DW$T$984, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$984, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$984, DW_AT_decl_line(0x4f) + .dwattr $C$DW$T$984, DW_AT_decl_column(0x03) + + +$C$DW$T$985 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$985, DW_AT_name("EK_TM4C123GXL_PWMName") + .dwattr $C$DW$T$985, DW_AT_byte_size(0x01) +$C$DW$362 .dwtag DW_TAG_enumerator + .dwattr $C$DW$362, DW_AT_name("EK_TM4C123GXL_PWM6") + .dwattr $C$DW$362, DW_AT_const_value(0x00) + .dwattr $C$DW$362, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$362, DW_AT_decl_line(0x56) + .dwattr $C$DW$362, DW_AT_decl_column(0x05) + +$C$DW$363 .dwtag DW_TAG_enumerator + .dwattr $C$DW$363, DW_AT_name("EK_TM4C123GXL_PWM7") + .dwattr $C$DW$363, DW_AT_const_value(0x01) + .dwattr $C$DW$363, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$363, DW_AT_decl_line(0x57) + .dwattr $C$DW$363, DW_AT_decl_column(0x05) + +$C$DW$364 .dwtag DW_TAG_enumerator + .dwattr $C$DW$364, DW_AT_name("EK_TM4C123GXL_PWMCOUNT") + .dwattr $C$DW$364, DW_AT_const_value(0x02) + .dwattr $C$DW$364, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$364, DW_AT_decl_line(0x59) + .dwattr $C$DW$364, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$985, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$985, DW_AT_decl_line(0x55) + .dwattr $C$DW$T$985, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$985 + +$C$DW$T$986 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$986, DW_AT_name("EK_TM4C123GXL_PWMName") + .dwattr $C$DW$T$986, DW_AT_type(*$C$DW$T$985) + .dwattr $C$DW$T$986, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$986, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$986, DW_AT_decl_line(0x5a) + .dwattr $C$DW$T$986, DW_AT_decl_column(0x03) + + +$C$DW$T$987 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$987, DW_AT_name("EK_TM4C123GXL_SDSPIName") + .dwattr $C$DW$T$987, DW_AT_byte_size(0x01) +$C$DW$365 .dwtag DW_TAG_enumerator + .dwattr $C$DW$365, DW_AT_name("EK_TM4C123GXL_SDSPI0") + .dwattr $C$DW$365, DW_AT_const_value(0x00) + .dwattr $C$DW$365, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$365, DW_AT_decl_line(0x61) + .dwattr $C$DW$365, DW_AT_decl_column(0x05) + +$C$DW$366 .dwtag DW_TAG_enumerator + .dwattr $C$DW$366, DW_AT_name("EK_TM4C123GXL_SDSPICOUNT") + .dwattr $C$DW$366, DW_AT_const_value(0x01) + .dwattr $C$DW$366, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$366, DW_AT_decl_line(0x63) + .dwattr $C$DW$366, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$987, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$987, DW_AT_decl_line(0x60) + .dwattr $C$DW$T$987, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$987 + +$C$DW$T$988 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$988, DW_AT_name("EK_TM4C123GXL_SDSPIName") + .dwattr $C$DW$T$988, DW_AT_type(*$C$DW$T$987) + .dwattr $C$DW$T$988, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$988, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$988, DW_AT_decl_line(0x64) + .dwattr $C$DW$T$988, DW_AT_decl_column(0x03) + + +$C$DW$T$989 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$989, DW_AT_name("EK_TM4C123GXL_SPIName") + .dwattr $C$DW$T$989, DW_AT_byte_size(0x01) +$C$DW$367 .dwtag DW_TAG_enumerator + .dwattr $C$DW$367, DW_AT_name("EK_TM4C123GXL_SPI0") + .dwattr $C$DW$367, DW_AT_const_value(0x00) + .dwattr $C$DW$367, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$367, DW_AT_decl_line(0x6b) + .dwattr $C$DW$367, DW_AT_decl_column(0x05) + +$C$DW$368 .dwtag DW_TAG_enumerator + .dwattr $C$DW$368, DW_AT_name("EK_TM4C123GXL_SPI2") + .dwattr $C$DW$368, DW_AT_const_value(0x01) + .dwattr $C$DW$368, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$368, DW_AT_decl_line(0x6c) + .dwattr $C$DW$368, DW_AT_decl_column(0x05) + +$C$DW$369 .dwtag DW_TAG_enumerator + .dwattr $C$DW$369, DW_AT_name("EK_TM4C123GXL_SPI3") + .dwattr $C$DW$369, DW_AT_const_value(0x02) + .dwattr $C$DW$369, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$369, DW_AT_decl_line(0x6d) + .dwattr $C$DW$369, DW_AT_decl_column(0x05) + +$C$DW$370 .dwtag DW_TAG_enumerator + .dwattr $C$DW$370, DW_AT_name("EK_TM4C123GXL_SPICOUNT") + .dwattr $C$DW$370, DW_AT_const_value(0x03) + .dwattr $C$DW$370, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$370, DW_AT_decl_line(0x6f) + .dwattr $C$DW$370, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$989, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$989, DW_AT_decl_line(0x6a) + .dwattr $C$DW$T$989, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$989 + +$C$DW$T$990 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$990, DW_AT_name("EK_TM4C123GXL_SPIName") + .dwattr $C$DW$T$990, DW_AT_type(*$C$DW$T$989) + .dwattr $C$DW$T$990, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$990, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$990, DW_AT_decl_line(0x70) + .dwattr $C$DW$T$990, DW_AT_decl_column(0x03) + + +$C$DW$T$991 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$991, DW_AT_name("EK_TM4C123GXL_UARTName") + .dwattr $C$DW$T$991, DW_AT_byte_size(0x01) +$C$DW$371 .dwtag DW_TAG_enumerator + .dwattr $C$DW$371, DW_AT_name("EK_TM4C123GXL_UART0") + .dwattr $C$DW$371, DW_AT_const_value(0x00) + .dwattr $C$DW$371, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$371, DW_AT_decl_line(0x77) + .dwattr $C$DW$371, DW_AT_decl_column(0x05) + +$C$DW$372 .dwtag DW_TAG_enumerator + .dwattr $C$DW$372, DW_AT_name("EK_TM4C123GXL_UARTCOUNT") + .dwattr $C$DW$372, DW_AT_const_value(0x01) + .dwattr $C$DW$372, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$372, DW_AT_decl_line(0x79) + .dwattr $C$DW$372, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$991, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$991, DW_AT_decl_line(0x76) + .dwattr $C$DW$T$991, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$991 + +$C$DW$T$992 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$992, DW_AT_name("EK_TM4C123GXL_UARTName") + .dwattr $C$DW$T$992, DW_AT_type(*$C$DW$T$991) + .dwattr $C$DW$T$992, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$992, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$992, DW_AT_decl_line(0x7a) + .dwattr $C$DW$T$992, DW_AT_decl_column(0x03) + + +$C$DW$T$993 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$993, DW_AT_name("EK_TM4C123GXL_USBMode") + .dwattr $C$DW$T$993, DW_AT_byte_size(0x01) +$C$DW$373 .dwtag DW_TAG_enumerator + .dwattr $C$DW$373, DW_AT_name("EK_TM4C123GXL_USBDEVICE") + .dwattr $C$DW$373, DW_AT_const_value(0x00) + .dwattr $C$DW$373, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$373, DW_AT_decl_line(0x81) + .dwattr $C$DW$373, DW_AT_decl_column(0x05) + +$C$DW$374 .dwtag DW_TAG_enumerator + .dwattr $C$DW$374, DW_AT_name("EK_TM4C123GXL_USBHOST") + .dwattr $C$DW$374, DW_AT_const_value(0x01) + .dwattr $C$DW$374, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$374, DW_AT_decl_line(0x82) + .dwattr $C$DW$374, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$993, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$993, DW_AT_decl_line(0x80) + .dwattr $C$DW$T$993, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$993 + +$C$DW$T$994 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$994, DW_AT_name("EK_TM4C123GXL_USBMode") + .dwattr $C$DW$T$994, DW_AT_type(*$C$DW$T$993) + .dwattr $C$DW$T$994, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$994, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$994, DW_AT_decl_line(0x83) + .dwattr $C$DW$T$994, DW_AT_decl_column(0x03) + + +$C$DW$T$995 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$995, DW_AT_name("EK_TM4C123GXL_WatchdogName") + .dwattr $C$DW$T$995, DW_AT_byte_size(0x01) +$C$DW$375 .dwtag DW_TAG_enumerator + .dwattr $C$DW$375, DW_AT_name("EK_TM4C123GXL_WATCHDOG0") + .dwattr $C$DW$375, DW_AT_const_value(0x00) + .dwattr $C$DW$375, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$375, DW_AT_decl_line(0x8a) + .dwattr $C$DW$375, DW_AT_decl_column(0x05) + +$C$DW$376 .dwtag DW_TAG_enumerator + .dwattr $C$DW$376, DW_AT_name("EK_TM4C123GXL_WATCHDOGCOUNT") + .dwattr $C$DW$376, DW_AT_const_value(0x01) + .dwattr $C$DW$376, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$376, DW_AT_decl_line(0x8c) + .dwattr $C$DW$376, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$995, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$995, DW_AT_decl_line(0x89) + .dwattr $C$DW$T$995, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$995 + +$C$DW$T$996 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$996, DW_AT_name("EK_TM4C123GXL_WatchdogName") + .dwattr $C$DW$T$996, DW_AT_type(*$C$DW$T$995) + .dwattr $C$DW$T$996, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$996, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$996, DW_AT_decl_line(0x8d) + .dwattr $C$DW$T$996, DW_AT_decl_column(0x03) + + +$C$DW$T$997 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$997, DW_AT_name("EK_TM4C123GXL_WiFiName") + .dwattr $C$DW$T$997, DW_AT_byte_size(0x01) +$C$DW$377 .dwtag DW_TAG_enumerator + .dwattr $C$DW$377, DW_AT_name("EK_TM4C123GXL_WIFI") + .dwattr $C$DW$377, DW_AT_const_value(0x00) + .dwattr $C$DW$377, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$377, DW_AT_decl_line(0x94) + .dwattr $C$DW$377, DW_AT_decl_column(0x05) + +$C$DW$378 .dwtag DW_TAG_enumerator + .dwattr $C$DW$378, DW_AT_name("EK_TM4C123GXL_WIFICOUNT") + .dwattr $C$DW$378, DW_AT_const_value(0x01) + .dwattr $C$DW$378, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$378, DW_AT_decl_line(0x96) + .dwattr $C$DW$378, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$997, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$997, DW_AT_decl_line(0x93) + .dwattr $C$DW$T$997, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$997 + +$C$DW$T$998 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$998, DW_AT_name("EK_TM4C123GXL_WiFiName") + .dwattr $C$DW$T$998, DW_AT_type(*$C$DW$T$997) + .dwattr $C$DW$T$998, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$998, DW_AT_decl_file("..\EK_TM4C123GXL.h") + .dwattr $C$DW$T$998, DW_AT_decl_line(0x97) + .dwattr $C$DW$T$998, DW_AT_decl_column(0x03) + + +$C$DW$T$198 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$198, DW_AT_name("GPIOTiva_Config") + .dwattr $C$DW$T$198, DW_AT_byte_size(0x14) +$C$DW$379 .dwtag DW_TAG_member + .dwattr $C$DW$379, DW_AT_type(*$C$DW$T$193) + .dwattr $C$DW$379, DW_AT_name("pinConfigs") + .dwattr $C$DW$379, DW_AT_TI_symbol_name("pinConfigs") + .dwattr $C$DW$379, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$379, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$379, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$379, DW_AT_decl_line(0xa7) + .dwattr $C$DW$379, DW_AT_decl_column(0x15) + +$C$DW$380 .dwtag DW_TAG_member + .dwattr $C$DW$380, DW_AT_type(*$C$DW$T$197) + .dwattr $C$DW$380, DW_AT_name("callbacks") + .dwattr $C$DW$380, DW_AT_TI_symbol_name("callbacks") + .dwattr $C$DW$380, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$380, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$380, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$380, DW_AT_decl_line(0xaa) + .dwattr $C$DW$380, DW_AT_decl_column(0x17) + +$C$DW$381 .dwtag DW_TAG_member + .dwattr $C$DW$381, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$381, DW_AT_name("numberOfPinConfigs") + .dwattr $C$DW$381, DW_AT_TI_symbol_name("numberOfPinConfigs") + .dwattr $C$DW$381, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$381, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$381, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$381, DW_AT_decl_line(0xad) + .dwattr $C$DW$381, DW_AT_decl_column(0x0e) + +$C$DW$382 .dwtag DW_TAG_member + .dwattr $C$DW$382, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$382, DW_AT_name("numberOfCallbacks") + .dwattr $C$DW$382, DW_AT_TI_symbol_name("numberOfCallbacks") + .dwattr $C$DW$382, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$382, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$382, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$382, DW_AT_decl_line(0xb0) + .dwattr $C$DW$382, DW_AT_decl_column(0x0e) + +$C$DW$383 .dwtag DW_TAG_member + .dwattr $C$DW$383, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$383, DW_AT_name("intPriority") + .dwattr $C$DW$383, DW_AT_TI_symbol_name("intPriority") + .dwattr $C$DW$383, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$383, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$383, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$383, DW_AT_decl_line(0xc0) + .dwattr $C$DW$383, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$198, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$T$198, DW_AT_decl_line(0xa5) + .dwattr $C$DW$T$198, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$198 + +$C$DW$T$999 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$999, DW_AT_name("GPIOTiva_Config") + .dwattr $C$DW$T$999, DW_AT_type(*$C$DW$T$198) + .dwattr $C$DW$T$999, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$999, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/gpio/GPIOTiva.h") + .dwattr $C$DW$T$999, DW_AT_decl_line(0xc1) + .dwattr $C$DW$T$999, DW_AT_decl_column(0x03) + +$C$DW$T$1000 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1000, DW_AT_type(*$C$DW$T$999) + + +$C$DW$T$199 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$199, DW_AT_name("I2CTiva_HWAttrs") + .dwattr $C$DW$T$199, DW_AT_byte_size(0x0c) +$C$DW$384 .dwtag DW_TAG_member + .dwattr $C$DW$384, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$384, DW_AT_name("baseAddr") + .dwattr $C$DW$384, DW_AT_TI_symbol_name("baseAddr") + .dwattr $C$DW$384, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$384, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$384, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$384, DW_AT_decl_line(0x90) + .dwattr $C$DW$384, DW_AT_decl_column(0x12) + +$C$DW$385 .dwtag DW_TAG_member + .dwattr $C$DW$385, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$385, DW_AT_name("intNum") + .dwattr $C$DW$385, DW_AT_TI_symbol_name("intNum") + .dwattr $C$DW$385, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$385, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$385, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$385, DW_AT_decl_line(0x92) + .dwattr $C$DW$385, DW_AT_decl_column(0x12) + +$C$DW$386 .dwtag DW_TAG_member + .dwattr $C$DW$386, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$386, DW_AT_name("intPriority") + .dwattr $C$DW$386, DW_AT_TI_symbol_name("intPriority") + .dwattr $C$DW$386, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$386, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$386, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$386, DW_AT_decl_line(0x94) + .dwattr $C$DW$386, DW_AT_decl_column(0x12) + + .dwattr $C$DW$T$199, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$T$199, DW_AT_decl_line(0x8e) + .dwattr $C$DW$T$199, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$199 + +$C$DW$T$1001 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1001, DW_AT_name("I2CTiva_HWAttrs") + .dwattr $C$DW$T$1001, DW_AT_type(*$C$DW$T$199) + .dwattr $C$DW$T$1001, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1001, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$T$1001, DW_AT_decl_line(0x95) + .dwattr $C$DW$T$1001, DW_AT_decl_column(0x03) + +$C$DW$T$1002 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1002, DW_AT_type(*$C$DW$T$1001) + + +$C$DW$T$1003 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1003, DW_AT_type(*$C$DW$T$1002) + .dwattr $C$DW$T$1003, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1003, DW_AT_byte_size(0x18) +$C$DW$387 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$387, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1003 + + +$C$DW$T$211 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$211, DW_AT_name("I2CTiva_Mode") + .dwattr $C$DW$T$211, DW_AT_byte_size(0x01) +$C$DW$388 .dwtag DW_TAG_enumerator + .dwattr $C$DW$388, DW_AT_name("I2CTiva_IDLE_MODE") + .dwattr $C$DW$388, DW_AT_const_value(0x00) + .dwattr $C$DW$388, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$388, DW_AT_decl_line(0x65) + .dwattr $C$DW$388, DW_AT_decl_column(0x05) + +$C$DW$389 .dwtag DW_TAG_enumerator + .dwattr $C$DW$389, DW_AT_name("I2CTiva_WRITE_MODE") + .dwattr $C$DW$389, DW_AT_const_value(0x01) + .dwattr $C$DW$389, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$389, DW_AT_decl_line(0x66) + .dwattr $C$DW$389, DW_AT_decl_column(0x05) + +$C$DW$390 .dwtag DW_TAG_enumerator + .dwattr $C$DW$390, DW_AT_name("I2CTiva_READ_MODE") + .dwattr $C$DW$390, DW_AT_const_value(0x02) + .dwattr $C$DW$390, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$390, DW_AT_decl_line(0x67) + .dwattr $C$DW$390, DW_AT_decl_column(0x05) + +$C$DW$391 .dwtag DW_TAG_enumerator + .dwattr $C$DW$391, DW_AT_name("I2CTiva_ERROR") + .dwattr $C$DW$391, DW_AT_const_value(0xff) + .dwattr $C$DW$391, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$391, DW_AT_decl_line(0x68) + .dwattr $C$DW$391, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$211, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$T$211, DW_AT_decl_line(0x64) + .dwattr $C$DW$T$211, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$211 + +$C$DW$T$212 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$212, DW_AT_name("I2CTiva_Mode") + .dwattr $C$DW$T$212, DW_AT_type(*$C$DW$T$211) + .dwattr $C$DW$T$212, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$212, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$T$212, DW_AT_decl_line(0x69) + .dwattr $C$DW$T$212, DW_AT_decl_column(0x03) + +$C$DW$T$213 .dwtag DW_TAG_volatile_type + .dwattr $C$DW$T$213, DW_AT_type(*$C$DW$T$212) + + +$C$DW$T$218 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$218, DW_AT_name("I2CTiva_Object") + .dwattr $C$DW$T$218, DW_AT_byte_size(0x80) +$C$DW$392 .dwtag DW_TAG_member + .dwattr $C$DW$392, DW_AT_type(*$C$DW$T$200) + .dwattr $C$DW$392, DW_AT_name("mutex") + .dwattr $C$DW$392, DW_AT_TI_symbol_name("mutex") + .dwattr $C$DW$392, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$392, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$392, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$392, DW_AT_decl_line(0x9d) + .dwattr $C$DW$392, DW_AT_decl_column(0x19) + +$C$DW$393 .dwtag DW_TAG_member + .dwattr $C$DW$393, DW_AT_type(*$C$DW$T$200) + .dwattr $C$DW$393, DW_AT_name("transferComplete") + .dwattr $C$DW$393, DW_AT_TI_symbol_name("transferComplete") + .dwattr $C$DW$393, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$393, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$393, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$393, DW_AT_decl_line(0x9e) + .dwattr $C$DW$393, DW_AT_decl_column(0x19) + +$C$DW$394 .dwtag DW_TAG_member + .dwattr $C$DW$394, DW_AT_type(*$C$DW$T$202) + .dwattr $C$DW$394, DW_AT_name("transferMode") + .dwattr $C$DW$394, DW_AT_TI_symbol_name("transferMode") + .dwattr $C$DW$394, DW_AT_data_member_location[DW_OP_plus_uconst 0x38] + .dwattr $C$DW$394, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$394, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$394, DW_AT_decl_line(0xa0) + .dwattr $C$DW$394, DW_AT_decl_column(0x19) + +$C$DW$395 .dwtag DW_TAG_member + .dwattr $C$DW$395, DW_AT_type(*$C$DW$T$209) + .dwattr $C$DW$395, DW_AT_name("transferCallbackFxn") + .dwattr $C$DW$395, DW_AT_TI_symbol_name("transferCallbackFxn") + .dwattr $C$DW$395, DW_AT_data_member_location[DW_OP_plus_uconst 0x3c] + .dwattr $C$DW$395, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$395, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$395, DW_AT_decl_line(0xa1) + .dwattr $C$DW$395, DW_AT_decl_column(0x19) + +$C$DW$396 .dwtag DW_TAG_member + .dwattr $C$DW$396, DW_AT_type(*$C$DW$T$210) + .dwattr $C$DW$396, DW_AT_name("hwi") + .dwattr $C$DW$396, DW_AT_TI_symbol_name("hwi") + .dwattr $C$DW$396, DW_AT_data_member_location[DW_OP_plus_uconst 0x40] + .dwattr $C$DW$396, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$396, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$396, DW_AT_decl_line(0xa3) + .dwattr $C$DW$396, DW_AT_decl_column(0x29) + +$C$DW$397 .dwtag DW_TAG_member + .dwattr $C$DW$397, DW_AT_type(*$C$DW$T$213) + .dwattr $C$DW$397, DW_AT_name("mode") + .dwattr $C$DW$397, DW_AT_TI_symbol_name("mode") + .dwattr $C$DW$397, DW_AT_data_member_location[DW_OP_plus_uconst 0x5c] + .dwattr $C$DW$397, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$397, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$397, DW_AT_decl_line(0xa5) + .dwattr $C$DW$397, DW_AT_decl_column(0x1b) + +$C$DW$398 .dwtag DW_TAG_member + .dwattr $C$DW$398, DW_AT_type(*$C$DW$T$206) + .dwattr $C$DW$398, DW_AT_name("currentTransaction") + .dwattr $C$DW$398, DW_AT_TI_symbol_name("currentTransaction") + .dwattr $C$DW$398, DW_AT_data_member_location[DW_OP_plus_uconst 0x60] + .dwattr $C$DW$398, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$398, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$398, DW_AT_decl_line(0xa7) + .dwattr $C$DW$398, DW_AT_decl_column(0x19) + +$C$DW$399 .dwtag DW_TAG_member + .dwattr $C$DW$399, DW_AT_type(*$C$DW$T$216) + .dwattr $C$DW$399, DW_AT_name("writeBufIdx") + .dwattr $C$DW$399, DW_AT_TI_symbol_name("writeBufIdx") + .dwattr $C$DW$399, DW_AT_data_member_location[DW_OP_plus_uconst 0x64] + .dwattr $C$DW$399, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$399, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$399, DW_AT_decl_line(0xa9) + .dwattr $C$DW$399, DW_AT_decl_column(0x19) + +$C$DW$400 .dwtag DW_TAG_member + .dwattr $C$DW$400, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$400, DW_AT_name("writeCountIdx") + .dwattr $C$DW$400, DW_AT_TI_symbol_name("writeCountIdx") + .dwattr $C$DW$400, DW_AT_data_member_location[DW_OP_plus_uconst 0x68] + .dwattr $C$DW$400, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$400, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$400, DW_AT_decl_line(0xaa) + .dwattr $C$DW$400, DW_AT_decl_column(0x19) + +$C$DW$401 .dwtag DW_TAG_member + .dwattr $C$DW$401, DW_AT_type(*$C$DW$T$216) + .dwattr $C$DW$401, DW_AT_name("readBufIdx") + .dwattr $C$DW$401, DW_AT_TI_symbol_name("readBufIdx") + .dwattr $C$DW$401, DW_AT_data_member_location[DW_OP_plus_uconst 0x6c] + .dwattr $C$DW$401, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$401, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$401, DW_AT_decl_line(0xac) + .dwattr $C$DW$401, DW_AT_decl_column(0x19) + +$C$DW$402 .dwtag DW_TAG_member + .dwattr $C$DW$402, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$402, DW_AT_name("readCountIdx") + .dwattr $C$DW$402, DW_AT_TI_symbol_name("readCountIdx") + .dwattr $C$DW$402, DW_AT_data_member_location[DW_OP_plus_uconst 0x70] + .dwattr $C$DW$402, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$402, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$402, DW_AT_decl_line(0xad) + .dwattr $C$DW$402, DW_AT_decl_column(0x19) + +$C$DW$403 .dwtag DW_TAG_member + .dwattr $C$DW$403, DW_AT_type(*$C$DW$T$206) + .dwattr $C$DW$403, DW_AT_name("headPtr") + .dwattr $C$DW$403, DW_AT_TI_symbol_name("headPtr") + .dwattr $C$DW$403, DW_AT_data_member_location[DW_OP_plus_uconst 0x74] + .dwattr $C$DW$403, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$403, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$403, DW_AT_decl_line(0xb0) + .dwattr $C$DW$403, DW_AT_decl_column(0x19) + +$C$DW$404 .dwtag DW_TAG_member + .dwattr $C$DW$404, DW_AT_type(*$C$DW$T$206) + .dwattr $C$DW$404, DW_AT_name("tailPtr") + .dwattr $C$DW$404, DW_AT_TI_symbol_name("tailPtr") + .dwattr $C$DW$404, DW_AT_data_member_location[DW_OP_plus_uconst 0x78] + .dwattr $C$DW$404, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$404, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$404, DW_AT_decl_line(0xb1) + .dwattr $C$DW$404, DW_AT_decl_column(0x19) + +$C$DW$405 .dwtag DW_TAG_member + .dwattr $C$DW$405, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$405, DW_AT_name("isOpen") + .dwattr $C$DW$405, DW_AT_TI_symbol_name("isOpen") + .dwattr $C$DW$405, DW_AT_data_member_location[DW_OP_plus_uconst 0x7c] + .dwattr $C$DW$405, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$405, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$405, DW_AT_decl_line(0xb3) + .dwattr $C$DW$405, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$218, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$T$218, DW_AT_decl_line(0x9c) + .dwattr $C$DW$T$218, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$218 + +$C$DW$T$1005 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1005, DW_AT_name("I2CTiva_Object") + .dwattr $C$DW$T$1005, DW_AT_type(*$C$DW$T$218) + .dwattr $C$DW$T$1005, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1005, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/i2c/I2CTiva.h") + .dwattr $C$DW$T$1005, DW_AT_decl_line(0xb4) + .dwattr $C$DW$T$1005, DW_AT_decl_column(0x03) + + +$C$DW$T$1006 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1006, DW_AT_type(*$C$DW$T$1005) + .dwattr $C$DW$T$1006, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1006, DW_AT_byte_size(0x100) +$C$DW$406 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$406, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1006 + + +$C$DW$T$241 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$241, DW_AT_name("I2C_BitRate") + .dwattr $C$DW$T$241, DW_AT_byte_size(0x01) +$C$DW$407 .dwtag DW_TAG_enumerator + .dwattr $C$DW$407, DW_AT_name("I2C_100kHz") + .dwattr $C$DW$407, DW_AT_const_value(0x00) + .dwattr $C$DW$407, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$407, DW_AT_decl_line(0x115) + .dwattr $C$DW$407, DW_AT_decl_column(0x05) + +$C$DW$408 .dwtag DW_TAG_enumerator + .dwattr $C$DW$408, DW_AT_name("I2C_400kHz") + .dwattr $C$DW$408, DW_AT_const_value(0x01) + .dwattr $C$DW$408, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$408, DW_AT_decl_line(0x116) + .dwattr $C$DW$408, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$241, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$241, DW_AT_decl_line(0x114) + .dwattr $C$DW$T$241, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$241 + +$C$DW$T$242 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$242, DW_AT_name("I2C_BitRate") + .dwattr $C$DW$T$242, DW_AT_type(*$C$DW$T$241) + .dwattr $C$DW$T$242, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$242, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$242, DW_AT_decl_line(0x117) + .dwattr $C$DW$T$242, DW_AT_decl_column(0x03) + + +$C$DW$T$224 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$224, DW_AT_name("I2C_Config") + .dwattr $C$DW$T$224, DW_AT_byte_size(0x0c) +$C$DW$409 .dwtag DW_TAG_member + .dwattr $C$DW$409, DW_AT_type(*$C$DW$T$221) + .dwattr $C$DW$409, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$409, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$409, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$409, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$409, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$409, DW_AT_decl_line(0x17a) + .dwattr $C$DW$409, DW_AT_decl_column(0x19) + +$C$DW$410 .dwtag DW_TAG_member + .dwattr $C$DW$410, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$410, DW_AT_name("object") + .dwattr $C$DW$410, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$410, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$410, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$410, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$410, DW_AT_decl_line(0x17d) + .dwattr $C$DW$410, DW_AT_decl_column(0x19) + +$C$DW$411 .dwtag DW_TAG_member + .dwattr $C$DW$411, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$411, DW_AT_name("hwAttrs") + .dwattr $C$DW$411, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$411, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$411, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$411, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$411, DW_AT_decl_line(0x180) + .dwattr $C$DW$411, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$224, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$224, DW_AT_decl_line(0x178) + .dwattr $C$DW$T$224, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$224 + +$C$DW$T$1008 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1008, DW_AT_name("I2C_Config") + .dwattr $C$DW$T$1008, DW_AT_type(*$C$DW$T$224) + .dwattr $C$DW$T$1008, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1008, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$1008, DW_AT_decl_line(0x181) + .dwattr $C$DW$T$1008, DW_AT_decl_column(0x03) + +$C$DW$T$1009 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1009, DW_AT_type(*$C$DW$T$1008) + + +$C$DW$T$1010 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1010, DW_AT_type(*$C$DW$T$1009) + .dwattr $C$DW$T$1010, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1010, DW_AT_byte_size(0x24) +$C$DW$412 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$412, DW_AT_upper_bound(0x02) + + .dwendtag $C$DW$T$1010 + +$C$DW$T$203 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$203, DW_AT_type(*$C$DW$T$224) + .dwattr $C$DW$T$203, DW_AT_address_class(0x20) + +$C$DW$T$204 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$204, DW_AT_name("I2C_Handle") + .dwattr $C$DW$T$204, DW_AT_type(*$C$DW$T$203) + .dwattr $C$DW$T$204, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$204, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$204, DW_AT_decl_line(0xda) + .dwattr $C$DW$T$204, DW_AT_decl_column(0x21) + + +$C$DW$T$234 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$234, DW_AT_type(*$C$DW$T$204) + .dwattr $C$DW$T$234, DW_AT_language(DW_LANG_C) +$C$DW$413 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$413, DW_AT_type(*$C$DW$T$204) + +$C$DW$414 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$414, DW_AT_type(*$C$DW$T$233) + + .dwendtag $C$DW$T$234 + +$C$DW$T$235 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$235, DW_AT_type(*$C$DW$T$234) + .dwattr $C$DW$T$235, DW_AT_address_class(0x20) + +$C$DW$T$236 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$236, DW_AT_name("I2C_OpenFxn") + .dwattr $C$DW$T$236, DW_AT_type(*$C$DW$T$235) + .dwattr $C$DW$T$236, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$236, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$236, DW_AT_decl_line(0x14d) + .dwattr $C$DW$T$236, DW_AT_decl_column(0x17) + + +$C$DW$T$240 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$240, DW_AT_name("I2C_FxnTable") + .dwattr $C$DW$T$240, DW_AT_byte_size(0x14) +$C$DW$415 .dwtag DW_TAG_member + .dwattr $C$DW$415, DW_AT_type(*$C$DW$T$227) + .dwattr $C$DW$415, DW_AT_name("closeFxn") + .dwattr $C$DW$415, DW_AT_TI_symbol_name("closeFxn") + .dwattr $C$DW$415, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$415, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$415, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$415, DW_AT_decl_line(0x15e) + .dwattr $C$DW$415, DW_AT_decl_column(0x19) + +$C$DW$416 .dwtag DW_TAG_member + .dwattr $C$DW$416, DW_AT_type(*$C$DW$T$230) + .dwattr $C$DW$416, DW_AT_name("controlFxn") + .dwattr $C$DW$416, DW_AT_TI_symbol_name("controlFxn") + .dwattr $C$DW$416, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$416, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$416, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$416, DW_AT_decl_line(0x161) + .dwattr $C$DW$416, DW_AT_decl_column(0x19) + +$C$DW$417 .dwtag DW_TAG_member + .dwattr $C$DW$417, DW_AT_type(*$C$DW$T$231) + .dwattr $C$DW$417, DW_AT_name("initFxn") + .dwattr $C$DW$417, DW_AT_TI_symbol_name("initFxn") + .dwattr $C$DW$417, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$417, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$417, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$417, DW_AT_decl_line(0x164) + .dwattr $C$DW$417, DW_AT_decl_column(0x19) + +$C$DW$418 .dwtag DW_TAG_member + .dwattr $C$DW$418, DW_AT_type(*$C$DW$T$236) + .dwattr $C$DW$418, DW_AT_name("openFxn") + .dwattr $C$DW$418, DW_AT_TI_symbol_name("openFxn") + .dwattr $C$DW$418, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$418, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$418, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$418, DW_AT_decl_line(0x167) + .dwattr $C$DW$418, DW_AT_decl_column(0x19) + +$C$DW$419 .dwtag DW_TAG_member + .dwattr $C$DW$419, DW_AT_type(*$C$DW$T$239) + .dwattr $C$DW$419, DW_AT_name("transferFxn") + .dwattr $C$DW$419, DW_AT_TI_symbol_name("transferFxn") + .dwattr $C$DW$419, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$419, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$419, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$419, DW_AT_decl_line(0x16a) + .dwattr $C$DW$419, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$240, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$240, DW_AT_decl_line(0x15c) + .dwattr $C$DW$T$240, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$240 + +$C$DW$T$219 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$219, DW_AT_name("I2C_FxnTable") + .dwattr $C$DW$T$219, DW_AT_type(*$C$DW$T$240) + .dwattr $C$DW$T$219, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$219, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$219, DW_AT_decl_line(0x16b) + .dwattr $C$DW$T$219, DW_AT_decl_column(0x03) + +$C$DW$T$220 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$220, DW_AT_type(*$C$DW$T$219) + +$C$DW$T$221 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$221, DW_AT_type(*$C$DW$T$220) + .dwattr $C$DW$T$221, DW_AT_address_class(0x20) + + +$C$DW$T$245 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$245, DW_AT_name("I2C_Params") + .dwattr $C$DW$T$245, DW_AT_byte_size(0x10) +$C$DW$420 .dwtag DW_TAG_member + .dwattr $C$DW$420, DW_AT_type(*$C$DW$T$202) + .dwattr $C$DW$420, DW_AT_name("transferMode") + .dwattr $C$DW$420, DW_AT_TI_symbol_name("transferMode") + .dwattr $C$DW$420, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$420, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$420, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$420, DW_AT_decl_line(0x12e) + .dwattr $C$DW$420, DW_AT_decl_column(0x19) + +$C$DW$421 .dwtag DW_TAG_member + .dwattr $C$DW$421, DW_AT_type(*$C$DW$T$209) + .dwattr $C$DW$421, DW_AT_name("transferCallbackFxn") + .dwattr $C$DW$421, DW_AT_TI_symbol_name("transferCallbackFxn") + .dwattr $C$DW$421, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$421, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$421, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$421, DW_AT_decl_line(0x12f) + .dwattr $C$DW$421, DW_AT_decl_column(0x19) + +$C$DW$422 .dwtag DW_TAG_member + .dwattr $C$DW$422, DW_AT_type(*$C$DW$T$242) + .dwattr $C$DW$422, DW_AT_name("bitRate") + .dwattr $C$DW$422, DW_AT_TI_symbol_name("bitRate") + .dwattr $C$DW$422, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$422, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$422, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$422, DW_AT_decl_line(0x130) + .dwattr $C$DW$422, DW_AT_decl_column(0x19) + +$C$DW$423 .dwtag DW_TAG_member + .dwattr $C$DW$423, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$423, DW_AT_name("custom") + .dwattr $C$DW$423, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$423, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$423, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$423, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$423, DW_AT_decl_line(0x131) + .dwattr $C$DW$423, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$245, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$245, DW_AT_decl_line(0x12d) + .dwattr $C$DW$T$245, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$245 + +$C$DW$T$232 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$232, DW_AT_name("I2C_Params") + .dwattr $C$DW$T$232, DW_AT_type(*$C$DW$T$245) + .dwattr $C$DW$T$232, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$232, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$232, DW_AT_decl_line(0x133) + .dwattr $C$DW$T$232, DW_AT_decl_column(0x03) + +$C$DW$T$233 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$233, DW_AT_type(*$C$DW$T$232) + .dwattr $C$DW$T$233, DW_AT_address_class(0x20) + + +$C$DW$T$246 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$246, DW_AT_name("I2C_Transaction") + .dwattr $C$DW$T$246, DW_AT_byte_size(0x1c) +$C$DW$424 .dwtag DW_TAG_member + .dwattr $C$DW$424, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$424, DW_AT_name("writeBuf") + .dwattr $C$DW$424, DW_AT_TI_symbol_name("writeBuf") + .dwattr $C$DW$424, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$424, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$424, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$424, DW_AT_decl_line(0xe7) + .dwattr $C$DW$424, DW_AT_decl_column(0x0e) + +$C$DW$425 .dwtag DW_TAG_member + .dwattr $C$DW$425, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$425, DW_AT_name("writeCount") + .dwattr $C$DW$425, DW_AT_TI_symbol_name("writeCount") + .dwattr $C$DW$425, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$425, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$425, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$425, DW_AT_decl_line(0xe8) + .dwattr $C$DW$425, DW_AT_decl_column(0x0d) + +$C$DW$426 .dwtag DW_TAG_member + .dwattr $C$DW$426, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$426, DW_AT_name("readBuf") + .dwattr $C$DW$426, DW_AT_TI_symbol_name("readBuf") + .dwattr $C$DW$426, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$426, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$426, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$426, DW_AT_decl_line(0xea) + .dwattr $C$DW$426, DW_AT_decl_column(0x0e) + +$C$DW$427 .dwtag DW_TAG_member + .dwattr $C$DW$427, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$427, DW_AT_name("readCount") + .dwattr $C$DW$427, DW_AT_TI_symbol_name("readCount") + .dwattr $C$DW$427, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$427, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$427, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$427, DW_AT_decl_line(0xeb) + .dwattr $C$DW$427, DW_AT_decl_column(0x0d) + +$C$DW$428 .dwtag DW_TAG_member + .dwattr $C$DW$428, DW_AT_type(*$C$DW$T$6) + .dwattr $C$DW$428, DW_AT_name("slaveAddress") + .dwattr $C$DW$428, DW_AT_TI_symbol_name("slaveAddress") + .dwattr $C$DW$428, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$428, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$428, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$428, DW_AT_decl_line(0xed) + .dwattr $C$DW$428, DW_AT_decl_column(0x13) + +$C$DW$429 .dwtag DW_TAG_member + .dwattr $C$DW$429, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$429, DW_AT_name("arg") + .dwattr $C$DW$429, DW_AT_TI_symbol_name("arg") + .dwattr $C$DW$429, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$429, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$429, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$429, DW_AT_decl_line(0xef) + .dwattr $C$DW$429, DW_AT_decl_column(0x0e) + +$C$DW$430 .dwtag DW_TAG_member + .dwattr $C$DW$430, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$430, DW_AT_name("nextPtr") + .dwattr $C$DW$430, DW_AT_TI_symbol_name("nextPtr") + .dwattr $C$DW$430, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$430, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$430, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$430, DW_AT_decl_line(0xf0) + .dwattr $C$DW$430, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$246, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$246, DW_AT_decl_line(0xe6) + .dwattr $C$DW$T$246, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$246 + +$C$DW$T$205 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$205, DW_AT_name("I2C_Transaction") + .dwattr $C$DW$T$205, DW_AT_type(*$C$DW$T$246) + .dwattr $C$DW$T$205, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$205, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$205, DW_AT_decl_line(0xf1) + .dwattr $C$DW$T$205, DW_AT_decl_column(0x03) + +$C$DW$T$206 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$206, DW_AT_type(*$C$DW$T$205) + .dwattr $C$DW$T$206, DW_AT_address_class(0x20) + + +$C$DW$T$201 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$201, DW_AT_name("I2C_TransferMode") + .dwattr $C$DW$T$201, DW_AT_byte_size(0x01) +$C$DW$431 .dwtag DW_TAG_enumerator + .dwattr $C$DW$431, DW_AT_name("I2C_MODE_BLOCKING") + .dwattr $C$DW$431, DW_AT_const_value(0x00) + .dwattr $C$DW$431, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$431, DW_AT_decl_line(0xfb) + .dwattr $C$DW$431, DW_AT_decl_column(0x05) + +$C$DW$432 .dwtag DW_TAG_enumerator + .dwattr $C$DW$432, DW_AT_name("I2C_MODE_CALLBACK") + .dwattr $C$DW$432, DW_AT_const_value(0x01) + .dwattr $C$DW$432, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$432, DW_AT_decl_line(0xfc) + .dwattr $C$DW$432, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$201, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$201, DW_AT_decl_line(0xfa) + .dwattr $C$DW$T$201, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$201 + +$C$DW$T$202 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$202, DW_AT_name("I2C_TransferMode") + .dwattr $C$DW$T$202, DW_AT_type(*$C$DW$T$201) + .dwattr $C$DW$T$202, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$202, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$202, DW_AT_decl_line(0xfd) + .dwattr $C$DW$T$202, DW_AT_decl_column(0x03) + + +$C$DW$T$247 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$247, DW_AT_name("PWMTiva_HWAttrs") + .dwattr $C$DW$T$247, DW_AT_byte_size(0x0c) +$C$DW$433 .dwtag DW_TAG_member + .dwattr $C$DW$433, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$433, DW_AT_name("baseAddr") + .dwattr $C$DW$433, DW_AT_TI_symbol_name("baseAddr") + .dwattr $C$DW$433, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$433, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$433, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$433, DW_AT_decl_line(0xad) + .dwattr $C$DW$433, DW_AT_decl_column(0x0e) + +$C$DW$434 .dwtag DW_TAG_member + .dwattr $C$DW$434, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$434, DW_AT_name("pwmOutput") + .dwattr $C$DW$434, DW_AT_TI_symbol_name("pwmOutput") + .dwattr $C$DW$434, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$434, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$434, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$434, DW_AT_decl_line(0xae) + .dwattr $C$DW$434, DW_AT_decl_column(0x0e) + +$C$DW$435 .dwtag DW_TAG_member + .dwattr $C$DW$435, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$435, DW_AT_name("pwmGenOpts") + .dwattr $C$DW$435, DW_AT_TI_symbol_name("pwmGenOpts") + .dwattr $C$DW$435, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$435, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$435, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$435, DW_AT_decl_line(0xaf) + .dwattr $C$DW$435, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$247, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$T$247, DW_AT_decl_line(0xac) + .dwattr $C$DW$T$247, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$247 + +$C$DW$T$1011 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1011, DW_AT_name("PWMTiva_HWAttrs") + .dwattr $C$DW$T$1011, DW_AT_type(*$C$DW$T$247) + .dwattr $C$DW$T$1011, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1011, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$T$1011, DW_AT_decl_line(0xb0) + .dwattr $C$DW$T$1011, DW_AT_decl_column(0x03) + +$C$DW$T$1012 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1012, DW_AT_type(*$C$DW$T$1011) + + +$C$DW$T$1013 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1013, DW_AT_type(*$C$DW$T$1012) + .dwattr $C$DW$T$1013, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1013, DW_AT_byte_size(0x18) +$C$DW$436 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$436, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1013 + + +$C$DW$T$252 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$252, DW_AT_name("PWMTiva_Object") + .dwattr $C$DW$T$252, DW_AT_byte_size(0x08) +$C$DW$437 .dwtag DW_TAG_member + .dwattr $C$DW$437, DW_AT_type(*$C$DW$T$249) + .dwattr $C$DW$437, DW_AT_name("pwmStatus") + .dwattr $C$DW$437, DW_AT_TI_symbol_name("pwmStatus") + .dwattr $C$DW$437, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$437, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$437, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$437, DW_AT_decl_line(0xc4) + .dwattr $C$DW$437, DW_AT_decl_column(0x15) + +$C$DW$438 .dwtag DW_TAG_member + .dwattr $C$DW$438, DW_AT_type(*$C$DW$T$251) + .dwattr $C$DW$438, DW_AT_name("pwmDuty") + .dwattr $C$DW$438, DW_AT_TI_symbol_name("pwmDuty") + .dwattr $C$DW$438, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$438, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$438, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$438, DW_AT_decl_line(0xc5) + .dwattr $C$DW$438, DW_AT_decl_column(0x15) + +$C$DW$439 .dwtag DW_TAG_member + .dwattr $C$DW$439, DW_AT_type(*$C$DW$T$215) + .dwattr $C$DW$439, DW_AT_name("pwmOutputBit") + .dwattr $C$DW$439, DW_AT_TI_symbol_name("pwmOutputBit") + .dwattr $C$DW$439, DW_AT_data_member_location[DW_OP_plus_uconst 0x6] + .dwattr $C$DW$439, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$439, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$439, DW_AT_decl_line(0xc6) + .dwattr $C$DW$439, DW_AT_decl_column(0x15) + +$C$DW$440 .dwtag DW_TAG_member + .dwattr $C$DW$440, DW_AT_type(*$C$DW$T$215) + .dwattr $C$DW$440, DW_AT_name("dutyMode") + .dwattr $C$DW$440, DW_AT_TI_symbol_name("dutyMode") + .dwattr $C$DW$440, DW_AT_data_member_location[DW_OP_plus_uconst 0x7] + .dwattr $C$DW$440, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$440, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$440, DW_AT_decl_line(0xc7) + .dwattr $C$DW$440, DW_AT_decl_column(0x15) + + .dwattr $C$DW$T$252, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$T$252, DW_AT_decl_line(0xc3) + .dwattr $C$DW$T$252, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$252 + +$C$DW$T$1015 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1015, DW_AT_name("PWMTiva_Object") + .dwattr $C$DW$T$1015, DW_AT_type(*$C$DW$T$252) + .dwattr $C$DW$T$1015, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1015, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$T$1015, DW_AT_decl_line(0xc8) + .dwattr $C$DW$T$1015, DW_AT_decl_column(0x03) + + +$C$DW$T$1016 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1016, DW_AT_type(*$C$DW$T$1015) + .dwattr $C$DW$T$1016, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1016, DW_AT_byte_size(0x10) +$C$DW$441 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$441, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1016 + + +$C$DW$T$254 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$254, DW_AT_name("PWMTiva_Status") + .dwattr $C$DW$T$254, DW_AT_byte_size(0x0c) +$C$DW$442 .dwtag DW_TAG_member + .dwattr $C$DW$442, DW_AT_type(*$C$DW$T$253) + .dwattr $C$DW$442, DW_AT_name("genPeriods") + .dwattr $C$DW$442, DW_AT_TI_symbol_name("genPeriods") + .dwattr $C$DW$442, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$442, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$442, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$442, DW_AT_decl_line(0xb8) + .dwattr $C$DW$442, DW_AT_decl_column(0x0e) + +$C$DW$443 .dwtag DW_TAG_member + .dwattr $C$DW$443, DW_AT_type(*$C$DW$T$215) + .dwattr $C$DW$443, DW_AT_name("cyclesPerMicroSec") + .dwattr $C$DW$443, DW_AT_TI_symbol_name("cyclesPerMicroSec") + .dwattr $C$DW$443, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$443, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$443, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$443, DW_AT_decl_line(0xb9) + .dwattr $C$DW$443, DW_AT_decl_column(0x0e) + +$C$DW$444 .dwtag DW_TAG_member + .dwattr $C$DW$444, DW_AT_type(*$C$DW$T$215) + .dwattr $C$DW$444, DW_AT_name("prescalar") + .dwattr $C$DW$444, DW_AT_TI_symbol_name("prescalar") + .dwattr $C$DW$444, DW_AT_data_member_location[DW_OP_plus_uconst 0x9] + .dwattr $C$DW$444, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$444, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$444, DW_AT_decl_line(0xba) + .dwattr $C$DW$444, DW_AT_decl_column(0x0e) + +$C$DW$445 .dwtag DW_TAG_member + .dwattr $C$DW$445, DW_AT_type(*$C$DW$T$215) + .dwattr $C$DW$445, DW_AT_name("activeOutputs") + .dwattr $C$DW$445, DW_AT_TI_symbol_name("activeOutputs") + .dwattr $C$DW$445, DW_AT_data_member_location[DW_OP_plus_uconst 0xa] + .dwattr $C$DW$445, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$445, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$445, DW_AT_decl_line(0xbb) + .dwattr $C$DW$445, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$254, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$T$254, DW_AT_decl_line(0xb7) + .dwattr $C$DW$T$254, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$254 + +$C$DW$T$248 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$248, DW_AT_name("PWMTiva_Status") + .dwattr $C$DW$T$248, DW_AT_type(*$C$DW$T$254) + .dwattr $C$DW$T$248, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$248, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h") + .dwattr $C$DW$T$248, DW_AT_decl_line(0xbc) + .dwattr $C$DW$T$248, DW_AT_decl_column(0x03) + +$C$DW$T$249 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$249, DW_AT_type(*$C$DW$T$248) + .dwattr $C$DW$T$249, DW_AT_address_class(0x20) + + +$C$DW$T$258 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$258, DW_AT_name("PWM_Config") + .dwattr $C$DW$T$258, DW_AT_byte_size(0x0c) +$C$DW$446 .dwtag DW_TAG_member + .dwattr $C$DW$446, DW_AT_type(*$C$DW$T$257) + .dwattr $C$DW$446, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$446, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$446, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$446, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$446, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$446, DW_AT_decl_line(0x181) + .dwattr $C$DW$446, DW_AT_decl_column(0x19) + +$C$DW$447 .dwtag DW_TAG_member + .dwattr $C$DW$447, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$447, DW_AT_name("object") + .dwattr $C$DW$447, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$447, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$447, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$447, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$447, DW_AT_decl_line(0x184) + .dwattr $C$DW$447, DW_AT_decl_column(0x19) + +$C$DW$448 .dwtag DW_TAG_member + .dwattr $C$DW$448, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$448, DW_AT_name("hwAttrs") + .dwattr $C$DW$448, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$448, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$448, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$448, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$448, DW_AT_decl_line(0x187) + .dwattr $C$DW$448, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$258, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$258, DW_AT_decl_line(0x17f) + .dwattr $C$DW$T$258, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$258 + +$C$DW$T$1018 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1018, DW_AT_name("PWM_Config") + .dwattr $C$DW$T$1018, DW_AT_type(*$C$DW$T$258) + .dwattr $C$DW$T$1018, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1018, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$1018, DW_AT_decl_line(0x188) + .dwattr $C$DW$T$1018, DW_AT_decl_column(0x03) + +$C$DW$T$1019 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1019, DW_AT_type(*$C$DW$T$1018) + + +$C$DW$T$1020 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1020, DW_AT_type(*$C$DW$T$1019) + .dwattr $C$DW$T$1020, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1020, DW_AT_byte_size(0x24) +$C$DW$449 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$449, DW_AT_upper_bound(0x02) + + .dwendtag $C$DW$T$1020 + +$C$DW$T$259 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$259, DW_AT_type(*$C$DW$T$258) + .dwattr $C$DW$T$259, DW_AT_address_class(0x20) + +$C$DW$T$260 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$260, DW_AT_name("PWM_Handle") + .dwattr $C$DW$T$260, DW_AT_type(*$C$DW$T$259) + .dwattr $C$DW$T$260, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$260, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$260, DW_AT_decl_line(0x105) + .dwattr $C$DW$T$260, DW_AT_decl_column(0x21) + + +$C$DW$T$274 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$274, DW_AT_type(*$C$DW$T$260) + .dwattr $C$DW$T$274, DW_AT_language(DW_LANG_C) +$C$DW$450 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$450, DW_AT_type(*$C$DW$T$260) + +$C$DW$451 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$451, DW_AT_type(*$C$DW$T$273) + + .dwendtag $C$DW$T$274 + +$C$DW$T$275 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$275, DW_AT_type(*$C$DW$T$274) + .dwattr $C$DW$T$275, DW_AT_address_class(0x20) + +$C$DW$T$276 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$276, DW_AT_name("PWM_OpenFxn") + .dwattr $C$DW$T$276, DW_AT_type(*$C$DW$T$275) + .dwattr $C$DW$T$276, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$276, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$276, DW_AT_decl_line(0x14e) + .dwattr $C$DW$T$276, DW_AT_decl_column(0x18) + + +$C$DW$T$281 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$281, DW_AT_name("PWM_DutyMode") + .dwattr $C$DW$T$281, DW_AT_byte_size(0x01) +$C$DW$452 .dwtag DW_TAG_enumerator + .dwattr $C$DW$452, DW_AT_name("PWM_DUTY_COUNTS") + .dwattr $C$DW$452, DW_AT_const_value(0x00) + .dwattr $C$DW$452, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$452, DW_AT_decl_line(0x10c) + .dwattr $C$DW$452, DW_AT_decl_column(0x05) + +$C$DW$453 .dwtag DW_TAG_enumerator + .dwattr $C$DW$453, DW_AT_name("PWM_DUTY_SCALAR") + .dwattr $C$DW$453, DW_AT_const_value(0x01) + .dwattr $C$DW$453, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$453, DW_AT_decl_line(0x10d) + .dwattr $C$DW$453, DW_AT_decl_column(0x05) + +$C$DW$454 .dwtag DW_TAG_enumerator + .dwattr $C$DW$454, DW_AT_name("PWM_DUTY_TIME") + .dwattr $C$DW$454, DW_AT_const_value(0x02) + .dwattr $C$DW$454, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$454, DW_AT_decl_line(0x10e) + .dwattr $C$DW$454, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$281, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$281, DW_AT_decl_line(0x10b) + .dwattr $C$DW$T$281, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$281 + +$C$DW$T$282 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$282, DW_AT_name("PWM_DutyMode") + .dwattr $C$DW$T$282, DW_AT_type(*$C$DW$T$281) + .dwattr $C$DW$T$282, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$282, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$282, DW_AT_decl_line(0x10f) + .dwattr $C$DW$T$282, DW_AT_decl_column(0x03) + + +$C$DW$T$280 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$280, DW_AT_name("PWM_FxnTable") + .dwattr $C$DW$T$280, DW_AT_byte_size(0x1c) +$C$DW$455 .dwtag DW_TAG_member + .dwattr $C$DW$455, DW_AT_type(*$C$DW$T$263) + .dwattr $C$DW$455, DW_AT_name("closeFxn") + .dwattr $C$DW$455, DW_AT_TI_symbol_name("closeFxn") + .dwattr $C$DW$455, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$455, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$455, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$455, DW_AT_decl_line(0x15f) + .dwattr $C$DW$455, DW_AT_decl_column(0x22) + +$C$DW$456 .dwtag DW_TAG_member + .dwattr $C$DW$456, DW_AT_type(*$C$DW$T$266) + .dwattr $C$DW$456, DW_AT_name("controlFxn") + .dwattr $C$DW$456, DW_AT_TI_symbol_name("controlFxn") + .dwattr $C$DW$456, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$456, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$456, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$456, DW_AT_decl_line(0x162) + .dwattr $C$DW$456, DW_AT_decl_column(0x22) + +$C$DW$457 .dwtag DW_TAG_member + .dwattr $C$DW$457, DW_AT_type(*$C$DW$T$269) + .dwattr $C$DW$457, DW_AT_name("getPeriodCountsFxn") + .dwattr $C$DW$457, DW_AT_TI_symbol_name("getPeriodCountsFxn") + .dwattr $C$DW$457, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$457, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$457, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$457, DW_AT_decl_line(0x165) + .dwattr $C$DW$457, DW_AT_decl_column(0x22) + +$C$DW$458 .dwtag DW_TAG_member + .dwattr $C$DW$458, DW_AT_type(*$C$DW$T$270) + .dwattr $C$DW$458, DW_AT_name("getPeriodMicroSecsFxn") + .dwattr $C$DW$458, DW_AT_TI_symbol_name("getPeriodMicroSecsFxn") + .dwattr $C$DW$458, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$458, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$458, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$458, DW_AT_decl_line(0x168) + .dwattr $C$DW$458, DW_AT_decl_column(0x22) + +$C$DW$459 .dwtag DW_TAG_member + .dwattr $C$DW$459, DW_AT_type(*$C$DW$T$271) + .dwattr $C$DW$459, DW_AT_name("initFxn") + .dwattr $C$DW$459, DW_AT_TI_symbol_name("initFxn") + .dwattr $C$DW$459, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$459, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$459, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$459, DW_AT_decl_line(0x16b) + .dwattr $C$DW$459, DW_AT_decl_column(0x22) + +$C$DW$460 .dwtag DW_TAG_member + .dwattr $C$DW$460, DW_AT_type(*$C$DW$T$276) + .dwattr $C$DW$460, DW_AT_name("openFxn") + .dwattr $C$DW$460, DW_AT_TI_symbol_name("openFxn") + .dwattr $C$DW$460, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$460, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$460, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$460, DW_AT_decl_line(0x16e) + .dwattr $C$DW$460, DW_AT_decl_column(0x22) + +$C$DW$461 .dwtag DW_TAG_member + .dwattr $C$DW$461, DW_AT_type(*$C$DW$T$279) + .dwattr $C$DW$461, DW_AT_name("setDutyFxn") + .dwattr $C$DW$461, DW_AT_TI_symbol_name("setDutyFxn") + .dwattr $C$DW$461, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$461, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$461, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$461, DW_AT_decl_line(0x171) + .dwattr $C$DW$461, DW_AT_decl_column(0x22) + + .dwattr $C$DW$T$280, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$280, DW_AT_decl_line(0x15d) + .dwattr $C$DW$T$280, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$280 + +$C$DW$T$255 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$255, DW_AT_name("PWM_FxnTable") + .dwattr $C$DW$T$255, DW_AT_type(*$C$DW$T$280) + .dwattr $C$DW$T$255, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$255, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$255, DW_AT_decl_line(0x172) + .dwattr $C$DW$T$255, DW_AT_decl_column(0x03) + +$C$DW$T$256 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$256, DW_AT_type(*$C$DW$T$255) + +$C$DW$T$257 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$257, DW_AT_type(*$C$DW$T$256) + .dwattr $C$DW$T$257, DW_AT_address_class(0x20) + + +$C$DW$T$285 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$285, DW_AT_name("PWM_Params") + .dwattr $C$DW$T$285, DW_AT_byte_size(0x0c) +$C$DW$462 .dwtag DW_TAG_member + .dwattr $C$DW$462, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$462, DW_AT_name("period") + .dwattr $C$DW$462, DW_AT_TI_symbol_name("period") + .dwattr $C$DW$462, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$462, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$462, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$462, DW_AT_decl_line(0x123) + .dwattr $C$DW$462, DW_AT_decl_column(0x12) + +$C$DW$463 .dwtag DW_TAG_member + .dwattr $C$DW$463, DW_AT_type(*$C$DW$T$282) + .dwattr $C$DW$463, DW_AT_name("dutyMode") + .dwattr $C$DW$463, DW_AT_TI_symbol_name("dutyMode") + .dwattr $C$DW$463, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$463, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$463, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$463, DW_AT_decl_line(0x124) + .dwattr $C$DW$463, DW_AT_decl_column(0x12) + +$C$DW$464 .dwtag DW_TAG_member + .dwattr $C$DW$464, DW_AT_type(*$C$DW$T$284) + .dwattr $C$DW$464, DW_AT_name("polarity") + .dwattr $C$DW$464, DW_AT_TI_symbol_name("polarity") + .dwattr $C$DW$464, DW_AT_data_member_location[DW_OP_plus_uconst 0x5] + .dwattr $C$DW$464, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$464, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$464, DW_AT_decl_line(0x125) + .dwattr $C$DW$464, DW_AT_decl_column(0x12) + +$C$DW$465 .dwtag DW_TAG_member + .dwattr $C$DW$465, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$465, DW_AT_name("custom") + .dwattr $C$DW$465, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$465, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$465, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$465, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$465, DW_AT_decl_line(0x126) + .dwattr $C$DW$465, DW_AT_decl_column(0x12) + + .dwattr $C$DW$T$285, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$285, DW_AT_decl_line(0x122) + .dwattr $C$DW$T$285, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$285 + +$C$DW$T$272 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$272, DW_AT_name("PWM_Params") + .dwattr $C$DW$T$272, DW_AT_type(*$C$DW$T$285) + .dwattr $C$DW$T$272, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$272, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$272, DW_AT_decl_line(0x128) + .dwattr $C$DW$T$272, DW_AT_decl_column(0x03) + +$C$DW$T$273 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$273, DW_AT_type(*$C$DW$T$272) + .dwattr $C$DW$T$273, DW_AT_address_class(0x20) + + +$C$DW$T$283 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$283, DW_AT_name("PWM_Polarity") + .dwattr $C$DW$T$283, DW_AT_byte_size(0x01) +$C$DW$466 .dwtag DW_TAG_enumerator + .dwattr $C$DW$466, DW_AT_name("PWM_POL_ACTIVE_HIGH") + .dwattr $C$DW$466, DW_AT_const_value(0x00) + .dwattr $C$DW$466, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$466, DW_AT_decl_line(0x116) + .dwattr $C$DW$466, DW_AT_decl_column(0x05) + +$C$DW$467 .dwtag DW_TAG_enumerator + .dwattr $C$DW$467, DW_AT_name("PWM_POL_ACTIVE_LOW") + .dwattr $C$DW$467, DW_AT_const_value(0x01) + .dwattr $C$DW$467, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$467, DW_AT_decl_line(0x117) + .dwattr $C$DW$467, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$283, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$283, DW_AT_decl_line(0x115) + .dwattr $C$DW$T$283, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$283 + +$C$DW$T$284 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$284, DW_AT_name("PWM_Polarity") + .dwattr $C$DW$T$284, DW_AT_type(*$C$DW$T$283) + .dwattr $C$DW$T$284, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$284, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$284, DW_AT_decl_line(0x118) + .dwattr $C$DW$T$284, DW_AT_decl_column(0x03) + + +$C$DW$T$287 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$287, DW_AT_name("RingBuf_Object") + .dwattr $C$DW$T$287, DW_AT_byte_size(0x18) +$C$DW$468 .dwtag DW_TAG_member + .dwattr $C$DW$468, DW_AT_type(*$C$DW$T$286) + .dwattr $C$DW$468, DW_AT_name("buffer") + .dwattr $C$DW$468, DW_AT_TI_symbol_name("buffer") + .dwattr $C$DW$468, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$468, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$468, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$468, DW_AT_decl_line(0x2d) + .dwattr $C$DW$468, DW_AT_decl_column(0x19) + +$C$DW$469 .dwtag DW_TAG_member + .dwattr $C$DW$469, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$469, DW_AT_name("length") + .dwattr $C$DW$469, DW_AT_TI_symbol_name("length") + .dwattr $C$DW$469, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$469, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$469, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$469, DW_AT_decl_line(0x2e) + .dwattr $C$DW$469, DW_AT_decl_column(0x19) + +$C$DW$470 .dwtag DW_TAG_member + .dwattr $C$DW$470, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$470, DW_AT_name("count") + .dwattr $C$DW$470, DW_AT_TI_symbol_name("count") + .dwattr $C$DW$470, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$470, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$470, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$470, DW_AT_decl_line(0x2f) + .dwattr $C$DW$470, DW_AT_decl_column(0x19) + +$C$DW$471 .dwtag DW_TAG_member + .dwattr $C$DW$471, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$471, DW_AT_name("head") + .dwattr $C$DW$471, DW_AT_TI_symbol_name("head") + .dwattr $C$DW$471, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$471, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$471, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$471, DW_AT_decl_line(0x30) + .dwattr $C$DW$471, DW_AT_decl_column(0x19) + +$C$DW$472 .dwtag DW_TAG_member + .dwattr $C$DW$472, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$472, DW_AT_name("tail") + .dwattr $C$DW$472, DW_AT_TI_symbol_name("tail") + .dwattr $C$DW$472, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$472, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$472, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$472, DW_AT_decl_line(0x31) + .dwattr $C$DW$472, DW_AT_decl_column(0x19) + +$C$DW$473 .dwtag DW_TAG_member + .dwattr $C$DW$473, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$473, DW_AT_name("maxCount") + .dwattr $C$DW$473, DW_AT_TI_symbol_name("maxCount") + .dwattr $C$DW$473, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$473, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$473, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$473, DW_AT_decl_line(0x32) + .dwattr $C$DW$473, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$287, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$T$287, DW_AT_decl_line(0x2c) + .dwattr $C$DW$T$287, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$287 + +$C$DW$T$376 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$376, DW_AT_name("RingBuf_Object") + .dwattr $C$DW$T$376, DW_AT_type(*$C$DW$T$287) + .dwattr $C$DW$T$376, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$376, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$T$376, DW_AT_decl_line(0x33) + .dwattr $C$DW$T$376, DW_AT_decl_column(0x03) + +$C$DW$T$1021 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1021, DW_AT_type(*$C$DW$T$287) + .dwattr $C$DW$T$1021, DW_AT_address_class(0x20) + +$C$DW$T$1022 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1022, DW_AT_name("RingBuf_Handle") + .dwattr $C$DW$T$1022, DW_AT_type(*$C$DW$T$1021) + .dwattr $C$DW$T$1022, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1022, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h") + .dwattr $C$DW$T$1022, DW_AT_decl_line(0x33) + .dwattr $C$DW$T$1022, DW_AT_decl_column(0x14) + + +$C$DW$T$290 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$290, DW_AT_name("SDSPITiva_CardType") + .dwattr $C$DW$T$290, DW_AT_byte_size(0x01) +$C$DW$474 .dwtag DW_TAG_enumerator + .dwattr $C$DW$474, DW_AT_name("SDSPITiva_NOCARD") + .dwattr $C$DW$474, DW_AT_const_value(0x00) + .dwattr $C$DW$474, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$474, DW_AT_decl_line(0x6d) + .dwattr $C$DW$474, DW_AT_decl_column(0x05) + +$C$DW$475 .dwtag DW_TAG_enumerator + .dwattr $C$DW$475, DW_AT_name("SDSPITiva_MMC") + .dwattr $C$DW$475, DW_AT_const_value(0x01) + .dwattr $C$DW$475, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$475, DW_AT_decl_line(0x6e) + .dwattr $C$DW$475, DW_AT_decl_column(0x05) + +$C$DW$476 .dwtag DW_TAG_enumerator + .dwattr $C$DW$476, DW_AT_name("SDSPITiva_SDSC") + .dwattr $C$DW$476, DW_AT_const_value(0x02) + .dwattr $C$DW$476, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$476, DW_AT_decl_line(0x6f) + .dwattr $C$DW$476, DW_AT_decl_column(0x05) + +$C$DW$477 .dwtag DW_TAG_enumerator + .dwattr $C$DW$477, DW_AT_name("SDSPITiva_SDHC") + .dwattr $C$DW$477, DW_AT_const_value(0x03) + .dwattr $C$DW$477, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$477, DW_AT_decl_line(0x70) + .dwattr $C$DW$477, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$290, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$290, DW_AT_decl_line(0x6c) + .dwattr $C$DW$T$290, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$290 + +$C$DW$T$291 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$291, DW_AT_name("SDSPITiva_CardType") + .dwattr $C$DW$T$291, DW_AT_type(*$C$DW$T$290) + .dwattr $C$DW$T$291, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$291, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$291, DW_AT_decl_line(0x71) + .dwattr $C$DW$T$291, DW_AT_decl_column(0x03) + + +$C$DW$T$289 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$289, DW_AT_name("SDSPITiva_HWAttrs") + .dwattr $C$DW$T$289, DW_AT_byte_size(0x24) +$C$DW$478 .dwtag DW_TAG_member + .dwattr $C$DW$478, DW_AT_type(*$C$DW$T$288) + .dwattr $C$DW$478, DW_AT_name("baseAddr") + .dwattr $C$DW$478, DW_AT_TI_symbol_name("baseAddr") + .dwattr $C$DW$478, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$478, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$478, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$478, DW_AT_decl_line(0xa2) + .dwattr $C$DW$478, DW_AT_decl_column(0x17) + +$C$DW$479 .dwtag DW_TAG_member + .dwattr $C$DW$479, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$479, DW_AT_name("portSCK") + .dwattr $C$DW$479, DW_AT_TI_symbol_name("portSCK") + .dwattr $C$DW$479, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$479, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$479, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$479, DW_AT_decl_line(0xa5) + .dwattr $C$DW$479, DW_AT_decl_column(0x0e) + +$C$DW$480 .dwtag DW_TAG_member + .dwattr $C$DW$480, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$480, DW_AT_name("pinSCK") + .dwattr $C$DW$480, DW_AT_TI_symbol_name("pinSCK") + .dwattr $C$DW$480, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$480, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$480, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$480, DW_AT_decl_line(0xa7) + .dwattr $C$DW$480, DW_AT_decl_column(0x0e) + +$C$DW$481 .dwtag DW_TAG_member + .dwattr $C$DW$481, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$481, DW_AT_name("portMISO") + .dwattr $C$DW$481, DW_AT_TI_symbol_name("portMISO") + .dwattr $C$DW$481, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$481, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$481, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$481, DW_AT_decl_line(0xaa) + .dwattr $C$DW$481, DW_AT_decl_column(0x0e) + +$C$DW$482 .dwtag DW_TAG_member + .dwattr $C$DW$482, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$482, DW_AT_name("pinMISO") + .dwattr $C$DW$482, DW_AT_TI_symbol_name("pinMISO") + .dwattr $C$DW$482, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$482, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$482, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$482, DW_AT_decl_line(0xac) + .dwattr $C$DW$482, DW_AT_decl_column(0x0e) + +$C$DW$483 .dwtag DW_TAG_member + .dwattr $C$DW$483, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$483, DW_AT_name("portMOSI") + .dwattr $C$DW$483, DW_AT_TI_symbol_name("portMOSI") + .dwattr $C$DW$483, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$483, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$483, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$483, DW_AT_decl_line(0xaf) + .dwattr $C$DW$483, DW_AT_decl_column(0x0e) + +$C$DW$484 .dwtag DW_TAG_member + .dwattr $C$DW$484, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$484, DW_AT_name("pinMOSI") + .dwattr $C$DW$484, DW_AT_TI_symbol_name("pinMOSI") + .dwattr $C$DW$484, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$484, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$484, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$484, DW_AT_decl_line(0xb1) + .dwattr $C$DW$484, DW_AT_decl_column(0x0e) + +$C$DW$485 .dwtag DW_TAG_member + .dwattr $C$DW$485, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$485, DW_AT_name("portCS") + .dwattr $C$DW$485, DW_AT_TI_symbol_name("portCS") + .dwattr $C$DW$485, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$485, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$485, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$485, DW_AT_decl_line(0xb4) + .dwattr $C$DW$485, DW_AT_decl_column(0x0e) + +$C$DW$486 .dwtag DW_TAG_member + .dwattr $C$DW$486, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$486, DW_AT_name("pinCS") + .dwattr $C$DW$486, DW_AT_TI_symbol_name("pinCS") + .dwattr $C$DW$486, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$486, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$486, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$486, DW_AT_decl_line(0xb6) + .dwattr $C$DW$486, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$289, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$289, DW_AT_decl_line(0xa0) + .dwattr $C$DW$T$289, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$289 + +$C$DW$T$1023 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1023, DW_AT_name("SDSPITiva_HWAttrs") + .dwattr $C$DW$T$1023, DW_AT_type(*$C$DW$T$289) + .dwattr $C$DW$T$1023, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1023, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$1023, DW_AT_decl_line(0xb7) + .dwattr $C$DW$T$1023, DW_AT_decl_column(0x03) + +$C$DW$T$1024 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1024, DW_AT_type(*$C$DW$T$1023) + + +$C$DW$T$1025 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1025, DW_AT_type(*$C$DW$T$1024) + .dwattr $C$DW$T$1025, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1025, DW_AT_byte_size(0x24) +$C$DW$487 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$487, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1025 + + +$C$DW$T$292 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$292, DW_AT_name("SDSPITiva_Object") + .dwattr $C$DW$T$292, DW_AT_byte_size(0x240) +$C$DW$488 .dwtag DW_TAG_member + .dwattr $C$DW$488, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$488, DW_AT_name("driveNumber") + .dwattr $C$DW$488, DW_AT_TI_symbol_name("driveNumber") + .dwattr $C$DW$488, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$488, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$488, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$488, DW_AT_decl_line(0xbf) + .dwattr $C$DW$488, DW_AT_decl_column(0x19) + +$C$DW$489 .dwtag DW_TAG_member + .dwattr $C$DW$489, DW_AT_type(*$C$DW$T$171) + .dwattr $C$DW$489, DW_AT_name("diskState") + .dwattr $C$DW$489, DW_AT_TI_symbol_name("diskState") + .dwattr $C$DW$489, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$489, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$489, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$489, DW_AT_decl_line(0xc0) + .dwattr $C$DW$489, DW_AT_decl_column(0x19) + +$C$DW$490 .dwtag DW_TAG_member + .dwattr $C$DW$490, DW_AT_type(*$C$DW$T$291) + .dwattr $C$DW$490, DW_AT_name("cardType") + .dwattr $C$DW$490, DW_AT_TI_symbol_name("cardType") + .dwattr $C$DW$490, DW_AT_data_member_location[DW_OP_plus_uconst 0x5] + .dwattr $C$DW$490, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$490, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$490, DW_AT_decl_line(0xc1) + .dwattr $C$DW$490, DW_AT_decl_column(0x19) + +$C$DW$491 .dwtag DW_TAG_member + .dwattr $C$DW$491, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$491, DW_AT_name("bitRate") + .dwattr $C$DW$491, DW_AT_TI_symbol_name("bitRate") + .dwattr $C$DW$491, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$491, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$491, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$491, DW_AT_decl_line(0xc2) + .dwattr $C$DW$491, DW_AT_decl_column(0x19) + +$C$DW$492 .dwtag DW_TAG_member + .dwattr $C$DW$492, DW_AT_type(*$C$DW$T$162) + .dwattr $C$DW$492, DW_AT_name("filesystem") + .dwattr $C$DW$492, DW_AT_TI_symbol_name("filesystem") + .dwattr $C$DW$492, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$492, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$492, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$492, DW_AT_decl_line(0xc3) + .dwattr $C$DW$492, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$292, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$292, DW_AT_decl_line(0xbe) + .dwattr $C$DW$T$292, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$292 + +$C$DW$T$1027 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1027, DW_AT_name("SDSPITiva_Object") + .dwattr $C$DW$T$1027, DW_AT_type(*$C$DW$T$292) + .dwattr $C$DW$T$1027, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1027, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$1027, DW_AT_decl_line(0xc4) + .dwattr $C$DW$T$1027, DW_AT_decl_column(0x03) + + +$C$DW$T$1028 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1028, DW_AT_type(*$C$DW$T$1027) + .dwattr $C$DW$T$1028, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1028, DW_AT_byte_size(0x240) +$C$DW$493 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$493, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1028 + +$C$DW$T$1030 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1030, DW_AT_type(*$C$DW$T$292) + .dwattr $C$DW$T$1030, DW_AT_address_class(0x20) + +$C$DW$T$1031 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1031, DW_AT_name("SDSPITiva_Handle") + .dwattr $C$DW$T$1031, DW_AT_type(*$C$DW$T$1030) + .dwattr $C$DW$T$1031, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1031, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h") + .dwattr $C$DW$T$1031, DW_AT_decl_line(0xc4) + .dwattr $C$DW$T$1031, DW_AT_decl_column(0x16) + + +$C$DW$T$296 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$296, DW_AT_name("SDSPI_Config") + .dwattr $C$DW$T$296, DW_AT_byte_size(0x0c) +$C$DW$494 .dwtag DW_TAG_member + .dwattr $C$DW$494, DW_AT_type(*$C$DW$T$295) + .dwattr $C$DW$494, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$494, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$494, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$494, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$494, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$494, DW_AT_decl_line(0x10c) + .dwattr $C$DW$494, DW_AT_decl_column(0x1b) + +$C$DW$495 .dwtag DW_TAG_member + .dwattr $C$DW$495, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$495, DW_AT_name("object") + .dwattr $C$DW$495, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$495, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$495, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$495, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$495, DW_AT_decl_line(0x10f) + .dwattr $C$DW$495, DW_AT_decl_column(0x1b) + +$C$DW$496 .dwtag DW_TAG_member + .dwattr $C$DW$496, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$496, DW_AT_name("hwAttrs") + .dwattr $C$DW$496, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$496, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$496, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$496, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$496, DW_AT_decl_line(0x112) + .dwattr $C$DW$496, DW_AT_decl_column(0x1b) + + .dwattr $C$DW$T$296, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$296, DW_AT_decl_line(0x10a) + .dwattr $C$DW$T$296, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$296 + +$C$DW$T$1032 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1032, DW_AT_name("SDSPI_Config") + .dwattr $C$DW$T$1032, DW_AT_type(*$C$DW$T$296) + .dwattr $C$DW$T$1032, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1032, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$1032, DW_AT_decl_line(0x113) + .dwattr $C$DW$T$1032, DW_AT_decl_column(0x03) + +$C$DW$T$1033 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1033, DW_AT_type(*$C$DW$T$1032) + + +$C$DW$T$1034 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1034, DW_AT_type(*$C$DW$T$1033) + .dwattr $C$DW$T$1034, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1034, DW_AT_byte_size(0x18) +$C$DW$497 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$497, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1034 + +$C$DW$T$297 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$297, DW_AT_type(*$C$DW$T$296) + .dwattr $C$DW$T$297, DW_AT_address_class(0x20) + +$C$DW$T$298 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$298, DW_AT_name("SDSPI_Handle") + .dwattr $C$DW$T$298, DW_AT_type(*$C$DW$T$297) + .dwattr $C$DW$T$298, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$298, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$298, DW_AT_decl_line(0xc0) + .dwattr $C$DW$T$298, DW_AT_decl_column(0x23) + + +$C$DW$T$304 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$304, DW_AT_type(*$C$DW$T$298) + .dwattr $C$DW$T$304, DW_AT_language(DW_LANG_C) +$C$DW$498 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$498, DW_AT_type(*$C$DW$T$298) + +$C$DW$499 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$499, DW_AT_type(*$C$DW$T$6) + +$C$DW$500 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$500, DW_AT_type(*$C$DW$T$303) + + .dwendtag $C$DW$T$304 + +$C$DW$T$305 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$305, DW_AT_type(*$C$DW$T$304) + .dwattr $C$DW$T$305, DW_AT_address_class(0x20) + +$C$DW$T$306 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$306, DW_AT_name("SDSPI_OpenFxn") + .dwattr $C$DW$T$306, DW_AT_type(*$C$DW$T$305) + .dwattr $C$DW$T$306, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$306, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$306, DW_AT_decl_line(0xda) + .dwattr $C$DW$T$306, DW_AT_decl_column(0x18) + + +$C$DW$T$311 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$311, DW_AT_name("SDSPI_FxnTable") + .dwattr $C$DW$T$311, DW_AT_byte_size(0x10) +$C$DW$501 .dwtag DW_TAG_member + .dwattr $C$DW$501, DW_AT_type(*$C$DW$T$301) + .dwattr $C$DW$501, DW_AT_name("initFxn") + .dwattr $C$DW$501, DW_AT_TI_symbol_name("initFxn") + .dwattr $C$DW$501, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$501, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$501, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$501, DW_AT_decl_line(0xf3) + .dwattr $C$DW$501, DW_AT_decl_column(0x1b) + +$C$DW$502 .dwtag DW_TAG_member + .dwattr $C$DW$502, DW_AT_type(*$C$DW$T$306) + .dwattr $C$DW$502, DW_AT_name("openFxn") + .dwattr $C$DW$502, DW_AT_TI_symbol_name("openFxn") + .dwattr $C$DW$502, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$502, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$502, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$502, DW_AT_decl_line(0xf6) + .dwattr $C$DW$502, DW_AT_decl_column(0x1b) + +$C$DW$503 .dwtag DW_TAG_member + .dwattr $C$DW$503, DW_AT_type(*$C$DW$T$307) + .dwattr $C$DW$503, DW_AT_name("closeFxn") + .dwattr $C$DW$503, DW_AT_TI_symbol_name("closeFxn") + .dwattr $C$DW$503, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$503, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$503, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$503, DW_AT_decl_line(0xf9) + .dwattr $C$DW$503, DW_AT_decl_column(0x1b) + +$C$DW$504 .dwtag DW_TAG_member + .dwattr $C$DW$504, DW_AT_type(*$C$DW$T$310) + .dwattr $C$DW$504, DW_AT_name("controlFxn") + .dwattr $C$DW$504, DW_AT_TI_symbol_name("controlFxn") + .dwattr $C$DW$504, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$504, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$504, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$504, DW_AT_decl_line(0xfc) + .dwattr $C$DW$504, DW_AT_decl_column(0x1b) + + .dwattr $C$DW$T$311, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$311, DW_AT_decl_line(0xf1) + .dwattr $C$DW$T$311, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$311 + +$C$DW$T$293 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$293, DW_AT_name("SDSPI_FxnTable") + .dwattr $C$DW$T$293, DW_AT_type(*$C$DW$T$311) + .dwattr $C$DW$T$293, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$293, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$293, DW_AT_decl_line(0xfd) + .dwattr $C$DW$T$293, DW_AT_decl_column(0x03) + +$C$DW$T$294 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$294, DW_AT_type(*$C$DW$T$293) + +$C$DW$T$295 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$295, DW_AT_type(*$C$DW$T$294) + .dwattr $C$DW$T$295, DW_AT_address_class(0x20) + + +$C$DW$T$312 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$312, DW_AT_name("SDSPI_Params") + .dwattr $C$DW$T$312, DW_AT_byte_size(0x08) +$C$DW$505 .dwtag DW_TAG_member + .dwattr $C$DW$505, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$505, DW_AT_name("bitRate") + .dwattr $C$DW$505, DW_AT_TI_symbol_name("bitRate") + .dwattr $C$DW$505, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$505, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$505, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$505, DW_AT_decl_line(0xcc) + .dwattr $C$DW$505, DW_AT_decl_column(0x0f) + +$C$DW$506 .dwtag DW_TAG_member + .dwattr $C$DW$506, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$506, DW_AT_name("custom") + .dwattr $C$DW$506, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$506, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$506, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$506, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$506, DW_AT_decl_line(0xcd) + .dwattr $C$DW$506, DW_AT_decl_column(0x0f) + + .dwattr $C$DW$T$312, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$312, DW_AT_decl_line(0xcb) + .dwattr $C$DW$T$312, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$312 + +$C$DW$T$302 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$302, DW_AT_name("SDSPI_Params") + .dwattr $C$DW$T$302, DW_AT_type(*$C$DW$T$312) + .dwattr $C$DW$T$302, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$302, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$302, DW_AT_decl_line(0xce) + .dwattr $C$DW$T$302, DW_AT_decl_column(0x03) + +$C$DW$T$303 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$303, DW_AT_type(*$C$DW$T$302) + .dwattr $C$DW$T$303, DW_AT_address_class(0x20) + + +$C$DW$T$328 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$328, DW_AT_name("SPITivaDMA_FrameSize") + .dwattr $C$DW$T$328, DW_AT_byte_size(0x01) +$C$DW$507 .dwtag DW_TAG_enumerator + .dwattr $C$DW$507, DW_AT_name("SPITivaDMA_8bit") + .dwattr $C$DW$507, DW_AT_const_value(0x00) + .dwattr $C$DW$507, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$507, DW_AT_decl_line(0xb6) + .dwattr $C$DW$507, DW_AT_decl_column(0x05) + +$C$DW$508 .dwtag DW_TAG_enumerator + .dwattr $C$DW$508, DW_AT_name("SPITivaDMA_16bit") + .dwattr $C$DW$508, DW_AT_const_value(0x01) + .dwattr $C$DW$508, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$508, DW_AT_decl_line(0xb7) + .dwattr $C$DW$508, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$328, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$328, DW_AT_decl_line(0xb5) + .dwattr $C$DW$T$328, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$328 + +$C$DW$T$329 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$329, DW_AT_name("SPITivaDMA_FrameSize") + .dwattr $C$DW$T$329, DW_AT_type(*$C$DW$T$328) + .dwattr $C$DW$T$329, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$329, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$329, DW_AT_decl_line(0xb8) + .dwattr $C$DW$T$329, DW_AT_decl_column(0x03) + + +$C$DW$T$318 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$318, DW_AT_name("SPITivaDMA_HWAttrs") + .dwattr $C$DW$T$318, DW_AT_byte_size(0x28) +$C$DW$509 .dwtag DW_TAG_member + .dwattr $C$DW$509, DW_AT_type(*$C$DW$T$313) + .dwattr $C$DW$509, DW_AT_name("baseAddr") + .dwattr $C$DW$509, DW_AT_TI_symbol_name("baseAddr") + .dwattr $C$DW$509, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$509, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$509, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$509, DW_AT_decl_line(0xe3) + .dwattr $C$DW$509, DW_AT_decl_column(0x17) + +$C$DW$510 .dwtag DW_TAG_member + .dwattr $C$DW$510, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$510, DW_AT_name("intNum") + .dwattr $C$DW$510, DW_AT_TI_symbol_name("intNum") + .dwattr $C$DW$510, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$510, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$510, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$510, DW_AT_decl_line(0xe5) + .dwattr $C$DW$510, DW_AT_decl_column(0x17) + +$C$DW$511 .dwtag DW_TAG_member + .dwattr $C$DW$511, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$511, DW_AT_name("intPriority") + .dwattr $C$DW$511, DW_AT_TI_symbol_name("intPriority") + .dwattr $C$DW$511, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$511, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$511, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$511, DW_AT_decl_line(0xe8) + .dwattr $C$DW$511, DW_AT_decl_column(0x17) + +$C$DW$512 .dwtag DW_TAG_member + .dwattr $C$DW$512, DW_AT_type(*$C$DW$T$314) + .dwattr $C$DW$512, DW_AT_name("scratchBufPtr") + .dwattr $C$DW$512, DW_AT_TI_symbol_name("scratchBufPtr") + .dwattr $C$DW$512, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$512, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$512, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$512, DW_AT_decl_line(0xeb) + .dwattr $C$DW$512, DW_AT_decl_column(0x17) + +$C$DW$513 .dwtag DW_TAG_member + .dwattr $C$DW$513, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$513, DW_AT_name("defaultTxBufValue") + .dwattr $C$DW$513, DW_AT_TI_symbol_name("defaultTxBufValue") + .dwattr $C$DW$513, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$513, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$513, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$513, DW_AT_decl_line(0xed) + .dwattr $C$DW$513, DW_AT_decl_column(0x17) + +$C$DW$514 .dwtag DW_TAG_member + .dwattr $C$DW$514, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$514, DW_AT_name("rxChannelIndex") + .dwattr $C$DW$514, DW_AT_TI_symbol_name("rxChannelIndex") + .dwattr $C$DW$514, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$514, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$514, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$514, DW_AT_decl_line(0xef) + .dwattr $C$DW$514, DW_AT_decl_column(0x17) + +$C$DW$515 .dwtag DW_TAG_member + .dwattr $C$DW$515, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$515, DW_AT_name("txChannelIndex") + .dwattr $C$DW$515, DW_AT_TI_symbol_name("txChannelIndex") + .dwattr $C$DW$515, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$515, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$515, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$515, DW_AT_decl_line(0xf1) + .dwattr $C$DW$515, DW_AT_decl_column(0x17) + +$C$DW$516 .dwtag DW_TAG_member + .dwattr $C$DW$516, DW_AT_type(*$C$DW$T$317) + .dwattr $C$DW$516, DW_AT_name("channelMappingFxn") + .dwattr $C$DW$516, DW_AT_TI_symbol_name("channelMappingFxn") + .dwattr $C$DW$516, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$516, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$516, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$516, DW_AT_decl_line(0xf4) + .dwattr $C$DW$516, DW_AT_decl_column(0x0d) + +$C$DW$517 .dwtag DW_TAG_member + .dwattr $C$DW$517, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$517, DW_AT_name("rxChannelMappingFxnArg") + .dwattr $C$DW$517, DW_AT_TI_symbol_name("rxChannelMappingFxnArg") + .dwattr $C$DW$517, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$517, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$517, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$517, DW_AT_decl_line(0xf6) + .dwattr $C$DW$517, DW_AT_decl_column(0x17) + +$C$DW$518 .dwtag DW_TAG_member + .dwattr $C$DW$518, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$518, DW_AT_name("txChannelMappingFxnArg") + .dwattr $C$DW$518, DW_AT_TI_symbol_name("txChannelMappingFxnArg") + .dwattr $C$DW$518, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$518, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$518, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$518, DW_AT_decl_line(0xf8) + .dwattr $C$DW$518, DW_AT_decl_column(0x17) + + .dwattr $C$DW$T$318, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$318, DW_AT_decl_line(0xe1) + .dwattr $C$DW$T$318, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$318 + +$C$DW$T$1035 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1035, DW_AT_name("SPITivaDMA_HWAttrs") + .dwattr $C$DW$T$1035, DW_AT_type(*$C$DW$T$318) + .dwattr $C$DW$T$1035, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1035, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$1035, DW_AT_decl_line(0xf9) + .dwattr $C$DW$T$1035, DW_AT_decl_column(0x03) + +$C$DW$T$1036 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1036, DW_AT_type(*$C$DW$T$1035) + + +$C$DW$T$1037 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1037, DW_AT_type(*$C$DW$T$1036) + .dwattr $C$DW$T$1037, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1037, DW_AT_byte_size(0x78) +$C$DW$519 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$519, DW_AT_upper_bound(0x02) + + .dwendtag $C$DW$T$1037 + + +$C$DW$T$330 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$330, DW_AT_name("SPITivaDMA_Object") + .dwattr $C$DW$T$330, DW_AT_byte_size(0x4c) +$C$DW$520 .dwtag DW_TAG_member + .dwattr $C$DW$520, DW_AT_type(*$C$DW$T$200) + .dwattr $C$DW$520, DW_AT_name("transferComplete") + .dwattr $C$DW$520, DW_AT_TI_symbol_name("transferComplete") + .dwattr $C$DW$520, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$520, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$520, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$520, DW_AT_decl_line(0x101) + .dwattr $C$DW$520, DW_AT_decl_column(0x1b) + +$C$DW$521 .dwtag DW_TAG_member + .dwattr $C$DW$521, DW_AT_type(*$C$DW$T$210) + .dwattr $C$DW$521, DW_AT_name("hwi") + .dwattr $C$DW$521, DW_AT_TI_symbol_name("hwi") + .dwattr $C$DW$521, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$521, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$521, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$521, DW_AT_decl_line(0x102) + .dwattr $C$DW$521, DW_AT_decl_column(0x29) + +$C$DW$522 .dwtag DW_TAG_member + .dwattr $C$DW$522, DW_AT_type(*$C$DW$T$320) + .dwattr $C$DW$522, DW_AT_name("transferMode") + .dwattr $C$DW$522, DW_AT_TI_symbol_name("transferMode") + .dwattr $C$DW$522, DW_AT_data_member_location[DW_OP_plus_uconst 0x38] + .dwattr $C$DW$522, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$522, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$522, DW_AT_decl_line(0x104) + .dwattr $C$DW$522, DW_AT_decl_column(0x1b) + +$C$DW$523 .dwtag DW_TAG_member + .dwattr $C$DW$523, DW_AT_type(*$C$DW$T$327) + .dwattr $C$DW$523, DW_AT_name("transferCallbackFxn") + .dwattr $C$DW$523, DW_AT_TI_symbol_name("transferCallbackFxn") + .dwattr $C$DW$523, DW_AT_data_member_location[DW_OP_plus_uconst 0x3c] + .dwattr $C$DW$523, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$523, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$523, DW_AT_decl_line(0x105) + .dwattr $C$DW$523, DW_AT_decl_column(0x1b) + +$C$DW$524 .dwtag DW_TAG_member + .dwattr $C$DW$524, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$524, DW_AT_name("transferTimeout") + .dwattr $C$DW$524, DW_AT_TI_symbol_name("transferTimeout") + .dwattr $C$DW$524, DW_AT_data_member_location[DW_OP_plus_uconst 0x40] + .dwattr $C$DW$524, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$524, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$524, DW_AT_decl_line(0x106) + .dwattr $C$DW$524, DW_AT_decl_column(0x1b) + +$C$DW$525 .dwtag DW_TAG_member + .dwattr $C$DW$525, DW_AT_type(*$C$DW$T$324) + .dwattr $C$DW$525, DW_AT_name("transaction") + .dwattr $C$DW$525, DW_AT_TI_symbol_name("transaction") + .dwattr $C$DW$525, DW_AT_data_member_location[DW_OP_plus_uconst 0x44] + .dwattr $C$DW$525, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$525, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$525, DW_AT_decl_line(0x108) + .dwattr $C$DW$525, DW_AT_decl_column(0x1b) + +$C$DW$526 .dwtag DW_TAG_member + .dwattr $C$DW$526, DW_AT_type(*$C$DW$T$329) + .dwattr $C$DW$526, DW_AT_name("frameSize") + .dwattr $C$DW$526, DW_AT_TI_symbol_name("frameSize") + .dwattr $C$DW$526, DW_AT_data_member_location[DW_OP_plus_uconst 0x48] + .dwattr $C$DW$526, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$526, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$526, DW_AT_decl_line(0x10a) + .dwattr $C$DW$526, DW_AT_decl_column(0x1b) + +$C$DW$527 .dwtag DW_TAG_member + .dwattr $C$DW$527, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$527, DW_AT_name("isOpen") + .dwattr $C$DW$527, DW_AT_TI_symbol_name("isOpen") + .dwattr $C$DW$527, DW_AT_data_member_location[DW_OP_plus_uconst 0x49] + .dwattr $C$DW$527, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$527, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$527, DW_AT_decl_line(0x10c) + .dwattr $C$DW$527, DW_AT_decl_column(0x1b) + + .dwattr $C$DW$T$330, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$330, DW_AT_decl_line(0x100) + .dwattr $C$DW$T$330, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$330 + +$C$DW$T$1039 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1039, DW_AT_name("SPITivaDMA_Object") + .dwattr $C$DW$T$1039, DW_AT_type(*$C$DW$T$330) + .dwattr $C$DW$T$1039, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1039, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$1039, DW_AT_decl_line(0x10d) + .dwattr $C$DW$T$1039, DW_AT_decl_column(0x03) + + +$C$DW$T$1040 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1040, DW_AT_type(*$C$DW$T$1039) + .dwattr $C$DW$T$1040, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1040, DW_AT_byte_size(0xe4) +$C$DW$528 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$528, DW_AT_upper_bound(0x02) + + .dwendtag $C$DW$T$1040 + +$C$DW$T$1042 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1042, DW_AT_type(*$C$DW$T$330) + .dwattr $C$DW$T$1042, DW_AT_address_class(0x20) + +$C$DW$T$1043 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1043, DW_AT_name("SPITivaDMA_Handle") + .dwattr $C$DW$T$1043, DW_AT_type(*$C$DW$T$1042) + .dwattr $C$DW$T$1043, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1043, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h") + .dwattr $C$DW$T$1043, DW_AT_decl_line(0x10d) + .dwattr $C$DW$T$1043, DW_AT_decl_column(0x17) + + +$C$DW$T$334 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$334, DW_AT_name("SPI_Config") + .dwattr $C$DW$T$334, DW_AT_byte_size(0x0c) +$C$DW$529 .dwtag DW_TAG_member + .dwattr $C$DW$529, DW_AT_type(*$C$DW$T$333) + .dwattr $C$DW$529, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$529, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$529, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$529, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$529, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$529, DW_AT_decl_line(0x1b6) + .dwattr $C$DW$529, DW_AT_decl_column(0x19) + +$C$DW$530 .dwtag DW_TAG_member + .dwattr $C$DW$530, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$530, DW_AT_name("object") + .dwattr $C$DW$530, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$530, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$530, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$530, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$530, DW_AT_decl_line(0x1b9) + .dwattr $C$DW$530, DW_AT_decl_column(0x19) + +$C$DW$531 .dwtag DW_TAG_member + .dwattr $C$DW$531, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$531, DW_AT_name("hwAttrs") + .dwattr $C$DW$531, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$531, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$531, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$531, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$531, DW_AT_decl_line(0x1bc) + .dwattr $C$DW$531, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$334, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$334, DW_AT_decl_line(0x1b4) + .dwattr $C$DW$T$334, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$334 + +$C$DW$T$1044 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1044, DW_AT_name("SPI_Config") + .dwattr $C$DW$T$1044, DW_AT_type(*$C$DW$T$334) + .dwattr $C$DW$T$1044, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1044, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$1044, DW_AT_decl_line(0x1bd) + .dwattr $C$DW$T$1044, DW_AT_decl_column(0x03) + +$C$DW$T$1045 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1045, DW_AT_type(*$C$DW$T$1044) + + +$C$DW$T$1046 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1046, DW_AT_type(*$C$DW$T$1045) + .dwattr $C$DW$T$1046, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1046, DW_AT_byte_size(0x30) +$C$DW$532 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$532, DW_AT_upper_bound(0x03) + + .dwendtag $C$DW$T$1046 + +$C$DW$T$321 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$321, DW_AT_type(*$C$DW$T$334) + .dwattr $C$DW$T$321, DW_AT_address_class(0x20) + +$C$DW$T$322 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$322, DW_AT_name("SPI_Handle") + .dwattr $C$DW$T$322, DW_AT_type(*$C$DW$T$321) + .dwattr $C$DW$T$322, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$322, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$322, DW_AT_decl_line(0xf1) + .dwattr $C$DW$T$322, DW_AT_decl_column(0x21) + + +$C$DW$T$344 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$344, DW_AT_type(*$C$DW$T$322) + .dwattr $C$DW$T$344, DW_AT_language(DW_LANG_C) +$C$DW$533 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$533, DW_AT_type(*$C$DW$T$322) + +$C$DW$534 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$534, DW_AT_type(*$C$DW$T$343) + + .dwendtag $C$DW$T$344 + +$C$DW$T$345 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$345, DW_AT_type(*$C$DW$T$344) + .dwattr $C$DW$T$345, DW_AT_address_class(0x20) + +$C$DW$T$346 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$346, DW_AT_name("SPI_OpenFxn") + .dwattr $C$DW$T$346, DW_AT_type(*$C$DW$T$345) + .dwattr $C$DW$T$346, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$346, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$346, DW_AT_decl_line(0x177) + .dwattr $C$DW$T$346, DW_AT_decl_column(0x17) + + +$C$DW$T$355 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$355, DW_AT_name("SPI_FrameFormat") + .dwattr $C$DW$T$355, DW_AT_byte_size(0x01) +$C$DW$535 .dwtag DW_TAG_enumerator + .dwattr $C$DW$535, DW_AT_name("SPI_POL0_PHA0") + .dwattr $C$DW$535, DW_AT_const_value(0x00) + .dwattr $C$DW$535, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$535, DW_AT_decl_line(0x12a) + .dwattr $C$DW$535, DW_AT_decl_column(0x05) + +$C$DW$536 .dwtag DW_TAG_enumerator + .dwattr $C$DW$536, DW_AT_name("SPI_POL0_PHA1") + .dwattr $C$DW$536, DW_AT_const_value(0x01) + .dwattr $C$DW$536, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$536, DW_AT_decl_line(0x12b) + .dwattr $C$DW$536, DW_AT_decl_column(0x05) + +$C$DW$537 .dwtag DW_TAG_enumerator + .dwattr $C$DW$537, DW_AT_name("SPI_POL1_PHA0") + .dwattr $C$DW$537, DW_AT_const_value(0x02) + .dwattr $C$DW$537, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$537, DW_AT_decl_line(0x12c) + .dwattr $C$DW$537, DW_AT_decl_column(0x05) + +$C$DW$538 .dwtag DW_TAG_enumerator + .dwattr $C$DW$538, DW_AT_name("SPI_POL1_PHA1") + .dwattr $C$DW$538, DW_AT_const_value(0x03) + .dwattr $C$DW$538, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$538, DW_AT_decl_line(0x12d) + .dwattr $C$DW$538, DW_AT_decl_column(0x05) + +$C$DW$539 .dwtag DW_TAG_enumerator + .dwattr $C$DW$539, DW_AT_name("SPI_TI") + .dwattr $C$DW$539, DW_AT_const_value(0x04) + .dwattr $C$DW$539, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$539, DW_AT_decl_line(0x12e) + .dwattr $C$DW$539, DW_AT_decl_column(0x05) + +$C$DW$540 .dwtag DW_TAG_enumerator + .dwattr $C$DW$540, DW_AT_name("SPI_MW") + .dwattr $C$DW$540, DW_AT_const_value(0x05) + .dwattr $C$DW$540, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$540, DW_AT_decl_line(0x12f) + .dwattr $C$DW$540, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$355, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$355, DW_AT_decl_line(0x129) + .dwattr $C$DW$T$355, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$355 + +$C$DW$T$356 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$356, DW_AT_name("SPI_FrameFormat") + .dwattr $C$DW$T$356, DW_AT_type(*$C$DW$T$355) + .dwattr $C$DW$T$356, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$356, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$356, DW_AT_decl_line(0x130) + .dwattr $C$DW$T$356, DW_AT_decl_column(0x03) + + +$C$DW$T$352 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$352, DW_AT_name("SPI_FxnTable") + .dwattr $C$DW$T$352, DW_AT_byte_size(0x1c) +$C$DW$541 .dwtag DW_TAG_member + .dwattr $C$DW$541, DW_AT_type(*$C$DW$T$337) + .dwattr $C$DW$541, DW_AT_name("closeFxn") + .dwattr $C$DW$541, DW_AT_TI_symbol_name("closeFxn") + .dwattr $C$DW$541, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$541, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$541, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$541, DW_AT_decl_line(0x194) + .dwattr $C$DW$541, DW_AT_decl_column(0x1d) + +$C$DW$542 .dwtag DW_TAG_member + .dwattr $C$DW$542, DW_AT_type(*$C$DW$T$340) + .dwattr $C$DW$542, DW_AT_name("controlFxn") + .dwattr $C$DW$542, DW_AT_TI_symbol_name("controlFxn") + .dwattr $C$DW$542, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$542, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$542, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$542, DW_AT_decl_line(0x197) + .dwattr $C$DW$542, DW_AT_decl_column(0x1d) + +$C$DW$543 .dwtag DW_TAG_member + .dwattr $C$DW$543, DW_AT_type(*$C$DW$T$341) + .dwattr $C$DW$543, DW_AT_name("initFxn") + .dwattr $C$DW$543, DW_AT_TI_symbol_name("initFxn") + .dwattr $C$DW$543, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$543, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$543, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$543, DW_AT_decl_line(0x19a) + .dwattr $C$DW$543, DW_AT_decl_column(0x1d) + +$C$DW$544 .dwtag DW_TAG_member + .dwattr $C$DW$544, DW_AT_type(*$C$DW$T$346) + .dwattr $C$DW$544, DW_AT_name("openFxn") + .dwattr $C$DW$544, DW_AT_TI_symbol_name("openFxn") + .dwattr $C$DW$544, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$544, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$544, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$544, DW_AT_decl_line(0x19d) + .dwattr $C$DW$544, DW_AT_decl_column(0x1d) + +$C$DW$545 .dwtag DW_TAG_member + .dwattr $C$DW$545, DW_AT_type(*$C$DW$T$349) + .dwattr $C$DW$545, DW_AT_name("transferFxn") + .dwattr $C$DW$545, DW_AT_TI_symbol_name("transferFxn") + .dwattr $C$DW$545, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$545, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$545, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$545, DW_AT_decl_line(0x1a0) + .dwattr $C$DW$545, DW_AT_decl_column(0x1d) + +$C$DW$546 .dwtag DW_TAG_member + .dwattr $C$DW$546, DW_AT_type(*$C$DW$T$350) + .dwattr $C$DW$546, DW_AT_name("transferCancelFxn") + .dwattr $C$DW$546, DW_AT_TI_symbol_name("transferCancelFxn") + .dwattr $C$DW$546, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$546, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$546, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$546, DW_AT_decl_line(0x1a3) + .dwattr $C$DW$546, DW_AT_decl_column(0x1d) + +$C$DW$547 .dwtag DW_TAG_member + .dwattr $C$DW$547, DW_AT_type(*$C$DW$T$351) + .dwattr $C$DW$547, DW_AT_name("serviceISRFxn") + .dwattr $C$DW$547, DW_AT_TI_symbol_name("serviceISRFxn") + .dwattr $C$DW$547, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$547, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$547, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$547, DW_AT_decl_line(0x1a6) + .dwattr $C$DW$547, DW_AT_decl_column(0x1d) + + .dwattr $C$DW$T$352, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$352, DW_AT_decl_line(0x192) + .dwattr $C$DW$T$352, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$352 + +$C$DW$T$331 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$331, DW_AT_name("SPI_FxnTable") + .dwattr $C$DW$T$331, DW_AT_type(*$C$DW$T$352) + .dwattr $C$DW$T$331, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$331, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$331, DW_AT_decl_line(0x1a7) + .dwattr $C$DW$T$331, DW_AT_decl_column(0x03) + +$C$DW$T$332 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$332, DW_AT_type(*$C$DW$T$331) + +$C$DW$T$333 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$333, DW_AT_type(*$C$DW$T$332) + .dwattr $C$DW$T$333, DW_AT_address_class(0x20) + + +$C$DW$T$353 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$353, DW_AT_name("SPI_Mode") + .dwattr $C$DW$T$353, DW_AT_byte_size(0x01) +$C$DW$548 .dwtag DW_TAG_enumerator + .dwattr $C$DW$548, DW_AT_name("SPI_MASTER") + .dwattr $C$DW$548, DW_AT_const_value(0x00) + .dwattr $C$DW$548, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$548, DW_AT_decl_line(0x121) + .dwattr $C$DW$548, DW_AT_decl_column(0x05) + +$C$DW$549 .dwtag DW_TAG_enumerator + .dwattr $C$DW$549, DW_AT_name("SPI_SLAVE") + .dwattr $C$DW$549, DW_AT_const_value(0x01) + .dwattr $C$DW$549, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$549, DW_AT_decl_line(0x122) + .dwattr $C$DW$549, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$353, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$353, DW_AT_decl_line(0x120) + .dwattr $C$DW$T$353, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$353 + +$C$DW$T$354 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$354, DW_AT_name("SPI_Mode") + .dwattr $C$DW$T$354, DW_AT_type(*$C$DW$T$353) + .dwattr $C$DW$T$354, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$354, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$354, DW_AT_decl_line(0x123) + .dwattr $C$DW$T$354, DW_AT_decl_column(0x03) + + +$C$DW$T$357 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$357, DW_AT_name("SPI_Params") + .dwattr $C$DW$T$357, DW_AT_byte_size(0x20) +$C$DW$550 .dwtag DW_TAG_member + .dwattr $C$DW$550, DW_AT_type(*$C$DW$T$320) + .dwattr $C$DW$550, DW_AT_name("transferMode") + .dwattr $C$DW$550, DW_AT_TI_symbol_name("transferMode") + .dwattr $C$DW$550, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$550, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$550, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$550, DW_AT_decl_line(0x152) + .dwattr $C$DW$550, DW_AT_decl_column(0x19) + +$C$DW$551 .dwtag DW_TAG_member + .dwattr $C$DW$551, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$551, DW_AT_name("transferTimeout") + .dwattr $C$DW$551, DW_AT_TI_symbol_name("transferTimeout") + .dwattr $C$DW$551, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$551, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$551, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$551, DW_AT_decl_line(0x153) + .dwattr $C$DW$551, DW_AT_decl_column(0x19) + +$C$DW$552 .dwtag DW_TAG_member + .dwattr $C$DW$552, DW_AT_type(*$C$DW$T$327) + .dwattr $C$DW$552, DW_AT_name("transferCallbackFxn") + .dwattr $C$DW$552, DW_AT_TI_symbol_name("transferCallbackFxn") + .dwattr $C$DW$552, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$552, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$552, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$552, DW_AT_decl_line(0x156) + .dwattr $C$DW$552, DW_AT_decl_column(0x19) + +$C$DW$553 .dwtag DW_TAG_member + .dwattr $C$DW$553, DW_AT_type(*$C$DW$T$354) + .dwattr $C$DW$553, DW_AT_name("mode") + .dwattr $C$DW$553, DW_AT_TI_symbol_name("mode") + .dwattr $C$DW$553, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$553, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$553, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$553, DW_AT_decl_line(0x157) + .dwattr $C$DW$553, DW_AT_decl_column(0x19) + +$C$DW$554 .dwtag DW_TAG_member + .dwattr $C$DW$554, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$554, DW_AT_name("bitRate") + .dwattr $C$DW$554, DW_AT_TI_symbol_name("bitRate") + .dwattr $C$DW$554, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$554, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$554, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$554, DW_AT_decl_line(0x158) + .dwattr $C$DW$554, DW_AT_decl_column(0x19) + +$C$DW$555 .dwtag DW_TAG_member + .dwattr $C$DW$555, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$555, DW_AT_name("dataSize") + .dwattr $C$DW$555, DW_AT_TI_symbol_name("dataSize") + .dwattr $C$DW$555, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$555, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$555, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$555, DW_AT_decl_line(0x159) + .dwattr $C$DW$555, DW_AT_decl_column(0x19) + +$C$DW$556 .dwtag DW_TAG_member + .dwattr $C$DW$556, DW_AT_type(*$C$DW$T$356) + .dwattr $C$DW$556, DW_AT_name("frameFormat") + .dwattr $C$DW$556, DW_AT_TI_symbol_name("frameFormat") + .dwattr $C$DW$556, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$556, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$556, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$556, DW_AT_decl_line(0x15a) + .dwattr $C$DW$556, DW_AT_decl_column(0x19) + +$C$DW$557 .dwtag DW_TAG_member + .dwattr $C$DW$557, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$557, DW_AT_name("custom") + .dwattr $C$DW$557, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$557, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$557, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$557, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$557, DW_AT_decl_line(0x15b) + .dwattr $C$DW$557, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$357, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$357, DW_AT_decl_line(0x151) + .dwattr $C$DW$T$357, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$357 + +$C$DW$T$342 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$342, DW_AT_name("SPI_Params") + .dwattr $C$DW$T$342, DW_AT_type(*$C$DW$T$357) + .dwattr $C$DW$T$342, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$342, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$342, DW_AT_decl_line(0x15d) + .dwattr $C$DW$T$342, DW_AT_decl_column(0x03) + +$C$DW$T$343 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$343, DW_AT_type(*$C$DW$T$342) + .dwattr $C$DW$T$343, DW_AT_address_class(0x20) + + +$C$DW$T$358 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$358, DW_AT_name("SPI_Status") + .dwattr $C$DW$T$358, DW_AT_byte_size(0x01) +$C$DW$558 .dwtag DW_TAG_enumerator + .dwattr $C$DW$558, DW_AT_name("SPI_TRANSFER_COMPLETED") + .dwattr $C$DW$558, DW_AT_const_value(0x00) + .dwattr $C$DW$558, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$558, DW_AT_decl_line(0xf7) + .dwattr $C$DW$558, DW_AT_decl_column(0x05) + +$C$DW$559 .dwtag DW_TAG_enumerator + .dwattr $C$DW$559, DW_AT_name("SPI_TRANSFER_STARTED") + .dwattr $C$DW$559, DW_AT_const_value(0x01) + .dwattr $C$DW$559, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$559, DW_AT_decl_line(0xf8) + .dwattr $C$DW$559, DW_AT_decl_column(0x05) + +$C$DW$560 .dwtag DW_TAG_enumerator + .dwattr $C$DW$560, DW_AT_name("SPI_TRANSFER_CANCELED") + .dwattr $C$DW$560, DW_AT_const_value(0x02) + .dwattr $C$DW$560, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$560, DW_AT_decl_line(0xf9) + .dwattr $C$DW$560, DW_AT_decl_column(0x05) + +$C$DW$561 .dwtag DW_TAG_enumerator + .dwattr $C$DW$561, DW_AT_name("SPI_TRANSFER_FAILED") + .dwattr $C$DW$561, DW_AT_const_value(0x03) + .dwattr $C$DW$561, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$561, DW_AT_decl_line(0xfa) + .dwattr $C$DW$561, DW_AT_decl_column(0x05) + +$C$DW$562 .dwtag DW_TAG_enumerator + .dwattr $C$DW$562, DW_AT_name("SPI_TRANSFER_CSN_DEASSERT") + .dwattr $C$DW$562, DW_AT_const_value(0x04) + .dwattr $C$DW$562, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$562, DW_AT_decl_line(0xfb) + .dwattr $C$DW$562, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$358, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$358, DW_AT_decl_line(0xf6) + .dwattr $C$DW$T$358, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$358 + +$C$DW$T$359 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$359, DW_AT_name("SPI_Status") + .dwattr $C$DW$T$359, DW_AT_type(*$C$DW$T$358) + .dwattr $C$DW$T$359, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$359, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$359, DW_AT_decl_line(0xfc) + .dwattr $C$DW$T$359, DW_AT_decl_column(0x03) + + +$C$DW$T$360 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$360, DW_AT_name("SPI_Transaction") + .dwattr $C$DW$T$360, DW_AT_byte_size(0x14) +$C$DW$563 .dwtag DW_TAG_member + .dwattr $C$DW$563, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$563, DW_AT_name("count") + .dwattr $C$DW$563, DW_AT_TI_symbol_name("count") + .dwattr $C$DW$563, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$563, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$563, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$563, DW_AT_decl_line(0x108) + .dwattr $C$DW$563, DW_AT_decl_column(0x10) + +$C$DW$564 .dwtag DW_TAG_member + .dwattr $C$DW$564, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$564, DW_AT_name("txBuf") + .dwattr $C$DW$564, DW_AT_TI_symbol_name("txBuf") + .dwattr $C$DW$564, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$564, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$564, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$564, DW_AT_decl_line(0x109) + .dwattr $C$DW$564, DW_AT_decl_column(0x10) + +$C$DW$565 .dwtag DW_TAG_member + .dwattr $C$DW$565, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$565, DW_AT_name("rxBuf") + .dwattr $C$DW$565, DW_AT_TI_symbol_name("rxBuf") + .dwattr $C$DW$565, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$565, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$565, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$565, DW_AT_decl_line(0x10a) + .dwattr $C$DW$565, DW_AT_decl_column(0x10) + +$C$DW$566 .dwtag DW_TAG_member + .dwattr $C$DW$566, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$566, DW_AT_name("arg") + .dwattr $C$DW$566, DW_AT_TI_symbol_name("arg") + .dwattr $C$DW$566, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$566, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$566, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$566, DW_AT_decl_line(0x10b) + .dwattr $C$DW$566, DW_AT_decl_column(0x10) + +$C$DW$567 .dwtag DW_TAG_member + .dwattr $C$DW$567, DW_AT_type(*$C$DW$T$359) + .dwattr $C$DW$567, DW_AT_name("status") + .dwattr $C$DW$567, DW_AT_TI_symbol_name("status") + .dwattr $C$DW$567, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$567, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$567, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$567, DW_AT_decl_line(0x10e) + .dwattr $C$DW$567, DW_AT_decl_column(0x10) + + .dwattr $C$DW$T$360, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$360, DW_AT_decl_line(0x106) + .dwattr $C$DW$T$360, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$360 + +$C$DW$T$323 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$323, DW_AT_name("SPI_Transaction") + .dwattr $C$DW$T$323, DW_AT_type(*$C$DW$T$360) + .dwattr $C$DW$T$323, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$323, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$323, DW_AT_decl_line(0x111) + .dwattr $C$DW$T$323, DW_AT_decl_column(0x03) + +$C$DW$T$324 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$324, DW_AT_type(*$C$DW$T$323) + .dwattr $C$DW$T$324, DW_AT_address_class(0x20) + + +$C$DW$T$319 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$319, DW_AT_name("SPI_TransferMode") + .dwattr $C$DW$T$319, DW_AT_byte_size(0x01) +$C$DW$568 .dwtag DW_TAG_enumerator + .dwattr $C$DW$568, DW_AT_name("SPI_MODE_BLOCKING") + .dwattr $C$DW$568, DW_AT_const_value(0x00) + .dwattr $C$DW$568, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$568, DW_AT_decl_line(0x141) + .dwattr $C$DW$568, DW_AT_decl_column(0x05) + +$C$DW$569 .dwtag DW_TAG_enumerator + .dwattr $C$DW$569, DW_AT_name("SPI_MODE_CALLBACK") + .dwattr $C$DW$569, DW_AT_const_value(0x01) + .dwattr $C$DW$569, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$569, DW_AT_decl_line(0x146) + .dwattr $C$DW$569, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$319, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$319, DW_AT_decl_line(0x13c) + .dwattr $C$DW$T$319, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$319 + +$C$DW$T$320 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$320, DW_AT_name("SPI_TransferMode") + .dwattr $C$DW$T$320, DW_AT_type(*$C$DW$T$319) + .dwattr $C$DW$T$320, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$320, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$320, DW_AT_decl_line(0x147) + .dwattr $C$DW$T$320, DW_AT_decl_column(0x03) + + +$C$DW$T$367 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$367, DW_AT_name("UARTTiva_FxnSet") + .dwattr $C$DW$T$367, DW_AT_byte_size(0x08) +$C$DW$570 .dwtag DW_TAG_member + .dwattr $C$DW$570, DW_AT_type(*$C$DW$T$364) + .dwattr $C$DW$570, DW_AT_name("readIsrFxn") + .dwattr $C$DW$570, DW_AT_TI_symbol_name("readIsrFxn") + .dwattr $C$DW$570, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$570, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$570, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$570, DW_AT_decl_line(0x75) + .dwattr $C$DW$570, DW_AT_decl_column(0x0c) + +$C$DW$571 .dwtag DW_TAG_member + .dwattr $C$DW$571, DW_AT_type(*$C$DW$T$366) + .dwattr $C$DW$571, DW_AT_name("readTaskFxn") + .dwattr $C$DW$571, DW_AT_TI_symbol_name("readTaskFxn") + .dwattr $C$DW$571, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$571, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$571, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$571, DW_AT_decl_line(0x76) + .dwattr $C$DW$571, DW_AT_decl_column(0x0c) + + .dwattr $C$DW$T$367, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$367, DW_AT_decl_line(0x74) + .dwattr $C$DW$T$367, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$367 + +$C$DW$T$377 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$377, DW_AT_name("UARTTiva_FxnSet") + .dwattr $C$DW$T$377, DW_AT_type(*$C$DW$T$367) + .dwattr $C$DW$T$377, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$377, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$377, DW_AT_decl_line(0x77) + .dwattr $C$DW$T$377, DW_AT_decl_column(0x03) + + +$C$DW$T$368 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$368, DW_AT_name("UARTTiva_HWAttrs") + .dwattr $C$DW$T$368, DW_AT_byte_size(0x18) +$C$DW$572 .dwtag DW_TAG_member + .dwattr $C$DW$572, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$572, DW_AT_name("baseAddr") + .dwattr $C$DW$572, DW_AT_TI_symbol_name("baseAddr") + .dwattr $C$DW$572, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$572, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$572, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$572, DW_AT_decl_line(0xa7) + .dwattr $C$DW$572, DW_AT_decl_column(0x15) + +$C$DW$573 .dwtag DW_TAG_member + .dwattr $C$DW$573, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$573, DW_AT_name("intNum") + .dwattr $C$DW$573, DW_AT_TI_symbol_name("intNum") + .dwattr $C$DW$573, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$573, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$573, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$573, DW_AT_decl_line(0xa9) + .dwattr $C$DW$573, DW_AT_decl_column(0x15) + +$C$DW$574 .dwtag DW_TAG_member + .dwattr $C$DW$574, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$574, DW_AT_name("intPriority") + .dwattr $C$DW$574, DW_AT_TI_symbol_name("intPriority") + .dwattr $C$DW$574, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$574, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$574, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$574, DW_AT_decl_line(0xab) + .dwattr $C$DW$574, DW_AT_decl_column(0x15) + +$C$DW$575 .dwtag DW_TAG_member + .dwattr $C$DW$575, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$575, DW_AT_name("flowControl") + .dwattr $C$DW$575, DW_AT_TI_symbol_name("flowControl") + .dwattr $C$DW$575, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$575, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$575, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$575, DW_AT_decl_line(0xad) + .dwattr $C$DW$575, DW_AT_decl_column(0x15) + +$C$DW$576 .dwtag DW_TAG_member + .dwattr $C$DW$576, DW_AT_type(*$C$DW$T$286) + .dwattr $C$DW$576, DW_AT_name("ringBufPtr") + .dwattr $C$DW$576, DW_AT_TI_symbol_name("ringBufPtr") + .dwattr $C$DW$576, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$576, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$576, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$576, DW_AT_decl_line(0xaf) + .dwattr $C$DW$576, DW_AT_decl_column(0x15) + +$C$DW$577 .dwtag DW_TAG_member + .dwattr $C$DW$577, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$577, DW_AT_name("ringBufSize") + .dwattr $C$DW$577, DW_AT_TI_symbol_name("ringBufSize") + .dwattr $C$DW$577, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$577, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$577, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$577, DW_AT_decl_line(0xb1) + .dwattr $C$DW$577, DW_AT_decl_column(0x15) + + .dwattr $C$DW$T$368, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$368, DW_AT_decl_line(0xa5) + .dwattr $C$DW$T$368, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$368 + +$C$DW$T$1047 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1047, DW_AT_name("UARTTiva_HWAttrs") + .dwattr $C$DW$T$1047, DW_AT_type(*$C$DW$T$368) + .dwattr $C$DW$T$1047, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1047, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$1047, DW_AT_decl_line(0xb2) + .dwattr $C$DW$T$1047, DW_AT_decl_column(0x03) + +$C$DW$T$1048 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1048, DW_AT_type(*$C$DW$T$1047) + + +$C$DW$T$1049 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1049, DW_AT_type(*$C$DW$T$1048) + .dwattr $C$DW$T$1049, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1049, DW_AT_byte_size(0x18) +$C$DW$578 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$578, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1049 + + +$C$DW$T$383 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$383, DW_AT_name("UARTTiva_Object") + .dwattr $C$DW$T$383, DW_AT_byte_size(0xcc) +$C$DW$579 .dwtag DW_TAG_member + .dwattr $C$DW$579, DW_AT_type(*$C$DW$T$150) + .dwattr $C$DW$579, DW_AT_name("state") + .dwattr $C$DW$579, DW_AT_TI_symbol_name("state") + .dwattr $C$DW$579, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$579, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$579, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$579, DW_AT_decl_line(0xd4) + .dwattr $C$DW$579, DW_AT_decl_column(0x07) + +$C$DW$580 .dwtag DW_TAG_member + .dwattr $C$DW$580, DW_AT_type(*$C$DW$T$369) + .dwattr $C$DW$580, DW_AT_name("timeoutClk") + .dwattr $C$DW$580, DW_AT_TI_symbol_name("timeoutClk") + .dwattr $C$DW$580, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$580, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$580, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$580, DW_AT_decl_line(0xd6) + .dwattr $C$DW$580, DW_AT_decl_column(0x1a) + +$C$DW$581 .dwtag DW_TAG_member + .dwattr $C$DW$581, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$581, DW_AT_name("baudRate") + .dwattr $C$DW$581, DW_AT_TI_symbol_name("baudRate") + .dwattr $C$DW$581, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$581, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$581, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$581, DW_AT_decl_line(0xd7) + .dwattr $C$DW$581, DW_AT_decl_column(0x1a) + +$C$DW$582 .dwtag DW_TAG_member + .dwattr $C$DW$582, DW_AT_type(*$C$DW$T$371) + .dwattr $C$DW$582, DW_AT_name("dataLength") + .dwattr $C$DW$582, DW_AT_TI_symbol_name("dataLength") + .dwattr $C$DW$582, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c] + .dwattr $C$DW$582, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$582, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$582, DW_AT_decl_line(0xd8) + .dwattr $C$DW$582, DW_AT_decl_column(0x1a) + +$C$DW$583 .dwtag DW_TAG_member + .dwattr $C$DW$583, DW_AT_type(*$C$DW$T$373) + .dwattr $C$DW$583, DW_AT_name("stopBits") + .dwattr $C$DW$583, DW_AT_TI_symbol_name("stopBits") + .dwattr $C$DW$583, DW_AT_data_member_location[DW_OP_plus_uconst 0x2d] + .dwattr $C$DW$583, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$583, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$583, DW_AT_decl_line(0xd9) + .dwattr $C$DW$583, DW_AT_decl_column(0x1a) + +$C$DW$584 .dwtag DW_TAG_member + .dwattr $C$DW$584, DW_AT_type(*$C$DW$T$375) + .dwattr $C$DW$584, DW_AT_name("parityType") + .dwattr $C$DW$584, DW_AT_TI_symbol_name("parityType") + .dwattr $C$DW$584, DW_AT_data_member_location[DW_OP_plus_uconst 0x2e] + .dwattr $C$DW$584, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$584, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$584, DW_AT_decl_line(0xda) + .dwattr $C$DW$584, DW_AT_decl_column(0x1a) + +$C$DW$585 .dwtag DW_TAG_member + .dwattr $C$DW$585, DW_AT_type(*$C$DW$T$376) + .dwattr $C$DW$585, DW_AT_name("ringBuffer") + .dwattr $C$DW$585, DW_AT_TI_symbol_name("ringBuffer") + .dwattr $C$DW$585, DW_AT_data_member_location[DW_OP_plus_uconst 0x30] + .dwattr $C$DW$585, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$585, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$585, DW_AT_decl_line(0xdd) + .dwattr $C$DW$585, DW_AT_decl_column(0x1a) + +$C$DW$586 .dwtag DW_TAG_member + .dwattr $C$DW$586, DW_AT_type(*$C$DW$T$377) + .dwattr $C$DW$586, DW_AT_name("readFxns") + .dwattr $C$DW$586, DW_AT_TI_symbol_name("readFxns") + .dwattr $C$DW$586, DW_AT_data_member_location[DW_OP_plus_uconst 0x48] + .dwattr $C$DW$586, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$586, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$586, DW_AT_decl_line(0xdf) + .dwattr $C$DW$586, DW_AT_decl_column(0x1a) + +$C$DW$587 .dwtag DW_TAG_member + .dwattr $C$DW$587, DW_AT_type(*$C$DW$T$286) + .dwattr $C$DW$587, DW_AT_name("readBuf") + .dwattr $C$DW$587, DW_AT_TI_symbol_name("readBuf") + .dwattr $C$DW$587, DW_AT_data_member_location[DW_OP_plus_uconst 0x50] + .dwattr $C$DW$587, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$587, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$587, DW_AT_decl_line(0xe0) + .dwattr $C$DW$587, DW_AT_decl_column(0x1a) + +$C$DW$588 .dwtag DW_TAG_member + .dwattr $C$DW$588, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$588, DW_AT_name("readSize") + .dwattr $C$DW$588, DW_AT_TI_symbol_name("readSize") + .dwattr $C$DW$588, DW_AT_data_member_location[DW_OP_plus_uconst 0x54] + .dwattr $C$DW$588, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$588, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$588, DW_AT_decl_line(0xe1) + .dwattr $C$DW$588, DW_AT_decl_column(0x1a) + +$C$DW$589 .dwtag DW_TAG_member + .dwattr $C$DW$589, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$589, DW_AT_name("readCount") + .dwattr $C$DW$589, DW_AT_TI_symbol_name("readCount") + .dwattr $C$DW$589, DW_AT_data_member_location[DW_OP_plus_uconst 0x58] + .dwattr $C$DW$589, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$589, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$589, DW_AT_decl_line(0xe2) + .dwattr $C$DW$589, DW_AT_decl_column(0x1a) + +$C$DW$590 .dwtag DW_TAG_member + .dwattr $C$DW$590, DW_AT_type(*$C$DW$T$200) + .dwattr $C$DW$590, DW_AT_name("readSem") + .dwattr $C$DW$590, DW_AT_TI_symbol_name("readSem") + .dwattr $C$DW$590, DW_AT_data_member_location[DW_OP_plus_uconst 0x5c] + .dwattr $C$DW$590, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$590, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$590, DW_AT_decl_line(0xe3) + .dwattr $C$DW$590, DW_AT_decl_column(0x1a) + +$C$DW$591 .dwtag DW_TAG_member + .dwattr $C$DW$591, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$591, DW_AT_name("readTimeout") + .dwattr $C$DW$591, DW_AT_TI_symbol_name("readTimeout") + .dwattr $C$DW$591, DW_AT_data_member_location[DW_OP_plus_uconst 0x78] + .dwattr $C$DW$591, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$591, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$591, DW_AT_decl_line(0xe4) + .dwattr $C$DW$591, DW_AT_decl_column(0x1a) + +$C$DW$592 .dwtag DW_TAG_member + .dwattr $C$DW$592, DW_AT_type(*$C$DW$T$380) + .dwattr $C$DW$592, DW_AT_name("readCallback") + .dwattr $C$DW$592, DW_AT_TI_symbol_name("readCallback") + .dwattr $C$DW$592, DW_AT_data_member_location[DW_OP_plus_uconst 0x7c] + .dwattr $C$DW$592, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$592, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$592, DW_AT_decl_line(0xe5) + .dwattr $C$DW$592, DW_AT_decl_column(0x1a) + +$C$DW$593 .dwtag DW_TAG_member + .dwattr $C$DW$593, DW_AT_type(*$C$DW$T$382) + .dwattr $C$DW$593, DW_AT_name("writeBuf") + .dwattr $C$DW$593, DW_AT_TI_symbol_name("writeBuf") + .dwattr $C$DW$593, DW_AT_data_member_location[DW_OP_plus_uconst 0x80] + .dwattr $C$DW$593, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$593, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$593, DW_AT_decl_line(0xe8) + .dwattr $C$DW$593, DW_AT_decl_column(0x1a) + +$C$DW$594 .dwtag DW_TAG_member + .dwattr $C$DW$594, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$594, DW_AT_name("writeSize") + .dwattr $C$DW$594, DW_AT_TI_symbol_name("writeSize") + .dwattr $C$DW$594, DW_AT_data_member_location[DW_OP_plus_uconst 0x84] + .dwattr $C$DW$594, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$594, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$594, DW_AT_decl_line(0xe9) + .dwattr $C$DW$594, DW_AT_decl_column(0x1a) + +$C$DW$595 .dwtag DW_TAG_member + .dwattr $C$DW$595, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$595, DW_AT_name("writeCount") + .dwattr $C$DW$595, DW_AT_TI_symbol_name("writeCount") + .dwattr $C$DW$595, DW_AT_data_member_location[DW_OP_plus_uconst 0x88] + .dwattr $C$DW$595, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$595, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$595, DW_AT_decl_line(0xea) + .dwattr $C$DW$595, DW_AT_decl_column(0x1a) + +$C$DW$596 .dwtag DW_TAG_member + .dwattr $C$DW$596, DW_AT_type(*$C$DW$T$200) + .dwattr $C$DW$596, DW_AT_name("writeSem") + .dwattr $C$DW$596, DW_AT_TI_symbol_name("writeSem") + .dwattr $C$DW$596, DW_AT_data_member_location[DW_OP_plus_uconst 0x8c] + .dwattr $C$DW$596, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$596, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$596, DW_AT_decl_line(0xeb) + .dwattr $C$DW$596, DW_AT_decl_column(0x1a) + +$C$DW$597 .dwtag DW_TAG_member + .dwattr $C$DW$597, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$597, DW_AT_name("writeTimeout") + .dwattr $C$DW$597, DW_AT_TI_symbol_name("writeTimeout") + .dwattr $C$DW$597, DW_AT_data_member_location[DW_OP_plus_uconst 0xa8] + .dwattr $C$DW$597, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$597, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$597, DW_AT_decl_line(0xec) + .dwattr $C$DW$597, DW_AT_decl_column(0x1a) + +$C$DW$598 .dwtag DW_TAG_member + .dwattr $C$DW$598, DW_AT_type(*$C$DW$T$380) + .dwattr $C$DW$598, DW_AT_name("writeCallback") + .dwattr $C$DW$598, DW_AT_TI_symbol_name("writeCallback") + .dwattr $C$DW$598, DW_AT_data_member_location[DW_OP_plus_uconst 0xac] + .dwattr $C$DW$598, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$598, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$598, DW_AT_decl_line(0xed) + .dwattr $C$DW$598, DW_AT_decl_column(0x1a) + +$C$DW$599 .dwtag DW_TAG_member + .dwattr $C$DW$599, DW_AT_type(*$C$DW$T$210) + .dwattr $C$DW$599, DW_AT_name("hwi") + .dwattr $C$DW$599, DW_AT_TI_symbol_name("hwi") + .dwattr $C$DW$599, DW_AT_data_member_location[DW_OP_plus_uconst 0xb0] + .dwattr $C$DW$599, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$599, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$599, DW_AT_decl_line(0xef) + .dwattr $C$DW$599, DW_AT_decl_column(0x29) + + .dwattr $C$DW$T$383, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$383, DW_AT_decl_line(0xb9) + .dwattr $C$DW$T$383, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$383 + +$C$DW$T$1051 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1051, DW_AT_name("UARTTiva_Object") + .dwattr $C$DW$T$1051, DW_AT_type(*$C$DW$T$383) + .dwattr $C$DW$T$1051, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1051, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$1051, DW_AT_decl_line(0xf0) + .dwattr $C$DW$T$1051, DW_AT_decl_column(0x03) + + +$C$DW$T$1052 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1052, DW_AT_type(*$C$DW$T$1051) + .dwattr $C$DW$T$1052, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1052, DW_AT_byte_size(0xcc) +$C$DW$600 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$600, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1052 + +$C$DW$T$1054 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1054, DW_AT_type(*$C$DW$T$383) + .dwattr $C$DW$T$1054, DW_AT_address_class(0x20) + +$C$DW$T$1055 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1055, DW_AT_name("UARTTiva_Handle") + .dwattr $C$DW$T$1055, DW_AT_type(*$C$DW$T$1054) + .dwattr $C$DW$T$1055, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1055, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h") + .dwattr $C$DW$T$1055, DW_AT_decl_line(0xf0) + .dwattr $C$DW$T$1055, DW_AT_decl_column(0x15) + + +$C$DW$T$387 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$387, DW_AT_name("UART_Config") + .dwattr $C$DW$T$387, DW_AT_byte_size(0x0c) +$C$DW$601 .dwtag DW_TAG_member + .dwattr $C$DW$601, DW_AT_type(*$C$DW$T$386) + .dwattr $C$DW$601, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$601, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$601, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$601, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$601, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$601, DW_AT_decl_line(0x22f) + .dwattr $C$DW$601, DW_AT_decl_column(0x1d) + +$C$DW$602 .dwtag DW_TAG_member + .dwattr $C$DW$602, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$602, DW_AT_name("object") + .dwattr $C$DW$602, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$602, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$602, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$602, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$602, DW_AT_decl_line(0x232) + .dwattr $C$DW$602, DW_AT_decl_column(0x1d) + +$C$DW$603 .dwtag DW_TAG_member + .dwattr $C$DW$603, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$603, DW_AT_name("hwAttrs") + .dwattr $C$DW$603, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$603, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$603, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$603, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$603, DW_AT_decl_line(0x235) + .dwattr $C$DW$603, DW_AT_decl_column(0x1d) + + .dwattr $C$DW$T$387, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$387, DW_AT_decl_line(0x22d) + .dwattr $C$DW$T$387, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$387 + +$C$DW$T$1056 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1056, DW_AT_name("UART_Config") + .dwattr $C$DW$T$1056, DW_AT_type(*$C$DW$T$387) + .dwattr $C$DW$T$1056, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1056, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$1056, DW_AT_decl_line(0x236) + .dwattr $C$DW$T$1056, DW_AT_decl_column(0x03) + +$C$DW$T$1057 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1057, DW_AT_type(*$C$DW$T$1056) + + +$C$DW$T$1058 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1058, DW_AT_type(*$C$DW$T$1057) + .dwattr $C$DW$T$1058, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1058, DW_AT_byte_size(0x18) +$C$DW$604 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$604, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1058 + +$C$DW$T$361 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$361, DW_AT_type(*$C$DW$T$387) + .dwattr $C$DW$T$361, DW_AT_address_class(0x20) + +$C$DW$T$362 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$362, DW_AT_name("UART_Handle") + .dwattr $C$DW$T$362, DW_AT_type(*$C$DW$T$361) + .dwattr $C$DW$T$362, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$362, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$362, DW_AT_decl_line(0x11a) + .dwattr $C$DW$T$362, DW_AT_decl_column(0x22) + + +$C$DW$T$397 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$397, DW_AT_type(*$C$DW$T$362) + .dwattr $C$DW$T$397, DW_AT_language(DW_LANG_C) +$C$DW$605 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$605, DW_AT_type(*$C$DW$T$362) + +$C$DW$606 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$606, DW_AT_type(*$C$DW$T$396) + + .dwendtag $C$DW$T$397 + +$C$DW$T$398 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$398, DW_AT_type(*$C$DW$T$397) + .dwattr $C$DW$T$398, DW_AT_address_class(0x20) + +$C$DW$T$399 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$399, DW_AT_name("UART_OpenFxn") + .dwattr $C$DW$T$399, DW_AT_type(*$C$DW$T$398) + .dwattr $C$DW$T$399, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$399, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$399, DW_AT_decl_line(0x1d1) + .dwattr $C$DW$T$399, DW_AT_decl_column(0x17) + + +$C$DW$T$144 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$144, DW_AT_name("UART_DataMode") + .dwattr $C$DW$T$144, DW_AT_byte_size(0x01) +$C$DW$607 .dwtag DW_TAG_enumerator + .dwattr $C$DW$607, DW_AT_name("UART_DATA_BINARY") + .dwattr $C$DW$607, DW_AT_const_value(0x00) + .dwattr $C$DW$607, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$607, DW_AT_decl_line(0x165) + .dwattr $C$DW$607, DW_AT_decl_column(0x05) + +$C$DW$608 .dwtag DW_TAG_enumerator + .dwattr $C$DW$608, DW_AT_name("UART_DATA_TEXT") + .dwattr $C$DW$608, DW_AT_const_value(0x01) + .dwattr $C$DW$608, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$608, DW_AT_decl_line(0x166) + .dwattr $C$DW$608, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$144, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$144, DW_AT_decl_line(0x164) + .dwattr $C$DW$T$144, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$144 + +$C$DW$T$145 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$145, DW_AT_name("UART_DataMode") + .dwattr $C$DW$T$145, DW_AT_type(*$C$DW$T$144) + .dwattr $C$DW$T$145, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$145, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$145, DW_AT_decl_line(0x167) + .dwattr $C$DW$T$145, DW_AT_decl_column(0x03) + + +$C$DW$T$148 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$148, DW_AT_name("UART_Echo") + .dwattr $C$DW$T$148, DW_AT_byte_size(0x01) +$C$DW$609 .dwtag DW_TAG_enumerator + .dwattr $C$DW$609, DW_AT_name("UART_ECHO_OFF") + .dwattr $C$DW$609, DW_AT_const_value(0x00) + .dwattr $C$DW$609, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$609, DW_AT_decl_line(0x177) + .dwattr $C$DW$609, DW_AT_decl_column(0x05) + +$C$DW$610 .dwtag DW_TAG_enumerator + .dwattr $C$DW$610, DW_AT_name("UART_ECHO_ON") + .dwattr $C$DW$610, DW_AT_const_value(0x01) + .dwattr $C$DW$610, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$610, DW_AT_decl_line(0x178) + .dwattr $C$DW$610, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$148, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$148, DW_AT_decl_line(0x176) + .dwattr $C$DW$T$148, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$148 + +$C$DW$T$149 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$149, DW_AT_name("UART_Echo") + .dwattr $C$DW$T$149, DW_AT_type(*$C$DW$T$148) + .dwattr $C$DW$T$149, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$149, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$149, DW_AT_decl_line(0x179) + .dwattr $C$DW$T$149, DW_AT_decl_column(0x03) + + +$C$DW$T$410 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$410, DW_AT_name("UART_FxnTable") + .dwattr $C$DW$T$410, DW_AT_byte_size(0x28) +$C$DW$611 .dwtag DW_TAG_member + .dwattr $C$DW$611, DW_AT_type(*$C$DW$T$390) + .dwattr $C$DW$611, DW_AT_name("closeFxn") + .dwattr $C$DW$611, DW_AT_TI_symbol_name("closeFxn") + .dwattr $C$DW$611, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$611, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$611, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$611, DW_AT_decl_line(0x204) + .dwattr $C$DW$611, DW_AT_decl_column(0x1d) + +$C$DW$612 .dwtag DW_TAG_member + .dwattr $C$DW$612, DW_AT_type(*$C$DW$T$393) + .dwattr $C$DW$612, DW_AT_name("controlFxn") + .dwattr $C$DW$612, DW_AT_TI_symbol_name("controlFxn") + .dwattr $C$DW$612, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$612, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$612, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$612, DW_AT_decl_line(0x207) + .dwattr $C$DW$612, DW_AT_decl_column(0x1d) + +$C$DW$613 .dwtag DW_TAG_member + .dwattr $C$DW$613, DW_AT_type(*$C$DW$T$394) + .dwattr $C$DW$613, DW_AT_name("initFxn") + .dwattr $C$DW$613, DW_AT_TI_symbol_name("initFxn") + .dwattr $C$DW$613, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$613, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$613, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$613, DW_AT_decl_line(0x20a) + .dwattr $C$DW$613, DW_AT_decl_column(0x1d) + +$C$DW$614 .dwtag DW_TAG_member + .dwattr $C$DW$614, DW_AT_type(*$C$DW$T$399) + .dwattr $C$DW$614, DW_AT_name("openFxn") + .dwattr $C$DW$614, DW_AT_TI_symbol_name("openFxn") + .dwattr $C$DW$614, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$614, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$614, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$614, DW_AT_decl_line(0x20d) + .dwattr $C$DW$614, DW_AT_decl_column(0x1d) + +$C$DW$615 .dwtag DW_TAG_member + .dwattr $C$DW$615, DW_AT_type(*$C$DW$T$402) + .dwattr $C$DW$615, DW_AT_name("readFxn") + .dwattr $C$DW$615, DW_AT_TI_symbol_name("readFxn") + .dwattr $C$DW$615, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$615, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$615, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$615, DW_AT_decl_line(0x210) + .dwattr $C$DW$615, DW_AT_decl_column(0x1d) + +$C$DW$616 .dwtag DW_TAG_member + .dwattr $C$DW$616, DW_AT_type(*$C$DW$T$403) + .dwattr $C$DW$616, DW_AT_name("readPollingFxn") + .dwattr $C$DW$616, DW_AT_TI_symbol_name("readPollingFxn") + .dwattr $C$DW$616, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$616, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$616, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$616, DW_AT_decl_line(0x213) + .dwattr $C$DW$616, DW_AT_decl_column(0x1d) + +$C$DW$617 .dwtag DW_TAG_member + .dwattr $C$DW$617, DW_AT_type(*$C$DW$T$404) + .dwattr $C$DW$617, DW_AT_name("readCancelFxn") + .dwattr $C$DW$617, DW_AT_TI_symbol_name("readCancelFxn") + .dwattr $C$DW$617, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$617, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$617, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$617, DW_AT_decl_line(0x216) + .dwattr $C$DW$617, DW_AT_decl_column(0x1d) + +$C$DW$618 .dwtag DW_TAG_member + .dwattr $C$DW$618, DW_AT_type(*$C$DW$T$407) + .dwattr $C$DW$618, DW_AT_name("writeFxn") + .dwattr $C$DW$618, DW_AT_TI_symbol_name("writeFxn") + .dwattr $C$DW$618, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$618, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$618, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$618, DW_AT_decl_line(0x219) + .dwattr $C$DW$618, DW_AT_decl_column(0x1d) + +$C$DW$619 .dwtag DW_TAG_member + .dwattr $C$DW$619, DW_AT_type(*$C$DW$T$408) + .dwattr $C$DW$619, DW_AT_name("writePollingFxn") + .dwattr $C$DW$619, DW_AT_TI_symbol_name("writePollingFxn") + .dwattr $C$DW$619, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$619, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$619, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$619, DW_AT_decl_line(0x21c) + .dwattr $C$DW$619, DW_AT_decl_column(0x1d) + +$C$DW$620 .dwtag DW_TAG_member + .dwattr $C$DW$620, DW_AT_type(*$C$DW$T$409) + .dwattr $C$DW$620, DW_AT_name("writeCancelFxn") + .dwattr $C$DW$620, DW_AT_TI_symbol_name("writeCancelFxn") + .dwattr $C$DW$620, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$620, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$620, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$620, DW_AT_decl_line(0x21f) + .dwattr $C$DW$620, DW_AT_decl_column(0x1d) + + .dwattr $C$DW$T$410, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$410, DW_AT_decl_line(0x202) + .dwattr $C$DW$T$410, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$410 + +$C$DW$T$384 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$384, DW_AT_name("UART_FxnTable") + .dwattr $C$DW$T$384, DW_AT_type(*$C$DW$T$410) + .dwattr $C$DW$T$384, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$384, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$384, DW_AT_decl_line(0x220) + .dwattr $C$DW$T$384, DW_AT_decl_column(0x03) + +$C$DW$T$385 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$385, DW_AT_type(*$C$DW$T$384) + +$C$DW$T$386 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$386, DW_AT_type(*$C$DW$T$385) + .dwattr $C$DW$T$386, DW_AT_address_class(0x20) + + +$C$DW$T$370 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$370, DW_AT_name("UART_LEN") + .dwattr $C$DW$T$370, DW_AT_byte_size(0x01) +$C$DW$621 .dwtag DW_TAG_enumerator + .dwattr $C$DW$621, DW_AT_name("UART_LEN_5") + .dwattr $C$DW$621, DW_AT_const_value(0x00) + .dwattr $C$DW$621, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$621, DW_AT_decl_line(0x181) + .dwattr $C$DW$621, DW_AT_decl_column(0x05) + +$C$DW$622 .dwtag DW_TAG_enumerator + .dwattr $C$DW$622, DW_AT_name("UART_LEN_6") + .dwattr $C$DW$622, DW_AT_const_value(0x01) + .dwattr $C$DW$622, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$622, DW_AT_decl_line(0x182) + .dwattr $C$DW$622, DW_AT_decl_column(0x05) + +$C$DW$623 .dwtag DW_TAG_enumerator + .dwattr $C$DW$623, DW_AT_name("UART_LEN_7") + .dwattr $C$DW$623, DW_AT_const_value(0x02) + .dwattr $C$DW$623, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$623, DW_AT_decl_line(0x183) + .dwattr $C$DW$623, DW_AT_decl_column(0x05) + +$C$DW$624 .dwtag DW_TAG_enumerator + .dwattr $C$DW$624, DW_AT_name("UART_LEN_8") + .dwattr $C$DW$624, DW_AT_const_value(0x03) + .dwattr $C$DW$624, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$624, DW_AT_decl_line(0x184) + .dwattr $C$DW$624, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$370, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$370, DW_AT_decl_line(0x180) + .dwattr $C$DW$T$370, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$370 + +$C$DW$T$371 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$371, DW_AT_name("UART_LEN") + .dwattr $C$DW$T$371, DW_AT_type(*$C$DW$T$370) + .dwattr $C$DW$T$371, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$371, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$371, DW_AT_decl_line(0x185) + .dwattr $C$DW$T$371, DW_AT_decl_column(0x03) + + +$C$DW$T$142 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$142, DW_AT_name("UART_Mode") + .dwattr $C$DW$T$142, DW_AT_byte_size(0x01) +$C$DW$625 .dwtag DW_TAG_enumerator + .dwattr $C$DW$625, DW_AT_name("UART_MODE_BLOCKING") + .dwattr $C$DW$625, DW_AT_const_value(0x00) + .dwattr $C$DW$625, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$625, DW_AT_decl_line(0x139) + .dwattr $C$DW$625, DW_AT_decl_column(0x05) + +$C$DW$626 .dwtag DW_TAG_enumerator + .dwattr $C$DW$626, DW_AT_name("UART_MODE_CALLBACK") + .dwattr $C$DW$626, DW_AT_const_value(0x01) + .dwattr $C$DW$626, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$626, DW_AT_decl_line(0x140) + .dwattr $C$DW$626, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$142, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$142, DW_AT_decl_line(0x134) + .dwattr $C$DW$T$142, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$142 + +$C$DW$T$143 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$143, DW_AT_name("UART_Mode") + .dwattr $C$DW$T$143, DW_AT_type(*$C$DW$T$142) + .dwattr $C$DW$T$143, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$143, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$143, DW_AT_decl_line(0x141) + .dwattr $C$DW$T$143, DW_AT_decl_column(0x03) + + +$C$DW$T$374 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$374, DW_AT_name("UART_PAR") + .dwattr $C$DW$T$374, DW_AT_byte_size(0x01) +$C$DW$627 .dwtag DW_TAG_enumerator + .dwattr $C$DW$627, DW_AT_name("UART_PAR_NONE") + .dwattr $C$DW$627, DW_AT_const_value(0x00) + .dwattr $C$DW$627, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$627, DW_AT_decl_line(0x197) + .dwattr $C$DW$627, DW_AT_decl_column(0x05) + +$C$DW$628 .dwtag DW_TAG_enumerator + .dwattr $C$DW$628, DW_AT_name("UART_PAR_EVEN") + .dwattr $C$DW$628, DW_AT_const_value(0x01) + .dwattr $C$DW$628, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$628, DW_AT_decl_line(0x198) + .dwattr $C$DW$628, DW_AT_decl_column(0x05) + +$C$DW$629 .dwtag DW_TAG_enumerator + .dwattr $C$DW$629, DW_AT_name("UART_PAR_ODD") + .dwattr $C$DW$629, DW_AT_const_value(0x02) + .dwattr $C$DW$629, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$629, DW_AT_decl_line(0x199) + .dwattr $C$DW$629, DW_AT_decl_column(0x05) + +$C$DW$630 .dwtag DW_TAG_enumerator + .dwattr $C$DW$630, DW_AT_name("UART_PAR_ZERO") + .dwattr $C$DW$630, DW_AT_const_value(0x03) + .dwattr $C$DW$630, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$630, DW_AT_decl_line(0x19a) + .dwattr $C$DW$630, DW_AT_decl_column(0x05) + +$C$DW$631 .dwtag DW_TAG_enumerator + .dwattr $C$DW$631, DW_AT_name("UART_PAR_ONE") + .dwattr $C$DW$631, DW_AT_const_value(0x04) + .dwattr $C$DW$631, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$631, DW_AT_decl_line(0x19b) + .dwattr $C$DW$631, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$374, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$374, DW_AT_decl_line(0x196) + .dwattr $C$DW$T$374, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$374 + +$C$DW$T$375 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$375, DW_AT_name("UART_PAR") + .dwattr $C$DW$T$375, DW_AT_type(*$C$DW$T$374) + .dwattr $C$DW$T$375, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$375, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$375, DW_AT_decl_line(0x19c) + .dwattr $C$DW$T$375, DW_AT_decl_column(0x03) + + +$C$DW$T$411 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$411, DW_AT_name("UART_Params") + .dwattr $C$DW$T$411, DW_AT_byte_size(0x24) +$C$DW$632 .dwtag DW_TAG_member + .dwattr $C$DW$632, DW_AT_type(*$C$DW$T$143) + .dwattr $C$DW$632, DW_AT_name("readMode") + .dwattr $C$DW$632, DW_AT_TI_symbol_name("readMode") + .dwattr $C$DW$632, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$632, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$632, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$632, DW_AT_decl_line(0x1a7) + .dwattr $C$DW$632, DW_AT_decl_column(0x17) + +$C$DW$633 .dwtag DW_TAG_member + .dwattr $C$DW$633, DW_AT_type(*$C$DW$T$143) + .dwattr $C$DW$633, DW_AT_name("writeMode") + .dwattr $C$DW$633, DW_AT_TI_symbol_name("writeMode") + .dwattr $C$DW$633, DW_AT_data_member_location[DW_OP_plus_uconst 0x1] + .dwattr $C$DW$633, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$633, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$633, DW_AT_decl_line(0x1a8) + .dwattr $C$DW$633, DW_AT_decl_column(0x17) + +$C$DW$634 .dwtag DW_TAG_member + .dwattr $C$DW$634, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$634, DW_AT_name("readTimeout") + .dwattr $C$DW$634, DW_AT_TI_symbol_name("readTimeout") + .dwattr $C$DW$634, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$634, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$634, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$634, DW_AT_decl_line(0x1a9) + .dwattr $C$DW$634, DW_AT_decl_column(0x17) + +$C$DW$635 .dwtag DW_TAG_member + .dwattr $C$DW$635, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$635, DW_AT_name("writeTimeout") + .dwattr $C$DW$635, DW_AT_TI_symbol_name("writeTimeout") + .dwattr $C$DW$635, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$635, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$635, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$635, DW_AT_decl_line(0x1aa) + .dwattr $C$DW$635, DW_AT_decl_column(0x17) + +$C$DW$636 .dwtag DW_TAG_member + .dwattr $C$DW$636, DW_AT_type(*$C$DW$T$380) + .dwattr $C$DW$636, DW_AT_name("readCallback") + .dwattr $C$DW$636, DW_AT_TI_symbol_name("readCallback") + .dwattr $C$DW$636, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$636, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$636, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$636, DW_AT_decl_line(0x1ab) + .dwattr $C$DW$636, DW_AT_decl_column(0x17) + +$C$DW$637 .dwtag DW_TAG_member + .dwattr $C$DW$637, DW_AT_type(*$C$DW$T$380) + .dwattr $C$DW$637, DW_AT_name("writeCallback") + .dwattr $C$DW$637, DW_AT_TI_symbol_name("writeCallback") + .dwattr $C$DW$637, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$637, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$637, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$637, DW_AT_decl_line(0x1ac) + .dwattr $C$DW$637, DW_AT_decl_column(0x17) + +$C$DW$638 .dwtag DW_TAG_member + .dwattr $C$DW$638, DW_AT_type(*$C$DW$T$147) + .dwattr $C$DW$638, DW_AT_name("readReturnMode") + .dwattr $C$DW$638, DW_AT_TI_symbol_name("readReturnMode") + .dwattr $C$DW$638, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$638, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$638, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$638, DW_AT_decl_line(0x1ad) + .dwattr $C$DW$638, DW_AT_decl_column(0x17) + +$C$DW$639 .dwtag DW_TAG_member + .dwattr $C$DW$639, DW_AT_type(*$C$DW$T$145) + .dwattr $C$DW$639, DW_AT_name("readDataMode") + .dwattr $C$DW$639, DW_AT_TI_symbol_name("readDataMode") + .dwattr $C$DW$639, DW_AT_data_member_location[DW_OP_plus_uconst 0x15] + .dwattr $C$DW$639, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$639, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$639, DW_AT_decl_line(0x1ae) + .dwattr $C$DW$639, DW_AT_decl_column(0x17) + +$C$DW$640 .dwtag DW_TAG_member + .dwattr $C$DW$640, DW_AT_type(*$C$DW$T$145) + .dwattr $C$DW$640, DW_AT_name("writeDataMode") + .dwattr $C$DW$640, DW_AT_TI_symbol_name("writeDataMode") + .dwattr $C$DW$640, DW_AT_data_member_location[DW_OP_plus_uconst 0x16] + .dwattr $C$DW$640, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$640, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$640, DW_AT_decl_line(0x1af) + .dwattr $C$DW$640, DW_AT_decl_column(0x17) + +$C$DW$641 .dwtag DW_TAG_member + .dwattr $C$DW$641, DW_AT_type(*$C$DW$T$149) + .dwattr $C$DW$641, DW_AT_name("readEcho") + .dwattr $C$DW$641, DW_AT_TI_symbol_name("readEcho") + .dwattr $C$DW$641, DW_AT_data_member_location[DW_OP_plus_uconst 0x17] + .dwattr $C$DW$641, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$641, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$641, DW_AT_decl_line(0x1b0) + .dwattr $C$DW$641, DW_AT_decl_column(0x17) + +$C$DW$642 .dwtag DW_TAG_member + .dwattr $C$DW$642, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$642, DW_AT_name("baudRate") + .dwattr $C$DW$642, DW_AT_TI_symbol_name("baudRate") + .dwattr $C$DW$642, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$642, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$642, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$642, DW_AT_decl_line(0x1b1) + .dwattr $C$DW$642, DW_AT_decl_column(0x17) + +$C$DW$643 .dwtag DW_TAG_member + .dwattr $C$DW$643, DW_AT_type(*$C$DW$T$371) + .dwattr $C$DW$643, DW_AT_name("dataLength") + .dwattr $C$DW$643, DW_AT_TI_symbol_name("dataLength") + .dwattr $C$DW$643, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$643, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$643, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$643, DW_AT_decl_line(0x1b2) + .dwattr $C$DW$643, DW_AT_decl_column(0x17) + +$C$DW$644 .dwtag DW_TAG_member + .dwattr $C$DW$644, DW_AT_type(*$C$DW$T$373) + .dwattr $C$DW$644, DW_AT_name("stopBits") + .dwattr $C$DW$644, DW_AT_TI_symbol_name("stopBits") + .dwattr $C$DW$644, DW_AT_data_member_location[DW_OP_plus_uconst 0x1d] + .dwattr $C$DW$644, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$644, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$644, DW_AT_decl_line(0x1b3) + .dwattr $C$DW$644, DW_AT_decl_column(0x17) + +$C$DW$645 .dwtag DW_TAG_member + .dwattr $C$DW$645, DW_AT_type(*$C$DW$T$375) + .dwattr $C$DW$645, DW_AT_name("parityType") + .dwattr $C$DW$645, DW_AT_TI_symbol_name("parityType") + .dwattr $C$DW$645, DW_AT_data_member_location[DW_OP_plus_uconst 0x1e] + .dwattr $C$DW$645, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$645, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$645, DW_AT_decl_line(0x1b4) + .dwattr $C$DW$645, DW_AT_decl_column(0x17) + +$C$DW$646 .dwtag DW_TAG_member + .dwattr $C$DW$646, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$646, DW_AT_name("custom") + .dwattr $C$DW$646, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$646, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$646, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$646, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$646, DW_AT_decl_line(0x1b5) + .dwattr $C$DW$646, DW_AT_decl_column(0x17) + + .dwattr $C$DW$T$411, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$411, DW_AT_decl_line(0x1a6) + .dwattr $C$DW$T$411, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$411 + +$C$DW$T$395 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$395, DW_AT_name("UART_Params") + .dwattr $C$DW$T$395, DW_AT_type(*$C$DW$T$411) + .dwattr $C$DW$T$395, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$395, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$395, DW_AT_decl_line(0x1b7) + .dwattr $C$DW$T$395, DW_AT_decl_column(0x03) + +$C$DW$T$396 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$396, DW_AT_type(*$C$DW$T$395) + .dwattr $C$DW$T$396, DW_AT_address_class(0x20) + + +$C$DW$T$146 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$146, DW_AT_name("UART_ReturnMode") + .dwattr $C$DW$T$146, DW_AT_byte_size(0x01) +$C$DW$647 .dwtag DW_TAG_enumerator + .dwattr $C$DW$647, DW_AT_name("UART_RETURN_FULL") + .dwattr $C$DW$647, DW_AT_const_value(0x00) + .dwattr $C$DW$647, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$647, DW_AT_decl_line(0x157) + .dwattr $C$DW$647, DW_AT_decl_column(0x05) + +$C$DW$648 .dwtag DW_TAG_enumerator + .dwattr $C$DW$648, DW_AT_name("UART_RETURN_NEWLINE") + .dwattr $C$DW$648, DW_AT_const_value(0x01) + .dwattr $C$DW$648, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$648, DW_AT_decl_line(0x15a) + .dwattr $C$DW$648, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$146, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$146, DW_AT_decl_line(0x155) + .dwattr $C$DW$T$146, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$146 + +$C$DW$T$147 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$147, DW_AT_name("UART_ReturnMode") + .dwattr $C$DW$T$147, DW_AT_type(*$C$DW$T$146) + .dwattr $C$DW$T$147, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$147, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$147, DW_AT_decl_line(0x15b) + .dwattr $C$DW$T$147, DW_AT_decl_column(0x03) + + +$C$DW$T$372 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$372, DW_AT_name("UART_STOP") + .dwattr $C$DW$T$372, DW_AT_byte_size(0x01) +$C$DW$649 .dwtag DW_TAG_enumerator + .dwattr $C$DW$649, DW_AT_name("UART_STOP_ONE") + .dwattr $C$DW$649, DW_AT_const_value(0x00) + .dwattr $C$DW$649, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$649, DW_AT_decl_line(0x18d) + .dwattr $C$DW$649, DW_AT_decl_column(0x05) + +$C$DW$650 .dwtag DW_TAG_enumerator + .dwattr $C$DW$650, DW_AT_name("UART_STOP_TWO") + .dwattr $C$DW$650, DW_AT_const_value(0x01) + .dwattr $C$DW$650, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$650, DW_AT_decl_line(0x18e) + .dwattr $C$DW$650, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$372, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$372, DW_AT_decl_line(0x18c) + .dwattr $C$DW$T$372, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$372 + +$C$DW$T$373 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$373, DW_AT_name("UART_STOP") + .dwattr $C$DW$T$373, DW_AT_type(*$C$DW$T$372) + .dwattr $C$DW$T$373, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$373, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$373, DW_AT_decl_line(0x18f) + .dwattr $C$DW$T$373, DW_AT_decl_column(0x03) + + +$C$DW$T$412 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$412, DW_AT_name("WatchdogTiva_HWAttrs") + .dwattr $C$DW$T$412, DW_AT_byte_size(0x10) +$C$DW$651 .dwtag DW_TAG_member + .dwattr $C$DW$651, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$651, DW_AT_name("baseAddr") + .dwattr $C$DW$651, DW_AT_TI_symbol_name("baseAddr") + .dwattr $C$DW$651, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$651, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$651, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$651, DW_AT_decl_line(0x92) + .dwattr $C$DW$651, DW_AT_decl_column(0x12) + +$C$DW$652 .dwtag DW_TAG_member + .dwattr $C$DW$652, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$652, DW_AT_name("intNum") + .dwattr $C$DW$652, DW_AT_TI_symbol_name("intNum") + .dwattr $C$DW$652, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$652, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$652, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$652, DW_AT_decl_line(0x93) + .dwattr $C$DW$652, DW_AT_decl_column(0x12) + +$C$DW$653 .dwtag DW_TAG_member + .dwattr $C$DW$653, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$653, DW_AT_name("intPriority") + .dwattr $C$DW$653, DW_AT_TI_symbol_name("intPriority") + .dwattr $C$DW$653, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$653, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$653, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$653, DW_AT_decl_line(0x94) + .dwattr $C$DW$653, DW_AT_decl_column(0x12) + +$C$DW$654 .dwtag DW_TAG_member + .dwattr $C$DW$654, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$654, DW_AT_name("reloadValue") + .dwattr $C$DW$654, DW_AT_TI_symbol_name("reloadValue") + .dwattr $C$DW$654, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$654, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$654, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$654, DW_AT_decl_line(0x95) + .dwattr $C$DW$654, DW_AT_decl_column(0x12) + + .dwattr $C$DW$T$412, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$T$412, DW_AT_decl_line(0x91) + .dwattr $C$DW$T$412, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$412 + +$C$DW$T$1059 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1059, DW_AT_name("WatchdogTiva_HWAttrs") + .dwattr $C$DW$T$1059, DW_AT_type(*$C$DW$T$412) + .dwattr $C$DW$T$1059, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1059, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$T$1059, DW_AT_decl_line(0x96) + .dwattr $C$DW$T$1059, DW_AT_decl_column(0x03) + +$C$DW$T$1060 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1060, DW_AT_type(*$C$DW$T$1059) + + +$C$DW$T$1061 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1061, DW_AT_type(*$C$DW$T$1060) + .dwattr $C$DW$T$1061, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1061, DW_AT_byte_size(0x10) +$C$DW$655 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$655, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1061 + + +$C$DW$T$413 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$413, DW_AT_name("WatchdogTiva_Object") + .dwattr $C$DW$T$413, DW_AT_byte_size(0x20) +$C$DW$656 .dwtag DW_TAG_member + .dwattr $C$DW$656, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$656, DW_AT_name("isOpen") + .dwattr $C$DW$656, DW_AT_TI_symbol_name("isOpen") + .dwattr $C$DW$656, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$656, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$656, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$656, DW_AT_decl_line(0x9e) + .dwattr $C$DW$656, DW_AT_decl_column(0x12) + +$C$DW$657 .dwtag DW_TAG_member + .dwattr $C$DW$657, DW_AT_type(*$C$DW$T$210) + .dwattr $C$DW$657, DW_AT_name("hwi") + .dwattr $C$DW$657, DW_AT_TI_symbol_name("hwi") + .dwattr $C$DW$657, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$657, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$657, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$657, DW_AT_decl_line(0x9f) + .dwattr $C$DW$657, DW_AT_decl_column(0x29) + + .dwattr $C$DW$T$413, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$T$413, DW_AT_decl_line(0x9d) + .dwattr $C$DW$T$413, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$413 + +$C$DW$T$1063 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1063, DW_AT_name("WatchdogTiva_Object") + .dwattr $C$DW$T$1063, DW_AT_type(*$C$DW$T$413) + .dwattr $C$DW$T$1063, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1063, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h") + .dwattr $C$DW$T$1063, DW_AT_decl_line(0xa0) + .dwattr $C$DW$T$1063, DW_AT_decl_column(0x03) + + +$C$DW$T$1064 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1064, DW_AT_type(*$C$DW$T$1063) + .dwattr $C$DW$T$1064, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1064, DW_AT_byte_size(0x20) +$C$DW$658 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$658, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1064 + + +$C$DW$T$417 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$417, DW_AT_name("Watchdog_Config") + .dwattr $C$DW$T$417, DW_AT_byte_size(0x0c) +$C$DW$659 .dwtag DW_TAG_member + .dwattr $C$DW$659, DW_AT_type(*$C$DW$T$416) + .dwattr $C$DW$659, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$659, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$659, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$659, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$659, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$659, DW_AT_decl_line(0x141) + .dwattr $C$DW$659, DW_AT_decl_column(0x1e) + +$C$DW$660 .dwtag DW_TAG_member + .dwattr $C$DW$660, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$660, DW_AT_name("object") + .dwattr $C$DW$660, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$660, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$660, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$660, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$660, DW_AT_decl_line(0x144) + .dwattr $C$DW$660, DW_AT_decl_column(0x1e) + +$C$DW$661 .dwtag DW_TAG_member + .dwattr $C$DW$661, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$661, DW_AT_name("hwAttrs") + .dwattr $C$DW$661, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$661, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$661, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$661, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$661, DW_AT_decl_line(0x147) + .dwattr $C$DW$661, DW_AT_decl_column(0x1e) + + .dwattr $C$DW$T$417, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$417, DW_AT_decl_line(0x13d) + .dwattr $C$DW$T$417, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$417 + +$C$DW$T$1066 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1066, DW_AT_name("Watchdog_Config") + .dwattr $C$DW$T$1066, DW_AT_type(*$C$DW$T$417) + .dwattr $C$DW$T$1066, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1066, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$1066, DW_AT_decl_line(0x148) + .dwattr $C$DW$T$1066, DW_AT_decl_column(0x03) + +$C$DW$T$1067 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1067, DW_AT_type(*$C$DW$T$1066) + + +$C$DW$T$1068 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1068, DW_AT_type(*$C$DW$T$1067) + .dwattr $C$DW$T$1068, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1068, DW_AT_byte_size(0x18) +$C$DW$662 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$662, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1068 + +$C$DW$T$418 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$418, DW_AT_type(*$C$DW$T$417) + .dwattr $C$DW$T$418, DW_AT_address_class(0x20) + +$C$DW$T$419 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$419, DW_AT_name("Watchdog_Handle") + .dwattr $C$DW$T$419, DW_AT_type(*$C$DW$T$418) + .dwattr $C$DW$T$419, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$419, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$419, DW_AT_decl_line(0xc5) + .dwattr $C$DW$T$419, DW_AT_decl_column(0x21) + + +$C$DW$T$430 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$430, DW_AT_type(*$C$DW$T$419) + .dwattr $C$DW$T$430, DW_AT_language(DW_LANG_C) +$C$DW$663 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$663, DW_AT_type(*$C$DW$T$419) + +$C$DW$664 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$664, DW_AT_type(*$C$DW$T$429) + + .dwendtag $C$DW$T$430 + +$C$DW$T$431 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$431, DW_AT_type(*$C$DW$T$430) + .dwattr $C$DW$T$431, DW_AT_address_class(0x20) + +$C$DW$T$432 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$432, DW_AT_name("Watchdog_OpenFxn") + .dwattr $C$DW$T$432, DW_AT_type(*$C$DW$T$431) + .dwattr $C$DW$T$432, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$432, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$432, DW_AT_decl_line(0x11b) + .dwattr $C$DW$T$432, DW_AT_decl_column(0x1b) + + +$C$DW$T$442 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$442, DW_AT_name("Watchdog_DebugMode") + .dwattr $C$DW$T$442, DW_AT_byte_size(0x01) +$C$DW$665 .dwtag DW_TAG_enumerator + .dwattr $C$DW$665, DW_AT_name("Watchdog_DEBUG_STALL_ON") + .dwattr $C$DW$665, DW_AT_const_value(0x00) + .dwattr $C$DW$665, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$665, DW_AT_decl_line(0xd0) + .dwattr $C$DW$665, DW_AT_decl_column(0x05) + +$C$DW$666 .dwtag DW_TAG_enumerator + .dwattr $C$DW$666, DW_AT_name("Watchdog_DEBUG_STALL_OFF") + .dwattr $C$DW$666, DW_AT_const_value(0x01) + .dwattr $C$DW$666, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$666, DW_AT_decl_line(0xd1) + .dwattr $C$DW$666, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$442, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$442, DW_AT_decl_line(0xcf) + .dwattr $C$DW$T$442, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$442 + +$C$DW$T$443 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$443, DW_AT_name("Watchdog_DebugMode") + .dwattr $C$DW$T$443, DW_AT_type(*$C$DW$T$442) + .dwattr $C$DW$T$443, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$443, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$443, DW_AT_decl_line(0xd2) + .dwattr $C$DW$T$443, DW_AT_decl_column(0x03) + + +$C$DW$T$436 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$436, DW_AT_name("Watchdog_FxnTable") + .dwattr $C$DW$T$436, DW_AT_byte_size(0x18) +$C$DW$667 .dwtag DW_TAG_member + .dwattr $C$DW$667, DW_AT_type(*$C$DW$T$422) + .dwattr $C$DW$667, DW_AT_name("watchdogClear") + .dwattr $C$DW$667, DW_AT_TI_symbol_name("watchdogClear") + .dwattr $C$DW$667, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$667, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$667, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$667, DW_AT_decl_line(0x12a) + .dwattr $C$DW$667, DW_AT_decl_column(0x20) + +$C$DW$668 .dwtag DW_TAG_member + .dwattr $C$DW$668, DW_AT_type(*$C$DW$T$423) + .dwattr $C$DW$668, DW_AT_name("watchdogClose") + .dwattr $C$DW$668, DW_AT_TI_symbol_name("watchdogClose") + .dwattr $C$DW$668, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$668, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$668, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$668, DW_AT_decl_line(0x12b) + .dwattr $C$DW$668, DW_AT_decl_column(0x20) + +$C$DW$669 .dwtag DW_TAG_member + .dwattr $C$DW$669, DW_AT_type(*$C$DW$T$426) + .dwattr $C$DW$669, DW_AT_name("watchdogControl") + .dwattr $C$DW$669, DW_AT_TI_symbol_name("watchdogControl") + .dwattr $C$DW$669, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$669, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$669, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$669, DW_AT_decl_line(0x12c) + .dwattr $C$DW$669, DW_AT_decl_column(0x20) + +$C$DW$670 .dwtag DW_TAG_member + .dwattr $C$DW$670, DW_AT_type(*$C$DW$T$427) + .dwattr $C$DW$670, DW_AT_name("watchdogInit") + .dwattr $C$DW$670, DW_AT_TI_symbol_name("watchdogInit") + .dwattr $C$DW$670, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$670, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$670, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$670, DW_AT_decl_line(0x12d) + .dwattr $C$DW$670, DW_AT_decl_column(0x20) + +$C$DW$671 .dwtag DW_TAG_member + .dwattr $C$DW$671, DW_AT_type(*$C$DW$T$432) + .dwattr $C$DW$671, DW_AT_name("watchdogOpen") + .dwattr $C$DW$671, DW_AT_TI_symbol_name("watchdogOpen") + .dwattr $C$DW$671, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$671, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$671, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$671, DW_AT_decl_line(0x12e) + .dwattr $C$DW$671, DW_AT_decl_column(0x20) + +$C$DW$672 .dwtag DW_TAG_member + .dwattr $C$DW$672, DW_AT_type(*$C$DW$T$435) + .dwattr $C$DW$672, DW_AT_name("watchdogSetReload") + .dwattr $C$DW$672, DW_AT_TI_symbol_name("watchdogSetReload") + .dwattr $C$DW$672, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$672, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$672, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$672, DW_AT_decl_line(0x12f) + .dwattr $C$DW$672, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$436, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$436, DW_AT_decl_line(0x129) + .dwattr $C$DW$T$436, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$436 + +$C$DW$T$414 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$414, DW_AT_name("Watchdog_FxnTable") + .dwattr $C$DW$T$414, DW_AT_type(*$C$DW$T$436) + .dwattr $C$DW$T$414, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$414, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$414, DW_AT_decl_line(0x130) + .dwattr $C$DW$T$414, DW_AT_decl_column(0x03) + +$C$DW$T$415 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$415, DW_AT_type(*$C$DW$T$414) + +$C$DW$T$416 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$416, DW_AT_type(*$C$DW$T$415) + .dwattr $C$DW$T$416, DW_AT_address_class(0x20) + + +$C$DW$T$444 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$444, DW_AT_name("Watchdog_Params") + .dwattr $C$DW$T$444, DW_AT_byte_size(0x0c) +$C$DW$673 .dwtag DW_TAG_member + .dwattr $C$DW$673, DW_AT_type(*$C$DW$T$439) + .dwattr $C$DW$673, DW_AT_name("callbackFxn") + .dwattr $C$DW$673, DW_AT_TI_symbol_name("callbackFxn") + .dwattr $C$DW$673, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$673, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$673, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$673, DW_AT_decl_line(0xf3) + .dwattr $C$DW$673, DW_AT_decl_column(0x19) + +$C$DW$674 .dwtag DW_TAG_member + .dwattr $C$DW$674, DW_AT_type(*$C$DW$T$441) + .dwattr $C$DW$674, DW_AT_name("resetMode") + .dwattr $C$DW$674, DW_AT_TI_symbol_name("resetMode") + .dwattr $C$DW$674, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$674, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$674, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$674, DW_AT_decl_line(0xf5) + .dwattr $C$DW$674, DW_AT_decl_column(0x19) + +$C$DW$675 .dwtag DW_TAG_member + .dwattr $C$DW$675, DW_AT_type(*$C$DW$T$443) + .dwattr $C$DW$675, DW_AT_name("debugStallMode") + .dwattr $C$DW$675, DW_AT_TI_symbol_name("debugStallMode") + .dwattr $C$DW$675, DW_AT_data_member_location[DW_OP_plus_uconst 0x5] + .dwattr $C$DW$675, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$675, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$675, DW_AT_decl_line(0xf7) + .dwattr $C$DW$675, DW_AT_decl_column(0x19) + +$C$DW$676 .dwtag DW_TAG_member + .dwattr $C$DW$676, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$676, DW_AT_name("custom") + .dwattr $C$DW$676, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$676, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$676, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$676, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$676, DW_AT_decl_line(0xf9) + .dwattr $C$DW$676, DW_AT_decl_column(0x19) + + .dwattr $C$DW$T$444, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$444, DW_AT_decl_line(0xf2) + .dwattr $C$DW$T$444, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$444 + +$C$DW$T$428 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$428, DW_AT_name("Watchdog_Params") + .dwattr $C$DW$T$428, DW_AT_type(*$C$DW$T$444) + .dwattr $C$DW$T$428, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$428, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$428, DW_AT_decl_line(0xfb) + .dwattr $C$DW$T$428, DW_AT_decl_column(0x03) + +$C$DW$T$429 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$429, DW_AT_type(*$C$DW$T$428) + .dwattr $C$DW$T$429, DW_AT_address_class(0x20) + + +$C$DW$T$440 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$440, DW_AT_name("Watchdog_ResetMode") + .dwattr $C$DW$T$440, DW_AT_byte_size(0x01) +$C$DW$677 .dwtag DW_TAG_enumerator + .dwattr $C$DW$677, DW_AT_name("Watchdog_RESET_OFF") + .dwattr $C$DW$677, DW_AT_const_value(0x00) + .dwattr $C$DW$677, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$677, DW_AT_decl_line(0xdc) + .dwattr $C$DW$677, DW_AT_decl_column(0x05) + +$C$DW$678 .dwtag DW_TAG_enumerator + .dwattr $C$DW$678, DW_AT_name("Watchdog_RESET_ON") + .dwattr $C$DW$678, DW_AT_const_value(0x01) + .dwattr $C$DW$678, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$678, DW_AT_decl_line(0xdd) + .dwattr $C$DW$678, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$440, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$440, DW_AT_decl_line(0xdb) + .dwattr $C$DW$T$440, DW_AT_decl_column(0x0e) + .dwendtag $C$DW$T$440 + +$C$DW$T$441 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$441, DW_AT_name("Watchdog_ResetMode") + .dwattr $C$DW$T$441, DW_AT_type(*$C$DW$T$440) + .dwattr $C$DW$T$441, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$441, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$441, DW_AT_decl_line(0xde) + .dwattr $C$DW$T$441, DW_AT_decl_column(0x03) + + +$C$DW$T$445 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$445, DW_AT_name("WiFiCC3100_HWAttrs") + .dwattr $C$DW$T$445, DW_AT_byte_size(0x1c) +$C$DW$679 .dwtag DW_TAG_member + .dwattr $C$DW$679, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$679, DW_AT_name("irqPort") + .dwattr $C$DW$679, DW_AT_TI_symbol_name("irqPort") + .dwattr $C$DW$679, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$679, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$679, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$679, DW_AT_decl_line(0xd7) + .dwattr $C$DW$679, DW_AT_decl_column(0x11) + +$C$DW$680 .dwtag DW_TAG_member + .dwattr $C$DW$680, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$680, DW_AT_name("irqPin") + .dwattr $C$DW$680, DW_AT_TI_symbol_name("irqPin") + .dwattr $C$DW$680, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$680, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$680, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$680, DW_AT_decl_line(0xd8) + .dwattr $C$DW$680, DW_AT_decl_column(0x11) + +$C$DW$681 .dwtag DW_TAG_member + .dwattr $C$DW$681, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$681, DW_AT_name("irqIntNum") + .dwattr $C$DW$681, DW_AT_TI_symbol_name("irqIntNum") + .dwattr $C$DW$681, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$681, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$681, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$681, DW_AT_decl_line(0xd9) + .dwattr $C$DW$681, DW_AT_decl_column(0x11) + +$C$DW$682 .dwtag DW_TAG_member + .dwattr $C$DW$682, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$682, DW_AT_name("csPort") + .dwattr $C$DW$682, DW_AT_TI_symbol_name("csPort") + .dwattr $C$DW$682, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$682, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$682, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$682, DW_AT_decl_line(0xdb) + .dwattr $C$DW$682, DW_AT_decl_column(0x11) + +$C$DW$683 .dwtag DW_TAG_member + .dwattr $C$DW$683, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$683, DW_AT_name("csPin") + .dwattr $C$DW$683, DW_AT_TI_symbol_name("csPin") + .dwattr $C$DW$683, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$683, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$683, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$683, DW_AT_decl_line(0xdc) + .dwattr $C$DW$683, DW_AT_decl_column(0x11) + +$C$DW$684 .dwtag DW_TAG_member + .dwattr $C$DW$684, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$684, DW_AT_name("enPort") + .dwattr $C$DW$684, DW_AT_TI_symbol_name("enPort") + .dwattr $C$DW$684, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$684, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$684, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$684, DW_AT_decl_line(0xde) + .dwattr $C$DW$684, DW_AT_decl_column(0x11) + +$C$DW$685 .dwtag DW_TAG_member + .dwattr $C$DW$685, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$685, DW_AT_name("enPin") + .dwattr $C$DW$685, DW_AT_TI_symbol_name("enPin") + .dwattr $C$DW$685, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$685, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$685, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$685, DW_AT_decl_line(0xdf) + .dwattr $C$DW$685, DW_AT_decl_column(0x11) + + .dwattr $C$DW$T$445, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$T$445, DW_AT_decl_line(0xd6) + .dwattr $C$DW$T$445, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$445 + +$C$DW$T$1069 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1069, DW_AT_name("WiFiCC3100_HWAttrs") + .dwattr $C$DW$T$1069, DW_AT_type(*$C$DW$T$445) + .dwattr $C$DW$T$1069, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1069, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$T$1069, DW_AT_decl_line(0xe0) + .dwattr $C$DW$T$1069, DW_AT_decl_column(0x03) + +$C$DW$T$1070 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1070, DW_AT_type(*$C$DW$T$1069) + + +$C$DW$T$1071 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1071, DW_AT_type(*$C$DW$T$1070) + .dwattr $C$DW$T$1071, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1071, DW_AT_byte_size(0x1c) +$C$DW$686 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$686, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1071 + + +$C$DW$T$448 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$448, DW_AT_name("WiFiCC3100_Object") + .dwattr $C$DW$T$448, DW_AT_byte_size(0x30) +$C$DW$687 .dwtag DW_TAG_member + .dwattr $C$DW$687, DW_AT_type(*$C$DW$T$210) + .dwattr $C$DW$687, DW_AT_name("wifiHwi") + .dwattr $C$DW$687, DW_AT_TI_symbol_name("wifiHwi") + .dwattr $C$DW$687, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$687, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$687, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$687, DW_AT_decl_line(0xe8) + .dwattr $C$DW$687, DW_AT_decl_column(0x16) + +$C$DW$688 .dwtag DW_TAG_member + .dwattr $C$DW$688, DW_AT_type(*$C$DW$T$322) + .dwattr $C$DW$688, DW_AT_name("spiHandle") + .dwattr $C$DW$688, DW_AT_TI_symbol_name("spiHandle") + .dwattr $C$DW$688, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$688, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$688, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$688, DW_AT_decl_line(0xe9) + .dwattr $C$DW$688, DW_AT_decl_column(0x16) + +$C$DW$689 .dwtag DW_TAG_member + .dwattr $C$DW$689, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$689, DW_AT_name("bitRate") + .dwattr $C$DW$689, DW_AT_TI_symbol_name("bitRate") + .dwattr $C$DW$689, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$689, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$689, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$689, DW_AT_decl_line(0xeb) + .dwattr $C$DW$689, DW_AT_decl_column(0x16) + +$C$DW$690 .dwtag DW_TAG_member + .dwattr $C$DW$690, DW_AT_type(*$C$DW$T$11) + .dwattr $C$DW$690, DW_AT_name("spiIndex") + .dwattr $C$DW$690, DW_AT_TI_symbol_name("spiIndex") + .dwattr $C$DW$690, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$690, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$690, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$690, DW_AT_decl_line(0xec) + .dwattr $C$DW$690, DW_AT_decl_column(0x16) + +$C$DW$691 .dwtag DW_TAG_member + .dwattr $C$DW$691, DW_AT_type(*$C$DW$T$447) + .dwattr $C$DW$691, DW_AT_name("wifiIntFxn") + .dwattr $C$DW$691, DW_AT_TI_symbol_name("wifiIntFxn") + .dwattr $C$DW$691, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$691, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$691, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$691, DW_AT_decl_line(0xee) + .dwattr $C$DW$691, DW_AT_decl_column(0x16) + +$C$DW$692 .dwtag DW_TAG_member + .dwattr $C$DW$692, DW_AT_type(*$C$DW$T$141) + .dwattr $C$DW$692, DW_AT_name("isOpen") + .dwattr $C$DW$692, DW_AT_TI_symbol_name("isOpen") + .dwattr $C$DW$692, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c] + .dwattr $C$DW$692, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$692, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$692, DW_AT_decl_line(0xf0) + .dwattr $C$DW$692, DW_AT_decl_column(0x16) + + .dwattr $C$DW$T$448, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$T$448, DW_AT_decl_line(0xe7) + .dwattr $C$DW$T$448, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$448 + +$C$DW$T$1073 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1073, DW_AT_name("WiFiCC3100_Object") + .dwattr $C$DW$T$1073, DW_AT_type(*$C$DW$T$448) + .dwattr $C$DW$T$1073, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1073, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h") + .dwattr $C$DW$T$1073, DW_AT_decl_line(0xf1) + .dwattr $C$DW$T$1073, DW_AT_decl_column(0x03) + + +$C$DW$T$1074 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1074, DW_AT_type(*$C$DW$T$1073) + .dwattr $C$DW$T$1074, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1074, DW_AT_byte_size(0x30) +$C$DW$693 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$693, DW_AT_upper_bound(0x00) + + .dwendtag $C$DW$T$1074 + + +$C$DW$T$452 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$452, DW_AT_name("WiFi_Config") + .dwattr $C$DW$T$452, DW_AT_byte_size(0x0c) +$C$DW$694 .dwtag DW_TAG_member + .dwattr $C$DW$694, DW_AT_type(*$C$DW$T$451) + .dwattr $C$DW$694, DW_AT_name("fxnTablePtr") + .dwattr $C$DW$694, DW_AT_TI_symbol_name("fxnTablePtr") + .dwattr $C$DW$694, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$694, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$694, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$694, DW_AT_decl_line(0x122) + .dwattr $C$DW$694, DW_AT_decl_column(0x1c) + +$C$DW$695 .dwtag DW_TAG_member + .dwattr $C$DW$695, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$695, DW_AT_name("object") + .dwattr $C$DW$695, DW_AT_TI_symbol_name("object") + .dwattr $C$DW$695, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$695, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$695, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$695, DW_AT_decl_line(0x125) + .dwattr $C$DW$695, DW_AT_decl_column(0x1c) + +$C$DW$696 .dwtag DW_TAG_member + .dwattr $C$DW$696, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$696, DW_AT_name("hwAttrs") + .dwattr $C$DW$696, DW_AT_TI_symbol_name("hwAttrs") + .dwattr $C$DW$696, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$696, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$696, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$696, DW_AT_decl_line(0x128) + .dwattr $C$DW$696, DW_AT_decl_column(0x1c) + + .dwattr $C$DW$T$452, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$452, DW_AT_decl_line(0x120) + .dwattr $C$DW$T$452, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$452 + +$C$DW$T$1076 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1076, DW_AT_name("WiFi_Config") + .dwattr $C$DW$T$1076, DW_AT_type(*$C$DW$T$452) + .dwattr $C$DW$T$1076, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1076, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$1076, DW_AT_decl_line(0x129) + .dwattr $C$DW$T$1076, DW_AT_decl_column(0x03) + +$C$DW$T$1077 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1077, DW_AT_type(*$C$DW$T$1076) + + +$C$DW$T$1078 .dwtag DW_TAG_array_type + .dwattr $C$DW$T$1078, DW_AT_type(*$C$DW$T$1077) + .dwattr $C$DW$T$1078, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1078, DW_AT_byte_size(0x18) +$C$DW$697 .dwtag DW_TAG_subrange_type + .dwattr $C$DW$697, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1078 + +$C$DW$T$453 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$453, DW_AT_type(*$C$DW$T$452) + .dwattr $C$DW$T$453, DW_AT_address_class(0x20) + +$C$DW$T$454 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$454, DW_AT_name("WiFi_Handle") + .dwattr $C$DW$T$454, DW_AT_type(*$C$DW$T$453) + .dwattr $C$DW$T$454, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$454, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$454, DW_AT_decl_line(0xd6) + .dwattr $C$DW$T$454, DW_AT_decl_column(0x1d) + + +$C$DW$T$468 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$468, DW_AT_type(*$C$DW$T$454) + .dwattr $C$DW$T$468, DW_AT_language(DW_LANG_C) +$C$DW$698 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$698, DW_AT_type(*$C$DW$T$454) + +$C$DW$699 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$699, DW_AT_type(*$C$DW$T$11) + +$C$DW$700 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$700, DW_AT_type(*$C$DW$T$465) + +$C$DW$701 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$701, DW_AT_type(*$C$DW$T$467) + + .dwendtag $C$DW$T$468 + +$C$DW$T$469 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$469, DW_AT_type(*$C$DW$T$468) + .dwattr $C$DW$T$469, DW_AT_address_class(0x20) + +$C$DW$T$470 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$470, DW_AT_name("WiFi_OpenFxn") + .dwattr $C$DW$T$470, DW_AT_type(*$C$DW$T$469) + .dwattr $C$DW$T$470, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$470, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$470, DW_AT_decl_line(0xf1) + .dwattr $C$DW$T$470, DW_AT_decl_column(0x17) + + +$C$DW$T$471 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$471, DW_AT_name("WiFi_FxnTable") + .dwattr $C$DW$T$471, DW_AT_byte_size(0x10) +$C$DW$702 .dwtag DW_TAG_member + .dwattr $C$DW$702, DW_AT_type(*$C$DW$T$457) + .dwattr $C$DW$702, DW_AT_name("closeFxn") + .dwattr $C$DW$702, DW_AT_TI_symbol_name("closeFxn") + .dwattr $C$DW$702, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$702, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$702, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$702, DW_AT_decl_line(0x109) + .dwattr $C$DW$702, DW_AT_decl_column(0x17) + +$C$DW$703 .dwtag DW_TAG_member + .dwattr $C$DW$703, DW_AT_type(*$C$DW$T$460) + .dwattr $C$DW$703, DW_AT_name("controlFxn") + .dwattr $C$DW$703, DW_AT_TI_symbol_name("controlFxn") + .dwattr $C$DW$703, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$703, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$703, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$703, DW_AT_decl_line(0x10c) + .dwattr $C$DW$703, DW_AT_decl_column(0x17) + +$C$DW$704 .dwtag DW_TAG_member + .dwattr $C$DW$704, DW_AT_type(*$C$DW$T$461) + .dwattr $C$DW$704, DW_AT_name("initFxn") + .dwattr $C$DW$704, DW_AT_TI_symbol_name("initFxn") + .dwattr $C$DW$704, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$704, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$704, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$704, DW_AT_decl_line(0x10f) + .dwattr $C$DW$704, DW_AT_decl_column(0x17) + +$C$DW$705 .dwtag DW_TAG_member + .dwattr $C$DW$705, DW_AT_type(*$C$DW$T$470) + .dwattr $C$DW$705, DW_AT_name("openFxn") + .dwattr $C$DW$705, DW_AT_TI_symbol_name("openFxn") + .dwattr $C$DW$705, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$705, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$705, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$705, DW_AT_decl_line(0x112) + .dwattr $C$DW$705, DW_AT_decl_column(0x17) + + .dwattr $C$DW$T$471, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$471, DW_AT_decl_line(0x107) + .dwattr $C$DW$T$471, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$471 + +$C$DW$T$449 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$449, DW_AT_name("WiFi_FxnTable") + .dwattr $C$DW$T$449, DW_AT_type(*$C$DW$T$471) + .dwattr $C$DW$T$449, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$449, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$449, DW_AT_decl_line(0x113) + .dwattr $C$DW$T$449, DW_AT_decl_column(0x03) + +$C$DW$T$450 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$450, DW_AT_type(*$C$DW$T$449) + +$C$DW$T$451 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$451, DW_AT_type(*$C$DW$T$450) + .dwattr $C$DW$T$451, DW_AT_address_class(0x20) + + +$C$DW$T$472 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$472, DW_AT_name("WiFi_Params") + .dwattr $C$DW$T$472, DW_AT_byte_size(0x0c) +$C$DW$706 .dwtag DW_TAG_member + .dwattr $C$DW$706, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$706, DW_AT_name("bitRate") + .dwattr $C$DW$706, DW_AT_TI_symbol_name("bitRate") + .dwattr $C$DW$706, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$706, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$706, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$706, DW_AT_decl_line(0xe1) + .dwattr $C$DW$706, DW_AT_decl_column(0x0f) + +$C$DW$707 .dwtag DW_TAG_member + .dwattr $C$DW$707, DW_AT_type(*$C$DW$T$133) + .dwattr $C$DW$707, DW_AT_name("spawnTaskPri") + .dwattr $C$DW$707, DW_AT_TI_symbol_name("spawnTaskPri") + .dwattr $C$DW$707, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$707, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$707, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$707, DW_AT_decl_line(0xe2) + .dwattr $C$DW$707, DW_AT_decl_column(0x0f) + +$C$DW$708 .dwtag DW_TAG_member + .dwattr $C$DW$708, DW_AT_type(*$C$DW$T$244) + .dwattr $C$DW$708, DW_AT_name("custom") + .dwattr $C$DW$708, DW_AT_TI_symbol_name("custom") + .dwattr $C$DW$708, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$708, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$708, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$708, DW_AT_decl_line(0xe3) + .dwattr $C$DW$708, DW_AT_decl_column(0x0f) + + .dwattr $C$DW$T$472, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$472, DW_AT_decl_line(0xe0) + .dwattr $C$DW$T$472, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$472 + +$C$DW$T$466 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$466, DW_AT_name("WiFi_Params") + .dwattr $C$DW$T$466, DW_AT_type(*$C$DW$T$472) + .dwattr $C$DW$T$466, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$466, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$466, DW_AT_decl_line(0xe5) + .dwattr $C$DW$T$466, DW_AT_decl_column(0x03) + +$C$DW$T$467 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$467, DW_AT_type(*$C$DW$T$466) + .dwattr $C$DW$T$467, DW_AT_address_class(0x20) + +$C$DW$T$2 .dwtag DW_TAG_unspecified_type + .dwattr $C$DW$T$2, DW_AT_name("void") + +$C$DW$T$3 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$3, DW_AT_type(*$C$DW$T$2) + .dwattr $C$DW$T$3, DW_AT_address_class(0x20) + +$C$DW$T$510 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$510, DW_AT_name("xdc_Ptr") + .dwattr $C$DW$T$510, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$T$510, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$510, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$510, DW_AT_decl_line(0x2e) + .dwattr $C$DW$T$510, DW_AT_decl_column(0x1a) + +$C$DW$T$1079 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1079, DW_AT_name("CT__ti_sysbios_BIOS_Module__gateObj") + .dwattr $C$DW$T$1079, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$T$1079, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1079, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + 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DW_TAG_subrange_type + .dwattr $C$DW$738, DW_AT_upper_bound(0x01) + + .dwendtag $C$DW$T$1245 + + +$C$DW$T$207 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$207, DW_AT_language(DW_LANG_C) +$C$DW$739 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$739, DW_AT_type(*$C$DW$T$204) + +$C$DW$740 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$740, DW_AT_type(*$C$DW$T$206) + +$C$DW$741 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$741, DW_AT_type(*$C$DW$T$141) + + .dwendtag $C$DW$T$207 + +$C$DW$T$208 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$208, DW_AT_type(*$C$DW$T$207) + .dwattr $C$DW$T$208, DW_AT_address_class(0x20) + +$C$DW$T$209 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$209, DW_AT_name("I2C_CallbackFxn") + .dwattr $C$DW$T$209, DW_AT_type(*$C$DW$T$208) + .dwattr $C$DW$T$209, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$209, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$209, DW_AT_decl_line(0x10c) + .dwattr $C$DW$T$209, DW_AT_decl_column(0x10) + +$C$DW$T$222 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$222, DW_AT_type(*$C$DW$T$2) + +$C$DW$T$223 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$223, DW_AT_type(*$C$DW$T$222) + .dwattr $C$DW$T$223, DW_AT_address_class(0x20) + +$C$DW$T$1216 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1216, DW_AT_name("xdc_CPtr") + .dwattr $C$DW$T$1216, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$T$1216, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1216, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$1216, DW_AT_decl_line(0x2f) + .dwattr $C$DW$T$1216, DW_AT_decl_column(0x1a) + +$C$DW$T$1217 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1217, DW_AT_name("CPtr") + .dwattr $C$DW$T$1217, DW_AT_type(*$C$DW$T$1216) + .dwattr $C$DW$T$1217, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1217, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$1217, DW_AT_decl_line(0xf3) + .dwattr $C$DW$T$1217, DW_AT_decl_column(0x19) + + +$C$DW$T$225 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$225, DW_AT_language(DW_LANG_C) +$C$DW$742 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$742, DW_AT_type(*$C$DW$T$204) + + .dwendtag $C$DW$T$225 + +$C$DW$T$226 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$226, DW_AT_type(*$C$DW$T$225) + .dwattr $C$DW$T$226, DW_AT_address_class(0x20) + +$C$DW$T$227 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$227, DW_AT_name("I2C_CloseFxn") + .dwattr $C$DW$T$227, DW_AT_type(*$C$DW$T$226) + .dwattr $C$DW$T$227, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$227, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$227, DW_AT_decl_line(0x139) + .dwattr $C$DW$T$227, DW_AT_decl_column(0x17) + +$C$DW$T$231 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$231, DW_AT_name("I2C_InitFxn") + .dwattr $C$DW$T$231, DW_AT_type(*$C$DW$T$226) + .dwattr $C$DW$T$231, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$231, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/I2C.h") + .dwattr $C$DW$T$231, DW_AT_decl_line(0x147) + .dwattr $C$DW$T$231, DW_AT_decl_column(0x17) + + +$C$DW$T$261 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$261, DW_AT_language(DW_LANG_C) +$C$DW$743 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$743, DW_AT_type(*$C$DW$T$260) + + .dwendtag $C$DW$T$261 + +$C$DW$T$262 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$262, DW_AT_type(*$C$DW$T$261) + .dwattr $C$DW$T$262, DW_AT_address_class(0x20) + +$C$DW$T$263 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$263, DW_AT_name("PWM_CloseFxn") + .dwattr $C$DW$T$263, DW_AT_type(*$C$DW$T$262) + .dwattr $C$DW$T$263, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$263, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$263, DW_AT_decl_line(0x12e) + .dwattr $C$DW$T$263, DW_AT_decl_column(0x18) + +$C$DW$T$271 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$271, DW_AT_name("PWM_InitFxn") + .dwattr $C$DW$T$271, DW_AT_type(*$C$DW$T$262) + .dwattr $C$DW$T$271, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$271, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$271, DW_AT_decl_line(0x148) + .dwattr $C$DW$T$271, DW_AT_decl_column(0x18) + + +$C$DW$T$277 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$277, DW_AT_language(DW_LANG_C) +$C$DW$744 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$744, DW_AT_type(*$C$DW$T$260) + +$C$DW$745 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$745, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$T$277 + +$C$DW$T$278 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$278, DW_AT_type(*$C$DW$T$277) + .dwattr $C$DW$T$278, DW_AT_address_class(0x20) + +$C$DW$T$279 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$279, DW_AT_name("PWM_SetDutyFxn") + .dwattr $C$DW$T$279, DW_AT_type(*$C$DW$T$278) + .dwattr $C$DW$T$279, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$279, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h") + .dwattr $C$DW$T$279, DW_AT_decl_line(0x155) + .dwattr $C$DW$T$279, DW_AT_decl_column(0x18) + + +$C$DW$T$299 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$299, DW_AT_language(DW_LANG_C) +$C$DW$746 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$746, DW_AT_type(*$C$DW$T$298) + + .dwendtag $C$DW$T$299 + +$C$DW$T$300 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$300, DW_AT_type(*$C$DW$T$299) + .dwattr $C$DW$T$300, DW_AT_address_class(0x20) + +$C$DW$T$307 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$307, DW_AT_name("SDSPI_CloseFxn") + .dwattr $C$DW$T$307, DW_AT_type(*$C$DW$T$300) + .dwattr $C$DW$T$307, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$307, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$307, DW_AT_decl_line(0xe2) + .dwattr $C$DW$T$307, DW_AT_decl_column(0x17) + +$C$DW$T$301 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$301, DW_AT_name("SDSPI_InitFxn") + .dwattr $C$DW$T$301, DW_AT_type(*$C$DW$T$300) + .dwattr $C$DW$T$301, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$301, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h") + .dwattr $C$DW$T$301, DW_AT_decl_line(0xd4) + .dwattr $C$DW$T$301, DW_AT_decl_column(0x17) + + +$C$DW$T$316 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$316, DW_AT_language(DW_LANG_C) +$C$DW$747 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$747, DW_AT_type(*$C$DW$T$315) + + .dwendtag $C$DW$T$316 + +$C$DW$T$317 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$317, DW_AT_type(*$C$DW$T$316) + .dwattr $C$DW$T$317, DW_AT_address_class(0x20) + + +$C$DW$T$325 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$325, DW_AT_language(DW_LANG_C) +$C$DW$748 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$748, DW_AT_type(*$C$DW$T$322) + +$C$DW$749 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$749, DW_AT_type(*$C$DW$T$324) + + .dwendtag $C$DW$T$325 + +$C$DW$T$326 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$326, DW_AT_type(*$C$DW$T$325) + .dwattr $C$DW$T$326, DW_AT_address_class(0x20) + +$C$DW$T$327 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$327, DW_AT_name("SPI_CallbackFxn") + .dwattr $C$DW$T$327, DW_AT_type(*$C$DW$T$326) + .dwattr $C$DW$T$327, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$327, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$327, DW_AT_decl_line(0x11a) + .dwattr $C$DW$T$327, DW_AT_decl_column(0x17) + + +$C$DW$T$335 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$335, DW_AT_language(DW_LANG_C) +$C$DW$750 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$750, DW_AT_type(*$C$DW$T$322) + + .dwendtag $C$DW$T$335 + +$C$DW$T$336 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$336, DW_AT_type(*$C$DW$T$335) + .dwattr $C$DW$T$336, DW_AT_address_class(0x20) + +$C$DW$T$337 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$337, DW_AT_name("SPI_CloseFxn") + .dwattr $C$DW$T$337, DW_AT_type(*$C$DW$T$336) + .dwattr $C$DW$T$337, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$337, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$337, DW_AT_decl_line(0x163) + .dwattr $C$DW$T$337, DW_AT_decl_column(0x17) + +$C$DW$T$341 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$341, DW_AT_name("SPI_InitFxn") + .dwattr $C$DW$T$341, DW_AT_type(*$C$DW$T$336) + .dwattr $C$DW$T$341, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$341, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$341, DW_AT_decl_line(0x171) + .dwattr $C$DW$T$341, DW_AT_decl_column(0x17) + +$C$DW$T$351 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$351, DW_AT_name("SPI_ServiceISRFxn") + .dwattr $C$DW$T$351, DW_AT_type(*$C$DW$T$336) + .dwattr $C$DW$T$351, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$351, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$351, DW_AT_decl_line(0x17e) + .dwattr $C$DW$T$351, DW_AT_decl_column(0x17) + +$C$DW$T$350 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$350, DW_AT_name("SPI_TransferCancelFxn") + .dwattr $C$DW$T$350, DW_AT_type(*$C$DW$T$336) + .dwattr $C$DW$T$350, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$350, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$350, DW_AT_decl_line(0x18b) + .dwattr $C$DW$T$350, DW_AT_decl_column(0x17) + + +$C$DW$T$378 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$378, DW_AT_language(DW_LANG_C) +$C$DW$751 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$751, DW_AT_type(*$C$DW$T$362) + +$C$DW$752 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$752, DW_AT_type(*$C$DW$T$3) + +$C$DW$753 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$753, DW_AT_type(*$C$DW$T$217) + + .dwendtag $C$DW$T$378 + +$C$DW$T$379 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$379, DW_AT_type(*$C$DW$T$378) + .dwattr $C$DW$T$379, DW_AT_address_class(0x20) + +$C$DW$T$380 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$380, DW_AT_name("UART_Callback") + .dwattr $C$DW$T$380, DW_AT_type(*$C$DW$T$379) + .dwattr $C$DW$T$380, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$380, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$380, DW_AT_decl_line(0x12d) + .dwattr $C$DW$T$380, DW_AT_decl_column(0x17) + + +$C$DW$T$388 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$388, DW_AT_language(DW_LANG_C) +$C$DW$754 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$754, DW_AT_type(*$C$DW$T$362) + + .dwendtag $C$DW$T$388 + +$C$DW$T$389 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$389, DW_AT_type(*$C$DW$T$388) + .dwattr $C$DW$T$389, DW_AT_address_class(0x20) + +$C$DW$T$390 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$390, DW_AT_name("UART_CloseFxn") + .dwattr $C$DW$T$390, DW_AT_type(*$C$DW$T$389) + .dwattr $C$DW$T$390, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$390, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$390, DW_AT_decl_line(0x1bd) + .dwattr $C$DW$T$390, DW_AT_decl_column(0x17) + +$C$DW$T$394 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$394, DW_AT_name("UART_InitFxn") + .dwattr $C$DW$T$394, DW_AT_type(*$C$DW$T$389) + .dwattr $C$DW$T$394, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$394, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$394, DW_AT_decl_line(0x1cb) + .dwattr $C$DW$T$394, DW_AT_decl_column(0x17) + +$C$DW$T$404 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$404, DW_AT_name("UART_ReadCancelFxn") + .dwattr $C$DW$T$404, DW_AT_type(*$C$DW$T$389) + .dwattr $C$DW$T$404, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$404, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$404, DW_AT_decl_line(0x1e5) + .dwattr $C$DW$T$404, DW_AT_decl_column(0x13) + +$C$DW$T$409 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$409, DW_AT_name("UART_WriteCancelFxn") + .dwattr $C$DW$T$409, DW_AT_type(*$C$DW$T$389) + .dwattr $C$DW$T$409, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$409, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$409, DW_AT_decl_line(0x1fb) + .dwattr $C$DW$T$409, DW_AT_decl_column(0x13) + + +$C$DW$T$420 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$420, DW_AT_language(DW_LANG_C) +$C$DW$755 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$755, DW_AT_type(*$C$DW$T$419) + + .dwendtag $C$DW$T$420 + +$C$DW$T$421 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$421, DW_AT_type(*$C$DW$T$420) + .dwattr $C$DW$T$421, DW_AT_address_class(0x20) + +$C$DW$T$422 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$422, DW_AT_name("Watchdog_ClearFxn") + .dwattr $C$DW$T$422, DW_AT_type(*$C$DW$T$421) + .dwattr $C$DW$T$422, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$422, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$422, DW_AT_decl_line(0x101) + .dwattr $C$DW$T$422, DW_AT_decl_column(0x10) + +$C$DW$T$423 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$423, DW_AT_name("Watchdog_CloseFxn") + .dwattr $C$DW$T$423, DW_AT_type(*$C$DW$T$421) + .dwattr $C$DW$T$423, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$423, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$423, DW_AT_decl_line(0x107) + .dwattr $C$DW$T$423, DW_AT_decl_column(0x10) + +$C$DW$T$427 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$427, DW_AT_name("Watchdog_InitFxn") + .dwattr $C$DW$T$427, DW_AT_type(*$C$DW$T$421) + .dwattr $C$DW$T$427, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$427, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$427, DW_AT_decl_line(0x115) + .dwattr $C$DW$T$427, DW_AT_decl_column(0x10) + + +$C$DW$T$433 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$433, DW_AT_language(DW_LANG_C) +$C$DW$756 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$756, DW_AT_type(*$C$DW$T$419) + +$C$DW$757 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$757, DW_AT_type(*$C$DW$T$133) + + .dwendtag $C$DW$T$433 + +$C$DW$T$434 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$434, DW_AT_type(*$C$DW$T$433) + .dwattr $C$DW$T$434, DW_AT_address_class(0x20) + +$C$DW$T$435 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$435, DW_AT_name("Watchdog_SetReloadFxn") + .dwattr $C$DW$T$435, DW_AT_type(*$C$DW$T$434) + .dwattr $C$DW$T$435, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$435, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$435, DW_AT_decl_line(0x122) + .dwattr $C$DW$T$435, DW_AT_decl_column(0x10) + + +$C$DW$T$437 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$437, DW_AT_language(DW_LANG_C) +$C$DW$758 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$758, DW_AT_type(*$C$DW$T$244) + + .dwendtag $C$DW$T$437 + +$C$DW$T$438 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$438, DW_AT_type(*$C$DW$T$437) + .dwattr $C$DW$T$438, DW_AT_address_class(0x20) + +$C$DW$T$439 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$439, DW_AT_name("Watchdog_Callback") + .dwattr $C$DW$T$439, DW_AT_type(*$C$DW$T$438) + .dwattr $C$DW$T$439, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$439, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$439, DW_AT_decl_line(0xe8) + .dwattr $C$DW$T$439, DW_AT_decl_column(0x10) + + +$C$DW$T$446 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$446, DW_AT_language(DW_LANG_C) + .dwendtag $C$DW$T$446 + +$C$DW$T$447 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$447, DW_AT_type(*$C$DW$T$446) + .dwattr $C$DW$T$447, DW_AT_address_class(0x20) + + +$C$DW$T$455 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$455, DW_AT_language(DW_LANG_C) +$C$DW$759 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$759, DW_AT_type(*$C$DW$T$454) + + .dwendtag $C$DW$T$455 + +$C$DW$T$456 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$456, DW_AT_type(*$C$DW$T$455) + .dwattr $C$DW$T$456, DW_AT_address_class(0x20) + +$C$DW$T$457 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$457, DW_AT_name("WiFi_CloseFxn") + .dwattr $C$DW$T$457, DW_AT_type(*$C$DW$T$456) + .dwattr $C$DW$T$457, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$457, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$457, DW_AT_decl_line(0xf9) + .dwattr $C$DW$T$457, DW_AT_decl_column(0x10) + +$C$DW$T$461 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$461, DW_AT_name("WiFi_InitFxn") + .dwattr $C$DW$T$461, DW_AT_type(*$C$DW$T$456) + .dwattr $C$DW$T$461, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$461, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$461, DW_AT_decl_line(0xeb) + .dwattr $C$DW$T$461, DW_AT_decl_column(0x10) + + +$C$DW$T$463 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$463, DW_AT_language(DW_LANG_C) +$C$DW$760 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$760, DW_AT_type(*$C$DW$T$12) + +$C$DW$761 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$761, DW_AT_type(*$C$DW$T$462) + +$C$DW$762 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$762, DW_AT_type(*$C$DW$T$6) + + .dwendtag $C$DW$T$463 + +$C$DW$T$464 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$464, DW_AT_type(*$C$DW$T$463) + .dwattr $C$DW$T$464, DW_AT_address_class(0x20) + +$C$DW$T$465 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$465, DW_AT_name("WiFi_evntCallback") + .dwattr $C$DW$T$465, DW_AT_type(*$C$DW$T$464) + .dwattr $C$DW$T$465, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$465, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$465, DW_AT_decl_line(0xd1) + .dwattr $C$DW$T$465, DW_AT_decl_column(0x10) + + +$C$DW$T$487 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$487, DW_AT_language(DW_LANG_C) +$C$DW$763 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$763, DW_AT_type(*$C$DW$T$484) + +$C$DW$764 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$764, DW_AT_type(*$C$DW$T$190) + + .dwendtag $C$DW$T$487 + +$C$DW$T$488 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$488, DW_AT_type(*$C$DW$T$487) + .dwattr $C$DW$T$488, DW_AT_address_class(0x20) + + +$C$DW$T$502 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$502, DW_AT_language(DW_LANG_C) +$C$DW$765 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$765, DW_AT_type(*$C$DW$T$501) + + .dwendtag $C$DW$T$502 + +$C$DW$T$503 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$503, DW_AT_type(*$C$DW$T$502) + .dwattr $C$DW$T$503, DW_AT_address_class(0x20) + +$C$DW$T$1212 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1212, DW_AT_name("CT__ti_sysbios_knl_Clock_doTickFunc") + .dwattr $C$DW$T$1212, DW_AT_type(*$C$DW$T$503) + .dwattr $C$DW$T$1212, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1212, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h") + .dwattr $C$DW$T$1212, DW_AT_decl_line(0xf8) + .dwattr $C$DW$T$1212, DW_AT_decl_column(0x14) + +$C$DW$T$504 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$504, DW_AT_name("ti_sysbios_interfaces_IHwi_FuncPtr") + .dwattr $C$DW$T$504, DW_AT_type(*$C$DW$T$503) + .dwattr $C$DW$T$504, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$504, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/IHwi.h") + .dwattr $C$DW$T$504, DW_AT_decl_line(0x42) + .dwattr $C$DW$T$504, DW_AT_decl_column(0x14) + + +$C$DW$T$538 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$538, DW_AT_type(*$C$DW$T$504) + .dwattr $C$DW$T$538, DW_AT_language(DW_LANG_C) +$C$DW$766 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$766, DW_AT_type(*$C$DW$T$536) + +$C$DW$767 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$767, DW_AT_type(*$C$DW$T$537) + + .dwendtag $C$DW$T$538 + +$C$DW$T$539 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$539, DW_AT_type(*$C$DW$T$538) + .dwattr $C$DW$T$539, DW_AT_address_class(0x20) + + +$C$DW$T$623 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$623, DW_AT_type(*$C$DW$T$504) + .dwattr $C$DW$T$623, DW_AT_language(DW_LANG_C) +$C$DW$768 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$768, DW_AT_type(*$C$DW$T$3) + +$C$DW$769 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$769, DW_AT_type(*$C$DW$T$537) + + .dwendtag $C$DW$T$623 + +$C$DW$T$624 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$624, DW_AT_type(*$C$DW$T$623) + .dwattr $C$DW$T$624, DW_AT_address_class(0x20) + +$C$DW$T$1213 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1213, DW_AT_name("ti_sysbios_interfaces_IHwi_getFunc_FxnT") + .dwattr $C$DW$T$1213, DW_AT_type(*$C$DW$T$624) + .dwattr $C$DW$T$1213, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1213, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/IHwi.h") + .dwattr $C$DW$T$1213, DW_AT_decl_line(0x192) + .dwattr $C$DW$T$1213, DW_AT_decl_column(0x2e) + +$C$DW$T$612 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$612, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_FuncPtr") + .dwattr $C$DW$T$612, DW_AT_type(*$C$DW$T$504) + .dwattr $C$DW$T$612, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$612, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$612, DW_AT_decl_line(0x4b) + .dwattr $C$DW$T$612, DW_AT_decl_column(0x2c) + +$C$DW$T$663 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$663, DW_AT_name("ti_sysbios_interfaces_ITimer_FuncPtr") + .dwattr $C$DW$T$663, DW_AT_type(*$C$DW$T$503) + .dwattr $C$DW$T$663, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$663, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h") + .dwattr $C$DW$T$663, DW_AT_decl_line(0x42) + .dwattr $C$DW$T$663, DW_AT_decl_column(0x14) + + +$C$DW$T$681 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$681, DW_AT_type(*$C$DW$T$663) + .dwattr $C$DW$T$681, DW_AT_language(DW_LANG_C) +$C$DW$770 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$770, DW_AT_type(*$C$DW$T$3) + +$C$DW$771 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$771, DW_AT_type(*$C$DW$T$537) + + .dwendtag $C$DW$T$681 + +$C$DW$T$682 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$682, DW_AT_type(*$C$DW$T$681) + .dwattr $C$DW$T$682, DW_AT_address_class(0x20) + +$C$DW$T$1214 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1214, DW_AT_name("ti_sysbios_interfaces_ITimer_getFunc_FxnT") + .dwattr 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DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/ISystemSupport.h") + .dwattr $C$DW$T$1250, DW_AT_decl_line(0x8e) + .dwattr $C$DW$T$1250, DW_AT_decl_column(0x14) + +$C$DW$T$1251 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1251, DW_AT_name("xdc_runtime_System_AtexitHandler") + .dwattr $C$DW$T$1251, DW_AT_type(*$C$DW$T$635) + .dwattr $C$DW$T$1251, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1251, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$T$1251, DW_AT_decl_line(0x46) + .dwattr $C$DW$T$1251, DW_AT_decl_column(0x14) + +$C$DW$T$1252 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1252, DW_AT_name("__T1_xdc_runtime_System_Module_State__atexitHandlers") + .dwattr $C$DW$T$1252, DW_AT_type(*$C$DW$T$1251) + .dwattr $C$DW$T$1252, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1252, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$T$1252, DW_AT_decl_line(0x67) + .dwattr $C$DW$T$1252, DW_AT_decl_column(0x2a) + +$C$DW$T$1253 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1253, DW_AT_type(*$C$DW$T$1251) + .dwattr $C$DW$T$1253, DW_AT_address_class(0x20) + +$C$DW$T$1254 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1254, DW_AT_name("__ARRAY1_xdc_runtime_System_Module_State__atexitHandlers") + .dwattr $C$DW$T$1254, DW_AT_type(*$C$DW$T$1253) + .dwattr $C$DW$T$1254, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1254, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$T$1254, DW_AT_decl_line(0x68) + .dwattr $C$DW$T$1254, DW_AT_decl_column(0x2b) + +$C$DW$T$1255 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1255, DW_AT_name("__TA_xdc_runtime_System_Module_State__atexitHandlers") + .dwattr $C$DW$T$1255, DW_AT_type(*$C$DW$T$1254) + .dwattr $C$DW$T$1255, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1255, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$T$1255, DW_AT_decl_line(0x69) + .dwattr $C$DW$T$1255, DW_AT_decl_column(0x42) + +$C$DW$T$1256 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1256, DW_AT_name("xdc_runtime_System_ExitFxn") + .dwattr $C$DW$T$1256, DW_AT_type(*$C$DW$T$635) + .dwattr $C$DW$T$1256, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1256, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$T$1256, DW_AT_decl_line(0x4f) + .dwattr $C$DW$T$1256, DW_AT_decl_column(0x14) + +$C$DW$T$1257 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1257, DW_AT_name("CT__xdc_runtime_System_exitFxn") + .dwattr $C$DW$T$1257, DW_AT_type(*$C$DW$T$1256) + .dwattr $C$DW$T$1257, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1257, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h") + .dwattr $C$DW$T$1257, DW_AT_decl_line(0xcd) + .dwattr $C$DW$T$1257, DW_AT_decl_column(0x24) + + +$C$DW$T$640 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$640, DW_AT_language(DW_LANG_C) +$C$DW$790 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$790, DW_AT_type(*$C$DW$T$637) + +$C$DW$791 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$791, DW_AT_type(*$C$DW$T$639) + + .dwendtag $C$DW$T$640 + +$C$DW$T$641 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$641, DW_AT_type(*$C$DW$T$640) + .dwattr $C$DW$T$641, DW_AT_address_class(0x20) + + +$C$DW$T$642 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$642, DW_AT_language(DW_LANG_C) +$C$DW$792 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$792, DW_AT_type(*$C$DW$T$637) + + .dwendtag $C$DW$T$642 + +$C$DW$T$643 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$643, DW_AT_type(*$C$DW$T$642) + .dwattr $C$DW$T$643, DW_AT_address_class(0x20) + + +$C$DW$T$654 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$654, DW_AT_language(DW_LANG_C) +$C$DW$793 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$793, DW_AT_type(*$C$DW$T$618) + +$C$DW$794 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$794, DW_AT_type(*$C$DW$T$618) + + .dwendtag $C$DW$T$654 + +$C$DW$T$655 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$655, DW_AT_type(*$C$DW$T$654) + .dwattr $C$DW$T$655, DW_AT_address_class(0x20) + +$C$DW$T$1414 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1414, DW_AT_name("ti_sysbios_interfaces_ITaskSupport_swap_FxnT") + .dwattr $C$DW$T$1414, DW_AT_type(*$C$DW$T$655) + .dwattr $C$DW$T$1414, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1414, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h") + .dwattr $C$DW$T$1414, DW_AT_decl_line(0x99) + .dwattr $C$DW$T$1414, DW_AT_decl_column(0x14) + + +$C$DW$T$671 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$671, DW_AT_language(DW_LANG_C) +$C$DW$795 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$795, DW_AT_type(*$C$DW$T$3) + +$C$DW$796 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$796, DW_AT_type(*$C$DW$T$552) + + .dwendtag $C$DW$T$671 + +$C$DW$T$672 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$672, DW_AT_type(*$C$DW$T$671) + .dwattr $C$DW$T$672, DW_AT_address_class(0x20) + +$C$DW$T$1415 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1415, DW_AT_name("ti_sysbios_interfaces_ITimer_setNextTick_FxnT") + .dwattr $C$DW$T$1415, DW_AT_type(*$C$DW$T$672) + .dwattr $C$DW$T$1415, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1415, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h") + .dwattr $C$DW$T$1415, DW_AT_decl_line(0x157) + .dwattr $C$DW$T$1415, DW_AT_decl_column(0x14) + +$C$DW$T$1416 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1416, DW_AT_name("ti_sysbios_interfaces_ITimer_setPeriod_FxnT") + .dwattr $C$DW$T$1416, DW_AT_type(*$C$DW$T$672) + .dwattr $C$DW$T$1416, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1416, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h") + .dwattr $C$DW$T$1416, DW_AT_decl_line(0x16c) + .dwattr $C$DW$T$1416, DW_AT_decl_column(0x14) + +$C$DW$T$1417 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1417, DW_AT_name("ti_sysbios_interfaces_ITimer_trigger_FxnT") + .dwattr $C$DW$T$1417, DW_AT_type(*$C$DW$T$672) + .dwattr $C$DW$T$1417, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1417, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h") + .dwattr $C$DW$T$1417, DW_AT_decl_line(0x19d) + .dwattr $C$DW$T$1417, DW_AT_decl_column(0x14) + + +$C$DW$T$673 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$673, DW_AT_language(DW_LANG_C) +$C$DW$797 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$797, DW_AT_type(*$C$DW$T$3) + + .dwendtag $C$DW$T$673 + +$C$DW$T$674 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$674, DW_AT_type(*$C$DW$T$673) + .dwattr $C$DW$T$674, DW_AT_address_class(0x20) + +$C$DW$T$1239 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1239, DW_AT_name("ti_sysbios_interfaces_ITimer_start_FxnT") + .dwattr $C$DW$T$1239, DW_AT_type(*$C$DW$T$674) + .dwattr $C$DW$T$1239, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1239, 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DW_AT_type(*$C$DW$T$683) + .dwattr $C$DW$T$684, DW_AT_address_class(0x20) + +$C$DW$T$1419 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1419, DW_AT_name("ti_sysbios_interfaces_ITimer_setFunc_FxnT") + .dwattr $C$DW$T$1419, DW_AT_type(*$C$DW$T$684) + .dwattr $C$DW$T$1419, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1419, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h") + .dwattr $C$DW$T$1419, DW_AT_decl_line(0x196) + .dwattr $C$DW$T$1419, DW_AT_decl_column(0x14) + + +$C$DW$T$711 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$711, DW_AT_language(DW_LANG_C) +$C$DW$803 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$803, DW_AT_type(*$C$DW$T$708) + +$C$DW$804 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$804, DW_AT_type(*$C$DW$T$552) + + .dwendtag $C$DW$T$711 + +$C$DW$T$712 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$712, DW_AT_type(*$C$DW$T$711) + .dwattr $C$DW$T$712, DW_AT_address_class(0x20) + + +$C$DW$T$713 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$713, DW_AT_language(DW_LANG_C) +$C$DW$805 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$805, DW_AT_type(*$C$DW$T$708) + + .dwendtag $C$DW$T$713 + +$C$DW$T$714 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$714, DW_AT_type(*$C$DW$T$713) + .dwattr $C$DW$T$714, DW_AT_address_class(0x20) + + +$C$DW$T$717 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$717, DW_AT_language(DW_LANG_C) +$C$DW$806 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$806, DW_AT_type(*$C$DW$T$708) + +$C$DW$807 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$807, DW_AT_type(*$C$DW$T$678) + + .dwendtag $C$DW$T$717 + +$C$DW$T$718 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$718, DW_AT_type(*$C$DW$T$717) + .dwattr $C$DW$T$718, DW_AT_address_class(0x20) + + +$C$DW$T$721 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$721, DW_AT_language(DW_LANG_C) +$C$DW$808 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$808, DW_AT_type(*$C$DW$T$708) + +$C$DW$809 .dwtag DW_TAG_formal_parameter + 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DW_TAG_typedef + .dwattr $C$DW$T$340, DW_AT_name("SPI_ControlFxn") + .dwattr $C$DW$T$340, DW_AT_type(*$C$DW$T$339) + .dwattr $C$DW$T$340, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$340, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h") + .dwattr $C$DW$T$340, DW_AT_decl_line(0x169) + .dwattr $C$DW$T$340, DW_AT_decl_column(0x17) + + +$C$DW$T$365 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$365, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$365, DW_AT_language(DW_LANG_C) +$C$DW$931 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$931, DW_AT_type(*$C$DW$T$362) + + .dwendtag $C$DW$T$365 + +$C$DW$T$366 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$366, DW_AT_type(*$C$DW$T$365) + .dwattr $C$DW$T$366, DW_AT_address_class(0x20) + + +$C$DW$T$391 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$391, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$391, DW_AT_language(DW_LANG_C) +$C$DW$932 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$932, DW_AT_type(*$C$DW$T$362) + +$C$DW$933 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$933, DW_AT_type(*$C$DW$T$11) + +$C$DW$934 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$934, DW_AT_type(*$C$DW$T$3) + + .dwendtag $C$DW$T$391 + +$C$DW$T$392 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$392, DW_AT_type(*$C$DW$T$391) + .dwattr $C$DW$T$392, DW_AT_address_class(0x20) + +$C$DW$T$393 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$393, DW_AT_name("UART_ControlFxn") + .dwattr $C$DW$T$393, DW_AT_type(*$C$DW$T$392) + .dwattr $C$DW$T$393, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$393, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$393, DW_AT_decl_line(0x1c3) + .dwattr $C$DW$T$393, DW_AT_decl_column(0x17) + + +$C$DW$T$400 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$400, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$400, DW_AT_language(DW_LANG_C) +$C$DW$935 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$935, DW_AT_type(*$C$DW$T$362) + +$C$DW$936 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$936, DW_AT_type(*$C$DW$T$3) + +$C$DW$937 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$937, DW_AT_type(*$C$DW$T$217) + + .dwendtag $C$DW$T$400 + +$C$DW$T$401 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$401, DW_AT_type(*$C$DW$T$400) + .dwattr $C$DW$T$401, DW_AT_address_class(0x20) + +$C$DW$T$402 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$402, DW_AT_name("UART_ReadFxn") + .dwattr $C$DW$T$402, DW_AT_type(*$C$DW$T$401) + .dwattr $C$DW$T$402, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$402, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$402, DW_AT_decl_line(0x1d7) + .dwattr $C$DW$T$402, DW_AT_decl_column(0x13) + +$C$DW$T$403 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$403, DW_AT_name("UART_ReadPollingFxn") + .dwattr $C$DW$T$403, DW_AT_type(*$C$DW$T$401) + .dwattr $C$DW$T$403, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$403, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$403, DW_AT_decl_line(0x1de) + .dwattr $C$DW$T$403, DW_AT_decl_column(0x13) + + +$C$DW$T$405 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$405, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$405, DW_AT_language(DW_LANG_C) +$C$DW$938 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$938, DW_AT_type(*$C$DW$T$362) + +$C$DW$939 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$939, DW_AT_type(*$C$DW$T$223) + +$C$DW$940 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$940, DW_AT_type(*$C$DW$T$217) + + .dwendtag $C$DW$T$405 + +$C$DW$T$406 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$406, DW_AT_type(*$C$DW$T$405) + .dwattr $C$DW$T$406, DW_AT_address_class(0x20) + +$C$DW$T$407 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$407, DW_AT_name("UART_WriteFxn") + .dwattr $C$DW$T$407, DW_AT_type(*$C$DW$T$406) + .dwattr $C$DW$T$407, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$407, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$407, DW_AT_decl_line(0x1eb) + .dwattr $C$DW$T$407, DW_AT_decl_column(0x13) + +$C$DW$T$408 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$408, DW_AT_name("UART_WritePollingFxn") + .dwattr $C$DW$T$408, DW_AT_type(*$C$DW$T$406) + .dwattr $C$DW$T$408, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$408, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h") + .dwattr $C$DW$T$408, DW_AT_decl_line(0x1f3) + .dwattr $C$DW$T$408, DW_AT_decl_column(0x13) + + +$C$DW$T$424 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$424, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$424, DW_AT_language(DW_LANG_C) +$C$DW$941 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$941, DW_AT_type(*$C$DW$T$419) + +$C$DW$942 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$942, DW_AT_type(*$C$DW$T$11) + +$C$DW$943 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$943, DW_AT_type(*$C$DW$T$3) + + .dwendtag $C$DW$T$424 + +$C$DW$T$425 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$425, DW_AT_type(*$C$DW$T$424) + .dwattr $C$DW$T$425, DW_AT_address_class(0x20) + +$C$DW$T$426 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$426, DW_AT_name("Watchdog_ControlFxn") + .dwattr $C$DW$T$426, DW_AT_type(*$C$DW$T$425) + .dwattr $C$DW$T$426, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$426, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h") + .dwattr $C$DW$T$426, DW_AT_decl_line(0x10d) + .dwattr $C$DW$T$426, DW_AT_decl_column(0x10) + + +$C$DW$T$458 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$458, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$458, DW_AT_language(DW_LANG_C) +$C$DW$944 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$944, DW_AT_type(*$C$DW$T$454) + +$C$DW$945 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$945, DW_AT_type(*$C$DW$T$11) + +$C$DW$946 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$946, DW_AT_type(*$C$DW$T$3) + + .dwendtag $C$DW$T$458 + +$C$DW$T$459 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$459, DW_AT_type(*$C$DW$T$458) + .dwattr $C$DW$T$459, DW_AT_address_class(0x20) + +$C$DW$T$460 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$460, DW_AT_name("WiFi_ControlFxn") + .dwattr $C$DW$T$460, DW_AT_type(*$C$DW$T$459) + .dwattr $C$DW$T$460, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$460, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h") + .dwattr $C$DW$T$460, DW_AT_decl_line(0xff) + .dwattr $C$DW$T$460, DW_AT_decl_column(0x10) + + +$C$DW$T$1400 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$1400, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$1400, DW_AT_language(DW_LANG_C) + .dwendtag $C$DW$T$1400 + +$C$DW$T$1401 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1401, DW_AT_type(*$C$DW$T$1400) + .dwattr $C$DW$T$1401, DW_AT_address_class(0x20) + +$C$DW$T$1402 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1402, DW_AT_name("xdc_Fxn") + .dwattr $C$DW$T$1402, DW_AT_type(*$C$DW$T$1401) + .dwattr $C$DW$T$1402, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1402, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$1402, DW_AT_decl_line(0x46) + .dwattr $C$DW$T$1402, DW_AT_decl_column(0x1d) + +$C$DW$T$1623 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1623, DW_AT_name("Fxn") + .dwattr $C$DW$T$1623, DW_AT_type(*$C$DW$T$1402) + .dwattr $C$DW$T$1623, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1623, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$1623, DW_AT_decl_line(0xf1) + .dwattr $C$DW$T$1623, DW_AT_decl_column(0x19) + +$C$DW$T$1624 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1624, DW_AT_name("__cpulevel_t") + .dwattr $C$DW$T$1624, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$1624, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1624, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1624, DW_AT_decl_line(0x4f) + .dwattr $C$DW$T$1624, DW_AT_decl_column(0x0e) + +$C$DW$T$1625 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1625, DW_AT_name("__cpusetid_t") + .dwattr $C$DW$T$1625, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$1625, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1625, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1625, DW_AT_decl_line(0x50) + .dwattr $C$DW$T$1625, DW_AT_decl_column(0x0e) + +$C$DW$T$1626 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1626, DW_AT_name("__cpuwhich_t") + .dwattr $C$DW$T$1626, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$1626, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1626, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1626, DW_AT_decl_line(0x4e) + .dwattr $C$DW$T$1626, DW_AT_decl_column(0x0e) + +$C$DW$T$1627 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1627, DW_AT_name("__ct_rune_t") + .dwattr $C$DW$T$1627, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$1627, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1627, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1627, DW_AT_decl_line(0x68) + .dwattr $C$DW$T$1627, DW_AT_decl_column(0x0e) + +$C$DW$T$1628 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1628, DW_AT_name("__rune_t") + .dwattr $C$DW$T$1628, DW_AT_type(*$C$DW$T$1627) + .dwattr $C$DW$T$1628, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1628, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1628, DW_AT_decl_line(0x6b) + .dwattr $C$DW$T$1628, DW_AT_decl_column(0x15) + +$C$DW$T$1629 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1629, DW_AT_name("__wint_t") + .dwattr $C$DW$T$1629, DW_AT_type(*$C$DW$T$1627) + .dwattr $C$DW$T$1629, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1629, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1629, DW_AT_decl_line(0x6c) + .dwattr $C$DW$T$1629, DW_AT_decl_column(0x15) + +$C$DW$T$187 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$187, DW_AT_name("__int32_t") + .dwattr $C$DW$T$187, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$T$187, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$187, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$187, DW_AT_decl_line(0x3d) + .dwattr $C$DW$T$187, DW_AT_decl_column(0x0f) + +$C$DW$T$1630 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1630, DW_AT_name("__blksize_t") + .dwattr $C$DW$T$1630, DW_AT_type(*$C$DW$T$187) + .dwattr $C$DW$T$1630, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1630, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1630, DW_AT_decl_line(0x2e) + .dwattr $C$DW$T$1630, DW_AT_decl_column(0x13) + +$C$DW$T$1631 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1631, DW_AT_name("__clockid_t") + .dwattr $C$DW$T$1631, DW_AT_type(*$C$DW$T$187) + .dwattr $C$DW$T$1631, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1631, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$1631, DW_AT_decl_line(0x30) + .dwattr $C$DW$T$1631, DW_AT_decl_column(0x13) + +$C$DW$T$1632 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1632, DW_AT_name("__critical_t") + .dwattr $C$DW$T$1632, DW_AT_type(*$C$DW$T$187) + .dwattr $C$DW$T$1632, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1632, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$1632, DW_AT_decl_line(0x4e) + .dwattr $C$DW$T$1632, DW_AT_decl_column(0x13) + +$C$DW$T$1633 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1633, DW_AT_name("__int_fast16_t") + .dwattr $C$DW$T$1633, DW_AT_type(*$C$DW$T$187) + .dwattr $C$DW$T$1633, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1633, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$1633, DW_AT_decl_line(0x55) + .dwattr $C$DW$T$1633, DW_AT_decl_column(0x13) + +$C$DW$T$1634 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1634, DW_AT_name("int_fast16_t") + .dwattr $C$DW$T$1634, DW_AT_type(*$C$DW$T$1633) + .dwattr $C$DW$T$1634, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1634, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h") + .dwattr $C$DW$T$1634, DW_AT_decl_line(0x33) + .dwattr $C$DW$T$1634, DW_AT_decl_column(0x19) + +$C$DW$T$1635 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1635, DW_AT_name("__int_fast32_t") + .dwattr $C$DW$T$1635, DW_AT_type(*$C$DW$T$187) + .dwattr $C$DW$T$1635, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1635, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$1635, DW_AT_decl_line(0x56) + .dwattr $C$DW$T$1635, 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$C$DW$T$517, DW_AT_decl_line(0x22) + .dwattr $C$DW$T$517, DW_AT_decl_column(0x19) + +$C$DW$T$1920 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1920, DW_AT_name("CT__ti_sysbios_family_arm_m3_Hwi_disablePriority") + .dwattr $C$DW$T$1920, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1920, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1920, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$1920, DW_AT_decl_line(0x23d) + .dwattr $C$DW$T$1920, DW_AT_decl_column(0x12) + +$C$DW$T$1921 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1921, DW_AT_name("CT__ti_sysbios_family_arm_m3_Hwi_numSparseInterrupts") + .dwattr $C$DW$T$1921, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1921, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1921, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$1921, DW_AT_decl_line(0x24f) + .dwattr $C$DW$T$1921, DW_AT_decl_column(0x12) + +$C$DW$T$1922 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1922, DW_AT_name("CT__ti_sysbios_family_arm_m3_Hwi_priGroup") + .dwattr $C$DW$T$1922, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1922, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1922, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$1922, DW_AT_decl_line(0x246) + .dwattr $C$DW$T$1922, DW_AT_decl_column(0x12) + +$C$DW$T$1923 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1923, DW_AT_name("CT__ti_sysbios_knl_Clock_timerId") + .dwattr $C$DW$T$1923, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1923, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1923, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h") + .dwattr $C$DW$T$1923, DW_AT_decl_line(0xe9) + .dwattr $C$DW$T$1923, DW_AT_decl_column(0x12) + +$C$DW$T$1924 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1924, DW_AT_name("CT__ti_sysbios_knl_Swi_numConstructedSwis") + .dwattr $C$DW$T$1924, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1924, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1924, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$1924, DW_AT_decl_line(0xf6) + .dwattr $C$DW$T$1924, DW_AT_decl_column(0x12) + +$C$DW$T$1925 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1925, DW_AT_name("CT__ti_sysbios_knl_Swi_numPriorities") + .dwattr $C$DW$T$1925, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1925, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1925, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$1925, DW_AT_decl_line(0xdb) + .dwattr $C$DW$T$1925, DW_AT_decl_column(0x12) + +$C$DW$T$1926 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1926, DW_AT_name("CT__ti_sysbios_knl_Task_SupportProxy_stackAlignment") + .dwattr $C$DW$T$1926, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1926, DW_AT_language(DW_LANG_C) + .dwattr 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$1928, DW_AT_decl_line(0x17a) + .dwattr $C$DW$T$1928, DW_AT_decl_column(0x12) + +$C$DW$T$1929 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1929, DW_AT_name("UInt") + .dwattr $C$DW$T$1929, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1929, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1929, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$1929, DW_AT_decl_line(0xe0) + .dwattr $C$DW$T$1929, DW_AT_decl_column(0x19) + +$C$DW$T$1930 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1930, DW_AT_name("Uns") + .dwattr $C$DW$T$1930, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$1930, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1930, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$1930, DW_AT_decl_line(0x109) + .dwattr $C$DW$T$1930, DW_AT_decl_column(0x19) + + +$C$DW$T$522 .dwtag DW_TAG_subroutine_type + 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$1932, DW_AT_decl_line(0x25f) + .dwattr $C$DW$T$1932, DW_AT_decl_column(0x14) + +$C$DW$T$1933 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1933, DW_AT_name("CT__ti_sysbios_knl_Swi_taskDisable") + .dwattr $C$DW$T$1933, DW_AT_type(*$C$DW$T$523) + .dwattr $C$DW$T$1933, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1933, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$1933, DW_AT_decl_line(0xe9) + .dwattr $C$DW$T$1933, DW_AT_decl_column(0x14) + +$C$DW$T$1934 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1934, DW_AT_name("ti_sysbios_interfaces_IHwi_disable_FxnT") + .dwattr $C$DW$T$1934, DW_AT_type(*$C$DW$T$523) + .dwattr $C$DW$T$1934, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1934, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/IHwi.h") + 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DW_AT_decl_column(0x14) + +$C$DW$T$1937 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1937, DW_AT_name("ti_sysbios_interfaces_ITimer_getNumTimers_FxnT") + .dwattr $C$DW$T$1937, DW_AT_type(*$C$DW$T$523) + .dwattr $C$DW$T$1937, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1937, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h") + .dwattr $C$DW$T$1937, DW_AT_decl_line(0x13b) + .dwattr $C$DW$T$1937, DW_AT_decl_column(0x14) + + +$C$DW$T$530 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$530, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$T$530, DW_AT_language(DW_LANG_C) +$C$DW$983 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$983, DW_AT_type(*$C$DW$T$517) + + .dwendtag $C$DW$T$530 + +$C$DW$T$531 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$531, DW_AT_type(*$C$DW$T$530) + .dwattr $C$DW$T$531, DW_AT_address_class(0x20) + +$C$DW$T$1938 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1938, DW_AT_name("ti_sysbios_interfaces_IHwi_disableInterrupt_FxnT") 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DW_AT_type(*$C$DW$T$517) + +$C$DW$T$1940 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1940, DW_AT_name("__T1_ti_sysbios_knl_Task_Module_State__smpCurMask") + .dwattr $C$DW$T$1940, DW_AT_type(*$C$DW$T$738) + .dwattr $C$DW$T$1940, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1940, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$1940, DW_AT_decl_line(0x9a) + .dwattr $C$DW$T$1940, DW_AT_decl_column(0x1b) + +$C$DW$T$1941 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1941, DW_AT_name("__T1_ti_sysbios_knl_Task_Module_State__smpCurSet") + .dwattr $C$DW$T$1941, DW_AT_type(*$C$DW$T$738) + .dwattr $C$DW$T$1941, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1941, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$1941, DW_AT_decl_line(0x97) + .dwattr $C$DW$T$1941, DW_AT_decl_column(0x1b) + +$C$DW$T$1942 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1942, 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$C$DW$T$822, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$822, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$822, DW_AT_decl_line(0x30) + .dwattr $C$DW$T$822, DW_AT_decl_column(0x1a) + +$C$DW$T$1999 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1999, DW_AT_name("CT__ti_sysbios_BIOS_heapSection") + .dwattr $C$DW$T$1999, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$T$1999, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1999, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$1999, DW_AT_decl_line(0x10b) + .dwattr $C$DW$T$1999, DW_AT_decl_column(0x14) + +$C$DW$T$2000 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2000, DW_AT_name("CT__xdc_runtime_Text_nameEmpty") + .dwattr $C$DW$T$2000, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$T$2000, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2000, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2000, DW_AT_decl_line(0xc0) + .dwattr $C$DW$T$2000, DW_AT_decl_column(0x14) + +$C$DW$T$2001 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2001, DW_AT_name("CT__xdc_runtime_Text_nameStatic") + .dwattr $C$DW$T$2001, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$T$2001, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2001, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2001, DW_AT_decl_line(0xc5) + .dwattr $C$DW$T$2001, DW_AT_decl_column(0x14) + +$C$DW$T$2002 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2002, DW_AT_name("CT__xdc_runtime_Text_nameUnknown") + .dwattr $C$DW$T$2002, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$T$2002, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2002, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2002, DW_AT_decl_line(0xbb) + .dwattr $C$DW$T$2002, DW_AT_decl_column(0x14) + +$C$DW$T$2003 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2003, DW_AT_name("String") + .dwattr $C$DW$T$2003, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$T$2003, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2003, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$2003, DW_AT_decl_line(0xf5) + .dwattr $C$DW$T$2003, DW_AT_decl_column(0x19) + +$C$DW$T$1407 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1407, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$T$1407, DW_AT_address_class(0x20) + +$C$DW$T$868 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$868, DW_AT_type(*$C$DW$T$6) + +$C$DW$T$869 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$869, DW_AT_type(*$C$DW$T$868) + .dwattr $C$DW$T$869, DW_AT_address_class(0x20) + +$C$DW$T$870 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$870, DW_AT_name("xdc_CString") + .dwattr $C$DW$T$870, DW_AT_type(*$C$DW$T$869) + .dwattr $C$DW$T$870, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$870, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$870, DW_AT_decl_line(0x31) + .dwattr $C$DW$T$870, DW_AT_decl_column(0x1a) + +$C$DW$T$2004 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2004, DW_AT_name("CString") + .dwattr $C$DW$T$2004, DW_AT_type(*$C$DW$T$870) + .dwattr $C$DW$T$2004, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2004, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$2004, DW_AT_decl_line(0xf7) + .dwattr $C$DW$T$2004, DW_AT_decl_column(0x19) + +$C$DW$T$1688 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1688, DW_AT_type(*$C$DW$T$870) + .dwattr $C$DW$T$1688, DW_AT_address_class(0x20) + +$C$DW$T$526 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$526, DW_AT_name("xdc_Char") + .dwattr $C$DW$T$526, DW_AT_type(*$C$DW$T$6) + .dwattr $C$DW$T$526, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$526, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h") + .dwattr $C$DW$T$526, DW_AT_decl_line(0x1d) + .dwattr $C$DW$T$526, DW_AT_decl_column(0x19) + +$C$DW$T$2013 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2013, DW_AT_name("Char") + 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DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2015, DW_AT_decl_line(0xd3) + .dwattr $C$DW$T$2015, DW_AT_decl_column(0x12) + +$C$DW$T$527 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$527, DW_AT_type(*$C$DW$T$526) + .dwattr $C$DW$T$527, DW_AT_address_class(0x20) + +$C$DW$T$808 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$808, DW_AT_name("__ARRAY1_ti_sysbios_knl_Task_Instance_State__stack") + .dwattr $C$DW$T$808, DW_AT_type(*$C$DW$T$527) + .dwattr $C$DW$T$808, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$808, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$808, DW_AT_decl_line(0x8d) + .dwattr $C$DW$T$808, DW_AT_decl_column(0x13) + +$C$DW$T$809 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$809, DW_AT_name("__TA_ti_sysbios_knl_Task_Instance_State__stack") + .dwattr $C$DW$T$809, DW_AT_type(*$C$DW$T$808) + .dwattr $C$DW$T$809, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$809, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$809, DW_AT_decl_line(0x8e) + .dwattr $C$DW$T$809, DW_AT_decl_column(0x3c) + +$C$DW$T$2016 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2016, DW_AT_name("__ARRAY1_xdc_runtime_Text_charTab") + .dwattr $C$DW$T$2016, DW_AT_type(*$C$DW$T$527) + .dwattr $C$DW$T$2016, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2016, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2016, DW_AT_decl_line(0xd4) + .dwattr $C$DW$T$2016, DW_AT_decl_column(0x13) + +$C$DW$T$2017 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2017, DW_AT_name("__TA_xdc_runtime_Text_charTab") + .dwattr $C$DW$T$2017, DW_AT_type(*$C$DW$T$2016) + .dwattr $C$DW$T$2017, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2017, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2017, DW_AT_decl_line(0xd5) + .dwattr $C$DW$T$2017, DW_AT_decl_column(0x2b) + +$C$DW$T$2018 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2018, DW_AT_name("CT__xdc_runtime_Text_charTab") + .dwattr $C$DW$T$2018, DW_AT_type(*$C$DW$T$2017) + .dwattr $C$DW$T$2018, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2018, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h") + .dwattr $C$DW$T$2018, DW_AT_decl_line(0xd6) + .dwattr $C$DW$T$2018, DW_AT_decl_column(0x27) + + +$C$DW$T$528 .dwtag DW_TAG_subroutine_type + .dwattr $C$DW$T$528, DW_AT_type(*$C$DW$T$527) + .dwattr $C$DW$T$528, DW_AT_language(DW_LANG_C) + .dwendtag $C$DW$T$528 + +$C$DW$T$529 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$529, DW_AT_type(*$C$DW$T$528) + .dwattr $C$DW$T$529, DW_AT_address_class(0x20) + +$C$DW$T$2019 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2019, DW_AT_name("ti_sysbios_interfaces_IHwi_getTaskSP_FxnT") + .dwattr $C$DW$T$2019, DW_AT_type(*$C$DW$T$529) + .dwattr $C$DW$T$2019, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2019, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/IHwi.h") + .dwattr $C$DW$T$2019, DW_AT_decl_line(0x16f) + .dwattr $C$DW$T$2019, DW_AT_decl_column(0x15) + +$C$DW$T$929 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$929, DW_AT_type(*$C$DW$T$527) + .dwattr $C$DW$T$929, DW_AT_address_class(0x20) + + +$C$DW$T$19 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$19, DW_AT_name("__mq") + .dwattr $C$DW$T$19, DW_AT_declaration + .dwattr $C$DW$T$19, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$19, DW_AT_decl_line(0x4b) + .dwattr $C$DW$T$19, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$19 + +$C$DW$T$2020 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2020, DW_AT_type(*$C$DW$T$19) + .dwattr $C$DW$T$2020, DW_AT_address_class(0x20) + +$C$DW$T$2021 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2021, DW_AT_name("__mqd_t") + .dwattr $C$DW$T$2021, DW_AT_type(*$C$DW$T$2020) + .dwattr $C$DW$T$2021, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2021, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$2021, DW_AT_decl_line(0x4b) + .dwattr $C$DW$T$2021, DW_AT_decl_column(0x16) + + +$C$DW$T$20 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$20, DW_AT_name("__timer") + .dwattr $C$DW$T$20, DW_AT_declaration + .dwattr $C$DW$T$20, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$20, DW_AT_decl_line(0x4a) + .dwattr $C$DW$T$20, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$20 + +$C$DW$T$2022 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2022, DW_AT_type(*$C$DW$T$20) + .dwattr $C$DW$T$2022, DW_AT_address_class(0x20) + +$C$DW$T$2023 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2023, DW_AT_name("__timer_t") + .dwattr $C$DW$T$2023, DW_AT_type(*$C$DW$T$2022) + .dwattr $C$DW$T$2023, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2023, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$2023, DW_AT_decl_line(0x4a) + .dwattr $C$DW$T$2023, DW_AT_decl_column(0x19) + + +$C$DW$T$473 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$473, DW_AT_name("__va_list_t") + .dwattr $C$DW$T$473, DW_AT_byte_size(0x04) +$C$DW$990 .dwtag DW_TAG_member + .dwattr $C$DW$990, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$990, DW_AT_name("__ap") + .dwattr $C$DW$990, DW_AT_TI_symbol_name("__ap") + .dwattr $C$DW$990, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$990, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$990, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$990, DW_AT_decl_line(0x8c) + .dwattr $C$DW$990, DW_AT_decl_column(0x0c) + + .dwattr $C$DW$T$473, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$473, 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DW_AT_name("ti_sysbios_BIOS_RtsLockType") + .dwattr $C$DW$T$2030, DW_AT_byte_size(0x01) +$C$DW$1008 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1008, DW_AT_name("ti_sysbios_BIOS_NoLocking") + .dwattr $C$DW$1008, DW_AT_const_value(0x00) + .dwattr $C$DW$1008, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1008, DW_AT_decl_line(0x4f) + .dwattr $C$DW$1008, DW_AT_decl_column(0x05) + +$C$DW$1009 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1009, DW_AT_name("ti_sysbios_BIOS_GateHwi") + .dwattr $C$DW$1009, DW_AT_const_value(0x01) + .dwattr $C$DW$1009, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1009, DW_AT_decl_line(0x50) + .dwattr $C$DW$1009, DW_AT_decl_column(0x05) + +$C$DW$1010 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1010, DW_AT_name("ti_sysbios_BIOS_GateSwi") + .dwattr $C$DW$1010, DW_AT_const_value(0x02) + .dwattr $C$DW$1010, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1010, DW_AT_decl_line(0x51) + .dwattr $C$DW$1010, DW_AT_decl_column(0x05) + +$C$DW$1011 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1011, DW_AT_name("ti_sysbios_BIOS_GateMutex") + .dwattr $C$DW$1011, DW_AT_const_value(0x03) + .dwattr $C$DW$1011, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1011, DW_AT_decl_line(0x52) + .dwattr $C$DW$1011, DW_AT_decl_column(0x05) + +$C$DW$1012 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1012, DW_AT_name("ti_sysbios_BIOS_GateMutexPri") + .dwattr $C$DW$1012, DW_AT_const_value(0x04) + .dwattr $C$DW$1012, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1012, DW_AT_decl_line(0x53) + .dwattr $C$DW$1012, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$2030, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$2030, DW_AT_decl_line(0x4e) + .dwattr $C$DW$T$2030, DW_AT_decl_column(0x06) + .dwendtag $C$DW$T$2030 + +$C$DW$T$2031 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2031, DW_AT_name("ti_sysbios_BIOS_RtsLockType") + .dwattr $C$DW$T$2031, DW_AT_type(*$C$DW$T$2030) + .dwattr $C$DW$T$2031, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2031, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$2031, DW_AT_decl_line(0x55) + .dwattr $C$DW$T$2031, DW_AT_decl_column(0x2a) + + +$C$DW$T$508 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$508, DW_AT_name("ti_sysbios_BIOS_ThreadType") + .dwattr $C$DW$T$508, DW_AT_byte_size(0x01) +$C$DW$1013 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1013, DW_AT_name("ti_sysbios_BIOS_ThreadType_Hwi") + .dwattr $C$DW$1013, DW_AT_const_value(0x00) + .dwattr $C$DW$1013, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1013, DW_AT_decl_line(0x46) + .dwattr $C$DW$1013, DW_AT_decl_column(0x05) + +$C$DW$1014 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1014, DW_AT_name("ti_sysbios_BIOS_ThreadType_Swi") + .dwattr $C$DW$1014, DW_AT_const_value(0x01) + .dwattr $C$DW$1014, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1014, DW_AT_decl_line(0x47) + .dwattr $C$DW$1014, DW_AT_decl_column(0x05) + +$C$DW$1015 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1015, DW_AT_name("ti_sysbios_BIOS_ThreadType_Task") + .dwattr $C$DW$1015, DW_AT_const_value(0x02) + .dwattr $C$DW$1015, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1015, DW_AT_decl_line(0x48) + .dwattr $C$DW$1015, DW_AT_decl_column(0x05) + +$C$DW$1016 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1016, DW_AT_name("ti_sysbios_BIOS_ThreadType_Main") + .dwattr $C$DW$1016, DW_AT_const_value(0x03) + .dwattr $C$DW$1016, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1016, DW_AT_decl_line(0x49) + .dwattr $C$DW$1016, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$508, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$508, DW_AT_decl_line(0x45) + .dwattr $C$DW$T$508, DW_AT_decl_column(0x06) + .dwendtag $C$DW$T$508 + +$C$DW$T$509 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$509, DW_AT_name("ti_sysbios_BIOS_ThreadType") + .dwattr $C$DW$T$509, DW_AT_type(*$C$DW$T$508) + .dwattr $C$DW$T$509, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$509, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$509, DW_AT_decl_line(0x4b) + .dwattr $C$DW$T$509, DW_AT_decl_column(0x29) + +$C$DW$T$2032 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2032, DW_AT_name("__T1_ti_sysbios_BIOS_Module_State__smpThreadType") + .dwattr $C$DW$T$2032, DW_AT_type(*$C$DW$T$509) + .dwattr $C$DW$T$2032, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2032, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$2032, DW_AT_decl_line(0x7d) + .dwattr $C$DW$T$2032, DW_AT_decl_column(0x24) + +$C$DW$T$2033 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2033, DW_AT_type(*$C$DW$T$509) + .dwattr $C$DW$T$2033, DW_AT_address_class(0x20) + +$C$DW$T$2034 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2034, DW_AT_name("__ARRAY1_ti_sysbios_BIOS_Module_State__smpThreadType") + .dwattr $C$DW$T$2034, DW_AT_type(*$C$DW$T$2033) + .dwattr $C$DW$T$2034, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2034, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$2034, DW_AT_decl_line(0x7e) + .dwattr $C$DW$T$2034, DW_AT_decl_column(0x25) + +$C$DW$T$2035 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2035, DW_AT_name("__TA_ti_sysbios_BIOS_Module_State__smpThreadType") + .dwattr $C$DW$T$2035, DW_AT_type(*$C$DW$T$2034) + .dwattr $C$DW$T$2035, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2035, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$2035, DW_AT_decl_line(0x7f) + .dwattr $C$DW$T$2035, DW_AT_decl_column(0x3e) + + +$C$DW$T$500 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$500, DW_AT_name("ti_sysbios_BIOS_intSize") + .dwattr $C$DW$T$500, DW_AT_byte_size(0x04) +$C$DW$1017 .dwtag DW_TAG_member + .dwattr $C$DW$1017, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$1017, DW_AT_name("intSize") + .dwattr $C$DW$1017, DW_AT_TI_symbol_name("intSize") + .dwattr $C$DW$1017, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1017, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1017, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$1017, DW_AT_decl_line(0x73) + .dwattr $C$DW$1017, DW_AT_decl_column(0x0d) + + .dwattr $C$DW$T$500, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h") + .dwattr $C$DW$T$500, DW_AT_decl_line(0x72) + .dwattr $C$DW$T$500, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$500 + +$C$DW$T$2036 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2036, DW_AT_name("ti_sysbios_BIOS_intSize") + .dwattr $C$DW$T$2036, DW_AT_type(*$C$DW$T$500) + .dwattr $C$DW$T$2036, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2036, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/package/package.defs.h") + .dwattr $C$DW$T$2036, DW_AT_decl_line(0x10) + .dwattr $C$DW$T$2036, DW_AT_decl_column(0x28) + + +$C$DW$T$505 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$505, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Args__create") + .dwattr $C$DW$T$505, DW_AT_byte_size(0x08) +$C$DW$1018 .dwtag DW_TAG_member + .dwattr $C$DW$1018, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$1018, DW_AT_name("intNum") + .dwattr $C$DW$1018, DW_AT_TI_symbol_name("intNum") + .dwattr $C$DW$1018, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1018, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1018, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1018, DW_AT_decl_line(0x12f) + .dwattr $C$DW$1018, DW_AT_decl_column(0x0d) + +$C$DW$1019 .dwtag DW_TAG_member + .dwattr $C$DW$1019, DW_AT_type(*$C$DW$T$504) + .dwattr $C$DW$1019, DW_AT_name("hwiFxn") + .dwattr $C$DW$1019, DW_AT_TI_symbol_name("hwiFxn") + .dwattr $C$DW$1019, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1019, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1019, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1019, DW_AT_decl_line(0x130) + .dwattr $C$DW$1019, DW_AT_decl_column(0x28) + + .dwattr $C$DW$T$505, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$505, DW_AT_decl_line(0x12e) + .dwattr $C$DW$T$505, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$505 + +$C$DW$T$2037 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2037, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Args__create") + .dwattr $C$DW$T$2037, DW_AT_type(*$C$DW$T$505) + .dwattr $C$DW$T$2037, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2037, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$2037, DW_AT_decl_line(0x131) + .dwattr $C$DW$T$2037, DW_AT_decl_column(0x03) + + +$C$DW$T$507 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$507, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_CCR") + .dwattr $C$DW$T$507, DW_AT_byte_size(0x06) +$C$DW$1020 .dwtag DW_TAG_member + .dwattr $C$DW$1020, DW_AT_type(*$C$DW$T$506) + .dwattr $C$DW$1020, DW_AT_name("STKALIGN") + .dwattr $C$DW$1020, DW_AT_TI_symbol_name("STKALIGN") + .dwattr $C$DW$1020, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1020, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1020, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1020, DW_AT_decl_line(0x61) + .dwattr $C$DW$1020, DW_AT_decl_column(0x0f) + +$C$DW$1021 .dwtag DW_TAG_member + .dwattr $C$DW$1021, DW_AT_type(*$C$DW$T$506) + .dwattr $C$DW$1021, DW_AT_name("BFHFNMIGN") + .dwattr $C$DW$1021, DW_AT_TI_symbol_name("BFHFNMIGN") + .dwattr $C$DW$1021, DW_AT_data_member_location[DW_OP_plus_uconst 0x1] + .dwattr $C$DW$1021, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1021, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1021, DW_AT_decl_line(0x62) + .dwattr $C$DW$1021, DW_AT_decl_column(0x0f) + +$C$DW$1022 .dwtag DW_TAG_member + .dwattr $C$DW$1022, DW_AT_type(*$C$DW$T$506) + .dwattr $C$DW$1022, DW_AT_name("DIV_0_TRP") + .dwattr $C$DW$1022, DW_AT_TI_symbol_name("DIV_0_TRP") + .dwattr $C$DW$1022, DW_AT_data_member_location[DW_OP_plus_uconst 0x2] + .dwattr $C$DW$1022, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1022, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1022, DW_AT_decl_line(0x63) + .dwattr $C$DW$1022, DW_AT_decl_column(0x0f) + +$C$DW$1023 .dwtag DW_TAG_member + .dwattr $C$DW$1023, DW_AT_type(*$C$DW$T$506) + .dwattr $C$DW$1023, DW_AT_name("UNALIGN_TRP") + .dwattr $C$DW$1023, DW_AT_TI_symbol_name("UNALIGN_TRP") + .dwattr $C$DW$1023, DW_AT_data_member_location[DW_OP_plus_uconst 0x3] + .dwattr $C$DW$1023, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1023, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1023, DW_AT_decl_line(0x64) + .dwattr $C$DW$1023, DW_AT_decl_column(0x0f) + +$C$DW$1024 .dwtag DW_TAG_member + .dwattr $C$DW$1024, DW_AT_type(*$C$DW$T$506) + .dwattr $C$DW$1024, DW_AT_name("USERSETMPEND") + .dwattr $C$DW$1024, DW_AT_TI_symbol_name("USERSETMPEND") + .dwattr $C$DW$1024, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1024, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1024, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1024, DW_AT_decl_line(0x65) + .dwattr $C$DW$1024, DW_AT_decl_column(0x0f) + +$C$DW$1025 .dwtag DW_TAG_member + .dwattr $C$DW$1025, DW_AT_type(*$C$DW$T$506) + .dwattr $C$DW$1025, DW_AT_name("NONEBASETHRDENA") + .dwattr $C$DW$1025, DW_AT_TI_symbol_name("NONEBASETHRDENA") + .dwattr $C$DW$1025, DW_AT_data_member_location[DW_OP_plus_uconst 0x5] + .dwattr $C$DW$1025, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1025, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1025, DW_AT_decl_line(0x66) + .dwattr $C$DW$1025, DW_AT_decl_column(0x0f) + + .dwattr $C$DW$T$507, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$507, DW_AT_decl_line(0x60) + .dwattr $C$DW$T$507, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$507 + +$C$DW$T$2038 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2038, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_CCR") + .dwattr $C$DW$T$2038, DW_AT_type(*$C$DW$T$507) + .dwattr $C$DW$T$2038, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2038, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$2038, DW_AT_decl_line(0x15) + .dwattr $C$DW$T$2038, DW_AT_decl_column(0x31) + + +$C$DW$T$512 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$512, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_ExcContext") + .dwattr $C$DW$T$512, DW_AT_byte_size(0x78) +$C$DW$1026 .dwtag DW_TAG_member + .dwattr $C$DW$1026, DW_AT_type(*$C$DW$T$509) + .dwattr $C$DW$1026, DW_AT_name("threadType") + .dwattr $C$DW$1026, DW_AT_TI_symbol_name("threadType") + .dwattr $C$DW$1026, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1026, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1026, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1026, DW_AT_decl_line(0xf6) + .dwattr $C$DW$1026, DW_AT_decl_column(0x20) + +$C$DW$1027 .dwtag DW_TAG_member + .dwattr $C$DW$1027, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1027, DW_AT_name("threadHandle") + .dwattr $C$DW$1027, DW_AT_TI_symbol_name("threadHandle") + .dwattr $C$DW$1027, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1027, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1027, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1027, DW_AT_decl_line(0xf7) + .dwattr $C$DW$1027, DW_AT_decl_column(0x0d) + +$C$DW$1028 .dwtag DW_TAG_member + .dwattr $C$DW$1028, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1028, DW_AT_name("threadStack") + .dwattr $C$DW$1028, DW_AT_TI_symbol_name("threadStack") + .dwattr $C$DW$1028, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1028, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1028, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1028, DW_AT_decl_line(0xf8) + .dwattr $C$DW$1028, DW_AT_decl_column(0x0d) + +$C$DW$1029 .dwtag DW_TAG_member + .dwattr $C$DW$1029, DW_AT_type(*$C$DW$T$511) + .dwattr $C$DW$1029, DW_AT_name("threadStackSize") + .dwattr $C$DW$1029, DW_AT_TI_symbol_name("threadStackSize") + .dwattr $C$DW$1029, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1029, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1029, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1029, DW_AT_decl_line(0xf9) + .dwattr $C$DW$1029, DW_AT_decl_column(0x0f) + +$C$DW$1030 .dwtag DW_TAG_member + .dwattr $C$DW$1030, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1030, DW_AT_name("r0") + .dwattr $C$DW$1030, DW_AT_TI_symbol_name("r0") + .dwattr $C$DW$1030, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1030, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1030, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1030, DW_AT_decl_line(0xfa) + .dwattr $C$DW$1030, DW_AT_decl_column(0x0d) + +$C$DW$1031 .dwtag DW_TAG_member + .dwattr $C$DW$1031, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1031, DW_AT_name("r1") + .dwattr $C$DW$1031, DW_AT_TI_symbol_name("r1") + .dwattr $C$DW$1031, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1031, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1031, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1031, DW_AT_decl_line(0xfb) + .dwattr $C$DW$1031, DW_AT_decl_column(0x0d) + +$C$DW$1032 .dwtag DW_TAG_member + .dwattr $C$DW$1032, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1032, DW_AT_name("r2") + .dwattr $C$DW$1032, DW_AT_TI_symbol_name("r2") + .dwattr $C$DW$1032, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$1032, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1032, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1032, DW_AT_decl_line(0xfc) + .dwattr $C$DW$1032, DW_AT_decl_column(0x0d) + +$C$DW$1033 .dwtag DW_TAG_member + .dwattr $C$DW$1033, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1033, DW_AT_name("r3") + .dwattr $C$DW$1033, DW_AT_TI_symbol_name("r3") + .dwattr $C$DW$1033, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1033, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1033, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1033, DW_AT_decl_line(0xfd) + .dwattr $C$DW$1033, DW_AT_decl_column(0x0d) + +$C$DW$1034 .dwtag DW_TAG_member + .dwattr $C$DW$1034, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1034, DW_AT_name("r4") + .dwattr $C$DW$1034, DW_AT_TI_symbol_name("r4") + .dwattr $C$DW$1034, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1034, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1034, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1034, DW_AT_decl_line(0xfe) + .dwattr $C$DW$1034, DW_AT_decl_column(0x0d) + +$C$DW$1035 .dwtag DW_TAG_member + .dwattr $C$DW$1035, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1035, DW_AT_name("r5") + .dwattr $C$DW$1035, DW_AT_TI_symbol_name("r5") + .dwattr $C$DW$1035, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$1035, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1035, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1035, DW_AT_decl_line(0xff) + .dwattr $C$DW$1035, DW_AT_decl_column(0x0d) + +$C$DW$1036 .dwtag DW_TAG_member + .dwattr $C$DW$1036, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1036, DW_AT_name("r6") + .dwattr $C$DW$1036, DW_AT_TI_symbol_name("r6") + .dwattr $C$DW$1036, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$1036, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1036, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1036, DW_AT_decl_line(0x100) + .dwattr $C$DW$1036, DW_AT_decl_column(0x0d) + +$C$DW$1037 .dwtag DW_TAG_member + .dwattr $C$DW$1037, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1037, DW_AT_name("r7") + .dwattr $C$DW$1037, DW_AT_TI_symbol_name("r7") + .dwattr $C$DW$1037, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c] + .dwattr $C$DW$1037, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1037, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1037, DW_AT_decl_line(0x101) + .dwattr $C$DW$1037, DW_AT_decl_column(0x0d) + +$C$DW$1038 .dwtag DW_TAG_member + .dwattr $C$DW$1038, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1038, DW_AT_name("r8") + .dwattr $C$DW$1038, DW_AT_TI_symbol_name("r8") + .dwattr $C$DW$1038, DW_AT_data_member_location[DW_OP_plus_uconst 0x30] + .dwattr $C$DW$1038, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1038, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1038, DW_AT_decl_line(0x102) + .dwattr $C$DW$1038, DW_AT_decl_column(0x0d) + +$C$DW$1039 .dwtag DW_TAG_member + .dwattr $C$DW$1039, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1039, DW_AT_name("r9") + .dwattr $C$DW$1039, DW_AT_TI_symbol_name("r9") + .dwattr $C$DW$1039, DW_AT_data_member_location[DW_OP_plus_uconst 0x34] + .dwattr $C$DW$1039, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1039, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1039, DW_AT_decl_line(0x103) + .dwattr $C$DW$1039, DW_AT_decl_column(0x0d) + +$C$DW$1040 .dwtag DW_TAG_member + .dwattr $C$DW$1040, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1040, DW_AT_name("r10") + .dwattr $C$DW$1040, DW_AT_TI_symbol_name("r10") + .dwattr $C$DW$1040, DW_AT_data_member_location[DW_OP_plus_uconst 0x38] + .dwattr $C$DW$1040, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1040, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1040, DW_AT_decl_line(0x104) + .dwattr $C$DW$1040, DW_AT_decl_column(0x0d) + +$C$DW$1041 .dwtag DW_TAG_member + .dwattr $C$DW$1041, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1041, DW_AT_name("r11") + .dwattr $C$DW$1041, DW_AT_TI_symbol_name("r11") + .dwattr $C$DW$1041, DW_AT_data_member_location[DW_OP_plus_uconst 0x3c] + .dwattr $C$DW$1041, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1041, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1041, DW_AT_decl_line(0x105) + .dwattr $C$DW$1041, DW_AT_decl_column(0x0d) + +$C$DW$1042 .dwtag DW_TAG_member + .dwattr $C$DW$1042, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1042, DW_AT_name("r12") + .dwattr $C$DW$1042, DW_AT_TI_symbol_name("r12") + .dwattr $C$DW$1042, DW_AT_data_member_location[DW_OP_plus_uconst 0x40] + .dwattr $C$DW$1042, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1042, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1042, DW_AT_decl_line(0x106) + .dwattr $C$DW$1042, DW_AT_decl_column(0x0d) + +$C$DW$1043 .dwtag DW_TAG_member + .dwattr $C$DW$1043, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1043, DW_AT_name("sp") + .dwattr $C$DW$1043, DW_AT_TI_symbol_name("sp") + .dwattr $C$DW$1043, DW_AT_data_member_location[DW_OP_plus_uconst 0x44] + .dwattr $C$DW$1043, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1043, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1043, DW_AT_decl_line(0x107) + .dwattr $C$DW$1043, DW_AT_decl_column(0x0d) + +$C$DW$1044 .dwtag DW_TAG_member + .dwattr $C$DW$1044, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1044, DW_AT_name("lr") + .dwattr $C$DW$1044, DW_AT_TI_symbol_name("lr") + .dwattr $C$DW$1044, DW_AT_data_member_location[DW_OP_plus_uconst 0x48] + .dwattr $C$DW$1044, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1044, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1044, DW_AT_decl_line(0x108) + .dwattr $C$DW$1044, DW_AT_decl_column(0x0d) + +$C$DW$1045 .dwtag DW_TAG_member + .dwattr $C$DW$1045, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1045, DW_AT_name("pc") + .dwattr $C$DW$1045, DW_AT_TI_symbol_name("pc") + .dwattr $C$DW$1045, DW_AT_data_member_location[DW_OP_plus_uconst 0x4c] + .dwattr $C$DW$1045, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1045, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1045, DW_AT_decl_line(0x109) + .dwattr $C$DW$1045, DW_AT_decl_column(0x0d) + +$C$DW$1046 .dwtag DW_TAG_member + .dwattr $C$DW$1046, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1046, DW_AT_name("psr") + .dwattr $C$DW$1046, DW_AT_TI_symbol_name("psr") + .dwattr $C$DW$1046, DW_AT_data_member_location[DW_OP_plus_uconst 0x50] + .dwattr $C$DW$1046, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1046, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1046, DW_AT_decl_line(0x10a) + .dwattr $C$DW$1046, DW_AT_decl_column(0x0d) + +$C$DW$1047 .dwtag DW_TAG_member + .dwattr $C$DW$1047, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1047, DW_AT_name("ICSR") + .dwattr $C$DW$1047, DW_AT_TI_symbol_name("ICSR") + .dwattr $C$DW$1047, DW_AT_data_member_location[DW_OP_plus_uconst 0x54] + .dwattr $C$DW$1047, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1047, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1047, DW_AT_decl_line(0x10b) + .dwattr $C$DW$1047, DW_AT_decl_column(0x0d) + +$C$DW$1048 .dwtag DW_TAG_member + .dwattr $C$DW$1048, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1048, DW_AT_name("MMFSR") + .dwattr $C$DW$1048, DW_AT_TI_symbol_name("MMFSR") + .dwattr $C$DW$1048, DW_AT_data_member_location[DW_OP_plus_uconst 0x58] + .dwattr $C$DW$1048, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1048, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1048, DW_AT_decl_line(0x10c) + .dwattr $C$DW$1048, DW_AT_decl_column(0x0d) + +$C$DW$1049 .dwtag DW_TAG_member + .dwattr $C$DW$1049, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1049, DW_AT_name("BFSR") + .dwattr $C$DW$1049, DW_AT_TI_symbol_name("BFSR") + .dwattr $C$DW$1049, DW_AT_data_member_location[DW_OP_plus_uconst 0x5c] + .dwattr $C$DW$1049, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1049, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1049, DW_AT_decl_line(0x10d) + .dwattr $C$DW$1049, DW_AT_decl_column(0x0d) + +$C$DW$1050 .dwtag DW_TAG_member + .dwattr $C$DW$1050, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1050, DW_AT_name("UFSR") + .dwattr $C$DW$1050, DW_AT_TI_symbol_name("UFSR") + .dwattr $C$DW$1050, DW_AT_data_member_location[DW_OP_plus_uconst 0x60] + .dwattr $C$DW$1050, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1050, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1050, DW_AT_decl_line(0x10e) + .dwattr $C$DW$1050, DW_AT_decl_column(0x0d) + +$C$DW$1051 .dwtag DW_TAG_member + .dwattr $C$DW$1051, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1051, DW_AT_name("HFSR") + .dwattr $C$DW$1051, DW_AT_TI_symbol_name("HFSR") + .dwattr $C$DW$1051, DW_AT_data_member_location[DW_OP_plus_uconst 0x64] + .dwattr $C$DW$1051, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1051, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1051, DW_AT_decl_line(0x10f) + .dwattr $C$DW$1051, DW_AT_decl_column(0x0d) + +$C$DW$1052 .dwtag DW_TAG_member + .dwattr $C$DW$1052, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1052, DW_AT_name("DFSR") + .dwattr $C$DW$1052, DW_AT_TI_symbol_name("DFSR") + .dwattr $C$DW$1052, DW_AT_data_member_location[DW_OP_plus_uconst 0x68] + .dwattr $C$DW$1052, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1052, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1052, DW_AT_decl_line(0x110) + .dwattr $C$DW$1052, DW_AT_decl_column(0x0d) + +$C$DW$1053 .dwtag DW_TAG_member + .dwattr $C$DW$1053, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1053, DW_AT_name("MMAR") + .dwattr $C$DW$1053, DW_AT_TI_symbol_name("MMAR") + .dwattr $C$DW$1053, DW_AT_data_member_location[DW_OP_plus_uconst 0x6c] + .dwattr $C$DW$1053, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1053, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1053, DW_AT_decl_line(0x111) + .dwattr $C$DW$1053, DW_AT_decl_column(0x0d) + +$C$DW$1054 .dwtag DW_TAG_member + .dwattr $C$DW$1054, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1054, DW_AT_name("BFAR") + .dwattr $C$DW$1054, DW_AT_TI_symbol_name("BFAR") + .dwattr $C$DW$1054, DW_AT_data_member_location[DW_OP_plus_uconst 0x70] + .dwattr $C$DW$1054, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1054, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1054, DW_AT_decl_line(0x112) + .dwattr $C$DW$1054, DW_AT_decl_column(0x0d) + +$C$DW$1055 .dwtag DW_TAG_member + .dwattr $C$DW$1055, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1055, DW_AT_name("AFSR") + .dwattr $C$DW$1055, DW_AT_TI_symbol_name("AFSR") + .dwattr $C$DW$1055, DW_AT_data_member_location[DW_OP_plus_uconst 0x74] + .dwattr $C$DW$1055, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1055, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1055, DW_AT_decl_line(0x113) + .dwattr $C$DW$1055, DW_AT_decl_column(0x0d) + + .dwattr $C$DW$T$512, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$512, DW_AT_decl_line(0xf5) + .dwattr $C$DW$T$512, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$512 + +$C$DW$T$1420 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1420, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_ExcContext") + .dwattr $C$DW$T$1420, DW_AT_type(*$C$DW$T$512) + .dwattr $C$DW$T$1420, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1420, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$1420, DW_AT_decl_line(0x17) + .dwattr $C$DW$T$1420, DW_AT_decl_column(0x38) + +$C$DW$T$1421 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1421, DW_AT_type(*$C$DW$T$1420) + .dwattr $C$DW$T$1421, DW_AT_address_class(0x20) + +$C$DW$T$2039 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2039, DW_AT_name("__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excContext") + .dwattr $C$DW$T$2039, DW_AT_type(*$C$DW$T$1421) + .dwattr $C$DW$T$2039, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2039, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$2039, DW_AT_decl_line(0x144) + .dwattr $C$DW$T$2039, DW_AT_decl_column(0x32) + +$C$DW$T$2040 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2040, DW_AT_type(*$C$DW$T$1421) + .dwattr $C$DW$T$2040, DW_AT_address_class(0x20) + +$C$DW$T$2041 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2041, DW_AT_name("__ARRAY1_ti_sysbios_family_arm_m3_Hwi_Module_State__excContext") + .dwattr $C$DW$T$2041, DW_AT_type(*$C$DW$T$2040) + .dwattr $C$DW$T$2041, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2041, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$2041, DW_AT_decl_line(0x145) + .dwattr $C$DW$T$2041, DW_AT_decl_column(0x33) + +$C$DW$T$2042 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2042, DW_AT_name("__TA_ti_sysbios_family_arm_m3_Hwi_Module_State__excContext") + .dwattr $C$DW$T$2042, DW_AT_type(*$C$DW$T$2041) + .dwattr $C$DW$T$2042, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2042, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$2042, DW_AT_decl_line(0x146) + .dwattr $C$DW$T$2042, DW_AT_decl_column(0x48) + + +$C$DW$T$549 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$549, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Fxns__") + .dwattr $C$DW$T$549, DW_AT_byte_size(0x60) +$C$DW$1056 .dwtag DW_TAG_member + .dwattr $C$DW$1056, DW_AT_type(*$C$DW$T$475) + .dwattr $C$DW$1056, DW_AT_name("__base") + .dwattr $C$DW$1056, DW_AT_TI_symbol_name("__base") + .dwattr $C$DW$1056, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1056, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1056, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1056, DW_AT_decl_line(0x29f) + .dwattr $C$DW$1056, DW_AT_decl_column(0x1d) + +$C$DW$1057 .dwtag DW_TAG_member + .dwattr $C$DW$1057, DW_AT_type(*$C$DW$T$478) + .dwattr $C$DW$1057, DW_AT_name("__sysp") + .dwattr $C$DW$1057, DW_AT_TI_symbol_name("__sysp") + .dwattr $C$DW$1057, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1057, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1057, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1057, DW_AT_decl_line(0x2a0) + .dwattr $C$DW$1057, DW_AT_decl_column(0x27) + +$C$DW$1058 .dwtag DW_TAG_member + .dwattr $C$DW$1058, DW_AT_type(*$C$DW$T$516) + .dwattr $C$DW$1058, DW_AT_name("getStackInfo") + .dwattr $C$DW$1058, DW_AT_TI_symbol_name("getStackInfo") + .dwattr $C$DW$1058, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1058, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1058, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1058, DW_AT_decl_line(0x2a1) + .dwattr $C$DW$1058, DW_AT_decl_column(0x10) + +$C$DW$1059 .dwtag DW_TAG_member + .dwattr $C$DW$1059, DW_AT_type(*$C$DW$T$519) + .dwattr $C$DW$1059, DW_AT_name("getCoreStackInfo") + .dwattr $C$DW$1059, DW_AT_TI_symbol_name("getCoreStackInfo") + .dwattr $C$DW$1059, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1059, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1059, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1059, DW_AT_decl_line(0x2a2) + .dwattr $C$DW$1059, DW_AT_decl_column(0x10) + +$C$DW$1060 .dwtag DW_TAG_member + .dwattr $C$DW$1060, DW_AT_type(*$C$DW$T$521) + .dwattr $C$DW$1060, DW_AT_name("startup") + .dwattr $C$DW$1060, DW_AT_TI_symbol_name("startup") + .dwattr $C$DW$1060, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1060, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1060, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1060, DW_AT_decl_line(0x2a3) + .dwattr $C$DW$1060, DW_AT_decl_column(0x10) + +$C$DW$1061 .dwtag DW_TAG_member + .dwattr $C$DW$1061, DW_AT_type(*$C$DW$T$523) + .dwattr $C$DW$1061, DW_AT_name("disable") + .dwattr $C$DW$1061, DW_AT_TI_symbol_name("disable") + .dwattr $C$DW$1061, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1061, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1061, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1061, DW_AT_decl_line(0x2a4) + .dwattr $C$DW$1061, DW_AT_decl_column(0x10) + +$C$DW$1062 .dwtag DW_TAG_member + .dwattr $C$DW$1062, DW_AT_type(*$C$DW$T$523) + .dwattr $C$DW$1062, DW_AT_name("enable") + .dwattr $C$DW$1062, DW_AT_TI_symbol_name("enable") + .dwattr $C$DW$1062, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$1062, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1062, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1062, DW_AT_decl_line(0x2a5) + .dwattr $C$DW$1062, DW_AT_decl_column(0x10) + +$C$DW$1063 .dwtag DW_TAG_member + .dwattr $C$DW$1063, DW_AT_type(*$C$DW$T$525) + .dwattr $C$DW$1063, DW_AT_name("restore") + .dwattr $C$DW$1063, DW_AT_TI_symbol_name("restore") + .dwattr $C$DW$1063, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1063, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1063, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1063, DW_AT_decl_line(0x2a6) + .dwattr $C$DW$1063, DW_AT_decl_column(0x10) + +$C$DW$1064 .dwtag DW_TAG_member + .dwattr $C$DW$1064, DW_AT_type(*$C$DW$T$521) + .dwattr $C$DW$1064, DW_AT_name("switchFromBootStack") + .dwattr $C$DW$1064, DW_AT_TI_symbol_name("switchFromBootStack") + .dwattr $C$DW$1064, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1064, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1064, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1064, DW_AT_decl_line(0x2a7) + .dwattr $C$DW$1064, DW_AT_decl_column(0x10) + +$C$DW$1065 .dwtag DW_TAG_member + .dwattr $C$DW$1065, DW_AT_type(*$C$DW$T$525) + .dwattr $C$DW$1065, DW_AT_name("post") + .dwattr $C$DW$1065, DW_AT_TI_symbol_name("post") + .dwattr $C$DW$1065, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$1065, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1065, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1065, DW_AT_decl_line(0x2a8) + .dwattr $C$DW$1065, DW_AT_decl_column(0x10) + +$C$DW$1066 .dwtag DW_TAG_member + .dwattr $C$DW$1066, DW_AT_type(*$C$DW$T$529) + .dwattr $C$DW$1066, DW_AT_name("getTaskSP") + .dwattr $C$DW$1066, DW_AT_TI_symbol_name("getTaskSP") + .dwattr $C$DW$1066, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$1066, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1066, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1066, DW_AT_decl_line(0x2a9) + .dwattr $C$DW$1066, DW_AT_decl_column(0x11) + +$C$DW$1067 .dwtag DW_TAG_member + .dwattr $C$DW$1067, DW_AT_type(*$C$DW$T$531) + .dwattr $C$DW$1067, DW_AT_name("disableInterrupt") + .dwattr $C$DW$1067, DW_AT_TI_symbol_name("disableInterrupt") + .dwattr $C$DW$1067, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c] + .dwattr $C$DW$1067, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1067, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1067, DW_AT_decl_line(0x2aa) + .dwattr $C$DW$1067, DW_AT_decl_column(0x10) + +$C$DW$1068 .dwtag DW_TAG_member + .dwattr $C$DW$1068, DW_AT_type(*$C$DW$T$531) + .dwattr $C$DW$1068, DW_AT_name("enableInterrupt") + .dwattr $C$DW$1068, DW_AT_TI_symbol_name("enableInterrupt") + .dwattr $C$DW$1068, DW_AT_data_member_location[DW_OP_plus_uconst 0x30] + .dwattr $C$DW$1068, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1068, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1068, DW_AT_decl_line(0x2ab) + .dwattr $C$DW$1068, DW_AT_decl_column(0x10) + +$C$DW$1069 .dwtag DW_TAG_member + .dwattr $C$DW$1069, DW_AT_type(*$C$DW$T$533) + .dwattr $C$DW$1069, DW_AT_name("restoreInterrupt") + .dwattr $C$DW$1069, DW_AT_TI_symbol_name("restoreInterrupt") + .dwattr $C$DW$1069, DW_AT_data_member_location[DW_OP_plus_uconst 0x34] + .dwattr $C$DW$1069, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1069, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1069, DW_AT_decl_line(0x2ac) + .dwattr $C$DW$1069, DW_AT_decl_column(0x10) + +$C$DW$1070 .dwtag DW_TAG_member + .dwattr $C$DW$1070, DW_AT_type(*$C$DW$T$525) + .dwattr $C$DW$1070, DW_AT_name("clearInterrupt") + .dwattr $C$DW$1070, DW_AT_TI_symbol_name("clearInterrupt") + .dwattr $C$DW$1070, DW_AT_data_member_location[DW_OP_plus_uconst 0x38] + .dwattr $C$DW$1070, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1070, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1070, DW_AT_decl_line(0x2ad) + .dwattr $C$DW$1070, DW_AT_decl_column(0x10) + +$C$DW$1071 .dwtag DW_TAG_member + .dwattr $C$DW$1071, DW_AT_type(*$C$DW$T$539) + .dwattr $C$DW$1071, DW_AT_name("getFunc") + .dwattr $C$DW$1071, DW_AT_TI_symbol_name("getFunc") + .dwattr $C$DW$1071, DW_AT_data_member_location[DW_OP_plus_uconst 0x3c] + .dwattr $C$DW$1071, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1071, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1071, DW_AT_decl_line(0x2ae) + .dwattr $C$DW$1071, DW_AT_decl_column(0x2a) + +$C$DW$1072 .dwtag DW_TAG_member + .dwattr $C$DW$1072, DW_AT_type(*$C$DW$T$541) + .dwattr $C$DW$1072, DW_AT_name("setFunc") + .dwattr $C$DW$1072, DW_AT_TI_symbol_name("setFunc") + .dwattr $C$DW$1072, DW_AT_data_member_location[DW_OP_plus_uconst 0x40] + .dwattr $C$DW$1072, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1072, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1072, DW_AT_decl_line(0x2af) + .dwattr $C$DW$1072, DW_AT_decl_column(0x10) + +$C$DW$1073 .dwtag DW_TAG_member + .dwattr $C$DW$1073, DW_AT_type(*$C$DW$T$543) + .dwattr $C$DW$1073, DW_AT_name("getHookContext") + .dwattr $C$DW$1073, DW_AT_TI_symbol_name("getHookContext") + .dwattr $C$DW$1073, DW_AT_data_member_location[DW_OP_plus_uconst 0x44] + .dwattr $C$DW$1073, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1073, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1073, DW_AT_decl_line(0x2b0) + .dwattr $C$DW$1073, DW_AT_decl_column(0x0f) + +$C$DW$1074 .dwtag DW_TAG_member + .dwattr $C$DW$1074, DW_AT_type(*$C$DW$T$545) + .dwattr $C$DW$1074, DW_AT_name("setHookContext") + .dwattr $C$DW$1074, DW_AT_TI_symbol_name("setHookContext") + .dwattr $C$DW$1074, DW_AT_data_member_location[DW_OP_plus_uconst 0x48] + .dwattr $C$DW$1074, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1074, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1074, DW_AT_decl_line(0x2b1) + .dwattr $C$DW$1074, DW_AT_decl_column(0x10) + +$C$DW$1075 .dwtag DW_TAG_member + .dwattr $C$DW$1075, DW_AT_type(*$C$DW$T$548) + .dwattr $C$DW$1075, DW_AT_name("getIrp") + .dwattr $C$DW$1075, DW_AT_TI_symbol_name("getIrp") + .dwattr $C$DW$1075, DW_AT_data_member_location[DW_OP_plus_uconst 0x4c] + .dwattr $C$DW$1075, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1075, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1075, DW_AT_decl_line(0x2b2) + .dwattr $C$DW$1075, DW_AT_decl_column(0x26) + +$C$DW$1076 .dwtag DW_TAG_member + .dwattr $C$DW$1076, DW_AT_type(*$C$DW$T$476) + .dwattr $C$DW$1076, DW_AT_name("__sfxns") + .dwattr $C$DW$1076, DW_AT_TI_symbol_name("__sfxns") + .dwattr $C$DW$1076, DW_AT_data_member_location[DW_OP_plus_uconst 0x50] + .dwattr $C$DW$1076, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1076, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1076, DW_AT_decl_line(0x2b3) + .dwattr $C$DW$1076, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$549, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$549, DW_AT_decl_line(0x29e) + .dwattr $C$DW$T$549, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$549 + +$C$DW$T$609 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$609, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Fxns__") + .dwattr $C$DW$T$609, DW_AT_type(*$C$DW$T$549) + .dwattr $C$DW$T$609, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$609, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$609, DW_AT_decl_line(0x19) + .dwattr $C$DW$T$609, DW_AT_decl_column(0x34) + +$C$DW$T$610 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$610, DW_AT_type(*$C$DW$T$609) + +$C$DW$T$611 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$611, DW_AT_type(*$C$DW$T$610) + .dwattr $C$DW$T$611, DW_AT_address_class(0x20) + +$C$DW$T$2043 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2043, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Module") + .dwattr $C$DW$T$2043, DW_AT_type(*$C$DW$T$611) + .dwattr $C$DW$T$2043, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2043, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$2043, DW_AT_decl_line(0x1a) + .dwattr $C$DW$T$2043, DW_AT_decl_column(0x34) + + +$C$DW$T$22 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$22, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Module_State") + .dwattr $C$DW$T$22, DW_AT_declaration + .dwattr $C$DW$T$22, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$22, DW_AT_decl_line(0x18) + .dwattr $C$DW$T$22, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$22 + +$C$DW$T$2044 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2044, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Module_State") + .dwattr $C$DW$T$2044, DW_AT_type(*$C$DW$T$22) + .dwattr $C$DW$T$2044, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2044, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$2044, DW_AT_decl_line(0x18) + .dwattr $C$DW$T$2044, DW_AT_decl_column(0x3a) + + +$C$DW$T$605 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$605, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_NVIC") + .dwattr $C$DW$T$605, DW_AT_byte_size(0x1000) +$C$DW$1077 .dwtag DW_TAG_member + .dwattr $C$DW$1077, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1077, DW_AT_name("RES_00") + .dwattr $C$DW$1077, DW_AT_TI_symbol_name("RES_00") + .dwattr $C$DW$1077, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1077, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1077, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1077, DW_AT_decl_line(0xa1) + .dwattr $C$DW$1077, DW_AT_decl_column(0x10) + +$C$DW$1078 .dwtag DW_TAG_member + .dwattr $C$DW$1078, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1078, DW_AT_name("ICTR") + .dwattr $C$DW$1078, DW_AT_TI_symbol_name("ICTR") + .dwattr $C$DW$1078, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1078, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1078, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1078, DW_AT_decl_line(0xa2) + .dwattr $C$DW$1078, DW_AT_decl_column(0x10) + +$C$DW$1079 .dwtag DW_TAG_member + .dwattr $C$DW$1079, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1079, DW_AT_name("RES_08") + .dwattr $C$DW$1079, DW_AT_TI_symbol_name("RES_08") + .dwattr $C$DW$1079, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1079, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1079, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1079, DW_AT_decl_line(0xa3) + .dwattr $C$DW$1079, DW_AT_decl_column(0x10) + +$C$DW$1080 .dwtag DW_TAG_member + .dwattr $C$DW$1080, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1080, DW_AT_name("RES_0C") + .dwattr $C$DW$1080, DW_AT_TI_symbol_name("RES_0C") + .dwattr $C$DW$1080, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1080, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1080, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1080, DW_AT_decl_line(0xa4) + .dwattr $C$DW$1080, DW_AT_decl_column(0x10) + +$C$DW$1081 .dwtag DW_TAG_member + .dwattr $C$DW$1081, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1081, DW_AT_name("STCSR") + .dwattr $C$DW$1081, DW_AT_TI_symbol_name("STCSR") + .dwattr $C$DW$1081, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1081, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1081, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1081, DW_AT_decl_line(0xa5) + .dwattr $C$DW$1081, DW_AT_decl_column(0x10) + +$C$DW$1082 .dwtag DW_TAG_member + .dwattr $C$DW$1082, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1082, DW_AT_name("STRVR") + .dwattr $C$DW$1082, DW_AT_TI_symbol_name("STRVR") + .dwattr $C$DW$1082, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1082, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1082, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1082, DW_AT_decl_line(0xa6) + .dwattr $C$DW$1082, DW_AT_decl_column(0x10) + +$C$DW$1083 .dwtag DW_TAG_member + .dwattr $C$DW$1083, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1083, DW_AT_name("STCVR") + .dwattr $C$DW$1083, DW_AT_TI_symbol_name("STCVR") + .dwattr $C$DW$1083, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$1083, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1083, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1083, DW_AT_decl_line(0xa7) + .dwattr $C$DW$1083, DW_AT_decl_column(0x10) + +$C$DW$1084 .dwtag DW_TAG_member + .dwattr $C$DW$1084, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1084, DW_AT_name("STCALIB") + .dwattr $C$DW$1084, DW_AT_TI_symbol_name("STCALIB") + .dwattr $C$DW$1084, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1084, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1084, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1084, DW_AT_decl_line(0xa8) + .dwattr $C$DW$1084, DW_AT_decl_column(0x10) + +$C$DW$1085 .dwtag DW_TAG_member + .dwattr $C$DW$1085, DW_AT_type(*$C$DW$T$555) + .dwattr $C$DW$1085, DW_AT_name("RES_20") + .dwattr $C$DW$1085, DW_AT_TI_symbol_name("RES_20") + .dwattr $C$DW$1085, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1085, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1085, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1085, DW_AT_decl_line(0xa9) + .dwattr $C$DW$1085, DW_AT_decl_column(0x34) + +$C$DW$1086 .dwtag DW_TAG_member + .dwattr $C$DW$1086, DW_AT_type(*$C$DW$T$558) + .dwattr $C$DW$1086, DW_AT_name("ISER") + .dwattr $C$DW$1086, DW_AT_TI_symbol_name("ISER") + .dwattr $C$DW$1086, DW_AT_data_member_location[DW_OP_plus_uconst 0x100] + .dwattr $C$DW$1086, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1086, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1086, DW_AT_decl_line(0xaa) + .dwattr $C$DW$1086, DW_AT_decl_column(0x32) + +$C$DW$1087 .dwtag DW_TAG_member + .dwattr $C$DW$1087, DW_AT_type(*$C$DW$T$561) + .dwattr $C$DW$1087, DW_AT_name("RES_120") + .dwattr $C$DW$1087, DW_AT_TI_symbol_name("RES_120") + .dwattr $C$DW$1087, DW_AT_data_member_location[DW_OP_plus_uconst 0x120] + .dwattr $C$DW$1087, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1087, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1087, DW_AT_decl_line(0xab) + .dwattr $C$DW$1087, DW_AT_decl_column(0x35) + +$C$DW$1088 .dwtag DW_TAG_member + .dwattr $C$DW$1088, DW_AT_type(*$C$DW$T$563) + .dwattr $C$DW$1088, DW_AT_name("ICER") + .dwattr $C$DW$1088, DW_AT_TI_symbol_name("ICER") + .dwattr $C$DW$1088, DW_AT_data_member_location[DW_OP_plus_uconst 0x180] + .dwattr $C$DW$1088, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1088, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1088, DW_AT_decl_line(0xac) + .dwattr $C$DW$1088, DW_AT_decl_column(0x32) + +$C$DW$1089 .dwtag DW_TAG_member + .dwattr $C$DW$1089, DW_AT_type(*$C$DW$T$565) + .dwattr $C$DW$1089, DW_AT_name("RES_1A0") + .dwattr $C$DW$1089, DW_AT_TI_symbol_name("RES_1A0") + .dwattr $C$DW$1089, DW_AT_data_member_location[DW_OP_plus_uconst 0x1a0] + .dwattr $C$DW$1089, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1089, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1089, DW_AT_decl_line(0xad) + .dwattr $C$DW$1089, DW_AT_decl_column(0x35) + +$C$DW$1090 .dwtag DW_TAG_member + .dwattr $C$DW$1090, DW_AT_type(*$C$DW$T$567) + .dwattr $C$DW$1090, DW_AT_name("ISPR") + .dwattr $C$DW$1090, DW_AT_TI_symbol_name("ISPR") + .dwattr $C$DW$1090, DW_AT_data_member_location[DW_OP_plus_uconst 0x200] + .dwattr $C$DW$1090, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1090, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1090, DW_AT_decl_line(0xae) + .dwattr $C$DW$1090, DW_AT_decl_column(0x32) + +$C$DW$1091 .dwtag DW_TAG_member + .dwattr $C$DW$1091, DW_AT_type(*$C$DW$T$569) + .dwattr $C$DW$1091, DW_AT_name("RES_220") + .dwattr $C$DW$1091, DW_AT_TI_symbol_name("RES_220") + .dwattr $C$DW$1091, DW_AT_data_member_location[DW_OP_plus_uconst 0x220] + .dwattr $C$DW$1091, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1091, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1091, DW_AT_decl_line(0xaf) + .dwattr $C$DW$1091, DW_AT_decl_column(0x35) + +$C$DW$1092 .dwtag DW_TAG_member + .dwattr $C$DW$1092, DW_AT_type(*$C$DW$T$571) + .dwattr $C$DW$1092, DW_AT_name("ICPR") + .dwattr $C$DW$1092, DW_AT_TI_symbol_name("ICPR") + .dwattr $C$DW$1092, DW_AT_data_member_location[DW_OP_plus_uconst 0x280] + .dwattr $C$DW$1092, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1092, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1092, DW_AT_decl_line(0xb0) + .dwattr $C$DW$1092, DW_AT_decl_column(0x32) + +$C$DW$1093 .dwtag DW_TAG_member + .dwattr $C$DW$1093, DW_AT_type(*$C$DW$T$573) + .dwattr $C$DW$1093, DW_AT_name("RES_2A0") + .dwattr $C$DW$1093, DW_AT_TI_symbol_name("RES_2A0") + .dwattr $C$DW$1093, DW_AT_data_member_location[DW_OP_plus_uconst 0x2a0] + .dwattr $C$DW$1093, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1093, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1093, DW_AT_decl_line(0xb1) + .dwattr $C$DW$1093, DW_AT_decl_column(0x35) + +$C$DW$1094 .dwtag DW_TAG_member + .dwattr $C$DW$1094, DW_AT_type(*$C$DW$T$575) + .dwattr $C$DW$1094, DW_AT_name("IABR") + .dwattr $C$DW$1094, DW_AT_TI_symbol_name("IABR") + .dwattr $C$DW$1094, DW_AT_data_member_location[DW_OP_plus_uconst 0x300] + .dwattr $C$DW$1094, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1094, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1094, DW_AT_decl_line(0xb2) + .dwattr $C$DW$1094, DW_AT_decl_column(0x32) + +$C$DW$1095 .dwtag DW_TAG_member + .dwattr $C$DW$1095, DW_AT_type(*$C$DW$T$577) + .dwattr $C$DW$1095, DW_AT_name("RES_320") + .dwattr $C$DW$1095, DW_AT_TI_symbol_name("RES_320") + .dwattr $C$DW$1095, DW_AT_data_member_location[DW_OP_plus_uconst 0x320] + .dwattr $C$DW$1095, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1095, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1095, DW_AT_decl_line(0xb3) + .dwattr $C$DW$1095, DW_AT_decl_column(0x35) + +$C$DW$1096 .dwtag DW_TAG_member + .dwattr $C$DW$1096, DW_AT_type(*$C$DW$T$583) + .dwattr $C$DW$1096, DW_AT_name("IPR") + .dwattr $C$DW$1096, DW_AT_TI_symbol_name("IPR") + .dwattr $C$DW$1096, DW_AT_data_member_location[DW_OP_plus_uconst 0x400] + .dwattr $C$DW$1096, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1096, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1096, DW_AT_decl_line(0xb4) + .dwattr $C$DW$1096, DW_AT_decl_column(0x31) + +$C$DW$1097 .dwtag DW_TAG_member + .dwattr $C$DW$1097, DW_AT_type(*$C$DW$T$586) + .dwattr $C$DW$1097, DW_AT_name("RES_4F0") + .dwattr $C$DW$1097, DW_AT_TI_symbol_name("RES_4F0") + .dwattr $C$DW$1097, DW_AT_data_member_location[DW_OP_plus_uconst 0x4f0] + .dwattr $C$DW$1097, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1097, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1097, DW_AT_decl_line(0xb5) + .dwattr $C$DW$1097, DW_AT_decl_column(0x35) + +$C$DW$1098 .dwtag DW_TAG_member + .dwattr $C$DW$1098, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1098, DW_AT_name("CPUIDBR") + .dwattr $C$DW$1098, DW_AT_TI_symbol_name("CPUIDBR") + .dwattr $C$DW$1098, DW_AT_data_member_location[DW_OP_plus_uconst 0xd00] + .dwattr $C$DW$1098, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1098, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1098, DW_AT_decl_line(0xb6) + .dwattr $C$DW$1098, DW_AT_decl_column(0x10) + +$C$DW$1099 .dwtag DW_TAG_member + .dwattr $C$DW$1099, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1099, DW_AT_name("ICSR") + .dwattr $C$DW$1099, DW_AT_TI_symbol_name("ICSR") + .dwattr $C$DW$1099, DW_AT_data_member_location[DW_OP_plus_uconst 0xd04] + .dwattr $C$DW$1099, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1099, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1099, DW_AT_decl_line(0xb7) + .dwattr $C$DW$1099, DW_AT_decl_column(0x10) + +$C$DW$1100 .dwtag DW_TAG_member + .dwattr $C$DW$1100, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1100, DW_AT_name("VTOR") + .dwattr $C$DW$1100, DW_AT_TI_symbol_name("VTOR") + .dwattr $C$DW$1100, DW_AT_data_member_location[DW_OP_plus_uconst 0xd08] + .dwattr $C$DW$1100, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1100, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1100, DW_AT_decl_line(0xb8) + .dwattr $C$DW$1100, DW_AT_decl_column(0x10) + +$C$DW$1101 .dwtag DW_TAG_member + .dwattr $C$DW$1101, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1101, DW_AT_name("AIRCR") + .dwattr $C$DW$1101, DW_AT_TI_symbol_name("AIRCR") + .dwattr $C$DW$1101, DW_AT_data_member_location[DW_OP_plus_uconst 0xd0c] + .dwattr $C$DW$1101, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1101, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1101, DW_AT_decl_line(0xb9) + .dwattr $C$DW$1101, DW_AT_decl_column(0x10) + +$C$DW$1102 .dwtag DW_TAG_member + .dwattr $C$DW$1102, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1102, DW_AT_name("SCR") + .dwattr $C$DW$1102, DW_AT_TI_symbol_name("SCR") + .dwattr $C$DW$1102, DW_AT_data_member_location[DW_OP_plus_uconst 0xd10] + .dwattr $C$DW$1102, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1102, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1102, DW_AT_decl_line(0xba) + .dwattr $C$DW$1102, DW_AT_decl_column(0x10) + +$C$DW$1103 .dwtag DW_TAG_member + .dwattr $C$DW$1103, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1103, DW_AT_name("CCR") + .dwattr $C$DW$1103, DW_AT_TI_symbol_name("CCR") + .dwattr $C$DW$1103, DW_AT_data_member_location[DW_OP_plus_uconst 0xd14] + .dwattr $C$DW$1103, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1103, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1103, DW_AT_decl_line(0xbb) + .dwattr $C$DW$1103, DW_AT_decl_column(0x10) + +$C$DW$1104 .dwtag DW_TAG_member + .dwattr $C$DW$1104, DW_AT_type(*$C$DW$T$589) + .dwattr $C$DW$1104, DW_AT_name("SHPR") + .dwattr $C$DW$1104, DW_AT_TI_symbol_name("SHPR") + .dwattr $C$DW$1104, DW_AT_data_member_location[DW_OP_plus_uconst 0xd18] + .dwattr $C$DW$1104, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1104, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1104, DW_AT_decl_line(0xbc) + .dwattr $C$DW$1104, DW_AT_decl_column(0x32) + +$C$DW$1105 .dwtag DW_TAG_member + .dwattr $C$DW$1105, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1105, DW_AT_name("SHCSR") + .dwattr $C$DW$1105, DW_AT_TI_symbol_name("SHCSR") + .dwattr $C$DW$1105, DW_AT_data_member_location[DW_OP_plus_uconst 0xd24] + .dwattr $C$DW$1105, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1105, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1105, DW_AT_decl_line(0xbd) + .dwattr $C$DW$1105, DW_AT_decl_column(0x10) + +$C$DW$1106 .dwtag DW_TAG_member + .dwattr $C$DW$1106, DW_AT_type(*$C$DW$T$580) + .dwattr $C$DW$1106, DW_AT_name("MMFSR") + .dwattr $C$DW$1106, DW_AT_TI_symbol_name("MMFSR") + .dwattr $C$DW$1106, DW_AT_data_member_location[DW_OP_plus_uconst 0xd28] + .dwattr $C$DW$1106, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1106, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1106, DW_AT_decl_line(0xbe) + .dwattr $C$DW$1106, DW_AT_decl_column(0x0f) + +$C$DW$1107 .dwtag DW_TAG_member + .dwattr $C$DW$1107, DW_AT_type(*$C$DW$T$580) + .dwattr $C$DW$1107, DW_AT_name("BFSR") + .dwattr $C$DW$1107, DW_AT_TI_symbol_name("BFSR") + .dwattr $C$DW$1107, DW_AT_data_member_location[DW_OP_plus_uconst 0xd29] + .dwattr $C$DW$1107, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1107, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1107, DW_AT_decl_line(0xbf) + .dwattr $C$DW$1107, DW_AT_decl_column(0x0f) + +$C$DW$1108 .dwtag DW_TAG_member + .dwattr $C$DW$1108, DW_AT_type(*$C$DW$T$592) + .dwattr $C$DW$1108, DW_AT_name("UFSR") + .dwattr $C$DW$1108, DW_AT_TI_symbol_name("UFSR") + .dwattr $C$DW$1108, DW_AT_data_member_location[DW_OP_plus_uconst 0xd2a] + .dwattr $C$DW$1108, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1108, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1108, DW_AT_decl_line(0xc0) + .dwattr $C$DW$1108, DW_AT_decl_column(0x10) + +$C$DW$1109 .dwtag DW_TAG_member + .dwattr $C$DW$1109, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1109, DW_AT_name("HFSR") + .dwattr $C$DW$1109, DW_AT_TI_symbol_name("HFSR") + .dwattr $C$DW$1109, DW_AT_data_member_location[DW_OP_plus_uconst 0xd2c] + .dwattr $C$DW$1109, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1109, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1109, DW_AT_decl_line(0xc1) + .dwattr $C$DW$1109, DW_AT_decl_column(0x10) + +$C$DW$1110 .dwtag DW_TAG_member + .dwattr $C$DW$1110, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1110, DW_AT_name("DFSR") + .dwattr $C$DW$1110, DW_AT_TI_symbol_name("DFSR") + .dwattr $C$DW$1110, DW_AT_data_member_location[DW_OP_plus_uconst 0xd30] + .dwattr $C$DW$1110, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1110, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1110, DW_AT_decl_line(0xc2) + .dwattr $C$DW$1110, DW_AT_decl_column(0x10) + +$C$DW$1111 .dwtag DW_TAG_member + .dwattr $C$DW$1111, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1111, DW_AT_name("MMAR") + .dwattr $C$DW$1111, DW_AT_TI_symbol_name("MMAR") + .dwattr $C$DW$1111, DW_AT_data_member_location[DW_OP_plus_uconst 0xd34] + .dwattr $C$DW$1111, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1111, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1111, DW_AT_decl_line(0xc3) + .dwattr $C$DW$1111, DW_AT_decl_column(0x10) + +$C$DW$1112 .dwtag DW_TAG_member + .dwattr $C$DW$1112, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1112, DW_AT_name("BFAR") + .dwattr $C$DW$1112, DW_AT_TI_symbol_name("BFAR") + .dwattr $C$DW$1112, DW_AT_data_member_location[DW_OP_plus_uconst 0xd38] + .dwattr $C$DW$1112, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1112, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1112, DW_AT_decl_line(0xc4) + .dwattr $C$DW$1112, DW_AT_decl_column(0x10) + +$C$DW$1113 .dwtag DW_TAG_member + .dwattr $C$DW$1113, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1113, DW_AT_name("AFSR") + .dwattr $C$DW$1113, DW_AT_TI_symbol_name("AFSR") + .dwattr $C$DW$1113, DW_AT_data_member_location[DW_OP_plus_uconst 0xd3c] + .dwattr $C$DW$1113, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1113, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1113, DW_AT_decl_line(0xc5) + .dwattr $C$DW$1113, DW_AT_decl_column(0x10) + +$C$DW$1114 .dwtag DW_TAG_member + .dwattr $C$DW$1114, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1114, DW_AT_name("PFR0") + .dwattr $C$DW$1114, DW_AT_TI_symbol_name("PFR0") + .dwattr $C$DW$1114, DW_AT_data_member_location[DW_OP_plus_uconst 0xd40] + .dwattr $C$DW$1114, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1114, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1114, DW_AT_decl_line(0xc6) + .dwattr $C$DW$1114, DW_AT_decl_column(0x10) + +$C$DW$1115 .dwtag DW_TAG_member + .dwattr $C$DW$1115, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1115, DW_AT_name("PFR1") + .dwattr $C$DW$1115, DW_AT_TI_symbol_name("PFR1") + .dwattr $C$DW$1115, DW_AT_data_member_location[DW_OP_plus_uconst 0xd44] + .dwattr $C$DW$1115, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1115, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1115, DW_AT_decl_line(0xc7) + .dwattr $C$DW$1115, DW_AT_decl_column(0x10) + +$C$DW$1116 .dwtag DW_TAG_member + .dwattr $C$DW$1116, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1116, DW_AT_name("DFR0") + .dwattr $C$DW$1116, DW_AT_TI_symbol_name("DFR0") + .dwattr $C$DW$1116, DW_AT_data_member_location[DW_OP_plus_uconst 0xd48] + .dwattr $C$DW$1116, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1116, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1116, DW_AT_decl_line(0xc8) + .dwattr $C$DW$1116, DW_AT_decl_column(0x10) + +$C$DW$1117 .dwtag DW_TAG_member + .dwattr $C$DW$1117, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1117, DW_AT_name("AFR0") + .dwattr $C$DW$1117, DW_AT_TI_symbol_name("AFR0") + .dwattr $C$DW$1117, DW_AT_data_member_location[DW_OP_plus_uconst 0xd4c] + .dwattr $C$DW$1117, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1117, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1117, DW_AT_decl_line(0xc9) + .dwattr $C$DW$1117, DW_AT_decl_column(0x10) + +$C$DW$1118 .dwtag DW_TAG_member + .dwattr $C$DW$1118, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1118, DW_AT_name("MMFR0") + .dwattr $C$DW$1118, DW_AT_TI_symbol_name("MMFR0") + .dwattr $C$DW$1118, DW_AT_data_member_location[DW_OP_plus_uconst 0xd50] + .dwattr $C$DW$1118, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1118, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1118, DW_AT_decl_line(0xca) + .dwattr $C$DW$1118, DW_AT_decl_column(0x10) + +$C$DW$1119 .dwtag DW_TAG_member + .dwattr $C$DW$1119, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1119, DW_AT_name("MMFR1") + .dwattr $C$DW$1119, DW_AT_TI_symbol_name("MMFR1") + .dwattr $C$DW$1119, DW_AT_data_member_location[DW_OP_plus_uconst 0xd54] + .dwattr $C$DW$1119, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1119, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1119, DW_AT_decl_line(0xcb) + .dwattr $C$DW$1119, DW_AT_decl_column(0x10) + +$C$DW$1120 .dwtag DW_TAG_member + .dwattr $C$DW$1120, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1120, DW_AT_name("MMFR2") + .dwattr $C$DW$1120, DW_AT_TI_symbol_name("MMFR2") + .dwattr $C$DW$1120, DW_AT_data_member_location[DW_OP_plus_uconst 0xd58] + .dwattr $C$DW$1120, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1120, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1120, DW_AT_decl_line(0xcc) + .dwattr $C$DW$1120, DW_AT_decl_column(0x10) + +$C$DW$1121 .dwtag DW_TAG_member + .dwattr $C$DW$1121, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1121, DW_AT_name("MMFR3") + .dwattr $C$DW$1121, DW_AT_TI_symbol_name("MMFR3") + .dwattr $C$DW$1121, DW_AT_data_member_location[DW_OP_plus_uconst 0xd5c] + .dwattr $C$DW$1121, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1121, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1121, DW_AT_decl_line(0xcd) + .dwattr $C$DW$1121, DW_AT_decl_column(0x10) + +$C$DW$1122 .dwtag DW_TAG_member + .dwattr $C$DW$1122, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1122, DW_AT_name("ISAR0") + .dwattr $C$DW$1122, DW_AT_TI_symbol_name("ISAR0") + .dwattr $C$DW$1122, DW_AT_data_member_location[DW_OP_plus_uconst 0xd60] + .dwattr $C$DW$1122, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1122, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1122, DW_AT_decl_line(0xce) + .dwattr $C$DW$1122, DW_AT_decl_column(0x10) + +$C$DW$1123 .dwtag DW_TAG_member + .dwattr $C$DW$1123, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1123, DW_AT_name("ISAR1") + .dwattr $C$DW$1123, DW_AT_TI_symbol_name("ISAR1") + .dwattr $C$DW$1123, DW_AT_data_member_location[DW_OP_plus_uconst 0xd64] + .dwattr $C$DW$1123, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1123, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1123, DW_AT_decl_line(0xcf) + .dwattr $C$DW$1123, DW_AT_decl_column(0x10) + +$C$DW$1124 .dwtag DW_TAG_member + .dwattr $C$DW$1124, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1124, DW_AT_name("ISAR2") + .dwattr $C$DW$1124, DW_AT_TI_symbol_name("ISAR2") + .dwattr $C$DW$1124, DW_AT_data_member_location[DW_OP_plus_uconst 0xd68] + .dwattr $C$DW$1124, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1124, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1124, DW_AT_decl_line(0xd0) + .dwattr $C$DW$1124, DW_AT_decl_column(0x10) + +$C$DW$1125 .dwtag DW_TAG_member + .dwattr $C$DW$1125, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1125, DW_AT_name("ISAR3") + .dwattr $C$DW$1125, DW_AT_TI_symbol_name("ISAR3") + .dwattr $C$DW$1125, DW_AT_data_member_location[DW_OP_plus_uconst 0xd6c] + .dwattr $C$DW$1125, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1125, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1125, DW_AT_decl_line(0xd1) + .dwattr $C$DW$1125, DW_AT_decl_column(0x10) + +$C$DW$1126 .dwtag DW_TAG_member + .dwattr $C$DW$1126, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1126, DW_AT_name("ISAR4") + .dwattr $C$DW$1126, DW_AT_TI_symbol_name("ISAR4") + .dwattr $C$DW$1126, DW_AT_data_member_location[DW_OP_plus_uconst 0xd70] + .dwattr $C$DW$1126, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1126, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1126, DW_AT_decl_line(0xd2) + .dwattr $C$DW$1126, DW_AT_decl_column(0x10) + +$C$DW$1127 .dwtag DW_TAG_member + .dwattr $C$DW$1127, DW_AT_type(*$C$DW$T$595) + .dwattr $C$DW$1127, DW_AT_name("RES_D74") + .dwattr $C$DW$1127, DW_AT_TI_symbol_name("RES_D74") + .dwattr $C$DW$1127, DW_AT_data_member_location[DW_OP_plus_uconst 0xd74] + .dwattr $C$DW$1127, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1127, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1127, DW_AT_decl_line(0xd3) + .dwattr $C$DW$1127, DW_AT_decl_column(0x35) + +$C$DW$1128 .dwtag DW_TAG_member + .dwattr $C$DW$1128, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1128, DW_AT_name("CPACR") + .dwattr $C$DW$1128, DW_AT_TI_symbol_name("CPACR") + .dwattr $C$DW$1128, DW_AT_data_member_location[DW_OP_plus_uconst 0xd88] + .dwattr $C$DW$1128, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1128, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1128, DW_AT_decl_line(0xd4) + .dwattr $C$DW$1128, DW_AT_decl_column(0x10) + +$C$DW$1129 .dwtag DW_TAG_member + .dwattr $C$DW$1129, DW_AT_type(*$C$DW$T$598) + .dwattr $C$DW$1129, DW_AT_name("RES_D8C") + .dwattr $C$DW$1129, DW_AT_TI_symbol_name("RES_D8C") + .dwattr $C$DW$1129, DW_AT_data_member_location[DW_OP_plus_uconst 0xd8c] + .dwattr $C$DW$1129, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1129, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1129, DW_AT_decl_line(0xd5) + .dwattr $C$DW$1129, DW_AT_decl_column(0x35) + +$C$DW$1130 .dwtag DW_TAG_member + .dwattr $C$DW$1130, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1130, DW_AT_name("STI") + .dwattr $C$DW$1130, DW_AT_TI_symbol_name("STI") + .dwattr $C$DW$1130, DW_AT_data_member_location[DW_OP_plus_uconst 0xf00] + .dwattr $C$DW$1130, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1130, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1130, DW_AT_decl_line(0xd6) + .dwattr $C$DW$1130, DW_AT_decl_column(0x10) + +$C$DW$1131 .dwtag DW_TAG_member + .dwattr $C$DW$1131, DW_AT_type(*$C$DW$T$601) + .dwattr $C$DW$1131, DW_AT_name("RES_F04") + .dwattr $C$DW$1131, DW_AT_TI_symbol_name("RES_F04") + .dwattr $C$DW$1131, DW_AT_data_member_location[DW_OP_plus_uconst 0xf04] + .dwattr $C$DW$1131, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1131, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1131, DW_AT_decl_line(0xd7) + .dwattr $C$DW$1131, DW_AT_decl_column(0x35) + +$C$DW$1132 .dwtag DW_TAG_member + .dwattr $C$DW$1132, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1132, DW_AT_name("FPCCR") + .dwattr $C$DW$1132, DW_AT_TI_symbol_name("FPCCR") + .dwattr $C$DW$1132, DW_AT_data_member_location[DW_OP_plus_uconst 0xf34] + .dwattr $C$DW$1132, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1132, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1132, DW_AT_decl_line(0xd8) + .dwattr $C$DW$1132, DW_AT_decl_column(0x10) + +$C$DW$1133 .dwtag DW_TAG_member + .dwattr $C$DW$1133, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1133, DW_AT_name("FPCAR") + .dwattr $C$DW$1133, DW_AT_TI_symbol_name("FPCAR") + .dwattr $C$DW$1133, DW_AT_data_member_location[DW_OP_plus_uconst 0xf38] + .dwattr $C$DW$1133, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1133, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1133, DW_AT_decl_line(0xd9) + .dwattr $C$DW$1133, DW_AT_decl_column(0x10) + +$C$DW$1134 .dwtag DW_TAG_member + .dwattr $C$DW$1134, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1134, DW_AT_name("FPDSCR") + .dwattr $C$DW$1134, DW_AT_TI_symbol_name("FPDSCR") + .dwattr $C$DW$1134, DW_AT_data_member_location[DW_OP_plus_uconst 0xf3c] + .dwattr $C$DW$1134, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1134, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1134, DW_AT_decl_line(0xda) + .dwattr $C$DW$1134, DW_AT_decl_column(0x10) + +$C$DW$1135 .dwtag DW_TAG_member + .dwattr $C$DW$1135, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1135, DW_AT_name("MVFR0") + .dwattr $C$DW$1135, DW_AT_TI_symbol_name("MVFR0") + .dwattr $C$DW$1135, DW_AT_data_member_location[DW_OP_plus_uconst 0xf40] + .dwattr $C$DW$1135, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1135, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1135, DW_AT_decl_line(0xdb) + .dwattr $C$DW$1135, DW_AT_decl_column(0x10) + +$C$DW$1136 .dwtag DW_TAG_member + .dwattr $C$DW$1136, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1136, DW_AT_name("MVFR1") + .dwattr $C$DW$1136, DW_AT_TI_symbol_name("MVFR1") + .dwattr $C$DW$1136, DW_AT_data_member_location[DW_OP_plus_uconst 0xf44] + .dwattr $C$DW$1136, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1136, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1136, DW_AT_decl_line(0xdc) + .dwattr $C$DW$1136, DW_AT_decl_column(0x10) + +$C$DW$1137 .dwtag DW_TAG_member + .dwattr $C$DW$1137, DW_AT_type(*$C$DW$T$604) + .dwattr $C$DW$1137, DW_AT_name("RES_F48") + .dwattr $C$DW$1137, DW_AT_TI_symbol_name("RES_F48") + .dwattr $C$DW$1137, DW_AT_data_member_location[DW_OP_plus_uconst 0xf48] + .dwattr $C$DW$1137, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1137, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1137, DW_AT_decl_line(0xdd) + .dwattr $C$DW$1137, DW_AT_decl_column(0x35) + +$C$DW$1138 .dwtag DW_TAG_member + .dwattr $C$DW$1138, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1138, DW_AT_name("PID4") + .dwattr $C$DW$1138, DW_AT_TI_symbol_name("PID4") + .dwattr $C$DW$1138, DW_AT_data_member_location[DW_OP_plus_uconst 0xfd0] + .dwattr $C$DW$1138, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1138, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1138, DW_AT_decl_line(0xde) + .dwattr $C$DW$1138, DW_AT_decl_column(0x10) + +$C$DW$1139 .dwtag DW_TAG_member + .dwattr $C$DW$1139, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1139, DW_AT_name("PID5") + .dwattr $C$DW$1139, DW_AT_TI_symbol_name("PID5") + .dwattr $C$DW$1139, DW_AT_data_member_location[DW_OP_plus_uconst 0xfd4] + .dwattr $C$DW$1139, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1139, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1139, DW_AT_decl_line(0xdf) + .dwattr $C$DW$1139, DW_AT_decl_column(0x10) + +$C$DW$1140 .dwtag DW_TAG_member + .dwattr $C$DW$1140, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1140, DW_AT_name("PID6") + .dwattr $C$DW$1140, DW_AT_TI_symbol_name("PID6") + .dwattr $C$DW$1140, DW_AT_data_member_location[DW_OP_plus_uconst 0xfd8] + .dwattr $C$DW$1140, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1140, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1140, DW_AT_decl_line(0xe0) + .dwattr $C$DW$1140, DW_AT_decl_column(0x10) + +$C$DW$1141 .dwtag DW_TAG_member + .dwattr $C$DW$1141, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1141, DW_AT_name("PID7") + .dwattr $C$DW$1141, DW_AT_TI_symbol_name("PID7") + .dwattr $C$DW$1141, DW_AT_data_member_location[DW_OP_plus_uconst 0xfdc] + .dwattr $C$DW$1141, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1141, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1141, DW_AT_decl_line(0xe1) + .dwattr $C$DW$1141, DW_AT_decl_column(0x10) + +$C$DW$1142 .dwtag DW_TAG_member + .dwattr $C$DW$1142, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1142, DW_AT_name("PID0") + .dwattr $C$DW$1142, DW_AT_TI_symbol_name("PID0") + .dwattr $C$DW$1142, DW_AT_data_member_location[DW_OP_plus_uconst 0xfe0] + .dwattr $C$DW$1142, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1142, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1142, DW_AT_decl_line(0xe2) + .dwattr $C$DW$1142, DW_AT_decl_column(0x10) + +$C$DW$1143 .dwtag DW_TAG_member + .dwattr $C$DW$1143, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1143, DW_AT_name("PID1") + .dwattr $C$DW$1143, DW_AT_TI_symbol_name("PID1") + .dwattr $C$DW$1143, DW_AT_data_member_location[DW_OP_plus_uconst 0xfe4] + .dwattr $C$DW$1143, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1143, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1143, DW_AT_decl_line(0xe3) + .dwattr $C$DW$1143, DW_AT_decl_column(0x10) + +$C$DW$1144 .dwtag DW_TAG_member + .dwattr $C$DW$1144, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1144, DW_AT_name("PID2") + .dwattr $C$DW$1144, DW_AT_TI_symbol_name("PID2") + .dwattr $C$DW$1144, DW_AT_data_member_location[DW_OP_plus_uconst 0xfe8] + .dwattr $C$DW$1144, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1144, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1144, DW_AT_decl_line(0xe4) + .dwattr $C$DW$1144, DW_AT_decl_column(0x10) + +$C$DW$1145 .dwtag DW_TAG_member + .dwattr $C$DW$1145, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1145, DW_AT_name("PID3") + .dwattr $C$DW$1145, DW_AT_TI_symbol_name("PID3") + .dwattr $C$DW$1145, DW_AT_data_member_location[DW_OP_plus_uconst 0xfec] + .dwattr $C$DW$1145, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1145, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1145, DW_AT_decl_line(0xe5) + .dwattr $C$DW$1145, DW_AT_decl_column(0x10) + +$C$DW$1146 .dwtag DW_TAG_member + .dwattr $C$DW$1146, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1146, DW_AT_name("CID0") + .dwattr $C$DW$1146, DW_AT_TI_symbol_name("CID0") + .dwattr $C$DW$1146, DW_AT_data_member_location[DW_OP_plus_uconst 0xff0] + .dwattr $C$DW$1146, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1146, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1146, DW_AT_decl_line(0xe6) + .dwattr $C$DW$1146, DW_AT_decl_column(0x10) + +$C$DW$1147 .dwtag DW_TAG_member + .dwattr $C$DW$1147, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1147, DW_AT_name("CID1") + .dwattr $C$DW$1147, DW_AT_TI_symbol_name("CID1") + .dwattr $C$DW$1147, DW_AT_data_member_location[DW_OP_plus_uconst 0xff4] + .dwattr $C$DW$1147, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1147, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1147, DW_AT_decl_line(0xe7) + .dwattr $C$DW$1147, DW_AT_decl_column(0x10) + +$C$DW$1148 .dwtag DW_TAG_member + .dwattr $C$DW$1148, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1148, DW_AT_name("CID2") + .dwattr $C$DW$1148, DW_AT_TI_symbol_name("CID2") + .dwattr $C$DW$1148, DW_AT_data_member_location[DW_OP_plus_uconst 0xff8] + .dwattr $C$DW$1148, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1148, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1148, DW_AT_decl_line(0xe8) + .dwattr $C$DW$1148, DW_AT_decl_column(0x10) + +$C$DW$1149 .dwtag DW_TAG_member + .dwattr $C$DW$1149, DW_AT_type(*$C$DW$T$552) + .dwattr $C$DW$1149, DW_AT_name("CID3") + .dwattr $C$DW$1149, DW_AT_TI_symbol_name("CID3") + .dwattr $C$DW$1149, DW_AT_data_member_location[DW_OP_plus_uconst 0xffc] + .dwattr $C$DW$1149, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1149, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1149, DW_AT_decl_line(0xe9) + .dwattr $C$DW$1149, DW_AT_decl_column(0x10) + + .dwattr $C$DW$T$605, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$605, DW_AT_decl_line(0xa0) + .dwattr $C$DW$T$605, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$605 + +$C$DW$T$2045 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2045, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_NVIC") + .dwattr $C$DW$T$2045, DW_AT_type(*$C$DW$T$605) + .dwattr $C$DW$T$2045, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2045, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$2045, DW_AT_decl_line(0x16) + .dwattr $C$DW$T$2045, DW_AT_decl_column(0x32) + + +$C$DW$T$23 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$23, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Object") + .dwattr $C$DW$T$23, DW_AT_declaration + .dwattr $C$DW$T$23, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$23, DW_AT_decl_line(0x1c) + .dwattr $C$DW$T$23, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$23 + +$C$DW$T$534 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$534, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Object") + .dwattr $C$DW$T$534, DW_AT_type(*$C$DW$T$23) + .dwattr $C$DW$T$534, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$534, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$534, DW_AT_decl_line(0x1c) + .dwattr $C$DW$T$534, DW_AT_decl_column(0x34) + +$C$DW$T$535 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$535, DW_AT_type(*$C$DW$T$534) + .dwattr $C$DW$T$535, DW_AT_address_class(0x20) + +$C$DW$T$536 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$536, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Handle") + .dwattr $C$DW$T$536, DW_AT_type(*$C$DW$T$535) + .dwattr $C$DW$T$536, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$536, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$536, DW_AT_decl_line(0x1e) + .dwattr $C$DW$T$536, DW_AT_decl_column(0x2e) + +$C$DW$T$2046 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2046, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Instance") + .dwattr $C$DW$T$2046, DW_AT_type(*$C$DW$T$535) + .dwattr $C$DW$T$2046, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2046, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$2046, DW_AT_decl_line(0x20) + .dwattr $C$DW$T$2046, DW_AT_decl_column(0x2e) + + +$C$DW$T$24 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$24, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Object__") + .dwattr $C$DW$T$24, DW_AT_declaration + .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$24, DW_AT_decl_line(0x1f) + .dwattr $C$DW$T$24, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$24 + +$C$DW$T$2047 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2047, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Instance_State") + .dwattr $C$DW$T$2047, DW_AT_type(*$C$DW$T$24) + .dwattr $C$DW$T$2047, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2047, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$2047, DW_AT_decl_line(0x1f) + .dwattr $C$DW$T$2047, DW_AT_decl_column(0x36) + + +$C$DW$T$608 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$608, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Params") + .dwattr $C$DW$T$608, DW_AT_byte_size(0x30) +$C$DW$1150 .dwtag DW_TAG_member + .dwattr $C$DW$1150, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$1150, DW_AT_name("__size") + .dwattr $C$DW$1150, DW_AT_TI_symbol_name("__size") + .dwattr $C$DW$1150, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1150, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1150, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1150, DW_AT_decl_line(0x27f) + .dwattr $C$DW$1150, DW_AT_decl_column(0x0c) + +$C$DW$1151 .dwtag DW_TAG_member + .dwattr $C$DW$1151, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$1151, DW_AT_name("__self") + .dwattr $C$DW$1151, DW_AT_TI_symbol_name("__self") + .dwattr $C$DW$1151, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1151, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1151, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1151, DW_AT_decl_line(0x280) + .dwattr $C$DW$1151, DW_AT_decl_column(0x11) + +$C$DW$1152 .dwtag DW_TAG_member + .dwattr $C$DW$1152, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$1152, DW_AT_name("__fxns") + .dwattr $C$DW$1152, DW_AT_TI_symbol_name("__fxns") + .dwattr $C$DW$1152, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1152, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1152, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1152, DW_AT_decl_line(0x281) + .dwattr $C$DW$1152, DW_AT_decl_column(0x0b) + +$C$DW$1153 .dwtag DW_TAG_member + .dwattr $C$DW$1153, DW_AT_type(*$C$DW$T$491) + .dwattr $C$DW$1153, DW_AT_name("instance") + .dwattr $C$DW$1153, DW_AT_TI_symbol_name("instance") + .dwattr $C$DW$1153, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1153, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1153, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1153, DW_AT_decl_line(0x282) + .dwattr $C$DW$1153, DW_AT_decl_column(0x23) + +$C$DW$1154 .dwtag DW_TAG_member + .dwattr $C$DW$1154, DW_AT_type(*$C$DW$T$607) + .dwattr $C$DW$1154, DW_AT_name("maskSetting") + .dwattr $C$DW$1154, DW_AT_TI_symbol_name("maskSetting") + .dwattr $C$DW$1154, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1154, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1154, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1154, DW_AT_decl_line(0x283) + .dwattr $C$DW$1154, DW_AT_decl_column(0x2e) + +$C$DW$1155 .dwtag DW_TAG_member + .dwattr $C$DW$1155, DW_AT_type(*$C$DW$T$501) + .dwattr $C$DW$1155, DW_AT_name("arg") + .dwattr $C$DW$1155, DW_AT_TI_symbol_name("arg") + .dwattr $C$DW$1155, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1155, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1155, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1155, DW_AT_decl_line(0x284) + .dwattr $C$DW$1155, DW_AT_decl_column(0x0e) + +$C$DW$1156 .dwtag DW_TAG_member + .dwattr $C$DW$1156, DW_AT_type(*$C$DW$T$479) + .dwattr $C$DW$1156, DW_AT_name("enableInt") + .dwattr $C$DW$1156, DW_AT_TI_symbol_name("enableInt") + .dwattr $C$DW$1156, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$1156, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1156, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1156, DW_AT_decl_line(0x285) + .dwattr $C$DW$1156, DW_AT_decl_column(0x0e) + +$C$DW$1157 .dwtag DW_TAG_member + .dwattr $C$DW$1157, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$1157, DW_AT_name("eventId") + .dwattr $C$DW$1157, DW_AT_TI_symbol_name("eventId") + .dwattr $C$DW$1157, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1157, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1157, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1157, DW_AT_decl_line(0x286) + .dwattr $C$DW$1157, DW_AT_decl_column(0x0d) + +$C$DW$1158 .dwtag DW_TAG_member + .dwattr $C$DW$1158, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$1158, DW_AT_name("priority") + .dwattr $C$DW$1158, DW_AT_TI_symbol_name("priority") + .dwattr $C$DW$1158, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1158, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1158, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1158, DW_AT_decl_line(0x287) + .dwattr $C$DW$1158, DW_AT_decl_column(0x0d) + +$C$DW$1159 .dwtag DW_TAG_member + .dwattr $C$DW$1159, DW_AT_type(*$C$DW$T$479) + .dwattr $C$DW$1159, DW_AT_name("useDispatcher") + .dwattr $C$DW$1159, DW_AT_TI_symbol_name("useDispatcher") + .dwattr $C$DW$1159, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$1159, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1159, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1159, DW_AT_decl_line(0x288) + .dwattr $C$DW$1159, DW_AT_decl_column(0x0e) + +$C$DW$1160 .dwtag DW_TAG_member + .dwattr $C$DW$1160, DW_AT_type(*$C$DW$T$490) + .dwattr $C$DW$1160, DW_AT_name("__iprms") + .dwattr $C$DW$1160, DW_AT_TI_symbol_name("__iprms") + .dwattr $C$DW$1160, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$1160, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1160, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1160, DW_AT_decl_line(0x289) + .dwattr $C$DW$1160, DW_AT_decl_column(0x22) + + .dwattr $C$DW$T$608, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$T$608, DW_AT_decl_line(0x27e) + .dwattr $C$DW$T$608, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$608 + +$C$DW$T$1219 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$1219, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Params") + .dwattr $C$DW$T$1219, DW_AT_type(*$C$DW$T$608) + .dwattr $C$DW$T$1219, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$1219, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h") + .dwattr $C$DW$T$1219, DW_AT_decl_line(0x1b) + .dwattr $C$DW$T$1219, DW_AT_decl_column(0x34) + +$C$DW$T$1226 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1226, DW_AT_type(*$C$DW$T$1219) + .dwattr $C$DW$T$1226, DW_AT_address_class(0x20) + +$C$DW$T$1220 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$1220, DW_AT_type(*$C$DW$T$1219) + +$C$DW$T$1221 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$1221, DW_AT_type(*$C$DW$T$1220) + .dwattr $C$DW$T$1221, DW_AT_address_class(0x20) + + +$C$DW$T$621 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$621, DW_AT_name("ti_sysbios_family_arm_m3_Hwi_Struct") + .dwattr $C$DW$T$621, DW_AT_byte_size(0x1c) +$C$DW$1161 .dwtag DW_TAG_member + .dwattr $C$DW$1161, DW_AT_type(*$C$DW$T$611) + .dwattr $C$DW$1161, DW_AT_name("__fxns") + .dwattr $C$DW$1161, DW_AT_TI_symbol_name("__fxns") + .dwattr $C$DW$1161, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1161, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1161, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h") + .dwattr $C$DW$1161, DW_AT_decl_line(0x28e) + .dwattr $C$DW$1161, DW_AT_decl_column(0x30) + +$C$DW$1162 .dwtag DW_TAG_member + .dwattr $C$DW$1162, DW_AT_type(*$C$DW$T$501) + .dwattr $C$DW$1162, DW_AT_name("__f0") + .dwattr $C$DW$1162, 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DW_AT_name("ti_sysbios_knl_Event_Instance") + .dwattr $C$DW$T$2148, DW_AT_type(*$C$DW$T$748) + .dwattr $C$DW$T$2148, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2148, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2148, DW_AT_decl_line(0x2e) + .dwattr $C$DW$T$2148, DW_AT_decl_column(0x26) + + +$C$DW$T$49 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$49, DW_AT_name("ti_sysbios_knl_Event_Object__") + .dwattr $C$DW$T$49, DW_AT_declaration + .dwattr $C$DW$T$49, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$49, DW_AT_decl_line(0x2d) + .dwattr $C$DW$T$49, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$49 + +$C$DW$T$2149 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2149, DW_AT_name("ti_sysbios_knl_Event_Instance_State") + .dwattr $C$DW$T$2149, DW_AT_type(*$C$DW$T$49) + .dwattr $C$DW$T$2149, DW_AT_language(DW_LANG_C) + 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DW_AT_decl_line(0x13d) + .dwattr $C$DW$1333, DW_AT_decl_column(0x22) + + .dwattr $C$DW$T$733, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event.h") + .dwattr $C$DW$T$733, DW_AT_decl_line(0x138) + .dwattr $C$DW$T$733, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$733 + +$C$DW$T$2150 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2150, DW_AT_name("ti_sysbios_knl_Event_Params") + .dwattr $C$DW$T$2150, DW_AT_type(*$C$DW$T$733) + .dwattr $C$DW$T$2150, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2150, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2150, DW_AT_decl_line(0x29) + .dwattr $C$DW$T$2150, DW_AT_decl_column(0x2c) + + +$C$DW$T$737 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$737, DW_AT_name("ti_sysbios_knl_Event_PendElem") + .dwattr $C$DW$T$737, DW_AT_byte_size(0x20) +$C$DW$1334 .dwtag DW_TAG_member + .dwattr $C$DW$1334, DW_AT_type(*$C$DW$T$734) + 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DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1343, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1343, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event.h") + .dwattr $C$DW$1343, DW_AT_decl_line(0x142) + .dwattr $C$DW$1343, DW_AT_decl_column(0x17) + +$C$DW$1344 .dwtag DW_TAG_member + .dwattr $C$DW$1344, DW_AT_type(*$C$DW$T$739) + .dwattr $C$DW$1344, DW_AT_name("__f1") + .dwattr $C$DW$1344, DW_AT_TI_symbol_name("__f1") + .dwattr $C$DW$1344, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1344, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1344, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event.h") + .dwattr $C$DW$1344, DW_AT_decl_line(0x143) + .dwattr $C$DW$1344, DW_AT_decl_column(0x21) + +$C$DW$1345 .dwtag DW_TAG_member + .dwattr $C$DW$1345, DW_AT_type(*$C$DW$T$498) + .dwattr $C$DW$1345, DW_AT_name("__name") + .dwattr $C$DW$1345, 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DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1346, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1346, DW_AT_decl_line(0x43) + .dwattr $C$DW$1346, DW_AT_decl_column(0x29) + +$C$DW$1347 .dwtag DW_TAG_member + .dwattr $C$DW$1347, DW_AT_type(*$C$DW$T$742) + .dwattr $C$DW$1347, DW_AT_name("prev") + .dwattr $C$DW$1347, DW_AT_TI_symbol_name("prev") + .dwattr $C$DW$1347, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1347, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1347, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1347, DW_AT_decl_line(0x44) + .dwattr $C$DW$1347, DW_AT_decl_column(0x29) + + .dwattr $C$DW$T$743, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$T$743, DW_AT_decl_line(0x42) + .dwattr $C$DW$T$743, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$743 + +$C$DW$T$703 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$703, DW_AT_name("ti_sysbios_knl_Queue_Elem") + .dwattr $C$DW$T$703, DW_AT_type(*$C$DW$T$743) + .dwattr $C$DW$T$703, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$703, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$703, DW_AT_decl_line(0x40) + .dwattr $C$DW$T$703, DW_AT_decl_column(0x2a) + +$C$DW$T$741 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$741, DW_AT_type(*$C$DW$T$703) + .dwattr $C$DW$T$741, DW_AT_address_class(0x20) + +$C$DW$T$742 .dwtag DW_TAG_volatile_type + .dwattr $C$DW$T$742, DW_AT_type(*$C$DW$T$741) + + +$C$DW$T$57 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$57, DW_AT_name("ti_sysbios_knl_Queue_Object") + .dwattr $C$DW$T$57, DW_AT_declaration + .dwattr $C$DW$T$57, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$57, DW_AT_decl_line(0x42) + .dwattr $C$DW$T$57, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$57 + +$C$DW$T$771 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$771, DW_AT_name("ti_sysbios_knl_Queue_Object") + .dwattr $C$DW$T$771, DW_AT_type(*$C$DW$T$57) + .dwattr $C$DW$T$771, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$771, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$771, DW_AT_decl_line(0x42) + .dwattr $C$DW$T$771, DW_AT_decl_column(0x2c) + +$C$DW$T$772 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$772, DW_AT_type(*$C$DW$T$771) + .dwattr $C$DW$T$772, DW_AT_address_class(0x20) + +$C$DW$T$773 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$773, DW_AT_name("ti_sysbios_knl_Queue_Handle") + .dwattr $C$DW$T$773, DW_AT_type(*$C$DW$T$772) + .dwattr $C$DW$T$773, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$773, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$773, DW_AT_decl_line(0x44) + .dwattr $C$DW$T$773, DW_AT_decl_column(0x26) + +$C$DW$T$2169 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2169, DW_AT_name("__T1_ti_sysbios_knl_Task_Module_State__smpReadyQ") + .dwattr $C$DW$T$2169, DW_AT_type(*$C$DW$T$773) + .dwattr $C$DW$T$2169, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2169, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2169, DW_AT_decl_line(0xa0) + .dwattr $C$DW$T$2169, DW_AT_decl_column(0x25) + +$C$DW$T$2170 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2170, DW_AT_type(*$C$DW$T$773) + .dwattr $C$DW$T$2170, DW_AT_address_class(0x20) + +$C$DW$T$2171 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2171, DW_AT_name("__ARRAY1_ti_sysbios_knl_Task_Module_State__smpReadyQ") + .dwattr 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2173, DW_AT_decl_line(0x46) + .dwattr $C$DW$T$2173, DW_AT_decl_column(0x26) + + +$C$DW$T$58 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$58, DW_AT_name("ti_sysbios_knl_Queue_Object__") + .dwattr $C$DW$T$58, DW_AT_declaration + .dwattr $C$DW$T$58, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$58, DW_AT_decl_line(0x45) + .dwattr $C$DW$T$58, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$58 + +$C$DW$T$2174 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2174, DW_AT_name("ti_sysbios_knl_Queue_Instance_State") + .dwattr $C$DW$T$2174, DW_AT_type(*$C$DW$T$58) + .dwattr $C$DW$T$2174, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2174, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2174, DW_AT_decl_line(0x45) + .dwattr $C$DW$T$2174, DW_AT_decl_column(0x2e) + +$C$DW$T$2175 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2175, DW_AT_name("__T1_ti_sysbios_knl_Swi_Module_State__readyQ") + .dwattr $C$DW$T$2175, DW_AT_type(*$C$DW$T$2174) + .dwattr $C$DW$T$2175, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2175, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$2175, DW_AT_decl_line(0x69) + .dwattr $C$DW$T$2175, DW_AT_decl_column(0x2d) + +$C$DW$T$2176 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2176, DW_AT_name("__T1_ti_sysbios_knl_Task_Module_State__readyQ") + .dwattr $C$DW$T$2176, DW_AT_type(*$C$DW$T$2174) + .dwattr $C$DW$T$2176, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2176, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2176, DW_AT_decl_line(0x94) + .dwattr $C$DW$T$2176, DW_AT_decl_column(0x2d) + +$C$DW$T$2177 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2177, DW_AT_type(*$C$DW$T$2174) + .dwattr $C$DW$T$2177, DW_AT_address_class(0x20) + +$C$DW$T$2178 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2178, DW_AT_name("__ARRAY1_ti_sysbios_knl_Swi_Module_State__readyQ") + .dwattr $C$DW$T$2178, DW_AT_type(*$C$DW$T$2177) + .dwattr $C$DW$T$2178, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2178, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$2178, DW_AT_decl_line(0x6a) + .dwattr $C$DW$T$2178, DW_AT_decl_column(0x2e) + +$C$DW$T$2179 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2179, DW_AT_name("__TA_ti_sysbios_knl_Swi_Module_State__readyQ") + .dwattr $C$DW$T$2179, DW_AT_type(*$C$DW$T$2178) + .dwattr $C$DW$T$2179, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2179, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$2179, DW_AT_decl_line(0x6b) + .dwattr $C$DW$T$2179, DW_AT_decl_column(0x3a) + +$C$DW$T$2180 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2180, DW_AT_name("__ARRAY1_ti_sysbios_knl_Task_Module_State__readyQ") + .dwattr $C$DW$T$2180, DW_AT_type(*$C$DW$T$2177) + .dwattr $C$DW$T$2180, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2180, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2180, DW_AT_decl_line(0x95) + .dwattr $C$DW$T$2180, DW_AT_decl_column(0x2e) + +$C$DW$T$2181 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2181, DW_AT_name("__TA_ti_sysbios_knl_Task_Module_State__readyQ") + .dwattr $C$DW$T$2181, DW_AT_type(*$C$DW$T$2180) + .dwattr $C$DW$T$2181, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2181, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2181, DW_AT_decl_line(0x96) + .dwattr $C$DW$T$2181, DW_AT_decl_column(0x3b) + + +$C$DW$T$744 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$744, DW_AT_name("ti_sysbios_knl_Queue_Params") + .dwattr $C$DW$T$744, DW_AT_byte_size(0x18) +$C$DW$1348 .dwtag DW_TAG_member + .dwattr $C$DW$1348, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$1348, DW_AT_name("__size") + .dwattr $C$DW$1348, DW_AT_TI_symbol_name("__size") + .dwattr $C$DW$1348, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1348, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1348, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1348, DW_AT_decl_line(0xa0) + .dwattr $C$DW$1348, DW_AT_decl_column(0x0c) + +$C$DW$1349 .dwtag DW_TAG_member + .dwattr $C$DW$1349, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$1349, DW_AT_name("__self") + .dwattr $C$DW$1349, DW_AT_TI_symbol_name("__self") + .dwattr $C$DW$1349, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1349, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1349, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1349, DW_AT_decl_line(0xa1) + .dwattr $C$DW$1349, DW_AT_decl_column(0x11) + +$C$DW$1350 .dwtag DW_TAG_member + .dwattr $C$DW$1350, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$1350, DW_AT_name("__fxns") + .dwattr $C$DW$1350, DW_AT_TI_symbol_name("__fxns") + .dwattr $C$DW$1350, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1350, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1350, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1350, DW_AT_decl_line(0xa2) + .dwattr $C$DW$1350, DW_AT_decl_column(0x0b) + +$C$DW$1351 .dwtag DW_TAG_member + .dwattr $C$DW$1351, DW_AT_type(*$C$DW$T$491) + .dwattr $C$DW$1351, DW_AT_name("instance") + .dwattr $C$DW$1351, DW_AT_TI_symbol_name("instance") + .dwattr $C$DW$1351, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1351, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1351, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1351, DW_AT_decl_line(0xa3) + .dwattr $C$DW$1351, DW_AT_decl_column(0x23) + +$C$DW$1352 .dwtag DW_TAG_member + .dwattr $C$DW$1352, DW_AT_type(*$C$DW$T$490) + .dwattr $C$DW$1352, DW_AT_name("__iprms") + .dwattr $C$DW$1352, DW_AT_TI_symbol_name("__iprms") + .dwattr $C$DW$1352, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1352, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1352, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1352, DW_AT_decl_line(0xa4) + .dwattr $C$DW$1352, DW_AT_decl_column(0x22) + + .dwattr $C$DW$T$744, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$T$744, DW_AT_decl_line(0x9f) + .dwattr $C$DW$T$744, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$744 + +$C$DW$T$2182 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2182, DW_AT_name("ti_sysbios_knl_Queue_Params") + .dwattr $C$DW$T$2182, DW_AT_type(*$C$DW$T$744) + .dwattr $C$DW$T$2182, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2182, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2182, DW_AT_decl_line(0x41) + .dwattr $C$DW$T$2182, DW_AT_decl_column(0x2c) + + +$C$DW$T$745 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$745, DW_AT_name("ti_sysbios_knl_Queue_Struct") + .dwattr $C$DW$T$745, DW_AT_byte_size(0x0c) +$C$DW$1353 .dwtag DW_TAG_member + .dwattr $C$DW$1353, DW_AT_type(*$C$DW$T$703) + .dwattr $C$DW$1353, DW_AT_name("__f0") + .dwattr $C$DW$1353, DW_AT_TI_symbol_name("__f0") + .dwattr $C$DW$1353, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1353, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1353, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1353, DW_AT_decl_line(0xa9) + .dwattr $C$DW$1353, DW_AT_decl_column(0x1f) + +$C$DW$1354 .dwtag DW_TAG_member + .dwattr $C$DW$1354, DW_AT_type(*$C$DW$T$498) + .dwattr $C$DW$1354, DW_AT_name("__name") + .dwattr $C$DW$1354, DW_AT_TI_symbol_name("__name") + .dwattr $C$DW$1354, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1354, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1354, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$1354, DW_AT_decl_line(0xaa) + .dwattr $C$DW$1354, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$745, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h") + .dwattr $C$DW$T$745, DW_AT_decl_line(0xa8) + .dwattr $C$DW$T$745, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$745 + +$C$DW$T$739 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$739, DW_AT_name("ti_sysbios_knl_Queue_Struct") + .dwattr $C$DW$T$739, DW_AT_type(*$C$DW$T$745) + .dwattr $C$DW$T$739, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$739, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$739, DW_AT_decl_line(0x43) + .dwattr $C$DW$T$739, DW_AT_decl_column(0x2c) + + +$C$DW$T$746 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$746, DW_AT_name("ti_sysbios_knl_Semaphore_Args__create") + .dwattr $C$DW$T$746, DW_AT_byte_size(0x04) +$C$DW$1355 .dwtag DW_TAG_member + .dwattr $C$DW$1355, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$1355, DW_AT_name("count") + .dwattr $C$DW$1355, DW_AT_TI_symbol_name("count") + .dwattr $C$DW$1355, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1355, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1355, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1355, DW_AT_decl_line(0x59) + .dwattr $C$DW$1355, DW_AT_decl_column(0x0d) + + .dwattr $C$DW$T$746, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$T$746, DW_AT_decl_line(0x58) + .dwattr $C$DW$T$746, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$746 + +$C$DW$T$2183 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2183, DW_AT_name("ti_sysbios_knl_Semaphore_Args__create") + .dwattr $C$DW$T$2183, DW_AT_type(*$C$DW$T$746) + .dwattr $C$DW$T$2183, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2183, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$T$2183, DW_AT_decl_line(0x5a) + .dwattr $C$DW$T$2183, DW_AT_decl_column(0x03) + + +$C$DW$T$750 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$750, DW_AT_name("ti_sysbios_knl_Semaphore_Mode") + .dwattr $C$DW$T$750, DW_AT_byte_size(0x01) +$C$DW$1356 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1356, DW_AT_name("ti_sysbios_knl_Semaphore_Mode_COUNTING") + .dwattr $C$DW$1356, DW_AT_const_value(0x00) + .dwattr $C$DW$1356, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1356, DW_AT_decl_line(0x4b) + .dwattr $C$DW$1356, DW_AT_decl_column(0x05) + +$C$DW$1357 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1357, DW_AT_name("ti_sysbios_knl_Semaphore_Mode_BINARY") + .dwattr $C$DW$1357, DW_AT_const_value(0x01) + .dwattr $C$DW$1357, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1357, DW_AT_decl_line(0x4c) + .dwattr $C$DW$1357, DW_AT_decl_column(0x05) + +$C$DW$1358 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1358, DW_AT_name("ti_sysbios_knl_Semaphore_Mode_COUNTING_PRIORITY") + .dwattr $C$DW$1358, DW_AT_const_value(0x02) + .dwattr $C$DW$1358, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1358, DW_AT_decl_line(0x4d) + .dwattr $C$DW$1358, DW_AT_decl_column(0x05) + +$C$DW$1359 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1359, DW_AT_name("ti_sysbios_knl_Semaphore_Mode_BINARY_PRIORITY") + .dwattr $C$DW$1359, DW_AT_const_value(0x03) + .dwattr $C$DW$1359, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1359, DW_AT_decl_line(0x4e) + .dwattr $C$DW$1359, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$750, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$T$750, DW_AT_decl_line(0x4a) + .dwattr $C$DW$T$750, DW_AT_decl_column(0x06) + .dwendtag $C$DW$T$750 + +$C$DW$T$751 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$751, DW_AT_name("ti_sysbios_knl_Semaphore_Mode") + .dwattr $C$DW$T$751, DW_AT_type(*$C$DW$T$750) + .dwattr $C$DW$T$751, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$751, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$T$751, DW_AT_decl_line(0x50) + .dwattr $C$DW$T$751, DW_AT_decl_column(0x2c) + + +$C$DW$T$59 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$59, DW_AT_name("ti_sysbios_knl_Semaphore_Object") + .dwattr $C$DW$T$59, DW_AT_declaration + .dwattr $C$DW$T$59, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$59, DW_AT_decl_line(0x4e) + .dwattr $C$DW$T$59, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$59 + +$C$DW$T$2184 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2184, DW_AT_name("ti_sysbios_knl_Semaphore_Object") + .dwattr $C$DW$T$2184, DW_AT_type(*$C$DW$T$59) + .dwattr $C$DW$T$2184, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2184, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2184, DW_AT_decl_line(0x4e) + .dwattr $C$DW$T$2184, DW_AT_decl_column(0x30) + +$C$DW$T$2185 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2185, DW_AT_type(*$C$DW$T$2184) + .dwattr $C$DW$T$2185, DW_AT_address_class(0x20) + +$C$DW$T$2186 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2186, DW_AT_name("ti_sysbios_knl_Semaphore_Handle") + .dwattr $C$DW$T$2186, DW_AT_type(*$C$DW$T$2185) + .dwattr $C$DW$T$2186, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2186, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2186, DW_AT_decl_line(0x50) + .dwattr $C$DW$T$2186, DW_AT_decl_column(0x2a) + +$C$DW$T$2187 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2187, DW_AT_name("ti_sysbios_knl_Semaphore_Instance") + .dwattr $C$DW$T$2187, DW_AT_type(*$C$DW$T$2185) + .dwattr $C$DW$T$2187, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2187, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2187, DW_AT_decl_line(0x52) + .dwattr $C$DW$T$2187, DW_AT_decl_column(0x2a) + + +$C$DW$T$60 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$60, DW_AT_name("ti_sysbios_knl_Semaphore_Object__") + .dwattr $C$DW$T$60, DW_AT_declaration + .dwattr $C$DW$T$60, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$60, DW_AT_decl_line(0x51) + .dwattr $C$DW$T$60, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$60 + +$C$DW$T$2188 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2188, DW_AT_name("ti_sysbios_knl_Semaphore_Instance_State") + .dwattr $C$DW$T$2188, DW_AT_type(*$C$DW$T$60) + .dwattr $C$DW$T$2188, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2188, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2188, DW_AT_decl_line(0x51) + .dwattr $C$DW$T$2188, DW_AT_decl_column(0x32) + + +$C$DW$T$752 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$752, DW_AT_name("ti_sysbios_knl_Semaphore_Params") + .dwattr $C$DW$T$752, DW_AT_byte_size(0x24) +$C$DW$1360 .dwtag DW_TAG_member + .dwattr $C$DW$1360, DW_AT_type(*$C$DW$T$217) + .dwattr $C$DW$1360, DW_AT_name("__size") + .dwattr $C$DW$1360, DW_AT_TI_symbol_name("__size") + .dwattr $C$DW$1360, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1360, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1360, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1360, DW_AT_decl_line(0x103) + .dwattr $C$DW$1360, DW_AT_decl_column(0x0c) + +$C$DW$1361 .dwtag DW_TAG_member + .dwattr $C$DW$1361, DW_AT_type(*$C$DW$T$223) + .dwattr $C$DW$1361, DW_AT_name("__self") + .dwattr $C$DW$1361, DW_AT_TI_symbol_name("__self") + .dwattr $C$DW$1361, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1361, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1361, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1361, DW_AT_decl_line(0x104) + .dwattr $C$DW$1361, DW_AT_decl_column(0x11) + +$C$DW$1362 .dwtag DW_TAG_member + .dwattr $C$DW$1362, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$1362, DW_AT_name("__fxns") + .dwattr $C$DW$1362, DW_AT_TI_symbol_name("__fxns") + .dwattr $C$DW$1362, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1362, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1362, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1362, DW_AT_decl_line(0x105) + .dwattr $C$DW$1362, DW_AT_decl_column(0x0b) + +$C$DW$1363 .dwtag DW_TAG_member + .dwattr $C$DW$1363, DW_AT_type(*$C$DW$T$491) + .dwattr $C$DW$1363, DW_AT_name("instance") + .dwattr $C$DW$1363, DW_AT_TI_symbol_name("instance") + .dwattr $C$DW$1363, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1363, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1363, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1363, DW_AT_decl_line(0x106) + .dwattr $C$DW$1363, DW_AT_decl_column(0x23) + +$C$DW$1364 .dwtag DW_TAG_member + .dwattr $C$DW$1364, DW_AT_type(*$C$DW$T$749) + .dwattr $C$DW$1364, DW_AT_name("event") + .dwattr $C$DW$1364, DW_AT_TI_symbol_name("event") + .dwattr $C$DW$1364, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1364, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1364, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1364, DW_AT_decl_line(0x107) + .dwattr $C$DW$1364, DW_AT_decl_column(0x21) + +$C$DW$1365 .dwtag DW_TAG_member + .dwattr $C$DW$1365, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$1365, DW_AT_name("eventId") + .dwattr $C$DW$1365, DW_AT_TI_symbol_name("eventId") + .dwattr $C$DW$1365, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1365, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1365, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1365, DW_AT_decl_line(0x108) + .dwattr $C$DW$1365, DW_AT_decl_column(0x0e) + +$C$DW$1366 .dwtag DW_TAG_member + .dwattr $C$DW$1366, DW_AT_type(*$C$DW$T$751) + .dwattr $C$DW$1366, DW_AT_name("mode") + .dwattr $C$DW$1366, DW_AT_TI_symbol_name("mode") + .dwattr $C$DW$1366, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$1366, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1366, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1366, DW_AT_decl_line(0x109) + .dwattr $C$DW$1366, DW_AT_decl_column(0x23) + +$C$DW$1367 .dwtag DW_TAG_member + .dwattr $C$DW$1367, DW_AT_type(*$C$DW$T$490) + .dwattr $C$DW$1367, DW_AT_name("__iprms") + .dwattr $C$DW$1367, DW_AT_TI_symbol_name("__iprms") + .dwattr $C$DW$1367, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1367, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1367, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1367, DW_AT_decl_line(0x10a) + .dwattr $C$DW$1367, DW_AT_decl_column(0x22) + + .dwattr $C$DW$T$752, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$T$752, DW_AT_decl_line(0x102) + .dwattr $C$DW$T$752, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$752 + +$C$DW$T$2189 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2189, DW_AT_name("ti_sysbios_knl_Semaphore_Params") + .dwattr $C$DW$T$2189, DW_AT_type(*$C$DW$T$752) + .dwattr $C$DW$T$2189, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2189, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2189, DW_AT_decl_line(0x4d) + .dwattr $C$DW$T$2189, DW_AT_decl_column(0x30) + + +$C$DW$T$755 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$755, DW_AT_name("ti_sysbios_knl_Semaphore_PendElem") + .dwattr $C$DW$T$755, DW_AT_byte_size(0x14) +$C$DW$1368 .dwtag DW_TAG_member + .dwattr $C$DW$1368, DW_AT_type(*$C$DW$T$734) + .dwattr $C$DW$1368, DW_AT_name("tpElem") + .dwattr $C$DW$1368, DW_AT_TI_symbol_name("tpElem") + .dwattr $C$DW$1368, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1368, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1368, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1368, DW_AT_decl_line(0x6c) + .dwattr $C$DW$1368, DW_AT_decl_column(0x22) + +$C$DW$1369 .dwtag DW_TAG_member + .dwattr $C$DW$1369, DW_AT_type(*$C$DW$T$754) + .dwattr $C$DW$1369, DW_AT_name("pendState") + .dwattr $C$DW$1369, DW_AT_TI_symbol_name("pendState") + .dwattr $C$DW$1369, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1369, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1369, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$1369, DW_AT_decl_line(0x6d) + .dwattr $C$DW$1369, DW_AT_decl_column(0x28) + + .dwattr $C$DW$T$755, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h") + .dwattr $C$DW$T$755, DW_AT_decl_line(0x6b) + .dwattr $C$DW$T$755, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$755 + 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DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1401, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1401, DW_AT_decl_line(0x113) + .dwattr $C$DW$1401, DW_AT_decl_column(0x0e) + +$C$DW$1402 .dwtag DW_TAG_member + .dwattr $C$DW$1402, DW_AT_type(*$C$DW$T$479) + .dwattr $C$DW$1402, DW_AT_name("__f6") + .dwattr $C$DW$1402, DW_AT_TI_symbol_name("__f6") + .dwattr $C$DW$1402, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1402, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1402, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1402, DW_AT_decl_line(0x114) + .dwattr $C$DW$1402, DW_AT_decl_column(0x0e) + +$C$DW$1403 .dwtag DW_TAG_member + .dwattr $C$DW$1403, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$1403, DW_AT_name("__f7") + .dwattr $C$DW$1403, DW_AT_TI_symbol_name("__f7") + .dwattr $C$DW$1403, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1403, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1403, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1403, DW_AT_decl_line(0x115) + .dwattr $C$DW$1403, DW_AT_decl_column(0x0e) + +$C$DW$1404 .dwtag DW_TAG_member + .dwattr $C$DW$1404, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$1404, DW_AT_name("__f8") + .dwattr $C$DW$1404, DW_AT_TI_symbol_name("__f8") + .dwattr $C$DW$1404, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$1404, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1404, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1404, DW_AT_decl_line(0x116) + .dwattr $C$DW$1404, DW_AT_decl_column(0x0e) + +$C$DW$1405 .dwtag DW_TAG_member + .dwattr $C$DW$1405, DW_AT_type(*$C$DW$T$773) + .dwattr $C$DW$1405, DW_AT_name("__f9") + .dwattr $C$DW$1405, DW_AT_TI_symbol_name("__f9") + .dwattr $C$DW$1405, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$1405, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1405, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1405, DW_AT_decl_line(0x117) + .dwattr $C$DW$1405, DW_AT_decl_column(0x21) + +$C$DW$1406 .dwtag DW_TAG_member + .dwattr $C$DW$1406, DW_AT_type(*$C$DW$T$775) + .dwattr $C$DW$1406, DW_AT_name("__f10") + .dwattr $C$DW$1406, DW_AT_TI_symbol_name("__f10") + .dwattr $C$DW$1406, DW_AT_data_member_location[DW_OP_plus_uconst 0x2c] + .dwattr $C$DW$1406, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1406, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1406, DW_AT_decl_line(0x118) + .dwattr $C$DW$1406, DW_AT_decl_column(0x35) + +$C$DW$1407 .dwtag DW_TAG_member + .dwattr $C$DW$1407, DW_AT_type(*$C$DW$T$498) + .dwattr $C$DW$1407, DW_AT_name("__name") + .dwattr $C$DW$1407, DW_AT_TI_symbol_name("__name") + .dwattr $C$DW$1407, DW_AT_data_member_location[DW_OP_plus_uconst 0x30] + .dwattr $C$DW$1407, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1407, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$1407, DW_AT_decl_line(0x119) + .dwattr $C$DW$1407, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$776, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h") + .dwattr $C$DW$T$776, DW_AT_decl_line(0x10d) + .dwattr $C$DW$T$776, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$776 + +$C$DW$T$2201 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2201, DW_AT_name("ti_sysbios_knl_Swi_Struct") + .dwattr $C$DW$T$2201, DW_AT_type(*$C$DW$T$776) + .dwattr $C$DW$T$2201, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2201, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2201, DW_AT_decl_line(0x5c) + .dwattr $C$DW$T$2201, DW_AT_decl_column(0x2a) + + +$C$DW$T$778 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$778, DW_AT_name("ti_sysbios_knl_Task_Args__create") + .dwattr $C$DW$T$778, DW_AT_byte_size(0x04) +$C$DW$1408 .dwtag DW_TAG_member + .dwattr $C$DW$1408, DW_AT_type(*$C$DW$T$777) + .dwattr $C$DW$1408, DW_AT_name("fxn") + .dwattr $C$DW$1408, DW_AT_TI_symbol_name("fxn") + .dwattr $C$DW$1408, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1408, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1408, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1408, DW_AT_decl_line(0x7c) + .dwattr $C$DW$1408, DW_AT_decl_column(0x21) + + .dwattr $C$DW$T$778, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$778, DW_AT_decl_line(0x7b) + .dwattr $C$DW$T$778, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$778 + +$C$DW$T$2202 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2202, DW_AT_name("ti_sysbios_knl_Task_Args__create") + .dwattr $C$DW$T$2202, DW_AT_type(*$C$DW$T$778) + .dwattr $C$DW$T$2202, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2202, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2202, DW_AT_decl_line(0x7d) + .dwattr $C$DW$T$2202, DW_AT_decl_column(0x03) + + +$C$DW$T$788 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$788, DW_AT_name("ti_sysbios_knl_Task_HookSet") + .dwattr $C$DW$T$788, DW_AT_byte_size(0x18) +$C$DW$1409 .dwtag DW_TAG_member + .dwattr $C$DW$1409, DW_AT_type(*$C$DW$T$635) + .dwattr $C$DW$1409, DW_AT_name("registerFxn") + .dwattr $C$DW$1409, DW_AT_TI_symbol_name("registerFxn") + .dwattr $C$DW$1409, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1409, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1409, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1409, DW_AT_decl_line(0x6a) + .dwattr $C$DW$1409, DW_AT_decl_column(0x10) + +$C$DW$1410 .dwtag DW_TAG_member + .dwattr $C$DW$1410, DW_AT_type(*$C$DW$T$783) + .dwattr $C$DW$1410, DW_AT_name("createFxn") + .dwattr $C$DW$1410, DW_AT_TI_symbol_name("createFxn") + .dwattr $C$DW$1410, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1410, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1410, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1410, DW_AT_decl_line(0x6b) + .dwattr $C$DW$1410, DW_AT_decl_column(0x10) + +$C$DW$1411 .dwtag DW_TAG_member + .dwattr $C$DW$1411, DW_AT_type(*$C$DW$T$785) + .dwattr $C$DW$1411, DW_AT_name("readyFxn") + .dwattr $C$DW$1411, DW_AT_TI_symbol_name("readyFxn") + .dwattr $C$DW$1411, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1411, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1411, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1411, DW_AT_decl_line(0x6c) + .dwattr $C$DW$1411, DW_AT_decl_column(0x10) + +$C$DW$1412 .dwtag DW_TAG_member + .dwattr $C$DW$1412, DW_AT_type(*$C$DW$T$787) + .dwattr $C$DW$1412, DW_AT_name("switchFxn") + .dwattr $C$DW$1412, DW_AT_TI_symbol_name("switchFxn") + .dwattr $C$DW$1412, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1412, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1412, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1412, DW_AT_decl_line(0x6d) + .dwattr $C$DW$1412, DW_AT_decl_column(0x10) + +$C$DW$1413 .dwtag DW_TAG_member + .dwattr $C$DW$1413, DW_AT_type(*$C$DW$T$785) + .dwattr $C$DW$1413, DW_AT_name("exitFxn") + .dwattr $C$DW$1413, DW_AT_TI_symbol_name("exitFxn") + .dwattr $C$DW$1413, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1413, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1413, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1413, DW_AT_decl_line(0x6e) + .dwattr $C$DW$1413, DW_AT_decl_column(0x10) + +$C$DW$1414 .dwtag DW_TAG_member + .dwattr $C$DW$1414, DW_AT_type(*$C$DW$T$785) + .dwattr $C$DW$1414, DW_AT_name("deleteFxn") + .dwattr $C$DW$1414, DW_AT_TI_symbol_name("deleteFxn") + .dwattr $C$DW$1414, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1414, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1414, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1414, DW_AT_decl_line(0x6f) + .dwattr $C$DW$1414, DW_AT_decl_column(0x10) + + .dwattr $C$DW$T$788, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$788, DW_AT_decl_line(0x69) + .dwattr $C$DW$T$788, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$788 + +$C$DW$T$159 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$159, DW_AT_name("ti_sysbios_knl_Task_HookSet") + .dwattr $C$DW$T$159, DW_AT_type(*$C$DW$T$788) + .dwattr $C$DW$T$159, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$159, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$159, DW_AT_decl_line(0x66) + .dwattr $C$DW$T$159, DW_AT_decl_column(0x2c) + +$C$DW$T$2203 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2203, DW_AT_name("__T1_ti_sysbios_knl_Task_hooks") + .dwattr $C$DW$T$2203, DW_AT_type(*$C$DW$T$159) + .dwattr $C$DW$T$2203, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2203, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2203, DW_AT_decl_line(0x1ae) + .dwattr $C$DW$T$2203, DW_AT_decl_column(0x25) + +$C$DW$T$160 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$160, DW_AT_type(*$C$DW$T$159) + .dwattr $C$DW$T$160, DW_AT_address_class(0x20) + + +$C$DW$T$803 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$803, DW_AT_name("ti_sysbios_knl_Task_Mode") + .dwattr $C$DW$T$803, DW_AT_byte_size(0x01) +$C$DW$1415 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1415, DW_AT_name("ti_sysbios_knl_Task_Mode_RUNNING") + .dwattr $C$DW$1415, DW_AT_const_value(0x00) + .dwattr $C$DW$1415, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1415, DW_AT_decl_line(0x54) + .dwattr $C$DW$1415, DW_AT_decl_column(0x05) + +$C$DW$1416 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1416, DW_AT_name("ti_sysbios_knl_Task_Mode_READY") + .dwattr $C$DW$1416, DW_AT_const_value(0x01) + .dwattr $C$DW$1416, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1416, DW_AT_decl_line(0x55) + .dwattr $C$DW$1416, DW_AT_decl_column(0x05) + +$C$DW$1417 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1417, DW_AT_name("ti_sysbios_knl_Task_Mode_BLOCKED") + .dwattr $C$DW$1417, DW_AT_const_value(0x02) + .dwattr $C$DW$1417, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1417, DW_AT_decl_line(0x56) + .dwattr $C$DW$1417, DW_AT_decl_column(0x05) + +$C$DW$1418 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1418, DW_AT_name("ti_sysbios_knl_Task_Mode_TERMINATED") + .dwattr $C$DW$1418, DW_AT_const_value(0x03) + .dwattr $C$DW$1418, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1418, DW_AT_decl_line(0x57) + .dwattr $C$DW$1418, DW_AT_decl_column(0x05) + +$C$DW$1419 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1419, DW_AT_name("ti_sysbios_knl_Task_Mode_INACTIVE") + .dwattr $C$DW$1419, DW_AT_const_value(0x04) + .dwattr $C$DW$1419, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1419, DW_AT_decl_line(0x58) + .dwattr $C$DW$1419, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$803, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$803, DW_AT_decl_line(0x53) + .dwattr $C$DW$T$803, DW_AT_decl_column(0x06) + .dwendtag $C$DW$T$803 + +$C$DW$T$804 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$804, DW_AT_name("ti_sysbios_knl_Task_Mode") + .dwattr $C$DW$T$804, DW_AT_type(*$C$DW$T$803) + .dwattr $C$DW$T$804, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$804, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$804, DW_AT_decl_line(0x5a) + .dwattr $C$DW$T$804, DW_AT_decl_column(0x27) + + +$C$DW$T$64 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$64, DW_AT_name("ti_sysbios_knl_Task_Module_State") + .dwattr $C$DW$T$64, DW_AT_declaration + .dwattr $C$DW$T$64, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$64, DW_AT_decl_line(0x68) + .dwattr $C$DW$T$64, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$64 + +$C$DW$T$2204 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2204, DW_AT_name("ti_sysbios_knl_Task_Module_State") + .dwattr $C$DW$T$2204, DW_AT_type(*$C$DW$T$64) + .dwattr $C$DW$T$2204, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2204, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2204, DW_AT_decl_line(0x68) + .dwattr $C$DW$T$2204, DW_AT_decl_column(0x31) + + +$C$DW$T$794 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$794, DW_AT_name("ti_sysbios_knl_Task_Module_StateSmp") + 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1421, DW_AT_decl_line(0xb7) + .dwattr $C$DW$1421, DW_AT_decl_column(0x37) + + .dwattr $C$DW$T$794, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$794, DW_AT_decl_line(0xb5) + .dwattr $C$DW$T$794, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$794 + +$C$DW$T$2205 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2205, DW_AT_name("ti_sysbios_knl_Task_Module_StateSmp") + .dwattr $C$DW$T$2205, DW_AT_type(*$C$DW$T$794) + .dwattr $C$DW$T$2205, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2205, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2205, DW_AT_decl_line(0x6a) + .dwattr $C$DW$T$2205, DW_AT_decl_column(0x34) + + +$C$DW$T$65 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$65, DW_AT_name("ti_sysbios_knl_Task_Object") + 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DW_AT_type(*$C$DW$T$796) + .dwattr $C$DW$1431, DW_AT_name("stackHeap") + .dwattr $C$DW$1431, DW_AT_TI_symbol_name("stackHeap") + .dwattr $C$DW$1431, DW_AT_data_member_location[DW_OP_plus_uconst 0x24] + .dwattr $C$DW$1431, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1431, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1431, DW_AT_decl_line(0x1d2) + .dwattr $C$DW$1431, DW_AT_decl_column(0x1e) + +$C$DW$1432 .dwtag DW_TAG_member + .dwattr $C$DW$1432, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1432, DW_AT_name("env") + .dwattr $C$DW$1432, DW_AT_TI_symbol_name("env") + .dwattr $C$DW$1432, DW_AT_data_member_location[DW_OP_plus_uconst 0x28] + .dwattr $C$DW$1432, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1432, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1432, DW_AT_decl_line(0x1d3) + .dwattr $C$DW$1432, DW_AT_decl_column(0x0d) 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$C$DW$1434, DW_AT_decl_line(0x1d5) + .dwattr $C$DW$1434, DW_AT_decl_column(0x0e) + +$C$DW$1435 .dwtag DW_TAG_member + .dwattr $C$DW$1435, DW_AT_type(*$C$DW$T$490) + .dwattr $C$DW$1435, DW_AT_name("__iprms") + .dwattr $C$DW$1435, DW_AT_TI_symbol_name("__iprms") + .dwattr $C$DW$1435, DW_AT_data_member_location[DW_OP_plus_uconst 0x34] + .dwattr $C$DW$1435, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1435, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1435, DW_AT_decl_line(0x1d6) + .dwattr $C$DW$1435, DW_AT_decl_column(0x22) + + .dwattr $C$DW$T$797, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$797, DW_AT_decl_line(0x1c8) + .dwattr $C$DW$T$797, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$797 + +$C$DW$T$2218 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2218, DW_AT_name("ti_sysbios_knl_Task_Params") + .dwattr $C$DW$T$2218, DW_AT_type(*$C$DW$T$797) + .dwattr $C$DW$T$2218, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2218, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2218, DW_AT_decl_line(0x6b) + .dwattr $C$DW$T$2218, DW_AT_decl_column(0x2b) + + +$C$DW$T$801 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$801, DW_AT_name("ti_sysbios_knl_Task_PendElem") + .dwattr $C$DW$T$801, DW_AT_byte_size(0x10) +$C$DW$1436 .dwtag DW_TAG_member + .dwattr $C$DW$1436, DW_AT_type(*$C$DW$T$703) + .dwattr $C$DW$1436, DW_AT_name("qElem") + .dwattr $C$DW$1436, DW_AT_TI_symbol_name("qElem") + .dwattr $C$DW$1436, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1436, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1436, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1436, DW_AT_decl_line(0x86) + .dwattr $C$DW$1436, DW_AT_decl_column(0x1f) + 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+ .dwattr $C$DW$1438, DW_AT_decl_column(0x21) + + .dwattr $C$DW$T$801, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$801, DW_AT_decl_line(0x85) + .dwattr $C$DW$T$801, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$801 + +$C$DW$T$734 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$734, DW_AT_name("ti_sysbios_knl_Task_PendElem") + .dwattr $C$DW$T$734, DW_AT_type(*$C$DW$T$801) + .dwattr $C$DW$T$734, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$734, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$734, DW_AT_decl_line(0x67) + .dwattr $C$DW$T$734, DW_AT_decl_column(0x2d) + +$C$DW$T$807 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$807, DW_AT_type(*$C$DW$T$734) + .dwattr $C$DW$T$807, DW_AT_address_class(0x20) + + +$C$DW$T$802 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$802, DW_AT_name("ti_sysbios_knl_Task_RunQEntry") + .dwattr $C$DW$T$802, DW_AT_byte_size(0x10) +$C$DW$1439 .dwtag DW_TAG_member + .dwattr $C$DW$1439, DW_AT_type(*$C$DW$T$703) + .dwattr $C$DW$1439, DW_AT_name("elem") + .dwattr $C$DW$1439, DW_AT_TI_symbol_name("elem") + .dwattr $C$DW$1439, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1439, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1439, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1439, DW_AT_decl_line(0xac) + .dwattr $C$DW$1439, DW_AT_decl_column(0x1f) + +$C$DW$1440 .dwtag DW_TAG_member + .dwattr $C$DW$1440, DW_AT_type(*$C$DW$T$517) + .dwattr $C$DW$1440, DW_AT_name("coreId") + .dwattr $C$DW$1440, DW_AT_TI_symbol_name("coreId") + .dwattr $C$DW$1440, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1440, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1440, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + 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DW_AT_type(*$C$DW$T$802) + .dwattr $C$DW$T$789, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$789, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$789, DW_AT_decl_line(0x69) + .dwattr $C$DW$T$789, DW_AT_decl_column(0x2e) + +$C$DW$T$790 .dwtag DW_TAG_volatile_type + .dwattr $C$DW$T$790, DW_AT_type(*$C$DW$T$789) + +$C$DW$T$2219 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2219, DW_AT_name("__T1_ti_sysbios_knl_Task_Module_StateSmp__smpRunQ") + .dwattr $C$DW$T$2219, DW_AT_type(*$C$DW$T$790) + .dwattr $C$DW$T$2219, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2219, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$2219, DW_AT_decl_line(0xb2) + .dwattr $C$DW$T$2219, DW_AT_decl_column(0x30) + +$C$DW$T$791 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$791, DW_AT_type(*$C$DW$T$790) + .dwattr $C$DW$T$791, DW_AT_address_class(0x20) + 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DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1443, DW_AT_decl_line(0x5f) + .dwattr $C$DW$1443, DW_AT_decl_column(0x0d) + +$C$DW$1444 .dwtag DW_TAG_member + .dwattr $C$DW$1444, DW_AT_type(*$C$DW$T$511) + .dwattr $C$DW$1444, DW_AT_name("stackSize") + .dwattr $C$DW$1444, DW_AT_TI_symbol_name("stackSize") + .dwattr $C$DW$1444, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1444, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1444, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1444, DW_AT_decl_line(0x60) + .dwattr $C$DW$1444, DW_AT_decl_column(0x0f) + +$C$DW$1445 .dwtag DW_TAG_member + .dwattr $C$DW$1445, DW_AT_type(*$C$DW$T$796) + .dwattr $C$DW$1445, DW_AT_name("stackHeap") + .dwattr $C$DW$1445, DW_AT_TI_symbol_name("stackHeap") + .dwattr $C$DW$1445, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1445, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1445, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1445, DW_AT_decl_line(0x61) + .dwattr $C$DW$1445, DW_AT_decl_column(0x1e) + +$C$DW$1446 .dwtag DW_TAG_member + .dwattr $C$DW$1446, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1446, DW_AT_name("env") + .dwattr $C$DW$1446, DW_AT_TI_symbol_name("env") + .dwattr $C$DW$1446, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1446, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1446, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1446, DW_AT_decl_line(0x62) + .dwattr $C$DW$1446, DW_AT_decl_column(0x0d) + +$C$DW$1447 .dwtag DW_TAG_member + .dwattr $C$DW$1447, DW_AT_type(*$C$DW$T$804) + .dwattr $C$DW$1447, DW_AT_name("mode") + .dwattr $C$DW$1447, DW_AT_TI_symbol_name("mode") + .dwattr $C$DW$1447, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1447, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1447, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1447, DW_AT_decl_line(0x63) + .dwattr $C$DW$1447, DW_AT_decl_column(0x1e) + +$C$DW$1448 .dwtag DW_TAG_member + .dwattr $C$DW$1448, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1448, DW_AT_name("sp") + .dwattr $C$DW$1448, DW_AT_TI_symbol_name("sp") + .dwattr $C$DW$1448, DW_AT_data_member_location[DW_OP_plus_uconst 0x18] + .dwattr $C$DW$1448, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1448, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1448, DW_AT_decl_line(0x64) + .dwattr $C$DW$1448, DW_AT_decl_column(0x0d) + +$C$DW$1449 .dwtag DW_TAG_member + .dwattr $C$DW$1449, DW_AT_type(*$C$DW$T$511) + .dwattr $C$DW$1449, DW_AT_name("used") + .dwattr $C$DW$1449, DW_AT_TI_symbol_name("used") + .dwattr $C$DW$1449, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1449, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1449, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1449, DW_AT_decl_line(0x65) + .dwattr $C$DW$1449, DW_AT_decl_column(0x0f) + + .dwattr $C$DW$T$805, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$T$805, DW_AT_decl_line(0x5d) + .dwattr $C$DW$T$805, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$805 + +$C$DW$T$2220 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2220, DW_AT_name("ti_sysbios_knl_Task_Stat") + .dwattr $C$DW$T$2220, DW_AT_type(*$C$DW$T$805) + .dwattr $C$DW$T$2220, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2220, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2220, DW_AT_decl_line(0x65) + .dwattr $C$DW$T$2220, DW_AT_decl_column(0x29) + + +$C$DW$T$812 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$812, DW_AT_name("ti_sysbios_knl_Task_Struct") + .dwattr $C$DW$T$812, DW_AT_byte_size(0x50) +$C$DW$1450 .dwtag DW_TAG_member + .dwattr $C$DW$1450, DW_AT_type(*$C$DW$T$703) + .dwattr $C$DW$1450, DW_AT_name("__f0") + .dwattr $C$DW$1450, DW_AT_TI_symbol_name("__f0") + .dwattr $C$DW$1450, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1450, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1450, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h") + .dwattr $C$DW$1450, DW_AT_decl_line(0x1db) + .dwattr $C$DW$1450, DW_AT_decl_column(0x1f) + +$C$DW$1451 .dwtag DW_TAG_member + .dwattr $C$DW$1451, DW_AT_type(*$C$DW$T$806) + .dwattr $C$DW$1451, DW_AT_name("__f1") + .dwattr $C$DW$1451, DW_AT_TI_symbol_name("__f1") + .dwattr $C$DW$1451, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + 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DW_AT_TI_symbol_name("swap") + .dwattr $C$DW$1472, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1472, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1472, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h") + .dwattr $C$DW$1472, DW_AT_decl_line(0xab) + .dwattr $C$DW$1472, DW_AT_decl_column(0x10) + +$C$DW$1473 .dwtag DW_TAG_member + .dwattr $C$DW$1473, DW_AT_type(*$C$DW$T$657) + .dwattr $C$DW$1473, DW_AT_name("checkStack") + .dwattr $C$DW$1473, DW_AT_TI_symbol_name("checkStack") + .dwattr $C$DW$1473, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1473, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1473, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h") + .dwattr $C$DW$1473, DW_AT_decl_line(0xac) + .dwattr $C$DW$1473, DW_AT_decl_column(0x10) + +$C$DW$1474 .dwtag DW_TAG_member + .dwattr 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$C$DW$1475, DW_AT_decl_line(0xae) + .dwattr $C$DW$1475, DW_AT_decl_column(0x10) + +$C$DW$1476 .dwtag DW_TAG_member + .dwattr $C$DW$1476, DW_AT_type(*$C$DW$T$661) + .dwattr $C$DW$1476, DW_AT_name("getDefaultStackSize") + .dwattr $C$DW$1476, DW_AT_TI_symbol_name("getDefaultStackSize") + .dwattr $C$DW$1476, DW_AT_data_member_location[DW_OP_plus_uconst 0x1c] + .dwattr $C$DW$1476, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1476, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h") + .dwattr $C$DW$1476, DW_AT_decl_line(0xaf) + .dwattr $C$DW$1476, DW_AT_decl_column(0x11) + +$C$DW$1477 .dwtag DW_TAG_member + .dwattr $C$DW$1477, DW_AT_type(*$C$DW$T$476) + .dwattr $C$DW$1477, DW_AT_name("__sfxns") + .dwattr $C$DW$1477, DW_AT_TI_symbol_name("__sfxns") + .dwattr $C$DW$1477, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1477, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1477, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h") + .dwattr $C$DW$1477, DW_AT_decl_line(0xb0) + .dwattr $C$DW$1477, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$813, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h") + .dwattr $C$DW$T$813, DW_AT_decl_line(0xa7) + .dwattr $C$DW$T$813, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$813 + +$C$DW$T$2222 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2222, DW_AT_name("ti_sysbios_knl_Task_SupportProxy_Fxns__") + .dwattr $C$DW$T$2222, DW_AT_type(*$C$DW$T$813) + .dwattr $C$DW$T$2222, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2222, DW_AT_decl_file("C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h") + .dwattr $C$DW$T$2222, DW_AT_decl_line(0x86) + .dwattr $C$DW$T$2222, DW_AT_decl_column(0x38) + +$C$DW$T$2223 .dwtag DW_TAG_const_type + .dwattr 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.dwendtag $C$DW$T$67 + +$C$DW$T$2226 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2226, DW_AT_name("xdc_runtime_Core_ObjDesc") + .dwattr $C$DW$T$2226, DW_AT_type(*$C$DW$T$67) + .dwattr $C$DW$T$2226, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2226, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$2226, DW_AT_decl_line(0x1c) + .dwattr $C$DW$T$2226, DW_AT_decl_column(0x29) + + +$C$DW$T$819 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$819, DW_AT_name("xdc_runtime_Diags_DictElem") + .dwattr $C$DW$T$819, DW_AT_byte_size(0x08) +$C$DW$1478 .dwtag DW_TAG_member + .dwattr $C$DW$1478, DW_AT_type(*$C$DW$T$815) + .dwattr $C$DW$1478, DW_AT_name("modId") + .dwattr $C$DW$1478, DW_AT_TI_symbol_name("modId") + .dwattr $C$DW$1478, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1478, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1478, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$1478, DW_AT_decl_line(0x9a) + .dwattr $C$DW$1478, DW_AT_decl_column(0x20) + +$C$DW$1479 .dwtag DW_TAG_member + .dwattr $C$DW$1479, DW_AT_type(*$C$DW$T$818) + .dwattr $C$DW$1479, DW_AT_name("maskAddr") + .dwattr $C$DW$1479, DW_AT_TI_symbol_name("maskAddr") + .dwattr $C$DW$1479, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1479, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1479, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$1479, DW_AT_decl_line(0x9b) + .dwattr $C$DW$1479, DW_AT_decl_column(0x1d) + + .dwattr $C$DW$T$819, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$T$819, DW_AT_decl_line(0x99) + .dwattr $C$DW$T$819, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$819 + +$C$DW$T$2227 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2227, DW_AT_name("xdc_runtime_Diags_DictElem") + .dwattr $C$DW$T$2227, DW_AT_type(*$C$DW$T$819) + .dwattr $C$DW$T$2227, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2227, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$2227, DW_AT_decl_line(0x27) + .dwattr $C$DW$T$2227, DW_AT_decl_column(0x2b) + +$C$DW$T$2228 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$2228, DW_AT_type(*$C$DW$T$2227) + .dwattr $C$DW$T$2228, DW_AT_address_class(0x20) + +$C$DW$T$2229 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2229, DW_AT_name("CT__xdc_runtime_Diags_dictBase") + .dwattr $C$DW$T$2229, DW_AT_type(*$C$DW$T$2228) + .dwattr $C$DW$T$2229, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2229, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$T$2229, DW_AT_decl_line(0xf6) + .dwattr $C$DW$T$2229, DW_AT_decl_column(0x25) + + +$C$DW$T$2230 .dwtag DW_TAG_enumeration_type + .dwattr $C$DW$T$2230, DW_AT_name("xdc_runtime_Diags_EventLevel") + .dwattr $C$DW$T$2230, DW_AT_byte_size(0x01) +$C$DW$1480 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1480, DW_AT_name("xdc_runtime_Diags_LEVEL1") + .dwattr $C$DW$1480, DW_AT_const_value(0x00) + .dwattr $C$DW$1480, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$1480, DW_AT_decl_line(0x80) + .dwattr $C$DW$1480, DW_AT_decl_column(0x05) + +$C$DW$1481 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1481, DW_AT_name("xdc_runtime_Diags_LEVEL2") + .dwattr $C$DW$1481, DW_AT_const_value(0x20) + .dwattr $C$DW$1481, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$1481, DW_AT_decl_line(0x81) + .dwattr $C$DW$1481, DW_AT_decl_column(0x05) + +$C$DW$1482 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1482, DW_AT_name("xdc_runtime_Diags_LEVEL3") + .dwattr $C$DW$1482, DW_AT_const_value(0x40) + .dwattr $C$DW$1482, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$1482, DW_AT_decl_line(0x82) + .dwattr $C$DW$1482, DW_AT_decl_column(0x05) + +$C$DW$1483 .dwtag DW_TAG_enumerator + .dwattr $C$DW$1483, DW_AT_name("xdc_runtime_Diags_LEVEL4") + .dwattr $C$DW$1483, DW_AT_const_value(0x60) + .dwattr $C$DW$1483, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$1483, DW_AT_decl_line(0x83) + .dwattr $C$DW$1483, DW_AT_decl_column(0x05) + + .dwattr $C$DW$T$2230, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$T$2230, DW_AT_decl_line(0x7f) + .dwattr $C$DW$T$2230, DW_AT_decl_column(0x06) + .dwendtag $C$DW$T$2230 + +$C$DW$T$2231 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2231, DW_AT_name("xdc_runtime_Diags_EventLevel") + .dwattr $C$DW$T$2231, DW_AT_type(*$C$DW$T$2230) + .dwattr $C$DW$T$2231, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2231, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h") + .dwattr $C$DW$T$2231, DW_AT_decl_line(0x85) + .dwattr $C$DW$T$2231, DW_AT_decl_column(0x2b) + + +$C$DW$T$827 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$827, DW_AT_name("xdc_runtime_Error_Block") + .dwattr $C$DW$T$827, DW_AT_byte_size(0x30) +$C$DW$1484 .dwtag DW_TAG_member + .dwattr $C$DW$1484, DW_AT_type(*$C$DW$T$592) + .dwattr $C$DW$1484, DW_AT_name("unused") + .dwattr $C$DW$1484, DW_AT_TI_symbol_name("unused") + .dwattr $C$DW$1484, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1484, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1484, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$1484, DW_AT_decl_line(0x5e) + .dwattr $C$DW$1484, DW_AT_decl_column(0x10) + +$C$DW$1485 .dwtag DW_TAG_member + .dwattr $C$DW$1485, DW_AT_type(*$C$DW$T$820) + .dwattr $C$DW$1485, DW_AT_name("data") + .dwattr $C$DW$1485, DW_AT_TI_symbol_name("data") + .dwattr $C$DW$1485, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1485, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1485, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$1485, DW_AT_decl_line(0x5f) + .dwattr $C$DW$1485, DW_AT_decl_column(0x1c) + +$C$DW$1486 .dwtag DW_TAG_member + .dwattr $C$DW$1486, DW_AT_type(*$C$DW$T$821) + .dwattr $C$DW$1486, DW_AT_name("id") + .dwattr $C$DW$1486, DW_AT_TI_symbol_name("id") + .dwattr $C$DW$1486, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1486, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1486, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$1486, DW_AT_decl_line(0x60) + .dwattr $C$DW$1486, DW_AT_decl_column(0x1a) + +$C$DW$1487 .dwtag DW_TAG_member + .dwattr $C$DW$1487, DW_AT_type(*$C$DW$T$822) + .dwattr $C$DW$1487, DW_AT_name("msg") + .dwattr $C$DW$1487, DW_AT_TI_symbol_name("msg") + .dwattr $C$DW$1487, DW_AT_data_member_location[DW_OP_plus_uconst 0x10] + .dwattr $C$DW$1487, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1487, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$1487, DW_AT_decl_line(0x61) + .dwattr $C$DW$1487, DW_AT_decl_column(0x10) + +$C$DW$1488 .dwtag DW_TAG_member + .dwattr $C$DW$1488, DW_AT_type(*$C$DW$T$823) + .dwattr $C$DW$1488, DW_AT_name("site") + .dwattr $C$DW$1488, DW_AT_TI_symbol_name("site") + .dwattr $C$DW$1488, DW_AT_data_member_location[DW_OP_plus_uconst 0x14] + .dwattr $C$DW$1488, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1488, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$1488, DW_AT_decl_line(0x62) + .dwattr $C$DW$1488, DW_AT_decl_column(0x1c) + +$C$DW$1489 .dwtag DW_TAG_member + .dwattr $C$DW$1489, DW_AT_type(*$C$DW$T$826) + .dwattr $C$DW$1489, DW_AT_name("xtra") + .dwattr $C$DW$1489, DW_AT_TI_symbol_name("xtra") + .dwattr $C$DW$1489, DW_AT_data_member_location[DW_OP_plus_uconst 0x20] + .dwattr $C$DW$1489, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1489, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$1489, DW_AT_decl_line(0x63) + .dwattr $C$DW$1489, DW_AT_decl_column(0x28) + + .dwattr $C$DW$T$827, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h") + .dwattr $C$DW$T$827, DW_AT_decl_line(0x5d) + .dwattr $C$DW$T$827, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$827 + +$C$DW$T$638 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$638, DW_AT_name("xdc_runtime_Error_Block") + .dwattr $C$DW$T$638, DW_AT_type(*$C$DW$T$827) + .dwattr $C$DW$T$638, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$638, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$638, DW_AT_decl_line(0x2e) + .dwattr $C$DW$T$638, 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DW_AT_decl_column(0x10) + +$C$DW$1643 .dwtag DW_TAG_member + .dwattr $C$DW$1643, DW_AT_type(*$C$DW$T$951) + .dwattr $C$DW$1643, DW_AT_name("__label") + .dwattr $C$DW$1643, DW_AT_TI_symbol_name("__label") + .dwattr $C$DW$1643, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1643, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1643, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1643, DW_AT_decl_line(0xc5) + .dwattr $C$DW$1643, DW_AT_decl_column(0x20) + +$C$DW$1644 .dwtag DW_TAG_member + .dwattr $C$DW$1644, DW_AT_type(*$C$DW$T$815) + .dwattr $C$DW$1644, DW_AT_name("__mid") + .dwattr $C$DW$1644, DW_AT_TI_symbol_name("__mid") + .dwattr $C$DW$1644, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1644, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1644, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1644, DW_AT_decl_line(0xc6) + .dwattr $C$DW$1644, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$952, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$T$952, DW_AT_decl_line(0xc2) + .dwattr $C$DW$T$952, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$952 + +$C$DW$T$2461 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2461, DW_AT_name("xdc_runtime_Types_SysFxns") + .dwattr $C$DW$T$2461, DW_AT_type(*$C$DW$T$952) + .dwattr $C$DW$T$2461, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2461, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$2461, DW_AT_decl_line(0x131) + .dwattr $C$DW$T$2461, DW_AT_decl_column(0x2a) + + +$C$DW$T$958 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$958, DW_AT_name("xdc_runtime_Types_SysFxns2") + .dwattr $C$DW$T$958, DW_AT_byte_size(0x10) +$C$DW$1645 .dwtag DW_TAG_member + .dwattr $C$DW$1645, DW_AT_type(*$C$DW$T$957) + .dwattr $C$DW$1645, DW_AT_name("__create") + .dwattr $C$DW$1645, DW_AT_TI_symbol_name("__create") + .dwattr $C$DW$1645, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1645, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1645, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1645, DW_AT_decl_line(0xcb) + .dwattr $C$DW$1645, DW_AT_decl_column(0x0f) + +$C$DW$1646 .dwtag DW_TAG_member + .dwattr $C$DW$1646, DW_AT_type(*$C$DW$T$947) + .dwattr $C$DW$1646, DW_AT_name("__delete") + .dwattr $C$DW$1646, DW_AT_TI_symbol_name("__delete") + .dwattr $C$DW$1646, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1646, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1646, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1646, DW_AT_decl_line(0xcc) + .dwattr $C$DW$1646, DW_AT_decl_column(0x10) + +$C$DW$1647 .dwtag DW_TAG_member + .dwattr $C$DW$1647, DW_AT_type(*$C$DW$T$951) + .dwattr $C$DW$1647, DW_AT_name("__label") + .dwattr $C$DW$1647, DW_AT_TI_symbol_name("__label") + .dwattr $C$DW$1647, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$1647, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1647, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1647, DW_AT_decl_line(0xcd) + .dwattr $C$DW$1647, DW_AT_decl_column(0x20) + +$C$DW$1648 .dwtag DW_TAG_member + .dwattr $C$DW$1648, DW_AT_type(*$C$DW$T$815) + .dwattr $C$DW$1648, DW_AT_name("__mid") + .dwattr $C$DW$1648, DW_AT_TI_symbol_name("__mid") + .dwattr $C$DW$1648, DW_AT_data_member_location[DW_OP_plus_uconst 0xc] + .dwattr $C$DW$1648, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1648, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1648, DW_AT_decl_line(0xce) + .dwattr $C$DW$1648, DW_AT_decl_column(0x20) + + .dwattr $C$DW$T$958, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$T$958, DW_AT_decl_line(0xca) + .dwattr $C$DW$T$958, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$958 + +$C$DW$T$476 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$476, DW_AT_name("xdc_runtime_Types_SysFxns2") + .dwattr $C$DW$T$476, DW_AT_type(*$C$DW$T$958) + .dwattr $C$DW$T$476, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$476, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$476, DW_AT_decl_line(0x132) + .dwattr $C$DW$T$476, DW_AT_decl_column(0x2b) + +$C$DW$T$477 .dwtag DW_TAG_const_type + .dwattr $C$DW$T$477, DW_AT_type(*$C$DW$T$476) + +$C$DW$T$478 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$478, DW_AT_type(*$C$DW$T$477) + .dwattr $C$DW$T$478, DW_AT_address_class(0x20) + + +$C$DW$T$959 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$959, DW_AT_name("xdc_runtime_Types_Timestamp64") + .dwattr $C$DW$T$959, DW_AT_byte_size(0x08) +$C$DW$1649 .dwtag DW_TAG_member + .dwattr $C$DW$1649, DW_AT_type(*$C$DW$T$649) + .dwattr $C$DW$1649, DW_AT_name("hi") + .dwattr $C$DW$1649, DW_AT_TI_symbol_name("hi") + .dwattr $C$DW$1649, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1649, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1649, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1649, DW_AT_decl_line(0x7a) + .dwattr $C$DW$1649, DW_AT_decl_column(0x10) + +$C$DW$1650 .dwtag DW_TAG_member + .dwattr $C$DW$1650, DW_AT_type(*$C$DW$T$649) + .dwattr $C$DW$1650, DW_AT_name("lo") + .dwattr $C$DW$1650, DW_AT_TI_symbol_name("lo") + .dwattr $C$DW$1650, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1650, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1650, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1650, DW_AT_decl_line(0x7b) + .dwattr $C$DW$1650, DW_AT_decl_column(0x10) + + .dwattr $C$DW$T$959, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$T$959, DW_AT_decl_line(0x79) + .dwattr $C$DW$T$959, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$959 + +$C$DW$T$878 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$878, DW_AT_name("xdc_runtime_Types_Timestamp64") + .dwattr $C$DW$T$878, DW_AT_type(*$C$DW$T$959) + .dwattr $C$DW$T$878, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$878, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$878, DW_AT_decl_line(0x129) + .dwattr $C$DW$T$878, DW_AT_decl_column(0x2e) + + +$C$DW$T$960 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$960, DW_AT_name("xdc_runtime_Types_Vec") + .dwattr $C$DW$T$960, DW_AT_byte_size(0x08) +$C$DW$1651 .dwtag DW_TAG_member + .dwattr $C$DW$1651, DW_AT_type(*$C$DW$T$480) + .dwattr $C$DW$1651, DW_AT_name("len") + .dwattr $C$DW$1651, DW_AT_TI_symbol_name("len") + .dwattr $C$DW$1651, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$1651, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1651, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1651, DW_AT_decl_line(0xa5) + .dwattr $C$DW$1651, DW_AT_decl_column(0x0d) + +$C$DW$1652 .dwtag DW_TAG_member + .dwattr $C$DW$1652, DW_AT_type(*$C$DW$T$510) + .dwattr $C$DW$1652, DW_AT_name("arr") + .dwattr $C$DW$1652, DW_AT_TI_symbol_name("arr") + .dwattr $C$DW$1652, DW_AT_data_member_location[DW_OP_plus_uconst 0x4] + .dwattr $C$DW$1652, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$1652, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$1652, DW_AT_decl_line(0xa6) + .dwattr $C$DW$1652, DW_AT_decl_column(0x0d) + + .dwattr $C$DW$T$960, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h") + .dwattr $C$DW$T$960, DW_AT_decl_line(0xa4) + .dwattr $C$DW$T$960, DW_AT_decl_column(0x08) + .dwendtag $C$DW$T$960 + +$C$DW$T$2462 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$2462, DW_AT_name("xdc_runtime_Types_Vec") + .dwattr $C$DW$T$2462, DW_AT_type(*$C$DW$T$960) + .dwattr $C$DW$T$2462, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$2462, DW_AT_decl_file("C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h") + .dwattr $C$DW$T$2462, DW_AT_decl_line(0x12c) + .dwattr $C$DW$T$2462, DW_AT_decl_column(0x26) + + .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + +;*************************************************************** +;* DWARF CIE ENTRIES * +;*************************************************************** + +$C$DW$CIE .dwcie 14 + .dwcfi cfa_register, 13 + .dwcfi cfa_offset, 0 + .dwcfi same_value, 4 + .dwcfi same_value, 5 + .dwcfi same_value, 6 + .dwcfi same_value, 7 + .dwcfi same_value, 8 + .dwcfi same_value, 9 + .dwcfi same_value, 10 + .dwcfi same_value, 11 + .dwcfi same_value, 80 + .dwcfi same_value, 81 + .dwcfi same_value, 82 + .dwcfi same_value, 83 + .dwcfi same_value, 84 + .dwcfi same_value, 85 + .dwcfi same_value, 86 + .dwcfi same_value, 87 + .dwcfi same_value, 88 + .dwcfi same_value, 89 + .dwcfi same_value, 90 + .dwcfi same_value, 91 + .dwcfi same_value, 92 + .dwcfi same_value, 93 + .dwcfi same_value, 94 + .dwcfi same_value, 95 + .dwendentry + +;*************************************************************** +;* DWARF REGISTER MAP * +;*************************************************************** + +$C$DW$1653 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1653, DW_AT_name("A1") + .dwattr $C$DW$1653, DW_AT_location[DW_OP_reg0] + +$C$DW$1654 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1654, DW_AT_name("A2") + .dwattr $C$DW$1654, DW_AT_location[DW_OP_reg1] + +$C$DW$1655 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1655, DW_AT_name("A3") + .dwattr $C$DW$1655, DW_AT_location[DW_OP_reg2] + +$C$DW$1656 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1656, DW_AT_name("A4") + .dwattr $C$DW$1656, DW_AT_location[DW_OP_reg3] + +$C$DW$1657 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1657, DW_AT_name("V1") + .dwattr $C$DW$1657, DW_AT_location[DW_OP_reg4] + +$C$DW$1658 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1658, DW_AT_name("V2") + .dwattr $C$DW$1658, DW_AT_location[DW_OP_reg5] + +$C$DW$1659 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1659, DW_AT_name("V3") + .dwattr $C$DW$1659, DW_AT_location[DW_OP_reg6] + +$C$DW$1660 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1660, DW_AT_name("V4") + .dwattr $C$DW$1660, DW_AT_location[DW_OP_reg7] + +$C$DW$1661 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1661, DW_AT_name("V5") + .dwattr $C$DW$1661, DW_AT_location[DW_OP_reg8] + +$C$DW$1662 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1662, DW_AT_name("V6") + .dwattr $C$DW$1662, DW_AT_location[DW_OP_reg9] + +$C$DW$1663 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1663, DW_AT_name("V7") + .dwattr $C$DW$1663, DW_AT_location[DW_OP_reg10] + +$C$DW$1664 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1664, DW_AT_name("V8") + .dwattr $C$DW$1664, DW_AT_location[DW_OP_reg11] + +$C$DW$1665 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1665, DW_AT_name("V9") + .dwattr $C$DW$1665, DW_AT_location[DW_OP_reg12] + +$C$DW$1666 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1666, DW_AT_name("SP") + .dwattr $C$DW$1666, DW_AT_location[DW_OP_reg13] + +$C$DW$1667 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1667, DW_AT_name("LR") + .dwattr $C$DW$1667, DW_AT_location[DW_OP_reg14] + +$C$DW$1668 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1668, DW_AT_name("PC") + .dwattr $C$DW$1668, DW_AT_location[DW_OP_reg15] + +$C$DW$1669 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1669, DW_AT_name("SR") + .dwattr $C$DW$1669, DW_AT_location[DW_OP_reg17] + +$C$DW$1670 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1670, DW_AT_name("AP") + .dwattr $C$DW$1670, DW_AT_location[DW_OP_reg7] + +$C$DW$1671 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1671, DW_AT_name("D0") + .dwattr $C$DW$1671, DW_AT_location[DW_OP_regx 0x40] + +$C$DW$1672 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1672, DW_AT_name("D0_hi") + .dwattr $C$DW$1672, DW_AT_location[DW_OP_regx 0x41] + +$C$DW$1673 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1673, DW_AT_name("D1") + .dwattr $C$DW$1673, DW_AT_location[DW_OP_regx 0x42] + +$C$DW$1674 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1674, DW_AT_name("D1_hi") + .dwattr $C$DW$1674, DW_AT_location[DW_OP_regx 0x43] + +$C$DW$1675 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1675, DW_AT_name("D2") + .dwattr $C$DW$1675, DW_AT_location[DW_OP_regx 0x44] + +$C$DW$1676 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1676, DW_AT_name("D2_hi") + .dwattr $C$DW$1676, DW_AT_location[DW_OP_regx 0x45] + +$C$DW$1677 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1677, DW_AT_name("D3") + .dwattr $C$DW$1677, DW_AT_location[DW_OP_regx 0x46] + +$C$DW$1678 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1678, DW_AT_name("D3_hi") + .dwattr $C$DW$1678, DW_AT_location[DW_OP_regx 0x47] + +$C$DW$1679 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1679, DW_AT_name("D4") + .dwattr $C$DW$1679, DW_AT_location[DW_OP_regx 0x48] + +$C$DW$1680 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1680, DW_AT_name("D4_hi") + .dwattr $C$DW$1680, DW_AT_location[DW_OP_regx 0x49] + +$C$DW$1681 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1681, DW_AT_name("D5") + .dwattr $C$DW$1681, DW_AT_location[DW_OP_regx 0x4a] + +$C$DW$1682 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1682, DW_AT_name("D5_hi") + .dwattr $C$DW$1682, DW_AT_location[DW_OP_regx 0x4b] + +$C$DW$1683 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1683, DW_AT_name("D6") + .dwattr $C$DW$1683, DW_AT_location[DW_OP_regx 0x4c] + +$C$DW$1684 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1684, DW_AT_name("D6_hi") + .dwattr $C$DW$1684, DW_AT_location[DW_OP_regx 0x4d] + +$C$DW$1685 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1685, DW_AT_name("D7") + .dwattr $C$DW$1685, DW_AT_location[DW_OP_regx 0x4e] + +$C$DW$1686 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1686, DW_AT_name("D7_hi") + .dwattr $C$DW$1686, DW_AT_location[DW_OP_regx 0x4f] + +$C$DW$1687 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1687, DW_AT_name("D8") + .dwattr $C$DW$1687, DW_AT_location[DW_OP_regx 0x50] + +$C$DW$1688 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1688, DW_AT_name("D8_hi") + .dwattr $C$DW$1688, DW_AT_location[DW_OP_regx 0x51] + +$C$DW$1689 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1689, DW_AT_name("D9") + .dwattr $C$DW$1689, DW_AT_location[DW_OP_regx 0x52] + +$C$DW$1690 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1690, DW_AT_name("D9_hi") + .dwattr $C$DW$1690, DW_AT_location[DW_OP_regx 0x53] + +$C$DW$1691 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1691, DW_AT_name("D10") + .dwattr $C$DW$1691, DW_AT_location[DW_OP_regx 0x54] + +$C$DW$1692 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1692, DW_AT_name("D10_hi") + .dwattr $C$DW$1692, DW_AT_location[DW_OP_regx 0x55] + +$C$DW$1693 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1693, DW_AT_name("D11") + .dwattr $C$DW$1693, DW_AT_location[DW_OP_regx 0x56] + +$C$DW$1694 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1694, DW_AT_name("D11_hi") + .dwattr $C$DW$1694, DW_AT_location[DW_OP_regx 0x57] + +$C$DW$1695 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1695, DW_AT_name("D12") + .dwattr $C$DW$1695, DW_AT_location[DW_OP_regx 0x58] + +$C$DW$1696 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1696, DW_AT_name("D12_hi") + .dwattr $C$DW$1696, DW_AT_location[DW_OP_regx 0x59] + +$C$DW$1697 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1697, DW_AT_name("D13") + .dwattr $C$DW$1697, DW_AT_location[DW_OP_regx 0x5a] + +$C$DW$1698 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1698, DW_AT_name("D13_hi") + .dwattr $C$DW$1698, DW_AT_location[DW_OP_regx 0x5b] + +$C$DW$1699 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1699, DW_AT_name("D14") + .dwattr $C$DW$1699, DW_AT_location[DW_OP_regx 0x5c] + +$C$DW$1700 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1700, DW_AT_name("D14_hi") + .dwattr $C$DW$1700, DW_AT_location[DW_OP_regx 0x5d] + +$C$DW$1701 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1701, DW_AT_name("D15") + .dwattr $C$DW$1701, DW_AT_location[DW_OP_regx 0x5e] + +$C$DW$1702 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1702, DW_AT_name("D15_hi") + .dwattr $C$DW$1702, DW_AT_location[DW_OP_regx 0x5f] + +$C$DW$1703 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1703, DW_AT_name("FPEXC") + .dwattr $C$DW$1703, DW_AT_location[DW_OP_reg18] + +$C$DW$1704 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$1704, DW_AT_name("FPSCR") + .dwattr $C$DW$1704, DW_AT_location[DW_OP_reg19] + + .dwendtag $C$DW$CU + diff --git a/CCS/mm/Debug/EK_TM4C123GXL.d b/CCS/mm/Debug/EK_TM4C123GXL.d new file mode 100644 index 0000000..4b9f679 --- /dev/null +++ b/CCS/mm/Debug/EK_TM4C123GXL.d @@ -0,0 +1,491 @@ +# FIXED + +EK_TM4C123GXL.obj: ../EK_TM4C123GXL.c +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stddef.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h +EK_TM4C123GXL.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h +EK_TM4C123GXL.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/std.h +EK_TM4C123GXL.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/M4F.h +EK_TM4C123GXL.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/std.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/xdc.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__prologue.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__epilogue.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__prologue.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h 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+EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Main_Module_GateProxy.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__epilogue.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__prologue.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +EK_TM4C123GXL.obj: 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C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_SupportProxy.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_Module_GateProxy.h +EK_TM4C123GXL.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +EK_TM4C123GXL.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi__prologue.h +EK_TM4C123GXL.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package/package.defs.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log__prologue.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +EK_TM4C123GXL.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h +EK_TM4C123GXL.obj: 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+C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Clock_TimerProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/pwm/PWMTiva.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SDSPI.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/sdspi/SDSPITiva.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ff.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/integer.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/ffconf.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/diskio.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/SPI.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/spi/SPITivaDMA.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/UART.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/uart/UARTTiva.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/utils/RingBuf.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Clock_TimerProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Watchdog.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/watchdog/WatchdogTiva.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/WiFi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/wifi/WiFiCC3100.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h: diff --git a/CCS/mm/Debug/EK_TM4C123GXL.obj b/CCS/mm/Debug/EK_TM4C123GXL.obj new file mode 100644 index 0000000..29767bf Binary files /dev/null and b/CCS/mm/Debug/EK_TM4C123GXL.obj differ diff --git a/CCS/mm/Debug/ccsObjs.opt b/CCS/mm/Debug/ccsObjs.opt new file mode 100644 index 0000000..ea5defd --- /dev/null +++ b/CCS/mm/Debug/ccsObjs.opt @@ -0,0 +1 @@ +"./EK_TM4C123GXL.obj" "./lib/io.obj" "./lib/launchpad.obj" "./lib/main.obj" "./lib/motors.obj" "../src/sysbios/BIOS.obj" "../src/sysbios/m3_Hwi_asm.obj" "../src/sysbios/m3_Hwi_asm_switch.obj" "../src/sysbios/m3_IntrinsicsSupport_asm.obj" "../src/sysbios/m3_TaskSupport_asm.obj" "../EK_TM4C123GXL.cmd" -l"configPkg/linker.cmd" -l"C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/grlib/ccs/Debug/grlib.lib" -l"C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/usblib/ccs/Debug/usblib.lib" -l"C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/ccs/Debug/driverlib.lib" -llibc.a \ No newline at end of file diff --git a/CCS/mm/Debug/configPkg/.interfaces b/CCS/mm/Debug/configPkg/.interfaces new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/.libraries,em4f b/CCS/mm/Debug/configPkg/.libraries,em4f new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/.xdcenv.mak b/CCS/mm/Debug/configPkg/.xdcenv.mak new file mode 100644 index 0000000..83baccb --- /dev/null +++ b/CCS/mm/Debug/configPkg/.xdcenv.mak @@ -0,0 +1,16 @@ +# +_XDCBUILDCOUNT = +ifneq (,$(findstring path,$(_USEXDCENV_))) +override XDCPATH = C:/ti/tirtos_tivac_2_16_00_08/packages;C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages;C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages;C:/ti/tirtos_tivac_2_16_00_08/products/ndk_2_25_00_09/packages;C:/ti/tirtos_tivac_2_16_00_08/products/uia_2_00_05_50/packages;C:/ti/tirtos_tivac_2_16_00_08/products/ns_1_11_00_10/packages +override XDCROOT = C:/ti/ccs930/xdctools_3_60_02_34_core +override XDCBUILDCFG = ./config.bld +endif +ifneq (,$(findstring args,$(_USEXDCENV_))) +override XDCARGS = +override XDCTARGETS = +endif +# +ifeq (0,1) +PKGPATH = C:/ti/tirtos_tivac_2_16_00_08/packages;C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages;C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages;C:/ti/tirtos_tivac_2_16_00_08/products/ndk_2_25_00_09/packages;C:/ti/tirtos_tivac_2_16_00_08/products/uia_2_00_05_50/packages;C:/ti/tirtos_tivac_2_16_00_08/products/ns_1_11_00_10/packages;C:/ti/ccs930/xdctools_3_60_02_34_core/packages;.. +HOSTOS = Windows +endif diff --git a/CCS/mm/Debug/configPkg/compiler.opt b/CCS/mm/Debug/configPkg/compiler.opt new file mode 100644 index 0000000..0aaeceb --- /dev/null +++ b/CCS/mm/Debug/configPkg/compiler.opt @@ -0,0 +1 @@ +--endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -I"C:/ti/tirtos_tivac_2_16_00_08/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/ndk_2_25_00_09/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/uia_2_00_05_50/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/ns_1_11_00_10/packages" -I"C:/ti/ccs930/xdctools_3_60_02_34_core/packages" -I"C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg/.." -IC:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/rts -IC:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include -Dxdc_target_types__="ti/targets/arm/elf/std.h" -Dxdc_target_name__=M4F -Dxdc_cfg__xheader__="\"C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.h\"" diff --git a/CCS/mm/Debug/configPkg/compiler.opt.defs b/CCS/mm/Debug/configPkg/compiler.opt.defs new file mode 100644 index 0000000..d78899b --- /dev/null +++ b/CCS/mm/Debug/configPkg/compiler.opt.defs @@ -0,0 +1 @@ +-I"C:/ti/tirtos_tivac_2_16_00_08/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/ndk_2_25_00_09/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/uia_2_00_05_50/packages" -I"C:/ti/tirtos_tivac_2_16_00_08/products/ns_1_11_00_10/packages" -I"C:/ti/ccs930/xdctools_3_60_02_34_core/packages" -I"C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg/.." -IC:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/rts -IC:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include -Dxdc_target_types__="ti/targets/arm/elf/std.h" -Dxdc_target_name__=M4F -Dxdc_cfg__xheader__="\"C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.h\"" diff --git a/CCS/mm/Debug/configPkg/config.bld b/CCS/mm/Debug/configPkg/config.bld new file mode 100644 index 0000000..23fac25 --- /dev/null +++ b/CCS/mm/Debug/configPkg/config.bld @@ -0,0 +1,24 @@ +/* THIS IS A GENERATED FILE -- DO NOT EDIT */ + +var target; /* the target used for this build */ + +/* configuro was passed the target's name explicitly */ +try { + target = xdc.module('ti.targets.arm.elf.M4F'); +} +catch (e) { + throw new Error("Can't find the target named '" + 'ti.targets.arm.elf.M4F' + + "' along the path '" + environment["xdc.path"] + + "': please check the spelling of the target's name and that it exists along this path."); +} +if (!(target instanceof xdc.module("xdc.bld.ITarget").Module)) { + throw new Error("The module named 'ti.targets.arm.elf.M4F' exists but it's not a target: please check the spelling of the target's name"); +} + +/* configuro was passed compiler options explicitly */ +target.ccOpts.prefix = unescape("-mv7M4%20--code_state%3D16%20--float_support%3DFPv4SPD16%20-me%20--include_path%3D%22C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm%22%20--include_path%3D%22C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc%22%20--include_path%3D%22C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm%22%20--include_path%3D%22C%3A/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b%22%20--include_path%3D%22C%3A/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix%22%20--include_path%3D%22C%3A/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include%22%20--define%3Dccs%3D%22ccs%22%20--define%3DPART_TM4C123GH6PM%20--define%3Dccs%20--define%3DTIVAWARE%20-g%20--c99%20--gcc%20--diag_warning%3D225%20--diag_warning%3D255%20--diag_wrap%3Doff%20--display_error_number%20--gen_func_subsections%3Don%20--abi%3Deabi%20%20%20") + target.ccOpts.prefix; + +/* configuro was passed the target's rootDir explicitly */ +target.rootDir = 'C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS'; + +Build.targets = [target]; diff --git a/CCS/mm/Debug/configPkg/custom.mak b/CCS/mm/Debug/configPkg/custom.mak new file mode 100644 index 0000000..933fc39 --- /dev/null +++ b/CCS/mm/Debug/configPkg/custom.mak @@ -0,0 +1,11 @@ +## THIS IS A GENERATED FILE -- DO NOT EDIT +.configuro: .libraries,em4f linker.cmd package/cfg/gpiointerrupt_pem4f.oem4f + +# To simplify configuro usage in makefiles: +# o create a generic linker command file name +# o set modification times of compiler.opt* files to be greater than +# or equal to the generated config header +# +linker.cmd: package/cfg/gpiointerrupt_pem4f.xdl + $(SED) 's"^\"\(package/cfg/gpiointerrupt_pem4fcfg.cmd\)\"$""\"C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg/\1\""' package/cfg/gpiointerrupt_pem4f.xdl > $@ + -$(SETDATE) -r:max package/cfg/gpiointerrupt_pem4f.h compiler.opt compiler.opt.defs diff --git a/CCS/mm/Debug/configPkg/linker.cmd b/CCS/mm/Debug/configPkg/linker.cmd new file mode 100644 index 0000000..8a5b87e --- /dev/null +++ b/CCS/mm/Debug/configPkg/linker.cmd @@ -0,0 +1,156 @@ +/* + * Do not modify this file; it is automatically generated from the template + * linkcmd.xdt in the ti.platforms.tiva package and will be overwritten. + */ + +/* + * put '"'s around paths because, without this, the linker + * considers '-' as minus operator, not a file name character. + */ + + +-l"C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\Debug\configPkg\package\cfg\gpiointerrupt_pem4f.oem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\packages\ti\tirtos\utils\lib\release\ti.tirtos.utils.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/lib/cc3x00_host_driver.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_tivaware.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_wifi_tivaware.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\tidrivers_tivac_2_16_00_08\packages\ti\mw\fatfs\lib\release\ti.mw.fatfs.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/lib/tirtosport.aem4f" +-l"C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\src\sysbios\sysbios.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\catalog\arm\cortexm4\tiva\ce\lib\Boot.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\ti.targets.arm.rtsarm.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\boot.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\auto_init.aem4f" + +--retain="*(xdc.meta)" + +/* C6x Elf symbols */ +--symbol_map __TI_STACK_SIZE=__STACK_SIZE +--symbol_map __TI_STACK_BASE=__stack +--symbol_map _stack=__stack + + +--args 0x0 +-heap 0x0 +-stack 0x300 + +/* + * Linker command file contributions from all loaded packages: + */ + +/* Content from xdc.services.global (null): */ + +/* Content from xdc (null): */ + +/* Content from xdc.corevers (null): */ + +/* Content from xdc.shelf (null): */ + +/* Content from xdc.services.spec (null): */ + +/* Content from xdc.services.intern.xsr (null): */ + +/* Content from xdc.services.intern.gen (null): */ + +/* Content from xdc.services.intern.cmd (null): */ + +/* Content from xdc.bld (null): */ + +/* Content from ti.targets (null): */ + +/* Content from ti.targets.arm.elf (null): */ + +/* Content from xdc.rov (null): */ + +/* Content from xdc.runtime (null): */ + +/* Content from xdc.services.getset (null): */ + +/* Content from ti.targets.arm.rtsarm (null): */ + +/* Content from ti.sysbios.interfaces (null): */ + +/* Content from ti.sysbios.family (null): */ + +/* Content from ti.sysbios.family.arm (ti/sysbios/family/arm/linkcmd.xdt): */ +--retain "*(.vecs)" + +/* Content from ti.sysbios.rts (ti/sysbios/rts/linkcmd.xdt): */ + +/* Content from xdc.runtime.knl (null): */ + +/* Content from ti.catalog.arm.peripherals.timers (null): */ + +/* Content from ti.catalog.arm.cortexm4 (null): */ + +/* Content from ti.catalog (null): */ + +/* Content from ti.catalog.peripherals.hdvicp2 (null): */ + +/* Content from xdc.platform (null): */ + +/* Content from xdc.cfg (null): */ + +/* Content from ti.catalog.arm.cortexm3 (null): */ + +/* Content from ti.catalog.arm.cortexm4.tiva.ce (null): */ + +/* Content from ti.platforms.tiva (null): */ + +/* Content from ti.sysbios (null): */ + +/* Content from ti.drivers.ports (null): */ + +/* Content from ti.mw.fatfs (null): */ + +/* Content from ti.drivers (null): */ + +/* Content from ti.mw.wifi.cc3x00 (null): */ + +/* Content from ti.mw (null): */ + +/* Content from ti.sysbios.hal (null): */ + +/* Content from ti.sysbios.family.arm.m3 (ti/sysbios/family/arm/m3/linkcmd.xdt): */ +-u _c_int00 +--retain "*(.resetVecs)" +ti_sysbios_family_arm_m3_Hwi_nvic = 0xe000e000; + +/* Content from ti.sysbios.knl (null): */ + +/* Content from ti.sysbios.family.arm.lm4 (null): */ + +/* Content from ti.tirtos.utils (null): */ + +/* Content from ti.sysbios.gates (null): */ + +/* Content from ti.sysbios.xdcruntime (null): */ + +/* Content from ti.sysbios.heaps (null): */ + +/* Content from ti.sysbios.utils (null): */ + +/* Content from configPkg (null): */ + +/* Content from xdc.services.io (null): */ + + + +/* + * symbolic aliases for static instance objects + */ +xdc_runtime_Startup__EXECFXN__C = 1; +xdc_runtime_Startup__RESETFXN__C = 1; + + +SECTIONS +{ + .bootVecs: type = DSECT + .vecs: load > 0x20000000 + .resetVecs: load > 0x0 + + + + xdc.meta: type = COPY +} + diff --git a/CCS/mm/Debug/configPkg/package.bld b/CCS/mm/Debug/configPkg/package.bld new file mode 100644 index 0000000..0f01879 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package.bld @@ -0,0 +1,78 @@ +/* THIS IS A GENERATED FILE -- DO NOT EDIT */ + +var targ = xdc.module('ti.targets.arm.elf.M4F'); +/* configuro was told the platform explicitly */ +var platform = 'ti.platforms.tiva:TM4C123GH6PM'; + +/* decide whether to make an assembly or an executable */ +var makeAssembly = false; + + +var Executable = xdc.module('xdc.bld.Executable'); + +var exeOpts = new Executable.Attrs({ + cfgScript: 'C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/gpiointerrupt.cfg', + profile: 'release', + cfgHome: 'configPkg', +}); + +exeOpts.cfgArgs = 'null'; +exeOpts.cfgArgsEncoded = true; + +var exe = Pkg[makeAssembly ? 'addAssembly': 'addExecutable']( + 'gpiointerrupt', + targ, + platform, + exeOpts +); + +/* + * Generate the compiler.opt file + * Do this here instead of during the initial creation of the configuro + * package, because the contents of any config.bld script are unknown + * at that time. Config.bld can't be executed until the XDC build phase. + */ +if (makeAssembly) { + var suffix = targ.dllExt || '.p' + targ.suffix; +} +else { + var suffix = '.p' + targ.suffix; +} + +var thisObj = { + cfg: '../gpiointerrupt.cfg', + outputPath: 'C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg', + exeName: 'gpiointerrupt' + suffix, + exeIntName: 'gpiointerrupt' + suffix.replace('.', '_'), + targ: targ, + linkerCommandFile: 'linker.cmd', + compilerOptFile: 'compiler.opt', + compilerDefsFile: 'compiler.opt' + ".defs", + makeAssembly: makeAssembly +}; +var tmpl = xdc.loadTemplate('xdc/tools/configuro/template/compiler.opt.xdt'); +tmpl.genFile('compiler.opt', thisObj, [], false); + +/* + * Generate the custom makefile. + */ +var tmpl = xdc.loadTemplate('xdc/tools/configuro/template/' + + (makeAssembly? 'custom.mak.asm.xdt' : 'custom.mak.exe.xdt')); +tmpl.genFile('custom.mak', thisObj, [], false); +Pkg.makeEpilogue = "include custom.mak"; + +/* + * Generate the package script. + */ +var tmpl = xdc.loadTemplate('xdc/tools/configuro/template/package.xs.xdt'); +tmpl.genFile('package.xs', thisObj, [], false); + +if (makeAssembly) { +/* + * Generate the linker options into a staging file, so that the presence or + * age of the advertised linker command file can be the makefile trigger to + * rebuild the package from the user's config script. + */ + var tmpl = xdc.loadTemplate('xdc/tools/configuro/template/linker.cmd.asm.xdt'); + tmpl.genFile('linker.cmd.cp', thisObj, [], false); +} diff --git a/CCS/mm/Debug/configPkg/package.mak b/CCS/mm/Debug/configPkg/package.mak new file mode 100644 index 0000000..befd650 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package.mak @@ -0,0 +1,256 @@ +# +# Do not edit this file. This file is generated from +# package.bld. Any modifications to this file will be +# overwritten whenever makefiles are re-generated. +# + +unexport MAKEFILE_LIST +MK_NOGENDEPS := $(filter clean,$(MAKECMDGOALS)) +override PKGDIR = configPkg +XDCINCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\$(space),$(XPKGPATH)))) +XDCCFGDIR = package/cfg/ + +# +# The following dependencies ensure package.mak is rebuilt +# in the event that some included BOM script changes. +# +ifneq (clean,$(MAKECMDGOALS)) +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/utils.js: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/utils.js +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/xdc.tci: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/xdc.tci +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/template.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/template.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/om2.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/om2.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/xmlgen.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/xmlgen.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/xmlgen2.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/xmlgen2.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/Warnings.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/Warnings.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/IPackage.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/IPackage.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/package.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/package.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/Clock.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/Clock.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/Trace.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/Trace.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/bld.js: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/bld.js +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/BuildEnvironment.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/BuildEnvironment.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/PackageContents.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/PackageContents.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/_gen.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/_gen.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Library.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Library.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Executable.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Executable.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Repository.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Repository.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Configuration.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Configuration.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Script.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Script.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Manifest.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Manifest.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Utils.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Utils.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget2.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget2.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget3.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget3.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITargetFilter.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITargetFilter.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/package.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/package.xs +package.mak: config.bld +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/ITarget.xs: +package.mak: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/ITarget.xs +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/C28_large.xs: +package.mak: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/C28_large.xs +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/C28_float.xs: +package.mak: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/C28_float.xs +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/package.xs: +package.mak: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/package.xs +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/IArm.xs: +package.mak: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/IArm.xs +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/package.xs: +package.mak: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/package.xs +package.mak: package.bld +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/compiler.opt.xdt: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/compiler.opt.xdt +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/File.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/File.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/package.xs: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/package.xs +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/compiler.defs.xdt: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/compiler.defs.xdt +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/custom.mak.exe.xdt: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/custom.mak.exe.xdt +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/package.xs.xdt: +package.mak: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/tools/configuro/template/package.xs.xdt +endif + +ti.targets.arm.elf.M4F.rootDir ?= C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS +ti.targets.arm.elf.packageBase ?= C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/ +.PRECIOUS: $(XDCCFGDIR)/%.oem4f +.PHONY: all,em4f .dlls,em4f .executables,em4f test,em4f +all,em4f: .executables,em4f +.executables,em4f: .libraries,em4f +.executables,em4f: .dlls,em4f +.dlls,em4f: .libraries,em4f +.libraries,em4f: .interfaces + @$(RM) $@ + @$(TOUCH) "$@" + +.help:: + @$(ECHO) xdc test,em4f + @$(ECHO) xdc .executables,em4f + @$(ECHO) xdc .libraries,em4f + @$(ECHO) xdc .dlls,em4f + + +all: .executables +.executables: .libraries .dlls +.libraries: .interfaces + +PKGCFGS := $(wildcard package.xs) package/build.cfg +.interfaces: package/package.xdc.inc package/package.defs.h package.xdc $(PKGCFGS) + +-include package/package.xdc.dep +package/%.xdc.inc package/%_configPkg.c package/%.defs.h: %.xdc $(PKGCFGS) + @$(MSG) generating interfaces for package configPkg" (because $@ is older than $(firstword $?))" ... + $(XSRUN) -f xdc/services/intern/cmd/build.xs $(MK_IDLOPTS) -m package/package.xdc.dep -i package/package.xdc.inc package.xdc + +.dlls,em4f .dlls: gpiointerrupt.pem4f + +-include package/cfg/gpiointerrupt_pem4f.mak +-include package/cfg/gpiointerrupt_pem4f.cfg.mak +ifeq (,$(MK_NOGENDEPS)) +-include package/cfg/gpiointerrupt_pem4f.dep +endif +gpiointerrupt.pem4f: package/cfg/gpiointerrupt_pem4f.xdl + @ + + +ifeq (,$(wildcard .libraries,em4f)) +gpiointerrupt.pem4f package/cfg/gpiointerrupt_pem4f.c: .libraries,em4f +endif + +package/cfg/gpiointerrupt_pem4f.c package/cfg/gpiointerrupt_pem4f.h package/cfg/gpiointerrupt_pem4f.xdl: override _PROG_NAME := gpiointerrupt.xem4f +package/cfg/gpiointerrupt_pem4f.c: package/cfg/gpiointerrupt_pem4f.cfg +package/cfg/gpiointerrupt_pem4f.xdc.inc: package/cfg/gpiointerrupt_pem4f.xdl +package/cfg/gpiointerrupt_pem4f.xdl package/cfg/gpiointerrupt_pem4f.c: .interfaces + +clean:: clean,em4f + -$(RM) package/cfg/gpiointerrupt_pem4f.cfg + -$(RM) package/cfg/gpiointerrupt_pem4f.dep + -$(RM) package/cfg/gpiointerrupt_pem4f.c + -$(RM) package/cfg/gpiointerrupt_pem4f.xdc.inc + +clean,em4f:: + -$(RM) gpiointerrupt.pem4f +.executables,em4f .executables: gpiointerrupt.xem4f + +gpiointerrupt.xem4f: |gpiointerrupt.pem4f + +-include package/cfg/gpiointerrupt.xem4f.mak +gpiointerrupt.xem4f: package/cfg/gpiointerrupt_pem4f.oem4f + $(RM) $@ + @$(MSG) lnkem4f $@ ... + $(RM) $(XDCCFGDIR)/$@.map + $(ti.targets.arm.elf.M4F.rootDir)/bin/armcl -fs $(XDCCFGDIR)$(dir $@). -q -u _c_int00 --silicon_version=7M4 -z --strict_compatibility=on -o $@ package/cfg/gpiointerrupt_pem4f.oem4f package/cfg/gpiointerrupt_pem4f.xdl -w -c -m $(XDCCFGDIR)/$@.map -l $(ti.targets.arm.elf.M4F.rootDir)/lib/libc.a + +gpiointerrupt.xem4f: export C_DIR= +gpiointerrupt.xem4f: PATH:=$(ti.targets.arm.elf.M4F.rootDir)/bin/;$(PATH) +gpiointerrupt.xem4f: Path:=$(ti.targets.arm.elf.M4F.rootDir)/bin/;$(PATH) + +gpiointerrupt.test test,em4f test: gpiointerrupt.xem4f.test + +gpiointerrupt.xem4f.test:: gpiointerrupt.xem4f +ifeq (,$(_TESTLEVEL)) + @$(MAKE) -R -r --no-print-directory -f $(XDCROOT)/packages/xdc/bld/xdc.mak _TESTLEVEL=1 gpiointerrupt.xem4f.test +else + @$(MSG) running $< ... + $(call EXEC.gpiointerrupt.xem4f, ) +endif + +clean,em4f:: + -$(RM) $(wildcard .tmp,gpiointerrupt.xem4f,*) + + +clean:: clean,em4f + +clean,em4f:: + -$(RM) gpiointerrupt.xem4f +%,copy: + @$(if $<,,$(MSG) don\'t know how to build $*; exit 1) + @$(MSG) cp $< $@ + $(RM) $@ + $(CP) $< $@ +gpiointerrupt_pem4f.oem4f,copy : package/cfg/gpiointerrupt_pem4f.oem4f +gpiointerrupt_pem4f.sem4f,copy : package/cfg/gpiointerrupt_pem4f.sem4f + +$(XDCCFGDIR)%.c $(XDCCFGDIR)%.h $(XDCCFGDIR)%.xdl: $(XDCCFGDIR)%.cfg $(XDCROOT)/packages/xdc/cfg/Main.xs | .interfaces + @$(MSG) "configuring $(_PROG_NAME) from $< ..." + $(CONFIG) $(_PROG_XSOPTS) xdc.cfg $(_PROG_NAME) $(XDCCFGDIR)$*.cfg $(XDCCFGDIR)$* + +.PHONY: release,configPkg +ifeq (,$(MK_NOGENDEPS)) +-include package/rel/configPkg.tar.dep +endif +package/rel/configPkg/configPkg/package/package.rel.xml: package/package.bld.xml +package/rel/configPkg/configPkg/package/package.rel.xml: package/build.cfg +package/rel/configPkg/configPkg/package/package.rel.xml: package/package.xdc.inc +package/rel/configPkg/configPkg/package/package.rel.xml: .force + @$(MSG) generating external release references $@ ... + $(XS) $(JSENV) -f $(XDCROOT)/packages/xdc/bld/rel.js $(MK_RELOPTS) . $@ + +configPkg.tar: package/rel/configPkg.xdc.inc package/rel/configPkg/configPkg/package/package.rel.xml + @$(MSG) making release file $@ "(because of $(firstword $?))" ... + -$(RM) $@ + $(call MKRELTAR,package/rel/configPkg.xdc.inc,package/rel/configPkg.tar.dep) + + +release release,configPkg: all configPkg.tar +clean:: .clean + -$(RM) configPkg.tar + -$(RM) package/rel/configPkg.xdc.inc + -$(RM) package/rel/configPkg.tar.dep + +clean:: .clean + -$(RM) .libraries $(wildcard .libraries,*) +clean:: + -$(RM) .dlls $(wildcard .dlls,*) +# +# The following clean rule removes user specified +# generated files or directories. +# + +ifneq (clean,$(MAKECMDGOALS)) +ifeq (,$(wildcard package)) + $(shell $(MKDIR) package) +endif +ifeq (,$(wildcard package/cfg)) + $(shell $(MKDIR) package/cfg) +endif +ifeq (,$(wildcard package/lib)) + $(shell $(MKDIR) package/lib) +endif +ifeq (,$(wildcard package/rel)) + $(shell $(MKDIR) package/rel) +endif +ifeq (,$(wildcard package/internal)) + $(shell $(MKDIR) package/internal) +endif +endif +clean:: + -$(RMDIR) package + +include custom.mak diff --git a/CCS/mm/Debug/configPkg/package.xdc b/CCS/mm/Debug/configPkg/package.xdc new file mode 100644 index 0000000..2a51d45 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package.xdc @@ -0,0 +1,7 @@ +/*! + * Package generated by xdc.tools.configuro + * + * @_nodoc + */ +package configPkg { +} diff --git a/CCS/mm/Debug/configPkg/package.xs b/CCS/mm/Debug/configPkg/package.xs new file mode 100644 index 0000000..373d44f --- /dev/null +++ b/CCS/mm/Debug/configPkg/package.xs @@ -0,0 +1,20 @@ +/* THIS IS A GENERATED FILE -- DO NOT EDIT */ + +/* return the names of the generated config objects */ +function getLibs(prog) { + /* for programs, push the generated config object file into the + * generated linker command file. + */ + /* replace the last period in the name by an underscore */ + var name = "package/cfg/" + prog.name.replace(/\.([^.]*)$/, "_$1"); + /* base is a hack until we add cfgName to Program */ + var base = "package/cfg/" + prog.name.replace(/\.([^.]*)$/, ""); + var suffix = prog.build.target.suffix; + + var libs = [ +// name + '.o' + suffix, + base + '_p' + suffix + '.o' + suffix + ]; + + return libs.join(';'); +} diff --git a/CCS/mm/Debug/configPkg/package/.vers_b160 b/CCS/mm/Debug/configPkg/package/.vers_b160 new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/package/.vers_g180 b/CCS/mm/Debug/configPkg/package/.vers_g180 new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/package/.vers_r170 b/CCS/mm/Debug/configPkg/package/.vers_r170 new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/package/.xdc-B21 b/CCS/mm/Debug/configPkg/package/.xdc-B21 new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/package/build.cfg b/CCS/mm/Debug/configPkg/package/build.cfg new file mode 100644 index 0000000..5ec1eb1 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/build.cfg @@ -0,0 +1,9 @@ +if (pkg.$vers.length >= 3) { + pkg.$vers.push(Packages.xdc.services.global.Vers.getDate(xdc.csd() + '/..')); +} + +pkg.build.libraries = [ +]; + +pkg.build.libDesc = [ +]; diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt.xem4f.mak b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt.xem4f.mak new file mode 100644 index 0000000..0708364 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt.xem4f.mak @@ -0,0 +1,11 @@ +# +# Do not edit this file. This file is generated from +# package.bld. Any modifications to this file will be +# overwritten whenever makefiles are re-generated. +# +# target compatibility key = ti.targets.arm.elf.M4F{1,0,18.12,4 +# +gpiointerrupt.xem4f: package/cfg/gpiointerrupt.xem4f.mak + +clean:: + -$(RM) package/cfg/gpiointerrupt.xem4f.mak diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.c b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.c new file mode 100644 index 0000000..11ded26 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.c @@ -0,0 +1,16996 @@ +/* + * Do not modify this file; it is automatically + * generated and any modifications will be overwritten. + * + * @(#) xdc-B21 + */ + +#define __nested__ +#define __config__ + +#include + +/* + * ======== GENERATED SECTIONS ======== + * + * MODULE INCLUDES + * + * INTERNALS + * INHERITS + * VTABLE + * PATCH TABLE + * DECLARATIONS + * OBJECT OFFSETS + * TEMPLATES + * INITIALIZERS + * FUNCTION STUBS + * PROXY BODY + * OBJECT DESCRIPTOR + * VIRTUAL FUNCTIONS + * SYSTEM FUNCTIONS + * PRAGMAS + * + * INITIALIZATION ENTRY POINT + * PROGRAM GLOBALS + * CLINK DIRECTIVES + */ + + +/* + * ======== MODULE INCLUDES ======== + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * ======== ti.catalog.arm.cortexm4.tiva.ce.Boot INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.BIOS INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.BIOS_RtsGateProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_BIOS_RtsGateProxy_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_BIOS_RtsGateProxy_Module__; + +/* Module__root__V */ +extern ti_sysbios_BIOS_RtsGateProxy_Module__ ti_sysbios_BIOS_RtsGateProxy_Module__root__V; + +/* @@@ ti_sysbios_knl_Queue_Object__ */ +typedef struct ti_sysbios_knl_Queue_Object__ { + ti_sysbios_knl_Queue_Elem elem; +} ti_sysbios_knl_Queue_Object__; + +/* @@@ ti_sysbios_knl_Queue_Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_knl_Queue_Object__ obj; +} ti_sysbios_knl_Queue_Object2__; + +/* @@@ ti_sysbios_knl_Semaphore_Object__ */ +typedef struct ti_sysbios_knl_Semaphore_Object__ { + ti_sysbios_knl_Event_Handle event; + xdc_UInt eventId; + ti_sysbios_knl_Semaphore_Mode mode; + volatile xdc_UInt16 count; + ti_sysbios_knl_Queue_Object__ Object_field_pendQ; +} ti_sysbios_knl_Semaphore_Object__; + +/* @@@ ti_sysbios_knl_Semaphore_Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_knl_Semaphore_Object__ obj; +} ti_sysbios_knl_Semaphore_Object2__; + +/* Object__ */ +typedef struct ti_sysbios_gates_GateMutex_Object__ { + const ti_sysbios_gates_GateMutex_Fxns__ *__fxns; + ti_sysbios_knl_Task_Handle owner; + ti_sysbios_knl_Semaphore_Object__ Object_field_sem; +} ti_sysbios_gates_GateMutex_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_gates_GateMutex_Object__ obj; +} ti_sysbios_gates_GateMutex_Object2__; + +/* Object */ +typedef ti_sysbios_gates_GateMutex_Object__ ti_sysbios_BIOS_RtsGateProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_BIOS_RtsGateProxy_Object__ obj; +} ti_sysbios_BIOS_RtsGateProxy_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_BIOS_RtsGateProxy___VERS + #define ti_sysbios_BIOS_RtsGateProxy___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_BIOS_RtsGateProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.family.arm.lm4.Timer INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_family_arm_lm4_Timer_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_family_arm_lm4_Timer_Module__; + +/* Module__root__V */ +extern ti_sysbios_family_arm_lm4_Timer_Module__ ti_sysbios_family_arm_lm4_Timer_Module__root__V; + +/* Object__ */ +typedef struct ti_sysbios_family_arm_lm4_Timer_Object__ { + const ti_sysbios_family_arm_lm4_Timer_Fxns__ *__fxns; + xdc_Bool staticInst; + xdc_Int id; + ti_sysbios_family_arm_lm4_Timer_RunMode runMode; + ti_sysbios_family_arm_lm4_Timer_StartMode startMode; + xdc_UInt period; + ti_sysbios_family_arm_lm4_Timer_PeriodType periodType; + xdc_UInt intNum; + xdc_UArg arg; + ti_sysbios_family_arm_m3_Hwi_FuncPtr tickFxn; + xdc_runtime_Types_FreqHz extFreq; + ti_sysbios_family_arm_m3_Hwi_Handle hwi; + xdc_UInt prevThreshold; + xdc_UInt rollovers; + xdc_UInt savedCurrCount; + xdc_Bool altclk; +} ti_sysbios_family_arm_lm4_Timer_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_family_arm_lm4_Timer_Object__ obj; +} ti_sysbios_family_arm_lm4_Timer_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_family_arm_lm4_Timer___VERS + #define ti_sysbios_family_arm_lm4_Timer___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_family_arm_lm4_Timer___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.family.arm.m3.Hwi INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_family_arm_m3_Hwi_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_family_arm_m3_Hwi_Module__; + +/* Module__root__V */ +extern ti_sysbios_family_arm_m3_Hwi_Module__ ti_sysbios_family_arm_m3_Hwi_Module__root__V; + +/* Object__ */ +typedef struct ti_sysbios_family_arm_m3_Hwi_Object__ { + const ti_sysbios_family_arm_m3_Hwi_Fxns__ *__fxns; + xdc_UArg arg; + ti_sysbios_family_arm_m3_Hwi_FuncPtr fxn; + ti_sysbios_family_arm_m3_Hwi_Irp irp; + xdc_UInt8 priority; + xdc_Int16 intNum; + __TA_ti_sysbios_family_arm_m3_Hwi_Instance_State__hookEnv hookEnv; +} ti_sysbios_family_arm_m3_Hwi_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_family_arm_m3_Hwi_Object__ obj; +} ti_sysbios_family_arm_m3_Hwi_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_family_arm_m3_Hwi___VERS + #define ti_sysbios_family_arm_m3_Hwi___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_family_arm_m3_Hwi___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.family.arm.m3.IntrinsicsSupport INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.family.arm.m3.TaskSupport INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.gates.GateHwi INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_gates_GateHwi_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_gates_GateHwi_Module__; + +/* Module__root__V */ +extern ti_sysbios_gates_GateHwi_Module__ ti_sysbios_gates_GateHwi_Module__root__V; + +/* Object__ */ +typedef struct ti_sysbios_gates_GateHwi_Object__ { + const ti_sysbios_gates_GateHwi_Fxns__ *__fxns; +} ti_sysbios_gates_GateHwi_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_gates_GateHwi_Object__ obj; +} ti_sysbios_gates_GateHwi_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_gates_GateHwi___VERS + #define ti_sysbios_gates_GateHwi___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_gates_GateHwi___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.gates.GateMutex INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_gates_GateMutex_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_gates_GateMutex_Module__; + +/* Module__root__V */ +extern ti_sysbios_gates_GateMutex_Module__ ti_sysbios_gates_GateMutex_Module__root__V; + +/* <-- ti_sysbios_gates_GateMutex_Object */ + +/* __ParamsPtr */ +#ifdef ti_sysbios_gates_GateMutex___VERS + #define ti_sysbios_gates_GateMutex___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_gates_GateMutex___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.hal.Hwi INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_hal_Hwi_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_hal_Hwi_Module__; + +/* Module__root__V */ +extern ti_sysbios_hal_Hwi_Module__ ti_sysbios_hal_Hwi_Module__root__V; + +/* Object__ */ +typedef struct ti_sysbios_hal_Hwi_Object__ { + const ti_sysbios_hal_Hwi_Fxns__ *__fxns; + ti_sysbios_hal_Hwi_HwiProxy_Handle pi; +} ti_sysbios_hal_Hwi_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_hal_Hwi_Object__ obj; +} ti_sysbios_hal_Hwi_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_hal_Hwi___VERS + #define ti_sysbios_hal_Hwi___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_hal_Hwi___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.hal.Hwi_HwiProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_hal_Hwi_HwiProxy_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_hal_Hwi_HwiProxy_Module__; + +/* Module__root__V */ +extern ti_sysbios_hal_Hwi_HwiProxy_Module__ ti_sysbios_hal_Hwi_HwiProxy_Module__root__V; + +/* <-- ti_sysbios_family_arm_m3_Hwi_Object */ + +/* Object */ +typedef ti_sysbios_family_arm_m3_Hwi_Object__ ti_sysbios_hal_Hwi_HwiProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_hal_Hwi_HwiProxy_Object__ obj; +} ti_sysbios_hal_Hwi_HwiProxy_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_hal_Hwi_HwiProxy___VERS + #define ti_sysbios_hal_Hwi_HwiProxy___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_hal_Hwi_HwiProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.heaps.HeapMem INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_heaps_HeapMem_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_heaps_HeapMem_Module__; + +/* Module__root__V */ +extern ti_sysbios_heaps_HeapMem_Module__ ti_sysbios_heaps_HeapMem_Module__root__V; + +/* Object__ */ +typedef struct ti_sysbios_heaps_HeapMem_Object__ { + const ti_sysbios_heaps_HeapMem_Fxns__ *__fxns; + xdc_runtime_Memory_Size align; + __TA_ti_sysbios_heaps_HeapMem_Instance_State__buf buf; + ti_sysbios_heaps_HeapMem_Header head; + xdc_SizeT minBlockAlign; +} ti_sysbios_heaps_HeapMem_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_heaps_HeapMem_Object__ obj; +} ti_sysbios_heaps_HeapMem_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_heaps_HeapMem___VERS + #define ti_sysbios_heaps_HeapMem___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_heaps_HeapMem___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.heaps.HeapMem_Module_GateProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__; + +/* Module__root__V */ +extern ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__ ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__root__V; + +/* <-- ti_sysbios_gates_GateMutex_Object */ + +/* Object */ +typedef ti_sysbios_gates_GateMutex_Object__ ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__ obj; +} ti_sysbios_heaps_HeapMem_Module_GateProxy_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_heaps_HeapMem_Module_GateProxy___VERS + #define ti_sysbios_heaps_HeapMem_Module_GateProxy___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_heaps_HeapMem_Module_GateProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Clock INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_knl_Clock_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_knl_Clock_Module__; + +/* Module__root__V */ +extern ti_sysbios_knl_Clock_Module__ ti_sysbios_knl_Clock_Module__root__V; + +/* <-- ti_sysbios_knl_Queue_Object */ + +/* Object__ */ +typedef struct ti_sysbios_knl_Clock_Object__ { + ti_sysbios_knl_Queue_Elem elem; + xdc_UInt32 timeout; + xdc_UInt32 currTimeout; + xdc_UInt32 period; + volatile xdc_Bool active; + ti_sysbios_knl_Clock_FuncPtr fxn; + xdc_UArg arg; +} ti_sysbios_knl_Clock_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_knl_Clock_Object__ obj; +} ti_sysbios_knl_Clock_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_knl_Clock___VERS + #define ti_sysbios_knl_Clock___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_knl_Clock___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Clock_TimerProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_knl_Clock_TimerProxy_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_knl_Clock_TimerProxy_Module__; + +/* Module__root__V */ +extern ti_sysbios_knl_Clock_TimerProxy_Module__ ti_sysbios_knl_Clock_TimerProxy_Module__root__V; + +/* <-- ti_sysbios_family_arm_lm4_Timer_Object */ + +/* Object */ +typedef ti_sysbios_family_arm_lm4_Timer_Object__ ti_sysbios_knl_Clock_TimerProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_knl_Clock_TimerProxy_Object__ obj; +} ti_sysbios_knl_Clock_TimerProxy_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_knl_Clock_TimerProxy___VERS + #define ti_sysbios_knl_Clock_TimerProxy___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_knl_Clock_TimerProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Idle INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.knl.Intrinsics INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.knl.Intrinsics_SupportProxy INTERNALS ======== + */ + + +/* + * ======== ti.sysbios.knl.Queue INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_knl_Queue_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_knl_Queue_Module__; + +/* Module__root__V */ +extern ti_sysbios_knl_Queue_Module__ ti_sysbios_knl_Queue_Module__root__V; + +/* <-- ti_sysbios_knl_Queue_Object */ + +/* __ParamsPtr */ +#ifdef ti_sysbios_knl_Queue___VERS + #define ti_sysbios_knl_Queue___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_knl_Queue___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Semaphore INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_knl_Semaphore_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_knl_Semaphore_Module__; + +/* Module__root__V */ +extern ti_sysbios_knl_Semaphore_Module__ ti_sysbios_knl_Semaphore_Module__root__V; + +/* <-- ti_sysbios_knl_Semaphore_Object */ + +/* __ParamsPtr */ +#ifdef ti_sysbios_knl_Semaphore___VERS + #define ti_sysbios_knl_Semaphore___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_knl_Semaphore___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Swi INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_knl_Swi_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_knl_Swi_Module__; + +/* Module__root__V */ +extern ti_sysbios_knl_Swi_Module__ ti_sysbios_knl_Swi_Module__root__V; + +/* Object__ */ +typedef struct ti_sysbios_knl_Swi_Object__ { + ti_sysbios_knl_Queue_Elem qElem; + ti_sysbios_knl_Swi_FuncPtr fxn; + xdc_UArg arg0; + xdc_UArg arg1; + xdc_UInt priority; + xdc_UInt mask; + xdc_Bool posted; + xdc_UInt initTrigger; + xdc_UInt trigger; + ti_sysbios_knl_Queue_Handle readyQ; + __TA_ti_sysbios_knl_Swi_Instance_State__hookEnv hookEnv; +} ti_sysbios_knl_Swi_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_knl_Swi_Object__ obj; +} ti_sysbios_knl_Swi_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_knl_Swi___VERS + #define ti_sysbios_knl_Swi___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_knl_Swi___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Task INTERNALS ======== + */ + +/* Module__ */ +typedef struct ti_sysbios_knl_Task_Module__ { + xdc_runtime_Types_Link link; +} ti_sysbios_knl_Task_Module__; + +/* Module__root__V */ +extern ti_sysbios_knl_Task_Module__ ti_sysbios_knl_Task_Module__root__V; + +/* <-- ti_sysbios_knl_Queue_Object */ + +/* Object__ */ +typedef struct ti_sysbios_knl_Task_Object__ { + ti_sysbios_knl_Queue_Elem qElem; + volatile xdc_Int priority; + xdc_UInt mask; + xdc_Ptr context; + ti_sysbios_knl_Task_Mode mode; + ti_sysbios_knl_Task_PendElem *pendElem; + xdc_SizeT stackSize; + __TA_ti_sysbios_knl_Task_Instance_State__stack stack; + xdc_runtime_IHeap_Handle stackHeap; + ti_sysbios_knl_Task_FuncPtr fxn; + xdc_UArg arg0; + xdc_UArg arg1; + xdc_Ptr env; + __TA_ti_sysbios_knl_Task_Instance_State__hookEnv hookEnv; + xdc_Bool vitalTaskFlag; + ti_sysbios_knl_Queue_Handle readyQ; + xdc_UInt curCoreId; + xdc_UInt affinity; +} ti_sysbios_knl_Task_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + ti_sysbios_knl_Task_Object__ obj; +} ti_sysbios_knl_Task_Object2__; + +/* __ParamsPtr */ +#ifdef ti_sysbios_knl_Task___VERS + #define ti_sysbios_knl_Task___ParamsPtr xdc_UChar* +#else + #define ti_sysbios_knl_Task___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== ti.sysbios.knl.Task_SupportProxy INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Assert INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Core INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Defaults INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Diags INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Error INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Gate INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Log INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Main INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Main_Module_GateProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct xdc_runtime_Main_Module_GateProxy_Module__ { + xdc_runtime_Types_Link link; +} xdc_runtime_Main_Module_GateProxy_Module__; + +/* Module__root__V */ +extern xdc_runtime_Main_Module_GateProxy_Module__ xdc_runtime_Main_Module_GateProxy_Module__root__V; + +/* <-- ti_sysbios_gates_GateHwi_Object */ + +/* Object */ +typedef ti_sysbios_gates_GateHwi_Object__ xdc_runtime_Main_Module_GateProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + xdc_runtime_Main_Module_GateProxy_Object__ obj; +} xdc_runtime_Main_Module_GateProxy_Object2__; + +/* __ParamsPtr */ +#ifdef xdc_runtime_Main_Module_GateProxy___VERS + #define xdc_runtime_Main_Module_GateProxy___ParamsPtr xdc_UChar* +#else + #define xdc_runtime_Main_Module_GateProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== xdc.runtime.Memory INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Memory_HeapProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct xdc_runtime_Memory_HeapProxy_Module__ { + xdc_runtime_Types_Link link; +} xdc_runtime_Memory_HeapProxy_Module__; + +/* Module__root__V */ +extern xdc_runtime_Memory_HeapProxy_Module__ xdc_runtime_Memory_HeapProxy_Module__root__V; + +/* <-- ti_sysbios_heaps_HeapMem_Object */ + +/* Object */ +typedef ti_sysbios_heaps_HeapMem_Object__ xdc_runtime_Memory_HeapProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + xdc_runtime_Memory_HeapProxy_Object__ obj; +} xdc_runtime_Memory_HeapProxy_Object2__; + +/* __ParamsPtr */ +#ifdef xdc_runtime_Memory_HeapProxy___VERS + #define xdc_runtime_Memory_HeapProxy___ParamsPtr xdc_UChar* +#else + #define xdc_runtime_Memory_HeapProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== xdc.runtime.Registry INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Startup INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.SysMin INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.System INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.System_Module_GateProxy INTERNALS ======== + */ + +/* Module__ */ +typedef struct xdc_runtime_System_Module_GateProxy_Module__ { + xdc_runtime_Types_Link link; +} xdc_runtime_System_Module_GateProxy_Module__; + +/* Module__root__V */ +extern xdc_runtime_System_Module_GateProxy_Module__ xdc_runtime_System_Module_GateProxy_Module__root__V; + +/* <-- ti_sysbios_gates_GateHwi_Object */ + +/* Object */ +typedef ti_sysbios_gates_GateHwi_Object__ xdc_runtime_System_Module_GateProxy_Object__; + +/* Object2__ */ +typedef struct { + xdc_runtime_Types_InstHdr hdr; + xdc_runtime_System_Module_GateProxy_Object__ obj; +} xdc_runtime_System_Module_GateProxy_Object2__; + +/* __ParamsPtr */ +#ifdef xdc_runtime_System_Module_GateProxy___VERS + #define xdc_runtime_System_Module_GateProxy___ParamsPtr xdc_UChar* +#else + #define xdc_runtime_System_Module_GateProxy___ParamsPtr xdc_Ptr +#endif + + +/* + * ======== xdc.runtime.System_SupportProxy INTERNALS ======== + */ + + +/* + * ======== xdc.runtime.Text INTERNALS ======== + */ + + +/* + * ======== INHERITS ======== + */ + +#pragma DATA_SECTION(xdc_runtime_IHeap_Interface__BASE__C, ".const:xdc_runtime_IHeap_Interface__BASE__C"); +__FAR__ const xdc_runtime_Types_Base xdc_runtime_IHeap_Interface__BASE__C = {(void *)&xdc_runtime_IModule_Interface__BASE__C}; + +#pragma DATA_SECTION(xdc_runtime_ISystemSupport_Interface__BASE__C, ".const:xdc_runtime_ISystemSupport_Interface__BASE__C"); +__FAR__ const xdc_runtime_Types_Base xdc_runtime_ISystemSupport_Interface__BASE__C = {(void *)&xdc_runtime_IModule_Interface__BASE__C}; + +#pragma DATA_SECTION(ti_sysbios_interfaces_IIntrinsicsSupport_Interface__BASE__C, ".const:ti_sysbios_interfaces_IIntrinsicsSupport_Interface__BASE__C"); +__FAR__ const xdc_runtime_Types_Base ti_sysbios_interfaces_IIntrinsicsSupport_Interface__BASE__C = {(void *)&xdc_runtime_IModule_Interface__BASE__C}; + +#pragma DATA_SECTION(xdc_runtime_IGateProvider_Interface__BASE__C, ".const:xdc_runtime_IGateProvider_Interface__BASE__C"); +__FAR__ const xdc_runtime_Types_Base xdc_runtime_IGateProvider_Interface__BASE__C = {(void *)&xdc_runtime_IModule_Interface__BASE__C}; + +#pragma DATA_SECTION(xdc_runtime_IModule_Interface__BASE__C, ".const:xdc_runtime_IModule_Interface__BASE__C"); +__FAR__ const xdc_runtime_Types_Base xdc_runtime_IModule_Interface__BASE__C = {0}; + + +/* + * ======== ti.sysbios.family.arm.m3.IntrinsicsSupport VTABLE ======== + */ + +/* Module__FXNS__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__FXNS__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__FXNS__C"); +const ti_sysbios_family_arm_m3_IntrinsicsSupport_Fxns__ ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__FXNS__C = { + (void *)&ti_sysbios_interfaces_IIntrinsicsSupport_Interface__BASE__C, /* __base */ + &ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__FXNS__C.__sfxns, /* __sysp */ + ti_sysbios_family_arm_m3_IntrinsicsSupport_maxbit__E, + { + NULL, /* __create */ + NULL, /* __delete */ + NULL, /* __label */ + 0x8026, /* __mid */ + } /* __sfxns */ +}; + + +/* + * ======== ti.sysbios.gates.GateHwi VTABLE ======== + */ + +/* Module__FXNS__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__FXNS__C, ".const:ti_sysbios_gates_GateHwi_Module__FXNS__C"); +const ti_sysbios_gates_GateHwi_Fxns__ ti_sysbios_gates_GateHwi_Module__FXNS__C = { + (void *)&xdc_runtime_IGateProvider_Interface__BASE__C, /* __base */ + &ti_sysbios_gates_GateHwi_Module__FXNS__C.__sfxns, /* __sysp */ + ti_sysbios_gates_GateHwi_query__E, + ti_sysbios_gates_GateHwi_enter__E, + ti_sysbios_gates_GateHwi_leave__E, + { + ti_sysbios_gates_GateHwi_Object__create__S, + ti_sysbios_gates_GateHwi_Object__delete__S, + ti_sysbios_gates_GateHwi_Handle__label__S, + 0x8029, /* __mid */ + } /* __sfxns */ +}; + + +/* + * ======== ti.sysbios.gates.GateMutex VTABLE ======== + */ + +/* Module__FXNS__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__FXNS__C, ".const:ti_sysbios_gates_GateMutex_Module__FXNS__C"); +const ti_sysbios_gates_GateMutex_Fxns__ ti_sysbios_gates_GateMutex_Module__FXNS__C = { + (void *)&xdc_runtime_IGateProvider_Interface__BASE__C, /* __base */ + &ti_sysbios_gates_GateMutex_Module__FXNS__C.__sfxns, /* __sysp */ + ti_sysbios_gates_GateMutex_query__E, + ti_sysbios_gates_GateMutex_enter__E, + ti_sysbios_gates_GateMutex_leave__E, + { + ti_sysbios_gates_GateMutex_Object__create__S, + ti_sysbios_gates_GateMutex_Object__delete__S, + ti_sysbios_gates_GateMutex_Handle__label__S, + 0x802a, /* __mid */ + } /* __sfxns */ +}; + + +/* + * ======== ti.sysbios.heaps.HeapMem VTABLE ======== + */ + +/* Module__FXNS__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__FXNS__C, ".const:ti_sysbios_heaps_HeapMem_Module__FXNS__C"); +const ti_sysbios_heaps_HeapMem_Fxns__ ti_sysbios_heaps_HeapMem_Module__FXNS__C = { + (void *)&xdc_runtime_IHeap_Interface__BASE__C, /* __base */ + &ti_sysbios_heaps_HeapMem_Module__FXNS__C.__sfxns, /* __sysp */ + ti_sysbios_heaps_HeapMem_alloc__E, + ti_sysbios_heaps_HeapMem_free__E, + ti_sysbios_heaps_HeapMem_isBlocking__E, + ti_sysbios_heaps_HeapMem_getStats__E, + { + ti_sysbios_heaps_HeapMem_Object__create__S, + ti_sysbios_heaps_HeapMem_Object__delete__S, + ti_sysbios_heaps_HeapMem_Handle__label__S, + 0x802c, /* __mid */ + } /* __sfxns */ +}; + + +/* + * ======== xdc.runtime.SysMin VTABLE ======== + */ + +/* Module__FXNS__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__FXNS__C, ".const:xdc_runtime_SysMin_Module__FXNS__C"); +const xdc_runtime_SysMin_Fxns__ xdc_runtime_SysMin_Module__FXNS__C = { + (void *)&xdc_runtime_ISystemSupport_Interface__BASE__C, /* __base */ + &xdc_runtime_SysMin_Module__FXNS__C.__sfxns, /* __sysp */ + xdc_runtime_SysMin_abort__E, + xdc_runtime_SysMin_exit__E, + xdc_runtime_SysMin_flush__E, + xdc_runtime_SysMin_putch__E, + xdc_runtime_SysMin_ready__E, + { + NULL, /* __create */ + NULL, /* __delete */ + NULL, /* __label */ + 0x800e, /* __mid */ + } /* __sfxns */ +}; + + +/* + * ======== ti.catalog.arm.cortexm4.tiva.ce.Boot DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.BIOS DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct ti_sysbios_BIOS_Module_State__ { + xdc_runtime_Types_FreqHz cpuFreq; + xdc_UInt rtsGateCount; + xdc_IArg rtsGateKey; + ti_sysbios_BIOS_RtsGateProxy_Handle rtsGate; + ti_sysbios_BIOS_ThreadType threadType; + __TA_ti_sysbios_BIOS_Module_State__smpThreadType smpThreadType; + volatile ti_sysbios_BIOS_StartFuncPtr startFunc; + volatile ti_sysbios_BIOS_ExitFuncPtr exitFunc; +} ti_sysbios_BIOS_Module_State__; + +/* --> ti_sysbios_BIOS_startFunc */ +extern xdc_Void ti_sysbios_BIOS_startFunc(xdc_Void); + +/* --> ti_sysbios_BIOS_exitFunc */ +extern xdc_Void ti_sysbios_BIOS_exitFunc(xdc_Int); + +/* Module__state__V */ +ti_sysbios_BIOS_Module_State__ ti_sysbios_BIOS_Module__state__V; + + +/* + * ======== ti.sysbios.BIOS_RtsGateProxy DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.family.arm.lm4.Timer DECLARATIONS ======== + */ + +/* Object__table__V */ +ti_sysbios_family_arm_lm4_Timer_Object__ ti_sysbios_family_arm_lm4_Timer_Object__table__V[1]; + +/* Module_State__ */ +typedef struct ti_sysbios_family_arm_lm4_Timer_Module_State__ { + xdc_UInt availMask; + __TA_ti_sysbios_family_arm_lm4_Timer_Module_State__device device; + __TA_ti_sysbios_family_arm_lm4_Timer_Module_State__handles handles; +} ti_sysbios_family_arm_lm4_Timer_Module_State__; + +/* --> ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A */ +__T1_ti_sysbios_family_arm_lm4_Timer_Module_State__device ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A[6]; + +/* --> ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A */ +__T1_ti_sysbios_family_arm_lm4_Timer_Module_State__handles ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A[6]; + +/* Module__state__V */ +ti_sysbios_family_arm_lm4_Timer_Module_State__ ti_sysbios_family_arm_lm4_Timer_Module__state__V; + +/* --> ti_sysbios_family_arm_lm4_Timer_enableTiva */ +extern xdc_Void ti_sysbios_family_arm_lm4_Timer_enableTiva(xdc_Int); + +/* --> ti_sysbios_family_arm_lm4_Timer_disableTiva */ +extern xdc_Void ti_sysbios_family_arm_lm4_Timer_disableTiva(xdc_Int); + + +/* + * ======== ti.sysbios.family.arm.m3.Hwi DECLARATIONS ======== + */ + +/* Object__table__V */ +ti_sysbios_family_arm_m3_Hwi_Object__ ti_sysbios_family_arm_m3_Hwi_Object__table__V[1]; + +/* Module_State__ */ +typedef struct ti_sysbios_family_arm_m3_Hwi_Module_State__ { + xdc_Char *taskSP; + __TA_ti_sysbios_family_arm_m3_Hwi_Module_State__excActive excActive; + __TA_ti_sysbios_family_arm_m3_Hwi_Module_State__excContext excContext; + __TA_ti_sysbios_family_arm_m3_Hwi_Module_State__excStack excStack; + xdc_Ptr isrStack; + xdc_Ptr isrStackBase; + xdc_SizeT isrStackSize; + xdc_Ptr vectorTableBase; + xdc_UInt swiTaskKeys; + xdc_Ptr dispatchTable; + volatile xdc_Bool vnvicFlushRequired; + __TA_ti_sysbios_family_arm_m3_Hwi_Module_State__intAffinity intAffinity; + __TA_ti_sysbios_family_arm_m3_Hwi_Module_State__intAffinityMasks intAffinityMasks; +} ti_sysbios_family_arm_m3_Hwi_Module_State__; + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A */ +__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excActive ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A[1]; + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A */ +__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excContext ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A[1]; + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A */ +__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excStack ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A[1]; + +/* --> __TI_STACK_BASE */ +extern void* __TI_STACK_BASE; + +/* Module__state__V */ +ti_sysbios_family_arm_m3_Hwi_Module_State__ ti_sysbios_family_arm_m3_Hwi_Module__state__V; + +/* --> ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A */ +const __T1_ti_sysbios_family_arm_m3_Hwi_excHookFuncs ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A[2]; + +/* --> ti_sysbios_knl_Swi_disable__E */ +extern xdc_UInt ti_sysbios_knl_Swi_disable__E(xdc_Void); + +/* --> ti_sysbios_knl_Swi_restoreHwi__E */ +extern xdc_Void ti_sysbios_knl_Swi_restoreHwi__E(xdc_UInt); + +/* --> ti_sysbios_knl_Task_disable__E */ +extern xdc_UInt ti_sysbios_knl_Task_disable__E(xdc_Void); + +/* --> ti_sysbios_knl_Task_restoreHwi__E */ +extern xdc_Void ti_sysbios_knl_Task_restoreHwi__E(xdc_UInt); + + +/* + * ======== ti.sysbios.family.arm.m3.IntrinsicsSupport DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.family.arm.m3.TaskSupport DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.gates.GateHwi DECLARATIONS ======== + */ + +/* Object__table__V */ +ti_sysbios_gates_GateHwi_Object__ ti_sysbios_gates_GateHwi_Object__table__V[1]; + + +/* + * ======== ti.sysbios.gates.GateMutex DECLARATIONS ======== + */ + +/* Object__table__V */ +ti_sysbios_gates_GateMutex_Object__ ti_sysbios_gates_GateMutex_Object__table__V[2]; + + +/* + * ======== ti.sysbios.hal.Hwi DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.hal.Hwi_HwiProxy DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.heaps.HeapMem DECLARATIONS ======== + */ + +#ifdef __IAR_SYSTEMS_ICC__ + #pragma data_alignment=8 +#endif +/* --> ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A */ +__T1_ti_sysbios_heaps_HeapMem_Instance_State__buf ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A[1024]; +#ifdef __ti__align + #pragma DATA_ALIGN(ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A, 8); +#endif +#ifdef __GNUC__ +#ifndef __TI_COMPILER_VERSION__ +__T1_ti_sysbios_heaps_HeapMem_Instance_State__buf ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A[1024] __attribute__ ((aligned(8))); +#endif +#endif + +/* Object__table__V */ +ti_sysbios_heaps_HeapMem_Object__ ti_sysbios_heaps_HeapMem_Object__table__V[1]; + + +/* + * ======== ti.sysbios.heaps.HeapMem_Module_GateProxy DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.knl.Clock DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct ti_sysbios_knl_Clock_Module_State__ { + volatile xdc_UInt32 ticks; + xdc_UInt swiCount; + ti_sysbios_knl_Clock_TimerProxy_Handle timer; + ti_sysbios_knl_Swi_Handle swi; + volatile xdc_UInt numTickSkip; + xdc_UInt32 nextScheduledTick; + xdc_UInt32 maxSkippable; + xdc_Bool inWorkFunc; + xdc_Bool startDuringWorkFunc; + xdc_Bool ticking; + ti_sysbios_knl_Queue_Object__ Object_field_clockQ; +} ti_sysbios_knl_Clock_Module_State__; + +/* Module__state__V */ +ti_sysbios_knl_Clock_Module_State__ ti_sysbios_knl_Clock_Module__state__V; + +/* --> ti_sysbios_knl_Clock_doTick__I */ +extern xdc_Void ti_sysbios_knl_Clock_doTick__I(xdc_UArg); + + +/* + * ======== ti.sysbios.knl.Clock_TimerProxy DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.knl.Idle DECLARATIONS ======== + */ + +/* --> ti_sysbios_hal_Hwi_checkStack */ +extern xdc_Void ti_sysbios_hal_Hwi_checkStack(xdc_Void); + +/* --> ti_sysbios_knl_Idle_funcList__A */ +const __T1_ti_sysbios_knl_Idle_funcList ti_sysbios_knl_Idle_funcList__A[1]; + +/* --> ti_sysbios_knl_Idle_coreList__A */ +const __T1_ti_sysbios_knl_Idle_coreList ti_sysbios_knl_Idle_coreList__A[1]; + + +/* + * ======== ti.sysbios.knl.Intrinsics DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.knl.Intrinsics_SupportProxy DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.knl.Queue DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.knl.Semaphore DECLARATIONS ======== + */ + + +/* + * ======== ti.sysbios.knl.Swi DECLARATIONS ======== + */ + +/* Object__table__V */ +ti_sysbios_knl_Swi_Object__ ti_sysbios_knl_Swi_Object__table__V[1]; + +/* Module_State__ */ +typedef struct ti_sysbios_knl_Swi_Module_State__ { + volatile xdc_Bool locked; + xdc_UInt curSet; + xdc_UInt curTrigger; + ti_sysbios_knl_Swi_Handle curSwi; + ti_sysbios_knl_Queue_Handle curQ; + __TA_ti_sysbios_knl_Swi_Module_State__readyQ readyQ; + __TA_ti_sysbios_knl_Swi_Module_State__constructedSwis constructedSwis; +} ti_sysbios_knl_Swi_Module_State__; + +/* --> ti_sysbios_knl_Swi_Module_State_0_readyQ__A */ +__T1_ti_sysbios_knl_Swi_Module_State__readyQ ti_sysbios_knl_Swi_Module_State_0_readyQ__A[16]; + +/* Module__state__V */ +ti_sysbios_knl_Swi_Module_State__ ti_sysbios_knl_Swi_Module__state__V; + +/* --> ti_sysbios_knl_Task_disable__E */ +extern xdc_UInt ti_sysbios_knl_Task_disable__E(xdc_Void); + +/* --> ti_sysbios_knl_Task_restore__E */ +extern xdc_Void ti_sysbios_knl_Task_restore__E(xdc_UInt); + + +/* + * ======== ti.sysbios.knl.Task DECLARATIONS ======== + */ + +#ifdef __IAR_SYSTEMS_ICC__ + #pragma data_alignment=8 +#endif +/* --> ti_sysbios_knl_Task_Instance_State_0_stack__A */ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_0_stack__A[1024]; +#ifdef __ti__sect + #pragma DATA_SECTION(ti_sysbios_knl_Task_Instance_State_0_stack__A, ".bss:taskStackSection"); +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_0_stack__A[1024] __attribute__ ((section(".bss:taskStackSection"))); +#endif +#endif +#ifdef __ti__align + #pragma DATA_ALIGN(ti_sysbios_knl_Task_Instance_State_0_stack__A, 8); +#endif +#ifdef __GNUC__ +#ifndef __TI_COMPILER_VERSION__ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_0_stack__A[1024] __attribute__ ((aligned(8))); +#endif +#endif + +/* --> UARTMon_taskFxn */ +extern xdc_Void UARTMon_taskFxn(xdc_UArg,xdc_UArg); +#ifdef __IAR_SYSTEMS_ICC__ + #pragma data_alignment=8 +#endif + +/* --> ti_sysbios_knl_Task_Instance_State_1_stack__A */ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_1_stack__A[512]; +#ifdef __ti__sect + #pragma DATA_SECTION(ti_sysbios_knl_Task_Instance_State_1_stack__A, ".bss:taskStackSection"); +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_1_stack__A[512] __attribute__ ((section(".bss:taskStackSection"))); +#endif +#endif +#ifdef __ti__align + #pragma DATA_ALIGN(ti_sysbios_knl_Task_Instance_State_1_stack__A, 8); +#endif +#ifdef __GNUC__ +#ifndef __TI_COMPILER_VERSION__ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_1_stack__A[512] __attribute__ ((aligned(8))); +#endif +#endif + +/* Object__table__V */ +ti_sysbios_knl_Task_Object__ ti_sysbios_knl_Task_Object__table__V[2]; + +/* Module_State__ */ +typedef struct ti_sysbios_knl_Task_Module_State__ { + volatile xdc_Bool locked; + volatile xdc_UInt curSet; + xdc_Bool workFlag; + xdc_UInt vitalTasks; + ti_sysbios_knl_Task_Handle curTask; + ti_sysbios_knl_Queue_Handle curQ; + __TA_ti_sysbios_knl_Task_Module_State__readyQ readyQ; + __TA_ti_sysbios_knl_Task_Module_State__smpCurSet smpCurSet; + __TA_ti_sysbios_knl_Task_Module_State__smpCurMask smpCurMask; + __TA_ti_sysbios_knl_Task_Module_State__smpCurTask smpCurTask; + __TA_ti_sysbios_knl_Task_Module_State__smpReadyQ smpReadyQ; + __TA_ti_sysbios_knl_Task_Module_State__idleTask idleTask; + __TA_ti_sysbios_knl_Task_Module_State__constructedTasks constructedTasks; + ti_sysbios_knl_Queue_Object__ Object_field_inactiveQ; + ti_sysbios_knl_Queue_Object__ Object_field_terminatedQ; +} ti_sysbios_knl_Task_Module_State__; + +/* --> ti_sysbios_knl_Task_Module_State_0_readyQ__A */ +__T1_ti_sysbios_knl_Task_Module_State__readyQ ti_sysbios_knl_Task_Module_State_0_readyQ__A[16]; + +/* --> ti_sysbios_knl_Task_Module_State_0_idleTask__A */ +__T1_ti_sysbios_knl_Task_Module_State__idleTask ti_sysbios_knl_Task_Module_State_0_idleTask__A[1]; + +/* Module__state__V */ +ti_sysbios_knl_Task_Module_State__ ti_sysbios_knl_Task_Module__state__V; + + +/* + * ======== ti.sysbios.knl.Task_SupportProxy DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Assert DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Core DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Defaults DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Diags DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Error DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_Error_Module_State__ { + xdc_UInt16 count; +} xdc_runtime_Error_Module_State__; + +/* Module__state__V */ +xdc_runtime_Error_Module_State__ xdc_runtime_Error_Module__state__V; + + +/* + * ======== xdc.runtime.Gate DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Log DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Main DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Main_Module_GateProxy DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Memory DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_Memory_Module_State__ { + xdc_SizeT maxDefaultTypeAlign; +} xdc_runtime_Memory_Module_State__; + +/* Module__state__V */ +xdc_runtime_Memory_Module_State__ xdc_runtime_Memory_Module__state__V; + + +/* + * ======== xdc.runtime.Memory_HeapProxy DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Registry DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_Registry_Module_State__ { + xdc_runtime_Registry_Desc *listHead; + xdc_runtime_Types_ModuleId curId; +} xdc_runtime_Registry_Module_State__; + +/* Module__state__V */ +xdc_runtime_Registry_Module_State__ xdc_runtime_Registry_Module__state__V; + + +/* + * ======== xdc.runtime.Startup DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_Startup_Module_State__ { + xdc_Int *stateTab; + xdc_Bool execFlag; + xdc_Bool rtsDoneFlag; +} xdc_runtime_Startup_Module_State__; + +/* Module__state__V */ +xdc_runtime_Startup_Module_State__ xdc_runtime_Startup_Module__state__V; + +/* --> ti_sysbios_hal_Hwi_initStack */ +extern xdc_Void ti_sysbios_hal_Hwi_initStack(xdc_Void); + +/* --> xdc_runtime_Startup_firstFxns__A */ +const __T1_xdc_runtime_Startup_firstFxns xdc_runtime_Startup_firstFxns__A[5]; + +/* --> xdc_runtime_System_Module_startup__E */ +extern xdc_Int xdc_runtime_System_Module_startup__E(xdc_Int); + +/* --> xdc_runtime_SysMin_Module_startup__E */ +extern xdc_Int xdc_runtime_SysMin_Module_startup__E(xdc_Int); + +/* --> ti_sysbios_knl_Clock_Module_startup__E */ +extern xdc_Int ti_sysbios_knl_Clock_Module_startup__E(xdc_Int); + +/* --> ti_sysbios_knl_Swi_Module_startup__E */ +extern xdc_Int ti_sysbios_knl_Swi_Module_startup__E(xdc_Int); + +/* --> ti_sysbios_knl_Task_Module_startup__E */ +extern xdc_Int ti_sysbios_knl_Task_Module_startup__E(xdc_Int); + +/* --> ti_sysbios_hal_Hwi_Module_startup__E */ +extern xdc_Int ti_sysbios_hal_Hwi_Module_startup__E(xdc_Int); + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_startup__E */ +extern xdc_Int ti_sysbios_family_arm_m3_Hwi_Module_startup__E(xdc_Int); + +/* --> ti_sysbios_family_arm_lm4_Timer_Module_startup__E */ +extern xdc_Int ti_sysbios_family_arm_lm4_Timer_Module_startup__E(xdc_Int); + +/* --> xdc_runtime_Startup_sfxnTab__A */ +const __T1_xdc_runtime_Startup_sfxnTab xdc_runtime_Startup_sfxnTab__A[8]; + +/* --> xdc_runtime_Startup_sfxnRts__A */ +const __T1_xdc_runtime_Startup_sfxnRts xdc_runtime_Startup_sfxnRts__A[8]; + + +/* + * ======== xdc.runtime.SysMin DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_SysMin_Module_State__ { + __TA_xdc_runtime_SysMin_Module_State__outbuf outbuf; + xdc_UInt outidx; + xdc_Bool wrapped; +} xdc_runtime_SysMin_Module_State__; + +/* --> xdc_runtime_SysMin_Module_State_0_outbuf__A */ +__T1_xdc_runtime_SysMin_Module_State__outbuf xdc_runtime_SysMin_Module_State_0_outbuf__A[128]; + +/* Module__state__V */ +xdc_runtime_SysMin_Module_State__ xdc_runtime_SysMin_Module__state__V; + +/* --> xdc_runtime_SysMin_output__I */ +extern xdc_Void xdc_runtime_SysMin_output__I(xdc_Char*,xdc_UInt); + + +/* + * ======== xdc.runtime.System DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_System_Module_State__ { + __TA_xdc_runtime_System_Module_State__atexitHandlers atexitHandlers; + xdc_Int numAtexitHandlers; +} xdc_runtime_System_Module_State__; + +/* --> xdc_runtime_System_Module_State_0_atexitHandlers__A */ +__T1_xdc_runtime_System_Module_State__atexitHandlers xdc_runtime_System_Module_State_0_atexitHandlers__A[2]; + +/* Module__state__V */ +xdc_runtime_System_Module_State__ xdc_runtime_System_Module__state__V; + +/* --> xdc_runtime_System_printfExtend__I */ +extern xdc_Int xdc_runtime_System_printfExtend__I(xdc_Char**,xdc_CString*,xdc_VaList*,xdc_runtime_System_ParseData*); + + +/* + * ======== xdc.runtime.System_Module_GateProxy DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.System_SupportProxy DECLARATIONS ======== + */ + + +/* + * ======== xdc.runtime.Text DECLARATIONS ======== + */ + +/* Module_State__ */ +typedef struct xdc_runtime_Text_Module_State__ { + xdc_CPtr charBase; + xdc_CPtr nodeBase; +} xdc_runtime_Text_Module_State__; + +/* Module__state__V */ +xdc_runtime_Text_Module_State__ xdc_runtime_Text_Module__state__V; + +/* --> xdc_runtime_Text_charTab__A */ +const __T1_xdc_runtime_Text_charTab xdc_runtime_Text_charTab__A[6253]; + +/* --> xdc_runtime_Text_nodeTab__A */ +const __T1_xdc_runtime_Text_nodeTab xdc_runtime_Text_nodeTab__A[47]; + + +/* + * ======== OBJECT OFFSETS ======== + */ + +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Instance_State_sem__O, ".const:ti_sysbios_gates_GateMutex_Instance_State_sem__O"); +__FAR__ const xdc_SizeT ti_sysbios_gates_GateMutex_Instance_State_sem__O = offsetof(ti_sysbios_gates_GateMutex_Object__, Object_field_sem); + + +/* + * ======== OBJECT OFFSETS ======== + */ + +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module_State_clockQ__O, ".const:ti_sysbios_knl_Clock_Module_State_clockQ__O"); +__FAR__ const xdc_SizeT ti_sysbios_knl_Clock_Module_State_clockQ__O = offsetof(ti_sysbios_knl_Clock_Module_State__, Object_field_clockQ); + + +/* + * ======== OBJECT OFFSETS ======== + */ + +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Instance_State_pendQ__O, ".const:ti_sysbios_knl_Semaphore_Instance_State_pendQ__O"); +__FAR__ const xdc_SizeT ti_sysbios_knl_Semaphore_Instance_State_pendQ__O = offsetof(ti_sysbios_knl_Semaphore_Object__, Object_field_pendQ); + + +/* + * ======== OBJECT OFFSETS ======== + */ + +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module_State_inactiveQ__O, ".const:ti_sysbios_knl_Task_Module_State_inactiveQ__O"); +__FAR__ const xdc_SizeT ti_sysbios_knl_Task_Module_State_inactiveQ__O = offsetof(ti_sysbios_knl_Task_Module_State__, Object_field_inactiveQ); +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module_State_terminatedQ__O, ".const:ti_sysbios_knl_Task_Module_State_terminatedQ__O"); +__FAR__ const xdc_SizeT ti_sysbios_knl_Task_Module_State_terminatedQ__O = offsetof(ti_sysbios_knl_Task_Module_State__, Object_field_terminatedQ); + + +/* + * ======== xdc.cfg.Program TEMPLATE ======== + */ + +/* + * ======== __ASM__ ======== + * Define absolute path prefix for this executable's + * configuration generated files. + */ +xdc__META(__ASM__, "@(#)__ASM__ = C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f"); + +/* + * ======== __ISA__ ======== + * Define the ISA of this executable. This symbol is used by platform + * specific "exec" commands that support more than one ISA; e.g., gdb + */ +xdc__META(__ISA__, "@(#)__ISA__ = v7M4"); + +/* + * ======== __PLAT__ ======== + * Define the name of the platform that can run this executable. This + * symbol is used by platform independent "exec" commands + */ +xdc__META(__PLAT__, "@(#)__PLAT__ = ti.platforms.tiva"); + +/* + * ======== __TARG__ ======== + * Define the name of the target used to build this executable. + */ +xdc__META(__TARG__, "@(#)__TARG__ = ti.targets.arm.elf.M4F"); + +/* + * ======== __TRDR__ ======== + * Define the name of the class that can read/parse this executable. + */ +xdc__META(__TRDR__, "@(#)__TRDR__ = ti.targets.omf.elf.Elf32"); + + +/* + * ======== xdc.cfg.SourceDir TEMPLATE ======== + */ + + + +/* + * ======== ti.platforms.tiva.Platform TEMPLATE ======== + */ + + + +/* + * ======== xdc.runtime.Diags TEMPLATE ======== + */ + + + +/* + * ======== xdc.runtime.Startup TEMPLATE ======== + */ + +/* + * ======== MODULE STARTUP DONE FUNCTIONS ======== + */ +xdc_Bool xdc_runtime_System_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool xdc_runtime_System_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[0] < 0; +} +xdc_Bool xdc_runtime_SysMin_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool xdc_runtime_SysMin_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[1] < 0; +} +xdc_Bool ti_sysbios_knl_Clock_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool ti_sysbios_knl_Clock_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[2] < 0; +} +xdc_Bool ti_sysbios_knl_Swi_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool ti_sysbios_knl_Swi_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[3] < 0; +} +xdc_Bool ti_sysbios_knl_Task_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool ti_sysbios_knl_Task_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[4] < 0; +} +xdc_Bool ti_sysbios_hal_Hwi_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool ti_sysbios_hal_Hwi_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[5] < 0; +} +xdc_Bool ti_sysbios_family_arm_m3_Hwi_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool ti_sysbios_family_arm_m3_Hwi_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[6] < 0; +} +xdc_Bool ti_sysbios_family_arm_lm4_Timer_Module__startupDone__F(void); /* keep GCC prototype warning quiet */ +xdc_Bool ti_sysbios_family_arm_lm4_Timer_Module__startupDone__F(void) { + return (&xdc_runtime_Startup_Module__state__V)->stateTab == 0 || (&xdc_runtime_Startup_Module__state__V)->stateTab[7] < 0; +} + + +/* + * Startup_exec__I is an internal entry point called by target/platform + * boot code. Boot code is not brought into a partial-link assembly. So, + * without this pragma, whole program optimizers would otherwise optimize-out + * this function. + */ +#ifdef __ti__ +#pragma FUNC_EXT_CALLED(xdc_runtime_Startup_exec__I); +#endif + +#ifdef __GNUC__ +#if __GNUC__ >= 4 +xdc_Void xdc_runtime_Startup_exec__I(void) __attribute__ ((externally_visible)); +#endif +#endif + +/* + * ======== xdc_runtime_Startup_exec__I ======== + * Initialize all used modules that have startup functions + */ +xdc_Void xdc_runtime_Startup_exec__I(void) +{ + xdc_Int state[8]; + xdc_runtime_Startup_startModsFxn__C(state, 8); +} + +/* + * ======== xdc.runtime.Reset TEMPLATE ======== + */ + +/* + * Startup_reset__I is an internal entry point called by target/platform + * boot code. Boot code is not brought into a partial-link assembly. So, + * without this pragma, whole program optimizers would otherwise optimize-out + * this function. + */ +#ifdef __ti__ +#pragma FUNC_EXT_CALLED(xdc_runtime_Startup_reset__I); +#endif + +#ifdef __GNUC__ +#if __GNUC__ >= 4 +xdc_Void xdc_runtime_Startup_reset__I(void) __attribute__ ((externally_visible)); +#endif +#endif + + +/* + * ======== xdc_runtime_Startup_reset__I ======== + * This function is called by bootstrap initialization code as early as + * possible in the startup process. This function calls all functions in + * the Reset.fxns array _as well as_ Startup.resetFxn (if it's non-NULL) + */ +xdc_Void xdc_runtime_Startup_reset__I(void) +{ +} + +/* + * ======== xdc.runtime.System TEMPLATE ======== + */ + + +#include +#include +#include +#include +#include + +#include +#include + +/* + * ======== System_printfExtend__I ======== + * This function processes optional extended formats of printf. + * + * It returns the number of characters added to the result. + * + * Precision (maximum string length) is not supported for %$S. + * + * Right-justified (which is default) minimum width is not supported + * for %$L, %$S, or %$F. + */ +xdc_Int xdc_runtime_System_printfExtend__I(xdc_Char **pbuf, xdc_CString *pfmt, + xdc_VaList *pva, xdc_runtime_System_ParseData *parse) +{ + xdc_CString fmt = *pfmt; + xdc_Int res; + xdc_Char c; + xdc_Bool found = FALSE; + + /* + * Create a local variable 'va' to ensure that the dereference of + * pva only occurs once. + */ + va_list va = *pva; + + res = 0; + + c = *fmt++; + *pfmt = *pfmt + 1; + + + if (c == '$') { + c = *fmt++; + *pfmt = *pfmt + 1; + + if (c == 'L') { + xdc_runtime_Types_Label *lab = parse->aFlag ? + (xdc_runtime_Types_Label *)xdc_iargToPtr(va_arg(va, xdc_IArg)) : + (xdc_runtime_Types_Label *)va_arg(va, void *); + + /* + * Call Text_putLab to write out the label, taking the precision + * into account. + */ + res = xdc_runtime_Text_putLab(lab, pbuf, parse->precis); + + /* + * Set the length to 0 to indicate to 'doPrint' that nothing should + * be copied from parse.ptr. + */ + parse->len = 0; + + /* Update the minimum width field. */ + parse->width -= res; + + found = TRUE; + } + + if (c == 'F') { + xdc_runtime_Types_Site site; + + /* Retrieve the file name string from the argument list */ + site.file = parse->aFlag ? (xdc_Char *) xdc_iargToPtr(va_arg(va, xdc_IArg)) : + (xdc_Char *) va_arg(va, xdc_Char *); + + /* Retrieve the line number from the argument list. */ + site.line = parse->aFlag ? (xdc_Int) va_arg(va, xdc_IArg) : + (xdc_Int) va_arg(va, xdc_Int); + + /* + * Omit the 'mod' field, set it to 0. + * '0' is a safe sentinel value - the IDs for named modules are + * 0x8000 and higher, and the IDs for unnamed modules go from 0x1 + * to 0x7fff. + */ + site.mod = 0; + + /* + * Call putSite to format the file and line number. + * If a precision was specified, it will be used as the maximum + * string lengrth. + */ + res = xdc_runtime_Text_putSite(&site, pbuf, parse->precis); + + /* + * Set the length to 0 to indicate to 'doPrint' that nothing should + * be copied from parse.ptr. + */ + parse->len = 0; + + /* Update the minimum width field */ + parse->width -= res; + + found = TRUE; + } + + if (c == 'S') { + /* Retrieve the format string from the argument list */ + parse->ptr = parse->aFlag ? + (xdc_Char *) xdc_iargToPtr(va_arg(va, xdc_IArg)) : + (xdc_Char *) va_arg(va, xdc_Char *); + + /* Update pva before passing it to doPrint. */ + *pva = va; + + /* Perform the recursive format. System_doPrint does not advance + * the buffer pointer, so it has to be done explicitly. + */ + res = xdc_runtime_System_doPrint__I(*pbuf, parse->precis, + parse->ptr, pva, parse->aFlag); + + if (*pbuf) { + *pbuf += res; + } + + /* Update the temporary variable with any changes to *pva */ + va = *pva; + + /* + * Set the length to 0 to indicate to 'doPrint' that nothing should + * be copied from parse.ptr + */ + parse->len = 0; + + /* Update the minimum width field */ + parse->width -= res; + + /* Indicate that we were able to interpret the specifier */ + found = TRUE; + } + + } + + if (c == 'f') { + /* support arguments _after_ optional float support */ + if (parse->aFlag) { + (void)va_arg(va, xdc_IArg); + } + else { + (void)va_arg(va, double); + } + } + + if (found == FALSE) { + /* other character (like %) copy to output */ + *(parse->ptr) = c; + parse->len = 1; + } + + /* + * Before returning, we must update the value of pva. We use a label here + * so that all return points will go through this update. + * The 'goto end' is here to ensure that there is always a reference to the + * label (to avoid the compiler complaining). + */ + goto end; +end: + *pva = va; + return (res); +} + +/* + * ======== xdc.runtime.SysMin TEMPLATE ======== + */ + + +#if defined(__ti__) +extern int HOSTwrite(int, const char *, unsigned); +#elif (defined(gnu_targets_STD_) && defined(xdc_target__os_undefined)) +extern int _write(int, char *, int); +#define HOSTwrite(x,y,z) _write((int)(x),(char *)(y),(int)(z)) +#elif defined(__IAR_SYSTEMS_ICC__) +#include +#define HOSTwrite(x,y,z) __write((x),(unsigned char *)(y),(z)) +#else +#include +#endif + +/* + * ======== SysMin_output__I ======== + * HOSTWrite only writes a max of N chars at a time. The amount it writes + * is returned. This function loops until the entire buffer is written. + * Being a static function allows it to conditionally compile out. + */ +xdc_Void xdc_runtime_SysMin_output__I(xdc_Char *buf, xdc_UInt size) +{ +#if defined(__ti__) || (defined(gnu_targets_STD_) && defined(xdc_target__os_undefined)) || defined (__IAR_SYSTEMS_ICC__) + xdc_Int printCount; + + while (size != 0) { + printCount = HOSTwrite(1, buf, size); + if ((printCount <= 0) || ((xdc_UInt)printCount > size)) { + break; /* ensure we never get stuck in an infinite loop */ + } + size -= printCount; + buf = buf + printCount; + } +#else + fwrite(buf, 1, size, stdout); +#endif +} + +/* + * ======== xdc.runtime.Text TEMPLATE ======== + */ + + +/* + * ======== xdc_runtime_Text_visitRope__I ======== + * This function is indirectly called within Text.c through + * the visitRopeFxn configuration parameter of xdc.runtime.Text. + */ +void xdc_runtime_Text_visitRope__I(xdc_runtime_Text_RopeId rope, + xdc_Fxn visFxn, xdc_Ptr visState) +{ + xdc_String stack[7]; + xdc_runtime_Text_visitRope2__I(rope, visFxn, visState, stack); +} + + +/* + * ======== ti.catalog.arm.cortexm4.tiva.ce.Boot TEMPLATE ======== + */ + +#if defined(__ti__) +#pragma CODE_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_init, ".text:.bootCodeSection") +#endif + +/* + * ======== ti_catalog_arm_cortexm4_tiva_ce_Boot_init ======== + */ +xdc_Void ti_catalog_arm_cortexm4_tiva_ce_Boot_init() +{ + ti_catalog_arm_cortexm4_tiva_ce_Boot_sysCtlClockSet((xdc_ULong) + (-1056963264)); +} + + +/* + * ======== ti.sysbios.knl.Clock TEMPLATE ======== + */ + +Void ti_sysbios_knl_Clock_doTick__I(UArg arg) +{ + /* update system time */ + (&ti_sysbios_knl_Clock_Module__state__V)->ticks++; + + ti_sysbios_knl_Clock_logTick__E(); + + if (!ti_sysbios_knl_Queue_empty(ti_sysbios_knl_Clock_Module_State_clockQ())) { + (&ti_sysbios_knl_Clock_Module__state__V)->swiCount++; + + ti_sysbios_knl_Swi_post((&ti_sysbios_knl_Clock_Module__state__V)->swi); + } +} + +/* + * ======== ti.sysbios.knl.Task TEMPLATE ======== + */ + + + +/* + * ======== ti.sysbios.BIOS TEMPLATE ======== + */ + + +Void ti_sysbios_BIOS_atExitFunc__I(Int); + +extern Void ti_sysbios_BIOS_registerRTSLock(); +extern Void ti_sysbios_family_arm_lm4_Timer_startup__E(); + +Void ti_sysbios_BIOS_startFunc__I() +{ + xdc_runtime_System_atexit( + (xdc_runtime_System_AtexitHandler)ti_sysbios_BIOS_atExitFunc__I); + ti_sysbios_BIOS_registerRTSLock(); + ti_sysbios_family_arm_lm4_Timer_startup__E(); + ti_sysbios_hal_Hwi_startup(); + ti_sysbios_knl_Swi_startup(); + ti_sysbios_knl_Task_startup(); +} + +#include <_lock.h> + +Void ti_sysbios_BIOS_atExitFunc__I(Int notused) +{ + ti_sysbios_knl_Swi_disable(); + ti_sysbios_knl_Task_disable(); + ti_sysbios_BIOS_setThreadType(ti_sysbios_BIOS_ThreadType_Main); + + if ((&ti_sysbios_BIOS_Module__state__V)->rtsGate != NULL) { + _register_lock(_nop); + _register_unlock(_nop); + } +} + +/* + * ======== BIOS_rtsLock ======== + * Called by rts _lock() function + */ +Void ti_sysbios_BIOS_rtsLock() +{ + IArg key; + + key = ti_sysbios_BIOS_RtsGateProxy_enter((&ti_sysbios_BIOS_Module__state__V)->rtsGate); + if ((&ti_sysbios_BIOS_Module__state__V)->rtsGateCount == 0) { + (&ti_sysbios_BIOS_Module__state__V)->rtsGateKey = key; + } + /* Increment need not be atomic */ + (&ti_sysbios_BIOS_Module__state__V)->rtsGateCount++; +} + +/* + * ======== BIOS_rtsUnLock ======== + * Called by rts _unlock() function + */ +Void ti_sysbios_BIOS_rtsUnlock() +{ + (&ti_sysbios_BIOS_Module__state__V)->rtsGateCount--; + + if ((&ti_sysbios_BIOS_Module__state__V)->rtsGateCount == 0) { + ti_sysbios_BIOS_RtsGateProxy_leave((&ti_sysbios_BIOS_Module__state__V)->rtsGate, (&ti_sysbios_BIOS_Module__state__V)->rtsGateKey); + } +} + +/* + * ======== BIOS_nullFunc ======== + */ +Void ti_sysbios_BIOS_nullFunc__I() +{ +} + +/* + * ======== BIOS_registerRTSLock ======== + */ +Void ti_sysbios_BIOS_registerRTSLock(Void) +{ + if ((&ti_sysbios_BIOS_Module__state__V)->rtsGate != NULL) { + _register_lock(ti_sysbios_BIOS_rtsLock); + _register_unlock(ti_sysbios_BIOS_rtsUnlock); + } +} + +/* + * ======== BIOS_removeRTSLock ======== + */ +Void ti_sysbios_BIOS_removeRTSLock(Void) +{ + if ((&ti_sysbios_BIOS_Module__state__V)->rtsGate != NULL) { + _register_lock(ti_sysbios_BIOS_nullFunc); + _register_unlock(ti_sysbios_BIOS_nullFunc); + } +} + +/* + * ======== BIOS_exitFunc ======== + */ +Void ti_sysbios_BIOS_exitFunc(Int stat) +{ + /* remove the RTS lock */ + ti_sysbios_BIOS_removeRTSLock(); + + /* force thread type to 'Main' */ + ti_sysbios_BIOS_setThreadType(ti_sysbios_BIOS_ThreadType_Main); + + xdc_runtime_System_exit(stat); +} + +/* + * ======== BIOS_errorRaiseHook ======== + */ +Void ti_sysbios_BIOS_errorRaiseHook(xdc_runtime_Error_Block *eb) +{ + /* + * If this is an Assert thread, defang Gate threadtype check + */ + if (eb->id == xdc_runtime_Assert_E_assertFailed) { + /* remove the RTS lock */ + ti_sysbios_BIOS_removeRTSLock(); + /* force thread type to 'Main' */ + ti_sysbios_BIOS_setThreadType(ti_sysbios_BIOS_ThreadType_Main); + } + + /* Call the installed Error.raiseHook */ + ti_sysbios_BIOS_installedErrorHook(eb); +} + +/* + * ======== ti.sysbios.Build TEMPLATE ======== + */ + + +/* + * ======== ti.sysbios.family.arm.m3.Hwi TEMPLATE ======== + */ + +extern Void _c_int00(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); +extern Void ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I(); + + +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_resetVectors, ".resetVecs"); + +/* const because it is meant to be placed in ROM */ +const UInt32 ti_sysbios_family_arm_m3_Hwi_resetVectors[] = { + (UInt32)(&__TI_STACK_BASE), + (UInt32)(&_c_int00), + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* NMI */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* Hard Fault */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* Mem Fault */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* Bus Fault */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* Usage Fault */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* reserved */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* reserved */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* reserved */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* reserved */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* SVCall */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* Debug Mon */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I), /* reserved */ + (UInt32)(&ti_sysbios_family_arm_m3_Hwi_pendSV__I), /* pendSV */ +}; + +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_ramVectors, ".vecs"); + +/* place holder for RAM vector table */ +UInt32 ti_sysbios_family_arm_m3_Hwi_ramVectors[216]; + +UInt32 ti_sysbios_family_arm_m3_Hwi_dispatchTable[216]; + +#if defined(__IAR_SYSTEMS_ICC__) +Void ti_sysbios_family_arm_m3_Hwi_initIsrStackSize() +{ + #pragma section = "CSTACK" + ti_sysbios_family_arm_m3_Hwi_Module__state__V.isrStackSize = (SizeT)__section_size("CSTACK"); +} +#endif + +/* + * ======== ti.sysbios.rts.MemAlloc TEMPLATE ======== + */ + + + +#if defined(__ti__) + +#pragma FUNC_EXT_CALLED(malloc); +#pragma FUNC_EXT_CALLED(memalign); +#pragma FUNC_EXT_CALLED(free); +#pragma FUNC_EXT_CALLED(calloc); +#pragma FUNC_EXT_CALLED(realloc); + +#define ATTRIBUTE + +#elif defined(__IAR_SYSTEMS_ICC__) + +#define ATTRIBUTE + +#else + +#define ATTRIBUTE __attribute__ ((used)) + +#endif + + +#include + +#include +#include + +#include + +#if defined(__GNUC__) && !defined(__ti__) + +#include + +#endif + +/* + * Header is a union to make sure that the size is a power of 2. + * + * On the MSP430 small model (MSP430X), size_t is 2 bytes, which makes + * the size of this struct 6 bytes. + */ +typedef union Header { + struct { + Ptr actualBuf; + SizeT size; + } header; + UArg pad[2]; /* 4 words on 28L, 8 bytes on most others */ +} Header; + +/* + * ======== malloc ======== + */ +Void ATTRIBUTE *malloc(SizeT size) +{ + Header *packet; + xdc_runtime_Error_Block eb; + + xdc_runtime_Error_init(&eb); + + if (size == 0) { + return (NULL); + } + + packet = (Header *)xdc_runtime_Memory_alloc(NULL, + (SizeT)(size + sizeof(Header)), 0, &eb); + + if (packet == NULL) { + return (NULL); + } + + packet->header.actualBuf = (Ptr)packet; + packet->header.size = size + sizeof(Header); + + return (packet + 1); +} + +/* + * ======== memalign ======== + * mirrors the memalign() function from the TI run-time library + */ +Void ATTRIBUTE *memalign(SizeT alignment, SizeT size) +{ + Header *packet; + Void *tmp; + xdc_runtime_Error_Block eb; + + xdc_runtime_Error_init(&eb); + + if (alignment < sizeof(Header)) { + alignment = sizeof(Header); + } + + /* + * return NULL if size is 0, or alignment is not a power of 2 + */ + if (size == 0 || (alignment & (alignment - 1))) { + return (NULL); + } + + /* + * Allocate 'align + size' so that we have room for the 'packet' + * and can return an aligned buffer. + */ + tmp = xdc_runtime_Memory_alloc(NULL, alignment + size, alignment, &eb); + + if (tmp == NULL) { + return (NULL); + } + + packet = (Header *)((char *)tmp + alignment - sizeof(Header)); + + packet->header.actualBuf = tmp; + packet->header.size = size + sizeof(Header); + + return (packet + 1); +} + +/* + * ======== calloc ======== + */ +Void ATTRIBUTE *calloc(SizeT nmemb, SizeT size) +{ + SizeT nbytes; + Ptr retval; + + nbytes = nmemb * size; + + /* return NULL if there's an overflow */ + if (nmemb && size != (nbytes / nmemb)) { + return (NULL); + } + + retval = malloc(nbytes); + if (retval != NULL) { + (Void)memset(retval, (Int)'\0', nbytes); + } + + return (retval); +} + +/* + * ======== free ======== + */ +Void ATTRIBUTE free(Void *ptr) +{ + Header *packet; + + if (ptr != NULL) { + packet = ((Header *)ptr) - 1; + + xdc_runtime_Memory_free(NULL, (Ptr)packet->header.actualBuf, + (packet->header.size + + ((char*)packet - (char*)packet->header.actualBuf))); + } +} + +/* + * ======== realloc ======== + */ +Void ATTRIBUTE *realloc(Void *ptr, SizeT size) +{ + Ptr retval; + Header *packet; + SizeT oldSize; + + if (ptr == NULL) { + retval = malloc(size); + } + else if (size == 0) { + free(ptr); + retval = NULL; + } + else { + packet = (Header *)ptr - 1; + retval = malloc(size); + if (retval != NULL) { + oldSize = packet->header.size - sizeof(Header); + (Void)memcpy(retval, ptr, (size < oldSize) ? size : oldSize); + free(ptr); + } + } + + return (retval); +} + +#if defined(__GNUC__) && !defined(__ti__) + +/* + * ======== _malloc_r ======== + */ +Void ATTRIBUTE *_malloc_r(struct _reent *rptr, SizeT size) +{ + return malloc(size); +} + +/* + * ======== _calloc_r ======== + */ +Void ATTRIBUTE *_calloc_r(struct _reent *rptr, SizeT nmemb, SizeT size) +{ + return calloc(nmemb, size); +} + +/* + * ======== _free_r ======== + */ +Void ATTRIBUTE _free_r(struct _reent *rptr, Void *ptr) +{ + free(ptr); +} + +/* + * ======== _realloc_r ======== + */ +Void ATTRIBUTE *_realloc_r(struct _reent *rptr, Void *ptr, SizeT size) +{ + return realloc(ptr, size); +} + +#endif + + +/* + * ======== ti.catalog.arm.cortexm4.tiva.ce.Boot INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsEnabled__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsEnabled__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsEnabled ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsIncluded__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsIncluded__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsIncluded ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsMask__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsMask__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsMask ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsMask__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gateObj__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gateObj__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gateObj ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gateObj__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gatePrms__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gatePrms__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gatePrms ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gatePrms__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__id__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__id__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__id ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__id__C = (xdc_Bits16)0x8015; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerDefined__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerDefined__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerDefined ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerObj__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerObj__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerObj ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerObj__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn0__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn0__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn0 ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn0__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn1__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn1__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn1 ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn1__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn2__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn2__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn2 ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn2__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn4__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn4__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn4 ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn4__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn8__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn8__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn8 ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn8__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__startupDoneFxn__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__startupDoneFxn ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__startupDoneFxn__C = ((CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__count__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__count__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__count ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__heap__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__heap__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__heap ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__sizeof__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__sizeof__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__sizeof ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__table__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__table__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__table ti_catalog_arm_cortexm4_tiva_ce_Boot_Object__table__C = 0; + +/* A_mustUseEnhancedClockMode__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustUseEnhancedClockMode__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustUseEnhancedClockMode__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustUseEnhancedClockMode ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustUseEnhancedClockMode__C = (((xdc_runtime_Assert_Id)400) << 16 | 16); + +/* A_mustNotUseEnhancedClockMode__C */ +#pragma DATA_SECTION(ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustNotUseEnhancedClockMode__C, ".const:ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustNotUseEnhancedClockMode__C"); +__FAR__ const CT__ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustNotUseEnhancedClockMode ti_catalog_arm_cortexm4_tiva_ce_Boot_A_mustNotUseEnhancedClockMode__C = (((xdc_runtime_Assert_Id)474) << 16 | 16); + + +/* + * ======== ti.sysbios.BIOS INITIALIZERS ======== + */ + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_ti_sysbios_BIOS_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +ti_sysbios_BIOS_Module_State__ ti_sysbios_BIOS_Module__state__V __attribute__ ((section(".data_ti_sysbios_BIOS_Module__state__V"))); +#endif +#endif +ti_sysbios_BIOS_Module_State__ ti_sysbios_BIOS_Module__state__V = { + { + (xdc_Bits32)0x0, /* hi */ + (xdc_Bits32)0x4c4b400, /* lo */ + }, /* cpuFreq */ + (xdc_UInt)0x0, /* rtsGateCount */ + ((xdc_IArg)(0x0)), /* rtsGateKey */ + (ti_sysbios_BIOS_RtsGateProxy_Handle)&ti_sysbios_gates_GateMutex_Object__table__V[1], /* rtsGate */ + ti_sysbios_BIOS_ThreadType_Main, /* threadType */ + ((void*)0), /* smpThreadType */ + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_BIOS_startFunc)), /* startFunc */ + ((xdc_Void(*)(xdc_Int))((xdc_Fxn)ti_sysbios_BIOS_exitFunc)), /* exitFunc */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__diagsEnabled__C, ".const:ti_sysbios_BIOS_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__diagsEnabled ti_sysbios_BIOS_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__diagsIncluded__C, ".const:ti_sysbios_BIOS_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__diagsIncluded ti_sysbios_BIOS_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__diagsMask__C, ".const:ti_sysbios_BIOS_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__diagsMask ti_sysbios_BIOS_Module__diagsMask__C = ((CT__ti_sysbios_BIOS_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__gateObj__C, ".const:ti_sysbios_BIOS_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__gateObj ti_sysbios_BIOS_Module__gateObj__C = ((CT__ti_sysbios_BIOS_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__gatePrms__C, ".const:ti_sysbios_BIOS_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__gatePrms ti_sysbios_BIOS_Module__gatePrms__C = ((CT__ti_sysbios_BIOS_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__id__C, ".const:ti_sysbios_BIOS_Module__id__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__id ti_sysbios_BIOS_Module__id__C = (xdc_Bits16)0x8021; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerDefined__C, ".const:ti_sysbios_BIOS_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerDefined ti_sysbios_BIOS_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerObj__C, ".const:ti_sysbios_BIOS_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerObj ti_sysbios_BIOS_Module__loggerObj__C = ((CT__ti_sysbios_BIOS_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerFxn0__C, ".const:ti_sysbios_BIOS_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerFxn0 ti_sysbios_BIOS_Module__loggerFxn0__C = ((CT__ti_sysbios_BIOS_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerFxn1__C, ".const:ti_sysbios_BIOS_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerFxn1 ti_sysbios_BIOS_Module__loggerFxn1__C = ((CT__ti_sysbios_BIOS_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerFxn2__C, ".const:ti_sysbios_BIOS_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerFxn2 ti_sysbios_BIOS_Module__loggerFxn2__C = ((CT__ti_sysbios_BIOS_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerFxn4__C, ".const:ti_sysbios_BIOS_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerFxn4 ti_sysbios_BIOS_Module__loggerFxn4__C = ((CT__ti_sysbios_BIOS_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__loggerFxn8__C, ".const:ti_sysbios_BIOS_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__loggerFxn8 ti_sysbios_BIOS_Module__loggerFxn8__C = ((CT__ti_sysbios_BIOS_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Module__startupDoneFxn__C, ".const:ti_sysbios_BIOS_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_BIOS_Module__startupDoneFxn ti_sysbios_BIOS_Module__startupDoneFxn__C = ((CT__ti_sysbios_BIOS_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Object__count__C, ".const:ti_sysbios_BIOS_Object__count__C"); +__FAR__ const CT__ti_sysbios_BIOS_Object__count ti_sysbios_BIOS_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Object__heap__C, ".const:ti_sysbios_BIOS_Object__heap__C"); +__FAR__ const CT__ti_sysbios_BIOS_Object__heap ti_sysbios_BIOS_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Object__sizeof__C, ".const:ti_sysbios_BIOS_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_BIOS_Object__sizeof ti_sysbios_BIOS_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_Object__table__C, ".const:ti_sysbios_BIOS_Object__table__C"); +__FAR__ const CT__ti_sysbios_BIOS_Object__table ti_sysbios_BIOS_Object__table__C = 0; + +/* smpEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_smpEnabled__C, ".const:ti_sysbios_BIOS_smpEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_smpEnabled ti_sysbios_BIOS_smpEnabled__C = 0; + +/* cpuFreq__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_cpuFreq__C, ".const:ti_sysbios_BIOS_cpuFreq__C"); +__FAR__ const CT__ti_sysbios_BIOS_cpuFreq ti_sysbios_BIOS_cpuFreq__C = { + (xdc_Bits32)0x0, /* hi */ + (xdc_Bits32)0x4c4b400, /* lo */ +}; + +/* runtimeCreatesEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_runtimeCreatesEnabled__C, ".const:ti_sysbios_BIOS_runtimeCreatesEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_runtimeCreatesEnabled ti_sysbios_BIOS_runtimeCreatesEnabled__C = 1; + +/* taskEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_taskEnabled__C, ".const:ti_sysbios_BIOS_taskEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_taskEnabled ti_sysbios_BIOS_taskEnabled__C = 1; + +/* swiEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_swiEnabled__C, ".const:ti_sysbios_BIOS_swiEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_swiEnabled ti_sysbios_BIOS_swiEnabled__C = 1; + +/* clockEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_clockEnabled__C, ".const:ti_sysbios_BIOS_clockEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_clockEnabled ti_sysbios_BIOS_clockEnabled__C = 1; + +/* heapSize__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_heapSize__C, ".const:ti_sysbios_BIOS_heapSize__C"); +__FAR__ const CT__ti_sysbios_BIOS_heapSize ti_sysbios_BIOS_heapSize__C = (xdc_SizeT)0x400; + +/* heapSection__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_heapSection__C, ".const:ti_sysbios_BIOS_heapSection__C"); +__FAR__ const CT__ti_sysbios_BIOS_heapSection ti_sysbios_BIOS_heapSection__C = 0; + +/* heapTrackEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_heapTrackEnabled__C, ".const:ti_sysbios_BIOS_heapTrackEnabled__C"); +__FAR__ const CT__ti_sysbios_BIOS_heapTrackEnabled ti_sysbios_BIOS_heapTrackEnabled__C = 0; + +/* setupSecureContext__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_setupSecureContext__C, ".const:ti_sysbios_BIOS_setupSecureContext__C"); +__FAR__ const CT__ti_sysbios_BIOS_setupSecureContext ti_sysbios_BIOS_setupSecureContext__C = 0; + +/* useSK__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_useSK__C, ".const:ti_sysbios_BIOS_useSK__C"); +__FAR__ const CT__ti_sysbios_BIOS_useSK ti_sysbios_BIOS_useSK__C = 0; + +/* installedErrorHook__C */ +#pragma DATA_SECTION(ti_sysbios_BIOS_installedErrorHook__C, ".const:ti_sysbios_BIOS_installedErrorHook__C"); +__FAR__ const CT__ti_sysbios_BIOS_installedErrorHook ti_sysbios_BIOS_installedErrorHook__C = ((CT__ti_sysbios_BIOS_installedErrorHook)((xdc_Fxn)xdc_runtime_Error_print__E)); + + +/* + * ======== ti.sysbios.BIOS_RtsGateProxy INITIALIZERS ======== + */ + + +/* + * ======== ti.sysbios.family.arm.lm4.Timer INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_family_arm_lm4_Timer_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Object__PARAMS__C, ".const:ti_sysbios_family_arm_lm4_Timer_Object__PARAMS__C"); +__FAR__ const ti_sysbios_family_arm_lm4_Timer_Params ti_sysbios_family_arm_lm4_Timer_Object__PARAMS__C = { + sizeof (ti_sysbios_family_arm_lm4_Timer_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_family_arm_lm4_Timer_Object__PARAMS__C.__iprms, /* instance */ + ti_sysbios_interfaces_ITimer_RunMode_CONTINUOUS, /* runMode */ + ti_sysbios_interfaces_ITimer_StartMode_AUTO, /* startMode */ + ((xdc_UArg)0), /* arg */ + (xdc_UInt32)0x0, /* period */ + ti_sysbios_interfaces_ITimer_PeriodType_MICROSECS, /* periodType */ + { + (xdc_Bits32)0x0, /* hi */ + (xdc_Bits32)0x0, /* lo */ + }, /* extFreq */ + ((ti_sysbios_family_arm_m3_Hwi_Params*)0), /* hwiParams */ + (xdc_UInt)0xffffffff, /* prevThreshold */ + 0, /* altclk */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_family_arm_lm4_Timer_Module__ ti_sysbios_family_arm_lm4_Timer_Module__root__V = { + {&ti_sysbios_family_arm_lm4_Timer_Module__root__V.link, /* link.next */ + &ti_sysbios_family_arm_lm4_Timer_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_family_arm_lm4_Timer_Object__ ti_sysbios_family_arm_lm4_Timer_Object__table__V[1] = { + {/* instance#0 */ + 0, + 1, /* staticInst */ + (xdc_Int)0x0, /* id */ + ti_sysbios_interfaces_ITimer_RunMode_CONTINUOUS, /* runMode */ + ti_sysbios_interfaces_ITimer_StartMode_AUTO, /* startMode */ + (xdc_UInt)0x13880, /* period */ + ti_sysbios_interfaces_ITimer_PeriodType_COUNTS, /* periodType */ + (xdc_UInt)0x23, /* intNum */ + ((xdc_UArg)0), /* arg */ + ((xdc_Void(*)(xdc_UArg))((xdc_Fxn)ti_sysbios_knl_Clock_doTick__I)), /* tickFxn */ + { + (xdc_Bits32)0x0, /* hi */ + (xdc_Bits32)0x0, /* lo */ + }, /* extFreq */ + (ti_sysbios_family_arm_m3_Hwi_Handle)&ti_sysbios_family_arm_m3_Hwi_Object__table__V[0], /* hwi */ + (xdc_UInt)0xffffffff, /* prevThreshold */ + (xdc_UInt)0x0, /* rollovers */ + (xdc_UInt)0x0, /* savedCurrCount */ + 0, /* altclk */ + }, +}; + +/* --> ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A */ +__T1_ti_sysbios_family_arm_lm4_Timer_Module_State__device ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A[6] = { + { + (xdc_UInt)0x23, /* intNum */ + ((xdc_Ptr)(0x40030000)), /* baseAddr */ + }, /* [0] */ + { + (xdc_UInt)0x25, /* intNum */ + ((xdc_Ptr)(0x40031000)), /* baseAddr */ + }, /* [1] */ + { + (xdc_UInt)0x27, /* intNum */ + ((xdc_Ptr)(0x40032000)), /* baseAddr */ + }, /* [2] */ + { + (xdc_UInt)0x33, /* intNum */ + ((xdc_Ptr)(0x40033000)), /* baseAddr */ + }, /* [3] */ + { + (xdc_UInt)0x56, /* intNum */ + ((xdc_Ptr)(0x40034000)), /* baseAddr */ + }, /* [4] */ + { + (xdc_UInt)0x6c, /* intNum */ + ((xdc_Ptr)(0x40035000)), /* baseAddr */ + }, /* [5] */ +}; + +/* --> ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A */ +__T1_ti_sysbios_family_arm_lm4_Timer_Module_State__handles ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A[6] = { + (ti_sysbios_family_arm_lm4_Timer_Handle)&ti_sysbios_family_arm_lm4_Timer_Object__table__V[0], /* [0] */ + 0, /* [1] */ + 0, /* [2] */ + 0, /* [3] */ + 0, /* [4] */ + 0, /* [5] */ +}; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_ti_sysbios_family_arm_lm4_Timer_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +ti_sysbios_family_arm_lm4_Timer_Module_State__ ti_sysbios_family_arm_lm4_Timer_Module__state__V __attribute__ ((section(".data_ti_sysbios_family_arm_lm4_Timer_Module__state__V"))); +#endif +#endif +ti_sysbios_family_arm_lm4_Timer_Module_State__ ti_sysbios_family_arm_lm4_Timer_Module__state__V = { + (xdc_UInt)0x3e, /* availMask */ + ((void*)ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A), /* device */ + ((void*)ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A), /* handles */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__diagsEnabled__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__diagsEnabled ti_sysbios_family_arm_lm4_Timer_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__diagsIncluded__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__diagsIncluded ti_sysbios_family_arm_lm4_Timer_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__diagsMask__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__diagsMask ti_sysbios_family_arm_lm4_Timer_Module__diagsMask__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__gateObj__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__gateObj ti_sysbios_family_arm_lm4_Timer_Module__gateObj__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__gatePrms__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__gatePrms ti_sysbios_family_arm_lm4_Timer_Module__gatePrms__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__id__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__id__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__id ti_sysbios_family_arm_lm4_Timer_Module__id__C = (xdc_Bits16)0x802e; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerDefined__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerDefined ti_sysbios_family_arm_lm4_Timer_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerObj__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerObj ti_sysbios_family_arm_lm4_Timer_Module__loggerObj__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn0__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn0 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn0__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn1__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn1 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn1__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn2__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn2 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn2__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn4__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn4 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn4__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn8__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn8 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn8__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Module__startupDoneFxn__C, ".const:ti_sysbios_family_arm_lm4_Timer_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Module__startupDoneFxn ti_sysbios_family_arm_lm4_Timer_Module__startupDoneFxn__C = ((CT__ti_sysbios_family_arm_lm4_Timer_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Object__count__C, ".const:ti_sysbios_family_arm_lm4_Timer_Object__count__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Object__count ti_sysbios_family_arm_lm4_Timer_Object__count__C = 1; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Object__heap__C, ".const:ti_sysbios_family_arm_lm4_Timer_Object__heap__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Object__heap ti_sysbios_family_arm_lm4_Timer_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Object__sizeof__C, ".const:ti_sysbios_family_arm_lm4_Timer_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Object__sizeof ti_sysbios_family_arm_lm4_Timer_Object__sizeof__C = sizeof(ti_sysbios_family_arm_lm4_Timer_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Object__table__C, ".const:ti_sysbios_family_arm_lm4_Timer_Object__table__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_Object__table ti_sysbios_family_arm_lm4_Timer_Object__table__C = ti_sysbios_family_arm_lm4_Timer_Object__table__V; + +/* E_invalidTimer__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_E_invalidTimer__C, ".const:ti_sysbios_family_arm_lm4_Timer_E_invalidTimer__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_E_invalidTimer ti_sysbios_family_arm_lm4_Timer_E_invalidTimer__C = (((xdc_runtime_Error_Id)4522) << 16 | 0); + +/* E_notAvailable__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_E_notAvailable__C, ".const:ti_sysbios_family_arm_lm4_Timer_E_notAvailable__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_E_notAvailable ti_sysbios_family_arm_lm4_Timer_E_notAvailable__C = (((xdc_runtime_Error_Id)4558) << 16 | 0); + +/* E_cannotSupport__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_E_cannotSupport__C, ".const:ti_sysbios_family_arm_lm4_Timer_E_cannotSupport__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_E_cannotSupport ti_sysbios_family_arm_lm4_Timer_E_cannotSupport__C = (((xdc_runtime_Error_Id)4597) << 16 | 0); + +/* E_noaltclk__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_E_noaltclk__C, ".const:ti_sysbios_family_arm_lm4_Timer_E_noaltclk__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_E_noaltclk ti_sysbios_family_arm_lm4_Timer_E_noaltclk__C = (((xdc_runtime_Error_Id)4781) << 16 | 0); + +/* anyMask__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_anyMask__C, ".const:ti_sysbios_family_arm_lm4_Timer_anyMask__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_anyMask ti_sysbios_family_arm_lm4_Timer_anyMask__C = (xdc_UInt)0x3f; + +/* supportsAltclk__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_supportsAltclk__C, ".const:ti_sysbios_family_arm_lm4_Timer_supportsAltclk__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_supportsAltclk ti_sysbios_family_arm_lm4_Timer_supportsAltclk__C = 1; + +/* enableFunc__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_enableFunc__C, ".const:ti_sysbios_family_arm_lm4_Timer_enableFunc__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_enableFunc ti_sysbios_family_arm_lm4_Timer_enableFunc__C = ((CT__ti_sysbios_family_arm_lm4_Timer_enableFunc)((xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_enableTiva)); + +/* disableFunc__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_disableFunc__C, ".const:ti_sysbios_family_arm_lm4_Timer_disableFunc__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_disableFunc ti_sysbios_family_arm_lm4_Timer_disableFunc__C = ((CT__ti_sysbios_family_arm_lm4_Timer_disableFunc)((xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_disableTiva)); + +/* startupNeeded__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_startupNeeded__C, ".const:ti_sysbios_family_arm_lm4_Timer_startupNeeded__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_startupNeeded ti_sysbios_family_arm_lm4_Timer_startupNeeded__C = (xdc_UInt)0x1; + +/* numTimerDevices__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_numTimerDevices__C, ".const:ti_sysbios_family_arm_lm4_Timer_numTimerDevices__C"); +__FAR__ const CT__ti_sysbios_family_arm_lm4_Timer_numTimerDevices ti_sysbios_family_arm_lm4_Timer_numTimerDevices__C = (xdc_Int)0x6; + + +/* + * ======== ti.sysbios.family.arm.m3.Hwi INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_family_arm_m3_Hwi_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Object__PARAMS__C, ".const:ti_sysbios_family_arm_m3_Hwi_Object__PARAMS__C"); +__FAR__ const ti_sysbios_family_arm_m3_Hwi_Params ti_sysbios_family_arm_m3_Hwi_Object__PARAMS__C = { + sizeof (ti_sysbios_family_arm_m3_Hwi_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_family_arm_m3_Hwi_Object__PARAMS__C.__iprms, /* instance */ + ti_sysbios_interfaces_IHwi_MaskingOption_LOWER, /* maskSetting */ + ((xdc_UArg)(0x0)), /* arg */ + 1, /* enableInt */ + (xdc_Int)(-0x0 - 1), /* eventId */ + (xdc_Int)0xff, /* priority */ + 1, /* useDispatcher */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_family_arm_m3_Hwi_Module__ ti_sysbios_family_arm_m3_Hwi_Module__root__V = { + {&ti_sysbios_family_arm_m3_Hwi_Module__root__V.link, /* link.next */ + &ti_sysbios_family_arm_m3_Hwi_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_family_arm_m3_Hwi_Object__ ti_sysbios_family_arm_m3_Hwi_Object__table__V[1] = { + {/* instance#0 */ + 0, + ((xdc_UArg)((void*)(ti_sysbios_family_arm_lm4_Timer_Handle)&ti_sysbios_family_arm_lm4_Timer_Object__table__V[0])), /* arg */ + ((xdc_Void(*)(xdc_UArg))((xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_isrStub__E)), /* fxn */ + ((xdc_UArg)(0x3)), /* irp */ + (xdc_UInt8)0xff, /* priority */ + (xdc_Int16)0x23, /* intNum */ + ((void*)0), /* hookEnv */ + }, +}; + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A */ +__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excActive ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A[1] = { + 0, /* [0] */ +}; + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A */ +__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excContext ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A[1] = { + ((ti_sysbios_family_arm_m3_Hwi_ExcContext*)0), /* [0] */ +}; + +/* --> ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A */ +__T1_ti_sysbios_family_arm_m3_Hwi_Module_State__excStack ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A[1] = { + ((xdc_Ptr)0), /* [0] */ +}; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_ti_sysbios_family_arm_m3_Hwi_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +ti_sysbios_family_arm_m3_Hwi_Module_State__ ti_sysbios_family_arm_m3_Hwi_Module__state__V __attribute__ ((section(".data_ti_sysbios_family_arm_m3_Hwi_Module__state__V"))); +#endif +#endif +ti_sysbios_family_arm_m3_Hwi_Module_State__ ti_sysbios_family_arm_m3_Hwi_Module__state__V = { + ((xdc_Char*)0), /* taskSP */ + ((void*)ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A), /* excActive */ + ((void*)ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A), /* excContext */ + ((void*)ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A), /* excStack */ + ((xdc_Ptr)0), /* isrStack */ + ((xdc_Ptr)((void*)&__TI_STACK_BASE)), /* isrStackBase */ + (xdc_SizeT)0x300, /* isrStackSize */ + ((xdc_Ptr)(0x20000000)), /* vectorTableBase */ + (xdc_UInt)0x101, /* swiTaskKeys */ + ((xdc_Ptr)((void*)&ti_sysbios_family_arm_m3_Hwi_dispatchTable[0])), /* dispatchTable */ + 0, /* vnvicFlushRequired */ + ((void*)0), /* intAffinity */ + ((void*)0), /* intAffinityMasks */ +}; + +/* --> ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A, ".const:ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A"); +const __T1_ti_sysbios_family_arm_m3_Hwi_excHookFuncs ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A[2] = { + ((xdc_Void(*)(ti_sysbios_family_arm_m3_Hwi_ExcContext*))0), /* [0] */ + ((xdc_Void(*)(ti_sysbios_family_arm_m3_Hwi_ExcContext*))0), /* [1] */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__diagsEnabled__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__diagsEnabled ti_sysbios_family_arm_m3_Hwi_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__diagsIncluded__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__diagsIncluded ti_sysbios_family_arm_m3_Hwi_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__diagsMask__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__diagsMask ti_sysbios_family_arm_m3_Hwi_Module__diagsMask__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__gateObj__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__gateObj ti_sysbios_family_arm_m3_Hwi_Module__gateObj__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__gatePrms__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__gatePrms ti_sysbios_family_arm_m3_Hwi_Module__gatePrms__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__id__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__id__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__id ti_sysbios_family_arm_m3_Hwi_Module__id__C = (xdc_Bits16)0x8025; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerDefined__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerDefined ti_sysbios_family_arm_m3_Hwi_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerObj__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerObj ti_sysbios_family_arm_m3_Hwi_Module__loggerObj__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn0__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn0 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn0__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn1__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn1 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn1__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn2__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn2 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn2__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn4__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn4 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn4__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn8__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn8 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn8__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Module__startupDoneFxn__C, ".const:ti_sysbios_family_arm_m3_Hwi_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Module__startupDoneFxn ti_sysbios_family_arm_m3_Hwi_Module__startupDoneFxn__C = ((CT__ti_sysbios_family_arm_m3_Hwi_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Object__count__C, ".const:ti_sysbios_family_arm_m3_Hwi_Object__count__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Object__count ti_sysbios_family_arm_m3_Hwi_Object__count__C = 1; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Object__heap__C, ".const:ti_sysbios_family_arm_m3_Hwi_Object__heap__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Object__heap ti_sysbios_family_arm_m3_Hwi_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Object__sizeof__C, ".const:ti_sysbios_family_arm_m3_Hwi_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Object__sizeof ti_sysbios_family_arm_m3_Hwi_Object__sizeof__C = sizeof(ti_sysbios_family_arm_m3_Hwi_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Object__table__C, ".const:ti_sysbios_family_arm_m3_Hwi_Object__table__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_Object__table ti_sysbios_family_arm_m3_Hwi_Object__table__C = ti_sysbios_family_arm_m3_Hwi_Object__table__V; + +/* dispatcherAutoNestingSupport__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_dispatcherAutoNestingSupport__C, ".const:ti_sysbios_family_arm_m3_Hwi_dispatcherAutoNestingSupport__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_dispatcherAutoNestingSupport ti_sysbios_family_arm_m3_Hwi_dispatcherAutoNestingSupport__C = 1; + +/* dispatcherSwiSupport__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_dispatcherSwiSupport__C, ".const:ti_sysbios_family_arm_m3_Hwi_dispatcherSwiSupport__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_dispatcherSwiSupport ti_sysbios_family_arm_m3_Hwi_dispatcherSwiSupport__C = 1; + +/* dispatcherTaskSupport__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_dispatcherTaskSupport__C, ".const:ti_sysbios_family_arm_m3_Hwi_dispatcherTaskSupport__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_dispatcherTaskSupport ti_sysbios_family_arm_m3_Hwi_dispatcherTaskSupport__C = 1; + +/* dispatcherIrpTrackingSupport__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_dispatcherIrpTrackingSupport__C, ".const:ti_sysbios_family_arm_m3_Hwi_dispatcherIrpTrackingSupport__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_dispatcherIrpTrackingSupport ti_sysbios_family_arm_m3_Hwi_dispatcherIrpTrackingSupport__C = 1; + +/* NUM_INTERRUPTS__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_NUM_INTERRUPTS__C, ".const:ti_sysbios_family_arm_m3_Hwi_NUM_INTERRUPTS__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_NUM_INTERRUPTS ti_sysbios_family_arm_m3_Hwi_NUM_INTERRUPTS__C = (xdc_Int)0xd8; + +/* NUM_PRIORITIES__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_NUM_PRIORITIES__C, ".const:ti_sysbios_family_arm_m3_Hwi_NUM_PRIORITIES__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_NUM_PRIORITIES ti_sysbios_family_arm_m3_Hwi_NUM_PRIORITIES__C = (xdc_Int)0x8; + +/* LM_begin__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_LM_begin__C, ".const:ti_sysbios_family_arm_m3_Hwi_LM_begin__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_LM_begin ti_sysbios_family_arm_m3_Hwi_LM_begin__C = (((xdc_runtime_Log_Event)5809) << 16 | 768); + +/* LD_end__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_LD_end__C, ".const:ti_sysbios_family_arm_m3_Hwi_LD_end__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_LD_end ti_sysbios_family_arm_m3_Hwi_LD_end__C = (((xdc_runtime_Log_Event)5879) << 16 | 512); + +/* A_unsupportedMaskingOption__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_A_unsupportedMaskingOption__C, ".const:ti_sysbios_family_arm_m3_Hwi_A_unsupportedMaskingOption__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_A_unsupportedMaskingOption ti_sysbios_family_arm_m3_Hwi_A_unsupportedMaskingOption__C = (((xdc_runtime_Assert_Id)2092) << 16 | 16); + +/* E_alreadyDefined__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_alreadyDefined__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_alreadyDefined__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_alreadyDefined ti_sysbios_family_arm_m3_Hwi_E_alreadyDefined__C = (((xdc_runtime_Error_Id)4036) << 16 | 0); + +/* E_hwiLimitExceeded__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_hwiLimitExceeded__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_hwiLimitExceeded__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_hwiLimitExceeded ti_sysbios_family_arm_m3_Hwi_E_hwiLimitExceeded__C = (((xdc_runtime_Error_Id)4084) << 16 | 0); + +/* E_exception__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_exception__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_exception__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_exception ti_sysbios_family_arm_m3_Hwi_E_exception__C = (((xdc_runtime_Error_Id)4132) << 16 | 0); + +/* E_noIsr__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_noIsr__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_noIsr__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_noIsr ti_sysbios_family_arm_m3_Hwi_E_noIsr__C = (((xdc_runtime_Error_Id)4337) << 16 | 0); + +/* E_NMI__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_NMI__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_NMI__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_NMI ti_sysbios_family_arm_m3_Hwi_E_NMI__C = (((xdc_runtime_Error_Id)4365) << 16 | 0); + +/* E_hardFault__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_hardFault__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_hardFault__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_hardFault ti_sysbios_family_arm_m3_Hwi_E_hardFault__C = (((xdc_runtime_Error_Id)4375) << 16 | 0); + +/* E_memFault__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_memFault__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_memFault__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_memFault ti_sysbios_family_arm_m3_Hwi_E_memFault__C = (((xdc_runtime_Error_Id)4391) << 16 | 0); + +/* E_busFault__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_busFault__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_busFault__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_busFault ti_sysbios_family_arm_m3_Hwi_E_busFault__C = (((xdc_runtime_Error_Id)4421) << 16 | 0); + +/* E_usageFault__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_usageFault__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_usageFault__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_usageFault ti_sysbios_family_arm_m3_Hwi_E_usageFault__C = (((xdc_runtime_Error_Id)4451) << 16 | 0); + +/* E_svCall__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_svCall__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_svCall__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_svCall ti_sysbios_family_arm_m3_Hwi_E_svCall__C = (((xdc_runtime_Error_Id)4468) << 16 | 0); + +/* E_debugMon__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_debugMon__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_debugMon__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_debugMon ti_sysbios_family_arm_m3_Hwi_E_debugMon__C = (((xdc_runtime_Error_Id)4489) << 16 | 0); + +/* E_reserved__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_E_reserved__C, ".const:ti_sysbios_family_arm_m3_Hwi_E_reserved__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_E_reserved ti_sysbios_family_arm_m3_Hwi_E_reserved__C = (((xdc_runtime_Error_Id)4504) << 16 | 0); + +/* nullIsrFunc__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_nullIsrFunc__C, ".const:ti_sysbios_family_arm_m3_Hwi_nullIsrFunc__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_nullIsrFunc ti_sysbios_family_arm_m3_Hwi_nullIsrFunc__C = ((CT__ti_sysbios_family_arm_m3_Hwi_nullIsrFunc)((xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I)); + +/* excHandlerFunc__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_excHandlerFunc__C, ".const:ti_sysbios_family_arm_m3_Hwi_excHandlerFunc__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_excHandlerFunc ti_sysbios_family_arm_m3_Hwi_excHandlerFunc__C = ((CT__ti_sysbios_family_arm_m3_Hwi_excHandlerFunc)((xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_excHandlerMax__I)); + +/* excHookFunc__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_excHookFunc__C, ".const:ti_sysbios_family_arm_m3_Hwi_excHookFunc__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_excHookFunc ti_sysbios_family_arm_m3_Hwi_excHookFunc__C = ((CT__ti_sysbios_family_arm_m3_Hwi_excHookFunc)0); + +/* excHookFuncs__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_excHookFuncs__C, ".const:ti_sysbios_family_arm_m3_Hwi_excHookFuncs__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_excHookFuncs ti_sysbios_family_arm_m3_Hwi_excHookFuncs__C = ((CT__ti_sysbios_family_arm_m3_Hwi_excHookFuncs)ti_sysbios_family_arm_m3_Hwi_excHookFuncs__A); + +/* disablePriority__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_disablePriority__C, ".const:ti_sysbios_family_arm_m3_Hwi_disablePriority__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_disablePriority ti_sysbios_family_arm_m3_Hwi_disablePriority__C = (xdc_UInt)0x20; + +/* priGroup__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_priGroup__C, ".const:ti_sysbios_family_arm_m3_Hwi_priGroup__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_priGroup ti_sysbios_family_arm_m3_Hwi_priGroup__C = (xdc_UInt)0x0; + +/* numSparseInterrupts__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_numSparseInterrupts__C, ".const:ti_sysbios_family_arm_m3_Hwi_numSparseInterrupts__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_numSparseInterrupts ti_sysbios_family_arm_m3_Hwi_numSparseInterrupts__C = (xdc_UInt)0x0; + +/* swiDisable__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_swiDisable__C, ".const:ti_sysbios_family_arm_m3_Hwi_swiDisable__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_swiDisable ti_sysbios_family_arm_m3_Hwi_swiDisable__C = ((CT__ti_sysbios_family_arm_m3_Hwi_swiDisable)((xdc_Fxn)ti_sysbios_knl_Swi_disable__E)); + +/* swiRestoreHwi__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_swiRestoreHwi__C, ".const:ti_sysbios_family_arm_m3_Hwi_swiRestoreHwi__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_swiRestoreHwi ti_sysbios_family_arm_m3_Hwi_swiRestoreHwi__C = ((CT__ti_sysbios_family_arm_m3_Hwi_swiRestoreHwi)((xdc_Fxn)ti_sysbios_knl_Swi_restoreHwi__E)); + +/* taskDisable__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_taskDisable__C, ".const:ti_sysbios_family_arm_m3_Hwi_taskDisable__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_taskDisable ti_sysbios_family_arm_m3_Hwi_taskDisable__C = ((CT__ti_sysbios_family_arm_m3_Hwi_taskDisable)((xdc_Fxn)ti_sysbios_knl_Task_disable__E)); + +/* taskRestoreHwi__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_taskRestoreHwi__C, ".const:ti_sysbios_family_arm_m3_Hwi_taskRestoreHwi__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_taskRestoreHwi ti_sysbios_family_arm_m3_Hwi_taskRestoreHwi__C = ((CT__ti_sysbios_family_arm_m3_Hwi_taskRestoreHwi)((xdc_Fxn)ti_sysbios_knl_Task_restoreHwi__E)); + +/* ccr__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_ccr__C, ".const:ti_sysbios_family_arm_m3_Hwi_ccr__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_ccr ti_sysbios_family_arm_m3_Hwi_ccr__C = (xdc_UInt32)0x200; + +/* hooks__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_hooks__C, ".const:ti_sysbios_family_arm_m3_Hwi_hooks__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_Hwi_hooks ti_sysbios_family_arm_m3_Hwi_hooks__C = {0, 0}; + + +/* + * ======== ti.sysbios.family.arm.m3.IntrinsicsSupport INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsEnabled__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsEnabled ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsIncluded__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsIncluded ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsMask__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsMask ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsMask__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gateObj__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gateObj ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gateObj__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gatePrms__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gatePrms ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gatePrms__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__id__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__id__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__id ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__id__C = (xdc_Bits16)0x8026; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerDefined__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerDefined ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerObj__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerObj ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerObj__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn0__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn0 ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn0__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn1__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn1 ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn1__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn2__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn2 ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn2__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn4__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn4 ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn4__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn8__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn8 ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn8__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDoneFxn__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDoneFxn ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDoneFxn__C = ((CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__count__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__count__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__count ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__heap__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__heap__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__heap ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__sizeof__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__sizeof ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__table__C, ".const:ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__table__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__table ti_sysbios_family_arm_m3_IntrinsicsSupport_Object__table__C = 0; + + +/* + * ======== ti.sysbios.family.arm.m3.TaskSupport INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__diagsEnabled__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__diagsEnabled ti_sysbios_family_arm_m3_TaskSupport_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__diagsIncluded__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__diagsIncluded ti_sysbios_family_arm_m3_TaskSupport_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__diagsMask__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__diagsMask ti_sysbios_family_arm_m3_TaskSupport_Module__diagsMask__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__gateObj__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__gateObj ti_sysbios_family_arm_m3_TaskSupport_Module__gateObj__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__gatePrms__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__gatePrms ti_sysbios_family_arm_m3_TaskSupport_Module__gatePrms__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__id__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__id__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__id ti_sysbios_family_arm_m3_TaskSupport_Module__id__C = (xdc_Bits16)0x8027; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerDefined__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerDefined ti_sysbios_family_arm_m3_TaskSupport_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerObj__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerObj ti_sysbios_family_arm_m3_TaskSupport_Module__loggerObj__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn0__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn0 ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn0__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn1__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn1 ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn1__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn2__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn2 ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn2__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn4__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn4 ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn4__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn8__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn8 ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn8__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Module__startupDoneFxn__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Module__startupDoneFxn ti_sysbios_family_arm_m3_TaskSupport_Module__startupDoneFxn__C = ((CT__ti_sysbios_family_arm_m3_TaskSupport_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Object__count__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Object__count__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Object__count ti_sysbios_family_arm_m3_TaskSupport_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Object__heap__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Object__heap__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Object__heap ti_sysbios_family_arm_m3_TaskSupport_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Object__sizeof__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Object__sizeof ti_sysbios_family_arm_m3_TaskSupport_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_Object__table__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_Object__table__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_Object__table ti_sysbios_family_arm_m3_TaskSupport_Object__table__C = 0; + +/* defaultStackSize__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_defaultStackSize__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_defaultStackSize__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_defaultStackSize ti_sysbios_family_arm_m3_TaskSupport_defaultStackSize__C = (xdc_SizeT)0x800; + +/* stackAlignment__C */ +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_TaskSupport_stackAlignment__C, ".const:ti_sysbios_family_arm_m3_TaskSupport_stackAlignment__C"); +__FAR__ const CT__ti_sysbios_family_arm_m3_TaskSupport_stackAlignment ti_sysbios_family_arm_m3_TaskSupport_stackAlignment__C = (xdc_UInt)0x8; + + +/* + * ======== ti.sysbios.gates.GateHwi INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_gates_GateHwi_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Object__PARAMS__C, ".const:ti_sysbios_gates_GateHwi_Object__PARAMS__C"); +__FAR__ const ti_sysbios_gates_GateHwi_Params ti_sysbios_gates_GateHwi_Object__PARAMS__C = { + sizeof (ti_sysbios_gates_GateHwi_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_gates_GateHwi_Object__PARAMS__C.__iprms, /* instance */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_gates_GateHwi_Module__ ti_sysbios_gates_GateHwi_Module__root__V = { + {&ti_sysbios_gates_GateHwi_Module__root__V.link, /* link.next */ + &ti_sysbios_gates_GateHwi_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_gates_GateHwi_Object__ ti_sysbios_gates_GateHwi_Object__table__V[1] = { + {/* instance#0 */ + &ti_sysbios_gates_GateHwi_Module__FXNS__C, + }, +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__diagsEnabled__C, ".const:ti_sysbios_gates_GateHwi_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__diagsEnabled ti_sysbios_gates_GateHwi_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__diagsIncluded__C, ".const:ti_sysbios_gates_GateHwi_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__diagsIncluded ti_sysbios_gates_GateHwi_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__diagsMask__C, ".const:ti_sysbios_gates_GateHwi_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__diagsMask ti_sysbios_gates_GateHwi_Module__diagsMask__C = ((CT__ti_sysbios_gates_GateHwi_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__gateObj__C, ".const:ti_sysbios_gates_GateHwi_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__gateObj ti_sysbios_gates_GateHwi_Module__gateObj__C = ((CT__ti_sysbios_gates_GateHwi_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__gatePrms__C, ".const:ti_sysbios_gates_GateHwi_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__gatePrms ti_sysbios_gates_GateHwi_Module__gatePrms__C = ((CT__ti_sysbios_gates_GateHwi_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__id__C, ".const:ti_sysbios_gates_GateHwi_Module__id__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__id ti_sysbios_gates_GateHwi_Module__id__C = (xdc_Bits16)0x8029; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerDefined__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerDefined ti_sysbios_gates_GateHwi_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerObj__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerObj ti_sysbios_gates_GateHwi_Module__loggerObj__C = ((CT__ti_sysbios_gates_GateHwi_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerFxn0__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerFxn0 ti_sysbios_gates_GateHwi_Module__loggerFxn0__C = ((CT__ti_sysbios_gates_GateHwi_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerFxn1__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerFxn1 ti_sysbios_gates_GateHwi_Module__loggerFxn1__C = ((CT__ti_sysbios_gates_GateHwi_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerFxn2__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerFxn2 ti_sysbios_gates_GateHwi_Module__loggerFxn2__C = ((CT__ti_sysbios_gates_GateHwi_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerFxn4__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerFxn4 ti_sysbios_gates_GateHwi_Module__loggerFxn4__C = ((CT__ti_sysbios_gates_GateHwi_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__loggerFxn8__C, ".const:ti_sysbios_gates_GateHwi_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__loggerFxn8 ti_sysbios_gates_GateHwi_Module__loggerFxn8__C = ((CT__ti_sysbios_gates_GateHwi_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Module__startupDoneFxn__C, ".const:ti_sysbios_gates_GateHwi_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Module__startupDoneFxn ti_sysbios_gates_GateHwi_Module__startupDoneFxn__C = ((CT__ti_sysbios_gates_GateHwi_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Object__count__C, ".const:ti_sysbios_gates_GateHwi_Object__count__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Object__count ti_sysbios_gates_GateHwi_Object__count__C = 1; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Object__heap__C, ".const:ti_sysbios_gates_GateHwi_Object__heap__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Object__heap ti_sysbios_gates_GateHwi_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Object__sizeof__C, ".const:ti_sysbios_gates_GateHwi_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Object__sizeof ti_sysbios_gates_GateHwi_Object__sizeof__C = sizeof(ti_sysbios_gates_GateHwi_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Object__table__C, ".const:ti_sysbios_gates_GateHwi_Object__table__C"); +__FAR__ const CT__ti_sysbios_gates_GateHwi_Object__table ti_sysbios_gates_GateHwi_Object__table__C = ti_sysbios_gates_GateHwi_Object__table__V; + + +/* + * ======== ti.sysbios.gates.GateMutex INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_gates_GateMutex_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Object__PARAMS__C, ".const:ti_sysbios_gates_GateMutex_Object__PARAMS__C"); +__FAR__ const ti_sysbios_gates_GateMutex_Params ti_sysbios_gates_GateMutex_Object__PARAMS__C = { + sizeof (ti_sysbios_gates_GateMutex_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_gates_GateMutex_Object__PARAMS__C.__iprms, /* instance */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_gates_GateMutex_Module__ ti_sysbios_gates_GateMutex_Module__root__V = { + {&ti_sysbios_gates_GateMutex_Module__root__V.link, /* link.next */ + &ti_sysbios_gates_GateMutex_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_gates_GateMutex_Object__ ti_sysbios_gates_GateMutex_Object__table__V[2] = { + {/* instance#0 */ + &ti_sysbios_gates_GateMutex_Module__FXNS__C, + 0, /* owner */ + { + 0, /* event */ + (xdc_UInt)0x1, /* eventId */ + ti_sysbios_knl_Semaphore_Mode_COUNTING, /* mode */ + (xdc_UInt16)0x1, /* count */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_gates_GateMutex_Object__table__V[0].Object_field_sem.Object_field_pendQ.elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_gates_GateMutex_Object__table__V[0].Object_field_sem.Object_field_pendQ.elem)), /* prev */ + }, /* elem */ + }, /* Object_field_pendQ */ + }, /* Object_field_sem */ + }, + {/* instance#1 */ + &ti_sysbios_gates_GateMutex_Module__FXNS__C, + 0, /* owner */ + { + 0, /* event */ + (xdc_UInt)0x1, /* eventId */ + ti_sysbios_knl_Semaphore_Mode_COUNTING, /* mode */ + (xdc_UInt16)0x1, /* count */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_gates_GateMutex_Object__table__V[1].Object_field_sem.Object_field_pendQ.elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_gates_GateMutex_Object__table__V[1].Object_field_sem.Object_field_pendQ.elem)), /* prev */ + }, /* elem */ + }, /* Object_field_pendQ */ + }, /* Object_field_sem */ + }, +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__diagsEnabled__C, ".const:ti_sysbios_gates_GateMutex_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__diagsEnabled ti_sysbios_gates_GateMutex_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__diagsIncluded__C, ".const:ti_sysbios_gates_GateMutex_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__diagsIncluded ti_sysbios_gates_GateMutex_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__diagsMask__C, ".const:ti_sysbios_gates_GateMutex_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__diagsMask ti_sysbios_gates_GateMutex_Module__diagsMask__C = ((CT__ti_sysbios_gates_GateMutex_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__gateObj__C, ".const:ti_sysbios_gates_GateMutex_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__gateObj ti_sysbios_gates_GateMutex_Module__gateObj__C = ((CT__ti_sysbios_gates_GateMutex_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__gatePrms__C, ".const:ti_sysbios_gates_GateMutex_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__gatePrms ti_sysbios_gates_GateMutex_Module__gatePrms__C = ((CT__ti_sysbios_gates_GateMutex_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__id__C, ".const:ti_sysbios_gates_GateMutex_Module__id__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__id ti_sysbios_gates_GateMutex_Module__id__C = (xdc_Bits16)0x802a; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerDefined__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerDefined ti_sysbios_gates_GateMutex_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerObj__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerObj ti_sysbios_gates_GateMutex_Module__loggerObj__C = ((CT__ti_sysbios_gates_GateMutex_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerFxn0__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerFxn0 ti_sysbios_gates_GateMutex_Module__loggerFxn0__C = ((CT__ti_sysbios_gates_GateMutex_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerFxn1__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerFxn1 ti_sysbios_gates_GateMutex_Module__loggerFxn1__C = ((CT__ti_sysbios_gates_GateMutex_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerFxn2__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerFxn2 ti_sysbios_gates_GateMutex_Module__loggerFxn2__C = ((CT__ti_sysbios_gates_GateMutex_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerFxn4__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerFxn4 ti_sysbios_gates_GateMutex_Module__loggerFxn4__C = ((CT__ti_sysbios_gates_GateMutex_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__loggerFxn8__C, ".const:ti_sysbios_gates_GateMutex_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__loggerFxn8 ti_sysbios_gates_GateMutex_Module__loggerFxn8__C = ((CT__ti_sysbios_gates_GateMutex_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Module__startupDoneFxn__C, ".const:ti_sysbios_gates_GateMutex_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Module__startupDoneFxn ti_sysbios_gates_GateMutex_Module__startupDoneFxn__C = ((CT__ti_sysbios_gates_GateMutex_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Object__count__C, ".const:ti_sysbios_gates_GateMutex_Object__count__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Object__count ti_sysbios_gates_GateMutex_Object__count__C = 2; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Object__heap__C, ".const:ti_sysbios_gates_GateMutex_Object__heap__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Object__heap ti_sysbios_gates_GateMutex_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Object__sizeof__C, ".const:ti_sysbios_gates_GateMutex_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Object__sizeof ti_sysbios_gates_GateMutex_Object__sizeof__C = sizeof(ti_sysbios_gates_GateMutex_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Object__table__C, ".const:ti_sysbios_gates_GateMutex_Object__table__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_Object__table ti_sysbios_gates_GateMutex_Object__table__C = ti_sysbios_gates_GateMutex_Object__table__V; + +/* A_badContext__C */ +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_A_badContext__C, ".const:ti_sysbios_gates_GateMutex_A_badContext__C"); +__FAR__ const CT__ti_sysbios_gates_GateMutex_A_badContext ti_sysbios_gates_GateMutex_A_badContext__C = (((xdc_runtime_Assert_Id)2605) << 16 | 16); + + +/* + * ======== ti.sysbios.hal.Hwi INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_hal_Hwi_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Object__PARAMS__C, ".const:ti_sysbios_hal_Hwi_Object__PARAMS__C"); +__FAR__ const ti_sysbios_hal_Hwi_Params ti_sysbios_hal_Hwi_Object__PARAMS__C = { + sizeof (ti_sysbios_hal_Hwi_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_hal_Hwi_Object__PARAMS__C.__iprms, /* instance */ + ti_sysbios_interfaces_IHwi_MaskingOption_LOWER, /* maskSetting */ + ((xdc_UArg)(0x0)), /* arg */ + 1, /* enableInt */ + (xdc_Int)(-0x0 - 1), /* eventId */ + (xdc_Int)(-0x0 - 1), /* priority */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_hal_Hwi_Module__ ti_sysbios_hal_Hwi_Module__root__V = { + {&ti_sysbios_hal_Hwi_Module__root__V.link, /* link.next */ + &ti_sysbios_hal_Hwi_Module__root__V.link}, /* link.prev */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__diagsEnabled__C, ".const:ti_sysbios_hal_Hwi_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__diagsEnabled ti_sysbios_hal_Hwi_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__diagsIncluded__C, ".const:ti_sysbios_hal_Hwi_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__diagsIncluded ti_sysbios_hal_Hwi_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__diagsMask__C, ".const:ti_sysbios_hal_Hwi_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__diagsMask ti_sysbios_hal_Hwi_Module__diagsMask__C = ((CT__ti_sysbios_hal_Hwi_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__gateObj__C, ".const:ti_sysbios_hal_Hwi_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__gateObj ti_sysbios_hal_Hwi_Module__gateObj__C = ((CT__ti_sysbios_hal_Hwi_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__gatePrms__C, ".const:ti_sysbios_hal_Hwi_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__gatePrms ti_sysbios_hal_Hwi_Module__gatePrms__C = ((CT__ti_sysbios_hal_Hwi_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__id__C, ".const:ti_sysbios_hal_Hwi_Module__id__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__id ti_sysbios_hal_Hwi_Module__id__C = (xdc_Bits16)0x8020; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerDefined__C, ".const:ti_sysbios_hal_Hwi_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerDefined ti_sysbios_hal_Hwi_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerObj__C, ".const:ti_sysbios_hal_Hwi_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerObj ti_sysbios_hal_Hwi_Module__loggerObj__C = ((CT__ti_sysbios_hal_Hwi_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerFxn0__C, ".const:ti_sysbios_hal_Hwi_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerFxn0 ti_sysbios_hal_Hwi_Module__loggerFxn0__C = ((CT__ti_sysbios_hal_Hwi_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerFxn1__C, ".const:ti_sysbios_hal_Hwi_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerFxn1 ti_sysbios_hal_Hwi_Module__loggerFxn1__C = ((CT__ti_sysbios_hal_Hwi_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerFxn2__C, ".const:ti_sysbios_hal_Hwi_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerFxn2 ti_sysbios_hal_Hwi_Module__loggerFxn2__C = ((CT__ti_sysbios_hal_Hwi_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerFxn4__C, ".const:ti_sysbios_hal_Hwi_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerFxn4 ti_sysbios_hal_Hwi_Module__loggerFxn4__C = ((CT__ti_sysbios_hal_Hwi_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__loggerFxn8__C, ".const:ti_sysbios_hal_Hwi_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__loggerFxn8 ti_sysbios_hal_Hwi_Module__loggerFxn8__C = ((CT__ti_sysbios_hal_Hwi_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Module__startupDoneFxn__C, ".const:ti_sysbios_hal_Hwi_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Module__startupDoneFxn ti_sysbios_hal_Hwi_Module__startupDoneFxn__C = ((CT__ti_sysbios_hal_Hwi_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Object__count__C, ".const:ti_sysbios_hal_Hwi_Object__count__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Object__count ti_sysbios_hal_Hwi_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Object__heap__C, ".const:ti_sysbios_hal_Hwi_Object__heap__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Object__heap ti_sysbios_hal_Hwi_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Object__sizeof__C, ".const:ti_sysbios_hal_Hwi_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Object__sizeof ti_sysbios_hal_Hwi_Object__sizeof__C = sizeof(ti_sysbios_hal_Hwi_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Object__table__C, ".const:ti_sysbios_hal_Hwi_Object__table__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_Object__table ti_sysbios_hal_Hwi_Object__table__C = 0; + +/* dispatcherAutoNestingSupport__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport__C, ".const:ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport ti_sysbios_hal_Hwi_dispatcherAutoNestingSupport__C = 1; + +/* dispatcherSwiSupport__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_dispatcherSwiSupport__C, ".const:ti_sysbios_hal_Hwi_dispatcherSwiSupport__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_dispatcherSwiSupport ti_sysbios_hal_Hwi_dispatcherSwiSupport__C = 1; + +/* dispatcherTaskSupport__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_dispatcherTaskSupport__C, ".const:ti_sysbios_hal_Hwi_dispatcherTaskSupport__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_dispatcherTaskSupport ti_sysbios_hal_Hwi_dispatcherTaskSupport__C = 1; + +/* dispatcherIrpTrackingSupport__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport__C, ".const:ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport ti_sysbios_hal_Hwi_dispatcherIrpTrackingSupport__C = 1; + +/* E_stackOverflow__C */ +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_E_stackOverflow__C, ".const:ti_sysbios_hal_Hwi_E_stackOverflow__C"); +__FAR__ const CT__ti_sysbios_hal_Hwi_E_stackOverflow ti_sysbios_hal_Hwi_E_stackOverflow__C = (((xdc_runtime_Error_Id)3999) << 16 | 0); + + +/* + * ======== ti.sysbios.hal.Hwi_HwiProxy INITIALIZERS ======== + */ + + +/* + * ======== ti.sysbios.heaps.HeapMem INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_heaps_HeapMem_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Object__PARAMS__C, ".const:ti_sysbios_heaps_HeapMem_Object__PARAMS__C"); +__FAR__ const ti_sysbios_heaps_HeapMem_Params ti_sysbios_heaps_HeapMem_Object__PARAMS__C = { + sizeof (ti_sysbios_heaps_HeapMem_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_heaps_HeapMem_Object__PARAMS__C.__iprms, /* instance */ + (xdc_SizeT)0x0, /* minBlockAlign */ + ((xdc_Ptr)(0x0)), /* buf */ + ((xdc_UArg)(0x0)), /* size */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* --> ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A */ +__T1_ti_sysbios_heaps_HeapMem_Instance_State__buf ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A[1024]; + +/* Module__root__V */ +ti_sysbios_heaps_HeapMem_Module__ ti_sysbios_heaps_HeapMem_Module__root__V = { + {&ti_sysbios_heaps_HeapMem_Module__root__V.link, /* link.next */ + &ti_sysbios_heaps_HeapMem_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_heaps_HeapMem_Object__ ti_sysbios_heaps_HeapMem_Object__table__V[1] = { + {/* instance#0 */ + &ti_sysbios_heaps_HeapMem_Module__FXNS__C, + ((xdc_UArg)(0x8)), /* align */ + ((void*)ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A), /* buf */ + { + ((ti_sysbios_heaps_HeapMem_Header*)0), /* next */ + ((xdc_UArg)(0x400)), /* size */ + }, /* head */ + (xdc_SizeT)0x8, /* minBlockAlign */ + }, +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__diagsEnabled__C, ".const:ti_sysbios_heaps_HeapMem_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__diagsEnabled ti_sysbios_heaps_HeapMem_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__diagsIncluded__C, ".const:ti_sysbios_heaps_HeapMem_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__diagsIncluded ti_sysbios_heaps_HeapMem_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__diagsMask__C, ".const:ti_sysbios_heaps_HeapMem_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__diagsMask ti_sysbios_heaps_HeapMem_Module__diagsMask__C = ((CT__ti_sysbios_heaps_HeapMem_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__gateObj__C, ".const:ti_sysbios_heaps_HeapMem_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__gateObj ti_sysbios_heaps_HeapMem_Module__gateObj__C = ((CT__ti_sysbios_heaps_HeapMem_Module__gateObj)((void*)(xdc_runtime_IGateProvider_Handle)&ti_sysbios_gates_GateMutex_Object__table__V[0])); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__gatePrms__C, ".const:ti_sysbios_heaps_HeapMem_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__gatePrms ti_sysbios_heaps_HeapMem_Module__gatePrms__C = ((CT__ti_sysbios_heaps_HeapMem_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__id__C, ".const:ti_sysbios_heaps_HeapMem_Module__id__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__id ti_sysbios_heaps_HeapMem_Module__id__C = (xdc_Bits16)0x802c; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerDefined__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerDefined ti_sysbios_heaps_HeapMem_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerObj__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerObj ti_sysbios_heaps_HeapMem_Module__loggerObj__C = ((CT__ti_sysbios_heaps_HeapMem_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerFxn0__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn0 ti_sysbios_heaps_HeapMem_Module__loggerFxn0__C = ((CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerFxn1__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn1 ti_sysbios_heaps_HeapMem_Module__loggerFxn1__C = ((CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerFxn2__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn2 ti_sysbios_heaps_HeapMem_Module__loggerFxn2__C = ((CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerFxn4__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn4 ti_sysbios_heaps_HeapMem_Module__loggerFxn4__C = ((CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__loggerFxn8__C, ".const:ti_sysbios_heaps_HeapMem_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn8 ti_sysbios_heaps_HeapMem_Module__loggerFxn8__C = ((CT__ti_sysbios_heaps_HeapMem_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Module__startupDoneFxn__C, ".const:ti_sysbios_heaps_HeapMem_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Module__startupDoneFxn ti_sysbios_heaps_HeapMem_Module__startupDoneFxn__C = ((CT__ti_sysbios_heaps_HeapMem_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Object__count__C, ".const:ti_sysbios_heaps_HeapMem_Object__count__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Object__count ti_sysbios_heaps_HeapMem_Object__count__C = 1; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Object__heap__C, ".const:ti_sysbios_heaps_HeapMem_Object__heap__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Object__heap ti_sysbios_heaps_HeapMem_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Object__sizeof__C, ".const:ti_sysbios_heaps_HeapMem_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Object__sizeof ti_sysbios_heaps_HeapMem_Object__sizeof__C = sizeof(ti_sysbios_heaps_HeapMem_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Object__table__C, ".const:ti_sysbios_heaps_HeapMem_Object__table__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_Object__table ti_sysbios_heaps_HeapMem_Object__table__C = ti_sysbios_heaps_HeapMem_Object__table__V; + +/* A_zeroBlock__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_A_zeroBlock__C, ".const:ti_sysbios_heaps_HeapMem_A_zeroBlock__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_A_zeroBlock ti_sysbios_heaps_HeapMem_A_zeroBlock__C = (((xdc_runtime_Assert_Id)3291) << 16 | 16); + +/* A_heapSize__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_A_heapSize__C, ".const:ti_sysbios_heaps_HeapMem_A_heapSize__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_A_heapSize ti_sysbios_heaps_HeapMem_A_heapSize__C = (((xdc_runtime_Assert_Id)3327) << 16 | 16); + +/* A_align__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_A_align__C, ".const:ti_sysbios_heaps_HeapMem_A_align__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_A_align ti_sysbios_heaps_HeapMem_A_align__C = (((xdc_runtime_Assert_Id)3372) << 16 | 16); + +/* E_memory__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_E_memory__C, ".const:ti_sysbios_heaps_HeapMem_E_memory__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_E_memory ti_sysbios_heaps_HeapMem_E_memory__C = (((xdc_runtime_Error_Id)4745) << 16 | 0); + +/* A_invalidFree__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_A_invalidFree__C, ".const:ti_sysbios_heaps_HeapMem_A_invalidFree__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_A_invalidFree ti_sysbios_heaps_HeapMem_A_invalidFree__C = (((xdc_runtime_Assert_Id)3263) << 16 | 16); + +/* primaryHeapBaseAddr__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr__C, ".const:ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr__C = ((CT__ti_sysbios_heaps_HeapMem_primaryHeapBaseAddr)0); + +/* primaryHeapEndAddr__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_primaryHeapEndAddr__C, ".const:ti_sysbios_heaps_HeapMem_primaryHeapEndAddr__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_primaryHeapEndAddr ti_sysbios_heaps_HeapMem_primaryHeapEndAddr__C = ((CT__ti_sysbios_heaps_HeapMem_primaryHeapEndAddr)0); + +/* reqAlign__C */ +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_reqAlign__C, ".const:ti_sysbios_heaps_HeapMem_reqAlign__C"); +__FAR__ const CT__ti_sysbios_heaps_HeapMem_reqAlign ti_sysbios_heaps_HeapMem_reqAlign__C = (xdc_SizeT)0x8; + + +/* + * ======== ti.sysbios.heaps.HeapMem_Module_GateProxy INITIALIZERS ======== + */ + + +/* + * ======== ti.sysbios.knl.Clock INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Clock_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Object__PARAMS__C, ".const:ti_sysbios_knl_Clock_Object__PARAMS__C"); +__FAR__ const ti_sysbios_knl_Clock_Params ti_sysbios_knl_Clock_Object__PARAMS__C = { + sizeof (ti_sysbios_knl_Clock_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_knl_Clock_Object__PARAMS__C.__iprms, /* instance */ + 0, /* startFlag */ + (xdc_UInt32)0x0, /* period */ + ((xdc_UArg)0), /* arg */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_knl_Clock_Module__ ti_sysbios_knl_Clock_Module__root__V = { + {&ti_sysbios_knl_Clock_Module__root__V.link, /* link.next */ + &ti_sysbios_knl_Clock_Module__root__V.link}, /* link.prev */ +}; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_ti_sysbios_knl_Clock_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +ti_sysbios_knl_Clock_Module_State__ ti_sysbios_knl_Clock_Module__state__V __attribute__ ((section(".data_ti_sysbios_knl_Clock_Module__state__V"))); +#endif +#endif +ti_sysbios_knl_Clock_Module_State__ ti_sysbios_knl_Clock_Module__state__V = { + (xdc_UInt32)0x0, /* ticks */ + (xdc_UInt)0x0, /* swiCount */ + (ti_sysbios_knl_Clock_TimerProxy_Handle)&ti_sysbios_family_arm_lm4_Timer_Object__table__V[0], /* timer */ + (ti_sysbios_knl_Swi_Handle)&ti_sysbios_knl_Swi_Object__table__V[0], /* swi */ + (xdc_UInt)0x1, /* numTickSkip */ + (xdc_UInt32)0x1, /* nextScheduledTick */ + (xdc_UInt32)0x0, /* maxSkippable */ + 0, /* inWorkFunc */ + 0, /* startDuringWorkFunc */ + 0, /* ticking */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Clock_Module__state__V.Object_field_clockQ.elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Clock_Module__state__V.Object_field_clockQ.elem)), /* prev */ + }, /* elem */ + }, /* Object_field_clockQ */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Clock_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__diagsEnabled ti_sysbios_knl_Clock_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Clock_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__diagsIncluded ti_sysbios_knl_Clock_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__diagsMask__C, ".const:ti_sysbios_knl_Clock_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__diagsMask ti_sysbios_knl_Clock_Module__diagsMask__C = ((CT__ti_sysbios_knl_Clock_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__gateObj__C, ".const:ti_sysbios_knl_Clock_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__gateObj ti_sysbios_knl_Clock_Module__gateObj__C = ((CT__ti_sysbios_knl_Clock_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__gatePrms__C, ".const:ti_sysbios_knl_Clock_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__gatePrms ti_sysbios_knl_Clock_Module__gatePrms__C = ((CT__ti_sysbios_knl_Clock_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__id__C, ".const:ti_sysbios_knl_Clock_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__id ti_sysbios_knl_Clock_Module__id__C = (xdc_Bits16)0x8018; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerDefined__C, ".const:ti_sysbios_knl_Clock_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerDefined ti_sysbios_knl_Clock_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerObj__C, ".const:ti_sysbios_knl_Clock_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerObj ti_sysbios_knl_Clock_Module__loggerObj__C = ((CT__ti_sysbios_knl_Clock_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Clock_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerFxn0 ti_sysbios_knl_Clock_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Clock_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Clock_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerFxn1 ti_sysbios_knl_Clock_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Clock_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Clock_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerFxn2 ti_sysbios_knl_Clock_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Clock_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Clock_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerFxn4 ti_sysbios_knl_Clock_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Clock_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Clock_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__loggerFxn8 ti_sysbios_knl_Clock_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Clock_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Clock_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Module__startupDoneFxn ti_sysbios_knl_Clock_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Clock_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Object__count__C, ".const:ti_sysbios_knl_Clock_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Object__count ti_sysbios_knl_Clock_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Object__heap__C, ".const:ti_sysbios_knl_Clock_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Object__heap ti_sysbios_knl_Clock_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Object__sizeof__C, ".const:ti_sysbios_knl_Clock_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Object__sizeof ti_sysbios_knl_Clock_Object__sizeof__C = sizeof(ti_sysbios_knl_Clock_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Object__table__C, ".const:ti_sysbios_knl_Clock_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_Object__table ti_sysbios_knl_Clock_Object__table__C = 0; + +/* LW_delayed__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_LW_delayed__C, ".const:ti_sysbios_knl_Clock_LW_delayed__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_LW_delayed ti_sysbios_knl_Clock_LW_delayed__C = (((xdc_runtime_Log_Event)4999) << 16 | 1024); + +/* LM_tick__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_LM_tick__C, ".const:ti_sysbios_knl_Clock_LM_tick__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_LM_tick ti_sysbios_knl_Clock_LM_tick__C = (((xdc_runtime_Log_Event)5021) << 16 | 768); + +/* LM_begin__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_LM_begin__C, ".const:ti_sysbios_knl_Clock_LM_begin__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_LM_begin ti_sysbios_knl_Clock_LM_begin__C = (((xdc_runtime_Log_Event)5039) << 16 | 768); + +/* A_clockDisabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_A_clockDisabled__C, ".const:ti_sysbios_knl_Clock_A_clockDisabled__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_A_clockDisabled ti_sysbios_knl_Clock_A_clockDisabled__C = (((xdc_runtime_Assert_Id)712) << 16 | 16); + +/* A_badThreadType__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_A_badThreadType__C, ".const:ti_sysbios_knl_Clock_A_badThreadType__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_A_badThreadType ti_sysbios_knl_Clock_A_badThreadType__C = (((xdc_runtime_Assert_Id)793) << 16 | 16); + +/* serviceMargin__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_serviceMargin__C, ".const:ti_sysbios_knl_Clock_serviceMargin__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_serviceMargin ti_sysbios_knl_Clock_serviceMargin__C = (xdc_UInt32)0x0; + +/* tickSource__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_tickSource__C, ".const:ti_sysbios_knl_Clock_tickSource__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_tickSource ti_sysbios_knl_Clock_tickSource__C = ti_sysbios_knl_Clock_TickSource_TIMER; + +/* tickMode__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_tickMode__C, ".const:ti_sysbios_knl_Clock_tickMode__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_tickMode ti_sysbios_knl_Clock_tickMode__C = ti_sysbios_knl_Clock_TickMode_PERIODIC; + +/* timerId__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_timerId__C, ".const:ti_sysbios_knl_Clock_timerId__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_timerId ti_sysbios_knl_Clock_timerId__C = (xdc_UInt)(-0x0 - 1); + +/* tickPeriod__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_tickPeriod__C, ".const:ti_sysbios_knl_Clock_tickPeriod__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_tickPeriod ti_sysbios_knl_Clock_tickPeriod__C = (xdc_UInt32)0x3e8; + +/* doTickFunc__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_doTickFunc__C, ".const:ti_sysbios_knl_Clock_doTickFunc__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_doTickFunc ti_sysbios_knl_Clock_doTickFunc__C = ((CT__ti_sysbios_knl_Clock_doTickFunc)((xdc_Fxn)ti_sysbios_knl_Clock_doTick__I)); + +/* triggerClock__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Clock_triggerClock__C, ".const:ti_sysbios_knl_Clock_triggerClock__C"); +__FAR__ const CT__ti_sysbios_knl_Clock_triggerClock ti_sysbios_knl_Clock_triggerClock__C = 0; + + +/* + * ======== ti.sysbios.knl.Clock_TimerProxy INITIALIZERS ======== + */ + + +/* + * ======== ti.sysbios.knl.Idle INITIALIZERS ======== + */ + +/* --> ti_sysbios_knl_Idle_funcList__A */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_funcList__A, ".const:ti_sysbios_knl_Idle_funcList__A"); +const __T1_ti_sysbios_knl_Idle_funcList ti_sysbios_knl_Idle_funcList__A[1] = { + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_hal_Hwi_checkStack)), /* [0] */ +}; + +/* --> ti_sysbios_knl_Idle_coreList__A */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_coreList__A, ".const:ti_sysbios_knl_Idle_coreList__A"); +const __T1_ti_sysbios_knl_Idle_coreList ti_sysbios_knl_Idle_coreList__A[1] = { + (xdc_UInt)0x0, /* [0] */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Idle_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__diagsEnabled ti_sysbios_knl_Idle_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Idle_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__diagsIncluded ti_sysbios_knl_Idle_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__diagsMask__C, ".const:ti_sysbios_knl_Idle_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__diagsMask ti_sysbios_knl_Idle_Module__diagsMask__C = ((CT__ti_sysbios_knl_Idle_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__gateObj__C, ".const:ti_sysbios_knl_Idle_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__gateObj ti_sysbios_knl_Idle_Module__gateObj__C = ((CT__ti_sysbios_knl_Idle_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__gatePrms__C, ".const:ti_sysbios_knl_Idle_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__gatePrms ti_sysbios_knl_Idle_Module__gatePrms__C = ((CT__ti_sysbios_knl_Idle_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__id__C, ".const:ti_sysbios_knl_Idle_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__id ti_sysbios_knl_Idle_Module__id__C = (xdc_Bits16)0x8019; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerDefined__C, ".const:ti_sysbios_knl_Idle_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerDefined ti_sysbios_knl_Idle_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerObj__C, ".const:ti_sysbios_knl_Idle_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerObj ti_sysbios_knl_Idle_Module__loggerObj__C = ((CT__ti_sysbios_knl_Idle_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Idle_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerFxn0 ti_sysbios_knl_Idle_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Idle_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Idle_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerFxn1 ti_sysbios_knl_Idle_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Idle_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Idle_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerFxn2 ti_sysbios_knl_Idle_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Idle_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Idle_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerFxn4 ti_sysbios_knl_Idle_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Idle_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Idle_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__loggerFxn8 ti_sysbios_knl_Idle_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Idle_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Idle_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Module__startupDoneFxn ti_sysbios_knl_Idle_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Idle_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Object__count__C, ".const:ti_sysbios_knl_Idle_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Object__count ti_sysbios_knl_Idle_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Object__heap__C, ".const:ti_sysbios_knl_Idle_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Object__heap ti_sysbios_knl_Idle_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Object__sizeof__C, ".const:ti_sysbios_knl_Idle_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Object__sizeof ti_sysbios_knl_Idle_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_Object__table__C, ".const:ti_sysbios_knl_Idle_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_Object__table ti_sysbios_knl_Idle_Object__table__C = 0; + +/* funcList__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_funcList__C, ".const:ti_sysbios_knl_Idle_funcList__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_funcList ti_sysbios_knl_Idle_funcList__C = {1, ((__T1_ti_sysbios_knl_Idle_funcList*)ti_sysbios_knl_Idle_funcList__A)}; + +/* coreList__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Idle_coreList__C, ".const:ti_sysbios_knl_Idle_coreList__C"); +__FAR__ const CT__ti_sysbios_knl_Idle_coreList ti_sysbios_knl_Idle_coreList__C = {1, ((__T1_ti_sysbios_knl_Idle_coreList*)ti_sysbios_knl_Idle_coreList__A)}; + + +/* + * ======== ti.sysbios.knl.Intrinsics INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Intrinsics_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__diagsEnabled ti_sysbios_knl_Intrinsics_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Intrinsics_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__diagsIncluded ti_sysbios_knl_Intrinsics_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__diagsMask__C, ".const:ti_sysbios_knl_Intrinsics_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__diagsMask ti_sysbios_knl_Intrinsics_Module__diagsMask__C = ((CT__ti_sysbios_knl_Intrinsics_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__gateObj__C, ".const:ti_sysbios_knl_Intrinsics_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__gateObj ti_sysbios_knl_Intrinsics_Module__gateObj__C = ((CT__ti_sysbios_knl_Intrinsics_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__gatePrms__C, ".const:ti_sysbios_knl_Intrinsics_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__gatePrms ti_sysbios_knl_Intrinsics_Module__gatePrms__C = ((CT__ti_sysbios_knl_Intrinsics_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__id__C, ".const:ti_sysbios_knl_Intrinsics_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__id ti_sysbios_knl_Intrinsics_Module__id__C = (xdc_Bits16)0x801a; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerDefined__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerDefined ti_sysbios_knl_Intrinsics_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerObj__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerObj ti_sysbios_knl_Intrinsics_Module__loggerObj__C = ((CT__ti_sysbios_knl_Intrinsics_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn0 ti_sysbios_knl_Intrinsics_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn1 ti_sysbios_knl_Intrinsics_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn2 ti_sysbios_knl_Intrinsics_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn4 ti_sysbios_knl_Intrinsics_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Intrinsics_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn8 ti_sysbios_knl_Intrinsics_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Intrinsics_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Intrinsics_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Module__startupDoneFxn ti_sysbios_knl_Intrinsics_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Intrinsics_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Object__count__C, ".const:ti_sysbios_knl_Intrinsics_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Object__count ti_sysbios_knl_Intrinsics_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Object__heap__C, ".const:ti_sysbios_knl_Intrinsics_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Object__heap ti_sysbios_knl_Intrinsics_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Object__sizeof__C, ".const:ti_sysbios_knl_Intrinsics_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Object__sizeof ti_sysbios_knl_Intrinsics_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Intrinsics_Object__table__C, ".const:ti_sysbios_knl_Intrinsics_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Intrinsics_Object__table ti_sysbios_knl_Intrinsics_Object__table__C = 0; + + +/* + * ======== ti.sysbios.knl.Intrinsics_SupportProxy INITIALIZERS ======== + */ + + +/* + * ======== ti.sysbios.knl.Queue INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Queue_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Object__PARAMS__C, ".const:ti_sysbios_knl_Queue_Object__PARAMS__C"); +__FAR__ const ti_sysbios_knl_Queue_Params ti_sysbios_knl_Queue_Object__PARAMS__C = { + sizeof (ti_sysbios_knl_Queue_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_knl_Queue_Object__PARAMS__C.__iprms, /* instance */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_knl_Queue_Module__ ti_sysbios_knl_Queue_Module__root__V = { + {&ti_sysbios_knl_Queue_Module__root__V.link, /* link.next */ + &ti_sysbios_knl_Queue_Module__root__V.link}, /* link.prev */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Queue_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__diagsEnabled ti_sysbios_knl_Queue_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Queue_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__diagsIncluded ti_sysbios_knl_Queue_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__diagsMask__C, ".const:ti_sysbios_knl_Queue_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__diagsMask ti_sysbios_knl_Queue_Module__diagsMask__C = ((CT__ti_sysbios_knl_Queue_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__gateObj__C, ".const:ti_sysbios_knl_Queue_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__gateObj ti_sysbios_knl_Queue_Module__gateObj__C = ((CT__ti_sysbios_knl_Queue_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__gatePrms__C, ".const:ti_sysbios_knl_Queue_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__gatePrms ti_sysbios_knl_Queue_Module__gatePrms__C = ((CT__ti_sysbios_knl_Queue_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__id__C, ".const:ti_sysbios_knl_Queue_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__id ti_sysbios_knl_Queue_Module__id__C = (xdc_Bits16)0x801b; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerDefined__C, ".const:ti_sysbios_knl_Queue_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerDefined ti_sysbios_knl_Queue_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerObj__C, ".const:ti_sysbios_knl_Queue_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerObj ti_sysbios_knl_Queue_Module__loggerObj__C = ((CT__ti_sysbios_knl_Queue_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Queue_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerFxn0 ti_sysbios_knl_Queue_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Queue_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Queue_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerFxn1 ti_sysbios_knl_Queue_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Queue_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Queue_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerFxn2 ti_sysbios_knl_Queue_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Queue_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Queue_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerFxn4 ti_sysbios_knl_Queue_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Queue_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Queue_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__loggerFxn8 ti_sysbios_knl_Queue_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Queue_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Queue_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Module__startupDoneFxn ti_sysbios_knl_Queue_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Queue_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Object__count__C, ".const:ti_sysbios_knl_Queue_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Object__count ti_sysbios_knl_Queue_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Object__heap__C, ".const:ti_sysbios_knl_Queue_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Object__heap ti_sysbios_knl_Queue_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Object__sizeof__C, ".const:ti_sysbios_knl_Queue_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Object__sizeof ti_sysbios_knl_Queue_Object__sizeof__C = sizeof(ti_sysbios_knl_Queue_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Object__table__C, ".const:ti_sysbios_knl_Queue_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Queue_Object__table ti_sysbios_knl_Queue_Object__table__C = 0; + + +/* + * ======== ti.sysbios.knl.Semaphore INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Semaphore_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Object__PARAMS__C, ".const:ti_sysbios_knl_Semaphore_Object__PARAMS__C"); +__FAR__ const ti_sysbios_knl_Semaphore_Params ti_sysbios_knl_Semaphore_Object__PARAMS__C = { + sizeof (ti_sysbios_knl_Semaphore_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_knl_Semaphore_Object__PARAMS__C.__iprms, /* instance */ + 0, /* event */ + (xdc_UInt)0x1, /* eventId */ + ti_sysbios_knl_Semaphore_Mode_COUNTING, /* mode */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_knl_Semaphore_Module__ ti_sysbios_knl_Semaphore_Module__root__V = { + {&ti_sysbios_knl_Semaphore_Module__root__V.link, /* link.next */ + &ti_sysbios_knl_Semaphore_Module__root__V.link}, /* link.prev */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Semaphore_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__diagsEnabled ti_sysbios_knl_Semaphore_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Semaphore_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__diagsIncluded ti_sysbios_knl_Semaphore_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__diagsMask__C, ".const:ti_sysbios_knl_Semaphore_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__diagsMask ti_sysbios_knl_Semaphore_Module__diagsMask__C = ((CT__ti_sysbios_knl_Semaphore_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__gateObj__C, ".const:ti_sysbios_knl_Semaphore_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__gateObj ti_sysbios_knl_Semaphore_Module__gateObj__C = ((CT__ti_sysbios_knl_Semaphore_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__gatePrms__C, ".const:ti_sysbios_knl_Semaphore_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__gatePrms ti_sysbios_knl_Semaphore_Module__gatePrms__C = ((CT__ti_sysbios_knl_Semaphore_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__id__C, ".const:ti_sysbios_knl_Semaphore_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__id ti_sysbios_knl_Semaphore_Module__id__C = (xdc_Bits16)0x801c; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerDefined__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerDefined ti_sysbios_knl_Semaphore_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerObj__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerObj ti_sysbios_knl_Semaphore_Module__loggerObj__C = ((CT__ti_sysbios_knl_Semaphore_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn0 ti_sysbios_knl_Semaphore_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Semaphore_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn1 ti_sysbios_knl_Semaphore_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Semaphore_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn2 ti_sysbios_knl_Semaphore_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Semaphore_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn4 ti_sysbios_knl_Semaphore_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Semaphore_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Semaphore_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__loggerFxn8 ti_sysbios_knl_Semaphore_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Semaphore_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Semaphore_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Module__startupDoneFxn ti_sysbios_knl_Semaphore_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Semaphore_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Object__count__C, ".const:ti_sysbios_knl_Semaphore_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Object__count ti_sysbios_knl_Semaphore_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Object__heap__C, ".const:ti_sysbios_knl_Semaphore_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Object__heap ti_sysbios_knl_Semaphore_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Object__sizeof__C, ".const:ti_sysbios_knl_Semaphore_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Object__sizeof ti_sysbios_knl_Semaphore_Object__sizeof__C = sizeof(ti_sysbios_knl_Semaphore_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Object__table__C, ".const:ti_sysbios_knl_Semaphore_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_Object__table ti_sysbios_knl_Semaphore_Object__table__C = 0; + +/* LM_post__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_LM_post__C, ".const:ti_sysbios_knl_Semaphore_LM_post__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_LM_post ti_sysbios_knl_Semaphore_LM_post__C = (((xdc_runtime_Log_Event)5071) << 16 | 768); + +/* LM_pend__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_LM_pend__C, ".const:ti_sysbios_knl_Semaphore_LM_pend__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_LM_pend ti_sysbios_knl_Semaphore_LM_pend__C = (((xdc_runtime_Log_Event)5101) << 16 | 768); + +/* A_noEvents__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_A_noEvents__C, ".const:ti_sysbios_knl_Semaphore_A_noEvents__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_A_noEvents ti_sysbios_knl_Semaphore_A_noEvents__C = (((xdc_runtime_Assert_Id)1203) << 16 | 16); + +/* A_invTimeout__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_A_invTimeout__C, ".const:ti_sysbios_knl_Semaphore_A_invTimeout__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_A_invTimeout ti_sysbios_knl_Semaphore_A_invTimeout__C = (((xdc_runtime_Assert_Id)1258) << 16 | 16); + +/* A_badContext__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_A_badContext__C, ".const:ti_sysbios_knl_Semaphore_A_badContext__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_A_badContext ti_sysbios_knl_Semaphore_A_badContext__C = (((xdc_runtime_Assert_Id)992) << 16 | 16); + +/* A_overflow__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_A_overflow__C, ".const:ti_sysbios_knl_Semaphore_A_overflow__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_A_overflow ti_sysbios_knl_Semaphore_A_overflow__C = (((xdc_runtime_Assert_Id)1323) << 16 | 16); + +/* A_pendTaskDisabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_A_pendTaskDisabled__C, ".const:ti_sysbios_knl_Semaphore_A_pendTaskDisabled__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_A_pendTaskDisabled ti_sysbios_knl_Semaphore_A_pendTaskDisabled__C = (((xdc_runtime_Assert_Id)1377) << 16 | 16); + +/* supportsEvents__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_supportsEvents__C, ".const:ti_sysbios_knl_Semaphore_supportsEvents__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_supportsEvents ti_sysbios_knl_Semaphore_supportsEvents__C = 0; + +/* supportsPriority__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_supportsPriority__C, ".const:ti_sysbios_knl_Semaphore_supportsPriority__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_supportsPriority ti_sysbios_knl_Semaphore_supportsPriority__C = 0; + +/* eventPost__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_eventPost__C, ".const:ti_sysbios_knl_Semaphore_eventPost__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_eventPost ti_sysbios_knl_Semaphore_eventPost__C = ((CT__ti_sysbios_knl_Semaphore_eventPost)0); + +/* eventSync__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_eventSync__C, ".const:ti_sysbios_knl_Semaphore_eventSync__C"); +__FAR__ const CT__ti_sysbios_knl_Semaphore_eventSync ti_sysbios_knl_Semaphore_eventSync__C = ((CT__ti_sysbios_knl_Semaphore_eventSync)0); + + +/* + * ======== ti.sysbios.knl.Swi INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Swi_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Object__PARAMS__C, ".const:ti_sysbios_knl_Swi_Object__PARAMS__C"); +__FAR__ const ti_sysbios_knl_Swi_Params ti_sysbios_knl_Swi_Object__PARAMS__C = { + sizeof (ti_sysbios_knl_Swi_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_knl_Swi_Object__PARAMS__C.__iprms, /* instance */ + ((xdc_UArg)(0x0)), /* arg0 */ + ((xdc_UArg)(0x0)), /* arg1 */ + (xdc_UInt)(-0x0 - 1), /* priority */ + (xdc_UInt)0x0, /* trigger */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* Module__root__V */ +ti_sysbios_knl_Swi_Module__ ti_sysbios_knl_Swi_Module__root__V = { + {&ti_sysbios_knl_Swi_Module__root__V.link, /* link.next */ + &ti_sysbios_knl_Swi_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_knl_Swi_Object__ ti_sysbios_knl_Swi_Object__table__V[1] = { + {/* instance#0 */ + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Object__table__V[0].qElem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Object__table__V[0].qElem)), /* prev */ + }, /* qElem */ + ((xdc_Void(*)(xdc_UArg,xdc_UArg))((xdc_Fxn)ti_sysbios_knl_Clock_workFunc__E)), /* fxn */ + ((xdc_UArg)(0x0)), /* arg0 */ + ((xdc_UArg)(0x0)), /* arg1 */ + (xdc_UInt)0xf, /* priority */ + (xdc_UInt)0x8000, /* mask */ + 0, /* posted */ + (xdc_UInt)0x0, /* initTrigger */ + (xdc_UInt)0x0, /* trigger */ + (ti_sysbios_knl_Queue_Handle)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[15], /* readyQ */ + ((void*)0), /* hookEnv */ + }, +}; + +/* --> ti_sysbios_knl_Swi_Module_State_0_readyQ__A */ +__T1_ti_sysbios_knl_Swi_Module_State__readyQ ti_sysbios_knl_Swi_Module_State_0_readyQ__A[16] = { + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[0].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[0].elem)), /* prev */ + }, /* elem */ + }, /* [0] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[1].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[1].elem)), /* prev */ + }, /* elem */ + }, /* [1] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[2].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[2].elem)), /* prev */ + }, /* elem */ + }, /* [2] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[3].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[3].elem)), /* prev */ + }, /* elem */ + }, /* [3] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[4].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[4].elem)), /* prev */ + }, /* elem */ + }, /* [4] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[5].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[5].elem)), /* prev */ + }, /* elem */ + }, /* [5] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[6].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[6].elem)), /* prev */ + }, /* elem */ + }, /* [6] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[7].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[7].elem)), /* prev */ + }, /* elem */ + }, /* [7] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[8].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[8].elem)), /* prev */ + }, /* elem */ + }, /* [8] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[9].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[9].elem)), /* prev */ + }, /* elem */ + }, /* [9] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[10].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[10].elem)), /* prev */ + }, /* elem */ + }, /* [10] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[11].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[11].elem)), /* prev */ + }, /* elem */ + }, /* [11] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[12].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[12].elem)), /* prev */ + }, /* elem */ + }, /* [12] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[13].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[13].elem)), /* prev */ + }, /* elem */ + }, /* [13] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[14].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[14].elem)), /* prev */ + }, /* elem */ + }, /* [14] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[15].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Swi_Module_State_0_readyQ__A[15].elem)), /* prev */ + }, /* elem */ + }, /* [15] */ +}; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_ti_sysbios_knl_Swi_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +ti_sysbios_knl_Swi_Module_State__ ti_sysbios_knl_Swi_Module__state__V __attribute__ ((section(".data_ti_sysbios_knl_Swi_Module__state__V"))); +#endif +#endif +ti_sysbios_knl_Swi_Module_State__ ti_sysbios_knl_Swi_Module__state__V = { + 1, /* locked */ + (xdc_UInt)0x0, /* curSet */ + (xdc_UInt)0x0, /* curTrigger */ + 0, /* curSwi */ + 0, /* curQ */ + ((void*)ti_sysbios_knl_Swi_Module_State_0_readyQ__A), /* readyQ */ + ((void*)0), /* constructedSwis */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Swi_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__diagsEnabled ti_sysbios_knl_Swi_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Swi_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__diagsIncluded ti_sysbios_knl_Swi_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__diagsMask__C, ".const:ti_sysbios_knl_Swi_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__diagsMask ti_sysbios_knl_Swi_Module__diagsMask__C = ((CT__ti_sysbios_knl_Swi_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__gateObj__C, ".const:ti_sysbios_knl_Swi_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__gateObj ti_sysbios_knl_Swi_Module__gateObj__C = ((CT__ti_sysbios_knl_Swi_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__gatePrms__C, ".const:ti_sysbios_knl_Swi_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__gatePrms ti_sysbios_knl_Swi_Module__gatePrms__C = ((CT__ti_sysbios_knl_Swi_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__id__C, ".const:ti_sysbios_knl_Swi_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__id ti_sysbios_knl_Swi_Module__id__C = (xdc_Bits16)0x801d; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerDefined__C, ".const:ti_sysbios_knl_Swi_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerDefined ti_sysbios_knl_Swi_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerObj__C, ".const:ti_sysbios_knl_Swi_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerObj ti_sysbios_knl_Swi_Module__loggerObj__C = ((CT__ti_sysbios_knl_Swi_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Swi_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerFxn0 ti_sysbios_knl_Swi_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Swi_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Swi_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerFxn1 ti_sysbios_knl_Swi_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Swi_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Swi_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerFxn2 ti_sysbios_knl_Swi_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Swi_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Swi_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerFxn4 ti_sysbios_knl_Swi_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Swi_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Swi_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__loggerFxn8 ti_sysbios_knl_Swi_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Swi_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Swi_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Module__startupDoneFxn ti_sysbios_knl_Swi_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Swi_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Object__count__C, ".const:ti_sysbios_knl_Swi_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Object__count ti_sysbios_knl_Swi_Object__count__C = 1; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Object__heap__C, ".const:ti_sysbios_knl_Swi_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Object__heap ti_sysbios_knl_Swi_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Object__sizeof__C, ".const:ti_sysbios_knl_Swi_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Object__sizeof ti_sysbios_knl_Swi_Object__sizeof__C = sizeof(ti_sysbios_knl_Swi_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Object__table__C, ".const:ti_sysbios_knl_Swi_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_Object__table ti_sysbios_knl_Swi_Object__table__C = ti_sysbios_knl_Swi_Object__table__V; + +/* LM_begin__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_LM_begin__C, ".const:ti_sysbios_knl_Swi_LM_begin__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_LM_begin ti_sysbios_knl_Swi_LM_begin__C = (((xdc_runtime_Log_Event)5144) << 16 | 768); + +/* LD_end__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_LD_end__C, ".const:ti_sysbios_knl_Swi_LD_end__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_LD_end ti_sysbios_knl_Swi_LD_end__C = (((xdc_runtime_Log_Event)5191) << 16 | 512); + +/* LM_post__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_LM_post__C, ".const:ti_sysbios_knl_Swi_LM_post__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_LM_post ti_sysbios_knl_Swi_LM_post__C = (((xdc_runtime_Log_Event)5209) << 16 | 768); + +/* A_swiDisabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_A_swiDisabled__C, ".const:ti_sysbios_knl_Swi_A_swiDisabled__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_A_swiDisabled ti_sysbios_knl_Swi_A_swiDisabled__C = (((xdc_runtime_Assert_Id)1471) << 16 | 16); + +/* A_badPriority__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_A_badPriority__C, ".const:ti_sysbios_knl_Swi_A_badPriority__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_A_badPriority ti_sysbios_knl_Swi_A_badPriority__C = (((xdc_runtime_Assert_Id)1528) << 16 | 16); + +/* numPriorities__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_numPriorities__C, ".const:ti_sysbios_knl_Swi_numPriorities__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_numPriorities ti_sysbios_knl_Swi_numPriorities__C = (xdc_UInt)0x10; + +/* hooks__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_hooks__C, ".const:ti_sysbios_knl_Swi_hooks__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_hooks ti_sysbios_knl_Swi_hooks__C = {0, 0}; + +/* taskDisable__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_taskDisable__C, ".const:ti_sysbios_knl_Swi_taskDisable__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_taskDisable ti_sysbios_knl_Swi_taskDisable__C = ((CT__ti_sysbios_knl_Swi_taskDisable)((xdc_Fxn)ti_sysbios_knl_Task_disable__E)); + +/* taskRestore__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_taskRestore__C, ".const:ti_sysbios_knl_Swi_taskRestore__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_taskRestore ti_sysbios_knl_Swi_taskRestore__C = ((CT__ti_sysbios_knl_Swi_taskRestore)((xdc_Fxn)ti_sysbios_knl_Task_restore__E)); + +/* numConstructedSwis__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Swi_numConstructedSwis__C, ".const:ti_sysbios_knl_Swi_numConstructedSwis__C"); +__FAR__ const CT__ti_sysbios_knl_Swi_numConstructedSwis ti_sysbios_knl_Swi_numConstructedSwis__C = (xdc_UInt)0x0; + + +/* + * ======== ti.sysbios.knl.Task INITIALIZERS ======== + */ + +/* Object__DESC__C */ +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Task_Object__DESC__C; + +/* Object__PARAMS__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Object__PARAMS__C, ".const:ti_sysbios_knl_Task_Object__PARAMS__C"); +__FAR__ const ti_sysbios_knl_Task_Params ti_sysbios_knl_Task_Object__PARAMS__C = { + sizeof (ti_sysbios_knl_Task_Params), /* __size */ + 0, /* __self */ + 0, /* __fxns */ + (xdc_runtime_IInstance_Params*)&ti_sysbios_knl_Task_Object__PARAMS__C.__iprms, /* instance */ + ((xdc_UArg)(0x0)), /* arg0 */ + ((xdc_UArg)(0x0)), /* arg1 */ + (xdc_Int)0x1, /* priority */ + ((xdc_Ptr)0), /* stack */ + (xdc_SizeT)0x0, /* stackSize */ + 0, /* stackHeap */ + ((xdc_Ptr)0), /* env */ + 1, /* vitalTaskFlag */ + (xdc_UInt)0x0, /* affinity */ + { + sizeof (xdc_runtime_IInstance_Params), /* __size */ + 0, /* name */ + }, /* instance */ +}; + +/* --> ti_sysbios_knl_Task_Instance_State_0_stack__A */ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_0_stack__A[1024]; + +/* --> ti_sysbios_knl_Task_Instance_State_1_stack__A */ +__T1_ti_sysbios_knl_Task_Instance_State__stack ti_sysbios_knl_Task_Instance_State_1_stack__A[512]; + +/* Module__root__V */ +ti_sysbios_knl_Task_Module__ ti_sysbios_knl_Task_Module__root__V = { + {&ti_sysbios_knl_Task_Module__root__V.link, /* link.next */ + &ti_sysbios_knl_Task_Module__root__V.link}, /* link.prev */ +}; + +/* Object__table__V */ +ti_sysbios_knl_Task_Object__ ti_sysbios_knl_Task_Object__table__V[2] = { + {/* instance#0 */ + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Object__table__V[0].qElem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Object__table__V[0].qElem)), /* prev */ + }, /* qElem */ + (xdc_Int)0x1, /* priority */ + (xdc_UInt)0x2, /* mask */ + ((xdc_Ptr)0), /* context */ + ti_sysbios_knl_Task_Mode_INACTIVE, /* mode */ + ((ti_sysbios_knl_Task_PendElem*)0), /* pendElem */ + (xdc_SizeT)0x400, /* stackSize */ + ((void*)ti_sysbios_knl_Task_Instance_State_0_stack__A), /* stack */ + 0, /* stackHeap */ + ((xdc_Void(*)(xdc_UArg,xdc_UArg))((xdc_Fxn)UARTMon_taskFxn)), /* fxn */ + ((xdc_UArg)(0x0)), /* arg0 */ + ((xdc_UArg)(0x2580)), /* arg1 */ + ((xdc_Ptr)0), /* env */ + ((void*)0), /* hookEnv */ + 1, /* vitalTaskFlag */ + 0, /* readyQ */ + (xdc_UInt)0x0, /* curCoreId */ + (xdc_UInt)0x0, /* affinity */ + }, + {/* instance#1 */ + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Object__table__V[1].qElem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Object__table__V[1].qElem)), /* prev */ + }, /* qElem */ + (xdc_Int)0x0, /* priority */ + (xdc_UInt)0x1, /* mask */ + ((xdc_Ptr)0), /* context */ + ti_sysbios_knl_Task_Mode_INACTIVE, /* mode */ + ((ti_sysbios_knl_Task_PendElem*)0), /* pendElem */ + (xdc_SizeT)0x200, /* stackSize */ + ((void*)ti_sysbios_knl_Task_Instance_State_1_stack__A), /* stack */ + 0, /* stackHeap */ + ((xdc_Void(*)(xdc_UArg,xdc_UArg))((xdc_Fxn)ti_sysbios_knl_Idle_loop__E)), /* fxn */ + ((xdc_UArg)(0x0)), /* arg0 */ + ((xdc_UArg)(0x0)), /* arg1 */ + ((xdc_Ptr)0), /* env */ + ((void*)0), /* hookEnv */ + 1, /* vitalTaskFlag */ + 0, /* readyQ */ + (xdc_UInt)0x0, /* curCoreId */ + (xdc_UInt)0x0, /* affinity */ + }, +}; + +/* --> ti_sysbios_knl_Task_Module_State_0_readyQ__A */ +__T1_ti_sysbios_knl_Task_Module_State__readyQ ti_sysbios_knl_Task_Module_State_0_readyQ__A[16] = { + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[0].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[0].elem)), /* prev */ + }, /* elem */ + }, /* [0] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[1].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[1].elem)), /* prev */ + }, /* elem */ + }, /* [1] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[2].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[2].elem)), /* prev */ + }, /* elem */ + }, /* [2] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[3].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[3].elem)), /* prev */ + }, /* elem */ + }, /* [3] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[4].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[4].elem)), /* prev */ + }, /* elem */ + }, /* [4] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[5].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[5].elem)), /* prev */ + }, /* elem */ + }, /* [5] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[6].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[6].elem)), /* prev */ + }, /* elem */ + }, /* [6] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[7].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[7].elem)), /* prev */ + }, /* elem */ + }, /* [7] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[8].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[8].elem)), /* prev */ + }, /* elem */ + }, /* [8] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[9].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[9].elem)), /* prev */ + }, /* elem */ + }, /* [9] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[10].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[10].elem)), /* prev */ + }, /* elem */ + }, /* [10] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[11].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[11].elem)), /* prev */ + }, /* elem */ + }, /* [11] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[12].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[12].elem)), /* prev */ + }, /* elem */ + }, /* [12] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[13].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[13].elem)), /* prev */ + }, /* elem */ + }, /* [13] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[14].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[14].elem)), /* prev */ + }, /* elem */ + }, /* [14] */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[15].elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module_State_0_readyQ__A[15].elem)), /* prev */ + }, /* elem */ + }, /* [15] */ +}; + +/* --> ti_sysbios_knl_Task_Module_State_0_idleTask__A */ +__T1_ti_sysbios_knl_Task_Module_State__idleTask ti_sysbios_knl_Task_Module_State_0_idleTask__A[1] = { + (ti_sysbios_knl_Task_Handle)&ti_sysbios_knl_Task_Object__table__V[1], /* [0] */ +}; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_ti_sysbios_knl_Task_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +ti_sysbios_knl_Task_Module_State__ ti_sysbios_knl_Task_Module__state__V __attribute__ ((section(".data_ti_sysbios_knl_Task_Module__state__V"))); +#endif +#endif +ti_sysbios_knl_Task_Module_State__ ti_sysbios_knl_Task_Module__state__V = { + 1, /* locked */ + (xdc_UInt)0x0, /* curSet */ + 0, /* workFlag */ + (xdc_UInt)0x2, /* vitalTasks */ + 0, /* curTask */ + 0, /* curQ */ + ((void*)ti_sysbios_knl_Task_Module_State_0_readyQ__A), /* readyQ */ + ((void*)0), /* smpCurSet */ + ((void*)0), /* smpCurMask */ + ((void*)0), /* smpCurTask */ + ((void*)0), /* smpReadyQ */ + ((void*)ti_sysbios_knl_Task_Module_State_0_idleTask__A), /* idleTask */ + ((void*)0), /* constructedTasks */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module__state__V.Object_field_inactiveQ.elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module__state__V.Object_field_inactiveQ.elem)), /* prev */ + }, /* elem */ + }, /* Object_field_inactiveQ */ + { + { + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module__state__V.Object_field_terminatedQ.elem)), /* next */ + ((ti_sysbios_knl_Queue_Elem*)((void*)&ti_sysbios_knl_Task_Module__state__V.Object_field_terminatedQ.elem)), /* prev */ + }, /* elem */ + }, /* Object_field_terminatedQ */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__diagsEnabled__C, ".const:ti_sysbios_knl_Task_Module__diagsEnabled__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__diagsEnabled ti_sysbios_knl_Task_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__diagsIncluded__C, ".const:ti_sysbios_knl_Task_Module__diagsIncluded__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__diagsIncluded ti_sysbios_knl_Task_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__diagsMask__C, ".const:ti_sysbios_knl_Task_Module__diagsMask__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__diagsMask ti_sysbios_knl_Task_Module__diagsMask__C = ((CT__ti_sysbios_knl_Task_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__gateObj__C, ".const:ti_sysbios_knl_Task_Module__gateObj__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__gateObj ti_sysbios_knl_Task_Module__gateObj__C = ((CT__ti_sysbios_knl_Task_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__gatePrms__C, ".const:ti_sysbios_knl_Task_Module__gatePrms__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__gatePrms ti_sysbios_knl_Task_Module__gatePrms__C = ((CT__ti_sysbios_knl_Task_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__id__C, ".const:ti_sysbios_knl_Task_Module__id__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__id ti_sysbios_knl_Task_Module__id__C = (xdc_Bits16)0x801e; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerDefined__C, ".const:ti_sysbios_knl_Task_Module__loggerDefined__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerDefined ti_sysbios_knl_Task_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerObj__C, ".const:ti_sysbios_knl_Task_Module__loggerObj__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerObj ti_sysbios_knl_Task_Module__loggerObj__C = ((CT__ti_sysbios_knl_Task_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerFxn0__C, ".const:ti_sysbios_knl_Task_Module__loggerFxn0__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerFxn0 ti_sysbios_knl_Task_Module__loggerFxn0__C = ((CT__ti_sysbios_knl_Task_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerFxn1__C, ".const:ti_sysbios_knl_Task_Module__loggerFxn1__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerFxn1 ti_sysbios_knl_Task_Module__loggerFxn1__C = ((CT__ti_sysbios_knl_Task_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerFxn2__C, ".const:ti_sysbios_knl_Task_Module__loggerFxn2__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerFxn2 ti_sysbios_knl_Task_Module__loggerFxn2__C = ((CT__ti_sysbios_knl_Task_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerFxn4__C, ".const:ti_sysbios_knl_Task_Module__loggerFxn4__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerFxn4 ti_sysbios_knl_Task_Module__loggerFxn4__C = ((CT__ti_sysbios_knl_Task_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__loggerFxn8__C, ".const:ti_sysbios_knl_Task_Module__loggerFxn8__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__loggerFxn8 ti_sysbios_knl_Task_Module__loggerFxn8__C = ((CT__ti_sysbios_knl_Task_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Module__startupDoneFxn__C, ".const:ti_sysbios_knl_Task_Module__startupDoneFxn__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Module__startupDoneFxn ti_sysbios_knl_Task_Module__startupDoneFxn__C = ((CT__ti_sysbios_knl_Task_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Object__count__C, ".const:ti_sysbios_knl_Task_Object__count__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Object__count ti_sysbios_knl_Task_Object__count__C = 2; + +/* Object__heap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Object__heap__C, ".const:ti_sysbios_knl_Task_Object__heap__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Object__heap ti_sysbios_knl_Task_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Object__sizeof__C, ".const:ti_sysbios_knl_Task_Object__sizeof__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Object__sizeof ti_sysbios_knl_Task_Object__sizeof__C = sizeof(ti_sysbios_knl_Task_Object__); + +/* Object__table__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_Object__table__C, ".const:ti_sysbios_knl_Task_Object__table__C"); +__FAR__ const CT__ti_sysbios_knl_Task_Object__table ti_sysbios_knl_Task_Object__table__C = ti_sysbios_knl_Task_Object__table__V; + +/* LM_switch__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_switch__C, ".const:ti_sysbios_knl_Task_LM_switch__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_switch ti_sysbios_knl_Task_LM_switch__C = (((xdc_runtime_Log_Event)5249) << 16 | 768); + +/* LM_sleep__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_sleep__C, ".const:ti_sysbios_knl_Task_LM_sleep__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_sleep ti_sysbios_knl_Task_LM_sleep__C = (((xdc_runtime_Log_Event)5317) << 16 | 768); + +/* LD_ready__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LD_ready__C, ".const:ti_sysbios_knl_Task_LD_ready__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LD_ready ti_sysbios_knl_Task_LD_ready__C = (((xdc_runtime_Log_Event)5362) << 16 | 512); + +/* LD_block__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LD_block__C, ".const:ti_sysbios_knl_Task_LD_block__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LD_block ti_sysbios_knl_Task_LD_block__C = (((xdc_runtime_Log_Event)5403) << 16 | 512); + +/* LM_yield__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_yield__C, ".const:ti_sysbios_knl_Task_LM_yield__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_yield ti_sysbios_knl_Task_LM_yield__C = (((xdc_runtime_Log_Event)5435) << 16 | 768); + +/* LM_setPri__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_setPri__C, ".const:ti_sysbios_knl_Task_LM_setPri__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_setPri ti_sysbios_knl_Task_LM_setPri__C = (((xdc_runtime_Log_Event)5483) << 16 | 768); + +/* LD_exit__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LD_exit__C, ".const:ti_sysbios_knl_Task_LD_exit__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LD_exit ti_sysbios_knl_Task_LD_exit__C = (((xdc_runtime_Log_Event)5539) << 16 | 512); + +/* LM_setAffinity__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_setAffinity__C, ".const:ti_sysbios_knl_Task_LM_setAffinity__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_setAffinity ti_sysbios_knl_Task_LM_setAffinity__C = (((xdc_runtime_Log_Event)5570) << 16 | 768); + +/* LM_schedule__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_schedule__C, ".const:ti_sysbios_knl_Task_LM_schedule__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_schedule ti_sysbios_knl_Task_LM_schedule__C = (((xdc_runtime_Log_Event)5653) << 16 | 1024); + +/* LM_noWork__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_LM_noWork__C, ".const:ti_sysbios_knl_Task_LM_noWork__C"); +__FAR__ const CT__ti_sysbios_knl_Task_LM_noWork ti_sysbios_knl_Task_LM_noWork__C = (((xdc_runtime_Log_Event)5739) << 16 | 1024); + +/* E_stackOverflow__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_E_stackOverflow__C, ".const:ti_sysbios_knl_Task_E_stackOverflow__C"); +__FAR__ const CT__ti_sysbios_knl_Task_E_stackOverflow ti_sysbios_knl_Task_E_stackOverflow__C = (((xdc_runtime_Error_Id)3874) << 16 | 0); + +/* E_spOutOfBounds__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_E_spOutOfBounds__C, ".const:ti_sysbios_knl_Task_E_spOutOfBounds__C"); +__FAR__ const CT__ti_sysbios_knl_Task_E_spOutOfBounds ti_sysbios_knl_Task_E_spOutOfBounds__C = (((xdc_runtime_Error_Id)3917) << 16 | 0); + +/* E_deleteNotAllowed__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_E_deleteNotAllowed__C, ".const:ti_sysbios_knl_Task_E_deleteNotAllowed__C"); +__FAR__ const CT__ti_sysbios_knl_Task_E_deleteNotAllowed ti_sysbios_knl_Task_E_deleteNotAllowed__C = (((xdc_runtime_Error_Id)3968) << 16 | 0); + +/* A_badThreadType__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_badThreadType__C, ".const:ti_sysbios_knl_Task_A_badThreadType__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_badThreadType ti_sysbios_knl_Task_A_badThreadType__C = (((xdc_runtime_Assert_Id)1577) << 16 | 16); + +/* A_badTaskState__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_badTaskState__C, ".const:ti_sysbios_knl_Task_A_badTaskState__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_badTaskState ti_sysbios_knl_Task_A_badTaskState__C = (((xdc_runtime_Assert_Id)1646) << 16 | 16); + +/* A_noPendElem__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_noPendElem__C, ".const:ti_sysbios_knl_Task_A_noPendElem__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_noPendElem ti_sysbios_knl_Task_A_noPendElem__C = (((xdc_runtime_Assert_Id)1700) << 16 | 16); + +/* A_taskDisabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_taskDisabled__C, ".const:ti_sysbios_knl_Task_A_taskDisabled__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_taskDisabled ti_sysbios_knl_Task_A_taskDisabled__C = (((xdc_runtime_Assert_Id)1754) << 16 | 16); + +/* A_badPriority__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_badPriority__C, ".const:ti_sysbios_knl_Task_A_badPriority__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_badPriority ti_sysbios_knl_Task_A_badPriority__C = (((xdc_runtime_Assert_Id)1817) << 16 | 16); + +/* A_badTimeout__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_badTimeout__C, ".const:ti_sysbios_knl_Task_A_badTimeout__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_badTimeout ti_sysbios_knl_Task_A_badTimeout__C = (((xdc_runtime_Assert_Id)1867) << 16 | 16); + +/* A_badAffinity__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_badAffinity__C, ".const:ti_sysbios_knl_Task_A_badAffinity__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_badAffinity ti_sysbios_knl_Task_A_badAffinity__C = (((xdc_runtime_Assert_Id)1902) << 16 | 16); + +/* A_sleepTaskDisabled__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_sleepTaskDisabled__C, ".const:ti_sysbios_knl_Task_A_sleepTaskDisabled__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_sleepTaskDisabled ti_sysbios_knl_Task_A_sleepTaskDisabled__C = (((xdc_runtime_Assert_Id)1935) << 16 | 16); + +/* A_invalidCoreId__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_A_invalidCoreId__C, ".const:ti_sysbios_knl_Task_A_invalidCoreId__C"); +__FAR__ const CT__ti_sysbios_knl_Task_A_invalidCoreId ti_sysbios_knl_Task_A_invalidCoreId__C = (((xdc_runtime_Assert_Id)2019) << 16 | 16); + +/* numPriorities__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_numPriorities__C, ".const:ti_sysbios_knl_Task_numPriorities__C"); +__FAR__ const CT__ti_sysbios_knl_Task_numPriorities ti_sysbios_knl_Task_numPriorities__C = (xdc_UInt)0x10; + +/* defaultStackSize__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_defaultStackSize__C, ".const:ti_sysbios_knl_Task_defaultStackSize__C"); +__FAR__ const CT__ti_sysbios_knl_Task_defaultStackSize ti_sysbios_knl_Task_defaultStackSize__C = (xdc_SizeT)0x200; + +/* defaultStackHeap__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_defaultStackHeap__C, ".const:ti_sysbios_knl_Task_defaultStackHeap__C"); +__FAR__ const CT__ti_sysbios_knl_Task_defaultStackHeap ti_sysbios_knl_Task_defaultStackHeap__C = 0; + +/* allBlockedFunc__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_allBlockedFunc__C, ".const:ti_sysbios_knl_Task_allBlockedFunc__C"); +__FAR__ const CT__ti_sysbios_knl_Task_allBlockedFunc ti_sysbios_knl_Task_allBlockedFunc__C = ((CT__ti_sysbios_knl_Task_allBlockedFunc)0); + +/* initStackFlag__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_initStackFlag__C, ".const:ti_sysbios_knl_Task_initStackFlag__C"); +__FAR__ const CT__ti_sysbios_knl_Task_initStackFlag ti_sysbios_knl_Task_initStackFlag__C = 1; + +/* checkStackFlag__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_checkStackFlag__C, ".const:ti_sysbios_knl_Task_checkStackFlag__C"); +__FAR__ const CT__ti_sysbios_knl_Task_checkStackFlag ti_sysbios_knl_Task_checkStackFlag__C = 1; + +/* deleteTerminatedTasks__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_deleteTerminatedTasks__C, ".const:ti_sysbios_knl_Task_deleteTerminatedTasks__C"); +__FAR__ const CT__ti_sysbios_knl_Task_deleteTerminatedTasks ti_sysbios_knl_Task_deleteTerminatedTasks__C = 0; + +/* hooks__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_hooks__C, ".const:ti_sysbios_knl_Task_hooks__C"); +__FAR__ const CT__ti_sysbios_knl_Task_hooks ti_sysbios_knl_Task_hooks__C = {0, 0}; + +/* numConstructedTasks__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_numConstructedTasks__C, ".const:ti_sysbios_knl_Task_numConstructedTasks__C"); +__FAR__ const CT__ti_sysbios_knl_Task_numConstructedTasks ti_sysbios_knl_Task_numConstructedTasks__C = (xdc_UInt)0x0; + +/* startupHookFunc__C */ +#pragma DATA_SECTION(ti_sysbios_knl_Task_startupHookFunc__C, ".const:ti_sysbios_knl_Task_startupHookFunc__C"); +__FAR__ const CT__ti_sysbios_knl_Task_startupHookFunc ti_sysbios_knl_Task_startupHookFunc__C = ((CT__ti_sysbios_knl_Task_startupHookFunc)0); + + +/* + * ======== ti.sysbios.knl.Task_SupportProxy INITIALIZERS ======== + */ + + +/* + * ======== xdc.runtime.Assert INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__diagsEnabled__C, ".const:xdc_runtime_Assert_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__diagsEnabled xdc_runtime_Assert_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__diagsIncluded__C, ".const:xdc_runtime_Assert_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__diagsIncluded xdc_runtime_Assert_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__diagsMask__C, ".const:xdc_runtime_Assert_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__diagsMask xdc_runtime_Assert_Module__diagsMask__C = ((CT__xdc_runtime_Assert_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__gateObj__C, ".const:xdc_runtime_Assert_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__gateObj xdc_runtime_Assert_Module__gateObj__C = ((CT__xdc_runtime_Assert_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__gatePrms__C, ".const:xdc_runtime_Assert_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__gatePrms xdc_runtime_Assert_Module__gatePrms__C = ((CT__xdc_runtime_Assert_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__id__C, ".const:xdc_runtime_Assert_Module__id__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__id xdc_runtime_Assert_Module__id__C = (xdc_Bits16)0x8002; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerDefined__C, ".const:xdc_runtime_Assert_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerDefined xdc_runtime_Assert_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerObj__C, ".const:xdc_runtime_Assert_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerObj xdc_runtime_Assert_Module__loggerObj__C = ((CT__xdc_runtime_Assert_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerFxn0__C, ".const:xdc_runtime_Assert_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerFxn0 xdc_runtime_Assert_Module__loggerFxn0__C = ((CT__xdc_runtime_Assert_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerFxn1__C, ".const:xdc_runtime_Assert_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerFxn1 xdc_runtime_Assert_Module__loggerFxn1__C = ((CT__xdc_runtime_Assert_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerFxn2__C, ".const:xdc_runtime_Assert_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerFxn2 xdc_runtime_Assert_Module__loggerFxn2__C = ((CT__xdc_runtime_Assert_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerFxn4__C, ".const:xdc_runtime_Assert_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerFxn4 xdc_runtime_Assert_Module__loggerFxn4__C = ((CT__xdc_runtime_Assert_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__loggerFxn8__C, ".const:xdc_runtime_Assert_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__loggerFxn8 xdc_runtime_Assert_Module__loggerFxn8__C = ((CT__xdc_runtime_Assert_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Module__startupDoneFxn__C, ".const:xdc_runtime_Assert_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Assert_Module__startupDoneFxn xdc_runtime_Assert_Module__startupDoneFxn__C = ((CT__xdc_runtime_Assert_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Object__count__C, ".const:xdc_runtime_Assert_Object__count__C"); +__FAR__ const CT__xdc_runtime_Assert_Object__count xdc_runtime_Assert_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Object__heap__C, ".const:xdc_runtime_Assert_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Assert_Object__heap xdc_runtime_Assert_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Object__sizeof__C, ".const:xdc_runtime_Assert_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Assert_Object__sizeof xdc_runtime_Assert_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_Object__table__C, ".const:xdc_runtime_Assert_Object__table__C"); +__FAR__ const CT__xdc_runtime_Assert_Object__table xdc_runtime_Assert_Object__table__C = 0; + +/* E_assertFailed__C */ +#pragma DATA_SECTION(xdc_runtime_Assert_E_assertFailed__C, ".const:xdc_runtime_Assert_E_assertFailed__C"); +__FAR__ const CT__xdc_runtime_Assert_E_assertFailed xdc_runtime_Assert_E_assertFailed__C = (((xdc_runtime_Error_Id)3634) << 16 | 0); + + +/* + * ======== xdc.runtime.Core INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__diagsEnabled__C, ".const:xdc_runtime_Core_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Core_Module__diagsEnabled xdc_runtime_Core_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__diagsIncluded__C, ".const:xdc_runtime_Core_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Core_Module__diagsIncluded xdc_runtime_Core_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__diagsMask__C, ".const:xdc_runtime_Core_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Core_Module__diagsMask xdc_runtime_Core_Module__diagsMask__C = ((CT__xdc_runtime_Core_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__gateObj__C, ".const:xdc_runtime_Core_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Core_Module__gateObj xdc_runtime_Core_Module__gateObj__C = ((CT__xdc_runtime_Core_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__gatePrms__C, ".const:xdc_runtime_Core_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Core_Module__gatePrms xdc_runtime_Core_Module__gatePrms__C = ((CT__xdc_runtime_Core_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__id__C, ".const:xdc_runtime_Core_Module__id__C"); +__FAR__ const CT__xdc_runtime_Core_Module__id xdc_runtime_Core_Module__id__C = (xdc_Bits16)0x8003; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerDefined__C, ".const:xdc_runtime_Core_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerDefined xdc_runtime_Core_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerObj__C, ".const:xdc_runtime_Core_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerObj xdc_runtime_Core_Module__loggerObj__C = ((CT__xdc_runtime_Core_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerFxn0__C, ".const:xdc_runtime_Core_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerFxn0 xdc_runtime_Core_Module__loggerFxn0__C = ((CT__xdc_runtime_Core_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerFxn1__C, ".const:xdc_runtime_Core_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerFxn1 xdc_runtime_Core_Module__loggerFxn1__C = ((CT__xdc_runtime_Core_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerFxn2__C, ".const:xdc_runtime_Core_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerFxn2 xdc_runtime_Core_Module__loggerFxn2__C = ((CT__xdc_runtime_Core_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerFxn4__C, ".const:xdc_runtime_Core_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerFxn4 xdc_runtime_Core_Module__loggerFxn4__C = ((CT__xdc_runtime_Core_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__loggerFxn8__C, ".const:xdc_runtime_Core_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Core_Module__loggerFxn8 xdc_runtime_Core_Module__loggerFxn8__C = ((CT__xdc_runtime_Core_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Module__startupDoneFxn__C, ".const:xdc_runtime_Core_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Core_Module__startupDoneFxn xdc_runtime_Core_Module__startupDoneFxn__C = ((CT__xdc_runtime_Core_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Object__count__C, ".const:xdc_runtime_Core_Object__count__C"); +__FAR__ const CT__xdc_runtime_Core_Object__count xdc_runtime_Core_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Object__heap__C, ".const:xdc_runtime_Core_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Core_Object__heap xdc_runtime_Core_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Object__sizeof__C, ".const:xdc_runtime_Core_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Core_Object__sizeof xdc_runtime_Core_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Core_Object__table__C, ".const:xdc_runtime_Core_Object__table__C"); +__FAR__ const CT__xdc_runtime_Core_Object__table xdc_runtime_Core_Object__table__C = 0; + +/* A_initializedParams__C */ +#pragma DATA_SECTION(xdc_runtime_Core_A_initializedParams__C, ".const:xdc_runtime_Core_A_initializedParams__C"); +__FAR__ const CT__xdc_runtime_Core_A_initializedParams xdc_runtime_Core_A_initializedParams__C = (((xdc_runtime_Assert_Id)1) << 16 | 16); + + +/* + * ======== xdc.runtime.Defaults INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__diagsEnabled__C, ".const:xdc_runtime_Defaults_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__diagsEnabled xdc_runtime_Defaults_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__diagsIncluded__C, ".const:xdc_runtime_Defaults_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__diagsIncluded xdc_runtime_Defaults_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__diagsMask__C, ".const:xdc_runtime_Defaults_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__diagsMask xdc_runtime_Defaults_Module__diagsMask__C = ((CT__xdc_runtime_Defaults_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__gateObj__C, ".const:xdc_runtime_Defaults_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__gateObj xdc_runtime_Defaults_Module__gateObj__C = ((CT__xdc_runtime_Defaults_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__gatePrms__C, ".const:xdc_runtime_Defaults_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__gatePrms xdc_runtime_Defaults_Module__gatePrms__C = ((CT__xdc_runtime_Defaults_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__id__C, ".const:xdc_runtime_Defaults_Module__id__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__id xdc_runtime_Defaults_Module__id__C = (xdc_Bits16)0x8004; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerDefined__C, ".const:xdc_runtime_Defaults_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerDefined xdc_runtime_Defaults_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerObj__C, ".const:xdc_runtime_Defaults_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerObj xdc_runtime_Defaults_Module__loggerObj__C = ((CT__xdc_runtime_Defaults_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerFxn0__C, ".const:xdc_runtime_Defaults_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerFxn0 xdc_runtime_Defaults_Module__loggerFxn0__C = ((CT__xdc_runtime_Defaults_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerFxn1__C, ".const:xdc_runtime_Defaults_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerFxn1 xdc_runtime_Defaults_Module__loggerFxn1__C = ((CT__xdc_runtime_Defaults_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerFxn2__C, ".const:xdc_runtime_Defaults_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerFxn2 xdc_runtime_Defaults_Module__loggerFxn2__C = ((CT__xdc_runtime_Defaults_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerFxn4__C, ".const:xdc_runtime_Defaults_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerFxn4 xdc_runtime_Defaults_Module__loggerFxn4__C = ((CT__xdc_runtime_Defaults_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__loggerFxn8__C, ".const:xdc_runtime_Defaults_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__loggerFxn8 xdc_runtime_Defaults_Module__loggerFxn8__C = ((CT__xdc_runtime_Defaults_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Module__startupDoneFxn__C, ".const:xdc_runtime_Defaults_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Defaults_Module__startupDoneFxn xdc_runtime_Defaults_Module__startupDoneFxn__C = ((CT__xdc_runtime_Defaults_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Object__count__C, ".const:xdc_runtime_Defaults_Object__count__C"); +__FAR__ const CT__xdc_runtime_Defaults_Object__count xdc_runtime_Defaults_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Object__heap__C, ".const:xdc_runtime_Defaults_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Defaults_Object__heap xdc_runtime_Defaults_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Object__sizeof__C, ".const:xdc_runtime_Defaults_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Defaults_Object__sizeof xdc_runtime_Defaults_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Defaults_Object__table__C, ".const:xdc_runtime_Defaults_Object__table__C"); +__FAR__ const CT__xdc_runtime_Defaults_Object__table xdc_runtime_Defaults_Object__table__C = 0; + + +/* + * ======== xdc.runtime.Diags INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__diagsEnabled__C, ".const:xdc_runtime_Diags_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__diagsEnabled xdc_runtime_Diags_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__diagsIncluded__C, ".const:xdc_runtime_Diags_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__diagsIncluded xdc_runtime_Diags_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__diagsMask__C, ".const:xdc_runtime_Diags_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__diagsMask xdc_runtime_Diags_Module__diagsMask__C = ((CT__xdc_runtime_Diags_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__gateObj__C, ".const:xdc_runtime_Diags_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__gateObj xdc_runtime_Diags_Module__gateObj__C = ((CT__xdc_runtime_Diags_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__gatePrms__C, ".const:xdc_runtime_Diags_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__gatePrms xdc_runtime_Diags_Module__gatePrms__C = ((CT__xdc_runtime_Diags_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__id__C, ".const:xdc_runtime_Diags_Module__id__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__id xdc_runtime_Diags_Module__id__C = (xdc_Bits16)0x8005; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerDefined__C, ".const:xdc_runtime_Diags_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerDefined xdc_runtime_Diags_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerObj__C, ".const:xdc_runtime_Diags_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerObj xdc_runtime_Diags_Module__loggerObj__C = ((CT__xdc_runtime_Diags_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerFxn0__C, ".const:xdc_runtime_Diags_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerFxn0 xdc_runtime_Diags_Module__loggerFxn0__C = ((CT__xdc_runtime_Diags_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerFxn1__C, ".const:xdc_runtime_Diags_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerFxn1 xdc_runtime_Diags_Module__loggerFxn1__C = ((CT__xdc_runtime_Diags_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerFxn2__C, ".const:xdc_runtime_Diags_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerFxn2 xdc_runtime_Diags_Module__loggerFxn2__C = ((CT__xdc_runtime_Diags_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerFxn4__C, ".const:xdc_runtime_Diags_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerFxn4 xdc_runtime_Diags_Module__loggerFxn4__C = ((CT__xdc_runtime_Diags_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__loggerFxn8__C, ".const:xdc_runtime_Diags_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__loggerFxn8 xdc_runtime_Diags_Module__loggerFxn8__C = ((CT__xdc_runtime_Diags_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Module__startupDoneFxn__C, ".const:xdc_runtime_Diags_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Diags_Module__startupDoneFxn xdc_runtime_Diags_Module__startupDoneFxn__C = ((CT__xdc_runtime_Diags_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Object__count__C, ".const:xdc_runtime_Diags_Object__count__C"); +__FAR__ const CT__xdc_runtime_Diags_Object__count xdc_runtime_Diags_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Object__heap__C, ".const:xdc_runtime_Diags_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Diags_Object__heap xdc_runtime_Diags_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Object__sizeof__C, ".const:xdc_runtime_Diags_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Diags_Object__sizeof xdc_runtime_Diags_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_Object__table__C, ".const:xdc_runtime_Diags_Object__table__C"); +__FAR__ const CT__xdc_runtime_Diags_Object__table xdc_runtime_Diags_Object__table__C = 0; + +/* setMaskEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_setMaskEnabled__C, ".const:xdc_runtime_Diags_setMaskEnabled__C"); +__FAR__ const CT__xdc_runtime_Diags_setMaskEnabled xdc_runtime_Diags_setMaskEnabled__C = 0; + +/* dictBase__C */ +#pragma DATA_SECTION(xdc_runtime_Diags_dictBase__C, ".const:xdc_runtime_Diags_dictBase__C"); +__FAR__ const CT__xdc_runtime_Diags_dictBase xdc_runtime_Diags_dictBase__C = ((CT__xdc_runtime_Diags_dictBase)0); + + +/* + * ======== xdc.runtime.Error INITIALIZERS ======== + */ + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_Error_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_Error_Module_State__ xdc_runtime_Error_Module__state__V __attribute__ ((section(".data_xdc_runtime_Error_Module__state__V"))); +#endif +#endif +xdc_runtime_Error_Module_State__ xdc_runtime_Error_Module__state__V = { + (xdc_UInt16)0x0, /* count */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__diagsEnabled__C, ".const:xdc_runtime_Error_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Error_Module__diagsEnabled xdc_runtime_Error_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__diagsIncluded__C, ".const:xdc_runtime_Error_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Error_Module__diagsIncluded xdc_runtime_Error_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__diagsMask__C, ".const:xdc_runtime_Error_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Error_Module__diagsMask xdc_runtime_Error_Module__diagsMask__C = ((CT__xdc_runtime_Error_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__gateObj__C, ".const:xdc_runtime_Error_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Error_Module__gateObj xdc_runtime_Error_Module__gateObj__C = ((CT__xdc_runtime_Error_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__gatePrms__C, ".const:xdc_runtime_Error_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Error_Module__gatePrms xdc_runtime_Error_Module__gatePrms__C = ((CT__xdc_runtime_Error_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__id__C, ".const:xdc_runtime_Error_Module__id__C"); +__FAR__ const CT__xdc_runtime_Error_Module__id xdc_runtime_Error_Module__id__C = (xdc_Bits16)0x8006; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerDefined__C, ".const:xdc_runtime_Error_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerDefined xdc_runtime_Error_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerObj__C, ".const:xdc_runtime_Error_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerObj xdc_runtime_Error_Module__loggerObj__C = ((CT__xdc_runtime_Error_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerFxn0__C, ".const:xdc_runtime_Error_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerFxn0 xdc_runtime_Error_Module__loggerFxn0__C = ((CT__xdc_runtime_Error_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerFxn1__C, ".const:xdc_runtime_Error_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerFxn1 xdc_runtime_Error_Module__loggerFxn1__C = ((CT__xdc_runtime_Error_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerFxn2__C, ".const:xdc_runtime_Error_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerFxn2 xdc_runtime_Error_Module__loggerFxn2__C = ((CT__xdc_runtime_Error_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerFxn4__C, ".const:xdc_runtime_Error_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerFxn4 xdc_runtime_Error_Module__loggerFxn4__C = ((CT__xdc_runtime_Error_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__loggerFxn8__C, ".const:xdc_runtime_Error_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Error_Module__loggerFxn8 xdc_runtime_Error_Module__loggerFxn8__C = ((CT__xdc_runtime_Error_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Module__startupDoneFxn__C, ".const:xdc_runtime_Error_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Error_Module__startupDoneFxn xdc_runtime_Error_Module__startupDoneFxn__C = ((CT__xdc_runtime_Error_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Object__count__C, ".const:xdc_runtime_Error_Object__count__C"); +__FAR__ const CT__xdc_runtime_Error_Object__count xdc_runtime_Error_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Object__heap__C, ".const:xdc_runtime_Error_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Error_Object__heap xdc_runtime_Error_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Object__sizeof__C, ".const:xdc_runtime_Error_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Error_Object__sizeof xdc_runtime_Error_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Error_Object__table__C, ".const:xdc_runtime_Error_Object__table__C"); +__FAR__ const CT__xdc_runtime_Error_Object__table xdc_runtime_Error_Object__table__C = 0; + +/* policyFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Error_policyFxn__C, ".const:xdc_runtime_Error_policyFxn__C"); +__FAR__ const CT__xdc_runtime_Error_policyFxn xdc_runtime_Error_policyFxn__C = ((CT__xdc_runtime_Error_policyFxn)((xdc_Fxn)xdc_runtime_Error_policyDefault__E)); + +/* E_generic__C */ +#pragma DATA_SECTION(xdc_runtime_Error_E_generic__C, ".const:xdc_runtime_Error_E_generic__C"); +__FAR__ const CT__xdc_runtime_Error_E_generic xdc_runtime_Error_E_generic__C = (((xdc_runtime_Error_Id)3656) << 16 | 0); + +/* E_memory__C */ +#pragma DATA_SECTION(xdc_runtime_Error_E_memory__C, ".const:xdc_runtime_Error_E_memory__C"); +__FAR__ const CT__xdc_runtime_Error_E_memory xdc_runtime_Error_E_memory__C = (((xdc_runtime_Error_Id)3660) << 16 | 0); + +/* E_msgCode__C */ +#pragma DATA_SECTION(xdc_runtime_Error_E_msgCode__C, ".const:xdc_runtime_Error_E_msgCode__C"); +__FAR__ const CT__xdc_runtime_Error_E_msgCode xdc_runtime_Error_E_msgCode__C = (((xdc_runtime_Error_Id)3694) << 16 | 0); + +/* policy__C */ +#pragma DATA_SECTION(xdc_runtime_Error_policy__C, ".const:xdc_runtime_Error_policy__C"); +__FAR__ const CT__xdc_runtime_Error_policy xdc_runtime_Error_policy__C = xdc_runtime_Error_UNWIND; + +/* raiseHook__C */ +#pragma DATA_SECTION(xdc_runtime_Error_raiseHook__C, ".const:xdc_runtime_Error_raiseHook__C"); +__FAR__ const CT__xdc_runtime_Error_raiseHook xdc_runtime_Error_raiseHook__C = ((CT__xdc_runtime_Error_raiseHook)((xdc_Fxn)ti_sysbios_BIOS_errorRaiseHook__I)); + +/* maxDepth__C */ +#pragma DATA_SECTION(xdc_runtime_Error_maxDepth__C, ".const:xdc_runtime_Error_maxDepth__C"); +__FAR__ const CT__xdc_runtime_Error_maxDepth xdc_runtime_Error_maxDepth__C = (xdc_UInt16)0x2; + + +/* + * ======== xdc.runtime.Gate INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__diagsEnabled__C, ".const:xdc_runtime_Gate_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__diagsEnabled xdc_runtime_Gate_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__diagsIncluded__C, ".const:xdc_runtime_Gate_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__diagsIncluded xdc_runtime_Gate_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__diagsMask__C, ".const:xdc_runtime_Gate_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__diagsMask xdc_runtime_Gate_Module__diagsMask__C = ((CT__xdc_runtime_Gate_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__gateObj__C, ".const:xdc_runtime_Gate_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__gateObj xdc_runtime_Gate_Module__gateObj__C = ((CT__xdc_runtime_Gate_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__gatePrms__C, ".const:xdc_runtime_Gate_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__gatePrms xdc_runtime_Gate_Module__gatePrms__C = ((CT__xdc_runtime_Gate_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__id__C, ".const:xdc_runtime_Gate_Module__id__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__id xdc_runtime_Gate_Module__id__C = (xdc_Bits16)0x8007; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerDefined__C, ".const:xdc_runtime_Gate_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerDefined xdc_runtime_Gate_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerObj__C, ".const:xdc_runtime_Gate_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerObj xdc_runtime_Gate_Module__loggerObj__C = ((CT__xdc_runtime_Gate_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerFxn0__C, ".const:xdc_runtime_Gate_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerFxn0 xdc_runtime_Gate_Module__loggerFxn0__C = ((CT__xdc_runtime_Gate_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerFxn1__C, ".const:xdc_runtime_Gate_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerFxn1 xdc_runtime_Gate_Module__loggerFxn1__C = ((CT__xdc_runtime_Gate_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerFxn2__C, ".const:xdc_runtime_Gate_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerFxn2 xdc_runtime_Gate_Module__loggerFxn2__C = ((CT__xdc_runtime_Gate_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerFxn4__C, ".const:xdc_runtime_Gate_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerFxn4 xdc_runtime_Gate_Module__loggerFxn4__C = ((CT__xdc_runtime_Gate_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__loggerFxn8__C, ".const:xdc_runtime_Gate_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__loggerFxn8 xdc_runtime_Gate_Module__loggerFxn8__C = ((CT__xdc_runtime_Gate_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Module__startupDoneFxn__C, ".const:xdc_runtime_Gate_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Gate_Module__startupDoneFxn xdc_runtime_Gate_Module__startupDoneFxn__C = ((CT__xdc_runtime_Gate_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Object__count__C, ".const:xdc_runtime_Gate_Object__count__C"); +__FAR__ const CT__xdc_runtime_Gate_Object__count xdc_runtime_Gate_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Object__heap__C, ".const:xdc_runtime_Gate_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Gate_Object__heap xdc_runtime_Gate_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Object__sizeof__C, ".const:xdc_runtime_Gate_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Gate_Object__sizeof xdc_runtime_Gate_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Gate_Object__table__C, ".const:xdc_runtime_Gate_Object__table__C"); +__FAR__ const CT__xdc_runtime_Gate_Object__table xdc_runtime_Gate_Object__table__C = 0; + + +/* + * ======== xdc.runtime.Log INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__diagsEnabled__C, ".const:xdc_runtime_Log_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Log_Module__diagsEnabled xdc_runtime_Log_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__diagsIncluded__C, ".const:xdc_runtime_Log_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Log_Module__diagsIncluded xdc_runtime_Log_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__diagsMask__C, ".const:xdc_runtime_Log_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Log_Module__diagsMask xdc_runtime_Log_Module__diagsMask__C = ((CT__xdc_runtime_Log_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__gateObj__C, ".const:xdc_runtime_Log_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Log_Module__gateObj xdc_runtime_Log_Module__gateObj__C = ((CT__xdc_runtime_Log_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__gatePrms__C, ".const:xdc_runtime_Log_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Log_Module__gatePrms xdc_runtime_Log_Module__gatePrms__C = ((CT__xdc_runtime_Log_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__id__C, ".const:xdc_runtime_Log_Module__id__C"); +__FAR__ const CT__xdc_runtime_Log_Module__id xdc_runtime_Log_Module__id__C = (xdc_Bits16)0x8008; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerDefined__C, ".const:xdc_runtime_Log_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerDefined xdc_runtime_Log_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerObj__C, ".const:xdc_runtime_Log_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerObj xdc_runtime_Log_Module__loggerObj__C = ((CT__xdc_runtime_Log_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerFxn0__C, ".const:xdc_runtime_Log_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerFxn0 xdc_runtime_Log_Module__loggerFxn0__C = ((CT__xdc_runtime_Log_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerFxn1__C, ".const:xdc_runtime_Log_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerFxn1 xdc_runtime_Log_Module__loggerFxn1__C = ((CT__xdc_runtime_Log_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerFxn2__C, ".const:xdc_runtime_Log_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerFxn2 xdc_runtime_Log_Module__loggerFxn2__C = ((CT__xdc_runtime_Log_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerFxn4__C, ".const:xdc_runtime_Log_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerFxn4 xdc_runtime_Log_Module__loggerFxn4__C = ((CT__xdc_runtime_Log_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__loggerFxn8__C, ".const:xdc_runtime_Log_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Log_Module__loggerFxn8 xdc_runtime_Log_Module__loggerFxn8__C = ((CT__xdc_runtime_Log_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Module__startupDoneFxn__C, ".const:xdc_runtime_Log_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Log_Module__startupDoneFxn xdc_runtime_Log_Module__startupDoneFxn__C = ((CT__xdc_runtime_Log_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Object__count__C, ".const:xdc_runtime_Log_Object__count__C"); +__FAR__ const CT__xdc_runtime_Log_Object__count xdc_runtime_Log_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Object__heap__C, ".const:xdc_runtime_Log_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Log_Object__heap xdc_runtime_Log_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Object__sizeof__C, ".const:xdc_runtime_Log_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Log_Object__sizeof xdc_runtime_Log_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Log_Object__table__C, ".const:xdc_runtime_Log_Object__table__C"); +__FAR__ const CT__xdc_runtime_Log_Object__table xdc_runtime_Log_Object__table__C = 0; + +/* L_construct__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_construct__C, ".const:xdc_runtime_Log_L_construct__C"); +__FAR__ const CT__xdc_runtime_Log_L_construct xdc_runtime_Log_L_construct__C = (((xdc_runtime_Log_Event)4823) << 16 | 4); + +/* L_create__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_create__C, ".const:xdc_runtime_Log_L_create__C"); +__FAR__ const CT__xdc_runtime_Log_L_create xdc_runtime_Log_L_create__C = (((xdc_runtime_Log_Event)4847) << 16 | 4); + +/* L_destruct__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_destruct__C, ".const:xdc_runtime_Log_L_destruct__C"); +__FAR__ const CT__xdc_runtime_Log_L_destruct xdc_runtime_Log_L_destruct__C = (((xdc_runtime_Log_Event)4868) << 16 | 4); + +/* L_delete__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_delete__C, ".const:xdc_runtime_Log_L_delete__C"); +__FAR__ const CT__xdc_runtime_Log_L_delete xdc_runtime_Log_L_delete__C = (((xdc_runtime_Log_Event)4887) << 16 | 4); + +/* L_error__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_error__C, ".const:xdc_runtime_Log_L_error__C"); +__FAR__ const CT__xdc_runtime_Log_L_error xdc_runtime_Log_L_error__C = (((xdc_runtime_Log_Event)4904) << 16 | 192); + +/* L_warning__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_warning__C, ".const:xdc_runtime_Log_L_warning__C"); +__FAR__ const CT__xdc_runtime_Log_L_warning xdc_runtime_Log_L_warning__C = (((xdc_runtime_Log_Event)4918) << 16 | 224); + +/* L_info__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_info__C, ".const:xdc_runtime_Log_L_info__C"); +__FAR__ const CT__xdc_runtime_Log_L_info xdc_runtime_Log_L_info__C = (((xdc_runtime_Log_Event)4934) << 16 | 16384); + +/* L_start__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_start__C, ".const:xdc_runtime_Log_L_start__C"); +__FAR__ const CT__xdc_runtime_Log_L_start xdc_runtime_Log_L_start__C = (((xdc_runtime_Log_Event)4941) << 16 | 32768); + +/* L_stop__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_stop__C, ".const:xdc_runtime_Log_L_stop__C"); +__FAR__ const CT__xdc_runtime_Log_L_stop xdc_runtime_Log_L_stop__C = (((xdc_runtime_Log_Event)4952) << 16 | 32768); + +/* L_startInstance__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_startInstance__C, ".const:xdc_runtime_Log_L_startInstance__C"); +__FAR__ const CT__xdc_runtime_Log_L_startInstance xdc_runtime_Log_L_startInstance__C = (((xdc_runtime_Log_Event)4962) << 16 | 32768); + +/* L_stopInstance__C */ +#pragma DATA_SECTION(xdc_runtime_Log_L_stopInstance__C, ".const:xdc_runtime_Log_L_stopInstance__C"); +__FAR__ const CT__xdc_runtime_Log_L_stopInstance xdc_runtime_Log_L_stopInstance__C = (((xdc_runtime_Log_Event)4981) << 16 | 32768); + + +/* + * ======== xdc.runtime.Main INITIALIZERS ======== + */ + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__diagsEnabled__C, ".const:xdc_runtime_Main_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Main_Module__diagsEnabled xdc_runtime_Main_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__diagsIncluded__C, ".const:xdc_runtime_Main_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Main_Module__diagsIncluded xdc_runtime_Main_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__diagsMask__C, ".const:xdc_runtime_Main_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Main_Module__diagsMask xdc_runtime_Main_Module__diagsMask__C = ((CT__xdc_runtime_Main_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__gateObj__C, ".const:xdc_runtime_Main_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Main_Module__gateObj xdc_runtime_Main_Module__gateObj__C = ((CT__xdc_runtime_Main_Module__gateObj)((void*)(xdc_runtime_IGateProvider_Handle)&ti_sysbios_gates_GateHwi_Object__table__V[0])); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__gatePrms__C, ".const:xdc_runtime_Main_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Main_Module__gatePrms xdc_runtime_Main_Module__gatePrms__C = ((CT__xdc_runtime_Main_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__id__C, ".const:xdc_runtime_Main_Module__id__C"); +__FAR__ const CT__xdc_runtime_Main_Module__id xdc_runtime_Main_Module__id__C = (xdc_Bits16)0x8009; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerDefined__C, ".const:xdc_runtime_Main_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerDefined xdc_runtime_Main_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerObj__C, ".const:xdc_runtime_Main_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerObj xdc_runtime_Main_Module__loggerObj__C = ((CT__xdc_runtime_Main_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerFxn0__C, ".const:xdc_runtime_Main_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerFxn0 xdc_runtime_Main_Module__loggerFxn0__C = ((CT__xdc_runtime_Main_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerFxn1__C, ".const:xdc_runtime_Main_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerFxn1 xdc_runtime_Main_Module__loggerFxn1__C = ((CT__xdc_runtime_Main_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerFxn2__C, ".const:xdc_runtime_Main_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerFxn2 xdc_runtime_Main_Module__loggerFxn2__C = ((CT__xdc_runtime_Main_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerFxn4__C, ".const:xdc_runtime_Main_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerFxn4 xdc_runtime_Main_Module__loggerFxn4__C = ((CT__xdc_runtime_Main_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__loggerFxn8__C, ".const:xdc_runtime_Main_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Main_Module__loggerFxn8 xdc_runtime_Main_Module__loggerFxn8__C = ((CT__xdc_runtime_Main_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Module__startupDoneFxn__C, ".const:xdc_runtime_Main_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Main_Module__startupDoneFxn xdc_runtime_Main_Module__startupDoneFxn__C = ((CT__xdc_runtime_Main_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Object__count__C, ".const:xdc_runtime_Main_Object__count__C"); +__FAR__ const CT__xdc_runtime_Main_Object__count xdc_runtime_Main_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Object__heap__C, ".const:xdc_runtime_Main_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Main_Object__heap xdc_runtime_Main_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Object__sizeof__C, ".const:xdc_runtime_Main_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Main_Object__sizeof xdc_runtime_Main_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Main_Object__table__C, ".const:xdc_runtime_Main_Object__table__C"); +__FAR__ const CT__xdc_runtime_Main_Object__table xdc_runtime_Main_Object__table__C = 0; + + +/* + * ======== xdc.runtime.Main_Module_GateProxy INITIALIZERS ======== + */ + + +/* + * ======== xdc.runtime.Memory INITIALIZERS ======== + */ + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_Memory_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_Memory_Module_State__ xdc_runtime_Memory_Module__state__V __attribute__ ((section(".data_xdc_runtime_Memory_Module__state__V"))); +#endif +#endif +xdc_runtime_Memory_Module_State__ xdc_runtime_Memory_Module__state__V = { + (xdc_SizeT)0x8, /* maxDefaultTypeAlign */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__diagsEnabled__C, ".const:xdc_runtime_Memory_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__diagsEnabled xdc_runtime_Memory_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__diagsIncluded__C, ".const:xdc_runtime_Memory_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__diagsIncluded xdc_runtime_Memory_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__diagsMask__C, ".const:xdc_runtime_Memory_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__diagsMask xdc_runtime_Memory_Module__diagsMask__C = ((CT__xdc_runtime_Memory_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__gateObj__C, ".const:xdc_runtime_Memory_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__gateObj xdc_runtime_Memory_Module__gateObj__C = ((CT__xdc_runtime_Memory_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__gatePrms__C, ".const:xdc_runtime_Memory_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__gatePrms xdc_runtime_Memory_Module__gatePrms__C = ((CT__xdc_runtime_Memory_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__id__C, ".const:xdc_runtime_Memory_Module__id__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__id xdc_runtime_Memory_Module__id__C = (xdc_Bits16)0x800a; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerDefined__C, ".const:xdc_runtime_Memory_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerDefined xdc_runtime_Memory_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerObj__C, ".const:xdc_runtime_Memory_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerObj xdc_runtime_Memory_Module__loggerObj__C = ((CT__xdc_runtime_Memory_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerFxn0__C, ".const:xdc_runtime_Memory_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerFxn0 xdc_runtime_Memory_Module__loggerFxn0__C = ((CT__xdc_runtime_Memory_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerFxn1__C, ".const:xdc_runtime_Memory_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerFxn1 xdc_runtime_Memory_Module__loggerFxn1__C = ((CT__xdc_runtime_Memory_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerFxn2__C, ".const:xdc_runtime_Memory_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerFxn2 xdc_runtime_Memory_Module__loggerFxn2__C = ((CT__xdc_runtime_Memory_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerFxn4__C, ".const:xdc_runtime_Memory_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerFxn4 xdc_runtime_Memory_Module__loggerFxn4__C = ((CT__xdc_runtime_Memory_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__loggerFxn8__C, ".const:xdc_runtime_Memory_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__loggerFxn8 xdc_runtime_Memory_Module__loggerFxn8__C = ((CT__xdc_runtime_Memory_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Module__startupDoneFxn__C, ".const:xdc_runtime_Memory_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Memory_Module__startupDoneFxn xdc_runtime_Memory_Module__startupDoneFxn__C = ((CT__xdc_runtime_Memory_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Object__count__C, ".const:xdc_runtime_Memory_Object__count__C"); +__FAR__ const CT__xdc_runtime_Memory_Object__count xdc_runtime_Memory_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Object__heap__C, ".const:xdc_runtime_Memory_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Memory_Object__heap xdc_runtime_Memory_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Object__sizeof__C, ".const:xdc_runtime_Memory_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Memory_Object__sizeof xdc_runtime_Memory_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_Object__table__C, ".const:xdc_runtime_Memory_Object__table__C"); +__FAR__ const CT__xdc_runtime_Memory_Object__table xdc_runtime_Memory_Object__table__C = 0; + +/* defaultHeapInstance__C */ +#pragma DATA_SECTION(xdc_runtime_Memory_defaultHeapInstance__C, ".const:xdc_runtime_Memory_defaultHeapInstance__C"); +__FAR__ const CT__xdc_runtime_Memory_defaultHeapInstance xdc_runtime_Memory_defaultHeapInstance__C = (xdc_runtime_IHeap_Handle)&ti_sysbios_heaps_HeapMem_Object__table__V[0]; + + +/* + * ======== xdc.runtime.Memory_HeapProxy INITIALIZERS ======== + */ + + +/* + * ======== xdc.runtime.Registry INITIALIZERS ======== + */ + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_Registry_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_Registry_Module_State__ xdc_runtime_Registry_Module__state__V __attribute__ ((section(".data_xdc_runtime_Registry_Module__state__V"))); +#endif +#endif +xdc_runtime_Registry_Module_State__ xdc_runtime_Registry_Module__state__V = { + ((xdc_runtime_Types_RegDesc*)0), /* listHead */ + (xdc_Bits16)0x7fff, /* curId */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__diagsEnabled__C, ".const:xdc_runtime_Registry_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__diagsEnabled xdc_runtime_Registry_Module__diagsEnabled__C = (xdc_Bits32)0x90; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__diagsIncluded__C, ".const:xdc_runtime_Registry_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__diagsIncluded xdc_runtime_Registry_Module__diagsIncluded__C = (xdc_Bits32)0x90; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__diagsMask__C, ".const:xdc_runtime_Registry_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__diagsMask xdc_runtime_Registry_Module__diagsMask__C = ((CT__xdc_runtime_Registry_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__gateObj__C, ".const:xdc_runtime_Registry_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__gateObj xdc_runtime_Registry_Module__gateObj__C = ((CT__xdc_runtime_Registry_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__gatePrms__C, ".const:xdc_runtime_Registry_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__gatePrms xdc_runtime_Registry_Module__gatePrms__C = ((CT__xdc_runtime_Registry_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__id__C, ".const:xdc_runtime_Registry_Module__id__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__id xdc_runtime_Registry_Module__id__C = (xdc_Bits16)0x800b; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerDefined__C, ".const:xdc_runtime_Registry_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerDefined xdc_runtime_Registry_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerObj__C, ".const:xdc_runtime_Registry_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerObj xdc_runtime_Registry_Module__loggerObj__C = ((CT__xdc_runtime_Registry_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerFxn0__C, ".const:xdc_runtime_Registry_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerFxn0 xdc_runtime_Registry_Module__loggerFxn0__C = ((CT__xdc_runtime_Registry_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerFxn1__C, ".const:xdc_runtime_Registry_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerFxn1 xdc_runtime_Registry_Module__loggerFxn1__C = ((CT__xdc_runtime_Registry_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerFxn2__C, ".const:xdc_runtime_Registry_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerFxn2 xdc_runtime_Registry_Module__loggerFxn2__C = ((CT__xdc_runtime_Registry_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerFxn4__C, ".const:xdc_runtime_Registry_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerFxn4 xdc_runtime_Registry_Module__loggerFxn4__C = ((CT__xdc_runtime_Registry_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__loggerFxn8__C, ".const:xdc_runtime_Registry_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__loggerFxn8 xdc_runtime_Registry_Module__loggerFxn8__C = ((CT__xdc_runtime_Registry_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Module__startupDoneFxn__C, ".const:xdc_runtime_Registry_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Registry_Module__startupDoneFxn xdc_runtime_Registry_Module__startupDoneFxn__C = ((CT__xdc_runtime_Registry_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Object__count__C, ".const:xdc_runtime_Registry_Object__count__C"); +__FAR__ const CT__xdc_runtime_Registry_Object__count xdc_runtime_Registry_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Object__heap__C, ".const:xdc_runtime_Registry_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Registry_Object__heap xdc_runtime_Registry_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Object__sizeof__C, ".const:xdc_runtime_Registry_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Registry_Object__sizeof xdc_runtime_Registry_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Registry_Object__table__C, ".const:xdc_runtime_Registry_Object__table__C"); +__FAR__ const CT__xdc_runtime_Registry_Object__table xdc_runtime_Registry_Object__table__C = 0; + + +/* + * ======== xdc.runtime.Startup INITIALIZERS ======== + */ + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_Startup_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_Startup_Module_State__ xdc_runtime_Startup_Module__state__V __attribute__ ((section(".data_xdc_runtime_Startup_Module__state__V"))); +#endif +#endif +xdc_runtime_Startup_Module_State__ xdc_runtime_Startup_Module__state__V = { + ((xdc_Int*)0), /* stateTab */ + 0, /* execFlag */ + 0, /* rtsDoneFlag */ +}; + +/* --> xdc_runtime_Startup_firstFxns__A */ +#pragma DATA_SECTION(xdc_runtime_Startup_firstFxns__A, ".const:xdc_runtime_Startup_firstFxns__A"); +const __T1_xdc_runtime_Startup_firstFxns xdc_runtime_Startup_firstFxns__A[5] = { + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_heaps_HeapMem_init__I)), /* [0] */ + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_catalog_arm_cortexm4_tiva_ce_Boot_init__I)), /* [1] */ + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_hal_Hwi_initStack)), /* [2] */ + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_initNVIC__E)), /* [3] */ + ((xdc_Void(*)(xdc_Void))((xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_enableTimers__I)), /* [4] */ +}; + +/* --> xdc_runtime_Startup_sfxnTab__A */ +#pragma DATA_SECTION(xdc_runtime_Startup_sfxnTab__A, ".const:xdc_runtime_Startup_sfxnTab__A"); +const __T1_xdc_runtime_Startup_sfxnTab xdc_runtime_Startup_sfxnTab__A[8] = { + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)xdc_runtime_System_Module_startup__E)), /* [0] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)xdc_runtime_SysMin_Module_startup__E)), /* [1] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)ti_sysbios_knl_Clock_Module_startup__E)), /* [2] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)ti_sysbios_knl_Swi_Module_startup__E)), /* [3] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)ti_sysbios_knl_Task_Module_startup__E)), /* [4] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)ti_sysbios_hal_Hwi_Module_startup__E)), /* [5] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_Module_startup__E)), /* [6] */ + ((xdc_Int(*)(xdc_Int))((xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_Module_startup__E)), /* [7] */ +}; + +/* --> xdc_runtime_Startup_sfxnRts__A */ +#pragma DATA_SECTION(xdc_runtime_Startup_sfxnRts__A, ".const:xdc_runtime_Startup_sfxnRts__A"); +const __T1_xdc_runtime_Startup_sfxnRts xdc_runtime_Startup_sfxnRts__A[8] = { + 1, /* [0] */ + 1, /* [1] */ + 0, /* [2] */ + 0, /* [3] */ + 0, /* [4] */ + 0, /* [5] */ + 0, /* [6] */ + 0, /* [7] */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__diagsEnabled__C, ".const:xdc_runtime_Startup_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__diagsEnabled xdc_runtime_Startup_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__diagsIncluded__C, ".const:xdc_runtime_Startup_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__diagsIncluded xdc_runtime_Startup_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__diagsMask__C, ".const:xdc_runtime_Startup_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__diagsMask xdc_runtime_Startup_Module__diagsMask__C = ((CT__xdc_runtime_Startup_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__gateObj__C, ".const:xdc_runtime_Startup_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__gateObj xdc_runtime_Startup_Module__gateObj__C = ((CT__xdc_runtime_Startup_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__gatePrms__C, ".const:xdc_runtime_Startup_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__gatePrms xdc_runtime_Startup_Module__gatePrms__C = ((CT__xdc_runtime_Startup_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__id__C, ".const:xdc_runtime_Startup_Module__id__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__id xdc_runtime_Startup_Module__id__C = (xdc_Bits16)0x800c; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerDefined__C, ".const:xdc_runtime_Startup_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerDefined xdc_runtime_Startup_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerObj__C, ".const:xdc_runtime_Startup_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerObj xdc_runtime_Startup_Module__loggerObj__C = ((CT__xdc_runtime_Startup_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerFxn0__C, ".const:xdc_runtime_Startup_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerFxn0 xdc_runtime_Startup_Module__loggerFxn0__C = ((CT__xdc_runtime_Startup_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerFxn1__C, ".const:xdc_runtime_Startup_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerFxn1 xdc_runtime_Startup_Module__loggerFxn1__C = ((CT__xdc_runtime_Startup_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerFxn2__C, ".const:xdc_runtime_Startup_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerFxn2 xdc_runtime_Startup_Module__loggerFxn2__C = ((CT__xdc_runtime_Startup_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerFxn4__C, ".const:xdc_runtime_Startup_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerFxn4 xdc_runtime_Startup_Module__loggerFxn4__C = ((CT__xdc_runtime_Startup_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__loggerFxn8__C, ".const:xdc_runtime_Startup_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__loggerFxn8 xdc_runtime_Startup_Module__loggerFxn8__C = ((CT__xdc_runtime_Startup_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Module__startupDoneFxn__C, ".const:xdc_runtime_Startup_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Startup_Module__startupDoneFxn xdc_runtime_Startup_Module__startupDoneFxn__C = ((CT__xdc_runtime_Startup_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Object__count__C, ".const:xdc_runtime_Startup_Object__count__C"); +__FAR__ const CT__xdc_runtime_Startup_Object__count xdc_runtime_Startup_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Object__heap__C, ".const:xdc_runtime_Startup_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Startup_Object__heap xdc_runtime_Startup_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Object__sizeof__C, ".const:xdc_runtime_Startup_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Startup_Object__sizeof xdc_runtime_Startup_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_Object__table__C, ".const:xdc_runtime_Startup_Object__table__C"); +__FAR__ const CT__xdc_runtime_Startup_Object__table xdc_runtime_Startup_Object__table__C = 0; + +/* maxPasses__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_maxPasses__C, ".const:xdc_runtime_Startup_maxPasses__C"); +__FAR__ const CT__xdc_runtime_Startup_maxPasses xdc_runtime_Startup_maxPasses__C = (xdc_Int)0x20; + +/* firstFxns__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_firstFxns__C, ".const:xdc_runtime_Startup_firstFxns__C"); +__FAR__ const CT__xdc_runtime_Startup_firstFxns xdc_runtime_Startup_firstFxns__C = {5, ((__T1_xdc_runtime_Startup_firstFxns*)xdc_runtime_Startup_firstFxns__A)}; + +/* lastFxns__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_lastFxns__C, ".const:xdc_runtime_Startup_lastFxns__C"); +__FAR__ const CT__xdc_runtime_Startup_lastFxns xdc_runtime_Startup_lastFxns__C = {0, 0}; + +/* startModsFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_startModsFxn__C, ".const:xdc_runtime_Startup_startModsFxn__C"); +__FAR__ const CT__xdc_runtime_Startup_startModsFxn xdc_runtime_Startup_startModsFxn__C = ((CT__xdc_runtime_Startup_startModsFxn)((xdc_Fxn)xdc_runtime_Startup_startMods__I)); + +/* execImpl__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_execImpl__C, ".const:xdc_runtime_Startup_execImpl__C"); +__FAR__ const CT__xdc_runtime_Startup_execImpl xdc_runtime_Startup_execImpl__C = ((CT__xdc_runtime_Startup_execImpl)((xdc_Fxn)xdc_runtime_Startup_exec__I)); + +/* sfxnTab__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_sfxnTab__C, ".const:xdc_runtime_Startup_sfxnTab__C"); +__FAR__ const CT__xdc_runtime_Startup_sfxnTab xdc_runtime_Startup_sfxnTab__C = ((CT__xdc_runtime_Startup_sfxnTab)xdc_runtime_Startup_sfxnTab__A); + +/* sfxnRts__C */ +#pragma DATA_SECTION(xdc_runtime_Startup_sfxnRts__C, ".const:xdc_runtime_Startup_sfxnRts__C"); +__FAR__ const CT__xdc_runtime_Startup_sfxnRts xdc_runtime_Startup_sfxnRts__C = ((CT__xdc_runtime_Startup_sfxnRts)xdc_runtime_Startup_sfxnRts__A); + + +/* + * ======== xdc.runtime.SysMin INITIALIZERS ======== + */ + +/* --> xdc_runtime_SysMin_Module_State_0_outbuf__A */ +__T1_xdc_runtime_SysMin_Module_State__outbuf xdc_runtime_SysMin_Module_State_0_outbuf__A[128]; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_SysMin_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_SysMin_Module_State__ xdc_runtime_SysMin_Module__state__V __attribute__ ((section(".data_xdc_runtime_SysMin_Module__state__V"))); +#endif +#endif +xdc_runtime_SysMin_Module_State__ xdc_runtime_SysMin_Module__state__V = { + ((void*)xdc_runtime_SysMin_Module_State_0_outbuf__A), /* outbuf */ + (xdc_UInt)0x0, /* outidx */ + 0, /* wrapped */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__diagsEnabled__C, ".const:xdc_runtime_SysMin_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__diagsEnabled xdc_runtime_SysMin_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__diagsIncluded__C, ".const:xdc_runtime_SysMin_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__diagsIncluded xdc_runtime_SysMin_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__diagsMask__C, ".const:xdc_runtime_SysMin_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__diagsMask xdc_runtime_SysMin_Module__diagsMask__C = ((CT__xdc_runtime_SysMin_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__gateObj__C, ".const:xdc_runtime_SysMin_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__gateObj xdc_runtime_SysMin_Module__gateObj__C = ((CT__xdc_runtime_SysMin_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__gatePrms__C, ".const:xdc_runtime_SysMin_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__gatePrms xdc_runtime_SysMin_Module__gatePrms__C = ((CT__xdc_runtime_SysMin_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__id__C, ".const:xdc_runtime_SysMin_Module__id__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__id xdc_runtime_SysMin_Module__id__C = (xdc_Bits16)0x800e; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerDefined__C, ".const:xdc_runtime_SysMin_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerDefined xdc_runtime_SysMin_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerObj__C, ".const:xdc_runtime_SysMin_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerObj xdc_runtime_SysMin_Module__loggerObj__C = ((CT__xdc_runtime_SysMin_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerFxn0__C, ".const:xdc_runtime_SysMin_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerFxn0 xdc_runtime_SysMin_Module__loggerFxn0__C = ((CT__xdc_runtime_SysMin_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerFxn1__C, ".const:xdc_runtime_SysMin_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerFxn1 xdc_runtime_SysMin_Module__loggerFxn1__C = ((CT__xdc_runtime_SysMin_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerFxn2__C, ".const:xdc_runtime_SysMin_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerFxn2 xdc_runtime_SysMin_Module__loggerFxn2__C = ((CT__xdc_runtime_SysMin_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerFxn4__C, ".const:xdc_runtime_SysMin_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerFxn4 xdc_runtime_SysMin_Module__loggerFxn4__C = ((CT__xdc_runtime_SysMin_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__loggerFxn8__C, ".const:xdc_runtime_SysMin_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__loggerFxn8 xdc_runtime_SysMin_Module__loggerFxn8__C = ((CT__xdc_runtime_SysMin_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Module__startupDoneFxn__C, ".const:xdc_runtime_SysMin_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_SysMin_Module__startupDoneFxn xdc_runtime_SysMin_Module__startupDoneFxn__C = ((CT__xdc_runtime_SysMin_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Object__count__C, ".const:xdc_runtime_SysMin_Object__count__C"); +__FAR__ const CT__xdc_runtime_SysMin_Object__count xdc_runtime_SysMin_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Object__heap__C, ".const:xdc_runtime_SysMin_Object__heap__C"); +__FAR__ const CT__xdc_runtime_SysMin_Object__heap xdc_runtime_SysMin_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Object__sizeof__C, ".const:xdc_runtime_SysMin_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_SysMin_Object__sizeof xdc_runtime_SysMin_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_Object__table__C, ".const:xdc_runtime_SysMin_Object__table__C"); +__FAR__ const CT__xdc_runtime_SysMin_Object__table xdc_runtime_SysMin_Object__table__C = 0; + +/* bufSize__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_bufSize__C, ".const:xdc_runtime_SysMin_bufSize__C"); +__FAR__ const CT__xdc_runtime_SysMin_bufSize xdc_runtime_SysMin_bufSize__C = (xdc_SizeT)0x80; + +/* flushAtExit__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_flushAtExit__C, ".const:xdc_runtime_SysMin_flushAtExit__C"); +__FAR__ const CT__xdc_runtime_SysMin_flushAtExit xdc_runtime_SysMin_flushAtExit__C = 1; + +/* outputFxn__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_outputFxn__C, ".const:xdc_runtime_SysMin_outputFxn__C"); +__FAR__ const CT__xdc_runtime_SysMin_outputFxn xdc_runtime_SysMin_outputFxn__C = ((CT__xdc_runtime_SysMin_outputFxn)0); + +/* outputFunc__C */ +#pragma DATA_SECTION(xdc_runtime_SysMin_outputFunc__C, ".const:xdc_runtime_SysMin_outputFunc__C"); +__FAR__ const CT__xdc_runtime_SysMin_outputFunc xdc_runtime_SysMin_outputFunc__C = ((CT__xdc_runtime_SysMin_outputFunc)((xdc_Fxn)xdc_runtime_SysMin_output__I)); + + +/* + * ======== xdc.runtime.System INITIALIZERS ======== + */ + +/* --> xdc_runtime_System_Module_State_0_atexitHandlers__A */ +__T1_xdc_runtime_System_Module_State__atexitHandlers xdc_runtime_System_Module_State_0_atexitHandlers__A[2] = { + ((xdc_Void(*)(xdc_Int))0), /* [0] */ + ((xdc_Void(*)(xdc_Int))0), /* [1] */ +}; + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_System_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_System_Module_State__ xdc_runtime_System_Module__state__V __attribute__ ((section(".data_xdc_runtime_System_Module__state__V"))); +#endif +#endif +xdc_runtime_System_Module_State__ xdc_runtime_System_Module__state__V = { + ((void*)xdc_runtime_System_Module_State_0_atexitHandlers__A), /* atexitHandlers */ + (xdc_Int)0x0, /* numAtexitHandlers */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__diagsEnabled__C, ".const:xdc_runtime_System_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_System_Module__diagsEnabled xdc_runtime_System_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__diagsIncluded__C, ".const:xdc_runtime_System_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_System_Module__diagsIncluded xdc_runtime_System_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__diagsMask__C, ".const:xdc_runtime_System_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_System_Module__diagsMask xdc_runtime_System_Module__diagsMask__C = ((CT__xdc_runtime_System_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__gateObj__C, ".const:xdc_runtime_System_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_System_Module__gateObj xdc_runtime_System_Module__gateObj__C = ((CT__xdc_runtime_System_Module__gateObj)((void*)(xdc_runtime_IGateProvider_Handle)&ti_sysbios_gates_GateHwi_Object__table__V[0])); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__gatePrms__C, ".const:xdc_runtime_System_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_System_Module__gatePrms xdc_runtime_System_Module__gatePrms__C = ((CT__xdc_runtime_System_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__id__C, ".const:xdc_runtime_System_Module__id__C"); +__FAR__ const CT__xdc_runtime_System_Module__id xdc_runtime_System_Module__id__C = (xdc_Bits16)0x800d; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerDefined__C, ".const:xdc_runtime_System_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerDefined xdc_runtime_System_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerObj__C, ".const:xdc_runtime_System_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerObj xdc_runtime_System_Module__loggerObj__C = ((CT__xdc_runtime_System_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerFxn0__C, ".const:xdc_runtime_System_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerFxn0 xdc_runtime_System_Module__loggerFxn0__C = ((CT__xdc_runtime_System_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerFxn1__C, ".const:xdc_runtime_System_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerFxn1 xdc_runtime_System_Module__loggerFxn1__C = ((CT__xdc_runtime_System_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerFxn2__C, ".const:xdc_runtime_System_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerFxn2 xdc_runtime_System_Module__loggerFxn2__C = ((CT__xdc_runtime_System_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerFxn4__C, ".const:xdc_runtime_System_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerFxn4 xdc_runtime_System_Module__loggerFxn4__C = ((CT__xdc_runtime_System_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__loggerFxn8__C, ".const:xdc_runtime_System_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_System_Module__loggerFxn8 xdc_runtime_System_Module__loggerFxn8__C = ((CT__xdc_runtime_System_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_System_Module__startupDoneFxn__C, ".const:xdc_runtime_System_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_System_Module__startupDoneFxn xdc_runtime_System_Module__startupDoneFxn__C = ((CT__xdc_runtime_System_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_System_Object__count__C, ".const:xdc_runtime_System_Object__count__C"); +__FAR__ const CT__xdc_runtime_System_Object__count xdc_runtime_System_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_System_Object__heap__C, ".const:xdc_runtime_System_Object__heap__C"); +__FAR__ const CT__xdc_runtime_System_Object__heap xdc_runtime_System_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_System_Object__sizeof__C, ".const:xdc_runtime_System_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_System_Object__sizeof xdc_runtime_System_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_System_Object__table__C, ".const:xdc_runtime_System_Object__table__C"); +__FAR__ const CT__xdc_runtime_System_Object__table xdc_runtime_System_Object__table__C = 0; + +/* A_cannotFitIntoArg__C */ +#pragma DATA_SECTION(xdc_runtime_System_A_cannotFitIntoArg__C, ".const:xdc_runtime_System_A_cannotFitIntoArg__C"); +__FAR__ const CT__xdc_runtime_System_A_cannotFitIntoArg xdc_runtime_System_A_cannotFitIntoArg__C = (((xdc_runtime_Assert_Id)352) << 16 | 16); + +/* maxAtexitHandlers__C */ +#pragma DATA_SECTION(xdc_runtime_System_maxAtexitHandlers__C, ".const:xdc_runtime_System_maxAtexitHandlers__C"); +__FAR__ const CT__xdc_runtime_System_maxAtexitHandlers xdc_runtime_System_maxAtexitHandlers__C = (xdc_Int)0x2; + +/* abortFxn__C */ +#pragma DATA_SECTION(xdc_runtime_System_abortFxn__C, ".const:xdc_runtime_System_abortFxn__C"); +__FAR__ const CT__xdc_runtime_System_abortFxn xdc_runtime_System_abortFxn__C = ((CT__xdc_runtime_System_abortFxn)((xdc_Fxn)xdc_runtime_System_abortStd__E)); + +/* exitFxn__C */ +#pragma DATA_SECTION(xdc_runtime_System_exitFxn__C, ".const:xdc_runtime_System_exitFxn__C"); +__FAR__ const CT__xdc_runtime_System_exitFxn xdc_runtime_System_exitFxn__C = ((CT__xdc_runtime_System_exitFxn)((xdc_Fxn)xdc_runtime_System_exitStd__E)); + +/* extendFxn__C */ +#pragma DATA_SECTION(xdc_runtime_System_extendFxn__C, ".const:xdc_runtime_System_extendFxn__C"); +__FAR__ const CT__xdc_runtime_System_extendFxn xdc_runtime_System_extendFxn__C = ((CT__xdc_runtime_System_extendFxn)((xdc_Fxn)xdc_runtime_System_printfExtend__I)); + + +/* + * ======== xdc.runtime.System_Module_GateProxy INITIALIZERS ======== + */ + + +/* + * ======== xdc.runtime.System_SupportProxy INITIALIZERS ======== + */ + + +/* + * ======== xdc.runtime.Text INITIALIZERS ======== + */ + +/* Module__state__V */ +#if defined (__ICCARM__) +#pragma location = ".data_xdc_runtime_Text_Module__state__V" +#endif +#if defined(__GNUC__) && !(defined(__MACH__) && defined(__APPLE__)) +#ifndef __TI_COMPILER_VERSION__ +xdc_runtime_Text_Module_State__ xdc_runtime_Text_Module__state__V __attribute__ ((section(".data_xdc_runtime_Text_Module__state__V"))); +#endif +#endif +xdc_runtime_Text_Module_State__ xdc_runtime_Text_Module__state__V = { + ((xdc_CPtr)(&xdc_runtime_Text_charTab__A[0])), /* charBase */ + ((xdc_CPtr)(&xdc_runtime_Text_nodeTab__A[0])), /* nodeBase */ +}; + +/* --> xdc_runtime_Text_charTab__A */ +#pragma DATA_SECTION(xdc_runtime_Text_charTab__A, ".const:xdc_runtime_Text_charTab__A"); +const __T1_xdc_runtime_Text_charTab xdc_runtime_Text_charTab__A[6253] = { + (xdc_Char)0x0, /* [0] */ + (xdc_Char)0x41, /* [1] */ + (xdc_Char)0x5f, /* [2] */ + (xdc_Char)0x69, /* [3] */ + (xdc_Char)0x6e, /* [4] */ + (xdc_Char)0x69, /* [5] */ + (xdc_Char)0x74, /* [6] */ + (xdc_Char)0x69, /* [7] */ + (xdc_Char)0x61, /* [8] */ + (xdc_Char)0x6c, /* [9] */ + (xdc_Char)0x69, /* [10] */ + (xdc_Char)0x7a, /* [11] */ + (xdc_Char)0x65, /* [12] */ + (xdc_Char)0x64, /* [13] */ + (xdc_Char)0x50, /* [14] */ + (xdc_Char)0x61, /* [15] */ + (xdc_Char)0x72, /* [16] */ + (xdc_Char)0x61, /* [17] */ + (xdc_Char)0x6d, /* [18] */ + (xdc_Char)0x73, /* [19] */ + (xdc_Char)0x3a, /* [20] */ + (xdc_Char)0x20, /* [21] */ + (xdc_Char)0x75, /* [22] */ + (xdc_Char)0x6e, /* [23] */ + (xdc_Char)0x69, /* [24] */ + (xdc_Char)0x6e, /* [25] */ + (xdc_Char)0x69, /* [26] */ + (xdc_Char)0x74, /* [27] */ + (xdc_Char)0x69, /* [28] */ + (xdc_Char)0x61, /* [29] */ + (xdc_Char)0x6c, /* [30] */ + (xdc_Char)0x69, /* [31] */ + (xdc_Char)0x7a, /* [32] */ + (xdc_Char)0x65, /* [33] */ + (xdc_Char)0x64, /* [34] */ + (xdc_Char)0x20, /* [35] */ + (xdc_Char)0x50, /* [36] */ + (xdc_Char)0x61, /* [37] */ + (xdc_Char)0x72, /* [38] */ + (xdc_Char)0x61, /* [39] */ + (xdc_Char)0x6d, /* [40] */ + (xdc_Char)0x73, /* [41] */ + (xdc_Char)0x20, /* [42] */ + (xdc_Char)0x73, /* [43] */ + (xdc_Char)0x74, /* [44] */ + (xdc_Char)0x72, /* [45] */ + (xdc_Char)0x75, /* [46] */ + (xdc_Char)0x63, /* [47] */ + (xdc_Char)0x74, /* [48] */ + (xdc_Char)0x0, /* [49] */ + (xdc_Char)0x48, /* [50] */ + (xdc_Char)0x65, /* [51] */ + (xdc_Char)0x61, /* [52] */ + (xdc_Char)0x70, /* [53] */ + (xdc_Char)0x4d, /* [54] */ + (xdc_Char)0x69, /* [55] */ + (xdc_Char)0x6e, /* [56] */ + (xdc_Char)0x5f, /* [57] */ + (xdc_Char)0x63, /* [58] */ + (xdc_Char)0x72, /* [59] */ + (xdc_Char)0x65, /* [60] */ + (xdc_Char)0x61, /* [61] */ + (xdc_Char)0x74, /* [62] */ + (xdc_Char)0x65, /* [63] */ + (xdc_Char)0x20, /* [64] */ + (xdc_Char)0x63, /* [65] */ + (xdc_Char)0x61, /* [66] */ + (xdc_Char)0x6e, /* [67] */ + (xdc_Char)0x6e, /* [68] */ + (xdc_Char)0x6f, /* [69] */ + (xdc_Char)0x74, /* [70] */ + (xdc_Char)0x20, /* [71] */ + (xdc_Char)0x68, /* [72] */ + (xdc_Char)0x61, /* [73] */ + (xdc_Char)0x76, /* [74] */ + (xdc_Char)0x65, /* [75] */ + (xdc_Char)0x20, /* [76] */ + (xdc_Char)0x61, /* [77] */ + (xdc_Char)0x20, /* [78] */ + (xdc_Char)0x7a, /* [79] */ + (xdc_Char)0x65, /* [80] */ + (xdc_Char)0x72, /* [81] */ + (xdc_Char)0x6f, /* [82] */ + (xdc_Char)0x20, /* [83] */ + (xdc_Char)0x73, /* [84] */ + (xdc_Char)0x69, /* [85] */ + (xdc_Char)0x7a, /* [86] */ + (xdc_Char)0x65, /* [87] */ + (xdc_Char)0x20, /* [88] */ + (xdc_Char)0x76, /* [89] */ + (xdc_Char)0x61, /* [90] */ + (xdc_Char)0x6c, /* [91] */ + (xdc_Char)0x75, /* [92] */ + (xdc_Char)0x65, /* [93] */ + (xdc_Char)0x0, /* [94] */ + (xdc_Char)0x48, /* [95] */ + (xdc_Char)0x65, /* [96] */ + (xdc_Char)0x61, /* [97] */ + (xdc_Char)0x70, /* [98] */ + (xdc_Char)0x53, /* [99] */ + (xdc_Char)0x74, /* [100] */ + (xdc_Char)0x64, /* [101] */ + (xdc_Char)0x5f, /* [102] */ + (xdc_Char)0x63, /* [103] */ + (xdc_Char)0x72, /* [104] */ + (xdc_Char)0x65, /* [105] */ + (xdc_Char)0x61, /* [106] */ + (xdc_Char)0x74, /* [107] */ + (xdc_Char)0x65, /* [108] */ + (xdc_Char)0x20, /* [109] */ + (xdc_Char)0x63, /* [110] */ + (xdc_Char)0x61, /* [111] */ + (xdc_Char)0x6e, /* [112] */ + (xdc_Char)0x6e, /* [113] */ + (xdc_Char)0x6f, /* [114] */ + (xdc_Char)0x74, /* [115] */ + (xdc_Char)0x20, /* [116] */ + (xdc_Char)0x68, /* [117] */ + (xdc_Char)0x61, /* [118] */ + (xdc_Char)0x76, /* [119] */ + (xdc_Char)0x65, /* [120] */ + (xdc_Char)0x20, /* [121] */ + (xdc_Char)0x61, /* [122] */ + (xdc_Char)0x20, /* [123] */ + (xdc_Char)0x7a, /* [124] */ + (xdc_Char)0x65, /* [125] */ + (xdc_Char)0x72, /* [126] */ + (xdc_Char)0x6f, /* [127] */ + (xdc_Char)0x20, /* [128] */ + (xdc_Char)0x73, /* [129] */ + (xdc_Char)0x69, /* [130] */ + (xdc_Char)0x7a, /* [131] */ + (xdc_Char)0x65, /* [132] */ + (xdc_Char)0x20, /* [133] */ + (xdc_Char)0x76, /* [134] */ + (xdc_Char)0x61, /* [135] */ + (xdc_Char)0x6c, /* [136] */ + (xdc_Char)0x75, /* [137] */ + (xdc_Char)0x65, /* [138] */ + (xdc_Char)0x0, /* [139] */ + (xdc_Char)0x48, /* [140] */ + (xdc_Char)0x65, /* [141] */ + (xdc_Char)0x61, /* [142] */ + (xdc_Char)0x70, /* [143] */ + (xdc_Char)0x53, /* [144] */ + (xdc_Char)0x74, /* [145] */ + (xdc_Char)0x64, /* [146] */ + (xdc_Char)0x5f, /* [147] */ + (xdc_Char)0x61, /* [148] */ + (xdc_Char)0x6c, /* [149] */ + (xdc_Char)0x6c, /* [150] */ + (xdc_Char)0x6f, /* [151] */ + (xdc_Char)0x63, /* [152] */ + (xdc_Char)0x20, /* [153] */ + (xdc_Char)0x61, /* [154] */ + (xdc_Char)0x6c, /* [155] */ + (xdc_Char)0x69, /* [156] */ + (xdc_Char)0x67, /* [157] */ + (xdc_Char)0x6e, /* [158] */ + (xdc_Char)0x6d, /* [159] */ + (xdc_Char)0x65, /* [160] */ + (xdc_Char)0x6e, /* [161] */ + (xdc_Char)0x74, /* [162] */ + (xdc_Char)0x20, /* [163] */ + (xdc_Char)0x6d, /* [164] */ + (xdc_Char)0x75, /* [165] */ + (xdc_Char)0x73, /* [166] */ + (xdc_Char)0x74, /* [167] */ + (xdc_Char)0x20, /* [168] */ + (xdc_Char)0x62, /* [169] */ + (xdc_Char)0x65, /* [170] */ + (xdc_Char)0x20, /* [171] */ + (xdc_Char)0x61, /* [172] */ + (xdc_Char)0x20, /* [173] */ + (xdc_Char)0x70, /* [174] */ + (xdc_Char)0x6f, /* [175] */ + (xdc_Char)0x77, /* [176] */ + (xdc_Char)0x65, /* [177] */ + (xdc_Char)0x72, /* [178] */ + (xdc_Char)0x20, /* [179] */ + (xdc_Char)0x6f, /* [180] */ + (xdc_Char)0x66, /* [181] */ + (xdc_Char)0x20, /* [182] */ + (xdc_Char)0x32, /* [183] */ + (xdc_Char)0x0, /* [184] */ + (xdc_Char)0x48, /* [185] */ + (xdc_Char)0x65, /* [186] */ + (xdc_Char)0x61, /* [187] */ + (xdc_Char)0x70, /* [188] */ + (xdc_Char)0x53, /* [189] */ + (xdc_Char)0x74, /* [190] */ + (xdc_Char)0x64, /* [191] */ + (xdc_Char)0x20, /* [192] */ + (xdc_Char)0x69, /* [193] */ + (xdc_Char)0x6e, /* [194] */ + (xdc_Char)0x73, /* [195] */ + (xdc_Char)0x74, /* [196] */ + (xdc_Char)0x61, /* [197] */ + (xdc_Char)0x6e, /* [198] */ + (xdc_Char)0x63, /* [199] */ + (xdc_Char)0x65, /* [200] */ + (xdc_Char)0x20, /* [201] */ + (xdc_Char)0x74, /* [202] */ + (xdc_Char)0x6f, /* [203] */ + (xdc_Char)0x74, /* [204] */ + (xdc_Char)0x61, /* [205] */ + (xdc_Char)0x6c, /* [206] */ + (xdc_Char)0x46, /* [207] */ + (xdc_Char)0x72, /* [208] */ + (xdc_Char)0x65, /* [209] */ + (xdc_Char)0x65, /* [210] */ + (xdc_Char)0x53, /* [211] */ + (xdc_Char)0x69, /* [212] */ + (xdc_Char)0x7a, /* [213] */ + (xdc_Char)0x65, /* [214] */ + (xdc_Char)0x20, /* [215] */ + (xdc_Char)0x69, /* [216] */ + (xdc_Char)0x73, /* [217] */ + (xdc_Char)0x20, /* [218] */ + (xdc_Char)0x67, /* [219] */ + (xdc_Char)0x72, /* [220] */ + (xdc_Char)0x65, /* [221] */ + (xdc_Char)0x61, /* [222] */ + (xdc_Char)0x74, /* [223] */ + (xdc_Char)0x65, /* [224] */ + (xdc_Char)0x72, /* [225] */ + (xdc_Char)0x20, /* [226] */ + (xdc_Char)0x74, /* [227] */ + (xdc_Char)0x68, /* [228] */ + (xdc_Char)0x61, /* [229] */ + (xdc_Char)0x6e, /* [230] */ + (xdc_Char)0x20, /* [231] */ + (xdc_Char)0x73, /* [232] */ + (xdc_Char)0x74, /* [233] */ + (xdc_Char)0x61, /* [234] */ + (xdc_Char)0x72, /* [235] */ + (xdc_Char)0x74, /* [236] */ + (xdc_Char)0x69, /* [237] */ + (xdc_Char)0x6e, /* [238] */ + (xdc_Char)0x67, /* [239] */ + (xdc_Char)0x20, /* [240] */ + (xdc_Char)0x73, /* [241] */ + (xdc_Char)0x69, /* [242] */ + (xdc_Char)0x7a, /* [243] */ + (xdc_Char)0x65, /* [244] */ + (xdc_Char)0x0, /* [245] */ + (xdc_Char)0x48, /* [246] */ + (xdc_Char)0x65, /* [247] */ + (xdc_Char)0x61, /* [248] */ + (xdc_Char)0x70, /* [249] */ + (xdc_Char)0x53, /* [250] */ + (xdc_Char)0x74, /* [251] */ + (xdc_Char)0x64, /* [252] */ + (xdc_Char)0x5f, /* [253] */ + (xdc_Char)0x61, /* [254] */ + (xdc_Char)0x6c, /* [255] */ + (xdc_Char)0x6c, /* [256] */ + (xdc_Char)0x6f, /* [257] */ + (xdc_Char)0x63, /* [258] */ + (xdc_Char)0x20, /* [259] */ + (xdc_Char)0x2d, /* [260] */ + (xdc_Char)0x20, /* [261] */ + (xdc_Char)0x72, /* [262] */ + (xdc_Char)0x65, /* [263] */ + (xdc_Char)0x71, /* [264] */ + (xdc_Char)0x75, /* [265] */ + (xdc_Char)0x65, /* [266] */ + (xdc_Char)0x73, /* [267] */ + (xdc_Char)0x74, /* [268] */ + (xdc_Char)0x65, /* [269] */ + (xdc_Char)0x64, /* [270] */ + (xdc_Char)0x20, /* [271] */ + (xdc_Char)0x61, /* [272] */ + (xdc_Char)0x6c, /* [273] */ + (xdc_Char)0x69, /* [274] */ + (xdc_Char)0x67, /* [275] */ + (xdc_Char)0x6e, /* [276] */ + (xdc_Char)0x6d, /* [277] */ + (xdc_Char)0x65, /* [278] */ + (xdc_Char)0x6e, /* [279] */ + (xdc_Char)0x74, /* [280] */ + (xdc_Char)0x20, /* [281] */ + (xdc_Char)0x69, /* [282] */ + (xdc_Char)0x73, /* [283] */ + (xdc_Char)0x20, /* [284] */ + (xdc_Char)0x67, /* [285] */ + (xdc_Char)0x72, /* [286] */ + (xdc_Char)0x65, /* [287] */ + (xdc_Char)0x61, /* [288] */ + (xdc_Char)0x74, /* [289] */ + (xdc_Char)0x65, /* [290] */ + (xdc_Char)0x72, /* [291] */ + (xdc_Char)0x20, /* [292] */ + (xdc_Char)0x74, /* [293] */ + (xdc_Char)0x68, /* [294] */ + (xdc_Char)0x61, /* [295] */ + (xdc_Char)0x6e, /* [296] */ + (xdc_Char)0x20, /* [297] */ + (xdc_Char)0x61, /* [298] */ + (xdc_Char)0x6c, /* [299] */ + (xdc_Char)0x6c, /* [300] */ + (xdc_Char)0x6f, /* [301] */ + (xdc_Char)0x77, /* [302] */ + (xdc_Char)0x65, /* [303] */ + (xdc_Char)0x64, /* [304] */ + (xdc_Char)0x0, /* [305] */ + (xdc_Char)0x41, /* [306] */ + (xdc_Char)0x5f, /* [307] */ + (xdc_Char)0x69, /* [308] */ + (xdc_Char)0x6e, /* [309] */ + (xdc_Char)0x76, /* [310] */ + (xdc_Char)0x61, /* [311] */ + (xdc_Char)0x6c, /* [312] */ + (xdc_Char)0x69, /* [313] */ + (xdc_Char)0x64, /* [314] */ + (xdc_Char)0x4c, /* [315] */ + (xdc_Char)0x6f, /* [316] */ + (xdc_Char)0x67, /* [317] */ + (xdc_Char)0x67, /* [318] */ + (xdc_Char)0x65, /* [319] */ + (xdc_Char)0x72, /* [320] */ + (xdc_Char)0x3a, /* [321] */ + (xdc_Char)0x20, /* [322] */ + (xdc_Char)0x54, /* [323] */ + (xdc_Char)0x68, /* [324] */ + (xdc_Char)0x65, /* [325] */ + (xdc_Char)0x20, /* [326] */ + (xdc_Char)0x6c, /* [327] */ + (xdc_Char)0x6f, /* [328] */ + (xdc_Char)0x67, /* [329] */ + (xdc_Char)0x67, /* [330] */ + (xdc_Char)0x65, /* [331] */ + (xdc_Char)0x72, /* [332] */ + (xdc_Char)0x20, /* [333] */ + (xdc_Char)0x69, /* [334] */ + (xdc_Char)0x64, /* [335] */ + (xdc_Char)0x20, /* [336] */ + (xdc_Char)0x25, /* [337] */ + (xdc_Char)0x64, /* [338] */ + (xdc_Char)0x20, /* [339] */ + (xdc_Char)0x69, /* [340] */ + (xdc_Char)0x73, /* [341] */ + (xdc_Char)0x20, /* [342] */ + (xdc_Char)0x69, /* [343] */ + (xdc_Char)0x6e, /* [344] */ + (xdc_Char)0x76, /* [345] */ + (xdc_Char)0x61, /* [346] */ + (xdc_Char)0x6c, /* [347] */ + (xdc_Char)0x69, /* [348] */ + (xdc_Char)0x64, /* [349] */ + (xdc_Char)0x2e, /* [350] */ + (xdc_Char)0x0, /* [351] */ + (xdc_Char)0x41, /* [352] */ + (xdc_Char)0x5f, /* [353] */ + (xdc_Char)0x63, /* [354] */ + (xdc_Char)0x61, /* [355] */ + (xdc_Char)0x6e, /* [356] */ + (xdc_Char)0x6e, /* [357] */ + (xdc_Char)0x6f, /* [358] */ + (xdc_Char)0x74, /* [359] */ + (xdc_Char)0x46, /* [360] */ + (xdc_Char)0x69, /* [361] */ + (xdc_Char)0x74, /* [362] */ + (xdc_Char)0x49, /* [363] */ + (xdc_Char)0x6e, /* [364] */ + (xdc_Char)0x74, /* [365] */ + (xdc_Char)0x6f, /* [366] */ + (xdc_Char)0x41, /* [367] */ + (xdc_Char)0x72, /* [368] */ + (xdc_Char)0x67, /* [369] */ + (xdc_Char)0x3a, /* [370] */ + (xdc_Char)0x20, /* [371] */ + (xdc_Char)0x73, /* [372] */ + (xdc_Char)0x69, /* [373] */ + (xdc_Char)0x7a, /* [374] */ + (xdc_Char)0x65, /* [375] */ + (xdc_Char)0x6f, /* [376] */ + (xdc_Char)0x66, /* [377] */ + (xdc_Char)0x28, /* [378] */ + (xdc_Char)0x46, /* [379] */ + (xdc_Char)0x6c, /* [380] */ + (xdc_Char)0x6f, /* [381] */ + (xdc_Char)0x61, /* [382] */ + (xdc_Char)0x74, /* [383] */ + (xdc_Char)0x29, /* [384] */ + (xdc_Char)0x20, /* [385] */ + (xdc_Char)0x3e, /* [386] */ + (xdc_Char)0x20, /* [387] */ + (xdc_Char)0x73, /* [388] */ + (xdc_Char)0x69, /* [389] */ + (xdc_Char)0x7a, /* [390] */ + (xdc_Char)0x65, /* [391] */ + (xdc_Char)0x6f, /* [392] */ + (xdc_Char)0x66, /* [393] */ + (xdc_Char)0x28, /* [394] */ + (xdc_Char)0x41, /* [395] */ + (xdc_Char)0x72, /* [396] */ + (xdc_Char)0x67, /* [397] */ + (xdc_Char)0x29, /* [398] */ + (xdc_Char)0x0, /* [399] */ + (xdc_Char)0x41, /* [400] */ + (xdc_Char)0x5f, /* [401] */ + (xdc_Char)0x6d, /* [402] */ + (xdc_Char)0x75, /* [403] */ + (xdc_Char)0x73, /* [404] */ + (xdc_Char)0x74, /* [405] */ + (xdc_Char)0x55, /* [406] */ + (xdc_Char)0x73, /* [407] */ + (xdc_Char)0x65, /* [408] */ + (xdc_Char)0x45, /* [409] */ + (xdc_Char)0x6e, /* [410] */ + (xdc_Char)0x68, /* [411] */ + (xdc_Char)0x61, /* [412] */ + (xdc_Char)0x6e, /* [413] */ + (xdc_Char)0x63, /* [414] */ + (xdc_Char)0x65, /* [415] */ + (xdc_Char)0x64, /* [416] */ + (xdc_Char)0x43, /* [417] */ + (xdc_Char)0x6c, /* [418] */ + (xdc_Char)0x6f, /* [419] */ + (xdc_Char)0x63, /* [420] */ + (xdc_Char)0x6b, /* [421] */ + (xdc_Char)0x4d, /* [422] */ + (xdc_Char)0x6f, /* [423] */ + (xdc_Char)0x64, /* [424] */ + (xdc_Char)0x65, /* [425] */ + (xdc_Char)0x3a, /* [426] */ + (xdc_Char)0x20, /* [427] */ + (xdc_Char)0x54, /* [428] */ + (xdc_Char)0x68, /* [429] */ + (xdc_Char)0x69, /* [430] */ + (xdc_Char)0x73, /* [431] */ + (xdc_Char)0x20, /* [432] */ + (xdc_Char)0x64, /* [433] */ + (xdc_Char)0x65, /* [434] */ + (xdc_Char)0x76, /* [435] */ + (xdc_Char)0x69, /* [436] */ + (xdc_Char)0x63, /* [437] */ + (xdc_Char)0x65, /* [438] */ + (xdc_Char)0x20, /* [439] */ + (xdc_Char)0x72, /* [440] */ + (xdc_Char)0x65, /* [441] */ + (xdc_Char)0x71, /* [442] */ + (xdc_Char)0x75, /* [443] */ + (xdc_Char)0x69, /* [444] */ + (xdc_Char)0x72, /* [445] */ + (xdc_Char)0x65, /* [446] */ + (xdc_Char)0x73, /* [447] */ + (xdc_Char)0x20, /* [448] */ + (xdc_Char)0x74, /* [449] */ + (xdc_Char)0x68, /* [450] */ + (xdc_Char)0x65, /* [451] */ + (xdc_Char)0x20, /* [452] */ + (xdc_Char)0x45, /* [453] */ + (xdc_Char)0x6e, /* [454] */ + (xdc_Char)0x68, /* [455] */ + (xdc_Char)0x61, /* [456] */ + (xdc_Char)0x6e, /* [457] */ + (xdc_Char)0x63, /* [458] */ + (xdc_Char)0x65, /* [459] */ + (xdc_Char)0x64, /* [460] */ + (xdc_Char)0x20, /* [461] */ + (xdc_Char)0x43, /* [462] */ + (xdc_Char)0x6c, /* [463] */ + (xdc_Char)0x6f, /* [464] */ + (xdc_Char)0x63, /* [465] */ + (xdc_Char)0x6b, /* [466] */ + (xdc_Char)0x20, /* [467] */ + (xdc_Char)0x4d, /* [468] */ + (xdc_Char)0x6f, /* [469] */ + (xdc_Char)0x64, /* [470] */ + (xdc_Char)0x65, /* [471] */ + (xdc_Char)0x2e, /* [472] */ + (xdc_Char)0x0, /* [473] */ + (xdc_Char)0x41, /* [474] */ + (xdc_Char)0x5f, /* [475] */ + (xdc_Char)0x6d, /* [476] */ + (xdc_Char)0x75, /* [477] */ + (xdc_Char)0x73, /* [478] */ + (xdc_Char)0x74, /* [479] */ + (xdc_Char)0x4e, /* [480] */ + (xdc_Char)0x6f, /* [481] */ + (xdc_Char)0x74, /* [482] */ + (xdc_Char)0x55, /* [483] */ + (xdc_Char)0x73, /* [484] */ + (xdc_Char)0x65, /* [485] */ + (xdc_Char)0x45, /* [486] */ + (xdc_Char)0x6e, /* [487] */ + (xdc_Char)0x68, /* [488] */ + (xdc_Char)0x61, /* [489] */ + (xdc_Char)0x6e, /* [490] */ + (xdc_Char)0x63, /* [491] */ + (xdc_Char)0x65, /* [492] */ + (xdc_Char)0x64, /* [493] */ + (xdc_Char)0x43, /* [494] */ + (xdc_Char)0x6c, /* [495] */ + (xdc_Char)0x6f, /* [496] */ + (xdc_Char)0x63, /* [497] */ + (xdc_Char)0x6b, /* [498] */ + (xdc_Char)0x4d, /* [499] */ + (xdc_Char)0x6f, /* [500] */ + (xdc_Char)0x64, /* [501] */ + (xdc_Char)0x65, /* [502] */ + (xdc_Char)0x3a, /* [503] */ + (xdc_Char)0x20, /* [504] */ + (xdc_Char)0x54, /* [505] */ + (xdc_Char)0x68, /* [506] */ + (xdc_Char)0x69, /* [507] */ + (xdc_Char)0x73, /* [508] */ + (xdc_Char)0x20, /* [509] */ + (xdc_Char)0x64, /* [510] */ + (xdc_Char)0x65, /* [511] */ + (xdc_Char)0x76, /* [512] */ + (xdc_Char)0x69, /* [513] */ + (xdc_Char)0x63, /* [514] */ + (xdc_Char)0x65, /* [515] */ + (xdc_Char)0x20, /* [516] */ + (xdc_Char)0x64, /* [517] */ + (xdc_Char)0x6f, /* [518] */ + (xdc_Char)0x65, /* [519] */ + (xdc_Char)0x73, /* [520] */ + (xdc_Char)0x20, /* [521] */ + (xdc_Char)0x6e, /* [522] */ + (xdc_Char)0x6f, /* [523] */ + (xdc_Char)0x74, /* [524] */ + (xdc_Char)0x20, /* [525] */ + (xdc_Char)0x73, /* [526] */ + (xdc_Char)0x75, /* [527] */ + (xdc_Char)0x70, /* [528] */ + (xdc_Char)0x70, /* [529] */ + (xdc_Char)0x6f, /* [530] */ + (xdc_Char)0x72, /* [531] */ + (xdc_Char)0x74, /* [532] */ + (xdc_Char)0x20, /* [533] */ + (xdc_Char)0x74, /* [534] */ + (xdc_Char)0x68, /* [535] */ + (xdc_Char)0x65, /* [536] */ + (xdc_Char)0x20, /* [537] */ + (xdc_Char)0x45, /* [538] */ + (xdc_Char)0x6e, /* [539] */ + (xdc_Char)0x68, /* [540] */ + (xdc_Char)0x61, /* [541] */ + (xdc_Char)0x6e, /* [542] */ + (xdc_Char)0x63, /* [543] */ + (xdc_Char)0x65, /* [544] */ + (xdc_Char)0x64, /* [545] */ + (xdc_Char)0x20, /* [546] */ + (xdc_Char)0x43, /* [547] */ + (xdc_Char)0x6c, /* [548] */ + (xdc_Char)0x6f, /* [549] */ + (xdc_Char)0x63, /* [550] */ + (xdc_Char)0x6b, /* [551] */ + (xdc_Char)0x20, /* [552] */ + (xdc_Char)0x4d, /* [553] */ + (xdc_Char)0x6f, /* [554] */ + (xdc_Char)0x64, /* [555] */ + (xdc_Char)0x65, /* [556] */ + (xdc_Char)0x2e, /* [557] */ + (xdc_Char)0x0, /* [558] */ + (xdc_Char)0x41, /* [559] */ + (xdc_Char)0x5f, /* [560] */ + (xdc_Char)0x6e, /* [561] */ + (xdc_Char)0x75, /* [562] */ + (xdc_Char)0x6c, /* [563] */ + (xdc_Char)0x6c, /* [564] */ + (xdc_Char)0x50, /* [565] */ + (xdc_Char)0x6f, /* [566] */ + (xdc_Char)0x69, /* [567] */ + (xdc_Char)0x6e, /* [568] */ + (xdc_Char)0x74, /* [569] */ + (xdc_Char)0x65, /* [570] */ + (xdc_Char)0x72, /* [571] */ + (xdc_Char)0x3a, /* [572] */ + (xdc_Char)0x20, /* [573] */ + (xdc_Char)0x50, /* [574] */ + (xdc_Char)0x6f, /* [575] */ + (xdc_Char)0x69, /* [576] */ + (xdc_Char)0x6e, /* [577] */ + (xdc_Char)0x74, /* [578] */ + (xdc_Char)0x65, /* [579] */ + (xdc_Char)0x72, /* [580] */ + (xdc_Char)0x20, /* [581] */ + (xdc_Char)0x69, /* [582] */ + (xdc_Char)0x73, /* [583] */ + (xdc_Char)0x20, /* [584] */ + (xdc_Char)0x6e, /* [585] */ + (xdc_Char)0x75, /* [586] */ + (xdc_Char)0x6c, /* [587] */ + (xdc_Char)0x6c, /* [588] */ + (xdc_Char)0x0, /* [589] */ + (xdc_Char)0x41, /* [590] */ + (xdc_Char)0x5f, /* [591] */ + (xdc_Char)0x69, /* [592] */ + (xdc_Char)0x6e, /* [593] */ + (xdc_Char)0x76, /* [594] */ + (xdc_Char)0x61, /* [595] */ + (xdc_Char)0x6c, /* [596] */ + (xdc_Char)0x69, /* [597] */ + (xdc_Char)0x64, /* [598] */ + (xdc_Char)0x52, /* [599] */ + (xdc_Char)0x65, /* [600] */ + (xdc_Char)0x67, /* [601] */ + (xdc_Char)0x69, /* [602] */ + (xdc_Char)0x6f, /* [603] */ + (xdc_Char)0x6e, /* [604] */ + (xdc_Char)0x49, /* [605] */ + (xdc_Char)0x64, /* [606] */ + (xdc_Char)0x3a, /* [607] */ + (xdc_Char)0x20, /* [608] */ + (xdc_Char)0x4d, /* [609] */ + (xdc_Char)0x50, /* [610] */ + (xdc_Char)0x55, /* [611] */ + (xdc_Char)0x20, /* [612] */ + (xdc_Char)0x52, /* [613] */ + (xdc_Char)0x65, /* [614] */ + (xdc_Char)0x67, /* [615] */ + (xdc_Char)0x69, /* [616] */ + (xdc_Char)0x6f, /* [617] */ + (xdc_Char)0x6e, /* [618] */ + (xdc_Char)0x20, /* [619] */ + (xdc_Char)0x6e, /* [620] */ + (xdc_Char)0x75, /* [621] */ + (xdc_Char)0x6d, /* [622] */ + (xdc_Char)0x62, /* [623] */ + (xdc_Char)0x65, /* [624] */ + (xdc_Char)0x72, /* [625] */ + (xdc_Char)0x20, /* [626] */ + (xdc_Char)0x70, /* [627] */ + (xdc_Char)0x61, /* [628] */ + (xdc_Char)0x73, /* [629] */ + (xdc_Char)0x73, /* [630] */ + (xdc_Char)0x65, /* [631] */ + (xdc_Char)0x64, /* [632] */ + (xdc_Char)0x20, /* [633] */ + (xdc_Char)0x69, /* [634] */ + (xdc_Char)0x73, /* [635] */ + (xdc_Char)0x20, /* [636] */ + (xdc_Char)0x69, /* [637] */ + (xdc_Char)0x6e, /* [638] */ + (xdc_Char)0x76, /* [639] */ + (xdc_Char)0x61, /* [640] */ + (xdc_Char)0x6c, /* [641] */ + (xdc_Char)0x69, /* [642] */ + (xdc_Char)0x64, /* [643] */ + (xdc_Char)0x2e, /* [644] */ + (xdc_Char)0x0, /* [645] */ + (xdc_Char)0x41, /* [646] */ + (xdc_Char)0x5f, /* [647] */ + (xdc_Char)0x75, /* [648] */ + (xdc_Char)0x6e, /* [649] */ + (xdc_Char)0x61, /* [650] */ + (xdc_Char)0x6c, /* [651] */ + (xdc_Char)0x69, /* [652] */ + (xdc_Char)0x67, /* [653] */ + (xdc_Char)0x6e, /* [654] */ + (xdc_Char)0x65, /* [655] */ + (xdc_Char)0x64, /* [656] */ + (xdc_Char)0x42, /* [657] */ + (xdc_Char)0x61, /* [658] */ + (xdc_Char)0x73, /* [659] */ + (xdc_Char)0x65, /* [660] */ + (xdc_Char)0x41, /* [661] */ + (xdc_Char)0x64, /* [662] */ + (xdc_Char)0x64, /* [663] */ + (xdc_Char)0x72, /* [664] */ + (xdc_Char)0x3a, /* [665] */ + (xdc_Char)0x20, /* [666] */ + (xdc_Char)0x4d, /* [667] */ + (xdc_Char)0x50, /* [668] */ + (xdc_Char)0x55, /* [669] */ + (xdc_Char)0x20, /* [670] */ + (xdc_Char)0x72, /* [671] */ + (xdc_Char)0x65, /* [672] */ + (xdc_Char)0x67, /* [673] */ + (xdc_Char)0x69, /* [674] */ + (xdc_Char)0x6f, /* [675] */ + (xdc_Char)0x6e, /* [676] */ + (xdc_Char)0x20, /* [677] */ + (xdc_Char)0x62, /* [678] */ + (xdc_Char)0x61, /* [679] */ + (xdc_Char)0x73, /* [680] */ + (xdc_Char)0x65, /* [681] */ + (xdc_Char)0x20, /* [682] */ + (xdc_Char)0x61, /* [683] */ + (xdc_Char)0x64, /* [684] */ + (xdc_Char)0x64, /* [685] */ + (xdc_Char)0x72, /* [686] */ + (xdc_Char)0x65, /* [687] */ + (xdc_Char)0x73, /* [688] */ + (xdc_Char)0x73, /* [689] */ + (xdc_Char)0x20, /* [690] */ + (xdc_Char)0x6e, /* [691] */ + (xdc_Char)0x6f, /* [692] */ + (xdc_Char)0x74, /* [693] */ + (xdc_Char)0x20, /* [694] */ + (xdc_Char)0x61, /* [695] */ + (xdc_Char)0x6c, /* [696] */ + (xdc_Char)0x69, /* [697] */ + (xdc_Char)0x67, /* [698] */ + (xdc_Char)0x6e, /* [699] */ + (xdc_Char)0x65, /* [700] */ + (xdc_Char)0x64, /* [701] */ + (xdc_Char)0x20, /* [702] */ + (xdc_Char)0x74, /* [703] */ + (xdc_Char)0x6f, /* [704] */ + (xdc_Char)0x20, /* [705] */ + (xdc_Char)0x73, /* [706] */ + (xdc_Char)0x69, /* [707] */ + (xdc_Char)0x7a, /* [708] */ + (xdc_Char)0x65, /* [709] */ + (xdc_Char)0x2e, /* [710] */ + (xdc_Char)0x0, /* [711] */ + (xdc_Char)0x41, /* [712] */ + (xdc_Char)0x5f, /* [713] */ + (xdc_Char)0x63, /* [714] */ + (xdc_Char)0x6c, /* [715] */ + (xdc_Char)0x6f, /* [716] */ + (xdc_Char)0x63, /* [717] */ + (xdc_Char)0x6b, /* [718] */ + (xdc_Char)0x44, /* [719] */ + (xdc_Char)0x69, /* [720] */ + (xdc_Char)0x73, /* [721] */ + (xdc_Char)0x61, /* [722] */ + (xdc_Char)0x62, /* [723] */ + (xdc_Char)0x6c, /* [724] */ + (xdc_Char)0x65, /* [725] */ + (xdc_Char)0x64, /* [726] */ + (xdc_Char)0x3a, /* [727] */ + (xdc_Char)0x20, /* [728] */ + (xdc_Char)0x43, /* [729] */ + (xdc_Char)0x61, /* [730] */ + (xdc_Char)0x6e, /* [731] */ + (xdc_Char)0x6e, /* [732] */ + (xdc_Char)0x6f, /* [733] */ + (xdc_Char)0x74, /* [734] */ + (xdc_Char)0x20, /* [735] */ + (xdc_Char)0x63, /* [736] */ + (xdc_Char)0x72, /* [737] */ + (xdc_Char)0x65, /* [738] */ + (xdc_Char)0x61, /* [739] */ + (xdc_Char)0x74, /* [740] */ + (xdc_Char)0x65, /* [741] */ + (xdc_Char)0x20, /* [742] */ + (xdc_Char)0x61, /* [743] */ + (xdc_Char)0x20, /* [744] */ + (xdc_Char)0x63, /* [745] */ + (xdc_Char)0x6c, /* [746] */ + (xdc_Char)0x6f, /* [747] */ + (xdc_Char)0x63, /* [748] */ + (xdc_Char)0x6b, /* [749] */ + (xdc_Char)0x20, /* [750] */ + (xdc_Char)0x69, /* [751] */ + (xdc_Char)0x6e, /* [752] */ + (xdc_Char)0x73, /* [753] */ + (xdc_Char)0x74, /* [754] */ + (xdc_Char)0x61, /* [755] */ + (xdc_Char)0x6e, /* [756] */ + (xdc_Char)0x63, /* [757] */ + (xdc_Char)0x65, /* [758] */ + (xdc_Char)0x20, /* [759] */ + (xdc_Char)0x77, /* [760] */ + (xdc_Char)0x68, /* [761] */ + (xdc_Char)0x65, /* [762] */ + (xdc_Char)0x6e, /* [763] */ + (xdc_Char)0x20, /* [764] */ + (xdc_Char)0x42, /* [765] */ + (xdc_Char)0x49, /* [766] */ + (xdc_Char)0x4f, /* [767] */ + (xdc_Char)0x53, /* [768] */ + (xdc_Char)0x2e, /* [769] */ + (xdc_Char)0x63, /* [770] */ + (xdc_Char)0x6c, /* [771] */ + (xdc_Char)0x6f, /* [772] */ + (xdc_Char)0x63, /* [773] */ + (xdc_Char)0x6b, /* [774] */ + (xdc_Char)0x45, /* [775] */ + (xdc_Char)0x6e, /* [776] */ + (xdc_Char)0x61, /* [777] */ + (xdc_Char)0x62, /* [778] */ + (xdc_Char)0x6c, /* [779] */ + (xdc_Char)0x65, /* [780] */ + (xdc_Char)0x64, /* [781] */ + (xdc_Char)0x20, /* [782] */ + (xdc_Char)0x69, /* [783] */ + (xdc_Char)0x73, /* [784] */ + (xdc_Char)0x20, /* [785] */ + (xdc_Char)0x66, /* [786] */ + (xdc_Char)0x61, /* [787] */ + (xdc_Char)0x6c, /* [788] */ + (xdc_Char)0x73, /* [789] */ + (xdc_Char)0x65, /* [790] */ + (xdc_Char)0x2e, /* [791] */ + (xdc_Char)0x0, /* [792] */ + (xdc_Char)0x41, /* [793] */ + (xdc_Char)0x5f, /* [794] */ + (xdc_Char)0x62, /* [795] */ + (xdc_Char)0x61, /* [796] */ + (xdc_Char)0x64, /* [797] */ + (xdc_Char)0x54, /* [798] */ + (xdc_Char)0x68, /* [799] */ + (xdc_Char)0x72, /* [800] */ + (xdc_Char)0x65, /* [801] */ + (xdc_Char)0x61, /* [802] */ + (xdc_Char)0x64, /* [803] */ + (xdc_Char)0x54, /* [804] */ + (xdc_Char)0x79, /* [805] */ + (xdc_Char)0x70, /* [806] */ + (xdc_Char)0x65, /* [807] */ + (xdc_Char)0x3a, /* [808] */ + (xdc_Char)0x20, /* [809] */ + (xdc_Char)0x43, /* [810] */ + (xdc_Char)0x61, /* [811] */ + (xdc_Char)0x6e, /* [812] */ + (xdc_Char)0x6e, /* [813] */ + (xdc_Char)0x6f, /* [814] */ + (xdc_Char)0x74, /* [815] */ + (xdc_Char)0x20, /* [816] */ + (xdc_Char)0x63, /* [817] */ + (xdc_Char)0x72, /* [818] */ + (xdc_Char)0x65, /* [819] */ + (xdc_Char)0x61, /* [820] */ + (xdc_Char)0x74, /* [821] */ + (xdc_Char)0x65, /* [822] */ + (xdc_Char)0x2f, /* [823] */ + (xdc_Char)0x64, /* [824] */ + (xdc_Char)0x65, /* [825] */ + (xdc_Char)0x6c, /* [826] */ + (xdc_Char)0x65, /* [827] */ + (xdc_Char)0x74, /* [828] */ + (xdc_Char)0x65, /* [829] */ + (xdc_Char)0x20, /* [830] */ + (xdc_Char)0x61, /* [831] */ + (xdc_Char)0x20, /* [832] */ + (xdc_Char)0x43, /* [833] */ + (xdc_Char)0x6c, /* [834] */ + (xdc_Char)0x6f, /* [835] */ + (xdc_Char)0x63, /* [836] */ + (xdc_Char)0x6b, /* [837] */ + (xdc_Char)0x20, /* [838] */ + (xdc_Char)0x66, /* [839] */ + (xdc_Char)0x72, /* [840] */ + (xdc_Char)0x6f, /* [841] */ + (xdc_Char)0x6d, /* [842] */ + (xdc_Char)0x20, /* [843] */ + (xdc_Char)0x48, /* [844] */ + (xdc_Char)0x77, /* [845] */ + (xdc_Char)0x69, /* [846] */ + (xdc_Char)0x20, /* [847] */ + (xdc_Char)0x6f, /* [848] */ + (xdc_Char)0x72, /* [849] */ + (xdc_Char)0x20, /* [850] */ + (xdc_Char)0x53, /* [851] */ + (xdc_Char)0x77, /* [852] */ + (xdc_Char)0x69, /* [853] */ + (xdc_Char)0x20, /* [854] */ + (xdc_Char)0x74, /* [855] */ + (xdc_Char)0x68, /* [856] */ + (xdc_Char)0x72, /* [857] */ + (xdc_Char)0x65, /* [858] */ + (xdc_Char)0x61, /* [859] */ + (xdc_Char)0x64, /* [860] */ + (xdc_Char)0x2e, /* [861] */ + (xdc_Char)0x0, /* [862] */ + (xdc_Char)0x41, /* [863] */ + (xdc_Char)0x5f, /* [864] */ + (xdc_Char)0x6e, /* [865] */ + (xdc_Char)0x75, /* [866] */ + (xdc_Char)0x6c, /* [867] */ + (xdc_Char)0x6c, /* [868] */ + (xdc_Char)0x45, /* [869] */ + (xdc_Char)0x76, /* [870] */ + (xdc_Char)0x65, /* [871] */ + (xdc_Char)0x6e, /* [872] */ + (xdc_Char)0x74, /* [873] */ + (xdc_Char)0x4d, /* [874] */ + (xdc_Char)0x61, /* [875] */ + (xdc_Char)0x73, /* [876] */ + (xdc_Char)0x6b, /* [877] */ + (xdc_Char)0x73, /* [878] */ + (xdc_Char)0x3a, /* [879] */ + (xdc_Char)0x20, /* [880] */ + (xdc_Char)0x6f, /* [881] */ + (xdc_Char)0x72, /* [882] */ + (xdc_Char)0x4d, /* [883] */ + (xdc_Char)0x61, /* [884] */ + (xdc_Char)0x73, /* [885] */ + (xdc_Char)0x6b, /* [886] */ + (xdc_Char)0x20, /* [887] */ + (xdc_Char)0x61, /* [888] */ + (xdc_Char)0x6e, /* [889] */ + (xdc_Char)0x64, /* [890] */ + (xdc_Char)0x20, /* [891] */ + (xdc_Char)0x61, /* [892] */ + (xdc_Char)0x6e, /* [893] */ + (xdc_Char)0x64, /* [894] */ + (xdc_Char)0x4d, /* [895] */ + (xdc_Char)0x61, /* [896] */ + (xdc_Char)0x73, /* [897] */ + (xdc_Char)0x6b, /* [898] */ + (xdc_Char)0x20, /* [899] */ + (xdc_Char)0x61, /* [900] */ + (xdc_Char)0x72, /* [901] */ + (xdc_Char)0x65, /* [902] */ + (xdc_Char)0x20, /* [903] */ + (xdc_Char)0x6e, /* [904] */ + (xdc_Char)0x75, /* [905] */ + (xdc_Char)0x6c, /* [906] */ + (xdc_Char)0x6c, /* [907] */ + (xdc_Char)0x2e, /* [908] */ + (xdc_Char)0x0, /* [909] */ + (xdc_Char)0x41, /* [910] */ + (xdc_Char)0x5f, /* [911] */ + (xdc_Char)0x6e, /* [912] */ + (xdc_Char)0x75, /* [913] */ + (xdc_Char)0x6c, /* [914] */ + (xdc_Char)0x6c, /* [915] */ + (xdc_Char)0x45, /* [916] */ + (xdc_Char)0x76, /* [917] */ + (xdc_Char)0x65, /* [918] */ + (xdc_Char)0x6e, /* [919] */ + (xdc_Char)0x74, /* [920] */ + (xdc_Char)0x49, /* [921] */ + (xdc_Char)0x64, /* [922] */ + (xdc_Char)0x3a, /* [923] */ + (xdc_Char)0x20, /* [924] */ + (xdc_Char)0x70, /* [925] */ + (xdc_Char)0x6f, /* [926] */ + (xdc_Char)0x73, /* [927] */ + (xdc_Char)0x74, /* [928] */ + (xdc_Char)0x65, /* [929] */ + (xdc_Char)0x64, /* [930] */ + (xdc_Char)0x20, /* [931] */ + (xdc_Char)0x65, /* [932] */ + (xdc_Char)0x76, /* [933] */ + (xdc_Char)0x65, /* [934] */ + (xdc_Char)0x6e, /* [935] */ + (xdc_Char)0x74, /* [936] */ + (xdc_Char)0x49, /* [937] */ + (xdc_Char)0x64, /* [938] */ + (xdc_Char)0x20, /* [939] */ + (xdc_Char)0x69, /* [940] */ + (xdc_Char)0x73, /* [941] */ + (xdc_Char)0x20, /* [942] */ + (xdc_Char)0x6e, /* [943] */ + (xdc_Char)0x75, /* [944] */ + (xdc_Char)0x6c, /* [945] */ + (xdc_Char)0x6c, /* [946] */ + (xdc_Char)0x2e, /* [947] */ + (xdc_Char)0x0, /* [948] */ + (xdc_Char)0x41, /* [949] */ + (xdc_Char)0x5f, /* [950] */ + (xdc_Char)0x65, /* [951] */ + (xdc_Char)0x76, /* [952] */ + (xdc_Char)0x65, /* [953] */ + (xdc_Char)0x6e, /* [954] */ + (xdc_Char)0x74, /* [955] */ + (xdc_Char)0x49, /* [956] */ + (xdc_Char)0x6e, /* [957] */ + (xdc_Char)0x55, /* [958] */ + (xdc_Char)0x73, /* [959] */ + (xdc_Char)0x65, /* [960] */ + (xdc_Char)0x3a, /* [961] */ + (xdc_Char)0x20, /* [962] */ + (xdc_Char)0x45, /* [963] */ + (xdc_Char)0x76, /* [964] */ + (xdc_Char)0x65, /* [965] */ + (xdc_Char)0x6e, /* [966] */ + (xdc_Char)0x74, /* [967] */ + (xdc_Char)0x20, /* [968] */ + (xdc_Char)0x6f, /* [969] */ + (xdc_Char)0x62, /* [970] */ + (xdc_Char)0x6a, /* [971] */ + (xdc_Char)0x65, /* [972] */ + (xdc_Char)0x63, /* [973] */ + (xdc_Char)0x74, /* [974] */ + (xdc_Char)0x20, /* [975] */ + (xdc_Char)0x61, /* [976] */ + (xdc_Char)0x6c, /* [977] */ + (xdc_Char)0x72, /* [978] */ + (xdc_Char)0x65, /* [979] */ + (xdc_Char)0x61, /* [980] */ + (xdc_Char)0x64, /* [981] */ + (xdc_Char)0x79, /* [982] */ + (xdc_Char)0x20, /* [983] */ + (xdc_Char)0x69, /* [984] */ + (xdc_Char)0x6e, /* [985] */ + (xdc_Char)0x20, /* [986] */ + (xdc_Char)0x75, /* [987] */ + (xdc_Char)0x73, /* [988] */ + (xdc_Char)0x65, /* [989] */ + (xdc_Char)0x2e, /* [990] */ + (xdc_Char)0x0, /* [991] */ + (xdc_Char)0x41, /* [992] */ + (xdc_Char)0x5f, /* [993] */ + (xdc_Char)0x62, /* [994] */ + (xdc_Char)0x61, /* [995] */ + (xdc_Char)0x64, /* [996] */ + (xdc_Char)0x43, /* [997] */ + (xdc_Char)0x6f, /* [998] */ + (xdc_Char)0x6e, /* [999] */ + (xdc_Char)0x74, /* [1000] */ + (xdc_Char)0x65, /* [1001] */ + (xdc_Char)0x78, /* [1002] */ + (xdc_Char)0x74, /* [1003] */ + (xdc_Char)0x3a, /* [1004] */ + (xdc_Char)0x20, /* [1005] */ + (xdc_Char)0x62, /* [1006] */ + (xdc_Char)0x61, /* [1007] */ + (xdc_Char)0x64, /* [1008] */ + (xdc_Char)0x20, /* [1009] */ + (xdc_Char)0x63, /* [1010] */ + (xdc_Char)0x61, /* [1011] */ + (xdc_Char)0x6c, /* [1012] */ + (xdc_Char)0x6c, /* [1013] */ + (xdc_Char)0x69, /* [1014] */ + (xdc_Char)0x6e, /* [1015] */ + (xdc_Char)0x67, /* [1016] */ + (xdc_Char)0x20, /* [1017] */ + (xdc_Char)0x63, /* [1018] */ + (xdc_Char)0x6f, /* [1019] */ + (xdc_Char)0x6e, /* [1020] */ + (xdc_Char)0x74, /* [1021] */ + (xdc_Char)0x65, /* [1022] */ + (xdc_Char)0x78, /* [1023] */ + (xdc_Char)0x74, /* [1024] */ + (xdc_Char)0x2e, /* [1025] */ + (xdc_Char)0x20, /* [1026] */ + (xdc_Char)0x4d, /* [1027] */ + (xdc_Char)0x75, /* [1028] */ + (xdc_Char)0x73, /* [1029] */ + (xdc_Char)0x74, /* [1030] */ + (xdc_Char)0x20, /* [1031] */ + (xdc_Char)0x62, /* [1032] */ + (xdc_Char)0x65, /* [1033] */ + (xdc_Char)0x20, /* [1034] */ + (xdc_Char)0x63, /* [1035] */ + (xdc_Char)0x61, /* [1036] */ + (xdc_Char)0x6c, /* [1037] */ + (xdc_Char)0x6c, /* [1038] */ + (xdc_Char)0x65, /* [1039] */ + (xdc_Char)0x64, /* [1040] */ + (xdc_Char)0x20, /* [1041] */ + (xdc_Char)0x66, /* [1042] */ + (xdc_Char)0x72, /* [1043] */ + (xdc_Char)0x6f, /* [1044] */ + (xdc_Char)0x6d, /* [1045] */ + (xdc_Char)0x20, /* [1046] */ + (xdc_Char)0x61, /* [1047] */ + (xdc_Char)0x20, /* [1048] */ + (xdc_Char)0x54, /* [1049] */ + (xdc_Char)0x61, /* [1050] */ + (xdc_Char)0x73, /* [1051] */ + (xdc_Char)0x6b, /* [1052] */ + (xdc_Char)0x2e, /* [1053] */ + (xdc_Char)0x0, /* [1054] */ + (xdc_Char)0x41, /* [1055] */ + (xdc_Char)0x5f, /* [1056] */ + (xdc_Char)0x70, /* [1057] */ + (xdc_Char)0x65, /* [1058] */ + (xdc_Char)0x6e, /* [1059] */ + (xdc_Char)0x64, /* [1060] */ + (xdc_Char)0x54, /* [1061] */ + (xdc_Char)0x61, /* [1062] */ + (xdc_Char)0x73, /* [1063] */ + (xdc_Char)0x6b, /* [1064] */ + (xdc_Char)0x44, /* [1065] */ + (xdc_Char)0x69, /* [1066] */ + (xdc_Char)0x73, /* [1067] */ + (xdc_Char)0x61, /* [1068] */ + (xdc_Char)0x62, /* [1069] */ + (xdc_Char)0x6c, /* [1070] */ + (xdc_Char)0x65, /* [1071] */ + (xdc_Char)0x64, /* [1072] */ + (xdc_Char)0x3a, /* [1073] */ + (xdc_Char)0x20, /* [1074] */ + (xdc_Char)0x43, /* [1075] */ + (xdc_Char)0x61, /* [1076] */ + (xdc_Char)0x6e, /* [1077] */ + (xdc_Char)0x6e, /* [1078] */ + (xdc_Char)0x6f, /* [1079] */ + (xdc_Char)0x74, /* [1080] */ + (xdc_Char)0x20, /* [1081] */ + (xdc_Char)0x63, /* [1082] */ + (xdc_Char)0x61, /* [1083] */ + (xdc_Char)0x6c, /* [1084] */ + (xdc_Char)0x6c, /* [1085] */ + (xdc_Char)0x20, /* [1086] */ + (xdc_Char)0x45, /* [1087] */ + (xdc_Char)0x76, /* [1088] */ + (xdc_Char)0x65, /* [1089] */ + (xdc_Char)0x6e, /* [1090] */ + (xdc_Char)0x74, /* [1091] */ + (xdc_Char)0x5f, /* [1092] */ + (xdc_Char)0x70, /* [1093] */ + (xdc_Char)0x65, /* [1094] */ + (xdc_Char)0x6e, /* [1095] */ + (xdc_Char)0x64, /* [1096] */ + (xdc_Char)0x28, /* [1097] */ + (xdc_Char)0x29, /* [1098] */ + (xdc_Char)0x20, /* [1099] */ + (xdc_Char)0x77, /* [1100] */ + (xdc_Char)0x68, /* [1101] */ + (xdc_Char)0x69, /* [1102] */ + (xdc_Char)0x6c, /* [1103] */ + (xdc_Char)0x65, /* [1104] */ + (xdc_Char)0x20, /* [1105] */ + (xdc_Char)0x74, /* [1106] */ + (xdc_Char)0x68, /* [1107] */ + (xdc_Char)0x65, /* [1108] */ + (xdc_Char)0x20, /* [1109] */ + (xdc_Char)0x54, /* [1110] */ + (xdc_Char)0x61, /* [1111] */ + (xdc_Char)0x73, /* [1112] */ + (xdc_Char)0x6b, /* [1113] */ + (xdc_Char)0x20, /* [1114] */ + (xdc_Char)0x6f, /* [1115] */ + (xdc_Char)0x72, /* [1116] */ + (xdc_Char)0x20, /* [1117] */ + (xdc_Char)0x53, /* [1118] */ + (xdc_Char)0x77, /* [1119] */ + (xdc_Char)0x69, /* [1120] */ + (xdc_Char)0x20, /* [1121] */ + (xdc_Char)0x73, /* [1122] */ + (xdc_Char)0x63, /* [1123] */ + (xdc_Char)0x68, /* [1124] */ + (xdc_Char)0x65, /* [1125] */ + (xdc_Char)0x64, /* [1126] */ + (xdc_Char)0x75, /* [1127] */ + (xdc_Char)0x6c, /* [1128] */ + (xdc_Char)0x65, /* [1129] */ + (xdc_Char)0x72, /* [1130] */ + (xdc_Char)0x20, /* [1131] */ + (xdc_Char)0x69, /* [1132] */ + (xdc_Char)0x73, /* [1133] */ + (xdc_Char)0x20, /* [1134] */ + (xdc_Char)0x64, /* [1135] */ + (xdc_Char)0x69, /* [1136] */ + (xdc_Char)0x73, /* [1137] */ + (xdc_Char)0x61, /* [1138] */ + (xdc_Char)0x62, /* [1139] */ + (xdc_Char)0x6c, /* [1140] */ + (xdc_Char)0x65, /* [1141] */ + (xdc_Char)0x64, /* [1142] */ + (xdc_Char)0x2e, /* [1143] */ + (xdc_Char)0x0, /* [1144] */ + (xdc_Char)0x4d, /* [1145] */ + (xdc_Char)0x61, /* [1146] */ + (xdc_Char)0x69, /* [1147] */ + (xdc_Char)0x6c, /* [1148] */ + (xdc_Char)0x62, /* [1149] */ + (xdc_Char)0x6f, /* [1150] */ + (xdc_Char)0x78, /* [1151] */ + (xdc_Char)0x5f, /* [1152] */ + (xdc_Char)0x63, /* [1153] */ + (xdc_Char)0x72, /* [1154] */ + (xdc_Char)0x65, /* [1155] */ + (xdc_Char)0x61, /* [1156] */ + (xdc_Char)0x74, /* [1157] */ + (xdc_Char)0x65, /* [1158] */ + (xdc_Char)0x27, /* [1159] */ + (xdc_Char)0x73, /* [1160] */ + (xdc_Char)0x20, /* [1161] */ + (xdc_Char)0x62, /* [1162] */ + (xdc_Char)0x75, /* [1163] */ + (xdc_Char)0x66, /* [1164] */ + (xdc_Char)0x53, /* [1165] */ + (xdc_Char)0x69, /* [1166] */ + (xdc_Char)0x7a, /* [1167] */ + (xdc_Char)0x65, /* [1168] */ + (xdc_Char)0x20, /* [1169] */ + (xdc_Char)0x70, /* [1170] */ + (xdc_Char)0x61, /* [1171] */ + (xdc_Char)0x72, /* [1172] */ + (xdc_Char)0x61, /* [1173] */ + (xdc_Char)0x6d, /* [1174] */ + (xdc_Char)0x65, /* [1175] */ + (xdc_Char)0x74, /* [1176] */ + (xdc_Char)0x65, /* [1177] */ + (xdc_Char)0x72, /* [1178] */ + (xdc_Char)0x20, /* [1179] */ + (xdc_Char)0x69, /* [1180] */ + (xdc_Char)0x73, /* [1181] */ + (xdc_Char)0x20, /* [1182] */ + (xdc_Char)0x69, /* [1183] */ + (xdc_Char)0x6e, /* [1184] */ + (xdc_Char)0x76, /* [1185] */ + (xdc_Char)0x61, /* [1186] */ + (xdc_Char)0x6c, /* [1187] */ + (xdc_Char)0x69, /* [1188] */ + (xdc_Char)0x64, /* [1189] */ + (xdc_Char)0x20, /* [1190] */ + (xdc_Char)0x28, /* [1191] */ + (xdc_Char)0x74, /* [1192] */ + (xdc_Char)0x6f, /* [1193] */ + (xdc_Char)0x6f, /* [1194] */ + (xdc_Char)0x20, /* [1195] */ + (xdc_Char)0x73, /* [1196] */ + (xdc_Char)0x6d, /* [1197] */ + (xdc_Char)0x61, /* [1198] */ + (xdc_Char)0x6c, /* [1199] */ + (xdc_Char)0x6c, /* [1200] */ + (xdc_Char)0x29, /* [1201] */ + (xdc_Char)0x0, /* [1202] */ + (xdc_Char)0x41, /* [1203] */ + (xdc_Char)0x5f, /* [1204] */ + (xdc_Char)0x6e, /* [1205] */ + (xdc_Char)0x6f, /* [1206] */ + (xdc_Char)0x45, /* [1207] */ + (xdc_Char)0x76, /* [1208] */ + (xdc_Char)0x65, /* [1209] */ + (xdc_Char)0x6e, /* [1210] */ + (xdc_Char)0x74, /* [1211] */ + (xdc_Char)0x73, /* [1212] */ + (xdc_Char)0x3a, /* [1213] */ + (xdc_Char)0x20, /* [1214] */ + (xdc_Char)0x54, /* [1215] */ + (xdc_Char)0x68, /* [1216] */ + (xdc_Char)0x65, /* [1217] */ + (xdc_Char)0x20, /* [1218] */ + (xdc_Char)0x45, /* [1219] */ + (xdc_Char)0x76, /* [1220] */ + (xdc_Char)0x65, /* [1221] */ + (xdc_Char)0x6e, /* [1222] */ + (xdc_Char)0x74, /* [1223] */ + (xdc_Char)0x2e, /* [1224] */ + (xdc_Char)0x73, /* [1225] */ + (xdc_Char)0x75, /* [1226] */ + (xdc_Char)0x70, /* [1227] */ + (xdc_Char)0x70, /* [1228] */ + (xdc_Char)0x6f, /* [1229] */ + (xdc_Char)0x72, /* [1230] */ + (xdc_Char)0x74, /* [1231] */ + (xdc_Char)0x73, /* [1232] */ + (xdc_Char)0x45, /* [1233] */ + (xdc_Char)0x76, /* [1234] */ + (xdc_Char)0x65, /* [1235] */ + (xdc_Char)0x6e, /* [1236] */ + (xdc_Char)0x74, /* [1237] */ + (xdc_Char)0x73, /* [1238] */ + (xdc_Char)0x20, /* [1239] */ + (xdc_Char)0x66, /* [1240] */ + (xdc_Char)0x6c, /* [1241] */ + (xdc_Char)0x61, /* [1242] */ + (xdc_Char)0x67, /* [1243] */ + (xdc_Char)0x20, /* [1244] */ + (xdc_Char)0x69, /* [1245] */ + (xdc_Char)0x73, /* [1246] */ + (xdc_Char)0x20, /* [1247] */ + (xdc_Char)0x64, /* [1248] */ + (xdc_Char)0x69, /* [1249] */ + (xdc_Char)0x73, /* [1250] */ + (xdc_Char)0x61, /* [1251] */ + (xdc_Char)0x62, /* [1252] */ + (xdc_Char)0x6c, /* [1253] */ + (xdc_Char)0x65, /* [1254] */ + (xdc_Char)0x64, /* [1255] */ + (xdc_Char)0x2e, /* [1256] */ + (xdc_Char)0x0, /* [1257] */ + (xdc_Char)0x41, /* [1258] */ + (xdc_Char)0x5f, /* [1259] */ + (xdc_Char)0x69, /* [1260] */ + (xdc_Char)0x6e, /* [1261] */ + (xdc_Char)0x76, /* [1262] */ + (xdc_Char)0x54, /* [1263] */ + (xdc_Char)0x69, /* [1264] */ + (xdc_Char)0x6d, /* [1265] */ + (xdc_Char)0x65, /* [1266] */ + (xdc_Char)0x6f, /* [1267] */ + (xdc_Char)0x75, /* [1268] */ + (xdc_Char)0x74, /* [1269] */ + (xdc_Char)0x3a, /* [1270] */ + (xdc_Char)0x20, /* [1271] */ + (xdc_Char)0x43, /* [1272] */ + (xdc_Char)0x61, /* [1273] */ + (xdc_Char)0x6e, /* [1274] */ + (xdc_Char)0x27, /* [1275] */ + (xdc_Char)0x74, /* [1276] */ + (xdc_Char)0x20, /* [1277] */ + (xdc_Char)0x75, /* [1278] */ + (xdc_Char)0x73, /* [1279] */ + (xdc_Char)0x65, /* [1280] */ + (xdc_Char)0x20, /* [1281] */ + (xdc_Char)0x42, /* [1282] */ + (xdc_Char)0x49, /* [1283] */ + (xdc_Char)0x4f, /* [1284] */ + (xdc_Char)0x53, /* [1285] */ + (xdc_Char)0x5f, /* [1286] */ + (xdc_Char)0x45, /* [1287] */ + (xdc_Char)0x56, /* [1288] */ + (xdc_Char)0x45, /* [1289] */ + (xdc_Char)0x4e, /* [1290] */ + (xdc_Char)0x54, /* [1291] */ + (xdc_Char)0x5f, /* [1292] */ + (xdc_Char)0x41, /* [1293] */ + (xdc_Char)0x43, /* [1294] */ + (xdc_Char)0x51, /* [1295] */ + (xdc_Char)0x55, /* [1296] */ + (xdc_Char)0x49, /* [1297] */ + (xdc_Char)0x52, /* [1298] */ + (xdc_Char)0x45, /* [1299] */ + (xdc_Char)0x44, /* [1300] */ + (xdc_Char)0x20, /* [1301] */ + (xdc_Char)0x77, /* [1302] */ + (xdc_Char)0x69, /* [1303] */ + (xdc_Char)0x74, /* [1304] */ + (xdc_Char)0x68, /* [1305] */ + (xdc_Char)0x20, /* [1306] */ + (xdc_Char)0x74, /* [1307] */ + (xdc_Char)0x68, /* [1308] */ + (xdc_Char)0x69, /* [1309] */ + (xdc_Char)0x73, /* [1310] */ + (xdc_Char)0x20, /* [1311] */ + (xdc_Char)0x53, /* [1312] */ + (xdc_Char)0x65, /* [1313] */ + (xdc_Char)0x6d, /* [1314] */ + (xdc_Char)0x61, /* [1315] */ + (xdc_Char)0x70, /* [1316] */ + (xdc_Char)0x68, /* [1317] */ + (xdc_Char)0x6f, /* [1318] */ + (xdc_Char)0x72, /* [1319] */ + (xdc_Char)0x65, /* [1320] */ + (xdc_Char)0x2e, /* [1321] */ + (xdc_Char)0x0, /* [1322] */ + (xdc_Char)0x41, /* [1323] */ + (xdc_Char)0x5f, /* [1324] */ + (xdc_Char)0x6f, /* [1325] */ + (xdc_Char)0x76, /* [1326] */ + (xdc_Char)0x65, /* [1327] */ + (xdc_Char)0x72, /* [1328] */ + (xdc_Char)0x66, /* [1329] */ + (xdc_Char)0x6c, /* [1330] */ + (xdc_Char)0x6f, /* [1331] */ + (xdc_Char)0x77, /* [1332] */ + (xdc_Char)0x3a, /* [1333] */ + (xdc_Char)0x20, /* [1334] */ + (xdc_Char)0x43, /* [1335] */ + (xdc_Char)0x6f, /* [1336] */ + (xdc_Char)0x75, /* [1337] */ + (xdc_Char)0x6e, /* [1338] */ + (xdc_Char)0x74, /* [1339] */ + (xdc_Char)0x20, /* [1340] */ + (xdc_Char)0x68, /* [1341] */ + (xdc_Char)0x61, /* [1342] */ + (xdc_Char)0x73, /* [1343] */ + (xdc_Char)0x20, /* [1344] */ + (xdc_Char)0x65, /* [1345] */ + (xdc_Char)0x78, /* [1346] */ + (xdc_Char)0x63, /* [1347] */ + (xdc_Char)0x65, /* [1348] */ + (xdc_Char)0x65, /* [1349] */ + (xdc_Char)0x64, /* [1350] */ + (xdc_Char)0x65, /* [1351] */ + (xdc_Char)0x64, /* [1352] */ + (xdc_Char)0x20, /* [1353] */ + (xdc_Char)0x36, /* [1354] */ + (xdc_Char)0x35, /* [1355] */ + (xdc_Char)0x35, /* [1356] */ + (xdc_Char)0x33, /* [1357] */ + (xdc_Char)0x35, /* [1358] */ + (xdc_Char)0x20, /* [1359] */ + (xdc_Char)0x61, /* [1360] */ + (xdc_Char)0x6e, /* [1361] */ + (xdc_Char)0x64, /* [1362] */ + (xdc_Char)0x20, /* [1363] */ + (xdc_Char)0x72, /* [1364] */ + (xdc_Char)0x6f, /* [1365] */ + (xdc_Char)0x6c, /* [1366] */ + (xdc_Char)0x6c, /* [1367] */ + (xdc_Char)0x65, /* [1368] */ + (xdc_Char)0x64, /* [1369] */ + (xdc_Char)0x20, /* [1370] */ + (xdc_Char)0x6f, /* [1371] */ + (xdc_Char)0x76, /* [1372] */ + (xdc_Char)0x65, /* [1373] */ + (xdc_Char)0x72, /* [1374] */ + (xdc_Char)0x2e, /* [1375] */ + (xdc_Char)0x0, /* [1376] */ + (xdc_Char)0x41, /* [1377] */ + (xdc_Char)0x5f, /* [1378] */ + (xdc_Char)0x70, /* [1379] */ + (xdc_Char)0x65, /* [1380] */ + (xdc_Char)0x6e, /* [1381] */ + (xdc_Char)0x64, /* [1382] */ + (xdc_Char)0x54, /* [1383] */ + (xdc_Char)0x61, /* [1384] */ + (xdc_Char)0x73, /* [1385] */ + (xdc_Char)0x6b, /* [1386] */ + (xdc_Char)0x44, /* [1387] */ + (xdc_Char)0x69, /* [1388] */ + (xdc_Char)0x73, /* [1389] */ + (xdc_Char)0x61, /* [1390] */ + (xdc_Char)0x62, /* [1391] */ + (xdc_Char)0x6c, /* [1392] */ + (xdc_Char)0x65, /* [1393] */ + (xdc_Char)0x64, /* [1394] */ + (xdc_Char)0x3a, /* [1395] */ + (xdc_Char)0x20, /* [1396] */ + (xdc_Char)0x43, /* [1397] */ + (xdc_Char)0x61, /* [1398] */ + (xdc_Char)0x6e, /* [1399] */ + (xdc_Char)0x6e, /* [1400] */ + (xdc_Char)0x6f, /* [1401] */ + (xdc_Char)0x74, /* [1402] */ + (xdc_Char)0x20, /* [1403] */ + (xdc_Char)0x63, /* [1404] */ + (xdc_Char)0x61, /* [1405] */ + (xdc_Char)0x6c, /* [1406] */ + (xdc_Char)0x6c, /* [1407] */ + (xdc_Char)0x20, /* [1408] */ + (xdc_Char)0x53, /* [1409] */ + (xdc_Char)0x65, /* [1410] */ + (xdc_Char)0x6d, /* [1411] */ + (xdc_Char)0x61, /* [1412] */ + (xdc_Char)0x70, /* [1413] */ + (xdc_Char)0x68, /* [1414] */ + (xdc_Char)0x6f, /* [1415] */ + (xdc_Char)0x72, /* [1416] */ + (xdc_Char)0x65, /* [1417] */ + (xdc_Char)0x5f, /* [1418] */ + (xdc_Char)0x70, /* [1419] */ + (xdc_Char)0x65, /* [1420] */ + (xdc_Char)0x6e, /* [1421] */ + (xdc_Char)0x64, /* [1422] */ + (xdc_Char)0x28, /* [1423] */ + (xdc_Char)0x29, /* [1424] */ + (xdc_Char)0x20, /* [1425] */ + (xdc_Char)0x77, /* [1426] */ + (xdc_Char)0x68, /* [1427] */ + (xdc_Char)0x69, /* [1428] */ + (xdc_Char)0x6c, /* [1429] */ + (xdc_Char)0x65, /* [1430] */ + (xdc_Char)0x20, /* [1431] */ + (xdc_Char)0x74, /* [1432] */ + (xdc_Char)0x68, /* [1433] */ + (xdc_Char)0x65, /* [1434] */ + (xdc_Char)0x20, /* [1435] */ + (xdc_Char)0x54, /* [1436] */ + (xdc_Char)0x61, /* [1437] */ + (xdc_Char)0x73, /* [1438] */ + (xdc_Char)0x6b, /* [1439] */ + (xdc_Char)0x20, /* [1440] */ + (xdc_Char)0x6f, /* [1441] */ + (xdc_Char)0x72, /* [1442] */ + (xdc_Char)0x20, /* [1443] */ + (xdc_Char)0x53, /* [1444] */ + (xdc_Char)0x77, /* [1445] */ + (xdc_Char)0x69, /* [1446] */ + (xdc_Char)0x20, /* [1447] */ + (xdc_Char)0x73, /* [1448] */ + (xdc_Char)0x63, /* [1449] */ + (xdc_Char)0x68, /* [1450] */ + (xdc_Char)0x65, /* [1451] */ + (xdc_Char)0x64, /* [1452] */ + (xdc_Char)0x75, /* [1453] */ + (xdc_Char)0x6c, /* [1454] */ + (xdc_Char)0x65, /* [1455] */ + (xdc_Char)0x72, /* [1456] */ + (xdc_Char)0x20, /* [1457] */ + (xdc_Char)0x69, /* [1458] */ + (xdc_Char)0x73, /* [1459] */ + (xdc_Char)0x20, /* [1460] */ + (xdc_Char)0x64, /* [1461] */ + (xdc_Char)0x69, /* [1462] */ + (xdc_Char)0x73, /* [1463] */ + (xdc_Char)0x61, /* [1464] */ + (xdc_Char)0x62, /* [1465] */ + (xdc_Char)0x6c, /* [1466] */ + (xdc_Char)0x65, /* [1467] */ + (xdc_Char)0x64, /* [1468] */ + (xdc_Char)0x2e, /* [1469] */ + (xdc_Char)0x0, /* [1470] */ + (xdc_Char)0x41, /* [1471] */ + (xdc_Char)0x5f, /* [1472] */ + (xdc_Char)0x73, /* [1473] */ + (xdc_Char)0x77, /* [1474] */ + (xdc_Char)0x69, /* [1475] */ + (xdc_Char)0x44, /* [1476] */ + (xdc_Char)0x69, /* [1477] */ + (xdc_Char)0x73, /* [1478] */ + (xdc_Char)0x61, /* [1479] */ + (xdc_Char)0x62, /* [1480] */ + (xdc_Char)0x6c, /* [1481] */ + (xdc_Char)0x65, /* [1482] */ + (xdc_Char)0x64, /* [1483] */ + (xdc_Char)0x3a, /* [1484] */ + (xdc_Char)0x20, /* [1485] */ + (xdc_Char)0x43, /* [1486] */ + (xdc_Char)0x61, /* [1487] */ + (xdc_Char)0x6e, /* [1488] */ + (xdc_Char)0x6e, /* [1489] */ + (xdc_Char)0x6f, /* [1490] */ + (xdc_Char)0x74, /* [1491] */ + (xdc_Char)0x20, /* [1492] */ + (xdc_Char)0x63, /* [1493] */ + (xdc_Char)0x72, /* [1494] */ + (xdc_Char)0x65, /* [1495] */ + (xdc_Char)0x61, /* [1496] */ + (xdc_Char)0x74, /* [1497] */ + (xdc_Char)0x65, /* [1498] */ + (xdc_Char)0x20, /* [1499] */ + (xdc_Char)0x61, /* [1500] */ + (xdc_Char)0x20, /* [1501] */ + (xdc_Char)0x53, /* [1502] */ + (xdc_Char)0x77, /* [1503] */ + (xdc_Char)0x69, /* [1504] */ + (xdc_Char)0x20, /* [1505] */ + (xdc_Char)0x77, /* [1506] */ + (xdc_Char)0x68, /* [1507] */ + (xdc_Char)0x65, /* [1508] */ + (xdc_Char)0x6e, /* [1509] */ + (xdc_Char)0x20, /* [1510] */ + (xdc_Char)0x53, /* [1511] */ + (xdc_Char)0x77, /* [1512] */ + (xdc_Char)0x69, /* [1513] */ + (xdc_Char)0x20, /* [1514] */ + (xdc_Char)0x69, /* [1515] */ + (xdc_Char)0x73, /* [1516] */ + (xdc_Char)0x20, /* [1517] */ + (xdc_Char)0x64, /* [1518] */ + (xdc_Char)0x69, /* [1519] */ + (xdc_Char)0x73, /* [1520] */ + (xdc_Char)0x61, /* [1521] */ + (xdc_Char)0x62, /* [1522] */ + (xdc_Char)0x6c, /* [1523] */ + (xdc_Char)0x65, /* [1524] */ + (xdc_Char)0x64, /* [1525] */ + (xdc_Char)0x2e, /* [1526] */ + (xdc_Char)0x0, /* [1527] */ + (xdc_Char)0x41, /* [1528] */ + (xdc_Char)0x5f, /* [1529] */ + (xdc_Char)0x62, /* [1530] */ + (xdc_Char)0x61, /* [1531] */ + (xdc_Char)0x64, /* [1532] */ + (xdc_Char)0x50, /* [1533] */ + (xdc_Char)0x72, /* [1534] */ + (xdc_Char)0x69, /* [1535] */ + (xdc_Char)0x6f, /* [1536] */ + (xdc_Char)0x72, /* [1537] */ + (xdc_Char)0x69, /* [1538] */ + (xdc_Char)0x74, /* [1539] */ + (xdc_Char)0x79, /* [1540] */ + (xdc_Char)0x3a, /* [1541] */ + (xdc_Char)0x20, /* [1542] */ + (xdc_Char)0x41, /* [1543] */ + (xdc_Char)0x6e, /* [1544] */ + (xdc_Char)0x20, /* [1545] */ + (xdc_Char)0x69, /* [1546] */ + (xdc_Char)0x6e, /* [1547] */ + (xdc_Char)0x76, /* [1548] */ + (xdc_Char)0x61, /* [1549] */ + (xdc_Char)0x6c, /* [1550] */ + (xdc_Char)0x69, /* [1551] */ + (xdc_Char)0x64, /* [1552] */ + (xdc_Char)0x20, /* [1553] */ + (xdc_Char)0x53, /* [1554] */ + (xdc_Char)0x77, /* [1555] */ + (xdc_Char)0x69, /* [1556] */ + (xdc_Char)0x20, /* [1557] */ + (xdc_Char)0x70, /* [1558] */ + (xdc_Char)0x72, /* [1559] */ + (xdc_Char)0x69, /* [1560] */ + (xdc_Char)0x6f, /* [1561] */ + (xdc_Char)0x72, /* [1562] */ + (xdc_Char)0x69, /* [1563] */ + (xdc_Char)0x74, /* [1564] */ + (xdc_Char)0x79, /* [1565] */ + (xdc_Char)0x20, /* [1566] */ + (xdc_Char)0x77, /* [1567] */ + (xdc_Char)0x61, /* [1568] */ + (xdc_Char)0x73, /* [1569] */ + (xdc_Char)0x20, /* [1570] */ + (xdc_Char)0x75, /* [1571] */ + (xdc_Char)0x73, /* [1572] */ + (xdc_Char)0x65, /* [1573] */ + (xdc_Char)0x64, /* [1574] */ + (xdc_Char)0x2e, /* [1575] */ + (xdc_Char)0x0, /* [1576] */ + (xdc_Char)0x41, /* [1577] */ + (xdc_Char)0x5f, /* [1578] */ + (xdc_Char)0x62, /* [1579] */ + (xdc_Char)0x61, /* [1580] */ + (xdc_Char)0x64, /* [1581] */ + (xdc_Char)0x54, /* [1582] */ + (xdc_Char)0x68, /* [1583] */ + (xdc_Char)0x72, /* [1584] */ + (xdc_Char)0x65, /* [1585] */ + (xdc_Char)0x61, /* [1586] */ + (xdc_Char)0x64, /* [1587] */ + (xdc_Char)0x54, /* [1588] */ + (xdc_Char)0x79, /* [1589] */ + (xdc_Char)0x70, /* [1590] */ + (xdc_Char)0x65, /* [1591] */ + (xdc_Char)0x3a, /* [1592] */ + (xdc_Char)0x20, /* [1593] */ + (xdc_Char)0x43, /* [1594] */ + (xdc_Char)0x61, /* [1595] */ + (xdc_Char)0x6e, /* [1596] */ + (xdc_Char)0x6e, /* [1597] */ + (xdc_Char)0x6f, /* [1598] */ + (xdc_Char)0x74, /* [1599] */ + (xdc_Char)0x20, /* [1600] */ + (xdc_Char)0x63, /* [1601] */ + (xdc_Char)0x72, /* [1602] */ + (xdc_Char)0x65, /* [1603] */ + (xdc_Char)0x61, /* [1604] */ + (xdc_Char)0x74, /* [1605] */ + (xdc_Char)0x65, /* [1606] */ + (xdc_Char)0x2f, /* [1607] */ + (xdc_Char)0x64, /* [1608] */ + (xdc_Char)0x65, /* [1609] */ + (xdc_Char)0x6c, /* [1610] */ + (xdc_Char)0x65, /* [1611] */ + (xdc_Char)0x74, /* [1612] */ + (xdc_Char)0x65, /* [1613] */ + (xdc_Char)0x20, /* [1614] */ + (xdc_Char)0x61, /* [1615] */ + (xdc_Char)0x20, /* [1616] */ + (xdc_Char)0x74, /* [1617] */ + (xdc_Char)0x61, /* [1618] */ + (xdc_Char)0x73, /* [1619] */ + (xdc_Char)0x6b, /* [1620] */ + (xdc_Char)0x20, /* [1621] */ + (xdc_Char)0x66, /* [1622] */ + (xdc_Char)0x72, /* [1623] */ + (xdc_Char)0x6f, /* [1624] */ + (xdc_Char)0x6d, /* [1625] */ + (xdc_Char)0x20, /* [1626] */ + (xdc_Char)0x48, /* [1627] */ + (xdc_Char)0x77, /* [1628] */ + (xdc_Char)0x69, /* [1629] */ + (xdc_Char)0x20, /* [1630] */ + (xdc_Char)0x6f, /* [1631] */ + (xdc_Char)0x72, /* [1632] */ + (xdc_Char)0x20, /* [1633] */ + (xdc_Char)0x53, /* [1634] */ + (xdc_Char)0x77, /* [1635] */ + (xdc_Char)0x69, /* [1636] */ + (xdc_Char)0x20, /* [1637] */ + (xdc_Char)0x74, /* [1638] */ + (xdc_Char)0x68, /* [1639] */ + (xdc_Char)0x72, /* [1640] */ + (xdc_Char)0x65, /* [1641] */ + (xdc_Char)0x61, /* [1642] */ + (xdc_Char)0x64, /* [1643] */ + (xdc_Char)0x2e, /* [1644] */ + (xdc_Char)0x0, /* [1645] */ + (xdc_Char)0x41, /* [1646] */ + (xdc_Char)0x5f, /* [1647] */ + (xdc_Char)0x62, /* [1648] */ + (xdc_Char)0x61, /* [1649] */ + (xdc_Char)0x64, /* [1650] */ + (xdc_Char)0x54, /* [1651] */ + (xdc_Char)0x61, /* [1652] */ + (xdc_Char)0x73, /* [1653] */ + (xdc_Char)0x6b, /* [1654] */ + (xdc_Char)0x53, /* [1655] */ + (xdc_Char)0x74, /* [1656] */ + (xdc_Char)0x61, /* [1657] */ + (xdc_Char)0x74, /* [1658] */ + (xdc_Char)0x65, /* [1659] */ + (xdc_Char)0x3a, /* [1660] */ + (xdc_Char)0x20, /* [1661] */ + (xdc_Char)0x43, /* [1662] */ + (xdc_Char)0x61, /* [1663] */ + (xdc_Char)0x6e, /* [1664] */ + (xdc_Char)0x27, /* [1665] */ + (xdc_Char)0x74, /* [1666] */ + (xdc_Char)0x20, /* [1667] */ + (xdc_Char)0x64, /* [1668] */ + (xdc_Char)0x65, /* [1669] */ + (xdc_Char)0x6c, /* [1670] */ + (xdc_Char)0x65, /* [1671] */ + (xdc_Char)0x74, /* [1672] */ + (xdc_Char)0x65, /* [1673] */ + (xdc_Char)0x20, /* [1674] */ + (xdc_Char)0x61, /* [1675] */ + (xdc_Char)0x20, /* [1676] */ + (xdc_Char)0x74, /* [1677] */ + (xdc_Char)0x61, /* [1678] */ + (xdc_Char)0x73, /* [1679] */ + (xdc_Char)0x6b, /* [1680] */ + (xdc_Char)0x20, /* [1681] */ + (xdc_Char)0x69, /* [1682] */ + (xdc_Char)0x6e, /* [1683] */ + (xdc_Char)0x20, /* [1684] */ + (xdc_Char)0x52, /* [1685] */ + (xdc_Char)0x55, /* [1686] */ + (xdc_Char)0x4e, /* [1687] */ + (xdc_Char)0x4e, /* [1688] */ + (xdc_Char)0x49, /* [1689] */ + (xdc_Char)0x4e, /* [1690] */ + (xdc_Char)0x47, /* [1691] */ + (xdc_Char)0x20, /* [1692] */ + (xdc_Char)0x73, /* [1693] */ + (xdc_Char)0x74, /* [1694] */ + (xdc_Char)0x61, /* [1695] */ + (xdc_Char)0x74, /* [1696] */ + (xdc_Char)0x65, /* [1697] */ + (xdc_Char)0x2e, /* [1698] */ + (xdc_Char)0x0, /* [1699] */ + (xdc_Char)0x41, /* [1700] */ + (xdc_Char)0x5f, /* [1701] */ + (xdc_Char)0x6e, /* [1702] */ + (xdc_Char)0x6f, /* [1703] */ + (xdc_Char)0x50, /* [1704] */ + (xdc_Char)0x65, /* [1705] */ + (xdc_Char)0x6e, /* [1706] */ + (xdc_Char)0x64, /* [1707] */ + (xdc_Char)0x45, /* [1708] */ + (xdc_Char)0x6c, /* [1709] */ + (xdc_Char)0x65, /* [1710] */ + (xdc_Char)0x6d, /* [1711] */ + (xdc_Char)0x3a, /* [1712] */ + (xdc_Char)0x20, /* [1713] */ + (xdc_Char)0x4e, /* [1714] */ + (xdc_Char)0x6f, /* [1715] */ + (xdc_Char)0x74, /* [1716] */ + (xdc_Char)0x20, /* [1717] */ + (xdc_Char)0x65, /* [1718] */ + (xdc_Char)0x6e, /* [1719] */ + (xdc_Char)0x6f, /* [1720] */ + (xdc_Char)0x75, /* [1721] */ + (xdc_Char)0x67, /* [1722] */ + (xdc_Char)0x68, /* [1723] */ + (xdc_Char)0x20, /* [1724] */ + (xdc_Char)0x69, /* [1725] */ + (xdc_Char)0x6e, /* [1726] */ + (xdc_Char)0x66, /* [1727] */ + (xdc_Char)0x6f, /* [1728] */ + (xdc_Char)0x20, /* [1729] */ + (xdc_Char)0x74, /* [1730] */ + (xdc_Char)0x6f, /* [1731] */ + (xdc_Char)0x20, /* [1732] */ + (xdc_Char)0x64, /* [1733] */ + (xdc_Char)0x65, /* [1734] */ + (xdc_Char)0x6c, /* [1735] */ + (xdc_Char)0x65, /* [1736] */ + (xdc_Char)0x74, /* [1737] */ + (xdc_Char)0x65, /* [1738] */ + (xdc_Char)0x20, /* [1739] */ + (xdc_Char)0x42, /* [1740] */ + (xdc_Char)0x4c, /* [1741] */ + (xdc_Char)0x4f, /* [1742] */ + (xdc_Char)0x43, /* [1743] */ + (xdc_Char)0x4b, /* [1744] */ + (xdc_Char)0x45, /* [1745] */ + (xdc_Char)0x44, /* [1746] */ + (xdc_Char)0x20, /* [1747] */ + (xdc_Char)0x74, /* [1748] */ + (xdc_Char)0x61, /* [1749] */ + (xdc_Char)0x73, /* [1750] */ + (xdc_Char)0x6b, /* [1751] */ + (xdc_Char)0x2e, /* [1752] */ + (xdc_Char)0x0, /* [1753] */ + (xdc_Char)0x41, /* [1754] */ + (xdc_Char)0x5f, /* [1755] */ + (xdc_Char)0x74, /* [1756] */ + (xdc_Char)0x61, /* [1757] */ + (xdc_Char)0x73, /* [1758] */ + (xdc_Char)0x6b, /* [1759] */ + (xdc_Char)0x44, /* [1760] */ + (xdc_Char)0x69, /* [1761] */ + (xdc_Char)0x73, /* [1762] */ + (xdc_Char)0x61, /* [1763] */ + (xdc_Char)0x62, /* [1764] */ + (xdc_Char)0x6c, /* [1765] */ + (xdc_Char)0x65, /* [1766] */ + (xdc_Char)0x64, /* [1767] */ + (xdc_Char)0x3a, /* [1768] */ + (xdc_Char)0x20, /* [1769] */ + (xdc_Char)0x43, /* [1770] */ + (xdc_Char)0x61, /* [1771] */ + (xdc_Char)0x6e, /* [1772] */ + (xdc_Char)0x6e, /* [1773] */ + (xdc_Char)0x6f, /* [1774] */ + (xdc_Char)0x74, /* [1775] */ + (xdc_Char)0x20, /* [1776] */ + (xdc_Char)0x63, /* [1777] */ + (xdc_Char)0x72, /* [1778] */ + (xdc_Char)0x65, /* [1779] */ + (xdc_Char)0x61, /* [1780] */ + (xdc_Char)0x74, /* [1781] */ + (xdc_Char)0x65, /* [1782] */ + (xdc_Char)0x20, /* [1783] */ + (xdc_Char)0x61, /* [1784] */ + (xdc_Char)0x20, /* [1785] */ + (xdc_Char)0x74, /* [1786] */ + (xdc_Char)0x61, /* [1787] */ + (xdc_Char)0x73, /* [1788] */ + (xdc_Char)0x6b, /* [1789] */ + (xdc_Char)0x20, /* [1790] */ + (xdc_Char)0x77, /* [1791] */ + (xdc_Char)0x68, /* [1792] */ + (xdc_Char)0x65, /* [1793] */ + (xdc_Char)0x6e, /* [1794] */ + (xdc_Char)0x20, /* [1795] */ + (xdc_Char)0x74, /* [1796] */ + (xdc_Char)0x61, /* [1797] */ + (xdc_Char)0x73, /* [1798] */ + (xdc_Char)0x6b, /* [1799] */ + (xdc_Char)0x69, /* [1800] */ + (xdc_Char)0x6e, /* [1801] */ + (xdc_Char)0x67, /* [1802] */ + (xdc_Char)0x20, /* [1803] */ + (xdc_Char)0x69, /* [1804] */ + (xdc_Char)0x73, /* [1805] */ + (xdc_Char)0x20, /* [1806] */ + (xdc_Char)0x64, /* [1807] */ + (xdc_Char)0x69, /* [1808] */ + (xdc_Char)0x73, /* [1809] */ + (xdc_Char)0x61, /* [1810] */ + (xdc_Char)0x62, /* [1811] */ + (xdc_Char)0x6c, /* [1812] */ + (xdc_Char)0x65, /* [1813] */ + (xdc_Char)0x64, /* [1814] */ + (xdc_Char)0x2e, /* [1815] */ + (xdc_Char)0x0, /* [1816] */ + (xdc_Char)0x41, /* [1817] */ + (xdc_Char)0x5f, /* [1818] */ + (xdc_Char)0x62, /* [1819] */ + (xdc_Char)0x61, /* [1820] */ + (xdc_Char)0x64, /* [1821] */ + (xdc_Char)0x50, /* [1822] */ + (xdc_Char)0x72, /* [1823] */ + (xdc_Char)0x69, /* [1824] */ + (xdc_Char)0x6f, /* [1825] */ + (xdc_Char)0x72, /* [1826] */ + (xdc_Char)0x69, /* [1827] */ + (xdc_Char)0x74, /* [1828] */ + (xdc_Char)0x79, /* [1829] */ + (xdc_Char)0x3a, /* [1830] */ + (xdc_Char)0x20, /* [1831] */ + (xdc_Char)0x41, /* [1832] */ + (xdc_Char)0x6e, /* [1833] */ + (xdc_Char)0x20, /* [1834] */ + (xdc_Char)0x69, /* [1835] */ + (xdc_Char)0x6e, /* [1836] */ + (xdc_Char)0x76, /* [1837] */ + (xdc_Char)0x61, /* [1838] */ + (xdc_Char)0x6c, /* [1839] */ + (xdc_Char)0x69, /* [1840] */ + (xdc_Char)0x64, /* [1841] */ + (xdc_Char)0x20, /* [1842] */ + (xdc_Char)0x74, /* [1843] */ + (xdc_Char)0x61, /* [1844] */ + (xdc_Char)0x73, /* [1845] */ + (xdc_Char)0x6b, /* [1846] */ + (xdc_Char)0x20, /* [1847] */ + (xdc_Char)0x70, /* [1848] */ + (xdc_Char)0x72, /* [1849] */ + (xdc_Char)0x69, /* [1850] */ + (xdc_Char)0x6f, /* [1851] */ + (xdc_Char)0x72, /* [1852] */ + (xdc_Char)0x69, /* [1853] */ + (xdc_Char)0x74, /* [1854] */ + (xdc_Char)0x79, /* [1855] */ + (xdc_Char)0x20, /* [1856] */ + (xdc_Char)0x77, /* [1857] */ + (xdc_Char)0x61, /* [1858] */ + (xdc_Char)0x73, /* [1859] */ + (xdc_Char)0x20, /* [1860] */ + (xdc_Char)0x75, /* [1861] */ + (xdc_Char)0x73, /* [1862] */ + (xdc_Char)0x65, /* [1863] */ + (xdc_Char)0x64, /* [1864] */ + (xdc_Char)0x2e, /* [1865] */ + (xdc_Char)0x0, /* [1866] */ + (xdc_Char)0x41, /* [1867] */ + (xdc_Char)0x5f, /* [1868] */ + (xdc_Char)0x62, /* [1869] */ + (xdc_Char)0x61, /* [1870] */ + (xdc_Char)0x64, /* [1871] */ + (xdc_Char)0x54, /* [1872] */ + (xdc_Char)0x69, /* [1873] */ + (xdc_Char)0x6d, /* [1874] */ + (xdc_Char)0x65, /* [1875] */ + (xdc_Char)0x6f, /* [1876] */ + (xdc_Char)0x75, /* [1877] */ + (xdc_Char)0x74, /* [1878] */ + (xdc_Char)0x3a, /* [1879] */ + (xdc_Char)0x20, /* [1880] */ + (xdc_Char)0x43, /* [1881] */ + (xdc_Char)0x61, /* [1882] */ + (xdc_Char)0x6e, /* [1883] */ + (xdc_Char)0x27, /* [1884] */ + (xdc_Char)0x74, /* [1885] */ + (xdc_Char)0x20, /* [1886] */ + (xdc_Char)0x73, /* [1887] */ + (xdc_Char)0x6c, /* [1888] */ + (xdc_Char)0x65, /* [1889] */ + (xdc_Char)0x65, /* [1890] */ + (xdc_Char)0x70, /* [1891] */ + (xdc_Char)0x20, /* [1892] */ + (xdc_Char)0x46, /* [1893] */ + (xdc_Char)0x4f, /* [1894] */ + (xdc_Char)0x52, /* [1895] */ + (xdc_Char)0x45, /* [1896] */ + (xdc_Char)0x56, /* [1897] */ + (xdc_Char)0x45, /* [1898] */ + (xdc_Char)0x52, /* [1899] */ + (xdc_Char)0x2e, /* [1900] */ + (xdc_Char)0x0, /* [1901] */ + (xdc_Char)0x41, /* [1902] */ + (xdc_Char)0x5f, /* [1903] */ + (xdc_Char)0x62, /* [1904] */ + (xdc_Char)0x61, /* [1905] */ + (xdc_Char)0x64, /* [1906] */ + (xdc_Char)0x41, /* [1907] */ + (xdc_Char)0x66, /* [1908] */ + (xdc_Char)0x66, /* [1909] */ + (xdc_Char)0x69, /* [1910] */ + (xdc_Char)0x6e, /* [1911] */ + (xdc_Char)0x69, /* [1912] */ + (xdc_Char)0x74, /* [1913] */ + (xdc_Char)0x79, /* [1914] */ + (xdc_Char)0x3a, /* [1915] */ + (xdc_Char)0x20, /* [1916] */ + (xdc_Char)0x49, /* [1917] */ + (xdc_Char)0x6e, /* [1918] */ + (xdc_Char)0x76, /* [1919] */ + (xdc_Char)0x61, /* [1920] */ + (xdc_Char)0x6c, /* [1921] */ + (xdc_Char)0x69, /* [1922] */ + (xdc_Char)0x64, /* [1923] */ + (xdc_Char)0x20, /* [1924] */ + (xdc_Char)0x61, /* [1925] */ + (xdc_Char)0x66, /* [1926] */ + (xdc_Char)0x66, /* [1927] */ + (xdc_Char)0x69, /* [1928] */ + (xdc_Char)0x6e, /* [1929] */ + (xdc_Char)0x69, /* [1930] */ + (xdc_Char)0x74, /* [1931] */ + (xdc_Char)0x79, /* [1932] */ + (xdc_Char)0x2e, /* [1933] */ + (xdc_Char)0x0, /* [1934] */ + (xdc_Char)0x41, /* [1935] */ + (xdc_Char)0x5f, /* [1936] */ + (xdc_Char)0x73, /* [1937] */ + (xdc_Char)0x6c, /* [1938] */ + (xdc_Char)0x65, /* [1939] */ + (xdc_Char)0x65, /* [1940] */ + (xdc_Char)0x70, /* [1941] */ + (xdc_Char)0x54, /* [1942] */ + (xdc_Char)0x61, /* [1943] */ + (xdc_Char)0x73, /* [1944] */ + (xdc_Char)0x6b, /* [1945] */ + (xdc_Char)0x44, /* [1946] */ + (xdc_Char)0x69, /* [1947] */ + (xdc_Char)0x73, /* [1948] */ + (xdc_Char)0x61, /* [1949] */ + (xdc_Char)0x62, /* [1950] */ + (xdc_Char)0x6c, /* [1951] */ + (xdc_Char)0x65, /* [1952] */ + (xdc_Char)0x64, /* [1953] */ + (xdc_Char)0x3a, /* [1954] */ + (xdc_Char)0x20, /* [1955] */ + (xdc_Char)0x43, /* [1956] */ + (xdc_Char)0x61, /* [1957] */ + (xdc_Char)0x6e, /* [1958] */ + (xdc_Char)0x6e, /* [1959] */ + (xdc_Char)0x6f, /* [1960] */ + (xdc_Char)0x74, /* [1961] */ + (xdc_Char)0x20, /* [1962] */ + (xdc_Char)0x63, /* [1963] */ + (xdc_Char)0x61, /* [1964] */ + (xdc_Char)0x6c, /* [1965] */ + (xdc_Char)0x6c, /* [1966] */ + (xdc_Char)0x20, /* [1967] */ + (xdc_Char)0x54, /* [1968] */ + (xdc_Char)0x61, /* [1969] */ + (xdc_Char)0x73, /* [1970] */ + (xdc_Char)0x6b, /* [1971] */ + (xdc_Char)0x5f, /* [1972] */ + (xdc_Char)0x73, /* [1973] */ + (xdc_Char)0x6c, /* [1974] */ + (xdc_Char)0x65, /* [1975] */ + (xdc_Char)0x65, /* [1976] */ + (xdc_Char)0x70, /* [1977] */ + (xdc_Char)0x28, /* [1978] */ + (xdc_Char)0x29, /* [1979] */ + (xdc_Char)0x20, /* [1980] */ + (xdc_Char)0x77, /* [1981] */ + (xdc_Char)0x68, /* [1982] */ + (xdc_Char)0x69, /* [1983] */ + (xdc_Char)0x6c, /* [1984] */ + (xdc_Char)0x65, /* [1985] */ + (xdc_Char)0x20, /* [1986] */ + (xdc_Char)0x74, /* [1987] */ + (xdc_Char)0x68, /* [1988] */ + (xdc_Char)0x65, /* [1989] */ + (xdc_Char)0x20, /* [1990] */ + (xdc_Char)0x54, /* [1991] */ + (xdc_Char)0x61, /* [1992] */ + (xdc_Char)0x73, /* [1993] */ + (xdc_Char)0x6b, /* [1994] */ + (xdc_Char)0x20, /* [1995] */ + (xdc_Char)0x73, /* [1996] */ + (xdc_Char)0x63, /* [1997] */ + (xdc_Char)0x68, /* [1998] */ + (xdc_Char)0x65, /* [1999] */ + (xdc_Char)0x64, /* [2000] */ + (xdc_Char)0x75, /* [2001] */ + (xdc_Char)0x6c, /* [2002] */ + (xdc_Char)0x65, /* [2003] */ + (xdc_Char)0x72, /* [2004] */ + (xdc_Char)0x20, /* [2005] */ + (xdc_Char)0x69, /* [2006] */ + (xdc_Char)0x73, /* [2007] */ + (xdc_Char)0x20, /* [2008] */ + (xdc_Char)0x64, /* [2009] */ + (xdc_Char)0x69, /* [2010] */ + (xdc_Char)0x73, /* [2011] */ + (xdc_Char)0x61, /* [2012] */ + (xdc_Char)0x62, /* [2013] */ + (xdc_Char)0x6c, /* [2014] */ + (xdc_Char)0x65, /* [2015] */ + (xdc_Char)0x64, /* [2016] */ + (xdc_Char)0x2e, /* [2017] */ + (xdc_Char)0x0, /* [2018] */ + (xdc_Char)0x41, /* [2019] */ + (xdc_Char)0x5f, /* [2020] */ + (xdc_Char)0x69, /* [2021] */ + (xdc_Char)0x6e, /* [2022] */ + (xdc_Char)0x76, /* [2023] */ + (xdc_Char)0x61, /* [2024] */ + (xdc_Char)0x6c, /* [2025] */ + (xdc_Char)0x69, /* [2026] */ + (xdc_Char)0x64, /* [2027] */ + (xdc_Char)0x43, /* [2028] */ + (xdc_Char)0x6f, /* [2029] */ + (xdc_Char)0x72, /* [2030] */ + (xdc_Char)0x65, /* [2031] */ + (xdc_Char)0x49, /* [2032] */ + (xdc_Char)0x64, /* [2033] */ + (xdc_Char)0x3a, /* [2034] */ + (xdc_Char)0x20, /* [2035] */ + (xdc_Char)0x43, /* [2036] */ + (xdc_Char)0x61, /* [2037] */ + (xdc_Char)0x6e, /* [2038] */ + (xdc_Char)0x6e, /* [2039] */ + (xdc_Char)0x6f, /* [2040] */ + (xdc_Char)0x74, /* [2041] */ + (xdc_Char)0x20, /* [2042] */ + (xdc_Char)0x70, /* [2043] */ + (xdc_Char)0x61, /* [2044] */ + (xdc_Char)0x73, /* [2045] */ + (xdc_Char)0x73, /* [2046] */ + (xdc_Char)0x20, /* [2047] */ + (xdc_Char)0x61, /* [2048] */ + (xdc_Char)0x20, /* [2049] */ + (xdc_Char)0x6e, /* [2050] */ + (xdc_Char)0x6f, /* [2051] */ + (xdc_Char)0x6e, /* [2052] */ + (xdc_Char)0x2d, /* [2053] */ + (xdc_Char)0x7a, /* [2054] */ + (xdc_Char)0x65, /* [2055] */ + (xdc_Char)0x72, /* [2056] */ + (xdc_Char)0x6f, /* [2057] */ + (xdc_Char)0x20, /* [2058] */ + (xdc_Char)0x43, /* [2059] */ + (xdc_Char)0x6f, /* [2060] */ + (xdc_Char)0x72, /* [2061] */ + (xdc_Char)0x65, /* [2062] */ + (xdc_Char)0x49, /* [2063] */ + (xdc_Char)0x64, /* [2064] */ + (xdc_Char)0x20, /* [2065] */ + (xdc_Char)0x69, /* [2066] */ + (xdc_Char)0x6e, /* [2067] */ + (xdc_Char)0x20, /* [2068] */ + (xdc_Char)0x61, /* [2069] */ + (xdc_Char)0x20, /* [2070] */ + (xdc_Char)0x6e, /* [2071] */ + (xdc_Char)0x6f, /* [2072] */ + (xdc_Char)0x6e, /* [2073] */ + (xdc_Char)0x2d, /* [2074] */ + (xdc_Char)0x53, /* [2075] */ + (xdc_Char)0x4d, /* [2076] */ + (xdc_Char)0x50, /* [2077] */ + (xdc_Char)0x20, /* [2078] */ + (xdc_Char)0x61, /* [2079] */ + (xdc_Char)0x70, /* [2080] */ + (xdc_Char)0x70, /* [2081] */ + (xdc_Char)0x6c, /* [2082] */ + (xdc_Char)0x69, /* [2083] */ + (xdc_Char)0x63, /* [2084] */ + (xdc_Char)0x61, /* [2085] */ + (xdc_Char)0x74, /* [2086] */ + (xdc_Char)0x69, /* [2087] */ + (xdc_Char)0x6f, /* [2088] */ + (xdc_Char)0x6e, /* [2089] */ + (xdc_Char)0x2e, /* [2090] */ + (xdc_Char)0x0, /* [2091] */ + (xdc_Char)0x41, /* [2092] */ + (xdc_Char)0x5f, /* [2093] */ + (xdc_Char)0x75, /* [2094] */ + (xdc_Char)0x6e, /* [2095] */ + (xdc_Char)0x73, /* [2096] */ + (xdc_Char)0x75, /* [2097] */ + (xdc_Char)0x70, /* [2098] */ + (xdc_Char)0x70, /* [2099] */ + (xdc_Char)0x6f, /* [2100] */ + (xdc_Char)0x72, /* [2101] */ + (xdc_Char)0x74, /* [2102] */ + (xdc_Char)0x65, /* [2103] */ + (xdc_Char)0x64, /* [2104] */ + (xdc_Char)0x4d, /* [2105] */ + (xdc_Char)0x61, /* [2106] */ + (xdc_Char)0x73, /* [2107] */ + (xdc_Char)0x6b, /* [2108] */ + (xdc_Char)0x69, /* [2109] */ + (xdc_Char)0x6e, /* [2110] */ + (xdc_Char)0x67, /* [2111] */ + (xdc_Char)0x4f, /* [2112] */ + (xdc_Char)0x70, /* [2113] */ + (xdc_Char)0x74, /* [2114] */ + (xdc_Char)0x69, /* [2115] */ + (xdc_Char)0x6f, /* [2116] */ + (xdc_Char)0x6e, /* [2117] */ + (xdc_Char)0x3a, /* [2118] */ + (xdc_Char)0x20, /* [2119] */ + (xdc_Char)0x75, /* [2120] */ + (xdc_Char)0x6e, /* [2121] */ + (xdc_Char)0x73, /* [2122] */ + (xdc_Char)0x75, /* [2123] */ + (xdc_Char)0x70, /* [2124] */ + (xdc_Char)0x70, /* [2125] */ + (xdc_Char)0x6f, /* [2126] */ + (xdc_Char)0x72, /* [2127] */ + (xdc_Char)0x74, /* [2128] */ + (xdc_Char)0x65, /* [2129] */ + (xdc_Char)0x64, /* [2130] */ + (xdc_Char)0x20, /* [2131] */ + (xdc_Char)0x6d, /* [2132] */ + (xdc_Char)0x61, /* [2133] */ + (xdc_Char)0x73, /* [2134] */ + (xdc_Char)0x6b, /* [2135] */ + (xdc_Char)0x53, /* [2136] */ + (xdc_Char)0x65, /* [2137] */ + (xdc_Char)0x74, /* [2138] */ + (xdc_Char)0x74, /* [2139] */ + (xdc_Char)0x69, /* [2140] */ + (xdc_Char)0x6e, /* [2141] */ + (xdc_Char)0x67, /* [2142] */ + (xdc_Char)0x2e, /* [2143] */ + (xdc_Char)0x0, /* [2144] */ + (xdc_Char)0x41, /* [2145] */ + (xdc_Char)0x5f, /* [2146] */ + (xdc_Char)0x7a, /* [2147] */ + (xdc_Char)0x65, /* [2148] */ + (xdc_Char)0x72, /* [2149] */ + (xdc_Char)0x6f, /* [2150] */ + (xdc_Char)0x54, /* [2151] */ + (xdc_Char)0x69, /* [2152] */ + (xdc_Char)0x6d, /* [2153] */ + (xdc_Char)0x65, /* [2154] */ + (xdc_Char)0x6f, /* [2155] */ + (xdc_Char)0x75, /* [2156] */ + (xdc_Char)0x74, /* [2157] */ + (xdc_Char)0x3a, /* [2158] */ + (xdc_Char)0x20, /* [2159] */ + (xdc_Char)0x54, /* [2160] */ + (xdc_Char)0x69, /* [2161] */ + (xdc_Char)0x6d, /* [2162] */ + (xdc_Char)0x65, /* [2163] */ + (xdc_Char)0x6f, /* [2164] */ + (xdc_Char)0x75, /* [2165] */ + (xdc_Char)0x74, /* [2166] */ + (xdc_Char)0x20, /* [2167] */ + (xdc_Char)0x76, /* [2168] */ + (xdc_Char)0x61, /* [2169] */ + (xdc_Char)0x6c, /* [2170] */ + (xdc_Char)0x75, /* [2171] */ + (xdc_Char)0x65, /* [2172] */ + (xdc_Char)0x20, /* [2173] */ + (xdc_Char)0x61, /* [2174] */ + (xdc_Char)0x6e, /* [2175] */ + (xdc_Char)0x6e, /* [2176] */ + (xdc_Char)0x6f, /* [2177] */ + (xdc_Char)0x74, /* [2178] */ + (xdc_Char)0x20, /* [2179] */ + (xdc_Char)0x62, /* [2180] */ + (xdc_Char)0x65, /* [2181] */ + (xdc_Char)0x20, /* [2182] */ + (xdc_Char)0x7a, /* [2183] */ + (xdc_Char)0x65, /* [2184] */ + (xdc_Char)0x72, /* [2185] */ + (xdc_Char)0x6f, /* [2186] */ + (xdc_Char)0x0, /* [2187] */ + (xdc_Char)0x41, /* [2188] */ + (xdc_Char)0x5f, /* [2189] */ + (xdc_Char)0x69, /* [2190] */ + (xdc_Char)0x6e, /* [2191] */ + (xdc_Char)0x76, /* [2192] */ + (xdc_Char)0x61, /* [2193] */ + (xdc_Char)0x6c, /* [2194] */ + (xdc_Char)0x69, /* [2195] */ + (xdc_Char)0x64, /* [2196] */ + (xdc_Char)0x4b, /* [2197] */ + (xdc_Char)0x65, /* [2198] */ + (xdc_Char)0x79, /* [2199] */ + (xdc_Char)0x3a, /* [2200] */ + (xdc_Char)0x20, /* [2201] */ + (xdc_Char)0x74, /* [2202] */ + (xdc_Char)0x68, /* [2203] */ + (xdc_Char)0x65, /* [2204] */ + (xdc_Char)0x20, /* [2205] */ + (xdc_Char)0x6b, /* [2206] */ + (xdc_Char)0x65, /* [2207] */ + (xdc_Char)0x79, /* [2208] */ + (xdc_Char)0x20, /* [2209] */ + (xdc_Char)0x6d, /* [2210] */ + (xdc_Char)0x75, /* [2211] */ + (xdc_Char)0x73, /* [2212] */ + (xdc_Char)0x74, /* [2213] */ + (xdc_Char)0x20, /* [2214] */ + (xdc_Char)0x62, /* [2215] */ + (xdc_Char)0x65, /* [2216] */ + (xdc_Char)0x20, /* [2217] */ + (xdc_Char)0x73, /* [2218] */ + (xdc_Char)0x65, /* [2219] */ + (xdc_Char)0x74, /* [2220] */ + (xdc_Char)0x20, /* [2221] */ + (xdc_Char)0x74, /* [2222] */ + (xdc_Char)0x6f, /* [2223] */ + (xdc_Char)0x20, /* [2224] */ + (xdc_Char)0x61, /* [2225] */ + (xdc_Char)0x20, /* [2226] */ + (xdc_Char)0x6e, /* [2227] */ + (xdc_Char)0x6f, /* [2228] */ + (xdc_Char)0x6e, /* [2229] */ + (xdc_Char)0x2d, /* [2230] */ + (xdc_Char)0x64, /* [2231] */ + (xdc_Char)0x65, /* [2232] */ + (xdc_Char)0x66, /* [2233] */ + (xdc_Char)0x61, /* [2234] */ + (xdc_Char)0x75, /* [2235] */ + (xdc_Char)0x6c, /* [2236] */ + (xdc_Char)0x74, /* [2237] */ + (xdc_Char)0x20, /* [2238] */ + (xdc_Char)0x76, /* [2239] */ + (xdc_Char)0x61, /* [2240] */ + (xdc_Char)0x6c, /* [2241] */ + (xdc_Char)0x75, /* [2242] */ + (xdc_Char)0x65, /* [2243] */ + (xdc_Char)0x0, /* [2244] */ + (xdc_Char)0x41, /* [2245] */ + (xdc_Char)0x5f, /* [2246] */ + (xdc_Char)0x62, /* [2247] */ + (xdc_Char)0x61, /* [2248] */ + (xdc_Char)0x64, /* [2249] */ + (xdc_Char)0x43, /* [2250] */ + (xdc_Char)0x6f, /* [2251] */ + (xdc_Char)0x6e, /* [2252] */ + (xdc_Char)0x74, /* [2253] */ + (xdc_Char)0x65, /* [2254] */ + (xdc_Char)0x78, /* [2255] */ + (xdc_Char)0x74, /* [2256] */ + (xdc_Char)0x3a, /* [2257] */ + (xdc_Char)0x20, /* [2258] */ + (xdc_Char)0x62, /* [2259] */ + (xdc_Char)0x61, /* [2260] */ + (xdc_Char)0x64, /* [2261] */ + (xdc_Char)0x20, /* [2262] */ + (xdc_Char)0x63, /* [2263] */ + (xdc_Char)0x61, /* [2264] */ + (xdc_Char)0x6c, /* [2265] */ + (xdc_Char)0x6c, /* [2266] */ + (xdc_Char)0x69, /* [2267] */ + (xdc_Char)0x6e, /* [2268] */ + (xdc_Char)0x67, /* [2269] */ + (xdc_Char)0x20, /* [2270] */ + (xdc_Char)0x63, /* [2271] */ + (xdc_Char)0x6f, /* [2272] */ + (xdc_Char)0x6e, /* [2273] */ + (xdc_Char)0x74, /* [2274] */ + (xdc_Char)0x65, /* [2275] */ + (xdc_Char)0x78, /* [2276] */ + (xdc_Char)0x74, /* [2277] */ + (xdc_Char)0x2e, /* [2278] */ + (xdc_Char)0x20, /* [2279] */ + (xdc_Char)0x4d, /* [2280] */ + (xdc_Char)0x61, /* [2281] */ + (xdc_Char)0x79, /* [2282] */ + (xdc_Char)0x20, /* [2283] */ + (xdc_Char)0x6e, /* [2284] */ + (xdc_Char)0x6f, /* [2285] */ + (xdc_Char)0x74, /* [2286] */ + (xdc_Char)0x20, /* [2287] */ + (xdc_Char)0x62, /* [2288] */ + (xdc_Char)0x65, /* [2289] */ + (xdc_Char)0x20, /* [2290] */ + (xdc_Char)0x65, /* [2291] */ + (xdc_Char)0x6e, /* [2292] */ + (xdc_Char)0x74, /* [2293] */ + (xdc_Char)0x65, /* [2294] */ + (xdc_Char)0x72, /* [2295] */ + (xdc_Char)0x65, /* [2296] */ + (xdc_Char)0x64, /* [2297] */ + (xdc_Char)0x20, /* [2298] */ + (xdc_Char)0x66, /* [2299] */ + (xdc_Char)0x72, /* [2300] */ + (xdc_Char)0x6f, /* [2301] */ + (xdc_Char)0x6d, /* [2302] */ + (xdc_Char)0x20, /* [2303] */ + (xdc_Char)0x61, /* [2304] */ + (xdc_Char)0x20, /* [2305] */ + (xdc_Char)0x68, /* [2306] */ + (xdc_Char)0x61, /* [2307] */ + (xdc_Char)0x72, /* [2308] */ + (xdc_Char)0x64, /* [2309] */ + (xdc_Char)0x77, /* [2310] */ + (xdc_Char)0x61, /* [2311] */ + (xdc_Char)0x72, /* [2312] */ + (xdc_Char)0x65, /* [2313] */ + (xdc_Char)0x20, /* [2314] */ + (xdc_Char)0x69, /* [2315] */ + (xdc_Char)0x6e, /* [2316] */ + (xdc_Char)0x74, /* [2317] */ + (xdc_Char)0x65, /* [2318] */ + (xdc_Char)0x72, /* [2319] */ + (xdc_Char)0x72, /* [2320] */ + (xdc_Char)0x75, /* [2321] */ + (xdc_Char)0x70, /* [2322] */ + (xdc_Char)0x74, /* [2323] */ + (xdc_Char)0x20, /* [2324] */ + (xdc_Char)0x74, /* [2325] */ + (xdc_Char)0x68, /* [2326] */ + (xdc_Char)0x72, /* [2327] */ + (xdc_Char)0x65, /* [2328] */ + (xdc_Char)0x61, /* [2329] */ + (xdc_Char)0x64, /* [2330] */ + (xdc_Char)0x2e, /* [2331] */ + (xdc_Char)0x0, /* [2332] */ + (xdc_Char)0x41, /* [2333] */ + (xdc_Char)0x5f, /* [2334] */ + (xdc_Char)0x62, /* [2335] */ + (xdc_Char)0x61, /* [2336] */ + (xdc_Char)0x64, /* [2337] */ + (xdc_Char)0x43, /* [2338] */ + (xdc_Char)0x6f, /* [2339] */ + (xdc_Char)0x6e, /* [2340] */ + (xdc_Char)0x74, /* [2341] */ + (xdc_Char)0x65, /* [2342] */ + (xdc_Char)0x78, /* [2343] */ + (xdc_Char)0x74, /* [2344] */ + (xdc_Char)0x3a, /* [2345] */ + (xdc_Char)0x20, /* [2346] */ + (xdc_Char)0x62, /* [2347] */ + (xdc_Char)0x61, /* [2348] */ + (xdc_Char)0x64, /* [2349] */ + (xdc_Char)0x20, /* [2350] */ + (xdc_Char)0x63, /* [2351] */ + (xdc_Char)0x61, /* [2352] */ + (xdc_Char)0x6c, /* [2353] */ + (xdc_Char)0x6c, /* [2354] */ + (xdc_Char)0x69, /* [2355] */ + (xdc_Char)0x6e, /* [2356] */ + (xdc_Char)0x67, /* [2357] */ + (xdc_Char)0x20, /* [2358] */ + (xdc_Char)0x63, /* [2359] */ + (xdc_Char)0x6f, /* [2360] */ + (xdc_Char)0x6e, /* [2361] */ + (xdc_Char)0x74, /* [2362] */ + (xdc_Char)0x65, /* [2363] */ + (xdc_Char)0x78, /* [2364] */ + (xdc_Char)0x74, /* [2365] */ + (xdc_Char)0x2e, /* [2366] */ + (xdc_Char)0x20, /* [2367] */ + (xdc_Char)0x4d, /* [2368] */ + (xdc_Char)0x61, /* [2369] */ + (xdc_Char)0x79, /* [2370] */ + (xdc_Char)0x20, /* [2371] */ + (xdc_Char)0x6e, /* [2372] */ + (xdc_Char)0x6f, /* [2373] */ + (xdc_Char)0x74, /* [2374] */ + (xdc_Char)0x20, /* [2375] */ + (xdc_Char)0x62, /* [2376] */ + (xdc_Char)0x65, /* [2377] */ + (xdc_Char)0x20, /* [2378] */ + (xdc_Char)0x65, /* [2379] */ + (xdc_Char)0x6e, /* [2380] */ + (xdc_Char)0x74, /* [2381] */ + (xdc_Char)0x65, /* [2382] */ + (xdc_Char)0x72, /* [2383] */ + (xdc_Char)0x65, /* [2384] */ + (xdc_Char)0x64, /* [2385] */ + (xdc_Char)0x20, /* [2386] */ + (xdc_Char)0x66, /* [2387] */ + (xdc_Char)0x72, /* [2388] */ + (xdc_Char)0x6f, /* [2389] */ + (xdc_Char)0x6d, /* [2390] */ + (xdc_Char)0x20, /* [2391] */ + (xdc_Char)0x61, /* [2392] */ + (xdc_Char)0x20, /* [2393] */ + (xdc_Char)0x73, /* [2394] */ + (xdc_Char)0x6f, /* [2395] */ + (xdc_Char)0x66, /* [2396] */ + (xdc_Char)0x74, /* [2397] */ + (xdc_Char)0x77, /* [2398] */ + (xdc_Char)0x61, /* [2399] */ + (xdc_Char)0x72, /* [2400] */ + (xdc_Char)0x65, /* [2401] */ + (xdc_Char)0x20, /* [2402] */ + (xdc_Char)0x6f, /* [2403] */ + (xdc_Char)0x72, /* [2404] */ + (xdc_Char)0x20, /* [2405] */ + (xdc_Char)0x68, /* [2406] */ + (xdc_Char)0x61, /* [2407] */ + (xdc_Char)0x72, /* [2408] */ + (xdc_Char)0x64, /* [2409] */ + (xdc_Char)0x77, /* [2410] */ + (xdc_Char)0x61, /* [2411] */ + (xdc_Char)0x72, /* [2412] */ + (xdc_Char)0x65, /* [2413] */ + (xdc_Char)0x20, /* [2414] */ + (xdc_Char)0x69, /* [2415] */ + (xdc_Char)0x6e, /* [2416] */ + (xdc_Char)0x74, /* [2417] */ + (xdc_Char)0x65, /* [2418] */ + (xdc_Char)0x72, /* [2419] */ + (xdc_Char)0x72, /* [2420] */ + (xdc_Char)0x75, /* [2421] */ + (xdc_Char)0x70, /* [2422] */ + (xdc_Char)0x74, /* [2423] */ + (xdc_Char)0x20, /* [2424] */ + (xdc_Char)0x74, /* [2425] */ + (xdc_Char)0x68, /* [2426] */ + (xdc_Char)0x72, /* [2427] */ + (xdc_Char)0x65, /* [2428] */ + (xdc_Char)0x61, /* [2429] */ + (xdc_Char)0x64, /* [2430] */ + (xdc_Char)0x2e, /* [2431] */ + (xdc_Char)0x0, /* [2432] */ + (xdc_Char)0x41, /* [2433] */ + (xdc_Char)0x5f, /* [2434] */ + (xdc_Char)0x62, /* [2435] */ + (xdc_Char)0x61, /* [2436] */ + (xdc_Char)0x64, /* [2437] */ + (xdc_Char)0x43, /* [2438] */ + (xdc_Char)0x6f, /* [2439] */ + (xdc_Char)0x6e, /* [2440] */ + (xdc_Char)0x74, /* [2441] */ + (xdc_Char)0x65, /* [2442] */ + (xdc_Char)0x78, /* [2443] */ + (xdc_Char)0x74, /* [2444] */ + (xdc_Char)0x3a, /* [2445] */ + (xdc_Char)0x20, /* [2446] */ + (xdc_Char)0x62, /* [2447] */ + (xdc_Char)0x61, /* [2448] */ + (xdc_Char)0x64, /* [2449] */ + (xdc_Char)0x20, /* [2450] */ + (xdc_Char)0x63, /* [2451] */ + (xdc_Char)0x61, /* [2452] */ + (xdc_Char)0x6c, /* [2453] */ + (xdc_Char)0x6c, /* [2454] */ + (xdc_Char)0x69, /* [2455] */ + (xdc_Char)0x6e, /* [2456] */ + (xdc_Char)0x67, /* [2457] */ + (xdc_Char)0x20, /* [2458] */ + (xdc_Char)0x63, /* [2459] */ + (xdc_Char)0x6f, /* [2460] */ + (xdc_Char)0x6e, /* [2461] */ + (xdc_Char)0x74, /* [2462] */ + (xdc_Char)0x65, /* [2463] */ + (xdc_Char)0x78, /* [2464] */ + (xdc_Char)0x74, /* [2465] */ + (xdc_Char)0x2e, /* [2466] */ + (xdc_Char)0x20, /* [2467] */ + (xdc_Char)0x53, /* [2468] */ + (xdc_Char)0x65, /* [2469] */ + (xdc_Char)0x65, /* [2470] */ + (xdc_Char)0x20, /* [2471] */ + (xdc_Char)0x47, /* [2472] */ + (xdc_Char)0x61, /* [2473] */ + (xdc_Char)0x74, /* [2474] */ + (xdc_Char)0x65, /* [2475] */ + (xdc_Char)0x4d, /* [2476] */ + (xdc_Char)0x75, /* [2477] */ + (xdc_Char)0x74, /* [2478] */ + (xdc_Char)0x65, /* [2479] */ + (xdc_Char)0x78, /* [2480] */ + (xdc_Char)0x50, /* [2481] */ + (xdc_Char)0x72, /* [2482] */ + (xdc_Char)0x69, /* [2483] */ + (xdc_Char)0x20, /* [2484] */ + (xdc_Char)0x41, /* [2485] */ + (xdc_Char)0x50, /* [2486] */ + (xdc_Char)0x49, /* [2487] */ + (xdc_Char)0x20, /* [2488] */ + (xdc_Char)0x64, /* [2489] */ + (xdc_Char)0x6f, /* [2490] */ + (xdc_Char)0x63, /* [2491] */ + (xdc_Char)0x20, /* [2492] */ + (xdc_Char)0x66, /* [2493] */ + (xdc_Char)0x6f, /* [2494] */ + (xdc_Char)0x72, /* [2495] */ + (xdc_Char)0x20, /* [2496] */ + (xdc_Char)0x64, /* [2497] */ + (xdc_Char)0x65, /* [2498] */ + (xdc_Char)0x74, /* [2499] */ + (xdc_Char)0x61, /* [2500] */ + (xdc_Char)0x69, /* [2501] */ + (xdc_Char)0x6c, /* [2502] */ + (xdc_Char)0x73, /* [2503] */ + (xdc_Char)0x2e, /* [2504] */ + (xdc_Char)0x0, /* [2505] */ + (xdc_Char)0x41, /* [2506] */ + (xdc_Char)0x5f, /* [2507] */ + (xdc_Char)0x65, /* [2508] */ + (xdc_Char)0x6e, /* [2509] */ + (xdc_Char)0x74, /* [2510] */ + (xdc_Char)0x65, /* [2511] */ + (xdc_Char)0x72, /* [2512] */ + (xdc_Char)0x54, /* [2513] */ + (xdc_Char)0x61, /* [2514] */ + (xdc_Char)0x73, /* [2515] */ + (xdc_Char)0x6b, /* [2516] */ + (xdc_Char)0x44, /* [2517] */ + (xdc_Char)0x69, /* [2518] */ + (xdc_Char)0x73, /* [2519] */ + (xdc_Char)0x61, /* [2520] */ + (xdc_Char)0x62, /* [2521] */ + (xdc_Char)0x6c, /* [2522] */ + (xdc_Char)0x65, /* [2523] */ + (xdc_Char)0x64, /* [2524] */ + (xdc_Char)0x3a, /* [2525] */ + (xdc_Char)0x20, /* [2526] */ + (xdc_Char)0x43, /* [2527] */ + (xdc_Char)0x61, /* [2528] */ + (xdc_Char)0x6e, /* [2529] */ + (xdc_Char)0x6e, /* [2530] */ + (xdc_Char)0x6f, /* [2531] */ + (xdc_Char)0x74, /* [2532] */ + (xdc_Char)0x20, /* [2533] */ + (xdc_Char)0x63, /* [2534] */ + (xdc_Char)0x61, /* [2535] */ + (xdc_Char)0x6c, /* [2536] */ + (xdc_Char)0x6c, /* [2537] */ + (xdc_Char)0x20, /* [2538] */ + (xdc_Char)0x47, /* [2539] */ + (xdc_Char)0x61, /* [2540] */ + (xdc_Char)0x74, /* [2541] */ + (xdc_Char)0x65, /* [2542] */ + (xdc_Char)0x4d, /* [2543] */ + (xdc_Char)0x75, /* [2544] */ + (xdc_Char)0x74, /* [2545] */ + (xdc_Char)0x65, /* [2546] */ + (xdc_Char)0x78, /* [2547] */ + (xdc_Char)0x50, /* [2548] */ + (xdc_Char)0x72, /* [2549] */ + (xdc_Char)0x69, /* [2550] */ + (xdc_Char)0x5f, /* [2551] */ + (xdc_Char)0x65, /* [2552] */ + (xdc_Char)0x6e, /* [2553] */ + (xdc_Char)0x74, /* [2554] */ + (xdc_Char)0x65, /* [2555] */ + (xdc_Char)0x72, /* [2556] */ + (xdc_Char)0x28, /* [2557] */ + (xdc_Char)0x29, /* [2558] */ + (xdc_Char)0x20, /* [2559] */ + (xdc_Char)0x77, /* [2560] */ + (xdc_Char)0x68, /* [2561] */ + (xdc_Char)0x69, /* [2562] */ + (xdc_Char)0x6c, /* [2563] */ + (xdc_Char)0x65, /* [2564] */ + (xdc_Char)0x20, /* [2565] */ + (xdc_Char)0x74, /* [2566] */ + (xdc_Char)0x68, /* [2567] */ + (xdc_Char)0x65, /* [2568] */ + (xdc_Char)0x20, /* [2569] */ + (xdc_Char)0x54, /* [2570] */ + (xdc_Char)0x61, /* [2571] */ + (xdc_Char)0x73, /* [2572] */ + (xdc_Char)0x6b, /* [2573] */ + (xdc_Char)0x20, /* [2574] */ + (xdc_Char)0x6f, /* [2575] */ + (xdc_Char)0x72, /* [2576] */ + (xdc_Char)0x20, /* [2577] */ + (xdc_Char)0x53, /* [2578] */ + (xdc_Char)0x77, /* [2579] */ + (xdc_Char)0x69, /* [2580] */ + (xdc_Char)0x20, /* [2581] */ + (xdc_Char)0x73, /* [2582] */ + (xdc_Char)0x63, /* [2583] */ + (xdc_Char)0x68, /* [2584] */ + (xdc_Char)0x65, /* [2585] */ + (xdc_Char)0x64, /* [2586] */ + (xdc_Char)0x75, /* [2587] */ + (xdc_Char)0x6c, /* [2588] */ + (xdc_Char)0x65, /* [2589] */ + (xdc_Char)0x72, /* [2590] */ + (xdc_Char)0x20, /* [2591] */ + (xdc_Char)0x69, /* [2592] */ + (xdc_Char)0x73, /* [2593] */ + (xdc_Char)0x20, /* [2594] */ + (xdc_Char)0x64, /* [2595] */ + (xdc_Char)0x69, /* [2596] */ + (xdc_Char)0x73, /* [2597] */ + (xdc_Char)0x61, /* [2598] */ + (xdc_Char)0x62, /* [2599] */ + (xdc_Char)0x6c, /* [2600] */ + (xdc_Char)0x65, /* [2601] */ + (xdc_Char)0x64, /* [2602] */ + (xdc_Char)0x2e, /* [2603] */ + (xdc_Char)0x0, /* [2604] */ + (xdc_Char)0x41, /* [2605] */ + (xdc_Char)0x5f, /* [2606] */ + (xdc_Char)0x62, /* [2607] */ + (xdc_Char)0x61, /* [2608] */ + (xdc_Char)0x64, /* [2609] */ + (xdc_Char)0x43, /* [2610] */ + (xdc_Char)0x6f, /* [2611] */ + (xdc_Char)0x6e, /* [2612] */ + (xdc_Char)0x74, /* [2613] */ + (xdc_Char)0x65, /* [2614] */ + (xdc_Char)0x78, /* [2615] */ + (xdc_Char)0x74, /* [2616] */ + (xdc_Char)0x3a, /* [2617] */ + (xdc_Char)0x20, /* [2618] */ + (xdc_Char)0x62, /* [2619] */ + (xdc_Char)0x61, /* [2620] */ + (xdc_Char)0x64, /* [2621] */ + (xdc_Char)0x20, /* [2622] */ + (xdc_Char)0x63, /* [2623] */ + (xdc_Char)0x61, /* [2624] */ + (xdc_Char)0x6c, /* [2625] */ + (xdc_Char)0x6c, /* [2626] */ + (xdc_Char)0x69, /* [2627] */ + (xdc_Char)0x6e, /* [2628] */ + (xdc_Char)0x67, /* [2629] */ + (xdc_Char)0x20, /* [2630] */ + (xdc_Char)0x63, /* [2631] */ + (xdc_Char)0x6f, /* [2632] */ + (xdc_Char)0x6e, /* [2633] */ + (xdc_Char)0x74, /* [2634] */ + (xdc_Char)0x65, /* [2635] */ + (xdc_Char)0x78, /* [2636] */ + (xdc_Char)0x74, /* [2637] */ + (xdc_Char)0x2e, /* [2638] */ + (xdc_Char)0x20, /* [2639] */ + (xdc_Char)0x53, /* [2640] */ + (xdc_Char)0x65, /* [2641] */ + (xdc_Char)0x65, /* [2642] */ + (xdc_Char)0x20, /* [2643] */ + (xdc_Char)0x47, /* [2644] */ + (xdc_Char)0x61, /* [2645] */ + (xdc_Char)0x74, /* [2646] */ + (xdc_Char)0x65, /* [2647] */ + (xdc_Char)0x4d, /* [2648] */ + (xdc_Char)0x75, /* [2649] */ + (xdc_Char)0x74, /* [2650] */ + (xdc_Char)0x65, /* [2651] */ + (xdc_Char)0x78, /* [2652] */ + (xdc_Char)0x20, /* [2653] */ + (xdc_Char)0x41, /* [2654] */ + (xdc_Char)0x50, /* [2655] */ + (xdc_Char)0x49, /* [2656] */ + (xdc_Char)0x20, /* [2657] */ + (xdc_Char)0x64, /* [2658] */ + (xdc_Char)0x6f, /* [2659] */ + (xdc_Char)0x63, /* [2660] */ + (xdc_Char)0x20, /* [2661] */ + (xdc_Char)0x66, /* [2662] */ + (xdc_Char)0x6f, /* [2663] */ + (xdc_Char)0x72, /* [2664] */ + (xdc_Char)0x20, /* [2665] */ + (xdc_Char)0x64, /* [2666] */ + (xdc_Char)0x65, /* [2667] */ + (xdc_Char)0x74, /* [2668] */ + (xdc_Char)0x61, /* [2669] */ + (xdc_Char)0x69, /* [2670] */ + (xdc_Char)0x6c, /* [2671] */ + (xdc_Char)0x73, /* [2672] */ + (xdc_Char)0x2e, /* [2673] */ + (xdc_Char)0x0, /* [2674] */ + (xdc_Char)0x41, /* [2675] */ + (xdc_Char)0x5f, /* [2676] */ + (xdc_Char)0x62, /* [2677] */ + (xdc_Char)0x61, /* [2678] */ + (xdc_Char)0x64, /* [2679] */ + (xdc_Char)0x43, /* [2680] */ + (xdc_Char)0x6f, /* [2681] */ + (xdc_Char)0x6e, /* [2682] */ + (xdc_Char)0x74, /* [2683] */ + (xdc_Char)0x65, /* [2684] */ + (xdc_Char)0x78, /* [2685] */ + (xdc_Char)0x74, /* [2686] */ + (xdc_Char)0x3a, /* [2687] */ + (xdc_Char)0x20, /* [2688] */ + (xdc_Char)0x62, /* [2689] */ + (xdc_Char)0x61, /* [2690] */ + (xdc_Char)0x64, /* [2691] */ + (xdc_Char)0x20, /* [2692] */ + (xdc_Char)0x63, /* [2693] */ + (xdc_Char)0x61, /* [2694] */ + (xdc_Char)0x6c, /* [2695] */ + (xdc_Char)0x6c, /* [2696] */ + (xdc_Char)0x69, /* [2697] */ + (xdc_Char)0x6e, /* [2698] */ + (xdc_Char)0x67, /* [2699] */ + (xdc_Char)0x20, /* [2700] */ + (xdc_Char)0x63, /* [2701] */ + (xdc_Char)0x6f, /* [2702] */ + (xdc_Char)0x6e, /* [2703] */ + (xdc_Char)0x74, /* [2704] */ + (xdc_Char)0x65, /* [2705] */ + (xdc_Char)0x78, /* [2706] */ + (xdc_Char)0x74, /* [2707] */ + (xdc_Char)0x2e, /* [2708] */ + (xdc_Char)0x20, /* [2709] */ + (xdc_Char)0x53, /* [2710] */ + (xdc_Char)0x65, /* [2711] */ + (xdc_Char)0x65, /* [2712] */ + (xdc_Char)0x20, /* [2713] */ + (xdc_Char)0x47, /* [2714] */ + (xdc_Char)0x61, /* [2715] */ + (xdc_Char)0x74, /* [2716] */ + (xdc_Char)0x65, /* [2717] */ + (xdc_Char)0x53, /* [2718] */ + (xdc_Char)0x70, /* [2719] */ + (xdc_Char)0x69, /* [2720] */ + (xdc_Char)0x6e, /* [2721] */ + (xdc_Char)0x6c, /* [2722] */ + (xdc_Char)0x6f, /* [2723] */ + (xdc_Char)0x63, /* [2724] */ + (xdc_Char)0x6b, /* [2725] */ + (xdc_Char)0x20, /* [2726] */ + (xdc_Char)0x41, /* [2727] */ + (xdc_Char)0x50, /* [2728] */ + (xdc_Char)0x49, /* [2729] */ + (xdc_Char)0x20, /* [2730] */ + (xdc_Char)0x64, /* [2731] */ + (xdc_Char)0x6f, /* [2732] */ + (xdc_Char)0x63, /* [2733] */ + (xdc_Char)0x20, /* [2734] */ + (xdc_Char)0x66, /* [2735] */ + (xdc_Char)0x6f, /* [2736] */ + (xdc_Char)0x72, /* [2737] */ + (xdc_Char)0x20, /* [2738] */ + (xdc_Char)0x64, /* [2739] */ + (xdc_Char)0x65, /* [2740] */ + (xdc_Char)0x74, /* [2741] */ + (xdc_Char)0x61, /* [2742] */ + (xdc_Char)0x69, /* [2743] */ + (xdc_Char)0x6c, /* [2744] */ + (xdc_Char)0x73, /* [2745] */ + (xdc_Char)0x2e, /* [2746] */ + (xdc_Char)0x0, /* [2747] */ + (xdc_Char)0x41, /* [2748] */ + (xdc_Char)0x5f, /* [2749] */ + (xdc_Char)0x69, /* [2750] */ + (xdc_Char)0x6e, /* [2751] */ + (xdc_Char)0x76, /* [2752] */ + (xdc_Char)0x61, /* [2753] */ + (xdc_Char)0x6c, /* [2754] */ + (xdc_Char)0x69, /* [2755] */ + (xdc_Char)0x64, /* [2756] */ + (xdc_Char)0x51, /* [2757] */ + (xdc_Char)0x75, /* [2758] */ + (xdc_Char)0x61, /* [2759] */ + (xdc_Char)0x6c, /* [2760] */ + (xdc_Char)0x69, /* [2761] */ + (xdc_Char)0x74, /* [2762] */ + (xdc_Char)0x79, /* [2763] */ + (xdc_Char)0x3a, /* [2764] */ + (xdc_Char)0x20, /* [2765] */ + (xdc_Char)0x53, /* [2766] */ + (xdc_Char)0x65, /* [2767] */ + (xdc_Char)0x65, /* [2768] */ + (xdc_Char)0x20, /* [2769] */ + (xdc_Char)0x47, /* [2770] */ + (xdc_Char)0x61, /* [2771] */ + (xdc_Char)0x74, /* [2772] */ + (xdc_Char)0x65, /* [2773] */ + (xdc_Char)0x53, /* [2774] */ + (xdc_Char)0x70, /* [2775] */ + (xdc_Char)0x69, /* [2776] */ + (xdc_Char)0x6e, /* [2777] */ + (xdc_Char)0x6c, /* [2778] */ + (xdc_Char)0x6f, /* [2779] */ + (xdc_Char)0x63, /* [2780] */ + (xdc_Char)0x6b, /* [2781] */ + (xdc_Char)0x20, /* [2782] */ + (xdc_Char)0x41, /* [2783] */ + (xdc_Char)0x50, /* [2784] */ + (xdc_Char)0x49, /* [2785] */ + (xdc_Char)0x20, /* [2786] */ + (xdc_Char)0x64, /* [2787] */ + (xdc_Char)0x6f, /* [2788] */ + (xdc_Char)0x63, /* [2789] */ + (xdc_Char)0x20, /* [2790] */ + (xdc_Char)0x66, /* [2791] */ + (xdc_Char)0x6f, /* [2792] */ + (xdc_Char)0x72, /* [2793] */ + (xdc_Char)0x20, /* [2794] */ + (xdc_Char)0x64, /* [2795] */ + (xdc_Char)0x65, /* [2796] */ + (xdc_Char)0x74, /* [2797] */ + (xdc_Char)0x61, /* [2798] */ + (xdc_Char)0x69, /* [2799] */ + (xdc_Char)0x6c, /* [2800] */ + (xdc_Char)0x73, /* [2801] */ + (xdc_Char)0x2e, /* [2802] */ + (xdc_Char)0x0, /* [2803] */ + (xdc_Char)0x62, /* [2804] */ + (xdc_Char)0x75, /* [2805] */ + (xdc_Char)0x66, /* [2806] */ + (xdc_Char)0x20, /* [2807] */ + (xdc_Char)0x70, /* [2808] */ + (xdc_Char)0x61, /* [2809] */ + (xdc_Char)0x72, /* [2810] */ + (xdc_Char)0x61, /* [2811] */ + (xdc_Char)0x6d, /* [2812] */ + (xdc_Char)0x65, /* [2813] */ + (xdc_Char)0x74, /* [2814] */ + (xdc_Char)0x65, /* [2815] */ + (xdc_Char)0x72, /* [2816] */ + (xdc_Char)0x20, /* [2817] */ + (xdc_Char)0x63, /* [2818] */ + (xdc_Char)0x61, /* [2819] */ + (xdc_Char)0x6e, /* [2820] */ + (xdc_Char)0x6e, /* [2821] */ + (xdc_Char)0x6f, /* [2822] */ + (xdc_Char)0x74, /* [2823] */ + (xdc_Char)0x20, /* [2824] */ + (xdc_Char)0x62, /* [2825] */ + (xdc_Char)0x65, /* [2826] */ + (xdc_Char)0x20, /* [2827] */ + (xdc_Char)0x6e, /* [2828] */ + (xdc_Char)0x75, /* [2829] */ + (xdc_Char)0x6c, /* [2830] */ + (xdc_Char)0x6c, /* [2831] */ + (xdc_Char)0x0, /* [2832] */ + (xdc_Char)0x62, /* [2833] */ + (xdc_Char)0x75, /* [2834] */ + (xdc_Char)0x66, /* [2835] */ + (xdc_Char)0x20, /* [2836] */ + (xdc_Char)0x6e, /* [2837] */ + (xdc_Char)0x6f, /* [2838] */ + (xdc_Char)0x74, /* [2839] */ + (xdc_Char)0x20, /* [2840] */ + (xdc_Char)0x70, /* [2841] */ + (xdc_Char)0x72, /* [2842] */ + (xdc_Char)0x6f, /* [2843] */ + (xdc_Char)0x70, /* [2844] */ + (xdc_Char)0x65, /* [2845] */ + (xdc_Char)0x72, /* [2846] */ + (xdc_Char)0x6c, /* [2847] */ + (xdc_Char)0x79, /* [2848] */ + (xdc_Char)0x20, /* [2849] */ + (xdc_Char)0x61, /* [2850] */ + (xdc_Char)0x6c, /* [2851] */ + (xdc_Char)0x69, /* [2852] */ + (xdc_Char)0x67, /* [2853] */ + (xdc_Char)0x6e, /* [2854] */ + (xdc_Char)0x65, /* [2855] */ + (xdc_Char)0x64, /* [2856] */ + (xdc_Char)0x0, /* [2857] */ + (xdc_Char)0x61, /* [2858] */ + (xdc_Char)0x6c, /* [2859] */ + (xdc_Char)0x69, /* [2860] */ + (xdc_Char)0x67, /* [2861] */ + (xdc_Char)0x6e, /* [2862] */ + (xdc_Char)0x20, /* [2863] */ + (xdc_Char)0x70, /* [2864] */ + (xdc_Char)0x61, /* [2865] */ + (xdc_Char)0x72, /* [2866] */ + (xdc_Char)0x61, /* [2867] */ + (xdc_Char)0x6d, /* [2868] */ + (xdc_Char)0x65, /* [2869] */ + (xdc_Char)0x74, /* [2870] */ + (xdc_Char)0x65, /* [2871] */ + (xdc_Char)0x72, /* [2872] */ + (xdc_Char)0x20, /* [2873] */ + (xdc_Char)0x6d, /* [2874] */ + (xdc_Char)0x75, /* [2875] */ + (xdc_Char)0x73, /* [2876] */ + (xdc_Char)0x74, /* [2877] */ + (xdc_Char)0x20, /* [2878] */ + (xdc_Char)0x62, /* [2879] */ + (xdc_Char)0x65, /* [2880] */ + (xdc_Char)0x20, /* [2881] */ + (xdc_Char)0x30, /* [2882] */ + (xdc_Char)0x20, /* [2883] */ + (xdc_Char)0x6f, /* [2884] */ + (xdc_Char)0x72, /* [2885] */ + (xdc_Char)0x20, /* [2886] */ + (xdc_Char)0x61, /* [2887] */ + (xdc_Char)0x20, /* [2888] */ + (xdc_Char)0x70, /* [2889] */ + (xdc_Char)0x6f, /* [2890] */ + (xdc_Char)0x77, /* [2891] */ + (xdc_Char)0x65, /* [2892] */ + (xdc_Char)0x72, /* [2893] */ + (xdc_Char)0x20, /* [2894] */ + (xdc_Char)0x6f, /* [2895] */ + (xdc_Char)0x66, /* [2896] */ + (xdc_Char)0x20, /* [2897] */ + (xdc_Char)0x32, /* [2898] */ + (xdc_Char)0x20, /* [2899] */ + (xdc_Char)0x3e, /* [2900] */ + (xdc_Char)0x3d, /* [2901] */ + (xdc_Char)0x20, /* [2902] */ + (xdc_Char)0x74, /* [2903] */ + (xdc_Char)0x68, /* [2904] */ + (xdc_Char)0x65, /* [2905] */ + (xdc_Char)0x20, /* [2906] */ + (xdc_Char)0x76, /* [2907] */ + (xdc_Char)0x61, /* [2908] */ + (xdc_Char)0x6c, /* [2909] */ + (xdc_Char)0x75, /* [2910] */ + (xdc_Char)0x65, /* [2911] */ + (xdc_Char)0x20, /* [2912] */ + (xdc_Char)0x6f, /* [2913] */ + (xdc_Char)0x66, /* [2914] */ + (xdc_Char)0x20, /* [2915] */ + (xdc_Char)0x4d, /* [2916] */ + (xdc_Char)0x65, /* [2917] */ + (xdc_Char)0x6d, /* [2918] */ + (xdc_Char)0x6f, /* [2919] */ + (xdc_Char)0x72, /* [2920] */ + (xdc_Char)0x79, /* [2921] */ + (xdc_Char)0x5f, /* [2922] */ + (xdc_Char)0x67, /* [2923] */ + (xdc_Char)0x65, /* [2924] */ + (xdc_Char)0x74, /* [2925] */ + (xdc_Char)0x4d, /* [2926] */ + (xdc_Char)0x61, /* [2927] */ + (xdc_Char)0x78, /* [2928] */ + (xdc_Char)0x44, /* [2929] */ + (xdc_Char)0x65, /* [2930] */ + (xdc_Char)0x66, /* [2931] */ + (xdc_Char)0x61, /* [2932] */ + (xdc_Char)0x75, /* [2933] */ + (xdc_Char)0x6c, /* [2934] */ + (xdc_Char)0x74, /* [2935] */ + (xdc_Char)0x54, /* [2936] */ + (xdc_Char)0x79, /* [2937] */ + (xdc_Char)0x70, /* [2938] */ + (xdc_Char)0x65, /* [2939] */ + (xdc_Char)0x41, /* [2940] */ + (xdc_Char)0x6c, /* [2941] */ + (xdc_Char)0x69, /* [2942] */ + (xdc_Char)0x67, /* [2943] */ + (xdc_Char)0x6e, /* [2944] */ + (xdc_Char)0x28, /* [2945] */ + (xdc_Char)0x29, /* [2946] */ + (xdc_Char)0x0, /* [2947] */ + (xdc_Char)0x61, /* [2948] */ + (xdc_Char)0x6c, /* [2949] */ + (xdc_Char)0x69, /* [2950] */ + (xdc_Char)0x67, /* [2951] */ + (xdc_Char)0x6e, /* [2952] */ + (xdc_Char)0x20, /* [2953] */ + (xdc_Char)0x70, /* [2954] */ + (xdc_Char)0x61, /* [2955] */ + (xdc_Char)0x72, /* [2956] */ + (xdc_Char)0x61, /* [2957] */ + (xdc_Char)0x6d, /* [2958] */ + (xdc_Char)0x65, /* [2959] */ + (xdc_Char)0x74, /* [2960] */ + (xdc_Char)0x65, /* [2961] */ + (xdc_Char)0x72, /* [2962] */ + (xdc_Char)0x20, /* [2963] */ + (xdc_Char)0x31, /* [2964] */ + (xdc_Char)0x29, /* [2965] */ + (xdc_Char)0x20, /* [2966] */ + (xdc_Char)0x6d, /* [2967] */ + (xdc_Char)0x75, /* [2968] */ + (xdc_Char)0x73, /* [2969] */ + (xdc_Char)0x74, /* [2970] */ + (xdc_Char)0x20, /* [2971] */ + (xdc_Char)0x62, /* [2972] */ + (xdc_Char)0x65, /* [2973] */ + (xdc_Char)0x20, /* [2974] */ + (xdc_Char)0x30, /* [2975] */ + (xdc_Char)0x20, /* [2976] */ + (xdc_Char)0x6f, /* [2977] */ + (xdc_Char)0x72, /* [2978] */ + (xdc_Char)0x20, /* [2979] */ + (xdc_Char)0x61, /* [2980] */ + (xdc_Char)0x20, /* [2981] */ + (xdc_Char)0x70, /* [2982] */ + (xdc_Char)0x6f, /* [2983] */ + (xdc_Char)0x77, /* [2984] */ + (xdc_Char)0x65, /* [2985] */ + (xdc_Char)0x72, /* [2986] */ + (xdc_Char)0x20, /* [2987] */ + (xdc_Char)0x6f, /* [2988] */ + (xdc_Char)0x66, /* [2989] */ + (xdc_Char)0x20, /* [2990] */ + (xdc_Char)0x32, /* [2991] */ + (xdc_Char)0x20, /* [2992] */ + (xdc_Char)0x61, /* [2993] */ + (xdc_Char)0x6e, /* [2994] */ + (xdc_Char)0x64, /* [2995] */ + (xdc_Char)0x20, /* [2996] */ + (xdc_Char)0x32, /* [2997] */ + (xdc_Char)0x29, /* [2998] */ + (xdc_Char)0x20, /* [2999] */ + (xdc_Char)0x6e, /* [3000] */ + (xdc_Char)0x6f, /* [3001] */ + (xdc_Char)0x74, /* [3002] */ + (xdc_Char)0x20, /* [3003] */ + (xdc_Char)0x67, /* [3004] */ + (xdc_Char)0x72, /* [3005] */ + (xdc_Char)0x65, /* [3006] */ + (xdc_Char)0x61, /* [3007] */ + (xdc_Char)0x74, /* [3008] */ + (xdc_Char)0x65, /* [3009] */ + (xdc_Char)0x72, /* [3010] */ + (xdc_Char)0x20, /* [3011] */ + (xdc_Char)0x74, /* [3012] */ + (xdc_Char)0x68, /* [3013] */ + (xdc_Char)0x61, /* [3014] */ + (xdc_Char)0x6e, /* [3015] */ + (xdc_Char)0x20, /* [3016] */ + (xdc_Char)0x74, /* [3017] */ + (xdc_Char)0x68, /* [3018] */ + (xdc_Char)0x65, /* [3019] */ + (xdc_Char)0x20, /* [3020] */ + (xdc_Char)0x68, /* [3021] */ + (xdc_Char)0x65, /* [3022] */ + (xdc_Char)0x61, /* [3023] */ + (xdc_Char)0x70, /* [3024] */ + (xdc_Char)0x73, /* [3025] */ + (xdc_Char)0x20, /* [3026] */ + (xdc_Char)0x61, /* [3027] */ + (xdc_Char)0x6c, /* [3028] */ + (xdc_Char)0x69, /* [3029] */ + (xdc_Char)0x67, /* [3030] */ + (xdc_Char)0x6e, /* [3031] */ + (xdc_Char)0x6d, /* [3032] */ + (xdc_Char)0x65, /* [3033] */ + (xdc_Char)0x6e, /* [3034] */ + (xdc_Char)0x74, /* [3035] */ + (xdc_Char)0x0, /* [3036] */ + (xdc_Char)0x62, /* [3037] */ + (xdc_Char)0x6c, /* [3038] */ + (xdc_Char)0x6f, /* [3039] */ + (xdc_Char)0x63, /* [3040] */ + (xdc_Char)0x6b, /* [3041] */ + (xdc_Char)0x53, /* [3042] */ + (xdc_Char)0x69, /* [3043] */ + (xdc_Char)0x7a, /* [3044] */ + (xdc_Char)0x65, /* [3045] */ + (xdc_Char)0x20, /* [3046] */ + (xdc_Char)0x6d, /* [3047] */ + (xdc_Char)0x75, /* [3048] */ + (xdc_Char)0x73, /* [3049] */ + (xdc_Char)0x74, /* [3050] */ + (xdc_Char)0x20, /* [3051] */ + (xdc_Char)0x62, /* [3052] */ + (xdc_Char)0x65, /* [3053] */ + (xdc_Char)0x20, /* [3054] */ + (xdc_Char)0x6c, /* [3055] */ + (xdc_Char)0x61, /* [3056] */ + (xdc_Char)0x72, /* [3057] */ + (xdc_Char)0x67, /* [3058] */ + (xdc_Char)0x65, /* [3059] */ + (xdc_Char)0x20, /* [3060] */ + (xdc_Char)0x65, /* [3061] */ + (xdc_Char)0x6e, /* [3062] */ + (xdc_Char)0x6f, /* [3063] */ + (xdc_Char)0x75, /* [3064] */ + (xdc_Char)0x67, /* [3065] */ + (xdc_Char)0x68, /* [3066] */ + (xdc_Char)0x20, /* [3067] */ + (xdc_Char)0x74, /* [3068] */ + (xdc_Char)0x6f, /* [3069] */ + (xdc_Char)0x20, /* [3070] */ + (xdc_Char)0x68, /* [3071] */ + (xdc_Char)0x6f, /* [3072] */ + (xdc_Char)0x6c, /* [3073] */ + (xdc_Char)0x64, /* [3074] */ + (xdc_Char)0x20, /* [3075] */ + (xdc_Char)0x61, /* [3076] */ + (xdc_Char)0x74, /* [3077] */ + (xdc_Char)0x6c, /* [3078] */ + (xdc_Char)0x65, /* [3079] */ + (xdc_Char)0x61, /* [3080] */ + (xdc_Char)0x73, /* [3081] */ + (xdc_Char)0x74, /* [3082] */ + (xdc_Char)0x20, /* [3083] */ + (xdc_Char)0x74, /* [3084] */ + (xdc_Char)0x77, /* [3085] */ + (xdc_Char)0x6f, /* [3086] */ + (xdc_Char)0x20, /* [3087] */ + (xdc_Char)0x70, /* [3088] */ + (xdc_Char)0x6f, /* [3089] */ + (xdc_Char)0x69, /* [3090] */ + (xdc_Char)0x6e, /* [3091] */ + (xdc_Char)0x74, /* [3092] */ + (xdc_Char)0x65, /* [3093] */ + (xdc_Char)0x72, /* [3094] */ + (xdc_Char)0x73, /* [3095] */ + (xdc_Char)0x0, /* [3096] */ + (xdc_Char)0x6e, /* [3097] */ + (xdc_Char)0x75, /* [3098] */ + (xdc_Char)0x6d, /* [3099] */ + (xdc_Char)0x42, /* [3100] */ + (xdc_Char)0x6c, /* [3101] */ + (xdc_Char)0x6f, /* [3102] */ + (xdc_Char)0x63, /* [3103] */ + (xdc_Char)0x6b, /* [3104] */ + (xdc_Char)0x73, /* [3105] */ + (xdc_Char)0x20, /* [3106] */ + (xdc_Char)0x63, /* [3107] */ + (xdc_Char)0x61, /* [3108] */ + (xdc_Char)0x6e, /* [3109] */ + (xdc_Char)0x6e, /* [3110] */ + (xdc_Char)0x6f, /* [3111] */ + (xdc_Char)0x74, /* [3112] */ + (xdc_Char)0x20, /* [3113] */ + (xdc_Char)0x62, /* [3114] */ + (xdc_Char)0x65, /* [3115] */ + (xdc_Char)0x20, /* [3116] */ + (xdc_Char)0x7a, /* [3117] */ + (xdc_Char)0x65, /* [3118] */ + (xdc_Char)0x72, /* [3119] */ + (xdc_Char)0x6f, /* [3120] */ + (xdc_Char)0x0, /* [3121] */ + (xdc_Char)0x62, /* [3122] */ + (xdc_Char)0x75, /* [3123] */ + (xdc_Char)0x66, /* [3124] */ + (xdc_Char)0x53, /* [3125] */ + (xdc_Char)0x69, /* [3126] */ + (xdc_Char)0x7a, /* [3127] */ + (xdc_Char)0x65, /* [3128] */ + (xdc_Char)0x20, /* [3129] */ + (xdc_Char)0x63, /* [3130] */ + (xdc_Char)0x61, /* [3131] */ + (xdc_Char)0x6e, /* [3132] */ + (xdc_Char)0x6e, /* [3133] */ + (xdc_Char)0x6f, /* [3134] */ + (xdc_Char)0x74, /* [3135] */ + (xdc_Char)0x20, /* [3136] */ + (xdc_Char)0x62, /* [3137] */ + (xdc_Char)0x65, /* [3138] */ + (xdc_Char)0x20, /* [3139] */ + (xdc_Char)0x7a, /* [3140] */ + (xdc_Char)0x65, /* [3141] */ + (xdc_Char)0x72, /* [3142] */ + (xdc_Char)0x6f, /* [3143] */ + (xdc_Char)0x0, /* [3144] */ + (xdc_Char)0x48, /* [3145] */ + (xdc_Char)0x65, /* [3146] */ + (xdc_Char)0x61, /* [3147] */ + (xdc_Char)0x70, /* [3148] */ + (xdc_Char)0x42, /* [3149] */ + (xdc_Char)0x75, /* [3150] */ + (xdc_Char)0x66, /* [3151] */ + (xdc_Char)0x5f, /* [3152] */ + (xdc_Char)0x63, /* [3153] */ + (xdc_Char)0x72, /* [3154] */ + (xdc_Char)0x65, /* [3155] */ + (xdc_Char)0x61, /* [3156] */ + (xdc_Char)0x74, /* [3157] */ + (xdc_Char)0x65, /* [3158] */ + (xdc_Char)0x27, /* [3159] */ + (xdc_Char)0x73, /* [3160] */ + (xdc_Char)0x20, /* [3161] */ + (xdc_Char)0x62, /* [3162] */ + (xdc_Char)0x75, /* [3163] */ + (xdc_Char)0x66, /* [3164] */ + (xdc_Char)0x53, /* [3165] */ + (xdc_Char)0x69, /* [3166] */ + (xdc_Char)0x7a, /* [3167] */ + (xdc_Char)0x65, /* [3168] */ + (xdc_Char)0x20, /* [3169] */ + (xdc_Char)0x70, /* [3170] */ + (xdc_Char)0x61, /* [3171] */ + (xdc_Char)0x72, /* [3172] */ + (xdc_Char)0x61, /* [3173] */ + (xdc_Char)0x6d, /* [3174] */ + (xdc_Char)0x65, /* [3175] */ + (xdc_Char)0x74, /* [3176] */ + (xdc_Char)0x65, /* [3177] */ + (xdc_Char)0x72, /* [3178] */ + (xdc_Char)0x20, /* [3179] */ + (xdc_Char)0x69, /* [3180] */ + (xdc_Char)0x73, /* [3181] */ + (xdc_Char)0x20, /* [3182] */ + (xdc_Char)0x69, /* [3183] */ + (xdc_Char)0x6e, /* [3184] */ + (xdc_Char)0x76, /* [3185] */ + (xdc_Char)0x61, /* [3186] */ + (xdc_Char)0x6c, /* [3187] */ + (xdc_Char)0x69, /* [3188] */ + (xdc_Char)0x64, /* [3189] */ + (xdc_Char)0x20, /* [3190] */ + (xdc_Char)0x28, /* [3191] */ + (xdc_Char)0x74, /* [3192] */ + (xdc_Char)0x6f, /* [3193] */ + (xdc_Char)0x6f, /* [3194] */ + (xdc_Char)0x20, /* [3195] */ + (xdc_Char)0x73, /* [3196] */ + (xdc_Char)0x6d, /* [3197] */ + (xdc_Char)0x61, /* [3198] */ + (xdc_Char)0x6c, /* [3199] */ + (xdc_Char)0x6c, /* [3200] */ + (xdc_Char)0x29, /* [3201] */ + (xdc_Char)0x0, /* [3202] */ + (xdc_Char)0x43, /* [3203] */ + (xdc_Char)0x61, /* [3204] */ + (xdc_Char)0x6e, /* [3205] */ + (xdc_Char)0x6e, /* [3206] */ + (xdc_Char)0x6f, /* [3207] */ + (xdc_Char)0x74, /* [3208] */ + (xdc_Char)0x20, /* [3209] */ + (xdc_Char)0x63, /* [3210] */ + (xdc_Char)0x61, /* [3211] */ + (xdc_Char)0x6c, /* [3212] */ + (xdc_Char)0x6c, /* [3213] */ + (xdc_Char)0x20, /* [3214] */ + (xdc_Char)0x48, /* [3215] */ + (xdc_Char)0x65, /* [3216] */ + (xdc_Char)0x61, /* [3217] */ + (xdc_Char)0x70, /* [3218] */ + (xdc_Char)0x42, /* [3219] */ + (xdc_Char)0x75, /* [3220] */ + (xdc_Char)0x66, /* [3221] */ + (xdc_Char)0x5f, /* [3222] */ + (xdc_Char)0x66, /* [3223] */ + (xdc_Char)0x72, /* [3224] */ + (xdc_Char)0x65, /* [3225] */ + (xdc_Char)0x65, /* [3226] */ + (xdc_Char)0x20, /* [3227] */ + (xdc_Char)0x77, /* [3228] */ + (xdc_Char)0x68, /* [3229] */ + (xdc_Char)0x65, /* [3230] */ + (xdc_Char)0x6e, /* [3231] */ + (xdc_Char)0x20, /* [3232] */ + (xdc_Char)0x6e, /* [3233] */ + (xdc_Char)0x6f, /* [3234] */ + (xdc_Char)0x20, /* [3235] */ + (xdc_Char)0x62, /* [3236] */ + (xdc_Char)0x6c, /* [3237] */ + (xdc_Char)0x6f, /* [3238] */ + (xdc_Char)0x63, /* [3239] */ + (xdc_Char)0x6b, /* [3240] */ + (xdc_Char)0x73, /* [3241] */ + (xdc_Char)0x20, /* [3242] */ + (xdc_Char)0x68, /* [3243] */ + (xdc_Char)0x61, /* [3244] */ + (xdc_Char)0x76, /* [3245] */ + (xdc_Char)0x65, /* [3246] */ + (xdc_Char)0x20, /* [3247] */ + (xdc_Char)0x62, /* [3248] */ + (xdc_Char)0x65, /* [3249] */ + (xdc_Char)0x65, /* [3250] */ + (xdc_Char)0x6e, /* [3251] */ + (xdc_Char)0x20, /* [3252] */ + (xdc_Char)0x61, /* [3253] */ + (xdc_Char)0x6c, /* [3254] */ + (xdc_Char)0x6c, /* [3255] */ + (xdc_Char)0x6f, /* [3256] */ + (xdc_Char)0x63, /* [3257] */ + (xdc_Char)0x61, /* [3258] */ + (xdc_Char)0x74, /* [3259] */ + (xdc_Char)0x65, /* [3260] */ + (xdc_Char)0x64, /* [3261] */ + (xdc_Char)0x0, /* [3262] */ + (xdc_Char)0x41, /* [3263] */ + (xdc_Char)0x5f, /* [3264] */ + (xdc_Char)0x69, /* [3265] */ + (xdc_Char)0x6e, /* [3266] */ + (xdc_Char)0x76, /* [3267] */ + (xdc_Char)0x61, /* [3268] */ + (xdc_Char)0x6c, /* [3269] */ + (xdc_Char)0x69, /* [3270] */ + (xdc_Char)0x64, /* [3271] */ + (xdc_Char)0x46, /* [3272] */ + (xdc_Char)0x72, /* [3273] */ + (xdc_Char)0x65, /* [3274] */ + (xdc_Char)0x65, /* [3275] */ + (xdc_Char)0x3a, /* [3276] */ + (xdc_Char)0x20, /* [3277] */ + (xdc_Char)0x49, /* [3278] */ + (xdc_Char)0x6e, /* [3279] */ + (xdc_Char)0x76, /* [3280] */ + (xdc_Char)0x61, /* [3281] */ + (xdc_Char)0x6c, /* [3282] */ + (xdc_Char)0x69, /* [3283] */ + (xdc_Char)0x64, /* [3284] */ + (xdc_Char)0x20, /* [3285] */ + (xdc_Char)0x66, /* [3286] */ + (xdc_Char)0x72, /* [3287] */ + (xdc_Char)0x65, /* [3288] */ + (xdc_Char)0x65, /* [3289] */ + (xdc_Char)0x0, /* [3290] */ + (xdc_Char)0x41, /* [3291] */ + (xdc_Char)0x5f, /* [3292] */ + (xdc_Char)0x7a, /* [3293] */ + (xdc_Char)0x65, /* [3294] */ + (xdc_Char)0x72, /* [3295] */ + (xdc_Char)0x6f, /* [3296] */ + (xdc_Char)0x42, /* [3297] */ + (xdc_Char)0x6c, /* [3298] */ + (xdc_Char)0x6f, /* [3299] */ + (xdc_Char)0x63, /* [3300] */ + (xdc_Char)0x6b, /* [3301] */ + (xdc_Char)0x3a, /* [3302] */ + (xdc_Char)0x20, /* [3303] */ + (xdc_Char)0x43, /* [3304] */ + (xdc_Char)0x61, /* [3305] */ + (xdc_Char)0x6e, /* [3306] */ + (xdc_Char)0x6e, /* [3307] */ + (xdc_Char)0x6f, /* [3308] */ + (xdc_Char)0x74, /* [3309] */ + (xdc_Char)0x20, /* [3310] */ + (xdc_Char)0x61, /* [3311] */ + (xdc_Char)0x6c, /* [3312] */ + (xdc_Char)0x6c, /* [3313] */ + (xdc_Char)0x6f, /* [3314] */ + (xdc_Char)0x63, /* [3315] */ + (xdc_Char)0x61, /* [3316] */ + (xdc_Char)0x74, /* [3317] */ + (xdc_Char)0x65, /* [3318] */ + (xdc_Char)0x20, /* [3319] */ + (xdc_Char)0x73, /* [3320] */ + (xdc_Char)0x69, /* [3321] */ + (xdc_Char)0x7a, /* [3322] */ + (xdc_Char)0x65, /* [3323] */ + (xdc_Char)0x20, /* [3324] */ + (xdc_Char)0x30, /* [3325] */ + (xdc_Char)0x0, /* [3326] */ + (xdc_Char)0x41, /* [3327] */ + (xdc_Char)0x5f, /* [3328] */ + (xdc_Char)0x68, /* [3329] */ + (xdc_Char)0x65, /* [3330] */ + (xdc_Char)0x61, /* [3331] */ + (xdc_Char)0x70, /* [3332] */ + (xdc_Char)0x53, /* [3333] */ + (xdc_Char)0x69, /* [3334] */ + (xdc_Char)0x7a, /* [3335] */ + (xdc_Char)0x65, /* [3336] */ + (xdc_Char)0x3a, /* [3337] */ + (xdc_Char)0x20, /* [3338] */ + (xdc_Char)0x52, /* [3339] */ + (xdc_Char)0x65, /* [3340] */ + (xdc_Char)0x71, /* [3341] */ + (xdc_Char)0x75, /* [3342] */ + (xdc_Char)0x65, /* [3343] */ + (xdc_Char)0x73, /* [3344] */ + (xdc_Char)0x74, /* [3345] */ + (xdc_Char)0x65, /* [3346] */ + (xdc_Char)0x64, /* [3347] */ + (xdc_Char)0x20, /* [3348] */ + (xdc_Char)0x68, /* [3349] */ + (xdc_Char)0x65, /* [3350] */ + (xdc_Char)0x61, /* [3351] */ + (xdc_Char)0x70, /* [3352] */ + (xdc_Char)0x20, /* [3353] */ + (xdc_Char)0x73, /* [3354] */ + (xdc_Char)0x69, /* [3355] */ + (xdc_Char)0x7a, /* [3356] */ + (xdc_Char)0x65, /* [3357] */ + (xdc_Char)0x20, /* [3358] */ + (xdc_Char)0x69, /* [3359] */ + (xdc_Char)0x73, /* [3360] */ + (xdc_Char)0x20, /* [3361] */ + (xdc_Char)0x74, /* [3362] */ + (xdc_Char)0x6f, /* [3363] */ + (xdc_Char)0x6f, /* [3364] */ + (xdc_Char)0x20, /* [3365] */ + (xdc_Char)0x73, /* [3366] */ + (xdc_Char)0x6d, /* [3367] */ + (xdc_Char)0x61, /* [3368] */ + (xdc_Char)0x6c, /* [3369] */ + (xdc_Char)0x6c, /* [3370] */ + (xdc_Char)0x0, /* [3371] */ + (xdc_Char)0x41, /* [3372] */ + (xdc_Char)0x5f, /* [3373] */ + (xdc_Char)0x61, /* [3374] */ + (xdc_Char)0x6c, /* [3375] */ + (xdc_Char)0x69, /* [3376] */ + (xdc_Char)0x67, /* [3377] */ + (xdc_Char)0x6e, /* [3378] */ + (xdc_Char)0x3a, /* [3379] */ + (xdc_Char)0x20, /* [3380] */ + (xdc_Char)0x52, /* [3381] */ + (xdc_Char)0x65, /* [3382] */ + (xdc_Char)0x71, /* [3383] */ + (xdc_Char)0x75, /* [3384] */ + (xdc_Char)0x65, /* [3385] */ + (xdc_Char)0x73, /* [3386] */ + (xdc_Char)0x74, /* [3387] */ + (xdc_Char)0x65, /* [3388] */ + (xdc_Char)0x64, /* [3389] */ + (xdc_Char)0x20, /* [3390] */ + (xdc_Char)0x61, /* [3391] */ + (xdc_Char)0x6c, /* [3392] */ + (xdc_Char)0x69, /* [3393] */ + (xdc_Char)0x67, /* [3394] */ + (xdc_Char)0x6e, /* [3395] */ + (xdc_Char)0x20, /* [3396] */ + (xdc_Char)0x69, /* [3397] */ + (xdc_Char)0x73, /* [3398] */ + (xdc_Char)0x20, /* [3399] */ + (xdc_Char)0x6e, /* [3400] */ + (xdc_Char)0x6f, /* [3401] */ + (xdc_Char)0x74, /* [3402] */ + (xdc_Char)0x20, /* [3403] */ + (xdc_Char)0x61, /* [3404] */ + (xdc_Char)0x20, /* [3405] */ + (xdc_Char)0x70, /* [3406] */ + (xdc_Char)0x6f, /* [3407] */ + (xdc_Char)0x77, /* [3408] */ + (xdc_Char)0x65, /* [3409] */ + (xdc_Char)0x72, /* [3410] */ + (xdc_Char)0x20, /* [3411] */ + (xdc_Char)0x6f, /* [3412] */ + (xdc_Char)0x66, /* [3413] */ + (xdc_Char)0x20, /* [3414] */ + (xdc_Char)0x32, /* [3415] */ + (xdc_Char)0x0, /* [3416] */ + (xdc_Char)0x49, /* [3417] */ + (xdc_Char)0x6e, /* [3418] */ + (xdc_Char)0x76, /* [3419] */ + (xdc_Char)0x61, /* [3420] */ + (xdc_Char)0x6c, /* [3421] */ + (xdc_Char)0x69, /* [3422] */ + (xdc_Char)0x64, /* [3423] */ + (xdc_Char)0x20, /* [3424] */ + (xdc_Char)0x62, /* [3425] */ + (xdc_Char)0x6c, /* [3426] */ + (xdc_Char)0x6f, /* [3427] */ + (xdc_Char)0x63, /* [3428] */ + (xdc_Char)0x6b, /* [3429] */ + (xdc_Char)0x20, /* [3430] */ + (xdc_Char)0x61, /* [3431] */ + (xdc_Char)0x64, /* [3432] */ + (xdc_Char)0x64, /* [3433] */ + (xdc_Char)0x72, /* [3434] */ + (xdc_Char)0x65, /* [3435] */ + (xdc_Char)0x73, /* [3436] */ + (xdc_Char)0x73, /* [3437] */ + (xdc_Char)0x20, /* [3438] */ + (xdc_Char)0x6f, /* [3439] */ + (xdc_Char)0x6e, /* [3440] */ + (xdc_Char)0x20, /* [3441] */ + (xdc_Char)0x74, /* [3442] */ + (xdc_Char)0x68, /* [3443] */ + (xdc_Char)0x65, /* [3444] */ + (xdc_Char)0x20, /* [3445] */ + (xdc_Char)0x66, /* [3446] */ + (xdc_Char)0x72, /* [3447] */ + (xdc_Char)0x65, /* [3448] */ + (xdc_Char)0x65, /* [3449] */ + (xdc_Char)0x2e, /* [3450] */ + (xdc_Char)0x20, /* [3451] */ + (xdc_Char)0x46, /* [3452] */ + (xdc_Char)0x61, /* [3453] */ + (xdc_Char)0x69, /* [3454] */ + (xdc_Char)0x6c, /* [3455] */ + (xdc_Char)0x65, /* [3456] */ + (xdc_Char)0x64, /* [3457] */ + (xdc_Char)0x20, /* [3458] */ + (xdc_Char)0x74, /* [3459] */ + (xdc_Char)0x6f, /* [3460] */ + (xdc_Char)0x20, /* [3461] */ + (xdc_Char)0x66, /* [3462] */ + (xdc_Char)0x72, /* [3463] */ + (xdc_Char)0x65, /* [3464] */ + (xdc_Char)0x65, /* [3465] */ + (xdc_Char)0x20, /* [3466] */ + (xdc_Char)0x62, /* [3467] */ + (xdc_Char)0x6c, /* [3468] */ + (xdc_Char)0x6f, /* [3469] */ + (xdc_Char)0x63, /* [3470] */ + (xdc_Char)0x6b, /* [3471] */ + (xdc_Char)0x20, /* [3472] */ + (xdc_Char)0x62, /* [3473] */ + (xdc_Char)0x61, /* [3474] */ + (xdc_Char)0x63, /* [3475] */ + (xdc_Char)0x6b, /* [3476] */ + (xdc_Char)0x20, /* [3477] */ + (xdc_Char)0x74, /* [3478] */ + (xdc_Char)0x6f, /* [3479] */ + (xdc_Char)0x20, /* [3480] */ + (xdc_Char)0x68, /* [3481] */ + (xdc_Char)0x65, /* [3482] */ + (xdc_Char)0x61, /* [3483] */ + (xdc_Char)0x70, /* [3484] */ + (xdc_Char)0x2e, /* [3485] */ + (xdc_Char)0x0, /* [3486] */ + (xdc_Char)0x41, /* [3487] */ + (xdc_Char)0x5f, /* [3488] */ + (xdc_Char)0x64, /* [3489] */ + (xdc_Char)0x6f, /* [3490] */ + (xdc_Char)0x75, /* [3491] */ + (xdc_Char)0x62, /* [3492] */ + (xdc_Char)0x6c, /* [3493] */ + (xdc_Char)0x65, /* [3494] */ + (xdc_Char)0x46, /* [3495] */ + (xdc_Char)0x72, /* [3496] */ + (xdc_Char)0x65, /* [3497] */ + (xdc_Char)0x65, /* [3498] */ + (xdc_Char)0x3a, /* [3499] */ + (xdc_Char)0x20, /* [3500] */ + (xdc_Char)0x42, /* [3501] */ + (xdc_Char)0x75, /* [3502] */ + (xdc_Char)0x66, /* [3503] */ + (xdc_Char)0x66, /* [3504] */ + (xdc_Char)0x65, /* [3505] */ + (xdc_Char)0x72, /* [3506] */ + (xdc_Char)0x20, /* [3507] */ + (xdc_Char)0x61, /* [3508] */ + (xdc_Char)0x6c, /* [3509] */ + (xdc_Char)0x72, /* [3510] */ + (xdc_Char)0x65, /* [3511] */ + (xdc_Char)0x61, /* [3512] */ + (xdc_Char)0x64, /* [3513] */ + (xdc_Char)0x79, /* [3514] */ + (xdc_Char)0x20, /* [3515] */ + (xdc_Char)0x66, /* [3516] */ + (xdc_Char)0x72, /* [3517] */ + (xdc_Char)0x65, /* [3518] */ + (xdc_Char)0x65, /* [3519] */ + (xdc_Char)0x0, /* [3520] */ + (xdc_Char)0x41, /* [3521] */ + (xdc_Char)0x5f, /* [3522] */ + (xdc_Char)0x62, /* [3523] */ + (xdc_Char)0x75, /* [3524] */ + (xdc_Char)0x66, /* [3525] */ + (xdc_Char)0x4f, /* [3526] */ + (xdc_Char)0x76, /* [3527] */ + (xdc_Char)0x65, /* [3528] */ + (xdc_Char)0x72, /* [3529] */ + (xdc_Char)0x66, /* [3530] */ + (xdc_Char)0x6c, /* [3531] */ + (xdc_Char)0x6f, /* [3532] */ + (xdc_Char)0x77, /* [3533] */ + (xdc_Char)0x3a, /* [3534] */ + (xdc_Char)0x20, /* [3535] */ + (xdc_Char)0x42, /* [3536] */ + (xdc_Char)0x75, /* [3537] */ + (xdc_Char)0x66, /* [3538] */ + (xdc_Char)0x66, /* [3539] */ + (xdc_Char)0x65, /* [3540] */ + (xdc_Char)0x72, /* [3541] */ + (xdc_Char)0x20, /* [3542] */ + (xdc_Char)0x6f, /* [3543] */ + (xdc_Char)0x76, /* [3544] */ + (xdc_Char)0x65, /* [3545] */ + (xdc_Char)0x72, /* [3546] */ + (xdc_Char)0x66, /* [3547] */ + (xdc_Char)0x6c, /* [3548] */ + (xdc_Char)0x6f, /* [3549] */ + (xdc_Char)0x77, /* [3550] */ + (xdc_Char)0x0, /* [3551] */ + (xdc_Char)0x41, /* [3552] */ + (xdc_Char)0x5f, /* [3553] */ + (xdc_Char)0x6e, /* [3554] */ + (xdc_Char)0x6f, /* [3555] */ + (xdc_Char)0x74, /* [3556] */ + (xdc_Char)0x45, /* [3557] */ + (xdc_Char)0x6d, /* [3558] */ + (xdc_Char)0x70, /* [3559] */ + (xdc_Char)0x74, /* [3560] */ + (xdc_Char)0x79, /* [3561] */ + (xdc_Char)0x3a, /* [3562] */ + (xdc_Char)0x20, /* [3563] */ + (xdc_Char)0x48, /* [3564] */ + (xdc_Char)0x65, /* [3565] */ + (xdc_Char)0x61, /* [3566] */ + (xdc_Char)0x70, /* [3567] */ + (xdc_Char)0x20, /* [3568] */ + (xdc_Char)0x6e, /* [3569] */ + (xdc_Char)0x6f, /* [3570] */ + (xdc_Char)0x74, /* [3571] */ + (xdc_Char)0x20, /* [3572] */ + (xdc_Char)0x65, /* [3573] */ + (xdc_Char)0x6d, /* [3574] */ + (xdc_Char)0x70, /* [3575] */ + (xdc_Char)0x74, /* [3576] */ + (xdc_Char)0x79, /* [3577] */ + (xdc_Char)0x0, /* [3578] */ + (xdc_Char)0x41, /* [3579] */ + (xdc_Char)0x5f, /* [3580] */ + (xdc_Char)0x6e, /* [3581] */ + (xdc_Char)0x75, /* [3582] */ + (xdc_Char)0x6c, /* [3583] */ + (xdc_Char)0x6c, /* [3584] */ + (xdc_Char)0x4f, /* [3585] */ + (xdc_Char)0x62, /* [3586] */ + (xdc_Char)0x6a, /* [3587] */ + (xdc_Char)0x65, /* [3588] */ + (xdc_Char)0x63, /* [3589] */ + (xdc_Char)0x74, /* [3590] */ + (xdc_Char)0x3a, /* [3591] */ + (xdc_Char)0x20, /* [3592] */ + (xdc_Char)0x48, /* [3593] */ + (xdc_Char)0x65, /* [3594] */ + (xdc_Char)0x61, /* [3595] */ + (xdc_Char)0x70, /* [3596] */ + (xdc_Char)0x54, /* [3597] */ + (xdc_Char)0x72, /* [3598] */ + (xdc_Char)0x61, /* [3599] */ + (xdc_Char)0x63, /* [3600] */ + (xdc_Char)0x6b, /* [3601] */ + (xdc_Char)0x5f, /* [3602] */ + (xdc_Char)0x70, /* [3603] */ + (xdc_Char)0x72, /* [3604] */ + (xdc_Char)0x69, /* [3605] */ + (xdc_Char)0x6e, /* [3606] */ + (xdc_Char)0x74, /* [3607] */ + (xdc_Char)0x48, /* [3608] */ + (xdc_Char)0x65, /* [3609] */ + (xdc_Char)0x61, /* [3610] */ + (xdc_Char)0x70, /* [3611] */ + (xdc_Char)0x20, /* [3612] */ + (xdc_Char)0x63, /* [3613] */ + (xdc_Char)0x61, /* [3614] */ + (xdc_Char)0x6c, /* [3615] */ + (xdc_Char)0x6c, /* [3616] */ + (xdc_Char)0x65, /* [3617] */ + (xdc_Char)0x64, /* [3618] */ + (xdc_Char)0x20, /* [3619] */ + (xdc_Char)0x77, /* [3620] */ + (xdc_Char)0x69, /* [3621] */ + (xdc_Char)0x74, /* [3622] */ + (xdc_Char)0x68, /* [3623] */ + (xdc_Char)0x20, /* [3624] */ + (xdc_Char)0x6e, /* [3625] */ + (xdc_Char)0x75, /* [3626] */ + (xdc_Char)0x6c, /* [3627] */ + (xdc_Char)0x6c, /* [3628] */ + (xdc_Char)0x20, /* [3629] */ + (xdc_Char)0x6f, /* [3630] */ + (xdc_Char)0x62, /* [3631] */ + (xdc_Char)0x6a, /* [3632] */ + (xdc_Char)0x0, /* [3633] */ + (xdc_Char)0x61, /* [3634] */ + (xdc_Char)0x73, /* [3635] */ + (xdc_Char)0x73, /* [3636] */ + (xdc_Char)0x65, /* [3637] */ + (xdc_Char)0x72, /* [3638] */ + (xdc_Char)0x74, /* [3639] */ + (xdc_Char)0x69, /* [3640] */ + (xdc_Char)0x6f, /* [3641] */ + (xdc_Char)0x6e, /* [3642] */ + (xdc_Char)0x20, /* [3643] */ + (xdc_Char)0x66, /* [3644] */ + (xdc_Char)0x61, /* [3645] */ + (xdc_Char)0x69, /* [3646] */ + (xdc_Char)0x6c, /* [3647] */ + (xdc_Char)0x75, /* [3648] */ + (xdc_Char)0x72, /* [3649] */ + (xdc_Char)0x65, /* [3650] */ + (xdc_Char)0x25, /* [3651] */ + (xdc_Char)0x73, /* [3652] */ + (xdc_Char)0x25, /* [3653] */ + (xdc_Char)0x73, /* [3654] */ + (xdc_Char)0x0, /* [3655] */ + (xdc_Char)0x25, /* [3656] */ + (xdc_Char)0x24, /* [3657] */ + (xdc_Char)0x53, /* [3658] */ + (xdc_Char)0x0, /* [3659] */ + (xdc_Char)0x6f, /* [3660] */ + (xdc_Char)0x75, /* [3661] */ + (xdc_Char)0x74, /* [3662] */ + (xdc_Char)0x20, /* [3663] */ + (xdc_Char)0x6f, /* [3664] */ + (xdc_Char)0x66, /* [3665] */ + (xdc_Char)0x20, /* [3666] */ + (xdc_Char)0x6d, /* [3667] */ + (xdc_Char)0x65, /* [3668] */ + (xdc_Char)0x6d, /* [3669] */ + (xdc_Char)0x6f, /* [3670] */ + (xdc_Char)0x72, /* [3671] */ + (xdc_Char)0x79, /* [3672] */ + (xdc_Char)0x3a, /* [3673] */ + (xdc_Char)0x20, /* [3674] */ + (xdc_Char)0x68, /* [3675] */ + (xdc_Char)0x65, /* [3676] */ + (xdc_Char)0x61, /* [3677] */ + (xdc_Char)0x70, /* [3678] */ + (xdc_Char)0x3d, /* [3679] */ + (xdc_Char)0x30, /* [3680] */ + (xdc_Char)0x78, /* [3681] */ + (xdc_Char)0x25, /* [3682] */ + (xdc_Char)0x78, /* [3683] */ + (xdc_Char)0x2c, /* [3684] */ + (xdc_Char)0x20, /* [3685] */ + (xdc_Char)0x73, /* [3686] */ + (xdc_Char)0x69, /* [3687] */ + (xdc_Char)0x7a, /* [3688] */ + (xdc_Char)0x65, /* [3689] */ + (xdc_Char)0x3d, /* [3690] */ + (xdc_Char)0x25, /* [3691] */ + (xdc_Char)0x75, /* [3692] */ + (xdc_Char)0x0, /* [3693] */ + (xdc_Char)0x25, /* [3694] */ + (xdc_Char)0x73, /* [3695] */ + (xdc_Char)0x20, /* [3696] */ + (xdc_Char)0x30, /* [3697] */ + (xdc_Char)0x78, /* [3698] */ + (xdc_Char)0x25, /* [3699] */ + (xdc_Char)0x78, /* [3700] */ + (xdc_Char)0x0, /* [3701] */ + (xdc_Char)0x45, /* [3702] */ + (xdc_Char)0x5f, /* [3703] */ + (xdc_Char)0x62, /* [3704] */ + (xdc_Char)0x61, /* [3705] */ + (xdc_Char)0x64, /* [3706] */ + (xdc_Char)0x4c, /* [3707] */ + (xdc_Char)0x65, /* [3708] */ + (xdc_Char)0x76, /* [3709] */ + (xdc_Char)0x65, /* [3710] */ + (xdc_Char)0x6c, /* [3711] */ + (xdc_Char)0x3a, /* [3712] */ + (xdc_Char)0x20, /* [3713] */ + (xdc_Char)0x42, /* [3714] */ + (xdc_Char)0x61, /* [3715] */ + (xdc_Char)0x64, /* [3716] */ + (xdc_Char)0x20, /* [3717] */ + (xdc_Char)0x66, /* [3718] */ + (xdc_Char)0x69, /* [3719] */ + (xdc_Char)0x6c, /* [3720] */ + (xdc_Char)0x74, /* [3721] */ + (xdc_Char)0x65, /* [3722] */ + (xdc_Char)0x72, /* [3723] */ + (xdc_Char)0x20, /* [3724] */ + (xdc_Char)0x6c, /* [3725] */ + (xdc_Char)0x65, /* [3726] */ + (xdc_Char)0x76, /* [3727] */ + (xdc_Char)0x65, /* [3728] */ + (xdc_Char)0x6c, /* [3729] */ + (xdc_Char)0x20, /* [3730] */ + (xdc_Char)0x76, /* [3731] */ + (xdc_Char)0x61, /* [3732] */ + (xdc_Char)0x6c, /* [3733] */ + (xdc_Char)0x75, /* [3734] */ + (xdc_Char)0x65, /* [3735] */ + (xdc_Char)0x3a, /* [3736] */ + (xdc_Char)0x20, /* [3737] */ + (xdc_Char)0x25, /* [3738] */ + (xdc_Char)0x64, /* [3739] */ + (xdc_Char)0x0, /* [3740] */ + (xdc_Char)0x66, /* [3741] */ + (xdc_Char)0x72, /* [3742] */ + (xdc_Char)0x65, /* [3743] */ + (xdc_Char)0x65, /* [3744] */ + (xdc_Char)0x28, /* [3745] */ + (xdc_Char)0x29, /* [3746] */ + (xdc_Char)0x20, /* [3747] */ + (xdc_Char)0x69, /* [3748] */ + (xdc_Char)0x6e, /* [3749] */ + (xdc_Char)0x76, /* [3750] */ + (xdc_Char)0x61, /* [3751] */ + (xdc_Char)0x6c, /* [3752] */ + (xdc_Char)0x69, /* [3753] */ + (xdc_Char)0x64, /* [3754] */ + (xdc_Char)0x20, /* [3755] */ + (xdc_Char)0x69, /* [3756] */ + (xdc_Char)0x6e, /* [3757] */ + (xdc_Char)0x20, /* [3758] */ + (xdc_Char)0x67, /* [3759] */ + (xdc_Char)0x72, /* [3760] */ + (xdc_Char)0x6f, /* [3761] */ + (xdc_Char)0x77, /* [3762] */ + (xdc_Char)0x74, /* [3763] */ + (xdc_Char)0x68, /* [3764] */ + (xdc_Char)0x2d, /* [3765] */ + (xdc_Char)0x6f, /* [3766] */ + (xdc_Char)0x6e, /* [3767] */ + (xdc_Char)0x6c, /* [3768] */ + (xdc_Char)0x79, /* [3769] */ + (xdc_Char)0x20, /* [3770] */ + (xdc_Char)0x48, /* [3771] */ + (xdc_Char)0x65, /* [3772] */ + (xdc_Char)0x61, /* [3773] */ + (xdc_Char)0x70, /* [3774] */ + (xdc_Char)0x4d, /* [3775] */ + (xdc_Char)0x69, /* [3776] */ + (xdc_Char)0x6e, /* [3777] */ + (xdc_Char)0x0, /* [3778] */ + (xdc_Char)0x54, /* [3779] */ + (xdc_Char)0x68, /* [3780] */ + (xdc_Char)0x65, /* [3781] */ + (xdc_Char)0x20, /* [3782] */ + (xdc_Char)0x52, /* [3783] */ + (xdc_Char)0x54, /* [3784] */ + (xdc_Char)0x53, /* [3785] */ + (xdc_Char)0x20, /* [3786] */ + (xdc_Char)0x68, /* [3787] */ + (xdc_Char)0x65, /* [3788] */ + (xdc_Char)0x61, /* [3789] */ + (xdc_Char)0x70, /* [3790] */ + (xdc_Char)0x20, /* [3791] */ + (xdc_Char)0x69, /* [3792] */ + (xdc_Char)0x73, /* [3793] */ + (xdc_Char)0x20, /* [3794] */ + (xdc_Char)0x75, /* [3795] */ + (xdc_Char)0x73, /* [3796] */ + (xdc_Char)0x65, /* [3797] */ + (xdc_Char)0x64, /* [3798] */ + (xdc_Char)0x20, /* [3799] */ + (xdc_Char)0x75, /* [3800] */ + (xdc_Char)0x70, /* [3801] */ + (xdc_Char)0x2e, /* [3802] */ + (xdc_Char)0x20, /* [3803] */ + (xdc_Char)0x45, /* [3804] */ + (xdc_Char)0x78, /* [3805] */ + (xdc_Char)0x61, /* [3806] */ + (xdc_Char)0x6d, /* [3807] */ + (xdc_Char)0x69, /* [3808] */ + (xdc_Char)0x6e, /* [3809] */ + (xdc_Char)0x65, /* [3810] */ + (xdc_Char)0x20, /* [3811] */ + (xdc_Char)0x50, /* [3812] */ + (xdc_Char)0x72, /* [3813] */ + (xdc_Char)0x6f, /* [3814] */ + (xdc_Char)0x67, /* [3815] */ + (xdc_Char)0x72, /* [3816] */ + (xdc_Char)0x61, /* [3817] */ + (xdc_Char)0x6d, /* [3818] */ + (xdc_Char)0x2e, /* [3819] */ + (xdc_Char)0x68, /* [3820] */ + (xdc_Char)0x65, /* [3821] */ + (xdc_Char)0x61, /* [3822] */ + (xdc_Char)0x70, /* [3823] */ + (xdc_Char)0x2e, /* [3824] */ + (xdc_Char)0x0, /* [3825] */ + (xdc_Char)0x45, /* [3826] */ + (xdc_Char)0x5f, /* [3827] */ + (xdc_Char)0x62, /* [3828] */ + (xdc_Char)0x61, /* [3829] */ + (xdc_Char)0x64, /* [3830] */ + (xdc_Char)0x43, /* [3831] */ + (xdc_Char)0x6f, /* [3832] */ + (xdc_Char)0x6d, /* [3833] */ + (xdc_Char)0x6d, /* [3834] */ + (xdc_Char)0x61, /* [3835] */ + (xdc_Char)0x6e, /* [3836] */ + (xdc_Char)0x64, /* [3837] */ + (xdc_Char)0x3a, /* [3838] */ + (xdc_Char)0x20, /* [3839] */ + (xdc_Char)0x52, /* [3840] */ + (xdc_Char)0x65, /* [3841] */ + (xdc_Char)0x63, /* [3842] */ + (xdc_Char)0x65, /* [3843] */ + (xdc_Char)0x69, /* [3844] */ + (xdc_Char)0x76, /* [3845] */ + (xdc_Char)0x65, /* [3846] */ + (xdc_Char)0x64, /* [3847] */ + (xdc_Char)0x20, /* [3848] */ + (xdc_Char)0x69, /* [3849] */ + (xdc_Char)0x6e, /* [3850] */ + (xdc_Char)0x76, /* [3851] */ + (xdc_Char)0x61, /* [3852] */ + (xdc_Char)0x6c, /* [3853] */ + (xdc_Char)0x69, /* [3854] */ + (xdc_Char)0x64, /* [3855] */ + (xdc_Char)0x20, /* [3856] */ + (xdc_Char)0x63, /* [3857] */ + (xdc_Char)0x6f, /* [3858] */ + (xdc_Char)0x6d, /* [3859] */ + (xdc_Char)0x6d, /* [3860] */ + (xdc_Char)0x61, /* [3861] */ + (xdc_Char)0x6e, /* [3862] */ + (xdc_Char)0x64, /* [3863] */ + (xdc_Char)0x2c, /* [3864] */ + (xdc_Char)0x20, /* [3865] */ + (xdc_Char)0x69, /* [3866] */ + (xdc_Char)0x64, /* [3867] */ + (xdc_Char)0x3a, /* [3868] */ + (xdc_Char)0x20, /* [3869] */ + (xdc_Char)0x25, /* [3870] */ + (xdc_Char)0x64, /* [3871] */ + (xdc_Char)0x2e, /* [3872] */ + (xdc_Char)0x0, /* [3873] */ + (xdc_Char)0x45, /* [3874] */ + (xdc_Char)0x5f, /* [3875] */ + (xdc_Char)0x73, /* [3876] */ + (xdc_Char)0x74, /* [3877] */ + (xdc_Char)0x61, /* [3878] */ + (xdc_Char)0x63, /* [3879] */ + (xdc_Char)0x6b, /* [3880] */ + (xdc_Char)0x4f, /* [3881] */ + (xdc_Char)0x76, /* [3882] */ + (xdc_Char)0x65, /* [3883] */ + (xdc_Char)0x72, /* [3884] */ + (xdc_Char)0x66, /* [3885] */ + (xdc_Char)0x6c, /* [3886] */ + (xdc_Char)0x6f, /* [3887] */ + (xdc_Char)0x77, /* [3888] */ + (xdc_Char)0x3a, /* [3889] */ + (xdc_Char)0x20, /* [3890] */ + (xdc_Char)0x54, /* [3891] */ + (xdc_Char)0x61, /* [3892] */ + (xdc_Char)0x73, /* [3893] */ + (xdc_Char)0x6b, /* [3894] */ + (xdc_Char)0x20, /* [3895] */ + (xdc_Char)0x30, /* [3896] */ + (xdc_Char)0x78, /* [3897] */ + (xdc_Char)0x25, /* [3898] */ + (xdc_Char)0x78, /* [3899] */ + (xdc_Char)0x20, /* [3900] */ + (xdc_Char)0x73, /* [3901] */ + (xdc_Char)0x74, /* [3902] */ + (xdc_Char)0x61, /* [3903] */ + (xdc_Char)0x63, /* [3904] */ + (xdc_Char)0x6b, /* [3905] */ + (xdc_Char)0x20, /* [3906] */ + (xdc_Char)0x6f, /* [3907] */ + (xdc_Char)0x76, /* [3908] */ + (xdc_Char)0x65, /* [3909] */ + (xdc_Char)0x72, /* [3910] */ + (xdc_Char)0x66, /* [3911] */ + (xdc_Char)0x6c, /* [3912] */ + (xdc_Char)0x6f, /* [3913] */ + (xdc_Char)0x77, /* [3914] */ + (xdc_Char)0x2e, /* [3915] */ + (xdc_Char)0x0, /* [3916] */ + (xdc_Char)0x45, /* [3917] */ + (xdc_Char)0x5f, /* [3918] */ + (xdc_Char)0x73, /* [3919] */ + (xdc_Char)0x70, /* [3920] */ + (xdc_Char)0x4f, /* [3921] */ + (xdc_Char)0x75, /* [3922] */ + (xdc_Char)0x74, /* [3923] */ + (xdc_Char)0x4f, /* [3924] */ + (xdc_Char)0x66, /* [3925] */ + (xdc_Char)0x42, /* [3926] */ + (xdc_Char)0x6f, /* [3927] */ + (xdc_Char)0x75, /* [3928] */ + (xdc_Char)0x6e, /* [3929] */ + (xdc_Char)0x64, /* [3930] */ + (xdc_Char)0x73, /* [3931] */ + (xdc_Char)0x3a, /* [3932] */ + (xdc_Char)0x20, /* [3933] */ + (xdc_Char)0x54, /* [3934] */ + (xdc_Char)0x61, /* [3935] */ + (xdc_Char)0x73, /* [3936] */ + (xdc_Char)0x6b, /* [3937] */ + (xdc_Char)0x20, /* [3938] */ + (xdc_Char)0x30, /* [3939] */ + (xdc_Char)0x78, /* [3940] */ + (xdc_Char)0x25, /* [3941] */ + (xdc_Char)0x78, /* [3942] */ + (xdc_Char)0x20, /* [3943] */ + (xdc_Char)0x73, /* [3944] */ + (xdc_Char)0x74, /* [3945] */ + (xdc_Char)0x61, /* [3946] */ + (xdc_Char)0x63, /* [3947] */ + (xdc_Char)0x6b, /* [3948] */ + (xdc_Char)0x20, /* [3949] */ + (xdc_Char)0x65, /* [3950] */ + (xdc_Char)0x72, /* [3951] */ + (xdc_Char)0x72, /* [3952] */ + (xdc_Char)0x6f, /* [3953] */ + (xdc_Char)0x72, /* [3954] */ + (xdc_Char)0x2c, /* [3955] */ + (xdc_Char)0x20, /* [3956] */ + (xdc_Char)0x53, /* [3957] */ + (xdc_Char)0x50, /* [3958] */ + (xdc_Char)0x20, /* [3959] */ + (xdc_Char)0x3d, /* [3960] */ + (xdc_Char)0x20, /* [3961] */ + (xdc_Char)0x30, /* [3962] */ + (xdc_Char)0x78, /* [3963] */ + (xdc_Char)0x25, /* [3964] */ + (xdc_Char)0x78, /* [3965] */ + (xdc_Char)0x2e, /* [3966] */ + (xdc_Char)0x0, /* [3967] */ + (xdc_Char)0x45, /* [3968] */ + (xdc_Char)0x5f, /* [3969] */ + (xdc_Char)0x64, /* [3970] */ + (xdc_Char)0x65, /* [3971] */ + (xdc_Char)0x6c, /* [3972] */ + (xdc_Char)0x65, /* [3973] */ + (xdc_Char)0x74, /* [3974] */ + (xdc_Char)0x65, /* [3975] */ + (xdc_Char)0x4e, /* [3976] */ + (xdc_Char)0x6f, /* [3977] */ + (xdc_Char)0x74, /* [3978] */ + (xdc_Char)0x41, /* [3979] */ + (xdc_Char)0x6c, /* [3980] */ + (xdc_Char)0x6c, /* [3981] */ + (xdc_Char)0x6f, /* [3982] */ + (xdc_Char)0x77, /* [3983] */ + (xdc_Char)0x65, /* [3984] */ + (xdc_Char)0x64, /* [3985] */ + (xdc_Char)0x3a, /* [3986] */ + (xdc_Char)0x20, /* [3987] */ + (xdc_Char)0x54, /* [3988] */ + (xdc_Char)0x61, /* [3989] */ + (xdc_Char)0x73, /* [3990] */ + (xdc_Char)0x6b, /* [3991] */ + (xdc_Char)0x20, /* [3992] */ + (xdc_Char)0x30, /* [3993] */ + (xdc_Char)0x78, /* [3994] */ + (xdc_Char)0x25, /* [3995] */ + (xdc_Char)0x78, /* [3996] */ + (xdc_Char)0x2e, /* [3997] */ + (xdc_Char)0x0, /* [3998] */ + (xdc_Char)0x45, /* [3999] */ + (xdc_Char)0x5f, /* [4000] */ + (xdc_Char)0x73, /* [4001] */ + (xdc_Char)0x74, /* [4002] */ + (xdc_Char)0x61, /* [4003] */ + (xdc_Char)0x63, /* [4004] */ + (xdc_Char)0x6b, /* [4005] */ + (xdc_Char)0x4f, /* [4006] */ + (xdc_Char)0x76, /* [4007] */ + (xdc_Char)0x65, /* [4008] */ + (xdc_Char)0x72, /* [4009] */ + (xdc_Char)0x66, /* [4010] */ + (xdc_Char)0x6c, /* [4011] */ + (xdc_Char)0x6f, /* [4012] */ + (xdc_Char)0x77, /* [4013] */ + (xdc_Char)0x3a, /* [4014] */ + (xdc_Char)0x20, /* [4015] */ + (xdc_Char)0x49, /* [4016] */ + (xdc_Char)0x53, /* [4017] */ + (xdc_Char)0x52, /* [4018] */ + (xdc_Char)0x20, /* [4019] */ + (xdc_Char)0x73, /* [4020] */ + (xdc_Char)0x74, /* [4021] */ + (xdc_Char)0x61, /* [4022] */ + (xdc_Char)0x63, /* [4023] */ + (xdc_Char)0x6b, /* [4024] */ + (xdc_Char)0x20, /* [4025] */ + (xdc_Char)0x6f, /* [4026] */ + (xdc_Char)0x76, /* [4027] */ + (xdc_Char)0x65, /* [4028] */ + (xdc_Char)0x72, /* [4029] */ + (xdc_Char)0x66, /* [4030] */ + (xdc_Char)0x6c, /* [4031] */ + (xdc_Char)0x6f, /* [4032] */ + (xdc_Char)0x77, /* [4033] */ + (xdc_Char)0x2e, /* [4034] */ + (xdc_Char)0x0, /* [4035] */ + (xdc_Char)0x45, /* [4036] */ + (xdc_Char)0x5f, /* [4037] */ + (xdc_Char)0x61, /* [4038] */ + (xdc_Char)0x6c, /* [4039] */ + (xdc_Char)0x72, /* [4040] */ + (xdc_Char)0x65, /* [4041] */ + (xdc_Char)0x61, /* [4042] */ + (xdc_Char)0x64, /* [4043] */ + (xdc_Char)0x79, /* [4044] */ + (xdc_Char)0x44, /* [4045] */ + (xdc_Char)0x65, /* [4046] */ + (xdc_Char)0x66, /* [4047] */ + (xdc_Char)0x69, /* [4048] */ + (xdc_Char)0x6e, /* [4049] */ + (xdc_Char)0x65, /* [4050] */ + (xdc_Char)0x64, /* [4051] */ + (xdc_Char)0x3a, /* [4052] */ + (xdc_Char)0x20, /* [4053] */ + (xdc_Char)0x48, /* [4054] */ + (xdc_Char)0x77, /* [4055] */ + (xdc_Char)0x69, /* [4056] */ + (xdc_Char)0x20, /* [4057] */ + (xdc_Char)0x61, /* [4058] */ + (xdc_Char)0x6c, /* [4059] */ + (xdc_Char)0x72, /* [4060] */ + (xdc_Char)0x65, /* [4061] */ + (xdc_Char)0x61, /* [4062] */ + (xdc_Char)0x64, /* [4063] */ + (xdc_Char)0x79, /* [4064] */ + (xdc_Char)0x20, /* [4065] */ + (xdc_Char)0x64, /* [4066] */ + (xdc_Char)0x65, /* [4067] */ + (xdc_Char)0x66, /* [4068] */ + (xdc_Char)0x69, /* [4069] */ + (xdc_Char)0x6e, /* [4070] */ + (xdc_Char)0x65, /* [4071] */ + (xdc_Char)0x64, /* [4072] */ + (xdc_Char)0x3a, /* [4073] */ + (xdc_Char)0x20, /* [4074] */ + (xdc_Char)0x69, /* [4075] */ + (xdc_Char)0x6e, /* [4076] */ + (xdc_Char)0x74, /* [4077] */ + (xdc_Char)0x72, /* [4078] */ + (xdc_Char)0x23, /* [4079] */ + (xdc_Char)0x20, /* [4080] */ + (xdc_Char)0x25, /* [4081] */ + (xdc_Char)0x64, /* [4082] */ + (xdc_Char)0x0, /* [4083] */ + (xdc_Char)0x45, /* [4084] */ + (xdc_Char)0x5f, /* [4085] */ + (xdc_Char)0x68, /* [4086] */ + (xdc_Char)0x77, /* [4087] */ + (xdc_Char)0x69, /* [4088] */ + (xdc_Char)0x4c, /* [4089] */ + (xdc_Char)0x69, /* [4090] */ + (xdc_Char)0x6d, /* [4091] */ + (xdc_Char)0x69, /* [4092] */ + (xdc_Char)0x74, /* [4093] */ + (xdc_Char)0x45, /* [4094] */ + (xdc_Char)0x78, /* [4095] */ + (xdc_Char)0x63, /* [4096] */ + (xdc_Char)0x65, /* [4097] */ + (xdc_Char)0x65, /* [4098] */ + (xdc_Char)0x64, /* [4099] */ + (xdc_Char)0x65, /* [4100] */ + (xdc_Char)0x64, /* [4101] */ + (xdc_Char)0x3a, /* [4102] */ + (xdc_Char)0x20, /* [4103] */ + (xdc_Char)0x54, /* [4104] */ + (xdc_Char)0x6f, /* [4105] */ + (xdc_Char)0x6f, /* [4106] */ + (xdc_Char)0x20, /* [4107] */ + (xdc_Char)0x6d, /* [4108] */ + (xdc_Char)0x61, /* [4109] */ + (xdc_Char)0x6e, /* [4110] */ + (xdc_Char)0x79, /* [4111] */ + (xdc_Char)0x20, /* [4112] */ + (xdc_Char)0x69, /* [4113] */ + (xdc_Char)0x6e, /* [4114] */ + (xdc_Char)0x74, /* [4115] */ + (xdc_Char)0x65, /* [4116] */ + (xdc_Char)0x72, /* [4117] */ + (xdc_Char)0x72, /* [4118] */ + (xdc_Char)0x75, /* [4119] */ + (xdc_Char)0x70, /* [4120] */ + (xdc_Char)0x74, /* [4121] */ + (xdc_Char)0x73, /* [4122] */ + (xdc_Char)0x20, /* [4123] */ + (xdc_Char)0x64, /* [4124] */ + (xdc_Char)0x65, /* [4125] */ + (xdc_Char)0x66, /* [4126] */ + (xdc_Char)0x69, /* [4127] */ + (xdc_Char)0x6e, /* [4128] */ + (xdc_Char)0x65, /* [4129] */ + (xdc_Char)0x64, /* [4130] */ + (xdc_Char)0x0, /* [4131] */ + (xdc_Char)0x45, /* [4132] */ + (xdc_Char)0x5f, /* [4133] */ + (xdc_Char)0x65, /* [4134] */ + (xdc_Char)0x78, /* [4135] */ + (xdc_Char)0x63, /* [4136] */ + (xdc_Char)0x65, /* [4137] */ + (xdc_Char)0x70, /* [4138] */ + (xdc_Char)0x74, /* [4139] */ + (xdc_Char)0x69, /* [4140] */ + (xdc_Char)0x6f, /* [4141] */ + (xdc_Char)0x6e, /* [4142] */ + (xdc_Char)0x3a, /* [4143] */ + (xdc_Char)0x20, /* [4144] */ + (xdc_Char)0x69, /* [4145] */ + (xdc_Char)0x64, /* [4146] */ + (xdc_Char)0x20, /* [4147] */ + (xdc_Char)0x3d, /* [4148] */ + (xdc_Char)0x20, /* [4149] */ + (xdc_Char)0x25, /* [4150] */ + (xdc_Char)0x64, /* [4151] */ + (xdc_Char)0x2c, /* [4152] */ + (xdc_Char)0x20, /* [4153] */ + (xdc_Char)0x70, /* [4154] */ + (xdc_Char)0x63, /* [4155] */ + (xdc_Char)0x20, /* [4156] */ + (xdc_Char)0x3d, /* [4157] */ + (xdc_Char)0x20, /* [4158] */ + (xdc_Char)0x25, /* [4159] */ + (xdc_Char)0x30, /* [4160] */ + (xdc_Char)0x38, /* [4161] */ + (xdc_Char)0x78, /* [4162] */ + (xdc_Char)0x2e, /* [4163] */ + (xdc_Char)0xa, /* [4164] */ + (xdc_Char)0x54, /* [4165] */ + (xdc_Char)0x6f, /* [4166] */ + (xdc_Char)0x20, /* [4167] */ + (xdc_Char)0x73, /* [4168] */ + (xdc_Char)0x65, /* [4169] */ + (xdc_Char)0x65, /* [4170] */ + (xdc_Char)0x20, /* [4171] */ + (xdc_Char)0x6d, /* [4172] */ + (xdc_Char)0x6f, /* [4173] */ + (xdc_Char)0x72, /* [4174] */ + (xdc_Char)0x65, /* [4175] */ + (xdc_Char)0x20, /* [4176] */ + (xdc_Char)0x65, /* [4177] */ + (xdc_Char)0x78, /* [4178] */ + (xdc_Char)0x63, /* [4179] */ + (xdc_Char)0x65, /* [4180] */ + (xdc_Char)0x70, /* [4181] */ + (xdc_Char)0x74, /* [4182] */ + (xdc_Char)0x69, /* [4183] */ + (xdc_Char)0x6f, /* [4184] */ + (xdc_Char)0x6e, /* [4185] */ + (xdc_Char)0x20, /* [4186] */ + (xdc_Char)0x64, /* [4187] */ + (xdc_Char)0x65, /* [4188] */ + (xdc_Char)0x74, /* [4189] */ + (xdc_Char)0x61, /* [4190] */ + (xdc_Char)0x69, /* [4191] */ + (xdc_Char)0x6c, /* [4192] */ + (xdc_Char)0x2c, /* [4193] */ + (xdc_Char)0x20, /* [4194] */ + (xdc_Char)0x73, /* [4195] */ + (xdc_Char)0x65, /* [4196] */ + (xdc_Char)0x74, /* [4197] */ + (xdc_Char)0x20, /* [4198] */ + (xdc_Char)0x74, /* [4199] */ + (xdc_Char)0x69, /* [4200] */ + (xdc_Char)0x2e, /* [4201] */ + (xdc_Char)0x73, /* [4202] */ + (xdc_Char)0x79, /* [4203] */ + (xdc_Char)0x73, /* [4204] */ + (xdc_Char)0x62, /* [4205] */ + (xdc_Char)0x69, /* [4206] */ + (xdc_Char)0x6f, /* [4207] */ + (xdc_Char)0x73, /* [4208] */ + (xdc_Char)0x2e, /* [4209] */ + (xdc_Char)0x66, /* [4210] */ + (xdc_Char)0x61, /* [4211] */ + (xdc_Char)0x6d, /* [4212] */ + (xdc_Char)0x69, /* [4213] */ + (xdc_Char)0x6c, /* [4214] */ + (xdc_Char)0x79, /* [4215] */ + (xdc_Char)0x2e, /* [4216] */ + (xdc_Char)0x61, /* [4217] */ + (xdc_Char)0x72, /* [4218] */ + (xdc_Char)0x6d, /* [4219] */ + (xdc_Char)0x2e, /* [4220] */ + (xdc_Char)0x6d, /* [4221] */ + (xdc_Char)0x33, /* [4222] */ + (xdc_Char)0x2e, /* [4223] */ + (xdc_Char)0x48, /* [4224] */ + (xdc_Char)0x77, /* [4225] */ + (xdc_Char)0x69, /* [4226] */ + (xdc_Char)0x2e, /* [4227] */ + (xdc_Char)0x65, /* [4228] */ + (xdc_Char)0x6e, /* [4229] */ + (xdc_Char)0x61, /* [4230] */ + (xdc_Char)0x62, /* [4231] */ + (xdc_Char)0x6c, /* [4232] */ + (xdc_Char)0x65, /* [4233] */ + (xdc_Char)0x45, /* [4234] */ + (xdc_Char)0x78, /* [4235] */ + (xdc_Char)0x63, /* [4236] */ + (xdc_Char)0x65, /* [4237] */ + (xdc_Char)0x70, /* [4238] */ + (xdc_Char)0x74, /* [4239] */ + (xdc_Char)0x69, /* [4240] */ + (xdc_Char)0x6f, /* [4241] */ + (xdc_Char)0x6e, /* [4242] */ + (xdc_Char)0x20, /* [4243] */ + (xdc_Char)0x3d, /* [4244] */ + (xdc_Char)0x20, /* [4245] */ + (xdc_Char)0x74, /* [4246] */ + (xdc_Char)0x72, /* [4247] */ + (xdc_Char)0x75, /* [4248] */ + (xdc_Char)0x65, /* [4249] */ + (xdc_Char)0x20, /* [4250] */ + (xdc_Char)0x6f, /* [4251] */ + (xdc_Char)0x72, /* [4252] */ + (xdc_Char)0x2c, /* [4253] */ + (xdc_Char)0xa, /* [4254] */ + (xdc_Char)0x65, /* [4255] */ + (xdc_Char)0x78, /* [4256] */ + (xdc_Char)0x61, /* [4257] */ + (xdc_Char)0x6d, /* [4258] */ + (xdc_Char)0x69, /* [4259] */ + (xdc_Char)0x6e, /* [4260] */ + (xdc_Char)0x65, /* [4261] */ + (xdc_Char)0x20, /* [4262] */ + (xdc_Char)0x74, /* [4263] */ + (xdc_Char)0x68, /* [4264] */ + (xdc_Char)0x65, /* [4265] */ + (xdc_Char)0x20, /* [4266] */ + (xdc_Char)0x45, /* [4267] */ + (xdc_Char)0x78, /* [4268] */ + (xdc_Char)0x63, /* [4269] */ + (xdc_Char)0x65, /* [4270] */ + (xdc_Char)0x70, /* [4271] */ + (xdc_Char)0x74, /* [4272] */ + (xdc_Char)0x69, /* [4273] */ + (xdc_Char)0x6f, /* [4274] */ + (xdc_Char)0x6e, /* [4275] */ + (xdc_Char)0x20, /* [4276] */ + (xdc_Char)0x76, /* [4277] */ + (xdc_Char)0x69, /* [4278] */ + (xdc_Char)0x65, /* [4279] */ + (xdc_Char)0x77, /* [4280] */ + (xdc_Char)0x20, /* [4281] */ + (xdc_Char)0x66, /* [4282] */ + (xdc_Char)0x6f, /* [4283] */ + (xdc_Char)0x72, /* [4284] */ + (xdc_Char)0x20, /* [4285] */ + (xdc_Char)0x74, /* [4286] */ + (xdc_Char)0x68, /* [4287] */ + (xdc_Char)0x65, /* [4288] */ + (xdc_Char)0x20, /* [4289] */ + (xdc_Char)0x74, /* [4290] */ + (xdc_Char)0x69, /* [4291] */ + (xdc_Char)0x2e, /* [4292] */ + (xdc_Char)0x73, /* [4293] */ + (xdc_Char)0x79, /* [4294] */ + (xdc_Char)0x73, /* [4295] */ + (xdc_Char)0x62, /* [4296] */ + (xdc_Char)0x69, /* [4297] */ + (xdc_Char)0x6f, /* [4298] */ + (xdc_Char)0x73, /* [4299] */ + (xdc_Char)0x2e, /* [4300] */ + (xdc_Char)0x66, /* [4301] */ + (xdc_Char)0x61, /* [4302] */ + (xdc_Char)0x6d, /* [4303] */ + (xdc_Char)0x69, /* [4304] */ + (xdc_Char)0x6c, /* [4305] */ + (xdc_Char)0x79, /* [4306] */ + (xdc_Char)0x2e, /* [4307] */ + (xdc_Char)0x61, /* [4308] */ + (xdc_Char)0x72, /* [4309] */ + (xdc_Char)0x6d, /* [4310] */ + (xdc_Char)0x2e, /* [4311] */ + (xdc_Char)0x6d, /* [4312] */ + (xdc_Char)0x33, /* [4313] */ + (xdc_Char)0x2e, /* [4314] */ + (xdc_Char)0x48, /* [4315] */ + (xdc_Char)0x77, /* [4316] */ + (xdc_Char)0x69, /* [4317] */ + (xdc_Char)0x20, /* [4318] */ + (xdc_Char)0x6d, /* [4319] */ + (xdc_Char)0x6f, /* [4320] */ + (xdc_Char)0x64, /* [4321] */ + (xdc_Char)0x75, /* [4322] */ + (xdc_Char)0x6c, /* [4323] */ + (xdc_Char)0x65, /* [4324] */ + (xdc_Char)0x20, /* [4325] */ + (xdc_Char)0x75, /* [4326] */ + (xdc_Char)0x73, /* [4327] */ + (xdc_Char)0x69, /* [4328] */ + (xdc_Char)0x6e, /* [4329] */ + (xdc_Char)0x67, /* [4330] */ + (xdc_Char)0x20, /* [4331] */ + (xdc_Char)0x52, /* [4332] */ + (xdc_Char)0x4f, /* [4333] */ + (xdc_Char)0x56, /* [4334] */ + (xdc_Char)0x2e, /* [4335] */ + (xdc_Char)0x0, /* [4336] */ + (xdc_Char)0x45, /* [4337] */ + (xdc_Char)0x5f, /* [4338] */ + (xdc_Char)0x6e, /* [4339] */ + (xdc_Char)0x6f, /* [4340] */ + (xdc_Char)0x49, /* [4341] */ + (xdc_Char)0x73, /* [4342] */ + (xdc_Char)0x72, /* [4343] */ + (xdc_Char)0x3a, /* [4344] */ + (xdc_Char)0x20, /* [4345] */ + (xdc_Char)0x69, /* [4346] */ + (xdc_Char)0x64, /* [4347] */ + (xdc_Char)0x20, /* [4348] */ + (xdc_Char)0x3d, /* [4349] */ + (xdc_Char)0x20, /* [4350] */ + (xdc_Char)0x25, /* [4351] */ + (xdc_Char)0x64, /* [4352] */ + (xdc_Char)0x2c, /* [4353] */ + (xdc_Char)0x20, /* [4354] */ + (xdc_Char)0x70, /* [4355] */ + (xdc_Char)0x63, /* [4356] */ + (xdc_Char)0x20, /* [4357] */ + (xdc_Char)0x3d, /* [4358] */ + (xdc_Char)0x20, /* [4359] */ + (xdc_Char)0x25, /* [4360] */ + (xdc_Char)0x30, /* [4361] */ + (xdc_Char)0x38, /* [4362] */ + (xdc_Char)0x78, /* [4363] */ + (xdc_Char)0x0, /* [4364] */ + (xdc_Char)0x45, /* [4365] */ + (xdc_Char)0x5f, /* [4366] */ + (xdc_Char)0x4e, /* [4367] */ + (xdc_Char)0x4d, /* [4368] */ + (xdc_Char)0x49, /* [4369] */ + (xdc_Char)0x3a, /* [4370] */ + (xdc_Char)0x20, /* [4371] */ + (xdc_Char)0x25, /* [4372] */ + (xdc_Char)0x73, /* [4373] */ + (xdc_Char)0x0, /* [4374] */ + (xdc_Char)0x45, /* [4375] */ + (xdc_Char)0x5f, /* [4376] */ + (xdc_Char)0x68, /* [4377] */ + (xdc_Char)0x61, /* [4378] */ + (xdc_Char)0x72, /* [4379] */ + (xdc_Char)0x64, /* [4380] */ + (xdc_Char)0x46, /* [4381] */ + (xdc_Char)0x61, /* [4382] */ + (xdc_Char)0x75, /* [4383] */ + (xdc_Char)0x6c, /* [4384] */ + (xdc_Char)0x74, /* [4385] */ + (xdc_Char)0x3a, /* [4386] */ + (xdc_Char)0x20, /* [4387] */ + (xdc_Char)0x25, /* [4388] */ + (xdc_Char)0x73, /* [4389] */ + (xdc_Char)0x0, /* [4390] */ + (xdc_Char)0x45, /* [4391] */ + (xdc_Char)0x5f, /* [4392] */ + (xdc_Char)0x6d, /* [4393] */ + (xdc_Char)0x65, /* [4394] */ + (xdc_Char)0x6d, /* [4395] */ + (xdc_Char)0x46, /* [4396] */ + (xdc_Char)0x61, /* [4397] */ + (xdc_Char)0x75, /* [4398] */ + (xdc_Char)0x6c, /* [4399] */ + (xdc_Char)0x74, /* [4400] */ + (xdc_Char)0x3a, /* [4401] */ + (xdc_Char)0x20, /* [4402] */ + (xdc_Char)0x25, /* [4403] */ + (xdc_Char)0x73, /* [4404] */ + (xdc_Char)0x2c, /* [4405] */ + (xdc_Char)0x20, /* [4406] */ + (xdc_Char)0x61, /* [4407] */ + (xdc_Char)0x64, /* [4408] */ + (xdc_Char)0x64, /* [4409] */ + (xdc_Char)0x72, /* [4410] */ + (xdc_Char)0x65, /* [4411] */ + (xdc_Char)0x73, /* [4412] */ + (xdc_Char)0x73, /* [4413] */ + (xdc_Char)0x3a, /* [4414] */ + (xdc_Char)0x20, /* [4415] */ + (xdc_Char)0x25, /* [4416] */ + (xdc_Char)0x30, /* [4417] */ + (xdc_Char)0x38, /* [4418] */ + (xdc_Char)0x78, /* [4419] */ + (xdc_Char)0x0, /* [4420] */ + (xdc_Char)0x45, /* [4421] */ + (xdc_Char)0x5f, /* [4422] */ + (xdc_Char)0x62, /* [4423] */ + (xdc_Char)0x75, /* [4424] */ + (xdc_Char)0x73, /* [4425] */ + (xdc_Char)0x46, /* [4426] */ + (xdc_Char)0x61, /* [4427] */ + (xdc_Char)0x75, /* [4428] */ + (xdc_Char)0x6c, /* [4429] */ + (xdc_Char)0x74, /* [4430] */ + (xdc_Char)0x3a, /* [4431] */ + (xdc_Char)0x20, /* [4432] */ + (xdc_Char)0x25, /* [4433] */ + (xdc_Char)0x73, /* [4434] */ + (xdc_Char)0x2c, /* [4435] */ + (xdc_Char)0x20, /* [4436] */ + (xdc_Char)0x61, /* [4437] */ + (xdc_Char)0x64, /* [4438] */ + (xdc_Char)0x64, /* [4439] */ + (xdc_Char)0x72, /* [4440] */ + (xdc_Char)0x65, /* [4441] */ + (xdc_Char)0x73, /* [4442] */ + (xdc_Char)0x73, /* [4443] */ + (xdc_Char)0x3a, /* [4444] */ + (xdc_Char)0x20, /* [4445] */ + (xdc_Char)0x25, /* [4446] */ + (xdc_Char)0x30, /* [4447] */ + (xdc_Char)0x38, /* [4448] */ + (xdc_Char)0x78, /* [4449] */ + (xdc_Char)0x0, /* [4450] */ + (xdc_Char)0x45, /* [4451] */ + (xdc_Char)0x5f, /* [4452] */ + (xdc_Char)0x75, /* [4453] */ + (xdc_Char)0x73, /* [4454] */ + (xdc_Char)0x61, /* [4455] */ + (xdc_Char)0x67, /* [4456] */ + (xdc_Char)0x65, /* [4457] */ + (xdc_Char)0x46, /* [4458] */ + (xdc_Char)0x61, /* [4459] */ + (xdc_Char)0x75, /* [4460] */ + (xdc_Char)0x6c, /* [4461] */ + (xdc_Char)0x74, /* [4462] */ + (xdc_Char)0x3a, /* [4463] */ + (xdc_Char)0x20, /* [4464] */ + (xdc_Char)0x25, /* [4465] */ + (xdc_Char)0x73, /* [4466] */ + (xdc_Char)0x0, /* [4467] */ + (xdc_Char)0x45, /* [4468] */ + (xdc_Char)0x5f, /* [4469] */ + (xdc_Char)0x73, /* [4470] */ + (xdc_Char)0x76, /* [4471] */ + (xdc_Char)0x43, /* [4472] */ + (xdc_Char)0x61, /* [4473] */ + (xdc_Char)0x6c, /* [4474] */ + (xdc_Char)0x6c, /* [4475] */ + (xdc_Char)0x3a, /* [4476] */ + (xdc_Char)0x20, /* [4477] */ + (xdc_Char)0x73, /* [4478] */ + (xdc_Char)0x76, /* [4479] */ + (xdc_Char)0x4e, /* [4480] */ + (xdc_Char)0x75, /* [4481] */ + (xdc_Char)0x6d, /* [4482] */ + (xdc_Char)0x20, /* [4483] */ + (xdc_Char)0x3d, /* [4484] */ + (xdc_Char)0x20, /* [4485] */ + (xdc_Char)0x25, /* [4486] */ + (xdc_Char)0x64, /* [4487] */ + (xdc_Char)0x0, /* [4488] */ + (xdc_Char)0x45, /* [4489] */ + (xdc_Char)0x5f, /* [4490] */ + (xdc_Char)0x64, /* [4491] */ + (xdc_Char)0x65, /* [4492] */ + (xdc_Char)0x62, /* [4493] */ + (xdc_Char)0x75, /* [4494] */ + (xdc_Char)0x67, /* [4495] */ + (xdc_Char)0x4d, /* [4496] */ + (xdc_Char)0x6f, /* [4497] */ + (xdc_Char)0x6e, /* [4498] */ + (xdc_Char)0x3a, /* [4499] */ + (xdc_Char)0x20, /* [4500] */ + (xdc_Char)0x25, /* [4501] */ + (xdc_Char)0x73, /* [4502] */ + (xdc_Char)0x0, /* [4503] */ + (xdc_Char)0x45, /* [4504] */ + (xdc_Char)0x5f, /* [4505] */ + (xdc_Char)0x72, /* [4506] */ + (xdc_Char)0x65, /* [4507] */ + (xdc_Char)0x73, /* [4508] */ + (xdc_Char)0x65, /* [4509] */ + (xdc_Char)0x72, /* [4510] */ + (xdc_Char)0x76, /* [4511] */ + (xdc_Char)0x65, /* [4512] */ + (xdc_Char)0x64, /* [4513] */ + (xdc_Char)0x3a, /* [4514] */ + (xdc_Char)0x20, /* [4515] */ + (xdc_Char)0x25, /* [4516] */ + (xdc_Char)0x73, /* [4517] */ + (xdc_Char)0x20, /* [4518] */ + (xdc_Char)0x25, /* [4519] */ + (xdc_Char)0x64, /* [4520] */ + (xdc_Char)0x0, /* [4521] */ + (xdc_Char)0x45, /* [4522] */ + (xdc_Char)0x5f, /* [4523] */ + (xdc_Char)0x69, /* [4524] */ + (xdc_Char)0x6e, /* [4525] */ + (xdc_Char)0x76, /* [4526] */ + (xdc_Char)0x61, /* [4527] */ + (xdc_Char)0x6c, /* [4528] */ + (xdc_Char)0x69, /* [4529] */ + (xdc_Char)0x64, /* [4530] */ + (xdc_Char)0x54, /* [4531] */ + (xdc_Char)0x69, /* [4532] */ + (xdc_Char)0x6d, /* [4533] */ + (xdc_Char)0x65, /* [4534] */ + (xdc_Char)0x72, /* [4535] */ + (xdc_Char)0x3a, /* [4536] */ + (xdc_Char)0x20, /* [4537] */ + (xdc_Char)0x49, /* [4538] */ + (xdc_Char)0x6e, /* [4539] */ + (xdc_Char)0x76, /* [4540] */ + (xdc_Char)0x61, /* [4541] */ + (xdc_Char)0x6c, /* [4542] */ + (xdc_Char)0x69, /* [4543] */ + (xdc_Char)0x64, /* [4544] */ + (xdc_Char)0x20, /* [4545] */ + (xdc_Char)0x54, /* [4546] */ + (xdc_Char)0x69, /* [4547] */ + (xdc_Char)0x6d, /* [4548] */ + (xdc_Char)0x65, /* [4549] */ + (xdc_Char)0x72, /* [4550] */ + (xdc_Char)0x20, /* [4551] */ + (xdc_Char)0x49, /* [4552] */ + (xdc_Char)0x64, /* [4553] */ + (xdc_Char)0x20, /* [4554] */ + (xdc_Char)0x25, /* [4555] */ + (xdc_Char)0x64, /* [4556] */ + (xdc_Char)0x0, /* [4557] */ + (xdc_Char)0x45, /* [4558] */ + (xdc_Char)0x5f, /* [4559] */ + (xdc_Char)0x6e, /* [4560] */ + (xdc_Char)0x6f, /* [4561] */ + (xdc_Char)0x74, /* [4562] */ + (xdc_Char)0x41, /* [4563] */ + (xdc_Char)0x76, /* [4564] */ + (xdc_Char)0x61, /* [4565] */ + (xdc_Char)0x69, /* [4566] */ + (xdc_Char)0x6c, /* [4567] */ + (xdc_Char)0x61, /* [4568] */ + (xdc_Char)0x62, /* [4569] */ + (xdc_Char)0x6c, /* [4570] */ + (xdc_Char)0x65, /* [4571] */ + (xdc_Char)0x3a, /* [4572] */ + (xdc_Char)0x20, /* [4573] */ + (xdc_Char)0x54, /* [4574] */ + (xdc_Char)0x69, /* [4575] */ + (xdc_Char)0x6d, /* [4576] */ + (xdc_Char)0x65, /* [4577] */ + (xdc_Char)0x72, /* [4578] */ + (xdc_Char)0x20, /* [4579] */ + (xdc_Char)0x6e, /* [4580] */ + (xdc_Char)0x6f, /* [4581] */ + (xdc_Char)0x74, /* [4582] */ + (xdc_Char)0x20, /* [4583] */ + (xdc_Char)0x61, /* [4584] */ + (xdc_Char)0x76, /* [4585] */ + (xdc_Char)0x61, /* [4586] */ + (xdc_Char)0x69, /* [4587] */ + (xdc_Char)0x6c, /* [4588] */ + (xdc_Char)0x61, /* [4589] */ + (xdc_Char)0x62, /* [4590] */ + (xdc_Char)0x6c, /* [4591] */ + (xdc_Char)0x65, /* [4592] */ + (xdc_Char)0x20, /* [4593] */ + (xdc_Char)0x25, /* [4594] */ + (xdc_Char)0x64, /* [4595] */ + (xdc_Char)0x0, /* [4596] */ + (xdc_Char)0x45, /* [4597] */ + (xdc_Char)0x5f, /* [4598] */ + (xdc_Char)0x63, /* [4599] */ + (xdc_Char)0x61, /* [4600] */ + (xdc_Char)0x6e, /* [4601] */ + (xdc_Char)0x6e, /* [4602] */ + (xdc_Char)0x6f, /* [4603] */ + (xdc_Char)0x74, /* [4604] */ + (xdc_Char)0x53, /* [4605] */ + (xdc_Char)0x75, /* [4606] */ + (xdc_Char)0x70, /* [4607] */ + (xdc_Char)0x70, /* [4608] */ + (xdc_Char)0x6f, /* [4609] */ + (xdc_Char)0x72, /* [4610] */ + (xdc_Char)0x74, /* [4611] */ + (xdc_Char)0x3a, /* [4612] */ + (xdc_Char)0x20, /* [4613] */ + (xdc_Char)0x54, /* [4614] */ + (xdc_Char)0x69, /* [4615] */ + (xdc_Char)0x6d, /* [4616] */ + (xdc_Char)0x65, /* [4617] */ + (xdc_Char)0x72, /* [4618] */ + (xdc_Char)0x20, /* [4619] */ + (xdc_Char)0x63, /* [4620] */ + (xdc_Char)0x61, /* [4621] */ + (xdc_Char)0x6e, /* [4622] */ + (xdc_Char)0x6e, /* [4623] */ + (xdc_Char)0x6f, /* [4624] */ + (xdc_Char)0x74, /* [4625] */ + (xdc_Char)0x20, /* [4626] */ + (xdc_Char)0x73, /* [4627] */ + (xdc_Char)0x75, /* [4628] */ + (xdc_Char)0x70, /* [4629] */ + (xdc_Char)0x70, /* [4630] */ + (xdc_Char)0x6f, /* [4631] */ + (xdc_Char)0x72, /* [4632] */ + (xdc_Char)0x74, /* [4633] */ + (xdc_Char)0x20, /* [4634] */ + (xdc_Char)0x72, /* [4635] */ + (xdc_Char)0x65, /* [4636] */ + (xdc_Char)0x71, /* [4637] */ + (xdc_Char)0x75, /* [4638] */ + (xdc_Char)0x65, /* [4639] */ + (xdc_Char)0x73, /* [4640] */ + (xdc_Char)0x74, /* [4641] */ + (xdc_Char)0x65, /* [4642] */ + (xdc_Char)0x64, /* [4643] */ + (xdc_Char)0x20, /* [4644] */ + (xdc_Char)0x70, /* [4645] */ + (xdc_Char)0x65, /* [4646] */ + (xdc_Char)0x72, /* [4647] */ + (xdc_Char)0x69, /* [4648] */ + (xdc_Char)0x6f, /* [4649] */ + (xdc_Char)0x64, /* [4650] */ + (xdc_Char)0x20, /* [4651] */ + (xdc_Char)0x25, /* [4652] */ + (xdc_Char)0x64, /* [4653] */ + (xdc_Char)0x0, /* [4654] */ + (xdc_Char)0x45, /* [4655] */ + (xdc_Char)0x5f, /* [4656] */ + (xdc_Char)0x70, /* [4657] */ + (xdc_Char)0x72, /* [4658] */ + (xdc_Char)0x69, /* [4659] */ + (xdc_Char)0x6f, /* [4660] */ + (xdc_Char)0x72, /* [4661] */ + (xdc_Char)0x69, /* [4662] */ + (xdc_Char)0x74, /* [4663] */ + (xdc_Char)0x79, /* [4664] */ + (xdc_Char)0x3a, /* [4665] */ + (xdc_Char)0x20, /* [4666] */ + (xdc_Char)0x54, /* [4667] */ + (xdc_Char)0x68, /* [4668] */ + (xdc_Char)0x72, /* [4669] */ + (xdc_Char)0x65, /* [4670] */ + (xdc_Char)0x61, /* [4671] */ + (xdc_Char)0x64, /* [4672] */ + (xdc_Char)0x20, /* [4673] */ + (xdc_Char)0x70, /* [4674] */ + (xdc_Char)0x72, /* [4675] */ + (xdc_Char)0x69, /* [4676] */ + (xdc_Char)0x6f, /* [4677] */ + (xdc_Char)0x72, /* [4678] */ + (xdc_Char)0x69, /* [4679] */ + (xdc_Char)0x74, /* [4680] */ + (xdc_Char)0x79, /* [4681] */ + (xdc_Char)0x20, /* [4682] */ + (xdc_Char)0x69, /* [4683] */ + (xdc_Char)0x73, /* [4684] */ + (xdc_Char)0x20, /* [4685] */ + (xdc_Char)0x69, /* [4686] */ + (xdc_Char)0x6e, /* [4687] */ + (xdc_Char)0x76, /* [4688] */ + (xdc_Char)0x61, /* [4689] */ + (xdc_Char)0x6c, /* [4690] */ + (xdc_Char)0x69, /* [4691] */ + (xdc_Char)0x64, /* [4692] */ + (xdc_Char)0x20, /* [4693] */ + (xdc_Char)0x25, /* [4694] */ + (xdc_Char)0x64, /* [4695] */ + (xdc_Char)0x0, /* [4696] */ + (xdc_Char)0x72, /* [4697] */ + (xdc_Char)0x65, /* [4698] */ + (xdc_Char)0x71, /* [4699] */ + (xdc_Char)0x75, /* [4700] */ + (xdc_Char)0x65, /* [4701] */ + (xdc_Char)0x73, /* [4702] */ + (xdc_Char)0x74, /* [4703] */ + (xdc_Char)0x65, /* [4704] */ + (xdc_Char)0x64, /* [4705] */ + (xdc_Char)0x20, /* [4706] */ + (xdc_Char)0x73, /* [4707] */ + (xdc_Char)0x69, /* [4708] */ + (xdc_Char)0x7a, /* [4709] */ + (xdc_Char)0x65, /* [4710] */ + (xdc_Char)0x20, /* [4711] */ + (xdc_Char)0x69, /* [4712] */ + (xdc_Char)0x73, /* [4713] */ + (xdc_Char)0x20, /* [4714] */ + (xdc_Char)0x74, /* [4715] */ + (xdc_Char)0x6f, /* [4716] */ + (xdc_Char)0x6f, /* [4717] */ + (xdc_Char)0x20, /* [4718] */ + (xdc_Char)0x62, /* [4719] */ + (xdc_Char)0x69, /* [4720] */ + (xdc_Char)0x67, /* [4721] */ + (xdc_Char)0x3a, /* [4722] */ + (xdc_Char)0x20, /* [4723] */ + (xdc_Char)0x68, /* [4724] */ + (xdc_Char)0x61, /* [4725] */ + (xdc_Char)0x6e, /* [4726] */ + (xdc_Char)0x64, /* [4727] */ + (xdc_Char)0x6c, /* [4728] */ + (xdc_Char)0x65, /* [4729] */ + (xdc_Char)0x3d, /* [4730] */ + (xdc_Char)0x30, /* [4731] */ + (xdc_Char)0x78, /* [4732] */ + (xdc_Char)0x25, /* [4733] */ + (xdc_Char)0x78, /* [4734] */ + (xdc_Char)0x2c, /* [4735] */ + (xdc_Char)0x20, /* [4736] */ + (xdc_Char)0x73, /* [4737] */ + (xdc_Char)0x69, /* [4738] */ + (xdc_Char)0x7a, /* [4739] */ + (xdc_Char)0x65, /* [4740] */ + (xdc_Char)0x3d, /* [4741] */ + (xdc_Char)0x25, /* [4742] */ + (xdc_Char)0x75, /* [4743] */ + (xdc_Char)0x0, /* [4744] */ + (xdc_Char)0x6f, /* [4745] */ + (xdc_Char)0x75, /* [4746] */ + (xdc_Char)0x74, /* [4747] */ + (xdc_Char)0x20, /* [4748] */ + (xdc_Char)0x6f, /* [4749] */ + (xdc_Char)0x66, /* [4750] */ + (xdc_Char)0x20, /* [4751] */ + (xdc_Char)0x6d, /* [4752] */ + (xdc_Char)0x65, /* [4753] */ + (xdc_Char)0x6d, /* [4754] */ + (xdc_Char)0x6f, /* [4755] */ + (xdc_Char)0x72, /* [4756] */ + (xdc_Char)0x79, /* [4757] */ + (xdc_Char)0x3a, /* [4758] */ + (xdc_Char)0x20, /* [4759] */ + (xdc_Char)0x68, /* [4760] */ + (xdc_Char)0x61, /* [4761] */ + (xdc_Char)0x6e, /* [4762] */ + (xdc_Char)0x64, /* [4763] */ + (xdc_Char)0x6c, /* [4764] */ + (xdc_Char)0x65, /* [4765] */ + (xdc_Char)0x3d, /* [4766] */ + (xdc_Char)0x30, /* [4767] */ + (xdc_Char)0x78, /* [4768] */ + (xdc_Char)0x25, /* [4769] */ + (xdc_Char)0x78, /* [4770] */ + (xdc_Char)0x2c, /* [4771] */ + (xdc_Char)0x20, /* [4772] */ + (xdc_Char)0x73, /* [4773] */ + (xdc_Char)0x69, /* [4774] */ + (xdc_Char)0x7a, /* [4775] */ + (xdc_Char)0x65, /* [4776] */ + (xdc_Char)0x3d, /* [4777] */ + (xdc_Char)0x25, /* [4778] */ + (xdc_Char)0x75, /* [4779] */ + (xdc_Char)0x0, /* [4780] */ + (xdc_Char)0x45, /* [4781] */ + (xdc_Char)0x5f, /* [4782] */ + (xdc_Char)0x6e, /* [4783] */ + (xdc_Char)0x6f, /* [4784] */ + (xdc_Char)0x61, /* [4785] */ + (xdc_Char)0x6c, /* [4786] */ + (xdc_Char)0x74, /* [4787] */ + (xdc_Char)0x63, /* [4788] */ + (xdc_Char)0x6c, /* [4789] */ + (xdc_Char)0x6b, /* [4790] */ + (xdc_Char)0x3a, /* [4791] */ + (xdc_Char)0x20, /* [4792] */ + (xdc_Char)0x54, /* [4793] */ + (xdc_Char)0x69, /* [4794] */ + (xdc_Char)0x6d, /* [4795] */ + (xdc_Char)0x65, /* [4796] */ + (xdc_Char)0x72, /* [4797] */ + (xdc_Char)0x20, /* [4798] */ + (xdc_Char)0x64, /* [4799] */ + (xdc_Char)0x6f, /* [4800] */ + (xdc_Char)0x65, /* [4801] */ + (xdc_Char)0x73, /* [4802] */ + (xdc_Char)0x20, /* [4803] */ + (xdc_Char)0x6e, /* [4804] */ + (xdc_Char)0x6f, /* [4805] */ + (xdc_Char)0x74, /* [4806] */ + (xdc_Char)0x20, /* [4807] */ + (xdc_Char)0x73, /* [4808] */ + (xdc_Char)0x75, /* [4809] */ + (xdc_Char)0x70, /* [4810] */ + (xdc_Char)0x70, /* [4811] */ + (xdc_Char)0x6f, /* [4812] */ + (xdc_Char)0x72, /* [4813] */ + (xdc_Char)0x74, /* [4814] */ + (xdc_Char)0x20, /* [4815] */ + (xdc_Char)0x61, /* [4816] */ + (xdc_Char)0x6c, /* [4817] */ + (xdc_Char)0x74, /* [4818] */ + (xdc_Char)0x63, /* [4819] */ + (xdc_Char)0x6c, /* [4820] */ + (xdc_Char)0x6b, /* [4821] */ + (xdc_Char)0x0, /* [4822] */ + (xdc_Char)0x3c, /* [4823] */ + (xdc_Char)0x2d, /* [4824] */ + (xdc_Char)0x2d, /* [4825] */ + (xdc_Char)0x20, /* [4826] */ + (xdc_Char)0x63, /* [4827] */ + (xdc_Char)0x6f, /* [4828] */ + (xdc_Char)0x6e, /* [4829] */ + (xdc_Char)0x73, /* [4830] */ + (xdc_Char)0x74, /* [4831] */ + (xdc_Char)0x72, /* [4832] */ + (xdc_Char)0x75, /* [4833] */ + (xdc_Char)0x63, /* [4834] */ + (xdc_Char)0x74, /* [4835] */ + (xdc_Char)0x3a, /* [4836] */ + (xdc_Char)0x20, /* [4837] */ + (xdc_Char)0x25, /* [4838] */ + (xdc_Char)0x70, /* [4839] */ + (xdc_Char)0x28, /* [4840] */ + (xdc_Char)0x27, /* [4841] */ + (xdc_Char)0x25, /* [4842] */ + (xdc_Char)0x73, /* [4843] */ + (xdc_Char)0x27, /* [4844] */ + (xdc_Char)0x29, /* [4845] */ + (xdc_Char)0x0, /* [4846] */ + (xdc_Char)0x3c, /* [4847] */ + (xdc_Char)0x2d, /* [4848] */ + (xdc_Char)0x2d, /* [4849] */ + (xdc_Char)0x20, /* [4850] */ + (xdc_Char)0x63, /* [4851] */ + (xdc_Char)0x72, /* [4852] */ + (xdc_Char)0x65, /* [4853] */ + (xdc_Char)0x61, /* [4854] */ + (xdc_Char)0x74, /* [4855] */ + (xdc_Char)0x65, /* [4856] */ + (xdc_Char)0x3a, /* [4857] */ + (xdc_Char)0x20, /* [4858] */ + (xdc_Char)0x25, /* [4859] */ + (xdc_Char)0x70, /* [4860] */ + (xdc_Char)0x28, /* [4861] */ + (xdc_Char)0x27, /* [4862] */ + (xdc_Char)0x25, /* [4863] */ + (xdc_Char)0x73, /* [4864] */ + (xdc_Char)0x27, /* [4865] */ + (xdc_Char)0x29, /* [4866] */ + (xdc_Char)0x0, /* [4867] */ + (xdc_Char)0x2d, /* [4868] */ + (xdc_Char)0x2d, /* [4869] */ + (xdc_Char)0x3e, /* [4870] */ + (xdc_Char)0x20, /* [4871] */ + (xdc_Char)0x64, /* [4872] */ + (xdc_Char)0x65, /* [4873] */ + (xdc_Char)0x73, /* [4874] */ + (xdc_Char)0x74, /* [4875] */ + (xdc_Char)0x72, /* [4876] */ + (xdc_Char)0x75, /* [4877] */ + (xdc_Char)0x63, /* [4878] */ + (xdc_Char)0x74, /* [4879] */ + (xdc_Char)0x3a, /* [4880] */ + (xdc_Char)0x20, /* [4881] */ + (xdc_Char)0x28, /* [4882] */ + (xdc_Char)0x25, /* [4883] */ + (xdc_Char)0x70, /* [4884] */ + (xdc_Char)0x29, /* [4885] */ + (xdc_Char)0x0, /* [4886] */ + (xdc_Char)0x2d, /* [4887] */ + (xdc_Char)0x2d, /* [4888] */ + (xdc_Char)0x3e, /* [4889] */ + (xdc_Char)0x20, /* [4890] */ + (xdc_Char)0x64, /* [4891] */ + (xdc_Char)0x65, /* [4892] */ + (xdc_Char)0x6c, /* [4893] */ + (xdc_Char)0x65, /* [4894] */ + (xdc_Char)0x74, /* [4895] */ + (xdc_Char)0x65, /* [4896] */ + (xdc_Char)0x3a, /* [4897] */ + (xdc_Char)0x20, /* [4898] */ + (xdc_Char)0x28, /* [4899] */ + (xdc_Char)0x25, /* [4900] */ + (xdc_Char)0x70, /* [4901] */ + (xdc_Char)0x29, /* [4902] */ + (xdc_Char)0x0, /* [4903] */ + (xdc_Char)0x45, /* [4904] */ + (xdc_Char)0x52, /* [4905] */ + (xdc_Char)0x52, /* [4906] */ + (xdc_Char)0x4f, /* [4907] */ + (xdc_Char)0x52, /* [4908] */ + (xdc_Char)0x3a, /* [4909] */ + (xdc_Char)0x20, /* [4910] */ + (xdc_Char)0x25, /* [4911] */ + (xdc_Char)0x24, /* [4912] */ + (xdc_Char)0x46, /* [4913] */ + (xdc_Char)0x25, /* [4914] */ + (xdc_Char)0x24, /* [4915] */ + (xdc_Char)0x53, /* [4916] */ + (xdc_Char)0x0, /* [4917] */ + (xdc_Char)0x57, /* [4918] */ + (xdc_Char)0x41, /* [4919] */ + (xdc_Char)0x52, /* [4920] */ + (xdc_Char)0x4e, /* [4921] */ + (xdc_Char)0x49, /* [4922] */ + (xdc_Char)0x4e, /* [4923] */ + (xdc_Char)0x47, /* [4924] */ + (xdc_Char)0x3a, /* [4925] */ + (xdc_Char)0x20, /* [4926] */ + (xdc_Char)0x25, /* [4927] */ + (xdc_Char)0x24, /* [4928] */ + (xdc_Char)0x46, /* [4929] */ + (xdc_Char)0x25, /* [4930] */ + (xdc_Char)0x24, /* [4931] */ + (xdc_Char)0x53, /* [4932] */ + (xdc_Char)0x0, /* [4933] */ + (xdc_Char)0x25, /* [4934] */ + (xdc_Char)0x24, /* [4935] */ + (xdc_Char)0x46, /* [4936] */ + (xdc_Char)0x25, /* [4937] */ + (xdc_Char)0x24, /* [4938] */ + (xdc_Char)0x53, /* [4939] */ + (xdc_Char)0x0, /* [4940] */ + (xdc_Char)0x53, /* [4941] */ + (xdc_Char)0x74, /* [4942] */ + (xdc_Char)0x61, /* [4943] */ + (xdc_Char)0x72, /* [4944] */ + (xdc_Char)0x74, /* [4945] */ + (xdc_Char)0x3a, /* [4946] */ + (xdc_Char)0x20, /* [4947] */ + (xdc_Char)0x25, /* [4948] */ + (xdc_Char)0x24, /* [4949] */ + (xdc_Char)0x53, /* [4950] */ + (xdc_Char)0x0, /* [4951] */ + (xdc_Char)0x53, /* [4952] */ + (xdc_Char)0x74, /* [4953] */ + (xdc_Char)0x6f, /* [4954] */ + (xdc_Char)0x70, /* [4955] */ + (xdc_Char)0x3a, /* [4956] */ + (xdc_Char)0x20, /* [4957] */ + (xdc_Char)0x25, /* [4958] */ + (xdc_Char)0x24, /* [4959] */ + (xdc_Char)0x53, /* [4960] */ + (xdc_Char)0x0, /* [4961] */ + (xdc_Char)0x53, /* [4962] */ + (xdc_Char)0x74, /* [4963] */ + (xdc_Char)0x61, /* [4964] */ + (xdc_Char)0x72, /* [4965] */ + (xdc_Char)0x74, /* [4966] */ + (xdc_Char)0x49, /* [4967] */ + (xdc_Char)0x6e, /* [4968] */ + (xdc_Char)0x73, /* [4969] */ + (xdc_Char)0x74, /* [4970] */ + (xdc_Char)0x61, /* [4971] */ + (xdc_Char)0x6e, /* [4972] */ + (xdc_Char)0x63, /* [4973] */ + (xdc_Char)0x65, /* [4974] */ + (xdc_Char)0x3a, /* [4975] */ + (xdc_Char)0x20, /* [4976] */ + (xdc_Char)0x25, /* [4977] */ + (xdc_Char)0x24, /* [4978] */ + (xdc_Char)0x53, /* [4979] */ + (xdc_Char)0x0, /* [4980] */ + (xdc_Char)0x53, /* [4981] */ + (xdc_Char)0x74, /* [4982] */ + (xdc_Char)0x6f, /* [4983] */ + (xdc_Char)0x70, /* [4984] */ + (xdc_Char)0x49, /* [4985] */ + (xdc_Char)0x6e, /* [4986] */ + (xdc_Char)0x73, /* [4987] */ + (xdc_Char)0x74, /* [4988] */ + (xdc_Char)0x61, /* [4989] */ + (xdc_Char)0x6e, /* [4990] */ + (xdc_Char)0x63, /* [4991] */ + (xdc_Char)0x65, /* [4992] */ + (xdc_Char)0x3a, /* [4993] */ + (xdc_Char)0x20, /* [4994] */ + (xdc_Char)0x25, /* [4995] */ + (xdc_Char)0x24, /* [4996] */ + (xdc_Char)0x53, /* [4997] */ + (xdc_Char)0x0, /* [4998] */ + (xdc_Char)0x4c, /* [4999] */ + (xdc_Char)0x57, /* [5000] */ + (xdc_Char)0x5f, /* [5001] */ + (xdc_Char)0x64, /* [5002] */ + (xdc_Char)0x65, /* [5003] */ + (xdc_Char)0x6c, /* [5004] */ + (xdc_Char)0x61, /* [5005] */ + (xdc_Char)0x79, /* [5006] */ + (xdc_Char)0x65, /* [5007] */ + (xdc_Char)0x64, /* [5008] */ + (xdc_Char)0x3a, /* [5009] */ + (xdc_Char)0x20, /* [5010] */ + (xdc_Char)0x64, /* [5011] */ + (xdc_Char)0x65, /* [5012] */ + (xdc_Char)0x6c, /* [5013] */ + (xdc_Char)0x61, /* [5014] */ + (xdc_Char)0x79, /* [5015] */ + (xdc_Char)0x3a, /* [5016] */ + (xdc_Char)0x20, /* [5017] */ + (xdc_Char)0x25, /* [5018] */ + (xdc_Char)0x64, /* [5019] */ + (xdc_Char)0x0, /* [5020] */ + (xdc_Char)0x4c, /* [5021] */ + (xdc_Char)0x4d, /* [5022] */ + (xdc_Char)0x5f, /* [5023] */ + (xdc_Char)0x74, /* [5024] */ + (xdc_Char)0x69, /* [5025] */ + (xdc_Char)0x63, /* [5026] */ + (xdc_Char)0x6b, /* [5027] */ + (xdc_Char)0x3a, /* [5028] */ + (xdc_Char)0x20, /* [5029] */ + (xdc_Char)0x74, /* [5030] */ + (xdc_Char)0x69, /* [5031] */ + (xdc_Char)0x63, /* [5032] */ + (xdc_Char)0x6b, /* [5033] */ + (xdc_Char)0x3a, /* [5034] */ + (xdc_Char)0x20, /* [5035] */ + (xdc_Char)0x25, /* [5036] */ + (xdc_Char)0x64, /* [5037] */ + (xdc_Char)0x0, /* [5038] */ + (xdc_Char)0x4c, /* [5039] */ + (xdc_Char)0x4d, /* [5040] */ + (xdc_Char)0x5f, /* [5041] */ + (xdc_Char)0x62, /* [5042] */ + (xdc_Char)0x65, /* [5043] */ + (xdc_Char)0x67, /* [5044] */ + (xdc_Char)0x69, /* [5045] */ + (xdc_Char)0x6e, /* [5046] */ + (xdc_Char)0x3a, /* [5047] */ + (xdc_Char)0x20, /* [5048] */ + (xdc_Char)0x63, /* [5049] */ + (xdc_Char)0x6c, /* [5050] */ + (xdc_Char)0x6b, /* [5051] */ + (xdc_Char)0x3a, /* [5052] */ + (xdc_Char)0x20, /* [5053] */ + (xdc_Char)0x30, /* [5054] */ + (xdc_Char)0x78, /* [5055] */ + (xdc_Char)0x25, /* [5056] */ + (xdc_Char)0x78, /* [5057] */ + (xdc_Char)0x2c, /* [5058] */ + (xdc_Char)0x20, /* [5059] */ + (xdc_Char)0x66, /* [5060] */ + (xdc_Char)0x75, /* [5061] */ + (xdc_Char)0x6e, /* [5062] */ + (xdc_Char)0x63, /* [5063] */ + (xdc_Char)0x3a, /* [5064] */ + (xdc_Char)0x20, /* [5065] */ + (xdc_Char)0x30, /* [5066] */ + (xdc_Char)0x78, /* [5067] */ + (xdc_Char)0x25, /* [5068] */ + (xdc_Char)0x78, /* [5069] */ + (xdc_Char)0x0, /* [5070] */ + (xdc_Char)0x4c, /* [5071] */ + (xdc_Char)0x4d, /* [5072] */ + (xdc_Char)0x5f, /* [5073] */ + (xdc_Char)0x70, /* [5074] */ + (xdc_Char)0x6f, /* [5075] */ + (xdc_Char)0x73, /* [5076] */ + (xdc_Char)0x74, /* [5077] */ + (xdc_Char)0x3a, /* [5078] */ + (xdc_Char)0x20, /* [5079] */ + (xdc_Char)0x73, /* [5080] */ + (xdc_Char)0x65, /* [5081] */ + (xdc_Char)0x6d, /* [5082] */ + (xdc_Char)0x3a, /* [5083] */ + (xdc_Char)0x20, /* [5084] */ + (xdc_Char)0x30, /* [5085] */ + (xdc_Char)0x78, /* [5086] */ + (xdc_Char)0x25, /* [5087] */ + (xdc_Char)0x78, /* [5088] */ + (xdc_Char)0x2c, /* [5089] */ + (xdc_Char)0x20, /* [5090] */ + (xdc_Char)0x63, /* [5091] */ + (xdc_Char)0x6f, /* [5092] */ + (xdc_Char)0x75, /* [5093] */ + (xdc_Char)0x6e, /* [5094] */ + (xdc_Char)0x74, /* [5095] */ + (xdc_Char)0x3a, /* [5096] */ + (xdc_Char)0x20, /* [5097] */ + (xdc_Char)0x25, /* [5098] */ + (xdc_Char)0x64, /* [5099] */ + (xdc_Char)0x0, /* [5100] */ + (xdc_Char)0x4c, /* [5101] */ + (xdc_Char)0x4d, /* [5102] */ + (xdc_Char)0x5f, /* [5103] */ + (xdc_Char)0x70, /* [5104] */ + (xdc_Char)0x65, /* [5105] */ + (xdc_Char)0x6e, /* [5106] */ + (xdc_Char)0x64, /* [5107] */ + (xdc_Char)0x3a, /* [5108] */ + (xdc_Char)0x20, /* [5109] */ + (xdc_Char)0x73, /* [5110] */ + (xdc_Char)0x65, /* [5111] */ + (xdc_Char)0x6d, /* [5112] */ + (xdc_Char)0x3a, /* [5113] */ + (xdc_Char)0x20, /* [5114] */ + (xdc_Char)0x30, /* [5115] */ + (xdc_Char)0x78, /* [5116] */ + (xdc_Char)0x25, /* [5117] */ + (xdc_Char)0x78, /* [5118] */ + (xdc_Char)0x2c, /* [5119] */ + (xdc_Char)0x20, /* [5120] */ + (xdc_Char)0x63, /* [5121] */ + (xdc_Char)0x6f, /* [5122] */ + (xdc_Char)0x75, /* [5123] */ + (xdc_Char)0x6e, /* [5124] */ + (xdc_Char)0x74, /* [5125] */ + (xdc_Char)0x3a, /* [5126] */ + (xdc_Char)0x20, /* [5127] */ + (xdc_Char)0x25, /* [5128] */ + (xdc_Char)0x64, /* [5129] */ + (xdc_Char)0x2c, /* [5130] */ + (xdc_Char)0x20, /* [5131] */ + (xdc_Char)0x74, /* [5132] */ + (xdc_Char)0x69, /* [5133] */ + (xdc_Char)0x6d, /* [5134] */ + (xdc_Char)0x65, /* [5135] */ + (xdc_Char)0x6f, /* [5136] */ + (xdc_Char)0x75, /* [5137] */ + (xdc_Char)0x74, /* [5138] */ + (xdc_Char)0x3a, /* [5139] */ + (xdc_Char)0x20, /* [5140] */ + (xdc_Char)0x25, /* [5141] */ + (xdc_Char)0x64, /* [5142] */ + (xdc_Char)0x0, /* [5143] */ + (xdc_Char)0x4c, /* [5144] */ + (xdc_Char)0x4d, /* [5145] */ + (xdc_Char)0x5f, /* [5146] */ + (xdc_Char)0x62, /* [5147] */ + (xdc_Char)0x65, /* [5148] */ + (xdc_Char)0x67, /* [5149] */ + (xdc_Char)0x69, /* [5150] */ + (xdc_Char)0x6e, /* [5151] */ + (xdc_Char)0x3a, /* [5152] */ + (xdc_Char)0x20, /* [5153] */ + (xdc_Char)0x73, /* [5154] */ + (xdc_Char)0x77, /* [5155] */ + (xdc_Char)0x69, /* [5156] */ + (xdc_Char)0x3a, /* [5157] */ + (xdc_Char)0x20, /* [5158] */ + (xdc_Char)0x30, /* [5159] */ + (xdc_Char)0x78, /* [5160] */ + (xdc_Char)0x25, /* [5161] */ + (xdc_Char)0x78, /* [5162] */ + (xdc_Char)0x2c, /* [5163] */ + (xdc_Char)0x20, /* [5164] */ + (xdc_Char)0x66, /* [5165] */ + (xdc_Char)0x75, /* [5166] */ + (xdc_Char)0x6e, /* [5167] */ + (xdc_Char)0x63, /* [5168] */ + (xdc_Char)0x3a, /* [5169] */ + (xdc_Char)0x20, /* [5170] */ + (xdc_Char)0x30, /* [5171] */ + (xdc_Char)0x78, /* [5172] */ + (xdc_Char)0x25, /* [5173] */ + (xdc_Char)0x78, /* [5174] */ + (xdc_Char)0x2c, /* [5175] */ + (xdc_Char)0x20, /* [5176] */ + (xdc_Char)0x70, /* [5177] */ + (xdc_Char)0x72, /* [5178] */ + (xdc_Char)0x65, /* [5179] */ + (xdc_Char)0x54, /* [5180] */ + (xdc_Char)0x68, /* [5181] */ + (xdc_Char)0x72, /* [5182] */ + (xdc_Char)0x65, /* [5183] */ + (xdc_Char)0x61, /* [5184] */ + (xdc_Char)0x64, /* [5185] */ + (xdc_Char)0x3a, /* [5186] */ + (xdc_Char)0x20, /* [5187] */ + (xdc_Char)0x25, /* [5188] */ + (xdc_Char)0x64, /* [5189] */ + (xdc_Char)0x0, /* [5190] */ + (xdc_Char)0x4c, /* [5191] */ + (xdc_Char)0x44, /* [5192] */ + (xdc_Char)0x5f, /* [5193] */ + (xdc_Char)0x65, /* [5194] */ + (xdc_Char)0x6e, /* [5195] */ + (xdc_Char)0x64, /* [5196] */ + (xdc_Char)0x3a, /* [5197] */ + (xdc_Char)0x20, /* [5198] */ + (xdc_Char)0x73, /* [5199] */ + (xdc_Char)0x77, /* [5200] */ + (xdc_Char)0x69, /* [5201] */ + (xdc_Char)0x3a, /* [5202] */ + (xdc_Char)0x20, /* [5203] */ + (xdc_Char)0x30, /* [5204] */ + (xdc_Char)0x78, /* [5205] */ + (xdc_Char)0x25, /* [5206] */ + (xdc_Char)0x78, /* [5207] */ + (xdc_Char)0x0, /* [5208] */ + (xdc_Char)0x4c, /* [5209] */ + (xdc_Char)0x4d, /* [5210] */ + (xdc_Char)0x5f, /* [5211] */ + (xdc_Char)0x70, /* [5212] */ + (xdc_Char)0x6f, /* [5213] */ + (xdc_Char)0x73, /* [5214] */ + (xdc_Char)0x74, /* [5215] */ + (xdc_Char)0x3a, /* [5216] */ + (xdc_Char)0x20, /* [5217] */ + (xdc_Char)0x73, /* [5218] */ + (xdc_Char)0x77, /* [5219] */ + (xdc_Char)0x69, /* [5220] */ + (xdc_Char)0x3a, /* [5221] */ + (xdc_Char)0x20, /* [5222] */ + (xdc_Char)0x30, /* [5223] */ + (xdc_Char)0x78, /* [5224] */ + (xdc_Char)0x25, /* [5225] */ + (xdc_Char)0x78, /* [5226] */ + (xdc_Char)0x2c, /* [5227] */ + (xdc_Char)0x20, /* [5228] */ + (xdc_Char)0x66, /* [5229] */ + (xdc_Char)0x75, /* [5230] */ + (xdc_Char)0x6e, /* [5231] */ + (xdc_Char)0x63, /* [5232] */ + (xdc_Char)0x3a, /* [5233] */ + (xdc_Char)0x20, /* [5234] */ + (xdc_Char)0x30, /* [5235] */ + (xdc_Char)0x78, /* [5236] */ + (xdc_Char)0x25, /* [5237] */ + (xdc_Char)0x78, /* [5238] */ + (xdc_Char)0x2c, /* [5239] */ + (xdc_Char)0x20, /* [5240] */ + (xdc_Char)0x70, /* [5241] */ + (xdc_Char)0x72, /* [5242] */ + (xdc_Char)0x69, /* [5243] */ + (xdc_Char)0x3a, /* [5244] */ + (xdc_Char)0x20, /* [5245] */ + (xdc_Char)0x25, /* [5246] */ + (xdc_Char)0x64, /* [5247] */ + (xdc_Char)0x0, /* [5248] */ + (xdc_Char)0x4c, /* [5249] */ + (xdc_Char)0x4d, /* [5250] */ + (xdc_Char)0x5f, /* [5251] */ + (xdc_Char)0x73, /* [5252] */ + (xdc_Char)0x77, /* [5253] */ + (xdc_Char)0x69, /* [5254] */ + (xdc_Char)0x74, /* [5255] */ + (xdc_Char)0x63, /* [5256] */ + (xdc_Char)0x68, /* [5257] */ + (xdc_Char)0x3a, /* [5258] */ + (xdc_Char)0x20, /* [5259] */ + (xdc_Char)0x6f, /* [5260] */ + (xdc_Char)0x6c, /* [5261] */ + (xdc_Char)0x64, /* [5262] */ + (xdc_Char)0x74, /* [5263] */ + (xdc_Char)0x73, /* [5264] */ + (xdc_Char)0x6b, /* [5265] */ + (xdc_Char)0x3a, /* [5266] */ + (xdc_Char)0x20, /* [5267] */ + (xdc_Char)0x30, /* [5268] */ + (xdc_Char)0x78, /* [5269] */ + (xdc_Char)0x25, /* [5270] */ + (xdc_Char)0x78, /* [5271] */ + (xdc_Char)0x2c, /* [5272] */ + (xdc_Char)0x20, /* [5273] */ + (xdc_Char)0x6f, /* [5274] */ + (xdc_Char)0x6c, /* [5275] */ + (xdc_Char)0x64, /* [5276] */ + (xdc_Char)0x66, /* [5277] */ + (xdc_Char)0x75, /* [5278] */ + (xdc_Char)0x6e, /* [5279] */ + (xdc_Char)0x63, /* [5280] */ + (xdc_Char)0x3a, /* [5281] */ + (xdc_Char)0x20, /* [5282] */ + (xdc_Char)0x30, /* [5283] */ + (xdc_Char)0x78, /* [5284] */ + (xdc_Char)0x25, /* [5285] */ + (xdc_Char)0x78, /* [5286] */ + (xdc_Char)0x2c, /* [5287] */ + (xdc_Char)0x20, /* [5288] */ + (xdc_Char)0x6e, /* [5289] */ + (xdc_Char)0x65, /* [5290] */ + (xdc_Char)0x77, /* [5291] */ + (xdc_Char)0x74, /* [5292] */ + (xdc_Char)0x73, /* [5293] */ + (xdc_Char)0x6b, /* [5294] */ + (xdc_Char)0x3a, /* [5295] */ + (xdc_Char)0x20, /* [5296] */ + (xdc_Char)0x30, /* [5297] */ + (xdc_Char)0x78, /* [5298] */ + (xdc_Char)0x25, /* [5299] */ + (xdc_Char)0x78, /* [5300] */ + (xdc_Char)0x2c, /* [5301] */ + (xdc_Char)0x20, /* [5302] */ + (xdc_Char)0x6e, /* [5303] */ + (xdc_Char)0x65, /* [5304] */ + (xdc_Char)0x77, /* [5305] */ + (xdc_Char)0x66, /* [5306] */ + (xdc_Char)0x75, /* [5307] */ + (xdc_Char)0x6e, /* [5308] */ + (xdc_Char)0x63, /* [5309] */ + (xdc_Char)0x3a, /* [5310] */ + (xdc_Char)0x20, /* [5311] */ + (xdc_Char)0x30, /* [5312] */ + (xdc_Char)0x78, /* [5313] */ + (xdc_Char)0x25, /* [5314] */ + (xdc_Char)0x78, /* [5315] */ + (xdc_Char)0x0, /* [5316] */ + (xdc_Char)0x4c, /* [5317] */ + (xdc_Char)0x4d, /* [5318] */ + (xdc_Char)0x5f, /* [5319] */ + (xdc_Char)0x73, /* [5320] */ + (xdc_Char)0x6c, /* [5321] */ + (xdc_Char)0x65, /* [5322] */ + (xdc_Char)0x65, /* [5323] */ + (xdc_Char)0x70, /* [5324] */ + (xdc_Char)0x3a, /* [5325] */ + (xdc_Char)0x20, /* [5326] */ + (xdc_Char)0x74, /* [5327] */ + (xdc_Char)0x73, /* [5328] */ + (xdc_Char)0x6b, /* [5329] */ + (xdc_Char)0x3a, /* [5330] */ + (xdc_Char)0x20, /* [5331] */ + (xdc_Char)0x30, /* [5332] */ + (xdc_Char)0x78, /* [5333] */ + (xdc_Char)0x25, /* [5334] */ + (xdc_Char)0x78, /* [5335] */ + (xdc_Char)0x2c, /* [5336] */ + (xdc_Char)0x20, /* [5337] */ + (xdc_Char)0x66, /* [5338] */ + (xdc_Char)0x75, /* [5339] */ + (xdc_Char)0x6e, /* [5340] */ + (xdc_Char)0x63, /* [5341] */ + (xdc_Char)0x3a, /* [5342] */ + (xdc_Char)0x20, /* [5343] */ + (xdc_Char)0x30, /* [5344] */ + (xdc_Char)0x78, /* [5345] */ + (xdc_Char)0x25, /* [5346] */ + (xdc_Char)0x78, /* [5347] */ + (xdc_Char)0x2c, /* [5348] */ + (xdc_Char)0x20, /* [5349] */ + (xdc_Char)0x74, /* [5350] */ + (xdc_Char)0x69, /* [5351] */ + (xdc_Char)0x6d, /* [5352] */ + (xdc_Char)0x65, /* [5353] */ + (xdc_Char)0x6f, /* [5354] */ + (xdc_Char)0x75, /* [5355] */ + (xdc_Char)0x74, /* [5356] */ + (xdc_Char)0x3a, /* [5357] */ + (xdc_Char)0x20, /* [5358] */ + (xdc_Char)0x25, /* [5359] */ + (xdc_Char)0x64, /* [5360] */ + (xdc_Char)0x0, /* [5361] */ + (xdc_Char)0x4c, /* [5362] */ + (xdc_Char)0x44, /* [5363] */ + (xdc_Char)0x5f, /* [5364] */ + (xdc_Char)0x72, /* [5365] */ + (xdc_Char)0x65, /* [5366] */ + (xdc_Char)0x61, /* [5367] */ + (xdc_Char)0x64, /* [5368] */ + (xdc_Char)0x79, /* [5369] */ + (xdc_Char)0x3a, /* [5370] */ + (xdc_Char)0x20, /* [5371] */ + (xdc_Char)0x74, /* [5372] */ + (xdc_Char)0x73, /* [5373] */ + (xdc_Char)0x6b, /* [5374] */ + (xdc_Char)0x3a, /* [5375] */ + (xdc_Char)0x20, /* [5376] */ + (xdc_Char)0x30, /* [5377] */ + (xdc_Char)0x78, /* [5378] */ + (xdc_Char)0x25, /* [5379] */ + (xdc_Char)0x78, /* [5380] */ + (xdc_Char)0x2c, /* [5381] */ + (xdc_Char)0x20, /* [5382] */ + (xdc_Char)0x66, /* [5383] */ + (xdc_Char)0x75, /* [5384] */ + (xdc_Char)0x6e, /* [5385] */ + (xdc_Char)0x63, /* [5386] */ + (xdc_Char)0x3a, /* [5387] */ + (xdc_Char)0x20, /* [5388] */ + (xdc_Char)0x30, /* [5389] */ + (xdc_Char)0x78, /* [5390] */ + (xdc_Char)0x25, /* [5391] */ + (xdc_Char)0x78, /* [5392] */ + (xdc_Char)0x2c, /* [5393] */ + (xdc_Char)0x20, /* [5394] */ + (xdc_Char)0x70, /* [5395] */ + (xdc_Char)0x72, /* [5396] */ + (xdc_Char)0x69, /* [5397] */ + (xdc_Char)0x3a, /* [5398] */ + (xdc_Char)0x20, /* [5399] */ + (xdc_Char)0x25, /* [5400] */ + (xdc_Char)0x64, /* [5401] */ + (xdc_Char)0x0, /* [5402] */ + (xdc_Char)0x4c, /* [5403] */ + (xdc_Char)0x44, /* [5404] */ + (xdc_Char)0x5f, /* [5405] */ + (xdc_Char)0x62, /* [5406] */ + (xdc_Char)0x6c, /* [5407] */ + (xdc_Char)0x6f, /* [5408] */ + (xdc_Char)0x63, /* [5409] */ + (xdc_Char)0x6b, /* [5410] */ + (xdc_Char)0x3a, /* [5411] */ + (xdc_Char)0x20, /* [5412] */ + (xdc_Char)0x74, /* [5413] */ + (xdc_Char)0x73, /* [5414] */ + (xdc_Char)0x6b, /* [5415] */ + (xdc_Char)0x3a, /* [5416] */ + (xdc_Char)0x20, /* [5417] */ + (xdc_Char)0x30, /* [5418] */ + (xdc_Char)0x78, /* [5419] */ + (xdc_Char)0x25, /* [5420] */ + (xdc_Char)0x78, /* [5421] */ + (xdc_Char)0x2c, /* [5422] */ + (xdc_Char)0x20, /* [5423] */ + (xdc_Char)0x66, /* [5424] */ + (xdc_Char)0x75, /* [5425] */ + (xdc_Char)0x6e, /* [5426] */ + (xdc_Char)0x63, /* [5427] */ + (xdc_Char)0x3a, /* [5428] */ + (xdc_Char)0x20, /* [5429] */ + (xdc_Char)0x30, /* [5430] */ + (xdc_Char)0x78, /* [5431] */ + (xdc_Char)0x25, /* [5432] */ + (xdc_Char)0x78, /* [5433] */ + (xdc_Char)0x0, /* [5434] */ + (xdc_Char)0x4c, /* [5435] */ + (xdc_Char)0x4d, /* [5436] */ + (xdc_Char)0x5f, /* [5437] */ + (xdc_Char)0x79, /* [5438] */ + (xdc_Char)0x69, /* [5439] */ + (xdc_Char)0x65, /* [5440] */ + (xdc_Char)0x6c, /* [5441] */ + (xdc_Char)0x64, /* [5442] */ + (xdc_Char)0x3a, /* [5443] */ + (xdc_Char)0x20, /* [5444] */ + (xdc_Char)0x74, /* [5445] */ + (xdc_Char)0x73, /* [5446] */ + (xdc_Char)0x6b, /* [5447] */ + (xdc_Char)0x3a, /* [5448] */ + (xdc_Char)0x20, /* [5449] */ + (xdc_Char)0x30, /* [5450] */ + (xdc_Char)0x78, /* [5451] */ + (xdc_Char)0x25, /* [5452] */ + (xdc_Char)0x78, /* [5453] */ + (xdc_Char)0x2c, /* [5454] */ + (xdc_Char)0x20, /* [5455] */ + (xdc_Char)0x66, /* [5456] */ + (xdc_Char)0x75, /* [5457] */ + (xdc_Char)0x6e, /* [5458] */ + (xdc_Char)0x63, /* [5459] */ + (xdc_Char)0x3a, /* [5460] */ + (xdc_Char)0x20, /* [5461] */ + (xdc_Char)0x30, /* [5462] */ + (xdc_Char)0x78, /* [5463] */ + (xdc_Char)0x25, /* [5464] */ + (xdc_Char)0x78, /* [5465] */ + (xdc_Char)0x2c, /* [5466] */ + (xdc_Char)0x20, /* [5467] */ + (xdc_Char)0x63, /* [5468] */ + (xdc_Char)0x75, /* [5469] */ + (xdc_Char)0x72, /* [5470] */ + (xdc_Char)0x72, /* [5471] */ + (xdc_Char)0x54, /* [5472] */ + (xdc_Char)0x68, /* [5473] */ + (xdc_Char)0x72, /* [5474] */ + (xdc_Char)0x65, /* [5475] */ + (xdc_Char)0x61, /* [5476] */ + (xdc_Char)0x64, /* [5477] */ + (xdc_Char)0x3a, /* [5478] */ + (xdc_Char)0x20, /* [5479] */ + (xdc_Char)0x25, /* [5480] */ + (xdc_Char)0x64, /* [5481] */ + (xdc_Char)0x0, /* [5482] */ + (xdc_Char)0x4c, /* [5483] */ + (xdc_Char)0x4d, /* [5484] */ + (xdc_Char)0x5f, /* [5485] */ + (xdc_Char)0x73, /* [5486] */ + (xdc_Char)0x65, /* [5487] */ + (xdc_Char)0x74, /* [5488] */ + (xdc_Char)0x50, /* [5489] */ + (xdc_Char)0x72, /* [5490] */ + (xdc_Char)0x69, /* [5491] */ + (xdc_Char)0x3a, /* [5492] */ + (xdc_Char)0x20, /* [5493] */ + (xdc_Char)0x74, /* [5494] */ + (xdc_Char)0x73, /* [5495] */ + (xdc_Char)0x6b, /* [5496] */ + (xdc_Char)0x3a, /* [5497] */ + (xdc_Char)0x20, /* [5498] */ + (xdc_Char)0x30, /* [5499] */ + (xdc_Char)0x78, /* [5500] */ + (xdc_Char)0x25, /* [5501] */ + (xdc_Char)0x78, /* [5502] */ + (xdc_Char)0x2c, /* [5503] */ + (xdc_Char)0x20, /* [5504] */ + (xdc_Char)0x66, /* [5505] */ + (xdc_Char)0x75, /* [5506] */ + (xdc_Char)0x6e, /* [5507] */ + (xdc_Char)0x63, /* [5508] */ + (xdc_Char)0x3a, /* [5509] */ + (xdc_Char)0x20, /* [5510] */ + (xdc_Char)0x30, /* [5511] */ + (xdc_Char)0x78, /* [5512] */ + (xdc_Char)0x25, /* [5513] */ + (xdc_Char)0x78, /* [5514] */ + (xdc_Char)0x2c, /* [5515] */ + (xdc_Char)0x20, /* [5516] */ + (xdc_Char)0x6f, /* [5517] */ + (xdc_Char)0x6c, /* [5518] */ + (xdc_Char)0x64, /* [5519] */ + (xdc_Char)0x50, /* [5520] */ + (xdc_Char)0x72, /* [5521] */ + (xdc_Char)0x69, /* [5522] */ + (xdc_Char)0x3a, /* [5523] */ + (xdc_Char)0x20, /* [5524] */ + (xdc_Char)0x25, /* [5525] */ + (xdc_Char)0x64, /* [5526] */ + (xdc_Char)0x2c, /* [5527] */ + (xdc_Char)0x20, /* [5528] */ + (xdc_Char)0x6e, /* [5529] */ + (xdc_Char)0x65, /* [5530] */ + (xdc_Char)0x77, /* [5531] */ + (xdc_Char)0x50, /* [5532] */ + (xdc_Char)0x72, /* [5533] */ + (xdc_Char)0x69, /* [5534] */ + (xdc_Char)0x20, /* [5535] */ + (xdc_Char)0x25, /* [5536] */ + (xdc_Char)0x64, /* [5537] */ + (xdc_Char)0x0, /* [5538] */ + (xdc_Char)0x4c, /* [5539] */ + (xdc_Char)0x44, /* [5540] */ + (xdc_Char)0x5f, /* [5541] */ + (xdc_Char)0x65, /* [5542] */ + (xdc_Char)0x78, /* [5543] */ + (xdc_Char)0x69, /* [5544] */ + (xdc_Char)0x74, /* [5545] */ + (xdc_Char)0x3a, /* [5546] */ + (xdc_Char)0x20, /* [5547] */ + (xdc_Char)0x74, /* [5548] */ + (xdc_Char)0x73, /* [5549] */ + (xdc_Char)0x6b, /* [5550] */ + (xdc_Char)0x3a, /* [5551] */ + (xdc_Char)0x20, /* [5552] */ + (xdc_Char)0x30, /* [5553] */ + (xdc_Char)0x78, /* [5554] */ + (xdc_Char)0x25, /* [5555] */ + (xdc_Char)0x78, /* [5556] */ + (xdc_Char)0x2c, /* [5557] */ + (xdc_Char)0x20, /* [5558] */ + (xdc_Char)0x66, /* [5559] */ + (xdc_Char)0x75, /* [5560] */ + (xdc_Char)0x6e, /* [5561] */ + (xdc_Char)0x63, /* [5562] */ + (xdc_Char)0x3a, /* [5563] */ + (xdc_Char)0x20, /* [5564] */ + (xdc_Char)0x30, /* [5565] */ + (xdc_Char)0x78, /* [5566] */ + (xdc_Char)0x25, /* [5567] */ + (xdc_Char)0x78, /* [5568] */ + (xdc_Char)0x0, /* [5569] */ + (xdc_Char)0x4c, /* [5570] */ + (xdc_Char)0x4d, /* [5571] */ + (xdc_Char)0x5f, /* [5572] */ + (xdc_Char)0x73, /* [5573] */ + (xdc_Char)0x65, /* [5574] */ + (xdc_Char)0x74, /* [5575] */ + (xdc_Char)0x41, /* [5576] */ + (xdc_Char)0x66, /* [5577] */ + (xdc_Char)0x66, /* [5578] */ + (xdc_Char)0x69, /* [5579] */ + (xdc_Char)0x6e, /* [5580] */ + (xdc_Char)0x69, /* [5581] */ + (xdc_Char)0x74, /* [5582] */ + (xdc_Char)0x79, /* [5583] */ + (xdc_Char)0x3a, /* [5584] */ + (xdc_Char)0x20, /* [5585] */ + (xdc_Char)0x74, /* [5586] */ + (xdc_Char)0x73, /* [5587] */ + (xdc_Char)0x6b, /* [5588] */ + (xdc_Char)0x3a, /* [5589] */ + (xdc_Char)0x20, /* [5590] */ + (xdc_Char)0x30, /* [5591] */ + (xdc_Char)0x78, /* [5592] */ + (xdc_Char)0x25, /* [5593] */ + (xdc_Char)0x78, /* [5594] */ + (xdc_Char)0x2c, /* [5595] */ + (xdc_Char)0x20, /* [5596] */ + (xdc_Char)0x66, /* [5597] */ + (xdc_Char)0x75, /* [5598] */ + (xdc_Char)0x6e, /* [5599] */ + (xdc_Char)0x63, /* [5600] */ + (xdc_Char)0x3a, /* [5601] */ + (xdc_Char)0x20, /* [5602] */ + (xdc_Char)0x30, /* [5603] */ + (xdc_Char)0x78, /* [5604] */ + (xdc_Char)0x25, /* [5605] */ + (xdc_Char)0x78, /* [5606] */ + (xdc_Char)0x2c, /* [5607] */ + (xdc_Char)0x20, /* [5608] */ + (xdc_Char)0x6f, /* [5609] */ + (xdc_Char)0x6c, /* [5610] */ + (xdc_Char)0x64, /* [5611] */ + (xdc_Char)0x43, /* [5612] */ + (xdc_Char)0x6f, /* [5613] */ + (xdc_Char)0x72, /* [5614] */ + (xdc_Char)0x65, /* [5615] */ + (xdc_Char)0x3a, /* [5616] */ + (xdc_Char)0x20, /* [5617] */ + (xdc_Char)0x25, /* [5618] */ + (xdc_Char)0x64, /* [5619] */ + (xdc_Char)0x2c, /* [5620] */ + (xdc_Char)0x20, /* [5621] */ + (xdc_Char)0x6f, /* [5622] */ + (xdc_Char)0x6c, /* [5623] */ + (xdc_Char)0x64, /* [5624] */ + (xdc_Char)0x41, /* [5625] */ + (xdc_Char)0x66, /* [5626] */ + (xdc_Char)0x66, /* [5627] */ + (xdc_Char)0x69, /* [5628] */ + (xdc_Char)0x6e, /* [5629] */ + (xdc_Char)0x69, /* [5630] */ + (xdc_Char)0x74, /* [5631] */ + (xdc_Char)0x79, /* [5632] */ + (xdc_Char)0x20, /* [5633] */ + (xdc_Char)0x25, /* [5634] */ + (xdc_Char)0x64, /* [5635] */ + (xdc_Char)0x2c, /* [5636] */ + (xdc_Char)0x20, /* [5637] */ + (xdc_Char)0x6e, /* [5638] */ + (xdc_Char)0x65, /* [5639] */ + (xdc_Char)0x77, /* [5640] */ + (xdc_Char)0x41, /* [5641] */ + (xdc_Char)0x66, /* [5642] */ + (xdc_Char)0x66, /* [5643] */ + (xdc_Char)0x69, /* [5644] */ + (xdc_Char)0x6e, /* [5645] */ + (xdc_Char)0x69, /* [5646] */ + (xdc_Char)0x74, /* [5647] */ + (xdc_Char)0x79, /* [5648] */ + (xdc_Char)0x20, /* [5649] */ + (xdc_Char)0x25, /* [5650] */ + (xdc_Char)0x64, /* [5651] */ + (xdc_Char)0x0, /* [5652] */ + (xdc_Char)0x4c, /* [5653] */ + (xdc_Char)0x44, /* [5654] */ + (xdc_Char)0x5f, /* [5655] */ + (xdc_Char)0x73, /* [5656] */ + (xdc_Char)0x63, /* [5657] */ + (xdc_Char)0x68, /* [5658] */ + (xdc_Char)0x65, /* [5659] */ + (xdc_Char)0x64, /* [5660] */ + (xdc_Char)0x75, /* [5661] */ + (xdc_Char)0x6c, /* [5662] */ + (xdc_Char)0x65, /* [5663] */ + (xdc_Char)0x3a, /* [5664] */ + (xdc_Char)0x20, /* [5665] */ + (xdc_Char)0x63, /* [5666] */ + (xdc_Char)0x6f, /* [5667] */ + (xdc_Char)0x72, /* [5668] */ + (xdc_Char)0x65, /* [5669] */ + (xdc_Char)0x49, /* [5670] */ + (xdc_Char)0x64, /* [5671] */ + (xdc_Char)0x3a, /* [5672] */ + (xdc_Char)0x20, /* [5673] */ + (xdc_Char)0x25, /* [5674] */ + (xdc_Char)0x64, /* [5675] */ + (xdc_Char)0x2c, /* [5676] */ + (xdc_Char)0x20, /* [5677] */ + (xdc_Char)0x77, /* [5678] */ + (xdc_Char)0x6f, /* [5679] */ + (xdc_Char)0x72, /* [5680] */ + (xdc_Char)0x6b, /* [5681] */ + (xdc_Char)0x46, /* [5682] */ + (xdc_Char)0x6c, /* [5683] */ + (xdc_Char)0x61, /* [5684] */ + (xdc_Char)0x67, /* [5685] */ + (xdc_Char)0x3a, /* [5686] */ + (xdc_Char)0x20, /* [5687] */ + (xdc_Char)0x25, /* [5688] */ + (xdc_Char)0x64, /* [5689] */ + (xdc_Char)0x2c, /* [5690] */ + (xdc_Char)0x20, /* [5691] */ + (xdc_Char)0x63, /* [5692] */ + (xdc_Char)0x75, /* [5693] */ + (xdc_Char)0x72, /* [5694] */ + (xdc_Char)0x53, /* [5695] */ + (xdc_Char)0x65, /* [5696] */ + (xdc_Char)0x74, /* [5697] */ + (xdc_Char)0x4c, /* [5698] */ + (xdc_Char)0x6f, /* [5699] */ + (xdc_Char)0x63, /* [5700] */ + (xdc_Char)0x61, /* [5701] */ + (xdc_Char)0x6c, /* [5702] */ + (xdc_Char)0x3a, /* [5703] */ + (xdc_Char)0x20, /* [5704] */ + (xdc_Char)0x25, /* [5705] */ + (xdc_Char)0x64, /* [5706] */ + (xdc_Char)0x2c, /* [5707] */ + (xdc_Char)0x20, /* [5708] */ + (xdc_Char)0x63, /* [5709] */ + (xdc_Char)0x75, /* [5710] */ + (xdc_Char)0x72, /* [5711] */ + (xdc_Char)0x53, /* [5712] */ + (xdc_Char)0x65, /* [5713] */ + (xdc_Char)0x74, /* [5714] */ + (xdc_Char)0x58, /* [5715] */ + (xdc_Char)0x3a, /* [5716] */ + (xdc_Char)0x20, /* [5717] */ + (xdc_Char)0x25, /* [5718] */ + (xdc_Char)0x64, /* [5719] */ + (xdc_Char)0x2c, /* [5720] */ + (xdc_Char)0x20, /* [5721] */ + (xdc_Char)0x63, /* [5722] */ + (xdc_Char)0x75, /* [5723] */ + (xdc_Char)0x72, /* [5724] */ + (xdc_Char)0x4d, /* [5725] */ + (xdc_Char)0x61, /* [5726] */ + (xdc_Char)0x73, /* [5727] */ + (xdc_Char)0x6b, /* [5728] */ + (xdc_Char)0x4c, /* [5729] */ + (xdc_Char)0x6f, /* [5730] */ + (xdc_Char)0x63, /* [5731] */ + (xdc_Char)0x61, /* [5732] */ + (xdc_Char)0x6c, /* [5733] */ + (xdc_Char)0x3a, /* [5734] */ + (xdc_Char)0x20, /* [5735] */ + (xdc_Char)0x25, /* [5736] */ + (xdc_Char)0x64, /* [5737] */ + (xdc_Char)0x0, /* [5738] */ + (xdc_Char)0x4c, /* [5739] */ + (xdc_Char)0x44, /* [5740] */ + (xdc_Char)0x5f, /* [5741] */ + (xdc_Char)0x6e, /* [5742] */ + (xdc_Char)0x6f, /* [5743] */ + (xdc_Char)0x57, /* [5744] */ + (xdc_Char)0x6f, /* [5745] */ + (xdc_Char)0x72, /* [5746] */ + (xdc_Char)0x6b, /* [5747] */ + (xdc_Char)0x3a, /* [5748] */ + (xdc_Char)0x20, /* [5749] */ + (xdc_Char)0x63, /* [5750] */ + (xdc_Char)0x6f, /* [5751] */ + (xdc_Char)0x72, /* [5752] */ + (xdc_Char)0x65, /* [5753] */ + (xdc_Char)0x49, /* [5754] */ + (xdc_Char)0x64, /* [5755] */ + (xdc_Char)0x3a, /* [5756] */ + (xdc_Char)0x20, /* [5757] */ + (xdc_Char)0x25, /* [5758] */ + (xdc_Char)0x64, /* [5759] */ + (xdc_Char)0x2c, /* [5760] */ + (xdc_Char)0x20, /* [5761] */ + (xdc_Char)0x63, /* [5762] */ + (xdc_Char)0x75, /* [5763] */ + (xdc_Char)0x72, /* [5764] */ + (xdc_Char)0x53, /* [5765] */ + (xdc_Char)0x65, /* [5766] */ + (xdc_Char)0x74, /* [5767] */ + (xdc_Char)0x4c, /* [5768] */ + (xdc_Char)0x6f, /* [5769] */ + (xdc_Char)0x63, /* [5770] */ + (xdc_Char)0x61, /* [5771] */ + (xdc_Char)0x6c, /* [5772] */ + (xdc_Char)0x3a, /* [5773] */ + (xdc_Char)0x20, /* [5774] */ + (xdc_Char)0x25, /* [5775] */ + (xdc_Char)0x64, /* [5776] */ + (xdc_Char)0x2c, /* [5777] */ + (xdc_Char)0x20, /* [5778] */ + (xdc_Char)0x63, /* [5779] */ + (xdc_Char)0x75, /* [5780] */ + (xdc_Char)0x72, /* [5781] */ + (xdc_Char)0x53, /* [5782] */ + (xdc_Char)0x65, /* [5783] */ + (xdc_Char)0x74, /* [5784] */ + (xdc_Char)0x58, /* [5785] */ + (xdc_Char)0x3a, /* [5786] */ + (xdc_Char)0x20, /* [5787] */ + (xdc_Char)0x25, /* [5788] */ + (xdc_Char)0x64, /* [5789] */ + (xdc_Char)0x2c, /* [5790] */ + (xdc_Char)0x20, /* [5791] */ + (xdc_Char)0x63, /* [5792] */ + (xdc_Char)0x75, /* [5793] */ + (xdc_Char)0x72, /* [5794] */ + (xdc_Char)0x4d, /* [5795] */ + (xdc_Char)0x61, /* [5796] */ + (xdc_Char)0x73, /* [5797] */ + (xdc_Char)0x6b, /* [5798] */ + (xdc_Char)0x4c, /* [5799] */ + (xdc_Char)0x6f, /* [5800] */ + (xdc_Char)0x63, /* [5801] */ + (xdc_Char)0x61, /* [5802] */ + (xdc_Char)0x6c, /* [5803] */ + (xdc_Char)0x3a, /* [5804] */ + (xdc_Char)0x20, /* [5805] */ + (xdc_Char)0x25, /* [5806] */ + (xdc_Char)0x64, /* [5807] */ + (xdc_Char)0x0, /* [5808] */ + (xdc_Char)0x4c, /* [5809] */ + (xdc_Char)0x4d, /* [5810] */ + (xdc_Char)0x5f, /* [5811] */ + (xdc_Char)0x62, /* [5812] */ + (xdc_Char)0x65, /* [5813] */ + (xdc_Char)0x67, /* [5814] */ + (xdc_Char)0x69, /* [5815] */ + (xdc_Char)0x6e, /* [5816] */ + (xdc_Char)0x3a, /* [5817] */ + (xdc_Char)0x20, /* [5818] */ + (xdc_Char)0x68, /* [5819] */ + (xdc_Char)0x77, /* [5820] */ + (xdc_Char)0x69, /* [5821] */ + (xdc_Char)0x3a, /* [5822] */ + (xdc_Char)0x20, /* [5823] */ + (xdc_Char)0x30, /* [5824] */ + (xdc_Char)0x78, /* [5825] */ + (xdc_Char)0x25, /* [5826] */ + (xdc_Char)0x78, /* [5827] */ + (xdc_Char)0x2c, /* [5828] */ + (xdc_Char)0x20, /* [5829] */ + (xdc_Char)0x66, /* [5830] */ + (xdc_Char)0x75, /* [5831] */ + (xdc_Char)0x6e, /* [5832] */ + (xdc_Char)0x63, /* [5833] */ + (xdc_Char)0x3a, /* [5834] */ + (xdc_Char)0x20, /* [5835] */ + (xdc_Char)0x30, /* [5836] */ + (xdc_Char)0x78, /* [5837] */ + (xdc_Char)0x25, /* [5838] */ + (xdc_Char)0x78, /* [5839] */ + (xdc_Char)0x2c, /* [5840] */ + (xdc_Char)0x20, /* [5841] */ + (xdc_Char)0x70, /* [5842] */ + (xdc_Char)0x72, /* [5843] */ + (xdc_Char)0x65, /* [5844] */ + (xdc_Char)0x54, /* [5845] */ + (xdc_Char)0x68, /* [5846] */ + (xdc_Char)0x72, /* [5847] */ + (xdc_Char)0x65, /* [5848] */ + (xdc_Char)0x61, /* [5849] */ + (xdc_Char)0x64, /* [5850] */ + (xdc_Char)0x3a, /* [5851] */ + (xdc_Char)0x20, /* [5852] */ + (xdc_Char)0x25, /* [5853] */ + (xdc_Char)0x64, /* [5854] */ + (xdc_Char)0x2c, /* [5855] */ + (xdc_Char)0x20, /* [5856] */ + (xdc_Char)0x69, /* [5857] */ + (xdc_Char)0x6e, /* [5858] */ + (xdc_Char)0x74, /* [5859] */ + (xdc_Char)0x4e, /* [5860] */ + (xdc_Char)0x75, /* [5861] */ + (xdc_Char)0x6d, /* [5862] */ + (xdc_Char)0x3a, /* [5863] */ + (xdc_Char)0x20, /* [5864] */ + (xdc_Char)0x25, /* [5865] */ + (xdc_Char)0x64, /* [5866] */ + (xdc_Char)0x2c, /* [5867] */ + (xdc_Char)0x20, /* [5868] */ + (xdc_Char)0x69, /* [5869] */ + (xdc_Char)0x72, /* [5870] */ + (xdc_Char)0x70, /* [5871] */ + (xdc_Char)0x3a, /* [5872] */ + (xdc_Char)0x20, /* [5873] */ + (xdc_Char)0x30, /* [5874] */ + (xdc_Char)0x78, /* [5875] */ + (xdc_Char)0x25, /* [5876] */ + (xdc_Char)0x78, /* [5877] */ + (xdc_Char)0x0, /* [5878] */ + (xdc_Char)0x4c, /* [5879] */ + (xdc_Char)0x44, /* [5880] */ + (xdc_Char)0x5f, /* [5881] */ + (xdc_Char)0x65, /* [5882] */ + (xdc_Char)0x6e, /* [5883] */ + (xdc_Char)0x64, /* [5884] */ + (xdc_Char)0x3a, /* [5885] */ + (xdc_Char)0x20, /* [5886] */ + (xdc_Char)0x68, /* [5887] */ + (xdc_Char)0x77, /* [5888] */ + (xdc_Char)0x69, /* [5889] */ + (xdc_Char)0x3a, /* [5890] */ + (xdc_Char)0x20, /* [5891] */ + (xdc_Char)0x30, /* [5892] */ + (xdc_Char)0x78, /* [5893] */ + (xdc_Char)0x25, /* [5894] */ + (xdc_Char)0x78, /* [5895] */ + (xdc_Char)0x0, /* [5896] */ + (xdc_Char)0x78, /* [5897] */ + (xdc_Char)0x64, /* [5898] */ + (xdc_Char)0x63, /* [5899] */ + (xdc_Char)0x2e, /* [5900] */ + (xdc_Char)0x0, /* [5901] */ + (xdc_Char)0x72, /* [5902] */ + (xdc_Char)0x75, /* [5903] */ + (xdc_Char)0x6e, /* [5904] */ + (xdc_Char)0x74, /* [5905] */ + (xdc_Char)0x69, /* [5906] */ + (xdc_Char)0x6d, /* [5907] */ + (xdc_Char)0x65, /* [5908] */ + (xdc_Char)0x2e, /* [5909] */ + (xdc_Char)0x0, /* [5910] */ + (xdc_Char)0x41, /* [5911] */ + (xdc_Char)0x73, /* [5912] */ + (xdc_Char)0x73, /* [5913] */ + (xdc_Char)0x65, /* [5914] */ + (xdc_Char)0x72, /* [5915] */ + (xdc_Char)0x74, /* [5916] */ + (xdc_Char)0x0, /* [5917] */ + (xdc_Char)0x43, /* [5918] */ + (xdc_Char)0x6f, /* [5919] */ + (xdc_Char)0x72, /* [5920] */ + (xdc_Char)0x65, /* [5921] */ + (xdc_Char)0x0, /* [5922] */ + (xdc_Char)0x44, /* [5923] */ + (xdc_Char)0x65, /* [5924] */ + (xdc_Char)0x66, /* [5925] */ + (xdc_Char)0x61, /* [5926] */ + (xdc_Char)0x75, /* [5927] */ + (xdc_Char)0x6c, /* [5928] */ + (xdc_Char)0x74, /* [5929] */ + (xdc_Char)0x73, /* [5930] */ + (xdc_Char)0x0, /* [5931] */ + (xdc_Char)0x44, /* [5932] */ + (xdc_Char)0x69, /* [5933] */ + (xdc_Char)0x61, /* [5934] */ + (xdc_Char)0x67, /* [5935] */ + (xdc_Char)0x73, /* [5936] */ + (xdc_Char)0x0, /* [5937] */ + (xdc_Char)0x45, /* [5938] */ + (xdc_Char)0x72, /* [5939] */ + (xdc_Char)0x72, /* [5940] */ + (xdc_Char)0x6f, /* [5941] */ + (xdc_Char)0x72, /* [5942] */ + (xdc_Char)0x0, /* [5943] */ + (xdc_Char)0x47, /* [5944] */ + (xdc_Char)0x61, /* [5945] */ + (xdc_Char)0x74, /* [5946] */ + (xdc_Char)0x65, /* [5947] */ + (xdc_Char)0x0, /* [5948] */ + (xdc_Char)0x4c, /* [5949] */ + (xdc_Char)0x6f, /* [5950] */ + (xdc_Char)0x67, /* [5951] */ + (xdc_Char)0x0, /* [5952] */ + (xdc_Char)0x4d, /* [5953] */ + (xdc_Char)0x61, /* [5954] */ + (xdc_Char)0x69, /* [5955] */ + (xdc_Char)0x6e, /* [5956] */ + (xdc_Char)0x0, /* [5957] */ + (xdc_Char)0x4d, /* [5958] */ + (xdc_Char)0x65, /* [5959] */ + (xdc_Char)0x6d, /* [5960] */ + (xdc_Char)0x6f, /* [5961] */ + (xdc_Char)0x72, /* [5962] */ + (xdc_Char)0x79, /* [5963] */ + (xdc_Char)0x0, /* [5964] */ + (xdc_Char)0x52, /* [5965] */ + (xdc_Char)0x65, /* [5966] */ + (xdc_Char)0x67, /* [5967] */ + (xdc_Char)0x69, /* [5968] */ + (xdc_Char)0x73, /* [5969] */ + (xdc_Char)0x74, /* [5970] */ + (xdc_Char)0x72, /* [5971] */ + (xdc_Char)0x79, /* [5972] */ + (xdc_Char)0x0, /* [5973] */ + (xdc_Char)0x53, /* [5974] */ + (xdc_Char)0x74, /* [5975] */ + (xdc_Char)0x61, /* [5976] */ + (xdc_Char)0x72, /* [5977] */ + (xdc_Char)0x74, /* [5978] */ + (xdc_Char)0x75, /* [5979] */ + (xdc_Char)0x70, /* [5980] */ + (xdc_Char)0x0, /* [5981] */ + (xdc_Char)0x53, /* [5982] */ + (xdc_Char)0x79, /* [5983] */ + (xdc_Char)0x73, /* [5984] */ + (xdc_Char)0x74, /* [5985] */ + (xdc_Char)0x65, /* [5986] */ + (xdc_Char)0x6d, /* [5987] */ + (xdc_Char)0x0, /* [5988] */ + (xdc_Char)0x53, /* [5989] */ + (xdc_Char)0x79, /* [5990] */ + (xdc_Char)0x73, /* [5991] */ + (xdc_Char)0x4d, /* [5992] */ + (xdc_Char)0x69, /* [5993] */ + (xdc_Char)0x6e, /* [5994] */ + (xdc_Char)0x0, /* [5995] */ + (xdc_Char)0x54, /* [5996] */ + (xdc_Char)0x65, /* [5997] */ + (xdc_Char)0x78, /* [5998] */ + (xdc_Char)0x74, /* [5999] */ + (xdc_Char)0x0, /* [6000] */ + (xdc_Char)0x74, /* [6001] */ + (xdc_Char)0x69, /* [6002] */ + (xdc_Char)0x2e, /* [6003] */ + (xdc_Char)0x0, /* [6004] */ + (xdc_Char)0x63, /* [6005] */ + (xdc_Char)0x61, /* [6006] */ + (xdc_Char)0x74, /* [6007] */ + (xdc_Char)0x61, /* [6008] */ + (xdc_Char)0x6c, /* [6009] */ + (xdc_Char)0x6f, /* [6010] */ + (xdc_Char)0x67, /* [6011] */ + (xdc_Char)0x2e, /* [6012] */ + (xdc_Char)0x0, /* [6013] */ + (xdc_Char)0x61, /* [6014] */ + (xdc_Char)0x72, /* [6015] */ + (xdc_Char)0x6d, /* [6016] */ + (xdc_Char)0x2e, /* [6017] */ + (xdc_Char)0x0, /* [6018] */ + (xdc_Char)0x63, /* [6019] */ + (xdc_Char)0x6f, /* [6020] */ + (xdc_Char)0x72, /* [6021] */ + (xdc_Char)0x74, /* [6022] */ + (xdc_Char)0x65, /* [6023] */ + (xdc_Char)0x78, /* [6024] */ + (xdc_Char)0x6d, /* [6025] */ + (xdc_Char)0x34, /* [6026] */ + (xdc_Char)0x2e, /* [6027] */ + (xdc_Char)0x0, /* [6028] */ + (xdc_Char)0x74, /* [6029] */ + (xdc_Char)0x69, /* [6030] */ + (xdc_Char)0x76, /* [6031] */ + (xdc_Char)0x61, /* [6032] */ + (xdc_Char)0x2e, /* [6033] */ + (xdc_Char)0x0, /* [6034] */ + (xdc_Char)0x63, /* [6035] */ + (xdc_Char)0x65, /* [6036] */ + (xdc_Char)0x2e, /* [6037] */ + (xdc_Char)0x0, /* [6038] */ + (xdc_Char)0x42, /* [6039] */ + (xdc_Char)0x6f, /* [6040] */ + (xdc_Char)0x6f, /* [6041] */ + (xdc_Char)0x74, /* [6042] */ + (xdc_Char)0x0, /* [6043] */ + (xdc_Char)0x73, /* [6044] */ + (xdc_Char)0x79, /* [6045] */ + (xdc_Char)0x73, /* [6046] */ + (xdc_Char)0x62, /* [6047] */ + (xdc_Char)0x69, /* [6048] */ + (xdc_Char)0x6f, /* [6049] */ + (xdc_Char)0x73, /* [6050] */ + (xdc_Char)0x2e, /* [6051] */ + (xdc_Char)0x0, /* [6052] */ + (xdc_Char)0x6b, /* [6053] */ + (xdc_Char)0x6e, /* [6054] */ + (xdc_Char)0x6c, /* [6055] */ + (xdc_Char)0x2e, /* [6056] */ + (xdc_Char)0x0, /* [6057] */ + (xdc_Char)0x43, /* [6058] */ + (xdc_Char)0x6c, /* [6059] */ + (xdc_Char)0x6f, /* [6060] */ + (xdc_Char)0x63, /* [6061] */ + (xdc_Char)0x6b, /* [6062] */ + (xdc_Char)0x0, /* [6063] */ + (xdc_Char)0x49, /* [6064] */ + (xdc_Char)0x64, /* [6065] */ + (xdc_Char)0x6c, /* [6066] */ + (xdc_Char)0x65, /* [6067] */ + (xdc_Char)0x0, /* [6068] */ + (xdc_Char)0x49, /* [6069] */ + (xdc_Char)0x6e, /* [6070] */ + (xdc_Char)0x74, /* [6071] */ + (xdc_Char)0x72, /* [6072] */ + (xdc_Char)0x69, /* [6073] */ + (xdc_Char)0x6e, /* [6074] */ + (xdc_Char)0x73, /* [6075] */ + (xdc_Char)0x69, /* [6076] */ + (xdc_Char)0x63, /* [6077] */ + (xdc_Char)0x73, /* [6078] */ + (xdc_Char)0x0, /* [6079] */ + (xdc_Char)0x51, /* [6080] */ + (xdc_Char)0x75, /* [6081] */ + (xdc_Char)0x65, /* [6082] */ + (xdc_Char)0x75, /* [6083] */ + (xdc_Char)0x65, /* [6084] */ + (xdc_Char)0x0, /* [6085] */ + (xdc_Char)0x53, /* [6086] */ + (xdc_Char)0x65, /* [6087] */ + (xdc_Char)0x6d, /* [6088] */ + (xdc_Char)0x61, /* [6089] */ + (xdc_Char)0x70, /* [6090] */ + (xdc_Char)0x68, /* [6091] */ + (xdc_Char)0x6f, /* [6092] */ + (xdc_Char)0x72, /* [6093] */ + (xdc_Char)0x65, /* [6094] */ + (xdc_Char)0x0, /* [6095] */ + (xdc_Char)0x53, /* [6096] */ + (xdc_Char)0x77, /* [6097] */ + (xdc_Char)0x69, /* [6098] */ + (xdc_Char)0x0, /* [6099] */ + (xdc_Char)0x54, /* [6100] */ + (xdc_Char)0x61, /* [6101] */ + (xdc_Char)0x73, /* [6102] */ + (xdc_Char)0x6b, /* [6103] */ + (xdc_Char)0x0, /* [6104] */ + (xdc_Char)0x68, /* [6105] */ + (xdc_Char)0x61, /* [6106] */ + (xdc_Char)0x6c, /* [6107] */ + (xdc_Char)0x2e, /* [6108] */ + (xdc_Char)0x0, /* [6109] */ + (xdc_Char)0x48, /* [6110] */ + (xdc_Char)0x77, /* [6111] */ + (xdc_Char)0x69, /* [6112] */ + (xdc_Char)0x0, /* [6113] */ + (xdc_Char)0x42, /* [6114] */ + (xdc_Char)0x49, /* [6115] */ + (xdc_Char)0x4f, /* [6116] */ + (xdc_Char)0x53, /* [6117] */ + (xdc_Char)0x0, /* [6118] */ + (xdc_Char)0x66, /* [6119] */ + (xdc_Char)0x61, /* [6120] */ + (xdc_Char)0x6d, /* [6121] */ + (xdc_Char)0x69, /* [6122] */ + (xdc_Char)0x6c, /* [6123] */ + (xdc_Char)0x79, /* [6124] */ + (xdc_Char)0x2e, /* [6125] */ + (xdc_Char)0x0, /* [6126] */ + (xdc_Char)0x6d, /* [6127] */ + (xdc_Char)0x33, /* [6128] */ + (xdc_Char)0x2e, /* [6129] */ + (xdc_Char)0x0, /* [6130] */ + (xdc_Char)0x49, /* [6131] */ + (xdc_Char)0x6e, /* [6132] */ + (xdc_Char)0x74, /* [6133] */ + (xdc_Char)0x72, /* [6134] */ + (xdc_Char)0x69, /* [6135] */ + (xdc_Char)0x6e, /* [6136] */ + (xdc_Char)0x73, /* [6137] */ + (xdc_Char)0x69, /* [6138] */ + (xdc_Char)0x63, /* [6139] */ + (xdc_Char)0x73, /* [6140] */ + (xdc_Char)0x53, /* [6141] */ + (xdc_Char)0x75, /* [6142] */ + (xdc_Char)0x70, /* [6143] */ + (xdc_Char)0x70, /* [6144] */ + (xdc_Char)0x6f, /* [6145] */ + (xdc_Char)0x72, /* [6146] */ + (xdc_Char)0x74, /* [6147] */ + (xdc_Char)0x0, /* [6148] */ + (xdc_Char)0x54, /* [6149] */ + (xdc_Char)0x61, /* [6150] */ + (xdc_Char)0x73, /* [6151] */ + (xdc_Char)0x6b, /* [6152] */ + (xdc_Char)0x53, /* [6153] */ + (xdc_Char)0x75, /* [6154] */ + (xdc_Char)0x70, /* [6155] */ + (xdc_Char)0x70, /* [6156] */ + (xdc_Char)0x6f, /* [6157] */ + (xdc_Char)0x72, /* [6158] */ + (xdc_Char)0x74, /* [6159] */ + (xdc_Char)0x0, /* [6160] */ + (xdc_Char)0x67, /* [6161] */ + (xdc_Char)0x61, /* [6162] */ + (xdc_Char)0x74, /* [6163] */ + (xdc_Char)0x65, /* [6164] */ + (xdc_Char)0x73, /* [6165] */ + (xdc_Char)0x2e, /* [6166] */ + (xdc_Char)0x0, /* [6167] */ + (xdc_Char)0x47, /* [6168] */ + (xdc_Char)0x61, /* [6169] */ + (xdc_Char)0x74, /* [6170] */ + (xdc_Char)0x65, /* [6171] */ + (xdc_Char)0x48, /* [6172] */ + (xdc_Char)0x77, /* [6173] */ + (xdc_Char)0x69, /* [6174] */ + (xdc_Char)0x0, /* [6175] */ + (xdc_Char)0x47, /* [6176] */ + (xdc_Char)0x61, /* [6177] */ + (xdc_Char)0x74, /* [6178] */ + (xdc_Char)0x65, /* [6179] */ + (xdc_Char)0x4d, /* [6180] */ + (xdc_Char)0x75, /* [6181] */ + (xdc_Char)0x74, /* [6182] */ + (xdc_Char)0x65, /* [6183] */ + (xdc_Char)0x78, /* [6184] */ + (xdc_Char)0x0, /* [6185] */ + (xdc_Char)0x68, /* [6186] */ + (xdc_Char)0x65, /* [6187] */ + (xdc_Char)0x61, /* [6188] */ + (xdc_Char)0x70, /* [6189] */ + (xdc_Char)0x73, /* [6190] */ + (xdc_Char)0x2e, /* [6191] */ + (xdc_Char)0x0, /* [6192] */ + (xdc_Char)0x48, /* [6193] */ + (xdc_Char)0x65, /* [6194] */ + (xdc_Char)0x61, /* [6195] */ + (xdc_Char)0x70, /* [6196] */ + (xdc_Char)0x4d, /* [6197] */ + (xdc_Char)0x65, /* [6198] */ + (xdc_Char)0x6d, /* [6199] */ + (xdc_Char)0x0, /* [6200] */ + (xdc_Char)0x6c, /* [6201] */ + (xdc_Char)0x6d, /* [6202] */ + (xdc_Char)0x34, /* [6203] */ + (xdc_Char)0x2e, /* [6204] */ + (xdc_Char)0x0, /* [6205] */ + (xdc_Char)0x54, /* [6206] */ + (xdc_Char)0x69, /* [6207] */ + (xdc_Char)0x6d, /* [6208] */ + (xdc_Char)0x65, /* [6209] */ + (xdc_Char)0x72, /* [6210] */ + (xdc_Char)0x0, /* [6211] */ + (xdc_Char)0x55, /* [6212] */ + (xdc_Char)0x41, /* [6213] */ + (xdc_Char)0x52, /* [6214] */ + (xdc_Char)0x54, /* [6215] */ + (xdc_Char)0x4d, /* [6216] */ + (xdc_Char)0x6f, /* [6217] */ + (xdc_Char)0x6e, /* [6218] */ + (xdc_Char)0x54, /* [6219] */ + (xdc_Char)0x61, /* [6220] */ + (xdc_Char)0x73, /* [6221] */ + (xdc_Char)0x6b, /* [6222] */ + (xdc_Char)0x0, /* [6223] */ + (xdc_Char)0x74, /* [6224] */ + (xdc_Char)0x69, /* [6225] */ + (xdc_Char)0x2e, /* [6226] */ + (xdc_Char)0x73, /* [6227] */ + (xdc_Char)0x79, /* [6228] */ + (xdc_Char)0x73, /* [6229] */ + (xdc_Char)0x62, /* [6230] */ + (xdc_Char)0x69, /* [6231] */ + (xdc_Char)0x6f, /* [6232] */ + (xdc_Char)0x73, /* [6233] */ + (xdc_Char)0x2e, /* [6234] */ + (xdc_Char)0x6b, /* [6235] */ + (xdc_Char)0x6e, /* [6236] */ + (xdc_Char)0x6c, /* [6237] */ + (xdc_Char)0x2e, /* [6238] */ + (xdc_Char)0x54, /* [6239] */ + (xdc_Char)0x61, /* [6240] */ + (xdc_Char)0x73, /* [6241] */ + (xdc_Char)0x6b, /* [6242] */ + (xdc_Char)0x2e, /* [6243] */ + (xdc_Char)0x49, /* [6244] */ + (xdc_Char)0x64, /* [6245] */ + (xdc_Char)0x6c, /* [6246] */ + (xdc_Char)0x65, /* [6247] */ + (xdc_Char)0x54, /* [6248] */ + (xdc_Char)0x61, /* [6249] */ + (xdc_Char)0x73, /* [6250] */ + (xdc_Char)0x6b, /* [6251] */ + (xdc_Char)0x0, /* [6252] */ +}; + +/* --> xdc_runtime_Text_nodeTab__A */ +#pragma DATA_SECTION(xdc_runtime_Text_nodeTab__A, ".const:xdc_runtime_Text_nodeTab__A"); +const __T1_xdc_runtime_Text_nodeTab xdc_runtime_Text_nodeTab__A[47] = { + { + (xdc_Bits16)0x0, /* left */ + (xdc_Bits16)0x0, /* right */ + }, /* [0] */ + { + (xdc_Bits16)0x1709, /* left */ + (xdc_Bits16)0x170e, /* right */ + }, /* [1] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1717, /* right */ + }, /* [2] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x171e, /* right */ + }, /* [3] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1723, /* right */ + }, /* [4] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x172c, /* right */ + }, /* [5] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1732, /* right */ + }, /* [6] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1738, /* right */ + }, /* [7] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x173d, /* right */ + }, /* [8] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1741, /* right */ + }, /* [9] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1746, /* right */ + }, /* [10] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x174d, /* right */ + }, /* [11] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1756, /* right */ + }, /* [12] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x175e, /* right */ + }, /* [13] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x1765, /* right */ + }, /* [14] */ + { + (xdc_Bits16)0x8001, /* left */ + (xdc_Bits16)0x176c, /* right */ + }, /* [15] */ + { + (xdc_Bits16)0x1771, /* left */ + (xdc_Bits16)0x1775, /* right */ + }, /* [16] */ + { + (xdc_Bits16)0x8010, /* left */ + (xdc_Bits16)0x177e, /* right */ + }, /* [17] */ + { + (xdc_Bits16)0x8011, /* left */ + (xdc_Bits16)0x1783, /* right */ + }, /* [18] */ + { + (xdc_Bits16)0x8012, /* left */ + (xdc_Bits16)0x178d, /* right */ + }, /* [19] */ + { + (xdc_Bits16)0x8013, /* left */ + (xdc_Bits16)0x1793, /* right */ + }, /* [20] */ + { + (xdc_Bits16)0x8014, /* left */ + (xdc_Bits16)0x1797, /* right */ + }, /* [21] */ + { + (xdc_Bits16)0x1771, /* left */ + (xdc_Bits16)0x179c, /* right */ + }, /* [22] */ + { + (xdc_Bits16)0x8016, /* left */ + (xdc_Bits16)0x17a5, /* right */ + }, /* [23] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17aa, /* right */ + }, /* [24] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17b0, /* right */ + }, /* [25] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17b5, /* right */ + }, /* [26] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17c0, /* right */ + }, /* [27] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17c6, /* right */ + }, /* [28] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17d0, /* right */ + }, /* [29] */ + { + (xdc_Bits16)0x8017, /* left */ + (xdc_Bits16)0x17d4, /* right */ + }, /* [30] */ + { + (xdc_Bits16)0x8016, /* left */ + (xdc_Bits16)0x17d9, /* right */ + }, /* [31] */ + { + (xdc_Bits16)0x801f, /* left */ + (xdc_Bits16)0x17de, /* right */ + }, /* [32] */ + { + (xdc_Bits16)0x8016, /* left */ + (xdc_Bits16)0x17e2, /* right */ + }, /* [33] */ + { + (xdc_Bits16)0x8016, /* left */ + (xdc_Bits16)0x17e7, /* right */ + }, /* [34] */ + { + (xdc_Bits16)0x8022, /* left */ + (xdc_Bits16)0x177e, /* right */ + }, /* [35] */ + { + (xdc_Bits16)0x8023, /* left */ + (xdc_Bits16)0x17ef, /* right */ + }, /* [36] */ + { + (xdc_Bits16)0x8024, /* left */ + (xdc_Bits16)0x17de, /* right */ + }, /* [37] */ + { + (xdc_Bits16)0x8024, /* left */ + (xdc_Bits16)0x17f3, /* right */ + }, /* [38] */ + { + (xdc_Bits16)0x8024, /* left */ + (xdc_Bits16)0x1805, /* right */ + }, /* [39] */ + { + (xdc_Bits16)0x8016, /* left */ + (xdc_Bits16)0x1811, /* right */ + }, /* [40] */ + { + (xdc_Bits16)0x8028, /* left */ + (xdc_Bits16)0x1818, /* right */ + }, /* [41] */ + { + (xdc_Bits16)0x8028, /* left */ + (xdc_Bits16)0x1820, /* right */ + }, /* [42] */ + { + (xdc_Bits16)0x8016, /* left */ + (xdc_Bits16)0x182a, /* right */ + }, /* [43] */ + { + (xdc_Bits16)0x802b, /* left */ + (xdc_Bits16)0x1831, /* right */ + }, /* [44] */ + { + (xdc_Bits16)0x8023, /* left */ + (xdc_Bits16)0x1839, /* right */ + }, /* [45] */ + { + (xdc_Bits16)0x802d, /* left */ + (xdc_Bits16)0x183e, /* right */ + }, /* [46] */ +}; + +/* Module__diagsEnabled__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__diagsEnabled__C, ".const:xdc_runtime_Text_Module__diagsEnabled__C"); +__FAR__ const CT__xdc_runtime_Text_Module__diagsEnabled xdc_runtime_Text_Module__diagsEnabled__C = (xdc_Bits32)0x10; + +/* Module__diagsIncluded__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__diagsIncluded__C, ".const:xdc_runtime_Text_Module__diagsIncluded__C"); +__FAR__ const CT__xdc_runtime_Text_Module__diagsIncluded xdc_runtime_Text_Module__diagsIncluded__C = (xdc_Bits32)0x10; + +/* Module__diagsMask__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__diagsMask__C, ".const:xdc_runtime_Text_Module__diagsMask__C"); +__FAR__ const CT__xdc_runtime_Text_Module__diagsMask xdc_runtime_Text_Module__diagsMask__C = ((CT__xdc_runtime_Text_Module__diagsMask)0); + +/* Module__gateObj__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__gateObj__C, ".const:xdc_runtime_Text_Module__gateObj__C"); +__FAR__ const CT__xdc_runtime_Text_Module__gateObj xdc_runtime_Text_Module__gateObj__C = ((CT__xdc_runtime_Text_Module__gateObj)0); + +/* Module__gatePrms__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__gatePrms__C, ".const:xdc_runtime_Text_Module__gatePrms__C"); +__FAR__ const CT__xdc_runtime_Text_Module__gatePrms xdc_runtime_Text_Module__gatePrms__C = ((CT__xdc_runtime_Text_Module__gatePrms)0); + +/* Module__id__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__id__C, ".const:xdc_runtime_Text_Module__id__C"); +__FAR__ const CT__xdc_runtime_Text_Module__id xdc_runtime_Text_Module__id__C = (xdc_Bits16)0x800f; + +/* Module__loggerDefined__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerDefined__C, ".const:xdc_runtime_Text_Module__loggerDefined__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerDefined xdc_runtime_Text_Module__loggerDefined__C = 0; + +/* Module__loggerObj__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerObj__C, ".const:xdc_runtime_Text_Module__loggerObj__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerObj xdc_runtime_Text_Module__loggerObj__C = ((CT__xdc_runtime_Text_Module__loggerObj)0); + +/* Module__loggerFxn0__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerFxn0__C, ".const:xdc_runtime_Text_Module__loggerFxn0__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerFxn0 xdc_runtime_Text_Module__loggerFxn0__C = ((CT__xdc_runtime_Text_Module__loggerFxn0)0); + +/* Module__loggerFxn1__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerFxn1__C, ".const:xdc_runtime_Text_Module__loggerFxn1__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerFxn1 xdc_runtime_Text_Module__loggerFxn1__C = ((CT__xdc_runtime_Text_Module__loggerFxn1)0); + +/* Module__loggerFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerFxn2__C, ".const:xdc_runtime_Text_Module__loggerFxn2__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerFxn2 xdc_runtime_Text_Module__loggerFxn2__C = ((CT__xdc_runtime_Text_Module__loggerFxn2)0); + +/* Module__loggerFxn4__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerFxn4__C, ".const:xdc_runtime_Text_Module__loggerFxn4__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerFxn4 xdc_runtime_Text_Module__loggerFxn4__C = ((CT__xdc_runtime_Text_Module__loggerFxn4)0); + +/* Module__loggerFxn8__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__loggerFxn8__C, ".const:xdc_runtime_Text_Module__loggerFxn8__C"); +__FAR__ const CT__xdc_runtime_Text_Module__loggerFxn8 xdc_runtime_Text_Module__loggerFxn8__C = ((CT__xdc_runtime_Text_Module__loggerFxn8)0); + +/* Module__startupDoneFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Module__startupDoneFxn__C, ".const:xdc_runtime_Text_Module__startupDoneFxn__C"); +__FAR__ const CT__xdc_runtime_Text_Module__startupDoneFxn xdc_runtime_Text_Module__startupDoneFxn__C = ((CT__xdc_runtime_Text_Module__startupDoneFxn)0); + +/* Object__count__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Object__count__C, ".const:xdc_runtime_Text_Object__count__C"); +__FAR__ const CT__xdc_runtime_Text_Object__count xdc_runtime_Text_Object__count__C = 0; + +/* Object__heap__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Object__heap__C, ".const:xdc_runtime_Text_Object__heap__C"); +__FAR__ const CT__xdc_runtime_Text_Object__heap xdc_runtime_Text_Object__heap__C = 0; + +/* Object__sizeof__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Object__sizeof__C, ".const:xdc_runtime_Text_Object__sizeof__C"); +__FAR__ const CT__xdc_runtime_Text_Object__sizeof xdc_runtime_Text_Object__sizeof__C = 0; + +/* Object__table__C */ +#pragma DATA_SECTION(xdc_runtime_Text_Object__table__C, ".const:xdc_runtime_Text_Object__table__C"); +__FAR__ const CT__xdc_runtime_Text_Object__table xdc_runtime_Text_Object__table__C = 0; + +/* nameUnknown__C */ +#pragma DATA_SECTION(xdc_runtime_Text_nameUnknown__C, ".const:xdc_runtime_Text_nameUnknown__C"); +__FAR__ const CT__xdc_runtime_Text_nameUnknown xdc_runtime_Text_nameUnknown__C = "{unknown-instance-name}"; + +/* nameEmpty__C */ +#pragma DATA_SECTION(xdc_runtime_Text_nameEmpty__C, ".const:xdc_runtime_Text_nameEmpty__C"); +__FAR__ const CT__xdc_runtime_Text_nameEmpty xdc_runtime_Text_nameEmpty__C = "{empty-instance-name}"; + +/* nameStatic__C */ +#pragma DATA_SECTION(xdc_runtime_Text_nameStatic__C, ".const:xdc_runtime_Text_nameStatic__C"); +__FAR__ const CT__xdc_runtime_Text_nameStatic xdc_runtime_Text_nameStatic__C = "{static-instance-name}"; + +/* isLoaded__C */ +#pragma DATA_SECTION(xdc_runtime_Text_isLoaded__C, ".const:xdc_runtime_Text_isLoaded__C"); +__FAR__ const CT__xdc_runtime_Text_isLoaded xdc_runtime_Text_isLoaded__C = 1; + +/* charTab__C */ +#pragma DATA_SECTION(xdc_runtime_Text_charTab__C, ".const:xdc_runtime_Text_charTab__C"); +__FAR__ const CT__xdc_runtime_Text_charTab xdc_runtime_Text_charTab__C = ((CT__xdc_runtime_Text_charTab)xdc_runtime_Text_charTab__A); + +/* nodeTab__C */ +#pragma DATA_SECTION(xdc_runtime_Text_nodeTab__C, ".const:xdc_runtime_Text_nodeTab__C"); +__FAR__ const CT__xdc_runtime_Text_nodeTab xdc_runtime_Text_nodeTab__C = ((CT__xdc_runtime_Text_nodeTab)xdc_runtime_Text_nodeTab__A); + +/* charCnt__C */ +#pragma DATA_SECTION(xdc_runtime_Text_charCnt__C, ".const:xdc_runtime_Text_charCnt__C"); +__FAR__ const CT__xdc_runtime_Text_charCnt xdc_runtime_Text_charCnt__C = (xdc_Int16)0x186d; + +/* nodeCnt__C */ +#pragma DATA_SECTION(xdc_runtime_Text_nodeCnt__C, ".const:xdc_runtime_Text_nodeCnt__C"); +__FAR__ const CT__xdc_runtime_Text_nodeCnt xdc_runtime_Text_nodeCnt__C = (xdc_Int16)0x2f; + +/* unnamedModsLastId__C */ +#pragma DATA_SECTION(xdc_runtime_Text_unnamedModsLastId__C, ".const:xdc_runtime_Text_unnamedModsLastId__C"); +__FAR__ const CT__xdc_runtime_Text_unnamedModsLastId xdc_runtime_Text_unnamedModsLastId__C = (xdc_UInt16)0x4000; + +/* registryModsLastId__C */ +#pragma DATA_SECTION(xdc_runtime_Text_registryModsLastId__C, ".const:xdc_runtime_Text_registryModsLastId__C"); +__FAR__ const CT__xdc_runtime_Text_registryModsLastId xdc_runtime_Text_registryModsLastId__C = (xdc_UInt16)0x7fff; + +/* visitRopeFxn__C */ +#pragma DATA_SECTION(xdc_runtime_Text_visitRopeFxn__C, ".const:xdc_runtime_Text_visitRopeFxn__C"); +__FAR__ const CT__xdc_runtime_Text_visitRopeFxn xdc_runtime_Text_visitRopeFxn__C = ((CT__xdc_runtime_Text_visitRopeFxn)((xdc_Fxn)xdc_runtime_Text_visitRope__I)); + +/* visitRopeFxn2__C */ +#pragma DATA_SECTION(xdc_runtime_Text_visitRopeFxn2__C, ".const:xdc_runtime_Text_visitRopeFxn2__C"); +__FAR__ const CT__xdc_runtime_Text_visitRopeFxn2 xdc_runtime_Text_visitRopeFxn2__C = ((CT__xdc_runtime_Text_visitRopeFxn2)((xdc_Fxn)xdc_runtime_Text_visitRope2__I)); + + +/* + * ======== xdc.runtime.System FUNCTION STUBS ======== + */ + +/* printf_va__E */ +xdc_Int xdc_runtime_System_printf_va__E( xdc_CString fmt, va_list __va ) +{ + return xdc_runtime_System_printf_va__F(fmt, __va); +} + +/* printf__E */ +xdc_Int xdc_runtime_System_printf__E( xdc_CString fmt, ... ) +{ + xdc_Int __ret; + + va_list __va; va_start(__va, fmt); + __ret = xdc_runtime_System_printf_va__F(fmt, __va); + + va_end(__va); + return __ret; +} + +/* aprintf_va__E */ +xdc_Int xdc_runtime_System_aprintf_va__E( xdc_CString fmt, va_list __va ) +{ + return xdc_runtime_System_aprintf_va__F(fmt, __va); +} + +/* aprintf__E */ +xdc_Int xdc_runtime_System_aprintf__E( xdc_CString fmt, ... ) +{ + xdc_Int __ret; + + va_list __va; va_start(__va, fmt); + __ret = xdc_runtime_System_aprintf_va__F(fmt, __va); + + va_end(__va); + return __ret; +} + +/* sprintf_va__E */ +xdc_Int xdc_runtime_System_sprintf_va__E( xdc_Char buf[], xdc_CString fmt, va_list __va ) +{ + return xdc_runtime_System_sprintf_va__F(buf, fmt, __va); +} + +/* sprintf__E */ +xdc_Int xdc_runtime_System_sprintf__E( xdc_Char buf[], xdc_CString fmt, ... ) +{ + xdc_Int __ret; + + va_list __va; va_start(__va, fmt); + __ret = xdc_runtime_System_sprintf_va__F(buf, fmt, __va); + + va_end(__va); + return __ret; +} + +/* asprintf_va__E */ +xdc_Int xdc_runtime_System_asprintf_va__E( xdc_Char buf[], xdc_CString fmt, va_list __va ) +{ + return xdc_runtime_System_asprintf_va__F(buf, fmt, __va); +} + +/* asprintf__E */ +xdc_Int xdc_runtime_System_asprintf__E( xdc_Char buf[], xdc_CString fmt, ... ) +{ + xdc_Int __ret; + + va_list __va; va_start(__va, fmt); + __ret = xdc_runtime_System_asprintf_va__F(buf, fmt, __va); + + va_end(__va); + return __ret; +} + +/* snprintf_va__E */ +xdc_Int xdc_runtime_System_snprintf_va__E( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, va_list __va ) +{ + return xdc_runtime_System_snprintf_va__F(buf, n, fmt, __va); +} + +/* snprintf__E */ +xdc_Int xdc_runtime_System_snprintf__E( xdc_Char buf[], xdc_SizeT n, xdc_CString fmt, ... ) +{ + xdc_Int __ret; + + va_list __va; va_start(__va, fmt); + __ret = xdc_runtime_System_snprintf_va__F(buf, n, fmt, __va); + + va_end(__va); + return __ret; +} + + +/* + * ======== ti.sysbios.BIOS_RtsGateProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.gates.GateMutex */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_BIOS_RtsGateProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_gates_GateMutex_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_BIOS_RtsGateProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_BIOS_RtsGateProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_gates_GateMutex_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_gates_GateMutex___ParamsPtr)__paramsPtr, sizeof(xdc_runtime_IGateProvider_Params), __eb); +} + +/* create */ +ti_sysbios_BIOS_RtsGateProxy_Handle ti_sysbios_BIOS_RtsGateProxy_create( const ti_sysbios_BIOS_RtsGateProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (ti_sysbios_BIOS_RtsGateProxy_Handle)ti_sysbios_BIOS_RtsGateProxy_Object__create__S(0, 0, 0, (const xdc_UChar*)__prms, sizeof(ti_sysbios_BIOS_RtsGateProxy_Params), __eb); +} + +/* Object__delete__S */ +void ti_sysbios_BIOS_RtsGateProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_gates_GateMutex_Object__delete__S(instp); +} + +/* delete */ +void ti_sysbios_BIOS_RtsGateProxy_delete(ti_sysbios_BIOS_RtsGateProxy_Handle *instp) +{ + ti_sysbios_BIOS_RtsGateProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void ti_sysbios_BIOS_RtsGateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_gates_GateMutex_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_BIOS_RtsGateProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_gates_GateMutex_Handle__label__S(obj, lab); +} + +/* query__E */ +xdc_Bool ti_sysbios_BIOS_RtsGateProxy_query__E( xdc_Int qual ) +{ + return ti_sysbios_gates_GateMutex_query(qual); +} + +/* enter__E */ +xdc_IArg ti_sysbios_BIOS_RtsGateProxy_enter__E( ti_sysbios_BIOS_RtsGateProxy_Handle __inst ) +{ + return ti_sysbios_gates_GateMutex_enter((ti_sysbios_gates_GateMutex_Handle)__inst); +} + +/* leave__E */ +xdc_Void ti_sysbios_BIOS_RtsGateProxy_leave__E( ti_sysbios_BIOS_RtsGateProxy_Handle __inst, xdc_IArg key ) +{ + ti_sysbios_gates_GateMutex_leave((ti_sysbios_gates_GateMutex_Handle)__inst, key); +} + + +/* + * ======== ti.sysbios.hal.Hwi_HwiProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.family.arm.m3.Hwi */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_family_arm_m3_Hwi_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_hal_Hwi_HwiProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_family_arm_m3_Hwi_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_family_arm_m3_Hwi___ParamsPtr)__paramsPtr, sizeof(ti_sysbios_interfaces_IHwi_Params), __eb); +} + +/* create */ +ti_sysbios_hal_Hwi_HwiProxy_Handle ti_sysbios_hal_Hwi_HwiProxy_create( xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_HwiProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_hal_Hwi_HwiProxy_Args__create __args; + __args.intNum = intNum; + __args.hwiFxn = hwiFxn; + return (ti_sysbios_hal_Hwi_HwiProxy_Handle)ti_sysbios_hal_Hwi_HwiProxy_Object__create__S(0, 0, &__args, (const xdc_UChar*)__prms, sizeof(ti_sysbios_hal_Hwi_HwiProxy_Params), __eb); +} + +/* Object__delete__S */ +void ti_sysbios_hal_Hwi_HwiProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_family_arm_m3_Hwi_Object__delete__S(instp); +} + +/* delete */ +void ti_sysbios_hal_Hwi_HwiProxy_delete(ti_sysbios_hal_Hwi_HwiProxy_Handle *instp) +{ + ti_sysbios_hal_Hwi_HwiProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void ti_sysbios_hal_Hwi_HwiProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_family_arm_m3_Hwi_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_hal_Hwi_HwiProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_family_arm_m3_Hwi_Handle__label__S(obj, lab); +} + +/* getStackInfo__E */ +xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_getStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth ) +{ + return ti_sysbios_family_arm_m3_Hwi_getStackInfo(stkInfo, computeStackDepth); +} + +/* getCoreStackInfo__E */ +xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_getCoreStackInfo__E( ti_sysbios_interfaces_IHwi_StackInfo *stkInfo, xdc_Bool computeStackDepth, xdc_UInt coreId ) +{ + return ti_sysbios_family_arm_m3_Hwi_getCoreStackInfo(stkInfo, computeStackDepth, coreId); +} + +/* startup__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_startup__E( void ) +{ + ti_sysbios_family_arm_m3_Hwi_startup(); +} + +/* disable__E */ +xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_disable__E( void ) +{ + return ti_sysbios_family_arm_m3_Hwi_disable(); +} + +/* enable__E */ +xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_enable__E( void ) +{ + return ti_sysbios_family_arm_m3_Hwi_enable(); +} + +/* restore__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_restore__E( xdc_UInt key ) +{ + ti_sysbios_family_arm_m3_Hwi_restore(key); +} + +/* switchFromBootStack__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_switchFromBootStack__E( void ) +{ + ti_sysbios_family_arm_m3_Hwi_switchFromBootStack(); +} + +/* post__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_post__E( xdc_UInt intNum ) +{ + ti_sysbios_family_arm_m3_Hwi_post(intNum); +} + +/* getTaskSP__E */ +xdc_Char *ti_sysbios_hal_Hwi_HwiProxy_getTaskSP__E( void ) +{ + return ti_sysbios_family_arm_m3_Hwi_getTaskSP(); +} + +/* disableInterrupt__E */ +xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_disableInterrupt__E( xdc_UInt intNum ) +{ + return ti_sysbios_family_arm_m3_Hwi_disableInterrupt(intNum); +} + +/* enableInterrupt__E */ +xdc_UInt ti_sysbios_hal_Hwi_HwiProxy_enableInterrupt__E( xdc_UInt intNum ) +{ + return ti_sysbios_family_arm_m3_Hwi_enableInterrupt(intNum); +} + +/* restoreInterrupt__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_restoreInterrupt__E( xdc_UInt intNum, xdc_UInt key ) +{ + ti_sysbios_family_arm_m3_Hwi_restoreInterrupt(intNum, key); +} + +/* clearInterrupt__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_clearInterrupt__E( xdc_UInt intNum ) +{ + ti_sysbios_family_arm_m3_Hwi_clearInterrupt(intNum); +} + +/* getFunc__E */ +ti_sysbios_interfaces_IHwi_FuncPtr ti_sysbios_hal_Hwi_HwiProxy_getFunc__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, xdc_UArg *arg ) +{ + return ti_sysbios_family_arm_m3_Hwi_getFunc((ti_sysbios_family_arm_m3_Hwi_Handle)__inst, arg); +} + +/* setFunc__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_setFunc__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, ti_sysbios_interfaces_IHwi_FuncPtr fxn, xdc_UArg arg ) +{ + ti_sysbios_family_arm_m3_Hwi_setFunc((ti_sysbios_family_arm_m3_Hwi_Handle)__inst, fxn, arg); +} + +/* getHookContext__E */ +xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_getHookContext__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, xdc_Int id ) +{ + return ti_sysbios_family_arm_m3_Hwi_getHookContext((ti_sysbios_family_arm_m3_Hwi_Handle)__inst, id); +} + +/* setHookContext__E */ +xdc_Void ti_sysbios_hal_Hwi_HwiProxy_setHookContext__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst, xdc_Int id, xdc_Ptr hookContext ) +{ + ti_sysbios_family_arm_m3_Hwi_setHookContext((ti_sysbios_family_arm_m3_Hwi_Handle)__inst, id, hookContext); +} + +/* getIrp__E */ +ti_sysbios_interfaces_IHwi_Irp ti_sysbios_hal_Hwi_HwiProxy_getIrp__E( ti_sysbios_hal_Hwi_HwiProxy_Handle __inst ) +{ + return ti_sysbios_family_arm_m3_Hwi_getIrp((ti_sysbios_family_arm_m3_Hwi_Handle)__inst); +} + + +/* + * ======== ti.sysbios.heaps.HeapMem_Module_GateProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.gates.GateMutex */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_gates_GateMutex_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_heaps_HeapMem_Module_GateProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_gates_GateMutex_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_gates_GateMutex___ParamsPtr)__paramsPtr, sizeof(xdc_runtime_IGateProvider_Params), __eb); +} + +/* create */ +ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle ti_sysbios_heaps_HeapMem_Module_GateProxy_create( const ti_sysbios_heaps_HeapMem_Module_GateProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle)ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__create__S(0, 0, 0, (const xdc_UChar*)__prms, sizeof(ti_sysbios_heaps_HeapMem_Module_GateProxy_Params), __eb); +} + +/* Object__delete__S */ +void ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_gates_GateMutex_Object__delete__S(instp); +} + +/* delete */ +void ti_sysbios_heaps_HeapMem_Module_GateProxy_delete(ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle *instp) +{ + ti_sysbios_heaps_HeapMem_Module_GateProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void ti_sysbios_heaps_HeapMem_Module_GateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_gates_GateMutex_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_gates_GateMutex_Handle__label__S(obj, lab); +} + +/* query__E */ +xdc_Bool ti_sysbios_heaps_HeapMem_Module_GateProxy_query__E( xdc_Int qual ) +{ + return ti_sysbios_gates_GateMutex_query(qual); +} + +/* enter__E */ +xdc_IArg ti_sysbios_heaps_HeapMem_Module_GateProxy_enter__E( ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle __inst ) +{ + return ti_sysbios_gates_GateMutex_enter((ti_sysbios_gates_GateMutex_Handle)__inst); +} + +/* leave__E */ +xdc_Void ti_sysbios_heaps_HeapMem_Module_GateProxy_leave__E( ti_sysbios_heaps_HeapMem_Module_GateProxy_Handle __inst, xdc_IArg key ) +{ + ti_sysbios_gates_GateMutex_leave((ti_sysbios_gates_GateMutex_Handle)__inst, key); +} + + +/* + * ======== ti.sysbios.knl.Clock_TimerProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.family.arm.lm4.Timer */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Clock_TimerProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_family_arm_lm4_Timer_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_knl_Clock_TimerProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_knl_Clock_TimerProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_family_arm_lm4_Timer_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_family_arm_lm4_Timer___ParamsPtr)__paramsPtr, sizeof(ti_sysbios_interfaces_ITimer_Params), __eb); +} + +/* create */ +ti_sysbios_knl_Clock_TimerProxy_Handle ti_sysbios_knl_Clock_TimerProxy_create( xdc_Int id, ti_sysbios_interfaces_ITimer_FuncPtr tickFxn, const ti_sysbios_knl_Clock_TimerProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Clock_TimerProxy_Args__create __args; + __args.id = id; + __args.tickFxn = tickFxn; + return (ti_sysbios_knl_Clock_TimerProxy_Handle)ti_sysbios_knl_Clock_TimerProxy_Object__create__S(0, 0, &__args, (const xdc_UChar*)__prms, sizeof(ti_sysbios_knl_Clock_TimerProxy_Params), __eb); +} + +/* Object__delete__S */ +void ti_sysbios_knl_Clock_TimerProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_family_arm_lm4_Timer_Object__delete__S(instp); +} + +/* delete */ +void ti_sysbios_knl_Clock_TimerProxy_delete(ti_sysbios_knl_Clock_TimerProxy_Handle *instp) +{ + ti_sysbios_knl_Clock_TimerProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void ti_sysbios_knl_Clock_TimerProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_family_arm_lm4_Timer_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_knl_Clock_TimerProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_family_arm_lm4_Timer_Handle__label__S(obj, lab); +} + +/* getNumTimers__E */ +xdc_UInt ti_sysbios_knl_Clock_TimerProxy_getNumTimers__E( void ) +{ + return ti_sysbios_family_arm_lm4_Timer_getNumTimers(); +} + +/* getStatus__E */ +ti_sysbios_interfaces_ITimer_Status ti_sysbios_knl_Clock_TimerProxy_getStatus__E( xdc_UInt id ) +{ + return ti_sysbios_family_arm_lm4_Timer_getStatus(id); +} + +/* startup__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_startup__E( void ) +{ + ti_sysbios_family_arm_lm4_Timer_startup(); +} + +/* getMaxTicks__E */ +xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getMaxTicks__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ) +{ + return ti_sysbios_family_arm_lm4_Timer_getMaxTicks((ti_sysbios_family_arm_lm4_Timer_Handle)__inst); +} + +/* setNextTick__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_setNextTick__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 ticks ) +{ + ti_sysbios_family_arm_lm4_Timer_setNextTick((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, ticks); +} + +/* start__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_start__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ) +{ + ti_sysbios_family_arm_lm4_Timer_start((ti_sysbios_family_arm_lm4_Timer_Handle)__inst); +} + +/* stop__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_stop__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ) +{ + ti_sysbios_family_arm_lm4_Timer_stop((ti_sysbios_family_arm_lm4_Timer_Handle)__inst); +} + +/* setPeriod__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_setPeriod__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 period ) +{ + ti_sysbios_family_arm_lm4_Timer_setPeriod((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, period); +} + +/* setPeriodMicroSecs__E */ +xdc_Bool ti_sysbios_knl_Clock_TimerProxy_setPeriodMicroSecs__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 microsecs ) +{ + return ti_sysbios_family_arm_lm4_Timer_setPeriodMicroSecs((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, microsecs); +} + +/* getPeriod__E */ +xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getPeriod__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ) +{ + return ti_sysbios_family_arm_lm4_Timer_getPeriod((ti_sysbios_family_arm_lm4_Timer_Handle)__inst); +} + +/* getCount__E */ +xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getCount__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ) +{ + return ti_sysbios_family_arm_lm4_Timer_getCount((ti_sysbios_family_arm_lm4_Timer_Handle)__inst); +} + +/* getFreq__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_getFreq__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_runtime_Types_FreqHz *freq ) +{ + ti_sysbios_family_arm_lm4_Timer_getFreq((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, freq); +} + +/* getFunc__E */ +ti_sysbios_interfaces_ITimer_FuncPtr ti_sysbios_knl_Clock_TimerProxy_getFunc__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UArg *arg ) +{ + return ti_sysbios_family_arm_lm4_Timer_getFunc((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, arg); +} + +/* setFunc__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_setFunc__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, ti_sysbios_interfaces_ITimer_FuncPtr fxn, xdc_UArg arg ) +{ + ti_sysbios_family_arm_lm4_Timer_setFunc((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, fxn, arg); +} + +/* trigger__E */ +xdc_Void ti_sysbios_knl_Clock_TimerProxy_trigger__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 cycles ) +{ + ti_sysbios_family_arm_lm4_Timer_trigger((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, cycles); +} + +/* getExpiredCounts__E */ +xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getExpiredCounts__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst ) +{ + return ti_sysbios_family_arm_lm4_Timer_getExpiredCounts((ti_sysbios_family_arm_lm4_Timer_Handle)__inst); +} + +/* getExpiredTicks__E */ +xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getExpiredTicks__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_UInt32 tickPeriod ) +{ + return ti_sysbios_family_arm_lm4_Timer_getExpiredTicks((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, tickPeriod); +} + +/* getCurrentTick__E */ +xdc_UInt32 ti_sysbios_knl_Clock_TimerProxy_getCurrentTick__E( ti_sysbios_knl_Clock_TimerProxy_Handle __inst, xdc_Bool save ) +{ + return ti_sysbios_family_arm_lm4_Timer_getCurrentTick((ti_sysbios_family_arm_lm4_Timer_Handle)__inst, save); +} + + +/* + * ======== ti.sysbios.knl.Intrinsics_SupportProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.family.arm.m3.IntrinsicsSupport */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Intrinsics_SupportProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDone__S(); +} + +/* maxbit__E */ +xdc_UInt ti_sysbios_knl_Intrinsics_SupportProxy_maxbit__E( xdc_UInt bits ) +{ + return ti_sysbios_family_arm_m3_IntrinsicsSupport_maxbit(bits); +} + + +/* + * ======== ti.sysbios.knl.Task_SupportProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.family.arm.m3.TaskSupport */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Task_SupportProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_family_arm_m3_TaskSupport_Module__startupDone__S(); +} + +/* start__E */ +xdc_Ptr ti_sysbios_knl_Task_SupportProxy_start__E( xdc_Ptr curTask, ti_sysbios_interfaces_ITaskSupport_FuncPtr enter, ti_sysbios_interfaces_ITaskSupport_FuncPtr exit, xdc_runtime_Error_Block *eb ) +{ + return ti_sysbios_family_arm_m3_TaskSupport_start(curTask, enter, exit, eb); +} + +/* swap__E */ +xdc_Void ti_sysbios_knl_Task_SupportProxy_swap__E( xdc_Ptr *oldtskContext, xdc_Ptr *newtskContext ) +{ + ti_sysbios_family_arm_m3_TaskSupport_swap(oldtskContext, newtskContext); +} + +/* checkStack__E */ +xdc_Bool ti_sysbios_knl_Task_SupportProxy_checkStack__E( xdc_Char *stack, xdc_SizeT size ) +{ + return ti_sysbios_family_arm_m3_TaskSupport_checkStack(stack, size); +} + +/* stackUsed__E */ +xdc_SizeT ti_sysbios_knl_Task_SupportProxy_stackUsed__E( xdc_Char *stack, xdc_SizeT size ) +{ + return ti_sysbios_family_arm_m3_TaskSupport_stackUsed(stack, size); +} + +/* getStackAlignment__E */ +xdc_UInt ti_sysbios_knl_Task_SupportProxy_getStackAlignment__E( void ) +{ + return ti_sysbios_family_arm_m3_TaskSupport_getStackAlignment(); +} + +/* getDefaultStackSize__E */ +xdc_SizeT ti_sysbios_knl_Task_SupportProxy_getDefaultStackSize__E( void ) +{ + return ti_sysbios_family_arm_m3_TaskSupport_getDefaultStackSize(); +} + + +/* + * ======== xdc.runtime.Main_Module_GateProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.gates.GateHwi */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Main_Module_GateProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_gates_GateHwi_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr xdc_runtime_Main_Module_GateProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const xdc_runtime_Main_Module_GateProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_gates_GateHwi_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_gates_GateHwi___ParamsPtr)__paramsPtr, sizeof(xdc_runtime_IGateProvider_Params), __eb); +} + +/* create */ +xdc_runtime_Main_Module_GateProxy_Handle xdc_runtime_Main_Module_GateProxy_create( const xdc_runtime_Main_Module_GateProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (xdc_runtime_Main_Module_GateProxy_Handle)xdc_runtime_Main_Module_GateProxy_Object__create__S(0, 0, 0, (const xdc_UChar*)__prms, sizeof(xdc_runtime_Main_Module_GateProxy_Params), __eb); +} + +/* Object__delete__S */ +void xdc_runtime_Main_Module_GateProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_gates_GateHwi_Object__delete__S(instp); +} + +/* delete */ +void xdc_runtime_Main_Module_GateProxy_delete(xdc_runtime_Main_Module_GateProxy_Handle *instp) +{ + xdc_runtime_Main_Module_GateProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void xdc_runtime_Main_Module_GateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_gates_GateHwi_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *xdc_runtime_Main_Module_GateProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_gates_GateHwi_Handle__label__S(obj, lab); +} + +/* query__E */ +xdc_Bool xdc_runtime_Main_Module_GateProxy_query__E( xdc_Int qual ) +{ + return ti_sysbios_gates_GateHwi_query(qual); +} + +/* enter__E */ +xdc_IArg xdc_runtime_Main_Module_GateProxy_enter__E( xdc_runtime_Main_Module_GateProxy_Handle __inst ) +{ + return ti_sysbios_gates_GateHwi_enter((ti_sysbios_gates_GateHwi_Handle)__inst); +} + +/* leave__E */ +xdc_Void xdc_runtime_Main_Module_GateProxy_leave__E( xdc_runtime_Main_Module_GateProxy_Handle __inst, xdc_IArg key ) +{ + ti_sysbios_gates_GateHwi_leave((ti_sysbios_gates_GateHwi_Handle)__inst, key); +} + + +/* + * ======== xdc.runtime.Memory_HeapProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.heaps.HeapMem */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Memory_HeapProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_heaps_HeapMem_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr xdc_runtime_Memory_HeapProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const xdc_runtime_Memory_HeapProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_heaps_HeapMem_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_heaps_HeapMem___ParamsPtr)__paramsPtr, sizeof(xdc_runtime_IHeap_Params), __eb); +} + +/* create */ +xdc_runtime_Memory_HeapProxy_Handle xdc_runtime_Memory_HeapProxy_create( const xdc_runtime_Memory_HeapProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (xdc_runtime_Memory_HeapProxy_Handle)xdc_runtime_Memory_HeapProxy_Object__create__S(0, 0, 0, (const xdc_UChar*)__prms, sizeof(xdc_runtime_Memory_HeapProxy_Params), __eb); +} + +/* Object__delete__S */ +void xdc_runtime_Memory_HeapProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_heaps_HeapMem_Object__delete__S(instp); +} + +/* delete */ +void xdc_runtime_Memory_HeapProxy_delete(xdc_runtime_Memory_HeapProxy_Handle *instp) +{ + xdc_runtime_Memory_HeapProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void xdc_runtime_Memory_HeapProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_heaps_HeapMem_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *xdc_runtime_Memory_HeapProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_heaps_HeapMem_Handle__label__S(obj, lab); +} + +/* alloc__E */ +xdc_Ptr xdc_runtime_Memory_HeapProxy_alloc__E( xdc_runtime_Memory_HeapProxy_Handle __inst, xdc_SizeT size, xdc_SizeT align, xdc_runtime_Error_Block *eb ) +{ + return xdc_runtime_IHeap_alloc((xdc_runtime_IHeap_Handle)__inst, size, align, eb); +} + +/* free__E */ +xdc_Void xdc_runtime_Memory_HeapProxy_free__E( xdc_runtime_Memory_HeapProxy_Handle __inst, xdc_Ptr block, xdc_SizeT size ) +{ + xdc_runtime_IHeap_free((xdc_runtime_IHeap_Handle)__inst, block, size); +} + +/* isBlocking__E */ +xdc_Bool xdc_runtime_Memory_HeapProxy_isBlocking__E( xdc_runtime_Memory_HeapProxy_Handle __inst ) +{ + return xdc_runtime_IHeap_isBlocking((xdc_runtime_IHeap_Handle)__inst); +} + +/* getStats__E */ +xdc_Void xdc_runtime_Memory_HeapProxy_getStats__E( xdc_runtime_Memory_HeapProxy_Handle __inst, xdc_runtime_Memory_Stats *stats ) +{ + xdc_runtime_IHeap_getStats((xdc_runtime_IHeap_Handle)__inst, stats); +} + + +/* + * ======== xdc.runtime.System_Module_GateProxy PROXY BODY ======== + */ + +/* DELEGATES TO ti.sysbios.gates.GateHwi */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_System_Module_GateProxy_Module__startupDone__S( void ) +{ + return ti_sysbios_gates_GateHwi_Module__startupDone__S(); +} + +/* Object__create__S */ +xdc_Ptr xdc_runtime_System_Module_GateProxy_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const xdc_runtime_System_Module_GateProxy___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + return ti_sysbios_gates_GateHwi_Object__create__S(__obj, __osz, __aa, (const ti_sysbios_gates_GateHwi___ParamsPtr)__paramsPtr, sizeof(xdc_runtime_IGateProvider_Params), __eb); +} + +/* create */ +xdc_runtime_System_Module_GateProxy_Handle xdc_runtime_System_Module_GateProxy_create( const xdc_runtime_System_Module_GateProxy_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (xdc_runtime_System_Module_GateProxy_Handle)xdc_runtime_System_Module_GateProxy_Object__create__S(0, 0, 0, (const xdc_UChar*)__prms, sizeof(xdc_runtime_System_Module_GateProxy_Params), __eb); +} + +/* Object__delete__S */ +void xdc_runtime_System_Module_GateProxy_Object__delete__S( xdc_Ptr instp ) +{ + ti_sysbios_gates_GateHwi_Object__delete__S(instp); +} + +/* delete */ +void xdc_runtime_System_Module_GateProxy_delete(xdc_runtime_System_Module_GateProxy_Handle *instp) +{ + xdc_runtime_System_Module_GateProxy_Object__delete__S(instp); +} + +/* Params__init__S */ +void xdc_runtime_System_Module_GateProxy_Params__init__S( xdc_Ptr dst, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + ti_sysbios_gates_GateHwi_Params__init__S(dst, src, psz, isz); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *xdc_runtime_System_Module_GateProxy_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + return ti_sysbios_gates_GateHwi_Handle__label__S(obj, lab); +} + +/* query__E */ +xdc_Bool xdc_runtime_System_Module_GateProxy_query__E( xdc_Int qual ) +{ + return ti_sysbios_gates_GateHwi_query(qual); +} + +/* enter__E */ +xdc_IArg xdc_runtime_System_Module_GateProxy_enter__E( xdc_runtime_System_Module_GateProxy_Handle __inst ) +{ + return ti_sysbios_gates_GateHwi_enter((ti_sysbios_gates_GateHwi_Handle)__inst); +} + +/* leave__E */ +xdc_Void xdc_runtime_System_Module_GateProxy_leave__E( xdc_runtime_System_Module_GateProxy_Handle __inst, xdc_IArg key ) +{ + ti_sysbios_gates_GateHwi_leave((ti_sysbios_gates_GateHwi_Handle)__inst, key); +} + + +/* + * ======== xdc.runtime.System_SupportProxy PROXY BODY ======== + */ + +/* DELEGATES TO xdc.runtime.SysMin */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_System_SupportProxy_Module__startupDone__S( void ) +{ + return xdc_runtime_SysMin_Module__startupDone__S(); +} + +/* abort__E */ +xdc_Void xdc_runtime_System_SupportProxy_abort__E( xdc_CString str ) +{ + xdc_runtime_SysMin_abort(str); +} + +/* exit__E */ +xdc_Void xdc_runtime_System_SupportProxy_exit__E( xdc_Int stat ) +{ + xdc_runtime_SysMin_exit(stat); +} + +/* flush__E */ +xdc_Void xdc_runtime_System_SupportProxy_flush__E( void ) +{ + xdc_runtime_SysMin_flush(); +} + +/* putch__E */ +xdc_Void xdc_runtime_System_SupportProxy_putch__E( xdc_Char ch ) +{ + xdc_runtime_SysMin_putch(ch); +} + +/* ready__E */ +xdc_Bool xdc_runtime_System_SupportProxy_ready__E( void ) +{ + return xdc_runtime_SysMin_ready(); +} + + +/* + * ======== ti.sysbios.family.arm.lm4.Timer OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_family_arm_lm4_Timer_Object2__ s0; char c; } ti_sysbios_family_arm_lm4_Timer___S1; +#pragma DATA_SECTION(ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, ".const:ti_sysbios_family_arm_lm4_Timer_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_family_arm_lm4_Timer_Object__DESC__C = { + (xdc_CPtr)0, /* fxnTab */ + &ti_sysbios_family_arm_lm4_Timer_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_family_arm_lm4_Timer___S1) - sizeof(ti_sysbios_family_arm_lm4_Timer_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_family_arm_lm4_Timer_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_family_arm_lm4_Timer_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_family_arm_lm4_Timer_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.family.arm.m3.Hwi OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_family_arm_m3_Hwi_Object2__ s0; char c; } ti_sysbios_family_arm_m3_Hwi___S1; +#pragma DATA_SECTION(ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, ".const:ti_sysbios_family_arm_m3_Hwi_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_family_arm_m3_Hwi_Object__DESC__C = { + (xdc_CPtr)0, /* fxnTab */ + &ti_sysbios_family_arm_m3_Hwi_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_family_arm_m3_Hwi___S1) - sizeof(ti_sysbios_family_arm_m3_Hwi_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_family_arm_m3_Hwi_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_family_arm_m3_Hwi_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_family_arm_m3_Hwi_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.gates.GateHwi OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_gates_GateHwi_Object2__ s0; char c; } ti_sysbios_gates_GateHwi___S1; +#pragma DATA_SECTION(ti_sysbios_gates_GateHwi_Object__DESC__C, ".const:ti_sysbios_gates_GateHwi_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_gates_GateHwi_Object__DESC__C = { + (xdc_CPtr)&ti_sysbios_gates_GateHwi_Module__FXNS__C, /* fxnTab */ + &ti_sysbios_gates_GateHwi_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_gates_GateHwi___S1) - sizeof(ti_sysbios_gates_GateHwi_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_gates_GateHwi_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_gates_GateHwi_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_gates_GateHwi_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.gates.GateMutex OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_gates_GateMutex_Object2__ s0; char c; } ti_sysbios_gates_GateMutex___S1; +#pragma DATA_SECTION(ti_sysbios_gates_GateMutex_Object__DESC__C, ".const:ti_sysbios_gates_GateMutex_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_gates_GateMutex_Object__DESC__C = { + (xdc_CPtr)&ti_sysbios_gates_GateMutex_Module__FXNS__C, /* fxnTab */ + &ti_sysbios_gates_GateMutex_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_gates_GateMutex___S1) - sizeof(ti_sysbios_gates_GateMutex_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_gates_GateMutex_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_gates_GateMutex_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_gates_GateMutex_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.hal.Hwi OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_hal_Hwi_Object2__ s0; char c; } ti_sysbios_hal_Hwi___S1; +#pragma DATA_SECTION(ti_sysbios_hal_Hwi_Object__DESC__C, ".const:ti_sysbios_hal_Hwi_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_hal_Hwi_Object__DESC__C = { + (xdc_CPtr)0, /* fxnTab */ + &ti_sysbios_hal_Hwi_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_hal_Hwi___S1) - sizeof(ti_sysbios_hal_Hwi_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_hal_Hwi_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_hal_Hwi_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_hal_Hwi_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.heaps.HeapMem OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_heaps_HeapMem_Object2__ s0; char c; } ti_sysbios_heaps_HeapMem___S1; +#pragma DATA_SECTION(ti_sysbios_heaps_HeapMem_Object__DESC__C, ".const:ti_sysbios_heaps_HeapMem_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_heaps_HeapMem_Object__DESC__C = { + (xdc_CPtr)&ti_sysbios_heaps_HeapMem_Module__FXNS__C, /* fxnTab */ + &ti_sysbios_heaps_HeapMem_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_heaps_HeapMem___S1) - sizeof(ti_sysbios_heaps_HeapMem_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_heaps_HeapMem_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_heaps_HeapMem_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_heaps_HeapMem_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.knl.Clock OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_knl_Clock_Object2__ s0; char c; } ti_sysbios_knl_Clock___S1; +#pragma DATA_SECTION(ti_sysbios_knl_Clock_Object__DESC__C, ".const:ti_sysbios_knl_Clock_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Clock_Object__DESC__C = { + (xdc_CPtr)-1, /* fxnTab */ + &ti_sysbios_knl_Clock_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_knl_Clock___S1) - sizeof(ti_sysbios_knl_Clock_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_knl_Clock_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_knl_Clock_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_knl_Clock_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.knl.Queue OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_knl_Queue_Object2__ s0; char c; } ti_sysbios_knl_Queue___S1; +#pragma DATA_SECTION(ti_sysbios_knl_Queue_Object__DESC__C, ".const:ti_sysbios_knl_Queue_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Queue_Object__DESC__C = { + (xdc_CPtr)-1, /* fxnTab */ + &ti_sysbios_knl_Queue_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_knl_Queue___S1) - sizeof(ti_sysbios_knl_Queue_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_knl_Queue_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_knl_Queue_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_knl_Queue_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.knl.Semaphore OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_knl_Semaphore_Object2__ s0; char c; } ti_sysbios_knl_Semaphore___S1; +#pragma DATA_SECTION(ti_sysbios_knl_Semaphore_Object__DESC__C, ".const:ti_sysbios_knl_Semaphore_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Semaphore_Object__DESC__C = { + (xdc_CPtr)-1, /* fxnTab */ + &ti_sysbios_knl_Semaphore_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_knl_Semaphore___S1) - sizeof(ti_sysbios_knl_Semaphore_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_knl_Semaphore_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_knl_Semaphore_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_knl_Semaphore_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.knl.Swi OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_knl_Swi_Object2__ s0; char c; } ti_sysbios_knl_Swi___S1; +#pragma DATA_SECTION(ti_sysbios_knl_Swi_Object__DESC__C, ".const:ti_sysbios_knl_Swi_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Swi_Object__DESC__C = { + (xdc_CPtr)-1, /* fxnTab */ + &ti_sysbios_knl_Swi_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_knl_Swi___S1) - sizeof(ti_sysbios_knl_Swi_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_knl_Swi_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_knl_Swi_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_knl_Swi_Params), /* prmsSize */ +}; + + +/* + * ======== ti.sysbios.knl.Task OBJECT DESCRIPTOR ======== + */ + +/* Object__DESC__C */ +typedef struct { ti_sysbios_knl_Task_Object2__ s0; char c; } ti_sysbios_knl_Task___S1; +#pragma DATA_SECTION(ti_sysbios_knl_Task_Object__DESC__C, ".const:ti_sysbios_knl_Task_Object__DESC__C"); +__FAR__ const xdc_runtime_Core_ObjDesc ti_sysbios_knl_Task_Object__DESC__C = { + (xdc_CPtr)-1, /* fxnTab */ + &ti_sysbios_knl_Task_Module__root__V.link, /* modLink */ + sizeof(ti_sysbios_knl_Task___S1) - sizeof(ti_sysbios_knl_Task_Object2__), /* objAlign */ + 0, /* objHeap */ + 0, /* objName */ + sizeof(ti_sysbios_knl_Task_Object2__), /* objSize */ + (xdc_CPtr)&ti_sysbios_knl_Task_Object__PARAMS__C, /* prmsInit */ + sizeof(ti_sysbios_knl_Task_Params), /* prmsSize */ +}; + + +/* + * ======== xdc.runtime.IHeap VIRTUAL FUNCTIONS ======== + */ + +/* create */ +xdc_runtime_IHeap_Handle xdc_runtime_IHeap_create( xdc_runtime_IHeap_Module __mod, const xdc_runtime_IHeap_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (xdc_runtime_IHeap_Handle) __mod->__sysp->__create(0, 0, 0, (const xdc_UChar*)__prms, sizeof (xdc_runtime_IHeap_Params), __eb); +} + +/* delete */ +void xdc_runtime_IHeap_delete( xdc_runtime_IHeap_Handle *instp ) +{ + (*instp)->__fxns->__sysp->__delete(instp); +} + + +/* + * ======== xdc.runtime.IGateProvider VIRTUAL FUNCTIONS ======== + */ + +/* create */ +xdc_runtime_IGateProvider_Handle xdc_runtime_IGateProvider_create( xdc_runtime_IGateProvider_Module __mod, const xdc_runtime_IGateProvider_Params *__prms, xdc_runtime_Error_Block *__eb ) +{ + return (xdc_runtime_IGateProvider_Handle) __mod->__sysp->__create(0, 0, 0, (const xdc_UChar*)__prms, sizeof (xdc_runtime_IGateProvider_Params), __eb); +} + +/* delete */ +void xdc_runtime_IGateProvider_delete( xdc_runtime_IGateProvider_Handle *instp ) +{ + (*instp)->__fxns->__sysp->__delete(instp); +} + + +/* + * ======== ti.catalog.arm.cortexm4.tiva.ce.Boot SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool ti_catalog_arm_cortexm4_tiva_ce_Boot_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== ti.sysbios.BIOS SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_BIOS_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== ti.sysbios.BIOS_RtsGateProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_BIOS_RtsGateProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_BIOS_RtsGateProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_BIOS_RtsGateProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_BIOS_RtsGateProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_BIOS_RtsGateProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_BIOS_RtsGateProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_BIOS_RtsGateProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_BIOS_RtsGateProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_BIOS_RtsGateProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_BIOS_RtsGateProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_BIOS_RtsGateProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_BIOS_RtsGateProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_BIOS_RtsGateProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_BIOS_RtsGateProxy_Module_GateProxy_query + +xdc_Bool ti_sysbios_BIOS_RtsGateProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr ti_sysbios_BIOS_RtsGateProxy_Proxy__delegate__S( void ) +{ + return (void *)&ti_sysbios_gates_GateMutex_Module__FXNS__C; +} + + + +/* + * ======== ti.sysbios.family.arm.lm4.Timer SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_family_arm_lm4_Timer_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_family_arm_lm4_Timer_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_family_arm_lm4_Timer_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_family_arm_lm4_Timer_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_family_arm_lm4_Timer_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_family_arm_lm4_Timer_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_family_arm_lm4_Timer_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_family_arm_lm4_Timer_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_family_arm_lm4_Timer_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_family_arm_lm4_Timer_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_family_arm_lm4_Timer_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_family_arm_lm4_Timer_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_family_arm_lm4_Timer_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_family_arm_lm4_Timer_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_family_arm_lm4_Timer_Module__startupDone__S( void ) +{ + return ti_sysbios_family_arm_lm4_Timer_Module__startupDone__F(); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_family_arm_lm4_Timer_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32814; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_family_arm_lm4_Timer_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_family_arm_lm4_Timer_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_family_arm_lm4_Timer_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_family_arm_lm4_Timer_Object__ *)oa) + i; + } + + if (ti_sysbios_family_arm_lm4_Timer_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_family_arm_lm4_Timer_Object__ *)ti_sysbios_family_arm_lm4_Timer_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_family_arm_lm4_Timer_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_family_arm_lm4_Timer_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_family_arm_lm4_Timer_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_family_arm_lm4_Timer_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_family_arm_lm4_Timer_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_family_arm_lm4_Timer_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_family_arm_lm4_Timer___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_family_arm_lm4_Timer_Args__create *__args = __aa; + ti_sysbios_family_arm_lm4_Timer_Params __prms; + ti_sysbios_family_arm_lm4_Timer_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_family_arm_lm4_Timer_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_family_arm_lm4_Timer_Instance_init__E(__newobj, __args->id, __args->tickFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_Instance_finalize__E, iStat, (xdc_Bool)(__obj != NULL)); + return NULL; + } + + return __newobj; +} + +/* create */ +ti_sysbios_family_arm_lm4_Timer_Handle ti_sysbios_family_arm_lm4_Timer_create( xdc_Int id, ti_sysbios_interfaces_ITimer_FuncPtr tickFxn, const ti_sysbios_family_arm_lm4_Timer_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_family_arm_lm4_Timer_Params __prms; + ti_sysbios_family_arm_lm4_Timer_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_family_arm_lm4_Timer_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_family_arm_lm4_Timer_Instance_init__E(__newobj, id, tickFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_Instance_finalize__E, iStat, 0); + return NULL; + } + + return __newobj; +} + +/* construct */ +void ti_sysbios_family_arm_lm4_Timer_construct(ti_sysbios_family_arm_lm4_Timer_Struct *__obj, xdc_Int id, ti_sysbios_interfaces_ITimer_FuncPtr tickFxn, const ti_sysbios_family_arm_lm4_Timer_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_family_arm_lm4_Timer_Params __prms; + int iStat; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_family_arm_lm4_Timer_Params), __eb); + /* module-specific initialization */ + iStat = ti_sysbios_family_arm_lm4_Timer_Instance_init__E((xdc_Ptr)__obj, id, tickFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, (xdc_Ptr)__obj, (xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_Instance_finalize__E, iStat, 1); + } + +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_family_arm_lm4_Timer_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_Instance_finalize__E, 0, TRUE); +} + +/* destruct */ +void ti_sysbios_family_arm_lm4_Timer_destruct(ti_sysbios_family_arm_lm4_Timer_Struct *obj) +{ + ti_sysbios_family_arm_lm4_Timer_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_family_arm_lm4_Timer_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_lm4_Timer_Object__DESC__C, *((ti_sysbios_family_arm_lm4_Timer_Object**)instp), (xdc_Fxn)ti_sysbios_family_arm_lm4_Timer_Instance_finalize__E, 0, FALSE); + *((ti_sysbios_family_arm_lm4_Timer_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_family_arm_lm4_Timer_delete(ti_sysbios_family_arm_lm4_Timer_Handle *instp) +{ + ti_sysbios_family_arm_lm4_Timer_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.family.arm.m3.Hwi SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_family_arm_m3_Hwi_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_family_arm_m3_Hwi_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_family_arm_m3_Hwi_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_family_arm_m3_Hwi_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_family_arm_m3_Hwi_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_family_arm_m3_Hwi_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_family_arm_m3_Hwi_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_family_arm_m3_Hwi_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_family_arm_m3_Hwi_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_family_arm_m3_Hwi_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_family_arm_m3_Hwi_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_family_arm_m3_Hwi_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_family_arm_m3_Hwi_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_family_arm_m3_Hwi_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_family_arm_m3_Hwi_Module__startupDone__S( void ) +{ + return ti_sysbios_family_arm_m3_Hwi_Module__startupDone__F(); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_family_arm_m3_Hwi_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32805; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_family_arm_m3_Hwi_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_family_arm_m3_Hwi_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_family_arm_m3_Hwi_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_family_arm_m3_Hwi_Object__ *)oa) + i; + } + + if (ti_sysbios_family_arm_m3_Hwi_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_family_arm_m3_Hwi_Object__ *)ti_sysbios_family_arm_m3_Hwi_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_family_arm_m3_Hwi_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_family_arm_m3_Hwi_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_family_arm_m3_Hwi_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_family_arm_m3_Hwi_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_family_arm_m3_Hwi_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_family_arm_m3_Hwi_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_family_arm_m3_Hwi___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_family_arm_m3_Hwi_Args__create *__args = __aa; + ti_sysbios_family_arm_m3_Hwi_Params __prms; + ti_sysbios_family_arm_m3_Hwi_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_family_arm_m3_Hwi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_family_arm_m3_Hwi_Instance_init__E(__newobj, __args->intNum, __args->hwiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_Instance_finalize__E, iStat, (xdc_Bool)(__obj != NULL)); + return NULL; + } + + return __newobj; +} + +/* create */ +ti_sysbios_family_arm_m3_Hwi_Handle ti_sysbios_family_arm_m3_Hwi_create( xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_family_arm_m3_Hwi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_family_arm_m3_Hwi_Params __prms; + ti_sysbios_family_arm_m3_Hwi_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_family_arm_m3_Hwi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_family_arm_m3_Hwi_Instance_init__E(__newobj, intNum, hwiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_Instance_finalize__E, iStat, 0); + return NULL; + } + + return __newobj; +} + +/* construct */ +void ti_sysbios_family_arm_m3_Hwi_construct(ti_sysbios_family_arm_m3_Hwi_Struct *__obj, xdc_Int intNum, ti_sysbios_interfaces_IHwi_FuncPtr hwiFxn, const ti_sysbios_family_arm_m3_Hwi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_family_arm_m3_Hwi_Params __prms; + int iStat; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_family_arm_m3_Hwi_Params), __eb); + /* module-specific initialization */ + iStat = ti_sysbios_family_arm_m3_Hwi_Instance_init__E((xdc_Ptr)__obj, intNum, hwiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, (xdc_Ptr)__obj, (xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_Instance_finalize__E, iStat, 1); + } + +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_family_arm_m3_Hwi_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_Instance_finalize__E, 0, TRUE); +} + +/* destruct */ +void ti_sysbios_family_arm_m3_Hwi_destruct(ti_sysbios_family_arm_m3_Hwi_Struct *obj) +{ + ti_sysbios_family_arm_m3_Hwi_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_family_arm_m3_Hwi_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_family_arm_m3_Hwi_Object__DESC__C, *((ti_sysbios_family_arm_m3_Hwi_Object**)instp), (xdc_Fxn)ti_sysbios_family_arm_m3_Hwi_Instance_finalize__E, 0, FALSE); + *((ti_sysbios_family_arm_m3_Hwi_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_family_arm_m3_Hwi_delete(ti_sysbios_family_arm_m3_Hwi_Handle *instp) +{ + ti_sysbios_family_arm_m3_Hwi_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.family.arm.m3.IntrinsicsSupport SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== ti.sysbios.family.arm.m3.TaskSupport SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_family_arm_m3_TaskSupport_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== ti.sysbios.gates.GateHwi SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_gates_GateHwi_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_gates_GateHwi_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_gates_GateHwi_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_gates_GateHwi_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_gates_GateHwi_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_gates_GateHwi_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_gates_GateHwi_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_gates_GateHwi_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_gates_GateHwi_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_gates_GateHwi_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_gates_GateHwi_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_gates_GateHwi_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_gates_GateHwi_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_gates_GateHwi_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_gates_GateHwi_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_gates_GateHwi_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_gates_GateHwi_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_gates_GateHwi_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_gates_GateHwi_Module__startupDone__S( void ) +{ + return 1; +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_gates_GateHwi_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32809; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_gates_GateHwi_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_gates_GateHwi_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_gates_GateHwi_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_gates_GateHwi_Object__ *)oa) + i; + } + + if (ti_sysbios_gates_GateHwi_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_gates_GateHwi_Object__ *)ti_sysbios_gates_GateHwi_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_gates_GateHwi_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_gates_GateHwi_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_gates_GateHwi_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_gates_GateHwi_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_gates_GateHwi_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_gates_GateHwi_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_gates_GateHwi___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_gates_GateHwi_Params __prms; + ti_sysbios_gates_GateHwi_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_gates_GateHwi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_gates_GateHwi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_gates_GateHwi_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* create */ +ti_sysbios_gates_GateHwi_Handle ti_sysbios_gates_GateHwi_create( const ti_sysbios_gates_GateHwi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_gates_GateHwi_Params __prms; + ti_sysbios_gates_GateHwi_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_gates_GateHwi_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_gates_GateHwi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_gates_GateHwi_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* construct */ +void ti_sysbios_gates_GateHwi_construct(ti_sysbios_gates_GateHwi_Struct *__obj, const ti_sysbios_gates_GateHwi_Params *__paramsPtr ) +{ + ti_sysbios_gates_GateHwi_Params __prms; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_gates_GateHwi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_gates_GateHwi_Params), NULL); + /* module-specific initialization */ + ti_sysbios_gates_GateHwi_Instance_init__E((xdc_Ptr)__obj, &__prms); +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_gates_GateHwi_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_gates_GateHwi_Object__DESC__C, obj, NULL, -1, TRUE); +} + +/* destruct */ +void ti_sysbios_gates_GateHwi_destruct(ti_sysbios_gates_GateHwi_Struct *obj) +{ + ti_sysbios_gates_GateHwi_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_gates_GateHwi_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_gates_GateHwi_Object__DESC__C, *((ti_sysbios_gates_GateHwi_Object**)instp), NULL, -1, FALSE); + *((ti_sysbios_gates_GateHwi_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_gates_GateHwi_delete(ti_sysbios_gates_GateHwi_Handle *instp) +{ + ti_sysbios_gates_GateHwi_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.gates.GateMutex SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_gates_GateMutex_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_gates_GateMutex_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_gates_GateMutex_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_gates_GateMutex_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_gates_GateMutex_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_gates_GateMutex_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_gates_GateMutex_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_gates_GateMutex_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_gates_GateMutex_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_gates_GateMutex_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_gates_GateMutex_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_gates_GateMutex_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_gates_GateMutex_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_gates_GateMutex_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_gates_GateMutex_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_gates_GateMutex_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_gates_GateMutex_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_gates_GateMutex_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_gates_GateMutex_Module__startupDone__S( void ) +{ + return 1; +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_gates_GateMutex_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32810; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_gates_GateMutex_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_gates_GateMutex_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_gates_GateMutex_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_gates_GateMutex_Object__ *)oa) + i; + } + + if (ti_sysbios_gates_GateMutex_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_gates_GateMutex_Object__ *)ti_sysbios_gates_GateMutex_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_gates_GateMutex_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_gates_GateMutex_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_gates_GateMutex_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_gates_GateMutex_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_gates_GateMutex_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_gates_GateMutex_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_gates_GateMutex___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_gates_GateMutex_Params __prms; + ti_sysbios_gates_GateMutex_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_gates_GateMutex_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_gates_GateMutex_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_gates_GateMutex_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* create */ +ti_sysbios_gates_GateMutex_Handle ti_sysbios_gates_GateMutex_create( const ti_sysbios_gates_GateMutex_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_gates_GateMutex_Params __prms; + ti_sysbios_gates_GateMutex_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_gates_GateMutex_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_gates_GateMutex_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_gates_GateMutex_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* construct */ +void ti_sysbios_gates_GateMutex_construct(ti_sysbios_gates_GateMutex_Struct *__obj, const ti_sysbios_gates_GateMutex_Params *__paramsPtr ) +{ + ti_sysbios_gates_GateMutex_Params __prms; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_gates_GateMutex_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_gates_GateMutex_Params), NULL); + /* module-specific initialization */ + ti_sysbios_gates_GateMutex_Instance_init__E((xdc_Ptr)__obj, &__prms); +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_gates_GateMutex_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_gates_GateMutex_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_gates_GateMutex_Instance_finalize__E, -1, TRUE); +} + +/* destruct */ +void ti_sysbios_gates_GateMutex_destruct(ti_sysbios_gates_GateMutex_Struct *obj) +{ + ti_sysbios_gates_GateMutex_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_gates_GateMutex_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_gates_GateMutex_Object__DESC__C, *((ti_sysbios_gates_GateMutex_Object**)instp), (xdc_Fxn)ti_sysbios_gates_GateMutex_Instance_finalize__E, -1, FALSE); + *((ti_sysbios_gates_GateMutex_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_gates_GateMutex_delete(ti_sysbios_gates_GateMutex_Handle *instp) +{ + ti_sysbios_gates_GateMutex_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.hal.Hwi SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_hal_Hwi_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_hal_Hwi_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_hal_Hwi_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_hal_Hwi_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_hal_Hwi_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_hal_Hwi_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_hal_Hwi_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_hal_Hwi_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_hal_Hwi_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_hal_Hwi_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_hal_Hwi_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_hal_Hwi_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_hal_Hwi_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_hal_Hwi_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_hal_Hwi_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_hal_Hwi_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_hal_Hwi_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_hal_Hwi_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_hal_Hwi_Module__startupDone__S( void ) +{ + return ti_sysbios_hal_Hwi_Module__startupDone__F(); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_hal_Hwi_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32800; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_hal_Hwi_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_hal_Hwi_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_hal_Hwi_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_hal_Hwi_Object__ *)oa) + i; + } + + if (ti_sysbios_hal_Hwi_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_hal_Hwi_Object__ *)ti_sysbios_hal_Hwi_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_hal_Hwi_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_hal_Hwi_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_hal_Hwi_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_hal_Hwi_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_hal_Hwi_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_hal_Hwi_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_hal_Hwi___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_hal_Hwi_Args__create *__args = __aa; + ti_sysbios_hal_Hwi_Params __prms; + ti_sysbios_hal_Hwi_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_hal_Hwi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_hal_Hwi_Instance_init__E(__newobj, __args->intNum, __args->hwiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_hal_Hwi_Instance_finalize__E, iStat, (xdc_Bool)(__obj != NULL)); + return NULL; + } + + return __newobj; +} + +/* create */ +ti_sysbios_hal_Hwi_Handle ti_sysbios_hal_Hwi_create( xdc_Int intNum, ti_sysbios_hal_Hwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_hal_Hwi_Params __prms; + ti_sysbios_hal_Hwi_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_hal_Hwi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_hal_Hwi_Instance_init__E(__newobj, intNum, hwiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_hal_Hwi_Instance_finalize__E, iStat, 0); + return NULL; + } + + return __newobj; +} + +/* construct */ +void ti_sysbios_hal_Hwi_construct(ti_sysbios_hal_Hwi_Struct *__obj, xdc_Int intNum, ti_sysbios_hal_Hwi_FuncPtr hwiFxn, const ti_sysbios_hal_Hwi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_hal_Hwi_Params __prms; + int iStat; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_hal_Hwi_Params), __eb); + /* module-specific initialization */ + iStat = ti_sysbios_hal_Hwi_Instance_init__E((xdc_Ptr)__obj, intNum, hwiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, (xdc_Ptr)__obj, (xdc_Fxn)ti_sysbios_hal_Hwi_Instance_finalize__E, iStat, 1); + } + +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_hal_Hwi_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_hal_Hwi_Instance_finalize__E, 0, TRUE); +} + +/* destruct */ +void ti_sysbios_hal_Hwi_destruct(ti_sysbios_hal_Hwi_Struct *obj) +{ + ti_sysbios_hal_Hwi_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_hal_Hwi_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_hal_Hwi_Object__DESC__C, *((ti_sysbios_hal_Hwi_Object**)instp), (xdc_Fxn)ti_sysbios_hal_Hwi_Instance_finalize__E, 0, FALSE); + *((ti_sysbios_hal_Hwi_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_hal_Hwi_delete(ti_sysbios_hal_Hwi_Handle *instp) +{ + ti_sysbios_hal_Hwi_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.hal.Hwi_HwiProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_hal_Hwi_HwiProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_hal_Hwi_HwiProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_hal_Hwi_HwiProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_hal_Hwi_HwiProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_hal_Hwi_HwiProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_hal_Hwi_HwiProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_hal_Hwi_HwiProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_hal_Hwi_HwiProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_hal_Hwi_HwiProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_hal_Hwi_HwiProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_hal_Hwi_HwiProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_hal_Hwi_HwiProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_hal_Hwi_HwiProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_hal_Hwi_HwiProxy_Module_GateProxy_query + +xdc_Bool ti_sysbios_hal_Hwi_HwiProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr ti_sysbios_hal_Hwi_HwiProxy_Proxy__delegate__S( void ) +{ + return 0; +} + + + +/* + * ======== ti.sysbios.heaps.HeapMem SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_heaps_HeapMem_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_heaps_HeapMem_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_heaps_HeapMem_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_heaps_HeapMem_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_heaps_HeapMem_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_heaps_HeapMem_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_heaps_HeapMem_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_heaps_HeapMem_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_heaps_HeapMem_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_heaps_HeapMem_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_heaps_HeapMem_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_heaps_HeapMem_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_heaps_HeapMem_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_heaps_HeapMem_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_heaps_HeapMem_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_heaps_HeapMem_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_heaps_HeapMem_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_heaps_HeapMem_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_heaps_HeapMem_Module__startupDone__S( void ) +{ + return 1; +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_heaps_HeapMem_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32812; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_heaps_HeapMem_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_heaps_HeapMem_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_heaps_HeapMem_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_heaps_HeapMem_Object__ *)oa) + i; + } + + if (ti_sysbios_heaps_HeapMem_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_heaps_HeapMem_Object__ *)ti_sysbios_heaps_HeapMem_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_heaps_HeapMem_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_heaps_HeapMem_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_heaps_HeapMem_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_heaps_HeapMem_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_heaps_HeapMem_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_heaps_HeapMem_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_heaps_HeapMem___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_heaps_HeapMem_Params __prms; + ti_sysbios_heaps_HeapMem_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_heaps_HeapMem_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_heaps_HeapMem_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_heaps_HeapMem_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* create */ +ti_sysbios_heaps_HeapMem_Handle ti_sysbios_heaps_HeapMem_create( const ti_sysbios_heaps_HeapMem_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_heaps_HeapMem_Params __prms; + ti_sysbios_heaps_HeapMem_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_heaps_HeapMem_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_heaps_HeapMem_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_heaps_HeapMem_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* construct */ +void ti_sysbios_heaps_HeapMem_construct(ti_sysbios_heaps_HeapMem_Struct *__obj, const ti_sysbios_heaps_HeapMem_Params *__paramsPtr ) +{ + ti_sysbios_heaps_HeapMem_Params __prms; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_heaps_HeapMem_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_heaps_HeapMem_Params), NULL); + /* module-specific initialization */ + ti_sysbios_heaps_HeapMem_Instance_init__E((xdc_Ptr)__obj, &__prms); +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_heaps_HeapMem_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_heaps_HeapMem_Object__DESC__C, obj, NULL, -1, TRUE); +} + +/* destruct */ +void ti_sysbios_heaps_HeapMem_destruct(ti_sysbios_heaps_HeapMem_Struct *obj) +{ + ti_sysbios_heaps_HeapMem_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_heaps_HeapMem_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_heaps_HeapMem_Object__DESC__C, *((ti_sysbios_heaps_HeapMem_Object**)instp), NULL, -1, FALSE); + *((ti_sysbios_heaps_HeapMem_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_heaps_HeapMem_delete(ti_sysbios_heaps_HeapMem_Handle *instp) +{ + ti_sysbios_heaps_HeapMem_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.heaps.HeapMem_Module_GateProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_heaps_HeapMem_Module_GateProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_heaps_HeapMem_Module_GateProxy_Module_GateProxy_query + +xdc_Bool ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr ti_sysbios_heaps_HeapMem_Module_GateProxy_Proxy__delegate__S( void ) +{ + return (void *)&ti_sysbios_gates_GateMutex_Module__FXNS__C; +} + + + +/* + * ======== ti.sysbios.knl.Clock SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_knl_Clock_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_knl_Clock_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_knl_Clock_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_knl_Clock_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_knl_Clock_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_knl_Clock_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_knl_Clock_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_knl_Clock_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_knl_Clock_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_knl_Clock_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_knl_Clock_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_knl_Clock_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_knl_Clock_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_knl_Clock_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_knl_Clock_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_knl_Clock_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_knl_Clock_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_knl_Clock_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Clock_Module__startupDone__S( void ) +{ + return ti_sysbios_knl_Clock_Module__startupDone__F(); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_knl_Clock_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32792; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_knl_Clock_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_knl_Clock_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_knl_Clock_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_knl_Clock_Object__ *)oa) + i; + } + + if (ti_sysbios_knl_Clock_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_knl_Clock_Object__ *)ti_sysbios_knl_Clock_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_knl_Clock_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_knl_Clock_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_knl_Clock_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_knl_Clock_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_knl_Clock_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_knl_Clock_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_knl_Clock___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_knl_Clock_Args__create *__args = __aa; + ti_sysbios_knl_Clock_Params __prms; + ti_sysbios_knl_Clock_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Clock_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Clock_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_knl_Clock_Instance_init__E(__newobj, __args->clockFxn, __args->timeout, &__prms); + return __newobj; +} + +/* create */ +ti_sysbios_knl_Clock_Handle ti_sysbios_knl_Clock_create( ti_sysbios_knl_Clock_FuncPtr clockFxn, xdc_UInt timeout, const ti_sysbios_knl_Clock_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Clock_Params __prms; + ti_sysbios_knl_Clock_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Clock_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Clock_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_knl_Clock_Instance_init__E(__newobj, clockFxn, timeout, &__prms); + return __newobj; +} + +/* construct */ +void ti_sysbios_knl_Clock_construct(ti_sysbios_knl_Clock_Struct *__obj, ti_sysbios_knl_Clock_FuncPtr clockFxn, xdc_UInt timeout, const ti_sysbios_knl_Clock_Params *__paramsPtr ) +{ + ti_sysbios_knl_Clock_Params __prms; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_knl_Clock_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Clock_Params), NULL); + /* module-specific initialization */ + ti_sysbios_knl_Clock_Instance_init__E((xdc_Ptr)__obj, clockFxn, timeout, &__prms); +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_knl_Clock_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Clock_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_knl_Clock_Instance_finalize__E, -1, TRUE); +} + +/* destruct */ +void ti_sysbios_knl_Clock_destruct(ti_sysbios_knl_Clock_Struct *obj) +{ + ti_sysbios_knl_Clock_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_knl_Clock_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Clock_Object__DESC__C, *((ti_sysbios_knl_Clock_Object**)instp), (xdc_Fxn)ti_sysbios_knl_Clock_Instance_finalize__E, -1, FALSE); + *((ti_sysbios_knl_Clock_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_knl_Clock_delete(ti_sysbios_knl_Clock_Handle *instp) +{ + ti_sysbios_knl_Clock_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.knl.Clock_TimerProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_knl_Clock_TimerProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_knl_Clock_TimerProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_knl_Clock_TimerProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_knl_Clock_TimerProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_knl_Clock_TimerProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_knl_Clock_TimerProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_knl_Clock_TimerProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_knl_Clock_TimerProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_knl_Clock_TimerProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_knl_Clock_TimerProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_knl_Clock_TimerProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_knl_Clock_TimerProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_knl_Clock_TimerProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_knl_Clock_TimerProxy_Module_GateProxy_query + +xdc_Bool ti_sysbios_knl_Clock_TimerProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr ti_sysbios_knl_Clock_TimerProxy_Proxy__delegate__S( void ) +{ + return 0; +} + + + +/* + * ======== ti.sysbios.knl.Idle SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Idle_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== ti.sysbios.knl.Intrinsics SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Intrinsics_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== ti.sysbios.knl.Intrinsics_SupportProxy SYSTEM FUNCTIONS ======== + */ + + +xdc_Bool ti_sysbios_knl_Intrinsics_SupportProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr ti_sysbios_knl_Intrinsics_SupportProxy_Proxy__delegate__S( void ) +{ + return (void *)&ti_sysbios_family_arm_m3_IntrinsicsSupport_Module__FXNS__C; +} + + +/* + * ======== ti.sysbios.knl.Queue SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_knl_Queue_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_knl_Queue_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_knl_Queue_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_knl_Queue_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_knl_Queue_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_knl_Queue_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_knl_Queue_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_knl_Queue_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_knl_Queue_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_knl_Queue_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_knl_Queue_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_knl_Queue_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_knl_Queue_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_knl_Queue_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_knl_Queue_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_knl_Queue_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_knl_Queue_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_knl_Queue_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Queue_Module__startupDone__S( void ) +{ + return 1; +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_knl_Queue_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32795; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_knl_Queue_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_knl_Queue_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_knl_Queue_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_knl_Queue_Object__ *)oa) + i; + } + + if (ti_sysbios_knl_Queue_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_knl_Queue_Object__ *)ti_sysbios_knl_Queue_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_knl_Queue_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_knl_Queue_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_knl_Queue_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_knl_Queue_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_knl_Queue_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_knl_Queue_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_knl_Queue___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_knl_Queue_Params __prms; + ti_sysbios_knl_Queue_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Queue_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Queue_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_knl_Queue_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* create */ +ti_sysbios_knl_Queue_Handle ti_sysbios_knl_Queue_create( const ti_sysbios_knl_Queue_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Queue_Params __prms; + ti_sysbios_knl_Queue_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Queue_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Queue_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_knl_Queue_Instance_init__E(__newobj, &__prms); + return __newobj; +} + +/* construct */ +void ti_sysbios_knl_Queue_construct(ti_sysbios_knl_Queue_Struct *__obj, const ti_sysbios_knl_Queue_Params *__paramsPtr ) +{ + ti_sysbios_knl_Queue_Params __prms; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_knl_Queue_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Queue_Params), NULL); + /* module-specific initialization */ + ti_sysbios_knl_Queue_Instance_init__E((xdc_Ptr)__obj, &__prms); +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_knl_Queue_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Queue_Object__DESC__C, obj, NULL, -1, TRUE); +} + +/* destruct */ +void ti_sysbios_knl_Queue_destruct(ti_sysbios_knl_Queue_Struct *obj) +{ + ti_sysbios_knl_Queue_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_knl_Queue_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Queue_Object__DESC__C, *((ti_sysbios_knl_Queue_Object**)instp), NULL, -1, FALSE); + *((ti_sysbios_knl_Queue_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_knl_Queue_delete(ti_sysbios_knl_Queue_Handle *instp) +{ + ti_sysbios_knl_Queue_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.knl.Semaphore SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_knl_Semaphore_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_knl_Semaphore_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_knl_Semaphore_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_knl_Semaphore_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_knl_Semaphore_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_knl_Semaphore_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_knl_Semaphore_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_knl_Semaphore_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_knl_Semaphore_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_knl_Semaphore_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_knl_Semaphore_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_knl_Semaphore_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_knl_Semaphore_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_knl_Semaphore_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_knl_Semaphore_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_knl_Semaphore_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_knl_Semaphore_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_knl_Semaphore_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Semaphore_Module__startupDone__S( void ) +{ + return 1; +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_knl_Semaphore_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32796; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_knl_Semaphore_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_knl_Semaphore_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_knl_Semaphore_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_knl_Semaphore_Object__ *)oa) + i; + } + + if (ti_sysbios_knl_Semaphore_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_knl_Semaphore_Object__ *)ti_sysbios_knl_Semaphore_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_knl_Semaphore_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_knl_Semaphore_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_knl_Semaphore_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_knl_Semaphore_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_knl_Semaphore_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_knl_Semaphore_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_knl_Semaphore___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_knl_Semaphore_Args__create *__args = __aa; + ti_sysbios_knl_Semaphore_Params __prms; + ti_sysbios_knl_Semaphore_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Semaphore_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Semaphore_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_knl_Semaphore_Instance_init__E(__newobj, __args->count, &__prms); + return __newobj; +} + +/* create */ +ti_sysbios_knl_Semaphore_Handle ti_sysbios_knl_Semaphore_create( xdc_Int count, const ti_sysbios_knl_Semaphore_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Semaphore_Params __prms; + ti_sysbios_knl_Semaphore_Object *__newobj; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Semaphore_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Semaphore_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + ti_sysbios_knl_Semaphore_Instance_init__E(__newobj, count, &__prms); + return __newobj; +} + +/* construct */ +void ti_sysbios_knl_Semaphore_construct(ti_sysbios_knl_Semaphore_Struct *__obj, xdc_Int count, const ti_sysbios_knl_Semaphore_Params *__paramsPtr ) +{ + ti_sysbios_knl_Semaphore_Params __prms; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_knl_Semaphore_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Semaphore_Params), NULL); + /* module-specific initialization */ + ti_sysbios_knl_Semaphore_Instance_init__E((xdc_Ptr)__obj, count, &__prms); +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_knl_Semaphore_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Semaphore_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_knl_Semaphore_Instance_finalize__E, -1, TRUE); +} + +/* destruct */ +void ti_sysbios_knl_Semaphore_destruct(ti_sysbios_knl_Semaphore_Struct *obj) +{ + ti_sysbios_knl_Semaphore_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_knl_Semaphore_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Semaphore_Object__DESC__C, *((ti_sysbios_knl_Semaphore_Object**)instp), (xdc_Fxn)ti_sysbios_knl_Semaphore_Instance_finalize__E, -1, FALSE); + *((ti_sysbios_knl_Semaphore_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_knl_Semaphore_delete(ti_sysbios_knl_Semaphore_Handle *instp) +{ + ti_sysbios_knl_Semaphore_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.knl.Swi SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_knl_Swi_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_knl_Swi_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_knl_Swi_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_knl_Swi_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_knl_Swi_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_knl_Swi_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_knl_Swi_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_knl_Swi_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_knl_Swi_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_knl_Swi_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_knl_Swi_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_knl_Swi_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_knl_Swi_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_knl_Swi_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_knl_Swi_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_knl_Swi_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_knl_Swi_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_knl_Swi_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Swi_Module__startupDone__S( void ) +{ + return ti_sysbios_knl_Swi_Module__startupDone__F(); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_knl_Swi_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32797; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_knl_Swi_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_knl_Swi_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_knl_Swi_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_knl_Swi_Object__ *)oa) + i; + } + + if (ti_sysbios_knl_Swi_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_knl_Swi_Object__ *)ti_sysbios_knl_Swi_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_knl_Swi_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_knl_Swi_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_knl_Swi_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_knl_Swi_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_knl_Swi_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_knl_Swi_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_knl_Swi___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_knl_Swi_Args__create *__args = __aa; + ti_sysbios_knl_Swi_Params __prms; + ti_sysbios_knl_Swi_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Swi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_knl_Swi_Instance_init__E(__newobj, __args->swiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_knl_Swi_Instance_finalize__E, iStat, (xdc_Bool)(__obj != NULL)); + return NULL; + } + + return __newobj; +} + +/* create */ +ti_sysbios_knl_Swi_Handle ti_sysbios_knl_Swi_create( ti_sysbios_knl_Swi_FuncPtr swiFxn, const ti_sysbios_knl_Swi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Swi_Params __prms; + ti_sysbios_knl_Swi_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Swi_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_knl_Swi_Instance_init__E(__newobj, swiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_knl_Swi_Instance_finalize__E, iStat, 0); + return NULL; + } + + return __newobj; +} + +/* construct */ +void ti_sysbios_knl_Swi_construct(ti_sysbios_knl_Swi_Struct *__obj, ti_sysbios_knl_Swi_FuncPtr swiFxn, const ti_sysbios_knl_Swi_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Swi_Params __prms; + int iStat; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Swi_Params), __eb); + /* module-specific initialization */ + iStat = ti_sysbios_knl_Swi_Instance_init__E((xdc_Ptr)__obj, swiFxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, (xdc_Ptr)__obj, (xdc_Fxn)ti_sysbios_knl_Swi_Instance_finalize__E, iStat, 1); + } + +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_knl_Swi_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_knl_Swi_Instance_finalize__E, 0, TRUE); +} + +/* destruct */ +void ti_sysbios_knl_Swi_destruct(ti_sysbios_knl_Swi_Struct *obj) +{ + ti_sysbios_knl_Swi_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_knl_Swi_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Swi_Object__DESC__C, *((ti_sysbios_knl_Swi_Object**)instp), (xdc_Fxn)ti_sysbios_knl_Swi_Instance_finalize__E, 0, FALSE); + *((ti_sysbios_knl_Swi_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_knl_Swi_delete(ti_sysbios_knl_Swi_Handle *instp) +{ + ti_sysbios_knl_Swi_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.knl.Task SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID ti_sysbios_knl_Task_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL ti_sysbios_knl_Task_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB ti_sysbios_knl_Task_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK ti_sysbios_knl_Task_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF ti_sysbios_knl_Task_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ ti_sysbios_knl_Task_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 ti_sysbios_knl_Task_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 ti_sysbios_knl_Task_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 ti_sysbios_knl_Task_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 ti_sysbios_knl_Task_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 ti_sysbios_knl_Task_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ ti_sysbios_knl_Task_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS ti_sysbios_knl_Task_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create ti_sysbios_knl_Task_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete ti_sysbios_knl_Task_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter ti_sysbios_knl_Task_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave ti_sysbios_knl_Task_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query ti_sysbios_knl_Task_Module_GateProxy_query + +/* Module__startupDone__S */ +xdc_Bool ti_sysbios_knl_Task_Module__startupDone__S( void ) +{ + return ti_sysbios_knl_Task_Module__startupDone__F(); +} + +/* Handle__label__S */ +xdc_runtime_Types_Label *ti_sysbios_knl_Task_Handle__label__S(xdc_Ptr obj, xdc_runtime_Types_Label *lab) +{ + lab->handle = obj; + lab->modId = 32798; + xdc_runtime_Core_assignLabel(lab, 0, 0); + + return lab; +} + +/* Params__init__S */ +xdc_Void ti_sysbios_knl_Task_Params__init__S( xdc_Ptr prms, const void *src, xdc_SizeT psz, xdc_SizeT isz ) +{ + xdc_runtime_Core_assignParams__I(prms, (xdc_CPtr)(src ? src : &ti_sysbios_knl_Task_Object__PARAMS__C), psz, isz); +} + +/* Object__get__S */ +xdc_Ptr ti_sysbios_knl_Task_Object__get__S(xdc_Ptr oa, xdc_Int i) +{ + if (oa) { + return ((ti_sysbios_knl_Task_Object__ *)oa) + i; + } + + if (ti_sysbios_knl_Task_Object__count__C == 0) { + return NULL; + } + + return ((ti_sysbios_knl_Task_Object__ *)ti_sysbios_knl_Task_Object__table__C) + i; +} + +/* Object__first__S */ +xdc_Ptr ti_sysbios_knl_Task_Object__first__S( void ) +{ + xdc_runtime_Types_InstHdr *iHdr = (xdc_runtime_Types_InstHdr *)ti_sysbios_knl_Task_Module__root__V.link.next; + + if (iHdr != (xdc_runtime_Types_InstHdr *)&ti_sysbios_knl_Task_Module__root__V.link) { + return iHdr + 1; + } + else { + return NULL; + } +} + +/* Object__next__S */ +xdc_Ptr ti_sysbios_knl_Task_Object__next__S( xdc_Ptr obj ) +{ + xdc_runtime_Types_InstHdr *iHdr = ((xdc_runtime_Types_InstHdr *)obj) - 1; + + if (iHdr->link.next != (xdc_runtime_Types_Link *)&ti_sysbios_knl_Task_Module__root__V.link) { + return (xdc_runtime_Types_InstHdr *)(iHdr->link.next) + 1; + } + else { + return NULL; + } +} + +/* Object__create__S */ +xdc_Ptr ti_sysbios_knl_Task_Object__create__S ( + xdc_Ptr __obj, + xdc_SizeT __osz, + const xdc_Ptr __aa, + const ti_sysbios_knl_Task___ParamsPtr __paramsPtr, + xdc_SizeT __psz, + xdc_runtime_Error_Block *__eb) +{ + ti_sysbios_knl_Task_Args__create *__args = __aa; + ti_sysbios_knl_Task_Params __prms; + ti_sysbios_knl_Task_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Task_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Task_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_knl_Task_Instance_init__E(__newobj, __args->fxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Task_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_knl_Task_Instance_finalize__E, iStat, (xdc_Bool)(__obj != NULL)); + return NULL; + } + + return __newobj; +} + +/* create */ +ti_sysbios_knl_Task_Handle ti_sysbios_knl_Task_create( ti_sysbios_knl_Task_FuncPtr fxn, const ti_sysbios_knl_Task_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Task_Params __prms; + ti_sysbios_knl_Task_Object *__newobj; + int iStat; + + /* common instance initialization */ + __newobj = xdc_runtime_Core_createObject__I(&ti_sysbios_knl_Task_Object__DESC__C, 0, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Task_Params), __eb); + if (__newobj == NULL) { + return NULL; + } + + /* module-specific initialization */ + iStat = ti_sysbios_knl_Task_Instance_init__E(__newobj, fxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Task_Object__DESC__C, __newobj, (xdc_Fxn)ti_sysbios_knl_Task_Instance_finalize__E, iStat, 0); + return NULL; + } + + return __newobj; +} + +/* construct */ +void ti_sysbios_knl_Task_construct(ti_sysbios_knl_Task_Struct *__obj, ti_sysbios_knl_Task_FuncPtr fxn, const ti_sysbios_knl_Task_Params *__paramsPtr, xdc_runtime_Error_Block *__eb ) +{ + ti_sysbios_knl_Task_Params __prms; + int iStat; + + /* common instance initialization */ + xdc_runtime_Core_constructObject__I(&ti_sysbios_knl_Task_Object__DESC__C, __obj, &__prms, (xdc_Ptr)__paramsPtr, sizeof(ti_sysbios_knl_Task_Params), __eb); + /* module-specific initialization */ + iStat = ti_sysbios_knl_Task_Instance_init__E((xdc_Ptr)__obj, fxn, &__prms, __eb); + if (xdc_runtime_Error_check(__eb)) { + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Task_Object__DESC__C, (xdc_Ptr)__obj, (xdc_Fxn)ti_sysbios_knl_Task_Instance_finalize__E, iStat, 1); + } + +} + +/* Object__destruct__S */ +xdc_Void ti_sysbios_knl_Task_Object__destruct__S( xdc_Ptr obj ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Task_Object__DESC__C, obj, (xdc_Fxn)ti_sysbios_knl_Task_Instance_finalize__E, 0, TRUE); +} + +/* destruct */ +void ti_sysbios_knl_Task_destruct(ti_sysbios_knl_Task_Struct *obj) +{ + ti_sysbios_knl_Task_Object__destruct__S(obj); +} + +/* Object__delete__S */ +xdc_Void ti_sysbios_knl_Task_Object__delete__S( xdc_Ptr instp ) +{ + xdc_runtime_Core_deleteObject__I(&ti_sysbios_knl_Task_Object__DESC__C, *((ti_sysbios_knl_Task_Object**)instp), (xdc_Fxn)ti_sysbios_knl_Task_Instance_finalize__E, 0, FALSE); + *((ti_sysbios_knl_Task_Handle*)instp) = NULL; +} + +/* delete */ +void ti_sysbios_knl_Task_delete(ti_sysbios_knl_Task_Handle *instp) +{ + ti_sysbios_knl_Task_Object__delete__S(instp); +} + + +/* + * ======== ti.sysbios.knl.Task_SupportProxy SYSTEM FUNCTIONS ======== + */ + + +xdc_Bool ti_sysbios_knl_Task_SupportProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr ti_sysbios_knl_Task_SupportProxy_Proxy__delegate__S( void ) +{ + return 0; +} + + +/* + * ======== xdc.runtime.Assert SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Assert_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Core SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Core_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Defaults SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Defaults_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Diags SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Diags_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Error SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Error_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Gate SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Gate_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Log SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Log_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Main SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Main_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Main_Module_GateProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID xdc_runtime_Main_Module_GateProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL xdc_runtime_Main_Module_GateProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB xdc_runtime_Main_Module_GateProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK xdc_runtime_Main_Module_GateProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF xdc_runtime_Main_Module_GateProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ xdc_runtime_Main_Module_GateProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 xdc_runtime_Main_Module_GateProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ xdc_runtime_Main_Module_GateProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS xdc_runtime_Main_Module_GateProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create xdc_runtime_Main_Module_GateProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete xdc_runtime_Main_Module_GateProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter xdc_runtime_Main_Module_GateProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave xdc_runtime_Main_Module_GateProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query xdc_runtime_Main_Module_GateProxy_Module_GateProxy_query + +xdc_Bool xdc_runtime_Main_Module_GateProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr xdc_runtime_Main_Module_GateProxy_Proxy__delegate__S( void ) +{ + return (void *)&ti_sysbios_gates_GateHwi_Module__FXNS__C; +} + + + +/* + * ======== xdc.runtime.Memory SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Memory_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Memory_HeapProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID xdc_runtime_Memory_HeapProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL xdc_runtime_Memory_HeapProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB xdc_runtime_Memory_HeapProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK xdc_runtime_Memory_HeapProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF xdc_runtime_Memory_HeapProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ xdc_runtime_Memory_HeapProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 xdc_runtime_Memory_HeapProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 xdc_runtime_Memory_HeapProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 xdc_runtime_Memory_HeapProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 xdc_runtime_Memory_HeapProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 xdc_runtime_Memory_HeapProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ xdc_runtime_Memory_HeapProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS xdc_runtime_Memory_HeapProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create xdc_runtime_Memory_HeapProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete xdc_runtime_Memory_HeapProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter xdc_runtime_Memory_HeapProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave xdc_runtime_Memory_HeapProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query xdc_runtime_Memory_HeapProxy_Module_GateProxy_query + +xdc_Bool xdc_runtime_Memory_HeapProxy_Proxy__abstract__S( void ) +{ + return 1; +} +xdc_Ptr xdc_runtime_Memory_HeapProxy_Proxy__delegate__S( void ) +{ + return (void *)&ti_sysbios_heaps_HeapMem_Module__FXNS__C; +} + + + +/* + * ======== xdc.runtime.Registry SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Registry_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.Startup SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Startup_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== xdc.runtime.SysMin SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_SysMin_Module__startupDone__S( void ) +{ + return xdc_runtime_SysMin_Module__startupDone__F(); +} + + + +/* + * ======== xdc.runtime.System SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_System_Module__startupDone__S( void ) +{ + return xdc_runtime_System_Module__startupDone__F(); +} + + + +/* + * ======== xdc.runtime.System_Module_GateProxy SYSTEM FUNCTIONS ======== + */ + +/* per-module runtime symbols */ +#undef Module__MID +#define Module__MID xdc_runtime_System_Module_GateProxy_Module__id__C +#undef Module__DGSINCL +#define Module__DGSINCL xdc_runtime_System_Module_GateProxy_Module__diagsIncluded__C +#undef Module__DGSENAB +#define Module__DGSENAB xdc_runtime_System_Module_GateProxy_Module__diagsEnabled__C +#undef Module__DGSMASK +#define Module__DGSMASK xdc_runtime_System_Module_GateProxy_Module__diagsMask__C +#undef Module__LOGDEF +#define Module__LOGDEF xdc_runtime_System_Module_GateProxy_Module__loggerDefined__C +#undef Module__LOGOBJ +#define Module__LOGOBJ xdc_runtime_System_Module_GateProxy_Module__loggerObj__C +#undef Module__LOGFXN0 +#define Module__LOGFXN0 xdc_runtime_System_Module_GateProxy_Module__loggerFxn0__C +#undef Module__LOGFXN1 +#define Module__LOGFXN1 xdc_runtime_System_Module_GateProxy_Module__loggerFxn1__C +#undef Module__LOGFXN2 +#define Module__LOGFXN2 xdc_runtime_System_Module_GateProxy_Module__loggerFxn2__C +#undef Module__LOGFXN4 +#define Module__LOGFXN4 xdc_runtime_System_Module_GateProxy_Module__loggerFxn4__C +#undef Module__LOGFXN8 +#define Module__LOGFXN8 xdc_runtime_System_Module_GateProxy_Module__loggerFxn8__C +#undef Module__G_OBJ +#define Module__G_OBJ xdc_runtime_System_Module_GateProxy_Module__gateObj__C +#undef Module__G_PRMS +#define Module__G_PRMS xdc_runtime_System_Module_GateProxy_Module__gatePrms__C +#undef Module__GP_create +#define Module__GP_create xdc_runtime_System_Module_GateProxy_Module_GateProxy_create +#undef Module__GP_delete +#define Module__GP_delete xdc_runtime_System_Module_GateProxy_Module_GateProxy_delete +#undef Module__GP_enter +#define Module__GP_enter xdc_runtime_System_Module_GateProxy_Module_GateProxy_enter +#undef Module__GP_leave +#define Module__GP_leave xdc_runtime_System_Module_GateProxy_Module_GateProxy_leave +#undef Module__GP_query +#define Module__GP_query xdc_runtime_System_Module_GateProxy_Module_GateProxy_query + +xdc_Bool xdc_runtime_System_Module_GateProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr xdc_runtime_System_Module_GateProxy_Proxy__delegate__S( void ) +{ + return (void *)&ti_sysbios_gates_GateHwi_Module__FXNS__C; +} + + + +/* + * ======== xdc.runtime.System_SupportProxy SYSTEM FUNCTIONS ======== + */ + + +xdc_Bool xdc_runtime_System_SupportProxy_Proxy__abstract__S( void ) +{ + return 0; +} +xdc_Ptr xdc_runtime_System_SupportProxy_Proxy__delegate__S( void ) +{ + return (void *)&xdc_runtime_SysMin_Module__FXNS__C; +} + + +/* + * ======== xdc.runtime.Text SYSTEM FUNCTIONS ======== + */ + +/* Module__startupDone__S */ +xdc_Bool xdc_runtime_Text_Module__startupDone__S( void ) +{ + return 1; +} + + + +/* + * ======== INITIALIZATION ENTRY POINT ======== + */ + +extern int __xdc__init(void); +#ifdef __GNUC__ +#ifndef __TI_COMPILER_VERSION__ + __attribute__ ((externally_visible)) +#endif +#endif +__FAR__ int (* volatile __xdc__init__addr)(void) = &__xdc__init; + + +/* + * ======== PROGRAM GLOBALS ======== + */ + +#ifdef __GNUC__ +#ifndef __TI_COMPILER_VERSION__ + __attribute__ ((externally_visible)) +#endif +#endif +const ti_sysbios_knl_Task_Handle UARTMon_taskHandle = (ti_sysbios_knl_Task_Handle)((ti_sysbios_knl_Task_Handle)&ti_sysbios_knl_Task_Object__table__V[0]); + diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg new file mode 100644 index 0000000..f2b5879 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg @@ -0,0 +1,268 @@ +/* + * ======== package/cfg/gpiointerrupt_pem4f.cfg ======== + * This generated configuration script runs the user's configuration script + * the context of a specific target and platform in order to generate + * all the files necessary to create an executable; e.g., linker command + * files, static C/C++ data structures, etc. + */ + +/* + * ======== _applyChanges ======== + * Changes that bring the build target to the state at the end of the build + * model + */ +function _applyChanges(obj, chgObj) { + var wasSealed = false; + if (obj.$sealed) { + wasSealed = true; + obj.$unseal(); + } + for (var prop in chgObj) { + if (typeof obj[prop] == 'object' && obj[prop] != undefined) { + if ("$category" in obj[prop] && obj[prop].$category == "Vector") { + obj[prop].length = chgObj[prop].length; + for (var i = 0; i < chgObj[prop].length; i++) { + if (obj[prop].length < i + 1) { + obj[prop].length++; + } + obj[prop][i] = chgObj[prop][i]; + } + } + else { + _applyChanges(obj[prop], chgObj[prop]); + } + } + else { + obj[prop] = chgObj[prop]; + } + } + if (wasSealed) { + obj.$seal(); + } +} + +/* + * ======== _runescape ======== + * Recursive unescape to decode serialized strings + */ +function _runescape(obj) { + for (var i in obj) { + if (obj[i] != null) { + if (typeof obj[i] == 'string') { + obj[i] = unescape(obj[i]); + } + else if (typeof obj[i] == 'object') { + _runescape(obj[i]); + } + } + } +} + +/* + * ======== _getPlatCfg ======== + */ +function _getPlatCfg() { + var tmp = {}; + _runescape(tmp); + return (tmp); +} +/* + * ======== _cfginit ======== + */ +function _cfginit() { + xdc.loadPackage('xdc.services.intern.cmd'); + var prog = xdc.om['xdc.cfg.Program']; + + /* initialize prog attrs from build model */ + var build = { + profile: "release", + cfgScript: "C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm/gpiointerrupt.cfg", + cfgHome: "configPkg", + cfgArgs: "null", + cfgArgsEncoded: true, + releases: { + 0: { + name: "configPkg", + attrs: { + prefix: "", + label: "default" + }, + otherFiles: {}, + excludeDirs: {} + } + }, + prelink: false + }; + _runescape(build); + build.cfgArgs = null; + build.target = xdc.module("ti.targets.arm.elf.M4F"); + var targChange = { + platforms: [ + "ti.platforms.tiva%3ATM4C1294NCPDT%3A1" + ], + version: "ti.targets.arm.elf.M4F%7B1%2C0%2C18.12%2C4", + extensions: { + ".sem4fe": { + suf: ".sem4fe", + typ: "asm" + }, + ".sem4f": { + suf: ".sem4f", + typ: "asm" + }, + ".sv7M4": { + suf: ".sv7M4", + typ: "asm" + }, + ".sv7M": { + suf: ".sv7M", + typ: "asm" + } + }, + rootDir: "C%3A/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS", + ccOpts: { + prefix: "-mv7M4%20--code_state%3D16%20--float_support%3DFPv4SPD16%20-me%20--include_path%3D%22C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm%22%20--include_path%3D%22C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc%22%20--include_path%3D%22C%3A/Users/Allen/Documents/GitHub/mm20/CCS/mm%22%20--include_path%3D%22C%3A/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b%22%20--include_path%3D%22C%3A/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix%22%20--include_path%3D%22C%3A/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include%22%20--define%3Dccs%3D%22ccs%22%20--define%3DPART_TM4C123GH6PM%20--define%3Dccs%20--define%3DTIVAWARE%20-g%20--c99%20--gcc%20--diag_warning%3D225%20--diag_warning%3D255%20--diag_wrap%3Doff%20--display_error_number%20--gen_func_subsections%3Don%20--abi%3Deabi%20%20%20-qq%20-pdsw225" + }, + rawVersion: "18.12.4" + }; + _runescape(targChange); + _applyChanges(build.target, targChange); + + prog.build = build; + + prog.name = "gpiointerrupt.xem4f"; + prog.cfgBase = "package/cfg/gpiointerrupt_pem4f"; + + prog.endian = prog.build.target.model.endian; + prog.codeModel = prog.build.target.model.codeModel; + + /* use the platform package's Platform module */ + var Platform = xdc.useModule("ti.platforms.tiva.Platform"); + var platParams = _getPlatCfg(); + var invalidParams = []; + for (var prop in platParams) { + if (!(prop in Platform.PARAMS)) { + delete platParams[prop]; + invalidParams.push(prop); + } + } + prog.platformName = "ti.platforms.tiva:TM4C123GH6PM"; + prog.platform = Platform.create("TM4C123GH6PM", platParams); + for (var i = 0; i < invalidParams.length; i++) { + Platform.$logWarning("The parameter '" + invalidParams[i] + "' is " + + "passed to this platform instance through Build.platformTable, " + + "but the instance does not have a configuration parameter with " + + "that name.", prog.platform, "TM4C123GH6PM"); + } + + /* record the executable's package name */ + prog.buildPackage = "configPkg"; + + /* record build-model information required during config generation */ + prog.$$bind("$$isasm", 0); + prog.$$bind("$$isrom", 0); + prog.$$bind("$$gentab", [ + ]); + + /* bind prog to an appropriate execution context */ + prog.cpu = prog.platform.getExeContext(prog); + + /* import the target's run-time support pkg */ + xdc.loadPackage("ti.targets.arm.rtsarm"); +} + +/* function to import the cfg script's package */ +function _userscript(script) { + var home; + var spath; + home = xdc.loadPackage("configPkg"); + + xdc.om.$$bind('$homepkg', home); + + var cfgScript = "C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/gpiointerrupt.cfg"; + if (!script) { + utils.loadCapsule(cfgScript, false, spath); + } + else { + /* set up the same environment that loadCapsule would */ + var $saveCsd = utils.csd; + var $cfgFile = utils.findFile(cfgScript, spath); + var cname = cfgScript; + if ($cfgFile) { + $cfgFile = java.io.File($cfgFile); + utils.csd = $cfgFile.getParentFile().getCanonicalPath(); + cname = "" + $cfgFile.getCanonicalPath(); + } + + /* create the capsule object */ + var cap = { + prototype: utils.global, + $path: cname, + $private: {path: cname}, + $capsule: undefined, /* set to cap below */ + }; + + /* 'this.$capsule' is always cap object */ + cap.$capsule = cap; + + /* save the capsule object */ + utils.$$capmap[cname] = cap; + + try { + var cx = + Packages.org.mozilla.javascript.Context.getCurrentContext(); + var rdr = new + java.io.BufferedReader(new java.io.StringReader(script)); + Packages.config.Shell.evaluateLoad(cx, cap, rdr, cname, 1); + } + finally { + rdr.close(); + utils.csd = $saveCsd; + } + } +} + +function _postinit() { + var cout = null; + + var Program = xdc.om['xdc.cfg.Program']; + /* get the exec command for this executable */ + if (Program.execCmd == null) { + Program.execCmd = Program.platform.getExecCmd(Program, + xdc.om["ti.platforms.tiva"].packageBase); + } + cout = "define EXEC." + Program.name + '\n\n'; + cout += Program.execCmd; + cout += "\nendef\n\n"; + + /* if SourceDir generates a makefile, we need to run it */ + _genSourceDirMak("package/cfg/gpiointerrupt_pem4f", "gpiointerrupt.pem4f"); + + utils.genDep("package/cfg/gpiointerrupt_pem4f", "configPkg", utils.loadedFiles, cout, null); +} + +function _genSourceDirMak(cfgBase, cfgName) +{ + var SourceDir = xdc.om['xdc.cfg.SourceDir']; + + if (SourceDir && SourceDir.$instances.length > 0) { + /* construct rule to run SourceDir generated makefile */ + var make = "\t$(MAKE) -f " + + SourceDir.outputDir + "/" + SourceDir.makefileName; + + /* this file is included by package.mak (if it exists) */ + var file = new java.io.File(cfgBase + ".cfg.mak"); + file["delete"](); + var out = new java.io.BufferedWriter(new java.io.FileWriter(file)); + + /* add rules to run SourceDir generated makefile */ + out.write("# invoke SourceDir generated makefile for " + cfgName + + "\n" + cfgName + ": .libraries," + cfgName + + "\n.libraries," + cfgName + ": " + cfgBase + ".xdl\n" + + make + "\n\n" + + "clean::\n" + make + " clean\n\n" + ); + out.close(); + out = null; + } +} diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.dot b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.dot new file mode 100644 index 0000000..1a60605 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.dot @@ -0,0 +1,440 @@ +digraph configuration { + size="7.5,10"; + rankdir=LR; + ranksep=".50 equally"; + concentrate=true; + compound=true; + label="\nConfiguration for configPkg/gpiointerrupt.xem4f" + node [font=Helvetica, fontsize=14, fontcolor=black]; subgraph cluster0 {label=""; __cfg [label="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/gpiointerrupt.cfg", color=white, fontcolor=blue]; + node [font=Helvetica, fontsize=10]; subgraph cluster1 { + label=""; + xdc_services_global__top [shape=box,label="xdc.services.global\n1,0,0,0", color=white]; + xdc_services_global__bot [shape=point,label="", style=invis]; + xdc_services_global_Clock [style=filled,fillcolor=lightgray, label="Clock"]; + xdc_services_global__top -> xdc_services_global_Clock[style=invis]; + xdc_services_global_Clock -> xdc_services_global__bot[style=invis]; + } + subgraph cluster2 { + label=""; + xdc__top [shape=box,label="xdc\n1,1,1,0", color=white]; + xdc__bot [shape=point,label="", style=invis]; + } + subgraph cluster3 { + label=""; + xdc_corevers__top [shape=box,label="xdc.corevers\n16,0,2,0", color=white]; + } + subgraph cluster4 { + label=""; + xdc_shelf__top [shape=box,label="xdc.shelf\n1,0,0,1469558654417", color=white]; + } + subgraph cluster5 { + label=""; + xdc_services_spec__top [shape=box,label="xdc.services.spec\n1,0,0,1469558654417", color=white]; + } + subgraph cluster6 { + label=""; + xdc_services_intern_xsr__top [shape=box,label="xdc.services.intern.xsr\n1,0,0,1469558654417", color=white]; + } + subgraph cluster7 { + label=""; + xdc_services_intern_gen__top [shape=box,label="xdc.services.intern.gen\n1,0,0,1469558654417", color=white]; + } + subgraph cluster8 { + label=""; + xdc_services_intern_cmd__top [shape=box,label="xdc.services.intern.cmd\n1,0,0,1469558654417", color=white]; + } + subgraph cluster9 { + label=""; + xdc_bld__top [shape=box,label="xdc.bld\n1,0,2,1469558654417", color=white]; + xdc_bld__bot [shape=point,label="", style=invis]; + } + subgraph cluster10 { + label=""; + ti_targets__top [shape=box,label="ti.targets\n1,0,3,1469558654417", color=white]; + ti_targets__bot [shape=point,label="", style=invis]; + } + subgraph cluster11 { + label=""; + ti_targets_arm_elf__top [shape=box,label="ti.targets.arm.elf\n1,0,0,1469558654417", color=white]; + ti_targets_arm_elf__bot [shape=point,label="", style=invis]; + } + subgraph cluster12 { + label=""; + xdc_rov__top [shape=box,label="xdc.rov\n1,0,1,1469558654417", color=white]; + xdc_rov__bot [shape=point,label="", style=invis]; + } + subgraph cluster13 { + label=""; + xdc_runtime__top [shape=box,label="xdc.runtime\n2,1,0,1469558654417", color=white]; + xdc_runtime__bot [shape=point,label="", style=invis]; + xdc_runtime_Assert [style=filled,fillcolor=lightgray, label="Assert"]; + xdc_runtime__top -> xdc_runtime_Assert[style=invis]; + xdc_runtime_Assert -> xdc_runtime__bot[style=invis]; + xdc_runtime_Core [style=filled,fillcolor=lightgray, label="Core"]; + xdc_runtime__top -> xdc_runtime_Core[style=invis]; + xdc_runtime_Core -> xdc_runtime__bot[style=invis]; + xdc_runtime_Defaults [style=filled,fillcolor=lightgray, label="Defaults"]; + xdc_runtime__top -> xdc_runtime_Defaults[style=invis]; + xdc_runtime_Defaults -> xdc_runtime__bot[style=invis]; + xdc_runtime_Diags [style=filled,fillcolor=lightgray, label="Diags"]; + xdc_runtime__top -> xdc_runtime_Diags[style=invis]; + xdc_runtime_Diags -> xdc_runtime__bot[style=invis]; + xdc_runtime_Error [style=filled,fillcolor=lightgray, label="Error"]; + xdc_runtime__top -> xdc_runtime_Error[style=invis]; + xdc_runtime_Error -> xdc_runtime__bot[style=invis]; + xdc_runtime_Gate [style=filled,fillcolor=lightgray, label="Gate"]; + xdc_runtime__top -> xdc_runtime_Gate[style=invis]; + xdc_runtime_Gate -> xdc_runtime__bot[style=invis]; + xdc_runtime_Log [style=filled,fillcolor=lightgray, label="Log"]; + xdc_runtime__top -> xdc_runtime_Log[style=invis]; + xdc_runtime_Log -> xdc_runtime__bot[style=invis]; + xdc_runtime_Main [style=filled,fillcolor=lightgray, label="Main"]; + xdc_runtime__top -> xdc_runtime_Main[style=invis]; + xdc_runtime_Main -> xdc_runtime__bot[style=invis]; + xdc_runtime_Memory [style=filled,fillcolor=lightgray, label="Memory"]; + xdc_runtime__top -> xdc_runtime_Memory[style=invis]; + xdc_runtime_Memory -> xdc_runtime__bot[style=invis]; + xdc_runtime_Registry [style=filled,fillcolor=lightgray, label="Registry"]; + xdc_runtime__top -> xdc_runtime_Registry[style=invis]; + xdc_runtime_Registry -> xdc_runtime__bot[style=invis]; + xdc_runtime_Startup [style=filled,fillcolor=lightgray, label="Startup"]; + xdc_runtime__top -> xdc_runtime_Startup[style=invis]; + xdc_runtime_Startup -> xdc_runtime__bot[style=invis]; + xdc_runtime_Reset [style=filled,fillcolor=lightgray, label="Reset"]; + xdc_runtime__top -> xdc_runtime_Reset[style=invis]; + xdc_runtime_Reset -> xdc_runtime__bot[style=invis]; + xdc_runtime_System [style=filled,fillcolor=lightgray, label="System"]; + xdc_runtime__top -> xdc_runtime_System[style=invis]; + xdc_runtime_System -> xdc_runtime__bot[style=invis]; + xdc_runtime_SysMin [style=filled,fillcolor=lightgray, label="SysMin"]; + xdc_runtime__top -> xdc_runtime_SysMin[style=invis]; + xdc_runtime_SysMin -> xdc_runtime__bot[style=invis]; + xdc_runtime_Text [style=filled,fillcolor=lightgray, label="Text"]; + xdc_runtime__top -> xdc_runtime_Text[style=invis]; + xdc_runtime_Text -> xdc_runtime__bot[style=invis]; + xdc_runtime_Main_Module_GateProxy [style=filled,fillcolor=lightgray, label="Main_Module_GateProxy"]; + xdc_runtime__top -> xdc_runtime_Main_Module_GateProxy[style=invis]; + xdc_runtime_Main_Module_GateProxy -> xdc_runtime__bot[style=invis]; + xdc_runtime_Memory_HeapProxy [style=filled,fillcolor=lightgray, label="Memory_HeapProxy"]; + xdc_runtime__top -> xdc_runtime_Memory_HeapProxy[style=invis]; + xdc_runtime_Memory_HeapProxy -> xdc_runtime__bot[style=invis]; + xdc_runtime_System_SupportProxy [style=filled,fillcolor=lightgray, label="System_SupportProxy"]; + xdc_runtime__top -> xdc_runtime_System_SupportProxy[style=invis]; + xdc_runtime_System_SupportProxy -> xdc_runtime__bot[style=invis]; + xdc_runtime_System_Module_GateProxy [style=filled,fillcolor=lightgray, label="System_Module_GateProxy"]; + xdc_runtime__top -> xdc_runtime_System_Module_GateProxy[style=invis]; + xdc_runtime_System_Module_GateProxy -> xdc_runtime__bot[style=invis]; + } + subgraph cluster14 { + label=""; + xdc_services_getset__top [shape=box,label="xdc.services.getset\n1,0,0,1469558654417", color=white]; + xdc_services_getset__bot [shape=point,label="", style=invis]; + } + subgraph cluster15 { + label=""; + ti_targets_arm_rtsarm__top [shape=box,label="ti.targets.arm.rtsarm\n1,0,0,1469558654417", color=white]; + ti_targets_arm_rtsarm__bot [shape=point,label="", style=invis]; + } + subgraph cluster16 { + label=""; + ti_sysbios_interfaces__top [shape=box,label="ti.sysbios.interfaces\n2,0,0,0,0", color=white]; + } + subgraph cluster17 { + label=""; + ti_sysbios_family__top [shape=box,label="ti.sysbios.family\n2,0,0,0,0", color=white]; + ti_sysbios_family__bot [shape=point,label="", style=invis]; + ti_sysbios_family_Settings [style=filled,fillcolor=lightgray, label="Settings"]; + ti_sysbios_family__top -> ti_sysbios_family_Settings[style=invis]; + ti_sysbios_family_Settings -> ti_sysbios_family__bot[style=invis]; + } + subgraph cluster18 { + label=""; + ti_sysbios_family_arm__top [shape=box,label="ti.sysbios.family.arm\n2,0,0,0,0", color=white]; + ti_sysbios_family_arm__bot [shape=point,label="", style=invis]; + } + subgraph cluster19 { + label=""; + ti_sysbios_rts__top [shape=box,label="ti.sysbios.rts\n2,0,0,0,1469558654417", color=white]; + ti_sysbios_rts__bot [shape=point,label="", style=invis]; + ti_sysbios_rts_MemAlloc [style=filled,fillcolor=lightgray, label="MemAlloc"]; + ti_sysbios_rts__top -> ti_sysbios_rts_MemAlloc[style=invis]; + ti_sysbios_rts_MemAlloc -> ti_sysbios_rts__bot[style=invis]; + } + subgraph cluster20 { + label=""; + xdc_runtime_knl__top [shape=box,label="xdc.runtime.knl\n1,0,0,1469558654417", color=white]; + xdc_runtime_knl__bot [shape=point,label="", style=invis]; + } + subgraph cluster21 { + label=""; + ti_catalog_arm_peripherals_timers__top [shape=box,label="ti.catalog.arm.peripherals.timers\n", color=white]; + ti_catalog_arm_peripherals_timers__bot [shape=point,label="", style=invis]; + ti_catalog_arm_peripherals_timers_Timer [style=filled,fillcolor=lightgray, label="Timer"]; + ti_catalog_arm_peripherals_timers__top -> ti_catalog_arm_peripherals_timers_Timer[style=invis]; + ti_catalog_arm_peripherals_timers_Timer -> ti_catalog_arm_peripherals_timers__bot[style=invis]; + } + subgraph cluster22 { + label=""; + ti_catalog_arm_cortexm4__top [shape=box,label="ti.catalog.arm.cortexm4\n1,0,0,1469558654417", color=white]; + ti_catalog_arm_cortexm4__bot [shape=point,label="", style=invis]; + ti_catalog_arm_cortexm4_Tiva [style=filled,fillcolor=lightgray, label="Tiva"]; + ti_catalog_arm_cortexm4__top -> ti_catalog_arm_cortexm4_Tiva[style=invis]; + ti_catalog_arm_cortexm4_Tiva -> ti_catalog_arm_cortexm4__bot[style=invis]; + } + subgraph cluster23 { + label=""; + ti_catalog__top [shape=box,label="ti.catalog\n1,0,0,1469558654417", color=white]; + } + subgraph cluster24 { + label=""; + ti_catalog_peripherals_hdvicp2__top [shape=box,label="ti.catalog.peripherals.hdvicp2\n", color=white]; + ti_catalog_peripherals_hdvicp2__bot [shape=point,label="", style=invis]; + } + subgraph cluster25 { + label=""; + xdc_platform__top [shape=box,label="xdc.platform\n1,0,1,0", color=white]; + xdc_platform__bot [shape=point,label="", style=invis]; + xdc_platform_ExeContext [style=filled,fillcolor=lightgray, label="ExeContext"]; + xdc_platform__top -> xdc_platform_ExeContext[style=invis]; + xdc_platform_ExeContext -> xdc_platform__bot[style=invis]; + xdc_platform_Utils [style=filled,fillcolor=lightgray, label="Utils"]; + xdc_platform__top -> xdc_platform_Utils[style=invis]; + xdc_platform_Utils -> xdc_platform__bot[style=invis]; + } + subgraph cluster26 { + label=""; + xdc_cfg__top [shape=box,label="xdc.cfg\n1,0,2,0", color=white]; + xdc_cfg__bot [shape=point,label="", style=invis]; + xdc_cfg_Program [style=filled,fillcolor=lightgray, label="Program"]; + xdc_cfg__top -> xdc_cfg_Program[style=invis]; + xdc_cfg_Program -> xdc_cfg__bot[style=invis]; + xdc_cfg_Main [style=filled,fillcolor=lightgray, label="Main"]; + xdc_cfg__top -> xdc_cfg_Main[style=invis]; + xdc_cfg_Main -> xdc_cfg__bot[style=invis]; + xdc_cfg_SourceDir [style=filled,fillcolor=lightgray, label="SourceDir"]; + xdc_cfg__top -> xdc_cfg_SourceDir[style=invis]; + xdc_cfg_SourceDir -> xdc_cfg__bot[style=invis]; + } + subgraph cluster27 { + label=""; + ti_catalog_arm_cortexm3__top [shape=box,label="ti.catalog.arm.cortexm3\n1,0,0,1469558654417", color=white]; + ti_catalog_arm_cortexm3__bot [shape=point,label="", style=invis]; + } + subgraph cluster28 { + label=""; + ti_catalog_arm_cortexm4_tiva_ce__top [shape=box,label="ti.catalog.arm.cortexm4.tiva.ce\n1,0,0,1469558654417", color=white]; + ti_catalog_arm_cortexm4_tiva_ce__bot [shape=point,label="", style=invis]; + ti_catalog_arm_cortexm4_tiva_ce_Boot [style=filled,fillcolor=lightgray, label="Boot"]; + ti_catalog_arm_cortexm4_tiva_ce__top -> ti_catalog_arm_cortexm4_tiva_ce_Boot[style=invis]; + ti_catalog_arm_cortexm4_tiva_ce_Boot -> ti_catalog_arm_cortexm4_tiva_ce__bot[style=invis]; + } + subgraph cluster29 { + label=""; + ti_platforms_tiva__top [shape=box,label="ti.platforms.tiva\n1,0,0,1469558654417", color=white]; + ti_platforms_tiva__bot [shape=point,label="", style=invis]; + ti_platforms_tiva_Platform [style=filled,fillcolor=lightgray, label="Platform"]; + ti_platforms_tiva__top -> ti_platforms_tiva_Platform[style=invis]; + ti_platforms_tiva_Platform -> ti_platforms_tiva__bot[style=invis]; + } + subgraph cluster30 { + label=""; + ti_sysbios__top [shape=box,label="ti.sysbios\n2,0,0,0,0", color=white]; + ti_sysbios__bot [shape=point,label="", style=invis]; + ti_sysbios_BIOS [style=filled,fillcolor=lightgray, label="BIOS"]; + ti_sysbios__top -> ti_sysbios_BIOS[style=invis]; + ti_sysbios_BIOS -> ti_sysbios__bot[style=invis]; + ti_sysbios_Build [style=filled,fillcolor=lightgray, label="Build"]; + ti_sysbios__top -> ti_sysbios_Build[style=invis]; + ti_sysbios_Build -> ti_sysbios__bot[style=invis]; + ti_sysbios_BIOS_RtsGateProxy [style=filled,fillcolor=lightgray, label="BIOS_RtsGateProxy"]; + ti_sysbios__top -> ti_sysbios_BIOS_RtsGateProxy[style=invis]; + ti_sysbios_BIOS_RtsGateProxy -> ti_sysbios__bot[style=invis]; + } + subgraph cluster31 { + label=""; + ti_drivers_ports__top [shape=box,label="ti.drivers.ports\n1,0,0,0", color=white]; + } + subgraph cluster32 { + label=""; + ti_mw_fatfs__top [shape=box,label="ti.mw.fatfs\n", color=white]; + ti_mw_fatfs__bot [shape=point,label="", style=invis]; + } + subgraph cluster33 { + label=""; + ti_drivers__top [shape=box,label="ti.drivers\n1,0,0,0", color=white]; + ti_drivers__bot [shape=point,label="", style=invis]; + ti_drivers_Config [style=filled,fillcolor=lightgray, label="Config"]; + ti_drivers__top -> ti_drivers_Config[style=invis]; + ti_drivers_Config -> ti_drivers__bot[style=invis]; + } + subgraph cluster34 { + label=""; + ti_mw_wifi_cc3x00__top [shape=box,label="ti.mw.wifi.cc3x00\n1,0,0,1469558654417", color=white]; + } + subgraph cluster35 { + label=""; + ti_mw__top [shape=box,label="ti.mw\n", color=white]; + ti_mw__bot [shape=point,label="", style=invis]; + ti_mw_Config [style=filled,fillcolor=lightgray, label="Config"]; + ti_mw__top -> ti_mw_Config[style=invis]; + ti_mw_Config -> ti_mw__bot[style=invis]; + } + subgraph cluster36 { + label=""; + ti_sysbios_hal__top [shape=box,label="ti.sysbios.hal\n2,0,0,0,0", color=white]; + ti_sysbios_hal__bot [shape=point,label="", style=invis]; + ti_sysbios_hal_Hwi [style=filled,fillcolor=lightgray, label="Hwi"]; + ti_sysbios_hal__top -> ti_sysbios_hal_Hwi[style=invis]; + ti_sysbios_hal_Hwi -> ti_sysbios_hal__bot[style=invis]; + ti_sysbios_hal_Hwi_HwiProxy [style=filled,fillcolor=lightgray, label="Hwi_HwiProxy"]; + ti_sysbios_hal__top -> ti_sysbios_hal_Hwi_HwiProxy[style=invis]; + ti_sysbios_hal_Hwi_HwiProxy -> ti_sysbios_hal__bot[style=invis]; + } + subgraph cluster37 { + label=""; + ti_sysbios_family_arm_m3__top [shape=box,label="ti.sysbios.family.arm.m3\n2,0,0,0,0", color=white]; + ti_sysbios_family_arm_m3__bot [shape=point,label="", style=invis]; + ti_sysbios_family_arm_m3_Hwi [style=filled,fillcolor=lightgray, label="Hwi"]; + ti_sysbios_family_arm_m3__top -> ti_sysbios_family_arm_m3_Hwi[style=invis]; + ti_sysbios_family_arm_m3_Hwi -> ti_sysbios_family_arm_m3__bot[style=invis]; + ti_sysbios_family_arm_m3_IntrinsicsSupport [style=filled,fillcolor=lightgray, label="IntrinsicsSupport"]; + ti_sysbios_family_arm_m3__top -> ti_sysbios_family_arm_m3_IntrinsicsSupport[style=invis]; + ti_sysbios_family_arm_m3_IntrinsicsSupport -> ti_sysbios_family_arm_m3__bot[style=invis]; + ti_sysbios_family_arm_m3_TaskSupport [style=filled,fillcolor=lightgray, label="TaskSupport"]; + ti_sysbios_family_arm_m3__top -> ti_sysbios_family_arm_m3_TaskSupport[style=invis]; + ti_sysbios_family_arm_m3_TaskSupport -> ti_sysbios_family_arm_m3__bot[style=invis]; + } + subgraph cluster38 { + label=""; + ti_sysbios_knl__top [shape=box,label="ti.sysbios.knl\n2,0,0,0,0", color=white]; + ti_sysbios_knl__bot [shape=point,label="", style=invis]; + ti_sysbios_knl_Clock [style=filled,fillcolor=lightgray, label="Clock"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Clock[style=invis]; + ti_sysbios_knl_Clock -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Idle [style=filled,fillcolor=lightgray, label="Idle"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Idle[style=invis]; + ti_sysbios_knl_Idle -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Intrinsics [style=filled,fillcolor=lightgray, label="Intrinsics"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Intrinsics[style=invis]; + ti_sysbios_knl_Intrinsics -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Queue [style=filled,fillcolor=lightgray, label="Queue"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Queue[style=invis]; + ti_sysbios_knl_Queue -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Semaphore [style=filled,fillcolor=lightgray, label="Semaphore"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Semaphore[style=invis]; + ti_sysbios_knl_Semaphore -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Swi [style=filled,fillcolor=lightgray, label="Swi"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Swi[style=invis]; + ti_sysbios_knl_Swi -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Task [style=filled,fillcolor=lightgray, label="Task"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Task[style=invis]; + ti_sysbios_knl_Task -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Clock_TimerProxy [style=filled,fillcolor=lightgray, label="Clock_TimerProxy"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Clock_TimerProxy[style=invis]; + ti_sysbios_knl_Clock_TimerProxy -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Intrinsics_SupportProxy [style=filled,fillcolor=lightgray, label="Intrinsics_SupportProxy"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Intrinsics_SupportProxy[style=invis]; + ti_sysbios_knl_Intrinsics_SupportProxy -> ti_sysbios_knl__bot[style=invis]; + ti_sysbios_knl_Task_SupportProxy [style=filled,fillcolor=lightgray, label="Task_SupportProxy"]; + ti_sysbios_knl__top -> ti_sysbios_knl_Task_SupportProxy[style=invis]; + ti_sysbios_knl_Task_SupportProxy -> ti_sysbios_knl__bot[style=invis]; + } + subgraph cluster39 { + label=""; + ti_sysbios_family_arm_lm4__top [shape=box,label="ti.sysbios.family.arm.lm4\n1,0,0,0,1469558654417", color=white]; + ti_sysbios_family_arm_lm4__bot [shape=point,label="", style=invis]; + ti_sysbios_family_arm_lm4_Timer [style=filled,fillcolor=lightgray, label="Timer"]; + ti_sysbios_family_arm_lm4__top -> ti_sysbios_family_arm_lm4_Timer[style=invis]; + ti_sysbios_family_arm_lm4_Timer -> ti_sysbios_family_arm_lm4__bot[style=invis]; + } + subgraph cluster40 { + label=""; + ti_tirtos_utils__top [shape=box,label="ti.tirtos.utils\n", color=white]; + ti_tirtos_utils__bot [shape=point,label="", style=invis]; + ti_tirtos_utils_UARTMon [style=filled,fillcolor=lightgray, label="UARTMon"]; + ti_tirtos_utils__top -> ti_tirtos_utils_UARTMon[style=invis]; + ti_tirtos_utils_UARTMon -> ti_tirtos_utils__bot[style=invis]; + } + subgraph cluster41 { + label=""; + ti_sysbios_gates__top [shape=box,label="ti.sysbios.gates\n2,0,0,0,1469558654417", color=white]; + ti_sysbios_gates__bot [shape=point,label="", style=invis]; + ti_sysbios_gates_GateHwi [style=filled,fillcolor=lightgray, label="GateHwi"]; + ti_sysbios_gates__top -> ti_sysbios_gates_GateHwi[style=invis]; + ti_sysbios_gates_GateHwi -> ti_sysbios_gates__bot[style=invis]; + ti_sysbios_gates_GateMutex [style=filled,fillcolor=lightgray, label="GateMutex"]; + ti_sysbios_gates__top -> ti_sysbios_gates_GateMutex[style=invis]; + ti_sysbios_gates_GateMutex -> ti_sysbios_gates__bot[style=invis]; + } + subgraph cluster42 { + label=""; + ti_sysbios_xdcruntime__top [shape=box,label="ti.sysbios.xdcruntime\n1,0,0,1469558654417", color=white]; + ti_sysbios_xdcruntime__bot [shape=point,label="", style=invis]; + ti_sysbios_xdcruntime_Settings [style=filled,fillcolor=lightgray, label="Settings"]; + ti_sysbios_xdcruntime__top -> ti_sysbios_xdcruntime_Settings[style=invis]; + ti_sysbios_xdcruntime_Settings -> ti_sysbios_xdcruntime__bot[style=invis]; + } + subgraph cluster43 { + label=""; + ti_sysbios_heaps__top [shape=box,label="ti.sysbios.heaps\n2,0,0,0,1469558654417", color=white]; + ti_sysbios_heaps__bot [shape=point,label="", style=invis]; + ti_sysbios_heaps_HeapMem [style=filled,fillcolor=lightgray, label="HeapMem"]; + ti_sysbios_heaps__top -> ti_sysbios_heaps_HeapMem[style=invis]; + ti_sysbios_heaps_HeapMem -> ti_sysbios_heaps__bot[style=invis]; + ti_sysbios_heaps_HeapMem_Module_GateProxy [style=filled,fillcolor=lightgray, label="HeapMem_Module_GateProxy"]; + ti_sysbios_heaps__top -> ti_sysbios_heaps_HeapMem_Module_GateProxy[style=invis]; + ti_sysbios_heaps_HeapMem_Module_GateProxy -> ti_sysbios_heaps__bot[style=invis]; + } + subgraph cluster44 { + label=""; + ti_sysbios_utils__top [shape=box,label="ti.sysbios.utils\n2,0,0,0,1469558654417", color=white]; + ti_sysbios_utils__bot [shape=point,label="", style=invis]; + } + subgraph cluster45 { + label=""; + configPkg__top [shape=box,label="configPkg\n", color=white]; + } + subgraph cluster46 { + label=""; + xdc_services_io__top [shape=box,label="xdc.services.io\n1,0,0,0", color=white]; + xdc_services_io__bot [shape=point,label="", style=invis]; + } + } + node [font=Helvetica, fontsize=10]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_targets_arm_rtsarm__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster15]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_family_arm__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster18]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_catalog_arm_cortexm4_tiva_ce__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster28]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster30]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_drivers_ports__top -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster31]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_mw_fatfs__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster32]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_drivers__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster33]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_mw_wifi_cc3x00__top -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster34]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_hal__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster36]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_family_arm_m3__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster37]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_knl__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster38]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_family_arm_lm4__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster39]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_tirtos_utils__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster40]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_gates__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster41]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_xdcruntime__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster42]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_heaps__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster43]; + ti_targets_arm_elf_M4F__1_0_5__2_5 [shape=record,label="ti.targets.arm.elf.M4F|1,0,5.2,5",style=filled, fillcolor=lightgrey]; + ti_sysbios_utils__bot -> ti_targets_arm_elf_M4F__1_0_5__2_5 [ltail=cluster44]; + ti_targets_arm_elf_M4F__1_0_18__12_4 [shape=record,label="ti.targets.arm.elf.M4F|1,0,18.12,4",style=filled, fillcolor=lightgrey]; + configPkg__top -> ti_targets_arm_elf_M4F__1_0_18__12_4 [ltail=cluster45]; +} diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.mak b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.mak new file mode 100644 index 0000000..1c94aea --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.mak @@ -0,0 +1,8 @@ +# invoke SourceDir generated makefile for gpiointerrupt.pem4f +gpiointerrupt.pem4f: .libraries,gpiointerrupt.pem4f +.libraries,gpiointerrupt.pem4f: package/cfg/gpiointerrupt_pem4f.xdl + $(MAKE) -f C:\Users\Allen\Documents\GitHub\mm20\CCS\mm/src/makefile.libs + +clean:: + $(MAKE) -f C:\Users\Allen\Documents\GitHub\mm20\CCS\mm/src/makefile.libs clean + diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.xml b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.xml new file mode 100644 index 0000000..f3550c5 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.cfg.xml @@ -0,0 +1,7598 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + assertion failure%s%s0x0 + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + 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ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + 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common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + TREE_TABLE + viewInitDiagsMasks + DiagsMaskView + + +true + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + 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ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + MODULE + viewInitModule + ModuleView + + +true + + 0x10A_mustUseEnhancedClockMode: This device requires the Enhanced Clock Mode. + + 0x10A_mustNotUseEnhancedClockMode: This device does not support the Enhanced Clock Mode. + + + + + + + + + + + + + + + + + + + + + + 0tivanullnull + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + + + + MODULE + viewInitModule + ModuleView + + + + + MODULE_DATA + viewInitErrorScan + ErrorView + + +true + + + + + + 0x00x4c4b400 + + + + + + + + + + + + + + &ti_sysbios_BIOS_registerRTSLock&ti_sysbios_family_arm_lm4_Timer_startup__E + + + + + + + ALWAYS_ON + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_ON + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + true + xdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0 + null + null + null + null + COMMON_FILE + DELETE_POLICY + false + true + false +true + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + + + + module + undefined + + + common$.gate + common$.gateParams + + + + + + + instance + undefined + + + Log.Event + + + + + + + instance + undefined + + + Assert.Id + + + + + + + instance + undefined + + + Error.Id + + + + +0x00x0nullnullnull0x9falsenullnullnullnullnullnullnull0x0null0x0null0x10x2xdc.services.intern.xsr.Value$Obj@1f11159::(xdc.runtime.IGateProvider.Module)ti.sysbios.gates.GateMutexfalse + + + + + + + + -Dti_sysbios_knl_Task_minimizeLatency__D=FALSE-Dti_sysbios_knl_Clock_stopCheckNext__D=FALSE-Dti_sysbios_family_arm_m3_Hwi_enableException__D=TRUE-Dti_sysbios_family_arm_m3_Hwi_disablePriority__D=32U-Dti_sysbios_family_arm_m3_Hwi_numSparseInterrupts__D=0U + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFfalsexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + + E_stackOverflow: ISR stack overflow.0x0 + + + + + + ALWAYS_ON + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_ON + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + true + xdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0 + null + null + null + null + COMMON_FILE + DELETE_POLICY + false + true + false +true + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + + + + module + undefined + + + common$.gate + common$.gateParams + + + + + + + instance + undefined + + + Log.Event + + + + + + + instance + undefined + + + Assert.Id + + + + + + + instance + undefined + + + Error.Id + + + + +0x00x0nullnullnull0x8falsenullnullnullnullnullnullnull0x0null0x0nulltrueundefinedundefinedtruexdc.services.intern.xsr.Value$Obj@d2ce52::(ti.sysbios.interfaces.IHwi.Module)ti.sysbios.family.arm.m3.Hwifalse + + + + + + + + + + + + + + + + + + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFfalsexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + INSTANCE + viewInitBasic + BasicView + + + + + INSTANCE + viewInitDetailed + DetailedView + + + + + MODULE + viewInitModule + ModuleView + + + + + TREE + viewInitException + ExcContext + + +true + + 0x300undefinedLM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x + + 0x200undefinedLD_end: hwi: 0x%x + + 0x10A_unsupportedMaskingOption: unsupported maskSetting. + + E_alreadyDefined: Hwi already defined: intr# %d0x0 + + E_hwiLimitExceeded: Too many interrupts defined0x0 + + E_exception: id = %d, pc = %08x. +To see more exception detail, set ti.sysbios.family.arm.m3.Hwi.enableException = true or, +examine the Exception view for the ti.sysbios.family.arm.m3.Hwi module using ROV.0x0 + + E_noIsr: id = %d, pc = %08x0x0 + + E_NMI: %s0x0 + + E_hardFault: %s0x0 + + E_memFault: %s, address: %08x0x0 + + E_busFault: %s, address: %08x0x0 + + E_usageFault: %s0x0 + + E_svCall: svNum = %d0x0 + + E_debugMon: %s0x0 + + E_reserved: %s %d0x0 + + + + + + + + + + + + + + + + 0x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x00x0 + + + + 0x00x0 + + + nullnull + + + nullnull + + 0x10x00x00x00x00x0 + + + + + + + + + + + + + + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + true + true + 0xff + &ti_sysbios_family_arm_lm4_Timer_isrStub__E + xdc.services.intern.xsr.Value$Obj@362bc7::ti.sysbios.family.arm.m3.Hwi.Instance#0 + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + false + false + undefined + null + undefined + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFfalsexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + undefined + + + common$.gate + common$.gateParams + + + + instance + undefined + + + Log.Event + + + + instance + undefined + + + Assert.Id + + + + instance + undefined + + + Error.Id + + + + + + + + + + + + + + + + + + + + + + + + + + INSTANCE + viewInitBasic + BasicView + + + + + MODULE + viewInitModule + ModuleView + + +true + + + ALWAYS_ON + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_ON + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + ALWAYS_OFF + true + xdc.services.intern.xsr.Value$Obj@1882f93::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateHwi.Instance#0 + null + null + null + null + COMMON_FILE + DELETE_POLICY + false + true + false +true + + + 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See GateMutex API doc for details. + + + + + + + + + + + + + + + + + + + + + + + + + + ALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_ONALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFALWAYS_OFFtruexdc.services.intern.xsr.Value$Obj@103c0f2::(xdc.runtime.IGateProvider.Instance)ti.sysbios.gates.GateMutex.Instance#0nullnullnullnullCOMMON_FILEDELETE_POLICYfalsetruefalse + + + + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + module + 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COMMON_FILE + DELETE_POLICY + false + true + false +true + + + module + undefined + + + common$.instanceHeap + common$.instanceSection + common$.memoryPolicy + common$.namedModule + common$.namedInstance + common$.fxntab + common$.romPatchTable + + + + + + + module + undefined + + + common$.logger + common$.diags_ASSERT + common$.diags_ENTRY + common$.diags_EXIT + common$.diags_INTERNAL + common$.diags_LIFECYCLE + common$.diags_STATUS + common$.diags_USER1 + common$.diags_USER2 + common$.diags_USER3 + common$.diags_USER4 + common$.diags_USER5 + common$.diags_USER6 + common$.diags_INFO + common$.diags_ANALYSIS + + + + + + + module + undefined + + + common$.gate + common$.gateParams + + + + + + + instance + undefined + + + Log.Event + + + + + + + instance + undefined + + + Assert.Id + + + + + + + instance + undefined + + + Error.Id + + + + +0x00x0nullnullnull0xafalsenullnullnullnullnullnullnull0x0null0x0null0x10x2xdc.services.intern.xsr.Value$Obj@30944a::(xdc.runtime.IGateProvider.Module)ti.sysbios.gates.GateMutexfalse + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.dep b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.dep new file mode 100644 index 0000000..aaef3fb --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.dep @@ -0,0 +1,284 @@ +# +# The following is generated by utils.genDep for package/cfg/gpiointerrupt_pem4f +# +package/cfg/gpiointerrupt_pem4f.c package/cfg/gpiointerrupt_pem4f.h package/cfg/gpiointerrupt_pem4f.xdl:package.xs package/cfg/gpiointerrupt_pem4f.cfg C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/gpiointerrupt.cfg C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/IPackage.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/Warnings.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/BuildEnvironment.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Configuration.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Executable.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget2.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITarget3.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/ITargetFilter.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Library.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Manifest.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/PackageContents.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Repository.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Script.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/Utils.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/bld/_gen.xs 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C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/GateThread.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/SemProcess.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/SemThread.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/Semaphore.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/Sync.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/SyncGeneric.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/SyncNull.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/SyncSemThread.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/Thread.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/knl/package.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/getset/GetSet.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/Clock.xs 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C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/ITI813X.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/ITI8148.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/ITI8168.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/OMAP4430.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/Tiva.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/CC32xx.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/DRA7XX.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/MSP432.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/OMAP5430.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/TDA3XX.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/Tiva.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/Vayu.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/Boot.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/package.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/Platform.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/Build.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/Settings.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/HwiCommon.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/IntrinsicsSupport.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/MPU.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/Settings.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/TaskSupport.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/armSettings.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/Seconds.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/Timer.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/TimestampProvider.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/package.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Clobber.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Exception.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/IntrinsicsSupport.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Power.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/TaskSupport.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Timer.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/TimestampProvider.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/package.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/package.xs 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+C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/Hwi.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/Power.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/PowerNull.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/Seconds.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/SecondsClock.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/Timer.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/TimerNull.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapBuf.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapCallback.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapMem.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapMultiBuf.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapNull.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapTrack.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Idle.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Intrinsics.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Mailbox.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/MemAlloc.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/utils/Load.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/utils/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/CacheSupport.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/GateProcessSupport.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/GateThreadSupport.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/SemProcessSupport.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/SemThreadSupport.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/Settings.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/ThreadSupport.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/C28_float.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/C28_large.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/ITarget.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/IArm.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Config.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/Power.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/Config.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/FatFS.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/package.xs: + + +define EXEC.gpiointerrupt.xem4f + +@$(ECHO) ti.platforms.tiva platform package cannot execute gpiointerrupt.xem4f on Windows + +endef + +# +# The following is generated by java +# + +gpiointerrupt.xem4f: package/cfg/gpiointerrupt_pem4f.oem4f C:/ti/tirtos_tivac_2_16_00_08/packages/ti/tirtos/utils/lib/release/ti.tirtos.utils.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/lib/cc3x00_host_driver.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_tivaware.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_wifi_tivaware.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/lib/release/ti.mw.fatfs.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/lib/tirtosport.aem4f C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/src/sysbios/sysbios.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/lib/Boot.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/lib/ti.targets.arm.rtsarm.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/lib/boot.aem4f C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/lib/auto_init.aem4f + +package/cfg/gpiointerrupt_pem4f.c: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/cfg/Program.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/cfg/SourceDir.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/cfg/makefile.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/Platform.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Startup.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Reset.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/SysMin.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/Boot.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/Build.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/makefile.xdt C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/File.xs C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/package.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/MemAlloc.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/linkcmd.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/linkcmd.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/linkUtils.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/linkUtils.xs C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/linkcmd.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/Hwi_link.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/MPU_link.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/linkcmd.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/linkcmd.xdt C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi_link.xdt +package/cfg/gpiointerrupt_pem4f.c package/cfg/gpiointerrupt_pem4f.xdl: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/peripherals/timers/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/peripherals/hdvicp2/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/.interfaces C:/ti/tirtos_tivac_2_16_00_08/packages/ti/tirtos/utils/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/gates/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/.interfaces C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/utils/.interfaces .interfaces + +# +# rule-less goals for files outside this package +# (these goals force a re-build if these files are +# moved or deleted) +# +C:/ti/tirtos_tivac_2_16_00_08/packages/ti/tirtos/utils/lib/release/ti.tirtos.utils.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/lib/cc3x00_host_driver.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_tivaware.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_wifi_tivaware.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/lib/release/ti.mw.fatfs.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/lib/tirtosport.aem4f: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/src/sysbios/sysbios.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/lib/Boot.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/lib/ti.targets.arm.rtsarm.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/lib/boot.aem4f: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/lib/auto_init.aem4f: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/cfg/Program.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/cfg/SourceDir.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/cfg/makefile.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/Platform.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Startup.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Reset.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/SysMin.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/Boot.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/Build.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/makefile.xdt: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/File.xs: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/io/package.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/MemAlloc.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/linkcmd.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/linkcmd.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/linkUtils.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/linkUtils.xs: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/linkcmd.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/Hwi_link.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/MPU_link.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/linkcmd.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/linkcmd.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi_link.xdt: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/rtsarm/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/rts/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/peripherals/timers/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/peripherals/hdvicp2/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm3/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/platforms/tiva/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/fatfs/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/packages/ti/tirtos/utils/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/gates/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/xdcruntime/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/.interfaces: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/utils/.interfaces: + diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.h b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.h new file mode 100644 index 0000000..6d620cc --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.h @@ -0,0 +1,16 @@ +/* + * Do not modify this file; it is automatically + * generated and any modifications will be overwritten. + * + * @(#) xdc-B21 + */ + +#include + +#include +extern const ti_sysbios_knl_Task_Handle UARTMon_taskHandle; + +extern int xdc_runtime_Startup__EXECFXN__C; + +extern int xdc_runtime_Startup__RESETFXN__C; + diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.mak b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.mak new file mode 100644 index 0000000..4f342a0 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.mak @@ -0,0 +1,46 @@ +# +# Do not edit this file. This file is generated from +# package.bld. Any modifications to this file will be +# overwritten whenever makefiles are re-generated. +# +# target compatibility key = ti.targets.arm.elf.M4F{1,0,18.12,4 +# +ifeq (,$(MK_NOGENDEPS)) +-include package/cfg/gpiointerrupt_pem4f.oem4f.dep +package/cfg/gpiointerrupt_pem4f.oem4f.dep: ; +endif + +package/cfg/gpiointerrupt_pem4f.oem4f: | .interfaces +package/cfg/gpiointerrupt_pem4f.oem4f: package/cfg/gpiointerrupt_pem4f.c package/cfg/gpiointerrupt_pem4f.mak + @$(RM) $@.dep + $(RM) $@ + @$(MSG) clem4f $< ... + $(ti.targets.arm.elf.M4F.rootDir)/bin/armcl -c -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM --define=ccs --define=TIVAWARE -g --c99 --gcc --diag_warning=225 --diag_warning=255 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi -qq -pdsw225 -ms --fp_mode=strict --endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -eo.oem4f -ea.sem4f -Dxdc_cfg__xheader__='"configPkg/package/cfg/gpiointerrupt_pem4f.h"' -Dxdc_target_name__=M4F -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_release -Dxdc_bld__vers_1_0_18_12_4 -O2 $(XDCINCS) -I$(ti.targets.arm.elf.M4F.rootDir)/include/rts -I$(ti.targets.arm.elf.M4F.rootDir)/include -fs=./package/cfg -fr=./package/cfg -fc $< + $(MKDEP) -a $@.dep -p package/cfg -s oem4f $< -C -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM --define=ccs --define=TIVAWARE -g --c99 --gcc --diag_warning=225 --diag_warning=255 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi -qq -pdsw225 -ms --fp_mode=strict --endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -eo.oem4f -ea.sem4f -Dxdc_cfg__xheader__='"configPkg/package/cfg/gpiointerrupt_pem4f.h"' -Dxdc_target_name__=M4F -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_release -Dxdc_bld__vers_1_0_18_12_4 -O2 $(XDCINCS) -I$(ti.targets.arm.elf.M4F.rootDir)/include/rts -I$(ti.targets.arm.elf.M4F.rootDir)/include -fs=./package/cfg -fr=./package/cfg + -@$(FIXDEP) $@.dep $@.dep + +package/cfg/gpiointerrupt_pem4f.oem4f: export C_DIR= +package/cfg/gpiointerrupt_pem4f.oem4f: PATH:=$(ti.targets.arm.elf.M4F.rootDir)/bin/;$(PATH) +package/cfg/gpiointerrupt_pem4f.oem4f: Path:=$(ti.targets.arm.elf.M4F.rootDir)/bin/;$(PATH) + +package/cfg/gpiointerrupt_pem4f.sem4f: | .interfaces +package/cfg/gpiointerrupt_pem4f.sem4f: package/cfg/gpiointerrupt_pem4f.c package/cfg/gpiointerrupt_pem4f.mak + @$(RM) $@.dep + $(RM) $@ + @$(MSG) clem4f -n $< ... + $(ti.targets.arm.elf.M4F.rootDir)/bin/armcl -c -n -s --symdebug:none -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM --define=ccs --define=TIVAWARE -g --c99 --gcc --diag_warning=225 --diag_warning=255 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi -qq -pdsw225 --endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -eo.oem4f -ea.sem4f -Dxdc_cfg__xheader__='"configPkg/package/cfg/gpiointerrupt_pem4f.h"' -Dxdc_target_name__=M4F -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_release -Dxdc_bld__vers_1_0_18_12_4 -O2 $(XDCINCS) -I$(ti.targets.arm.elf.M4F.rootDir)/include/rts -I$(ti.targets.arm.elf.M4F.rootDir)/include -fs=./package/cfg -fr=./package/cfg -fc $< + $(MKDEP) -a $@.dep -p package/cfg -s oem4f $< -C -n -s --symdebug:none -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM --define=ccs --define=TIVAWARE -g --c99 --gcc --diag_warning=225 --diag_warning=255 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi -qq -pdsw225 --endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -eo.oem4f -ea.sem4f -Dxdc_cfg__xheader__='"configPkg/package/cfg/gpiointerrupt_pem4f.h"' -Dxdc_target_name__=M4F -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_release -Dxdc_bld__vers_1_0_18_12_4 -O2 $(XDCINCS) -I$(ti.targets.arm.elf.M4F.rootDir)/include/rts -I$(ti.targets.arm.elf.M4F.rootDir)/include -fs=./package/cfg -fr=./package/cfg + -@$(FIXDEP) $@.dep $@.dep + +package/cfg/gpiointerrupt_pem4f.sem4f: export C_DIR= +package/cfg/gpiointerrupt_pem4f.sem4f: PATH:=$(ti.targets.arm.elf.M4F.rootDir)/bin/;$(PATH) +package/cfg/gpiointerrupt_pem4f.sem4f: Path:=$(ti.targets.arm.elf.M4F.rootDir)/bin/;$(PATH) + +clean,em4f :: + -$(RM) package/cfg/gpiointerrupt_pem4f.oem4f + -$(RM) package/cfg/gpiointerrupt_pem4f.sem4f + +gpiointerrupt.pem4f: package/cfg/gpiointerrupt_pem4f.oem4f package/cfg/gpiointerrupt_pem4f.mak + +clean:: + -$(RM) package/cfg/gpiointerrupt_pem4f.mak diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.oem4f b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.oem4f new file mode 100644 index 0000000..eac1bcb Binary files /dev/null and b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.oem4f differ diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.oem4f.dep b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.oem4f.dep new file mode 100644 index 0000000..af31994 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.oem4f.dep @@ -0,0 +1,122 @@ +package/cfg/gpiointerrupt_pem4f.oem4f: package/cfg/gpiointerrupt_pem4f.c C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/catalog/arm/cortexm4/tiva/ce/Boot.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/lm4/Timer.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/Hwi.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/IntrinsicsSupport.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/m3/TaskSupport.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/gates/GateHwi.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/gates/GateMutex.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/hal/Hwi.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/HeapMem.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Idle.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Intrinsics.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Semaphore.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Core.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Defaults.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Gate.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Memory.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Registry.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Startup.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/SysMin.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/limits.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System__internal.h 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+C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/heaps/package/HeapMem_Module_GateProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Clock_TimerProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Intrinsics__prologue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Intrinsics_SupportProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Intrinsics__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__prologue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Gate__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Gate__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Main_Module_GateProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Memory_HeapProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Registry__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Registry__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/ISystemSupport.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_SupportProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_Module_GateProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__epilogue.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/xlocale/_stdio.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/xlocale/_string.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/std.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/package/package.defs.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/c28/Hwi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/gic/Hwi.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event__prologue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Event__epilogue.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/c28/Hwi__prologue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/c28/package/package.defs.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/c28/Hwi__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/gic/Hwi__prologue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/gic/package/package.defs.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/family/arm/gic/Hwi__epilogue.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h: diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.rov.xs b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.rov.xs new file mode 100644 index 0000000..85461c8 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.rov.xs @@ -0,0 +1,18647 @@ +__o = null +__obj = [ + this, // #0 + {}, // #1 + {}, // #2 ti.tirtos.utils.UARTMon + [], // #3 ti.tirtos.utils.UARTMon/$instances + {}, // #4 ti.tirtos.utils.UARTMon/common$ + [], // #5 ti.tirtos.utils.UARTMon/configNameMap$ + {}, // #6 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Memory' + [], // #7 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #8 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Diagnostics' + [], // #9 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #10 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Concurrency' + [], // #11 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #12 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Log Events' + [], // #13 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #14 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Asserts' + [], // #15 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #16 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Errors' + [], // #17 ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Errors'/fields + {}, // #18 xdc.rov.ViewInfo.Instance#20 + {}, // #19 xdc.rov.ViewInfo + [], // #20 xdc.rov.ViewInfo/$instances + {}, // #21 xdc.rov.ViewInfo.Instance#0 + [], // #22 xdc.rov.ViewInfo.Instance#0/viewMap + {}, // #23 xdc.rov.ViewInfo.Instance#0/viewMap/'DiagsMasks' + {}, // #24 xdc.rov.ViewInfo.Instance#1 + [], // #25 xdc.rov.ViewInfo.Instance#1/viewMap + {}, // #26 xdc.rov.ViewInfo.Instance#1/viewMap/'Basic' + {}, // #27 xdc.rov.ViewInfo.Instance#1/viewMap/'Records' + {}, // #28 xdc.rov.ViewInfo.Instance#2 + [], // #29 xdc.rov.ViewInfo.Instance#2/viewMap + {}, // #30 xdc.rov.ViewInfo.Instance#2/viewMap/'Basic' + {}, // #31 xdc.rov.ViewInfo.Instance#3 + [], // #32 xdc.rov.ViewInfo.Instance#3/viewMap + {}, // #33 xdc.rov.ViewInfo.Instance#3/viewMap/'Registered Modules' + {}, // #34 xdc.rov.ViewInfo.Instance#4 + [], // #35 xdc.rov.ViewInfo.Instance#4/viewMap + {}, // #36 xdc.rov.ViewInfo.Instance#4/viewMap/'Module' + {}, // #37 xdc.rov.ViewInfo.Instance#4/viewMap/'Startup State' + {}, // #38 xdc.rov.ViewInfo.Instance#5 + [], // #39 xdc.rov.ViewInfo.Instance#5/viewMap + {}, // #40 xdc.rov.ViewInfo.Instance#5/viewMap/'XDCROOT' + {}, // #41 xdc.rov.ViewInfo.Instance#5/viewMap/'XDCPATH' + {}, // #42 xdc.rov.ViewInfo.Instance#6 + [], // #43 xdc.rov.ViewInfo.Instance#6/viewMap + {}, // #44 xdc.rov.ViewInfo.Instance#6/viewMap/'Module' + {}, // #45 xdc.rov.ViewInfo.Instance#6/viewMap/'OutputBuffer' + {}, // #46 xdc.rov.ViewInfo.Instance#7 + [], // #47 xdc.rov.ViewInfo.Instance#7/viewMap + {}, // #48 xdc.rov.ViewInfo.Instance#7/viewMap/'Module' + {}, // #49 xdc.rov.ViewInfo.Instance#8 + [], // #50 xdc.rov.ViewInfo.Instance#8/viewMap + {}, // #51 xdc.rov.ViewInfo.Instance#8/viewMap/'MpuRegionAttrsView' + {}, // #52 xdc.rov.ViewInfo.Instance#9 + [], // #53 xdc.rov.ViewInfo.Instance#9/viewMap + {}, // #54 xdc.rov.ViewInfo.Instance#9/viewMap/'Basic' + {}, // #55 xdc.rov.ViewInfo.Instance#9/viewMap/'Module' + {}, // #56 xdc.rov.ViewInfo.Instance#10 + [], // #57 xdc.rov.ViewInfo.Instance#10/viewMap + {}, // #58 xdc.rov.ViewInfo.Instance#10/viewMap/'Idle.funcList' + {}, // #59 xdc.rov.ViewInfo.Instance#11 + [], // #60 xdc.rov.ViewInfo.Instance#11/viewMap + {}, // #61 xdc.rov.ViewInfo.Instance#11/viewMap/'Basic' + {}, // #62 xdc.rov.ViewInfo.Instance#12 + [], // #63 xdc.rov.ViewInfo.Instance#12/viewMap + {}, // #64 xdc.rov.ViewInfo.Instance#12/viewMap/'Basic' + {}, // #65 xdc.rov.ViewInfo.Instance#12/viewMap/'Detailed' + {}, // #66 xdc.rov.ViewInfo.Instance#13 + [], // #67 xdc.rov.ViewInfo.Instance#13/viewMap + {}, // #68 xdc.rov.ViewInfo.Instance#13/viewMap/'Basic' + {}, // #69 xdc.rov.ViewInfo.Instance#14 + [], // #70 xdc.rov.ViewInfo.Instance#14/viewMap + {}, // #71 xdc.rov.ViewInfo.Instance#14/viewMap/'Basic' + {}, // #72 xdc.rov.ViewInfo.Instance#15 + [], // #73 xdc.rov.ViewInfo.Instance#15/viewMap + {}, // #74 xdc.rov.ViewInfo.Instance#15/viewMap/'Basic' + {}, // #75 xdc.rov.ViewInfo.Instance#15/viewMap/'Module' + {}, // #76 xdc.rov.ViewInfo.Instance#15/viewMap/'ReadyQs' + {}, // #77 xdc.rov.ViewInfo.Instance#16 + [], // #78 xdc.rov.ViewInfo.Instance#16/viewMap + {}, // #79 xdc.rov.ViewInfo.Instance#16/viewMap/'Basic' + {}, // #80 xdc.rov.ViewInfo.Instance#16/viewMap/'Detailed' + {}, // #81 xdc.rov.ViewInfo.Instance#16/viewMap/'CallStacks' + {}, // #82 xdc.rov.ViewInfo.Instance#16/viewMap/'ReadyQs' + {}, // #83 xdc.rov.ViewInfo.Instance#16/viewMap/'Module' + {}, // #84 xdc.rov.ViewInfo.Instance#17 + [], // #85 xdc.rov.ViewInfo.Instance#17/viewMap + {}, // #86 xdc.rov.ViewInfo.Instance#17/viewMap/'Module' + {}, // #87 xdc.rov.ViewInfo.Instance#17/viewMap/'Scan for errors...' + {}, // #88 xdc.rov.ViewInfo.Instance#18 + [], // #89 xdc.rov.ViewInfo.Instance#18/viewMap + {}, // #90 xdc.rov.ViewInfo.Instance#18/viewMap/'Basic' + {}, // #91 xdc.rov.ViewInfo.Instance#18/viewMap/'Detailed' + {}, // #92 xdc.rov.ViewInfo.Instance#18/viewMap/'Module' + {}, // #93 xdc.rov.ViewInfo.Instance#18/viewMap/'Exception' + {}, // #94 xdc.rov.ViewInfo.Instance#19 + [], // #95 xdc.rov.ViewInfo.Instance#19/viewMap + {}, // #96 xdc.rov.ViewInfo.Instance#19/viewMap/'Basic' + {}, // #97 xdc.rov.ViewInfo.Instance#19/viewMap/'Device' + {}, // #98 xdc.rov.ViewInfo.Instance#19/viewMap/'Module' + {}, // #99 xdc.rov.ViewInfo.Instance#21 + [], // #100 xdc.rov.ViewInfo.Instance#21/viewMap + {}, // #101 xdc.rov.ViewInfo.Instance#21/viewMap/'Basic' + {}, // #102 xdc.rov.ViewInfo.Instance#22 + [], // #103 xdc.rov.ViewInfo.Instance#22/viewMap + {}, // #104 xdc.rov.ViewInfo.Instance#22/viewMap/'Basic' + {}, // #105 xdc.rov.ViewInfo.Instance#23 + [], // #106 xdc.rov.ViewInfo.Instance#23/viewMap + {}, // #107 xdc.rov.ViewInfo.Instance#23/viewMap/'Basic' + {}, // #108 xdc.rov.ViewInfo.Instance#24 + [], // #109 xdc.rov.ViewInfo.Instance#24/viewMap + {}, // #110 xdc.rov.ViewInfo.Instance#24/viewMap/'Basic' + {}, // #111 xdc.rov.ViewInfo.Instance#25 + [], // #112 xdc.rov.ViewInfo.Instance#25/viewMap + {}, // #113 xdc.rov.ViewInfo.Instance#25/viewMap/'Basic' + {}, // #114 xdc.rov.ViewInfo.Instance#25/viewMap/'Detailed' + {}, // #115 xdc.rov.ViewInfo.Instance#26 + [], // #116 xdc.rov.ViewInfo.Instance#26/viewMap + {}, // #117 xdc.rov.ViewInfo.Instance#26/viewMap/'Basic' + {}, // #118 xdc.rov.ViewInfo.Instance#27 + [], // #119 xdc.rov.ViewInfo.Instance#27/viewMap + {}, // #120 xdc.rov.ViewInfo.Instance#27/viewMap/'Basic' + {}, // #121 xdc.rov.ViewInfo.Instance#28 + [], // #122 xdc.rov.ViewInfo.Instance#28/viewMap + {}, // #123 xdc.rov.ViewInfo.Instance#28/viewMap/'Basic' + {}, // #124 xdc.rov.ViewInfo.Instance#29 + [], // #125 xdc.rov.ViewInfo.Instance#29/viewMap + {}, // #126 xdc.rov.ViewInfo.Instance#29/viewMap/'Basic' + {}, // #127 xdc.rov.ViewInfo.Instance#29/viewMap/'Detailed' + {}, // #128 xdc.rov.ViewInfo.Instance#30 + [], // #129 xdc.rov.ViewInfo.Instance#30/viewMap + {}, // #130 xdc.rov.ViewInfo.Instance#30/viewMap/'Basic' + {}, // #131 xdc.rov.ViewInfo.Instance#30/viewMap/'Detailed' + {}, // #132 xdc.rov.ViewInfo.Instance#30/viewMap/'FreeList' + {}, // #133 xdc.rov.ViewInfo.Instance#31 + [], // #134 xdc.rov.ViewInfo.Instance#31/viewMap + {}, // #135 xdc.rov.ViewInfo.Instance#31/viewMap/'Basic' + {}, // #136 xdc.rov.ViewInfo.Instance#31/viewMap/'Detailed' + {}, // #137 xdc.rov.ViewInfo.Instance#32 + [], // #138 xdc.rov.ViewInfo.Instance#32/viewMap + {}, // #139 xdc.rov.ViewInfo.Instance#32/viewMap/'Basic' + {}, // #140 xdc.rov.ViewInfo.Instance#32/viewMap/'HeapAllocList' + {}, // #141 xdc.rov.ViewInfo.Instance#32/viewMap/'TaskAllocList' + {}, // #142 xdc.rov.ViewInfo.Instance#33 + [], // #143 xdc.rov.ViewInfo.Instance#33/viewMap + {}, // #144 xdc.rov.ViewInfo.Instance#33/viewMap/'Basic' + {}, // #145 xdc.rov.ViewInfo.Instance#33/viewMap/'Module' + {}, // #146 xdc.rov.ViewInfo.Instance#34 + [], // #147 xdc.rov.ViewInfo.Instance#34/viewMap + {}, // #148 xdc.rov.ViewInfo.Instance#34/viewMap/'Basic' + {}, // #149 xdc.rov.ViewInfo.Instance#34/viewMap/'Device' + {}, // #150 xdc.rov.ViewInfo.Instance#34/viewMap/'Module' + {}, // #151 xdc.rov.ViewInfo.Instance#35 + [], // #152 xdc.rov.ViewInfo.Instance#35/viewMap + {}, // #153 xdc.rov.ViewInfo.Instance#35/viewMap/'Module' + [], // #154 xdc.rov.ViewInfo.Instance#20/viewMap + {}, // #155 xdc.rov.ViewInfo.Instance#20/viewMap/'Basic' + [], // #156 ti.tirtos.utils.UARTMon/viewNameMap$ + {}, // #157 xdc.runtime.Assert + [], // #158 xdc.runtime.Assert/$instances + {}, // #159 xdc.runtime.Error.Desc#0 + {}, // #160 xdc.runtime.Assert/common$ + {}, // #161 ti.sysbios.gates.GateHwi.Instance#0 + {}, // #162 ti.sysbios.gates.GateHwi + [], // #163 ti.sysbios.gates.GateHwi/$instances + {}, // #164 ti.sysbios.gates.GateHwi/common$ + [], // #165 ti.sysbios.gates.GateHwi/configNameMap$ + {}, // #166 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Memory' + [], // #167 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #168 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Diagnostics' + [], // #169 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #170 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Concurrency' + [], // #171 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #172 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Log Events' + [], // #173 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #174 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Asserts' + [], // #175 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #176 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Errors' + [], // #177 ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Errors'/fields + [], // #178 ti.sysbios.gates.GateHwi/viewNameMap$ + {}, // #179 ti.sysbios.gates.GateHwi.Instance#0/instance + [], // #180 xdc.runtime.Assert/configNameMap$ + {}, // #181 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Memory' + [], // #182 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #183 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Diagnostics' + [], // #184 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #185 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Concurrency' + [], // #186 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #187 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Log Events' + [], // #188 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #189 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Asserts' + [], // #190 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #191 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Errors' + [], // #192 xdc.runtime.Assert/configNameMap$/'xdc.runtime/Errors'/fields + [], // #193 xdc.runtime.Assert/viewNameMap$ + {}, // #194 xdc.runtime.Core + [], // #195 xdc.runtime.Core/$instances + {}, // #196 xdc.runtime.Assert.Desc#0 + {}, // #197 xdc.runtime.Core/common$ + [], // #198 xdc.runtime.Core/configNameMap$ + {}, // #199 xdc.runtime.Core/configNameMap$/'xdc.runtime/Memory' + [], // #200 xdc.runtime.Core/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #201 xdc.runtime.Core/configNameMap$/'xdc.runtime/Diagnostics' + [], // #202 xdc.runtime.Core/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #203 xdc.runtime.Core/configNameMap$/'xdc.runtime/Concurrency' + [], // #204 xdc.runtime.Core/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #205 xdc.runtime.Core/configNameMap$/'xdc.runtime/Log Events' + [], // #206 xdc.runtime.Core/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #207 xdc.runtime.Core/configNameMap$/'xdc.runtime/Asserts' + [], // #208 xdc.runtime.Core/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #209 xdc.runtime.Core/configNameMap$/'xdc.runtime/Errors' + [], // #210 xdc.runtime.Core/configNameMap$/'xdc.runtime/Errors'/fields + [], // #211 xdc.runtime.Core/viewNameMap$ + {}, // #212 xdc.runtime.Defaults + [], // #213 xdc.runtime.Defaults/$instances + {}, // #214 xdc.runtime.Defaults/common$ + [], // #215 xdc.runtime.Defaults/configNameMap$ + {}, // #216 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Memory' + [], // #217 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #218 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Diagnostics' + [], // #219 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #220 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Concurrency' + [], // #221 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #222 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Log Events' + [], // #223 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #224 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Asserts' + [], // #225 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #226 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Errors' + [], // #227 xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Errors'/fields + {}, // #228 xdc.runtime.Defaults/noRuntimeCommon$ + [], // #229 xdc.runtime.Defaults/viewNameMap$ + {}, // #230 xdc.runtime.Diags + [], // #231 xdc.runtime.Diags/$instances + {}, // #232 xdc.runtime.Diags/common$ + [], // #233 xdc.runtime.Diags/configNameMap$ + {}, // #234 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Memory' + [], // #235 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #236 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Diagnostics' + [], // #237 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #238 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Concurrency' + [], // #239 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #240 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Log Events' + [], // #241 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #242 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Asserts' + [], // #243 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #244 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Errors' + [], // #245 xdc.runtime.Diags/configNameMap$/'xdc.runtime/Errors'/fields + [], // #246 xdc.runtime.Diags/viewNameMap$ + {}, // #247 xdc.runtime.Error + [], // #248 xdc.runtime.Error/$instances + {}, // #249 xdc.runtime.Error.Desc#1 + {}, // #250 xdc.runtime.Error.Desc#2 + {}, // #251 xdc.runtime.Error.Desc#3 + {}, // #252 xdc.runtime.Error/common$ + [], // #253 xdc.runtime.Error/configNameMap$ + {}, // #254 xdc.runtime.Error/configNameMap$/'xdc.runtime/Memory' + [], // #255 xdc.runtime.Error/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #256 xdc.runtime.Error/configNameMap$/'xdc.runtime/Diagnostics' + [], // #257 xdc.runtime.Error/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #258 xdc.runtime.Error/configNameMap$/'xdc.runtime/Concurrency' + [], // #259 xdc.runtime.Error/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #260 xdc.runtime.Error/configNameMap$/'xdc.runtime/Log Events' + [], // #261 xdc.runtime.Error/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #262 xdc.runtime.Error/configNameMap$/'xdc.runtime/Asserts' + [], // #263 xdc.runtime.Error/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #264 xdc.runtime.Error/configNameMap$/'xdc.runtime/Errors' + [], // #265 xdc.runtime.Error/configNameMap$/'xdc.runtime/Errors'/fields + [], // #266 xdc.runtime.Error/viewNameMap$ + {}, // #267 xdc.runtime.Gate + [], // #268 xdc.runtime.Gate/$instances + {}, // #269 xdc.runtime.Gate/common$ + [], // #270 xdc.runtime.Gate/configNameMap$ + {}, // #271 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Memory' + [], // #272 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #273 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Diagnostics' + [], // #274 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #275 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Concurrency' + [], // #276 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #277 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Log Events' + [], // #278 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #279 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Asserts' + [], // #280 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #281 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Errors' + [], // #282 xdc.runtime.Gate/configNameMap$/'xdc.runtime/Errors'/fields + [], // #283 xdc.runtime.Gate/viewNameMap$ + {}, // #284 xdc.runtime.Log + [], // #285 xdc.runtime.Log/$instances + {}, // #286 xdc.runtime.Log.EventDesc#0 + {}, // #287 xdc.runtime.Log.EventDesc#1 + {}, // #288 xdc.runtime.Log.EventDesc#3 + {}, // #289 xdc.runtime.Log.EventDesc#2 + {}, // #290 xdc.runtime.Log.EventDesc#4 + {}, // #291 xdc.runtime.Log.EventDesc#6 + {}, // #292 xdc.runtime.Log.EventDesc#7 + {}, // #293 xdc.runtime.Log.EventDesc#9 + {}, // #294 xdc.runtime.Log.EventDesc#8 + {}, // #295 xdc.runtime.Log.EventDesc#10 + {}, // #296 xdc.runtime.Log.EventDesc#5 + {}, // #297 xdc.runtime.Log/common$ + [], // #298 xdc.runtime.Log/configNameMap$ + {}, // #299 xdc.runtime.Log/configNameMap$/'xdc.runtime/Memory' + [], // #300 xdc.runtime.Log/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #301 xdc.runtime.Log/configNameMap$/'xdc.runtime/Diagnostics' + [], // #302 xdc.runtime.Log/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #303 xdc.runtime.Log/configNameMap$/'xdc.runtime/Concurrency' + [], // #304 xdc.runtime.Log/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #305 xdc.runtime.Log/configNameMap$/'xdc.runtime/Log Events' + [], // #306 xdc.runtime.Log/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #307 xdc.runtime.Log/configNameMap$/'xdc.runtime/Asserts' + [], // #308 xdc.runtime.Log/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #309 xdc.runtime.Log/configNameMap$/'xdc.runtime/Errors' + [], // #310 xdc.runtime.Log/configNameMap$/'xdc.runtime/Errors'/fields + [], // #311 xdc.runtime.Log/idToInfo + [], // #312 xdc.runtime.Log/viewNameMap$ + {}, // #313 xdc.runtime.Main + [], // #314 xdc.runtime.Main/$instances + {}, // #315 xdc.runtime.Main/common$ + [], // #316 xdc.runtime.Main/configNameMap$ + {}, // #317 xdc.runtime.Main/configNameMap$/'xdc.runtime/Memory' + [], // #318 xdc.runtime.Main/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #319 xdc.runtime.Main/configNameMap$/'xdc.runtime/Diagnostics' + [], // #320 xdc.runtime.Main/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #321 xdc.runtime.Main/configNameMap$/'xdc.runtime/Concurrency' + [], // #322 xdc.runtime.Main/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #323 xdc.runtime.Main/configNameMap$/'xdc.runtime/Log Events' + [], // #324 xdc.runtime.Main/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #325 xdc.runtime.Main/configNameMap$/'xdc.runtime/Asserts' + [], // #326 xdc.runtime.Main/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #327 xdc.runtime.Main/configNameMap$/'xdc.runtime/Errors' + [], // #328 xdc.runtime.Main/configNameMap$/'xdc.runtime/Errors'/fields + [], // #329 xdc.runtime.Main/viewNameMap$ + {}, // #330 xdc.runtime.Memory + [], // #331 xdc.runtime.Memory/$instances + {}, // #332 ti.sysbios.heaps.HeapMem + [], // #333 ti.sysbios.heaps.HeapMem/$instances + {}, // #334 ti.sysbios.heaps.HeapMem.Instance#0 + {}, // #335 ti.sysbios.heaps.HeapMem.Instance#0/instance + {}, // #336 xdc.runtime.Assert.Desc#59 + {}, // #337 xdc.runtime.Assert.Desc#58 + {}, // #338 xdc.runtime.Assert.Desc#60 + {}, // #339 xdc.runtime.Assert.Desc#57 + {}, // #340 xdc.runtime.Error.Desc#29 + {}, // #341 ti.sysbios.gates.GateMutex + [], // #342 ti.sysbios.gates.GateMutex/$instances + {}, // #343 ti.sysbios.gates.GateMutex.Instance#0 + {}, // #344 ti.sysbios.gates.GateMutex.Instance#0/instance + {}, // #345 ti.sysbios.gates.GateMutex.Instance#1 + {}, // #346 ti.sysbios.gates.GateMutex.Instance#1/instance + {}, // #347 xdc.runtime.Assert.Desc#44 + {}, // #348 ti.sysbios.gates.GateMutex/common$ + [], // #349 ti.sysbios.gates.GateMutex/configNameMap$ + {}, // #350 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Memory' + [], // #351 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #352 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Diagnostics' + [], // #353 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #354 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Concurrency' + [], // #355 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #356 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Log Events' + [], // #357 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #358 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Asserts' + [], // #359 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #360 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Errors' + [], // #361 ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Errors'/fields + [], // #362 ti.sysbios.gates.GateMutex/viewNameMap$ + {}, // #363 ti.sysbios.heaps.HeapMem/common$ + [], // #364 ti.sysbios.heaps.HeapMem/configNameMap$ + {}, // #365 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Memory' + [], // #366 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #367 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Diagnostics' + [], // #368 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #369 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Concurrency' + [], // #370 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #371 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Log Events' + [], // #372 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #373 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Asserts' + [], // #374 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #375 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Errors' + [], // #376 ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Errors'/fields + [], // #377 ti.sysbios.heaps.HeapMem/viewNameMap$ + {}, // #378 xdc.runtime.Memory/common$ + [], // #379 xdc.runtime.Memory/configNameMap$ + {}, // #380 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Memory' + [], // #381 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #382 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Diagnostics' + [], // #383 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #384 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Concurrency' + [], // #385 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #386 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Log Events' + [], // #387 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #388 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Asserts' + [], // #389 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #390 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Errors' + [], // #391 xdc.runtime.Memory/configNameMap$/'xdc.runtime/Errors'/fields + [], // #392 xdc.runtime.Memory/viewNameMap$ + {}, // #393 xdc.runtime.Registry + [], // #394 xdc.runtime.Registry/$instances + {}, // #395 xdc.runtime.Registry/common$ + [], // #396 xdc.runtime.Registry/configNameMap$ + {}, // #397 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Memory' + [], // #398 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #399 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Diagnostics' + [], // #400 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #401 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Concurrency' + [], // #402 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #403 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Log Events' + [], // #404 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #405 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Asserts' + [], // #406 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #407 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Errors' + [], // #408 xdc.runtime.Registry/configNameMap$/'xdc.runtime/Errors'/fields + [], // #409 xdc.runtime.Registry/viewNameMap$ + {}, // #410 xdc.runtime.Startup + [], // #411 xdc.runtime.Startup/$instances + {}, // #412 xdc.runtime.Startup/common$ + [], // #413 xdc.runtime.Startup/configNameMap$ + {}, // #414 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Memory' + [], // #415 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #416 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Diagnostics' + [], // #417 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #418 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Concurrency' + [], // #419 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #420 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Log Events' + [], // #421 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #422 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Asserts' + [], // #423 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #424 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Errors' + [], // #425 xdc.runtime.Startup/configNameMap$/'xdc.runtime/Errors'/fields + [], // #426 xdc.runtime.Startup/firstFxns + [], // #427 xdc.runtime.Startup/lastFxns + [], // #428 xdc.runtime.Startup/sfxnRts + [], // #429 xdc.runtime.Startup/sfxnTab + [], // #430 xdc.runtime.Startup/viewNameMap$ + {}, // #431 xdc.runtime.System + [], // #432 xdc.runtime.System/$instances + {}, // #433 xdc.runtime.Assert.Desc#7 + {}, // #434 xdc.runtime.SysMin + [], // #435 xdc.runtime.SysMin/$instances + {}, // #436 xdc.runtime.SysMin/common$ + [], // #437 xdc.runtime.SysMin/configNameMap$ + {}, // #438 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Memory' + [], // #439 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #440 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Diagnostics' + [], // #441 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #442 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Concurrency' + [], // #443 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #444 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Log Events' + [], // #445 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #446 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Asserts' + [], // #447 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #448 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Errors' + [], // #449 xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Errors'/fields + [], // #450 xdc.runtime.SysMin/viewNameMap$ + {}, // #451 xdc.runtime.System/common$ + [], // #452 xdc.runtime.System/configNameMap$ + {}, // #453 xdc.runtime.System/configNameMap$/'xdc.runtime/Memory' + [], // #454 xdc.runtime.System/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #455 xdc.runtime.System/configNameMap$/'xdc.runtime/Diagnostics' + [], // #456 xdc.runtime.System/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #457 xdc.runtime.System/configNameMap$/'xdc.runtime/Concurrency' + [], // #458 xdc.runtime.System/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #459 xdc.runtime.System/configNameMap$/'xdc.runtime/Log Events' + [], // #460 xdc.runtime.System/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #461 xdc.runtime.System/configNameMap$/'xdc.runtime/Asserts' + [], // #462 xdc.runtime.System/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #463 xdc.runtime.System/configNameMap$/'xdc.runtime/Errors' + [], // #464 xdc.runtime.System/configNameMap$/'xdc.runtime/Errors'/fields + [], // #465 xdc.runtime.System/exitFxns + [], // #466 xdc.runtime.System/viewNameMap$ + {}, // #467 xdc.runtime.Text + [], // #468 xdc.runtime.Text/$instances + [], // #469 xdc.runtime.Text/charTab + {}, // #470 xdc.runtime.Text/common$ + [], // #471 xdc.runtime.Text/configNameMap$ + {}, // #472 xdc.runtime.Text/configNameMap$/'xdc.runtime/Memory' + [], // #473 xdc.runtime.Text/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #474 xdc.runtime.Text/configNameMap$/'xdc.runtime/Diagnostics' + [], // #475 xdc.runtime.Text/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #476 xdc.runtime.Text/configNameMap$/'xdc.runtime/Concurrency' + [], // #477 xdc.runtime.Text/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #478 xdc.runtime.Text/configNameMap$/'xdc.runtime/Log Events' + [], // #479 xdc.runtime.Text/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #480 xdc.runtime.Text/configNameMap$/'xdc.runtime/Asserts' + [], // #481 xdc.runtime.Text/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #482 xdc.runtime.Text/configNameMap$/'xdc.runtime/Errors' + [], // #483 xdc.runtime.Text/configNameMap$/'xdc.runtime/Errors'/fields + [], // #484 xdc.runtime.Text/nodeTab + {}, // #485 xdc.runtime.Text/nodeTab/0 + {}, // #486 xdc.runtime.Text/nodeTab/1 + {}, // #487 xdc.runtime.Text/nodeTab/2 + {}, // #488 xdc.runtime.Text/nodeTab/3 + {}, // #489 xdc.runtime.Text/nodeTab/4 + {}, // #490 xdc.runtime.Text/nodeTab/5 + {}, // #491 xdc.runtime.Text/nodeTab/6 + {}, // #492 xdc.runtime.Text/nodeTab/7 + {}, // #493 xdc.runtime.Text/nodeTab/8 + {}, // #494 xdc.runtime.Text/nodeTab/9 + {}, // #495 xdc.runtime.Text/nodeTab/10 + {}, // #496 xdc.runtime.Text/nodeTab/11 + {}, // #497 xdc.runtime.Text/nodeTab/12 + {}, // #498 xdc.runtime.Text/nodeTab/13 + {}, // #499 xdc.runtime.Text/nodeTab/14 + {}, // #500 xdc.runtime.Text/nodeTab/15 + {}, // #501 xdc.runtime.Text/nodeTab/16 + {}, // #502 xdc.runtime.Text/nodeTab/17 + {}, // #503 xdc.runtime.Text/nodeTab/18 + {}, // #504 xdc.runtime.Text/nodeTab/19 + {}, // #505 xdc.runtime.Text/nodeTab/20 + {}, // #506 xdc.runtime.Text/nodeTab/21 + {}, // #507 xdc.runtime.Text/nodeTab/22 + {}, // #508 xdc.runtime.Text/nodeTab/23 + {}, // #509 xdc.runtime.Text/nodeTab/24 + {}, // #510 xdc.runtime.Text/nodeTab/25 + {}, // #511 xdc.runtime.Text/nodeTab/26 + {}, // #512 xdc.runtime.Text/nodeTab/27 + {}, // #513 xdc.runtime.Text/nodeTab/28 + {}, // #514 xdc.runtime.Text/nodeTab/29 + {}, // #515 xdc.runtime.Text/nodeTab/30 + {}, // #516 xdc.runtime.Text/nodeTab/31 + {}, // #517 xdc.runtime.Text/nodeTab/32 + {}, // #518 xdc.runtime.Text/nodeTab/33 + {}, // #519 xdc.runtime.Text/nodeTab/34 + {}, // #520 xdc.runtime.Text/nodeTab/35 + {}, // #521 xdc.runtime.Text/nodeTab/36 + {}, // #522 xdc.runtime.Text/nodeTab/37 + {}, // #523 xdc.runtime.Text/nodeTab/38 + {}, // #524 xdc.runtime.Text/nodeTab/39 + {}, // #525 xdc.runtime.Text/nodeTab/40 + {}, // #526 xdc.runtime.Text/nodeTab/41 + {}, // #527 xdc.runtime.Text/nodeTab/42 + {}, // #528 xdc.runtime.Text/nodeTab/43 + {}, // #529 xdc.runtime.Text/nodeTab/44 + {}, // #530 xdc.runtime.Text/nodeTab/45 + {}, // #531 xdc.runtime.Text/nodeTab/46 + [], // #532 xdc.runtime.Text/viewNameMap$ + {}, // #533 ti.catalog.arm.cortexm4.tiva.ce.Boot + [], // #534 ti.catalog.arm.cortexm4.tiva.ce.Boot/$instances + {}, // #535 xdc.runtime.Assert.Desc#9 + {}, // #536 xdc.runtime.Assert.Desc#8 + {}, // #537 ti.catalog.arm.cortexm4.tiva.ce.Boot/common$ + [], // #538 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$ + {}, // #539 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Memory' + [], // #540 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #541 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Diagnostics' + [], // #542 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #543 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Concurrency' + [], // #544 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #545 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Log Events' + [], // #546 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #547 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Asserts' + [], // #548 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #549 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Errors' + [], // #550 ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Errors'/fields + [], // #551 ti.catalog.arm.cortexm4.tiva.ce.Boot/viewNameMap$ + {}, // #552 ti.sysbios.knl.Clock + [], // #553 ti.sysbios.knl.Clock/$instances + {}, // #554 xdc.runtime.Assert.Desc#14 + {}, // #555 xdc.runtime.Assert.Desc#13 + {}, // #556 xdc.runtime.Log.EventDesc#15 + {}, // #557 xdc.runtime.Log.EventDesc#14 + {}, // #558 xdc.runtime.Log.EventDesc#13 + {}, // #559 ti.sysbios.family.arm.lm4.Timer + [], // #560 ti.sysbios.family.arm.lm4.Timer/$instances + {}, // #561 ti.sysbios.family.arm.lm4.Timer.Instance#0 + {}, // #562 ti.sysbios.family.arm.lm4.Timer.Instance#0/extFreq + {}, // #563 ti.sysbios.family.arm.m3.Hwi.Params#1 + {}, // #564 ti.sysbios.family.arm.m3.Hwi.Params#1/instance + {}, // #565 ti.sysbios.family.arm.lm4.Timer.Instance#0/instance + {}, // #566 xdc.runtime.Error.Desc#33 + {}, // #567 xdc.runtime.Error.Desc#31 + {}, // #568 xdc.runtime.Error.Desc#34 + {}, // #569 xdc.runtime.Error.Desc#32 + {}, // #570 ti.sysbios.family.arm.lm4.Timer/common$ + [], // #571 ti.sysbios.family.arm.lm4.Timer/configNameMap$ + {}, // #572 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Memory' + [], // #573 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #574 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Diagnostics' + [], // #575 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #576 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Concurrency' + [], // #577 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #578 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Log Events' + [], // #579 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #580 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Asserts' + [], // #581 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #582 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Errors' + [], // #583 ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Errors'/fields + [], // #584 ti.sysbios.family.arm.lm4.Timer/viewNameMap$ + {}, // #585 ti.sysbios.knl.Clock/common$ + [], // #586 ti.sysbios.knl.Clock/configNameMap$ + {}, // #587 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Memory' + [], // #588 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #589 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Diagnostics' + [], // #590 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #591 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Concurrency' + [], // #592 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #593 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Log Events' + [], // #594 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #595 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Asserts' + [], // #596 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #597 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Errors' + [], // #598 ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Errors'/fields + [], // #599 ti.sysbios.knl.Clock/viewNameMap$ + {}, // #600 ti.sysbios.knl.Idle + [], // #601 ti.sysbios.knl.Idle/$instances + {}, // #602 ti.sysbios.knl.Idle/common$ + [], // #603 ti.sysbios.knl.Idle/configNameMap$ + {}, // #604 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Memory' + [], // #605 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #606 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Diagnostics' + [], // #607 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #608 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Concurrency' + [], // #609 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #610 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Log Events' + [], // #611 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #612 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Asserts' + [], // #613 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #614 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Errors' + [], // #615 ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Errors'/fields + [], // #616 ti.sysbios.knl.Idle/coreList + [], // #617 ti.sysbios.knl.Idle/funcList + [], // #618 ti.sysbios.knl.Idle/idleFxns + [], // #619 ti.sysbios.knl.Idle/viewNameMap$ + {}, // #620 ti.sysbios.knl.Intrinsics + [], // #621 ti.sysbios.knl.Intrinsics/$instances + {}, // #622 ti.sysbios.family.arm.m3.IntrinsicsSupport + [], // #623 ti.sysbios.family.arm.m3.IntrinsicsSupport/$instances + {}, // #624 ti.sysbios.family.arm.m3.IntrinsicsSupport/common$ + [], // #625 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$ + {}, // #626 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Memory' + [], // #627 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #628 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Diagnostics' + [], // #629 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #630 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Concurrency' + [], // #631 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #632 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Log Events' + [], // #633 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #634 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Asserts' + [], // #635 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #636 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Errors' + [], // #637 ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Errors'/fields + [], // #638 ti.sysbios.family.arm.m3.IntrinsicsSupport/viewNameMap$ + {}, // #639 ti.sysbios.knl.Intrinsics/common$ + [], // #640 ti.sysbios.knl.Intrinsics/configNameMap$ + {}, // #641 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Memory' + [], // #642 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #643 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Diagnostics' + [], // #644 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #645 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Concurrency' + [], // #646 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #647 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Log Events' + [], // #648 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #649 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Asserts' + [], // #650 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #651 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Errors' + [], // #652 ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Errors'/fields + [], // #653 ti.sysbios.knl.Intrinsics/viewNameMap$ + {}, // #654 ti.sysbios.knl.Queue + [], // #655 ti.sysbios.knl.Queue/$instances + {}, // #656 ti.sysbios.knl.Queue/common$ + [], // #657 ti.sysbios.knl.Queue/configNameMap$ + {}, // #658 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Memory' + [], // #659 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #660 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Diagnostics' + [], // #661 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #662 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Concurrency' + [], // #663 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #664 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Log Events' + [], // #665 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #666 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Asserts' + [], // #667 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #668 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Errors' + [], // #669 ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Errors'/fields + [], // #670 ti.sysbios.knl.Queue/viewNameMap$ + {}, // #671 ti.sysbios.knl.Semaphore + [], // #672 ti.sysbios.knl.Semaphore/$instances + {}, // #673 xdc.runtime.Assert.Desc#23 + {}, // #674 xdc.runtime.Assert.Desc#22 + {}, // #675 xdc.runtime.Assert.Desc#21 + {}, // #676 xdc.runtime.Assert.Desc#24 + {}, // #677 xdc.runtime.Assert.Desc#25 + {}, // #678 xdc.runtime.Log.EventDesc#19 + {}, // #679 xdc.runtime.Log.EventDesc#18 + {}, // #680 ti.sysbios.knl.Semaphore/common$ + [], // #681 ti.sysbios.knl.Semaphore/configNameMap$ + {}, // #682 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Memory' + [], // #683 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #684 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Diagnostics' + [], // #685 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #686 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Concurrency' + [], // #687 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #688 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Log Events' + [], // #689 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #690 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Asserts' + [], // #691 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #692 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Errors' + [], // #693 ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Errors'/fields + [], // #694 ti.sysbios.knl.Semaphore/viewNameMap$ + {}, // #695 ti.sysbios.knl.Swi + [], // #696 ti.sysbios.knl.Swi/$instances + {}, // #697 ti.sysbios.knl.Swi.Instance#0 + {}, // #698 ti.sysbios.knl.Swi.Instance#0/instance + {}, // #699 xdc.runtime.Assert.Desc#27 + {}, // #700 xdc.runtime.Assert.Desc#26 + {}, // #701 xdc.runtime.Log.EventDesc#21 + {}, // #702 xdc.runtime.Log.EventDesc#20 + {}, // #703 xdc.runtime.Log.EventDesc#22 + {}, // #704 ti.sysbios.knl.Swi/common$ + [], // #705 ti.sysbios.knl.Swi/configNameMap$ + {}, // #706 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Memory' + [], // #707 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #708 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Diagnostics' + [], // #709 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #710 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Concurrency' + [], // #711 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #712 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Log Events' + [], // #713 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #714 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Asserts' + [], // #715 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #716 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Errors' + [], // #717 ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Errors'/fields + [], // #718 ti.sysbios.knl.Swi/hooks + [], // #719 ti.sysbios.knl.Swi/viewNameMap$ + {}, // #720 ti.sysbios.knl.Task + [], // #721 ti.sysbios.knl.Task/$instances + {}, // #722 ti.sysbios.knl.Task.Instance#0 + {}, // #723 ti.sysbios.knl.Task.Instance#0/instance + {}, // #724 ti.sysbios.knl.Task.Instance#1 + {}, // #725 ti.sysbios.knl.Task.Instance#1/instance + {}, // #726 xdc.runtime.Assert.Desc#34 + {}, // #727 xdc.runtime.Assert.Desc#32 + {}, // #728 xdc.runtime.Assert.Desc#29 + {}, // #729 xdc.runtime.Assert.Desc#28 + {}, // #730 xdc.runtime.Assert.Desc#33 + {}, // #731 xdc.runtime.Assert.Desc#36 + {}, // #732 xdc.runtime.Assert.Desc#30 + {}, // #733 xdc.runtime.Assert.Desc#35 + {}, // #734 xdc.runtime.Assert.Desc#31 + {}, // #735 xdc.runtime.Error.Desc#10 + {}, // #736 xdc.runtime.Error.Desc#9 + {}, // #737 xdc.runtime.Error.Desc#8 + {}, // #738 xdc.runtime.Log.EventDesc#26 + {}, // #739 xdc.runtime.Log.EventDesc#29 + {}, // #740 xdc.runtime.Log.EventDesc#25 + {}, // #741 xdc.runtime.Log.EventDesc#32 + {}, // #742 xdc.runtime.Log.EventDesc#31 + {}, // #743 xdc.runtime.Log.EventDesc#30 + {}, // #744 xdc.runtime.Log.EventDesc#28 + {}, // #745 xdc.runtime.Log.EventDesc#24 + {}, // #746 xdc.runtime.Log.EventDesc#23 + {}, // #747 xdc.runtime.Log.EventDesc#27 + {}, // #748 ti.sysbios.family.arm.m3.TaskSupport + [], // #749 ti.sysbios.family.arm.m3.TaskSupport/$instances + {}, // #750 ti.sysbios.family.arm.m3.TaskSupport/common$ + [], // #751 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$ + {}, // #752 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Memory' + [], // #753 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #754 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Diagnostics' + [], // #755 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #756 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Concurrency' + [], // #757 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #758 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Log Events' + [], // #759 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #760 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Asserts' + [], // #761 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #762 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Errors' + [], // #763 ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Errors'/fields + [], // #764 ti.sysbios.family.arm.m3.TaskSupport/viewNameMap$ + {}, // #765 ti.sysbios.knl.Task/common$ + [], // #766 ti.sysbios.knl.Task/configNameMap$ + {}, // #767 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Memory' + [], // #768 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #769 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Diagnostics' + [], // #770 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #771 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Concurrency' + [], // #772 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #773 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Log Events' + [], // #774 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #775 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Asserts' + [], // #776 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #777 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Errors' + [], // #778 ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Errors'/fields + [], // #779 ti.sysbios.knl.Task/hooks + [], // #780 ti.sysbios.knl.Task/viewNameMap$ + {}, // #781 ti.sysbios.hal.Hwi + [], // #782 ti.sysbios.hal.Hwi/$instances + {}, // #783 xdc.runtime.Error.Desc#11 + {}, // #784 ti.sysbios.family.arm.m3.Hwi + [], // #785 ti.sysbios.family.arm.m3.Hwi/$instances + {}, // #786 ti.sysbios.family.arm.m3.Hwi.Instance#0 + {}, // #787 ti.sysbios.family.arm.m3.Hwi.Instance#0/instance + {}, // #788 xdc.runtime.Assert.Desc#37 + {}, // #789 xdc.runtime.Error.Desc#16 + {}, // #790 xdc.runtime.Error.Desc#12 + {}, // #791 xdc.runtime.Error.Desc#19 + {}, // #792 xdc.runtime.Error.Desc#22 + {}, // #793 xdc.runtime.Error.Desc#14 + {}, // #794 xdc.runtime.Error.Desc#17 + {}, // #795 xdc.runtime.Error.Desc#13 + {}, // #796 xdc.runtime.Error.Desc#18 + {}, // #797 xdc.runtime.Error.Desc#15 + {}, // #798 xdc.runtime.Error.Desc#23 + {}, // #799 xdc.runtime.Error.Desc#21 + {}, // #800 xdc.runtime.Error.Desc#20 + {}, // #801 xdc.runtime.Log.EventDesc#34 + {}, // #802 xdc.runtime.Log.EventDesc#33 + {}, // #803 ti.sysbios.family.arm.m3.Hwi/common$ + [], // #804 ti.sysbios.family.arm.m3.Hwi/configNameMap$ + {}, // #805 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Memory' + [], // #806 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #807 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Diagnostics' + [], // #808 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #809 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Concurrency' + [], // #810 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #811 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Log Events' + [], // #812 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #813 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Asserts' + [], // #814 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #815 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Errors' + [], // #816 ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Errors'/fields + [], // #817 ti.sysbios.family.arm.m3.Hwi/excContextBuffers + [], // #818 ti.sysbios.family.arm.m3.Hwi/excHookFuncs + [], // #819 ti.sysbios.family.arm.m3.Hwi/excStackBuffers + [], // #820 ti.sysbios.family.arm.m3.Hwi/hooks + [], // #821 ti.sysbios.family.arm.m3.Hwi/intAffinity + [], // #822 ti.sysbios.family.arm.m3.Hwi/interrupt + {}, // #823 ti.sysbios.family.arm.m3.Hwi/interrupt/0 + {}, // #824 ti.sysbios.family.arm.m3.Hwi/interrupt/1 + {}, // #825 ti.sysbios.family.arm.m3.Hwi/interrupt/2 + {}, // #826 ti.sysbios.family.arm.m3.Hwi/interrupt/3 + {}, // #827 ti.sysbios.family.arm.m3.Hwi/interrupt/4 + {}, // #828 ti.sysbios.family.arm.m3.Hwi/interrupt/5 + {}, // #829 ti.sysbios.family.arm.m3.Hwi/interrupt/6 + {}, // #830 ti.sysbios.family.arm.m3.Hwi/interrupt/7 + {}, // #831 ti.sysbios.family.arm.m3.Hwi/interrupt/8 + {}, // #832 ti.sysbios.family.arm.m3.Hwi/interrupt/9 + {}, // #833 ti.sysbios.family.arm.m3.Hwi/interrupt/10 + {}, // #834 ti.sysbios.family.arm.m3.Hwi/interrupt/11 + {}, // #835 ti.sysbios.family.arm.m3.Hwi/interrupt/12 + {}, // #836 ti.sysbios.family.arm.m3.Hwi/interrupt/13 + {}, // #837 ti.sysbios.family.arm.m3.Hwi/interrupt/14 + {}, // #838 ti.sysbios.family.arm.m3.Hwi/interrupt/15 + {}, // #839 ti.sysbios.family.arm.m3.Hwi/interrupt/16 + {}, // #840 ti.sysbios.family.arm.m3.Hwi/interrupt/17 + {}, // #841 ti.sysbios.family.arm.m3.Hwi/interrupt/18 + {}, // #842 ti.sysbios.family.arm.m3.Hwi/interrupt/19 + {}, // #843 ti.sysbios.family.arm.m3.Hwi/interrupt/20 + {}, // #844 ti.sysbios.family.arm.m3.Hwi/interrupt/21 + {}, // #845 ti.sysbios.family.arm.m3.Hwi/interrupt/22 + {}, // #846 ti.sysbios.family.arm.m3.Hwi/interrupt/23 + {}, // #847 ti.sysbios.family.arm.m3.Hwi/interrupt/24 + {}, // #848 ti.sysbios.family.arm.m3.Hwi/interrupt/25 + {}, // #849 ti.sysbios.family.arm.m3.Hwi/interrupt/26 + {}, // #850 ti.sysbios.family.arm.m3.Hwi/interrupt/27 + {}, // #851 ti.sysbios.family.arm.m3.Hwi/interrupt/28 + {}, // #852 ti.sysbios.family.arm.m3.Hwi/interrupt/29 + {}, // #853 ti.sysbios.family.arm.m3.Hwi/interrupt/30 + {}, // #854 ti.sysbios.family.arm.m3.Hwi/interrupt/31 + {}, // #855 ti.sysbios.family.arm.m3.Hwi/interrupt/32 + {}, // #856 ti.sysbios.family.arm.m3.Hwi/interrupt/33 + {}, // #857 ti.sysbios.family.arm.m3.Hwi/interrupt/34 + {}, // #858 ti.sysbios.family.arm.m3.Hwi/interrupt/35 + {}, // #859 ti.sysbios.family.arm.m3.Hwi/interrupt/36 + {}, // #860 ti.sysbios.family.arm.m3.Hwi/interrupt/37 + {}, // #861 ti.sysbios.family.arm.m3.Hwi/interrupt/38 + {}, // #862 ti.sysbios.family.arm.m3.Hwi/interrupt/39 + {}, // #863 ti.sysbios.family.arm.m3.Hwi/interrupt/40 + {}, // #864 ti.sysbios.family.arm.m3.Hwi/interrupt/41 + {}, // #865 ti.sysbios.family.arm.m3.Hwi/interrupt/42 + {}, // #866 ti.sysbios.family.arm.m3.Hwi/interrupt/43 + {}, // #867 ti.sysbios.family.arm.m3.Hwi/interrupt/44 + {}, // #868 ti.sysbios.family.arm.m3.Hwi/interrupt/45 + {}, // #869 ti.sysbios.family.arm.m3.Hwi/interrupt/46 + {}, // #870 ti.sysbios.family.arm.m3.Hwi/interrupt/47 + {}, // #871 ti.sysbios.family.arm.m3.Hwi/interrupt/48 + {}, // #872 ti.sysbios.family.arm.m3.Hwi/interrupt/49 + {}, // #873 ti.sysbios.family.arm.m3.Hwi/interrupt/50 + {}, // #874 ti.sysbios.family.arm.m3.Hwi/interrupt/51 + {}, // #875 ti.sysbios.family.arm.m3.Hwi/interrupt/52 + {}, // #876 ti.sysbios.family.arm.m3.Hwi/interrupt/53 + {}, // #877 ti.sysbios.family.arm.m3.Hwi/interrupt/54 + {}, // #878 ti.sysbios.family.arm.m3.Hwi/interrupt/55 + {}, // #879 ti.sysbios.family.arm.m3.Hwi/interrupt/56 + {}, // #880 ti.sysbios.family.arm.m3.Hwi/interrupt/57 + {}, // #881 ti.sysbios.family.arm.m3.Hwi/interrupt/58 + {}, // #882 ti.sysbios.family.arm.m3.Hwi/interrupt/59 + {}, // #883 ti.sysbios.family.arm.m3.Hwi/interrupt/60 + {}, // #884 ti.sysbios.family.arm.m3.Hwi/interrupt/61 + {}, // #885 ti.sysbios.family.arm.m3.Hwi/interrupt/62 + {}, // #886 ti.sysbios.family.arm.m3.Hwi/interrupt/63 + {}, // #887 ti.sysbios.family.arm.m3.Hwi/interrupt/64 + {}, // #888 ti.sysbios.family.arm.m3.Hwi/interrupt/65 + {}, // #889 ti.sysbios.family.arm.m3.Hwi/interrupt/66 + {}, // #890 ti.sysbios.family.arm.m3.Hwi/interrupt/67 + {}, // #891 ti.sysbios.family.arm.m3.Hwi/interrupt/68 + {}, // #892 ti.sysbios.family.arm.m3.Hwi/interrupt/69 + {}, // #893 ti.sysbios.family.arm.m3.Hwi/interrupt/70 + {}, // #894 ti.sysbios.family.arm.m3.Hwi/interrupt/71 + {}, // #895 ti.sysbios.family.arm.m3.Hwi/interrupt/72 + {}, // #896 ti.sysbios.family.arm.m3.Hwi/interrupt/73 + {}, // #897 ti.sysbios.family.arm.m3.Hwi/interrupt/74 + {}, // #898 ti.sysbios.family.arm.m3.Hwi/interrupt/75 + {}, // #899 ti.sysbios.family.arm.m3.Hwi/interrupt/76 + {}, // #900 ti.sysbios.family.arm.m3.Hwi/interrupt/77 + {}, // #901 ti.sysbios.family.arm.m3.Hwi/interrupt/78 + {}, // #902 ti.sysbios.family.arm.m3.Hwi/interrupt/79 + {}, // #903 ti.sysbios.family.arm.m3.Hwi/interrupt/80 + {}, // #904 ti.sysbios.family.arm.m3.Hwi/interrupt/81 + {}, // #905 ti.sysbios.family.arm.m3.Hwi/interrupt/82 + {}, // #906 ti.sysbios.family.arm.m3.Hwi/interrupt/83 + {}, // #907 ti.sysbios.family.arm.m3.Hwi/interrupt/84 + {}, // #908 ti.sysbios.family.arm.m3.Hwi/interrupt/85 + {}, // #909 ti.sysbios.family.arm.m3.Hwi/interrupt/86 + {}, // #910 ti.sysbios.family.arm.m3.Hwi/interrupt/87 + {}, // #911 ti.sysbios.family.arm.m3.Hwi/interrupt/88 + {}, // #912 ti.sysbios.family.arm.m3.Hwi/interrupt/89 + {}, // #913 ti.sysbios.family.arm.m3.Hwi/interrupt/90 + {}, // #914 ti.sysbios.family.arm.m3.Hwi/interrupt/91 + {}, // #915 ti.sysbios.family.arm.m3.Hwi/interrupt/92 + {}, // #916 ti.sysbios.family.arm.m3.Hwi/interrupt/93 + {}, // #917 ti.sysbios.family.arm.m3.Hwi/interrupt/94 + {}, // #918 ti.sysbios.family.arm.m3.Hwi/interrupt/95 + {}, // #919 ti.sysbios.family.arm.m3.Hwi/interrupt/96 + {}, // #920 ti.sysbios.family.arm.m3.Hwi/interrupt/97 + {}, // #921 ti.sysbios.family.arm.m3.Hwi/interrupt/98 + {}, // #922 ti.sysbios.family.arm.m3.Hwi/interrupt/99 + {}, // #923 ti.sysbios.family.arm.m3.Hwi/interrupt/100 + {}, // #924 ti.sysbios.family.arm.m3.Hwi/interrupt/101 + {}, // #925 ti.sysbios.family.arm.m3.Hwi/interrupt/102 + {}, // #926 ti.sysbios.family.arm.m3.Hwi/interrupt/103 + {}, // #927 ti.sysbios.family.arm.m3.Hwi/interrupt/104 + {}, // #928 ti.sysbios.family.arm.m3.Hwi/interrupt/105 + {}, // #929 ti.sysbios.family.arm.m3.Hwi/interrupt/106 + {}, // #930 ti.sysbios.family.arm.m3.Hwi/interrupt/107 + {}, // #931 ti.sysbios.family.arm.m3.Hwi/interrupt/108 + {}, // #932 ti.sysbios.family.arm.m3.Hwi/interrupt/109 + {}, // #933 ti.sysbios.family.arm.m3.Hwi/interrupt/110 + {}, // #934 ti.sysbios.family.arm.m3.Hwi/interrupt/111 + {}, // #935 ti.sysbios.family.arm.m3.Hwi/interrupt/112 + {}, // #936 ti.sysbios.family.arm.m3.Hwi/interrupt/113 + {}, // #937 ti.sysbios.family.arm.m3.Hwi/interrupt/114 + {}, // #938 ti.sysbios.family.arm.m3.Hwi/interrupt/115 + {}, // #939 ti.sysbios.family.arm.m3.Hwi/interrupt/116 + {}, // #940 ti.sysbios.family.arm.m3.Hwi/interrupt/117 + {}, // #941 ti.sysbios.family.arm.m3.Hwi/interrupt/118 + {}, // #942 ti.sysbios.family.arm.m3.Hwi/interrupt/119 + {}, // #943 ti.sysbios.family.arm.m3.Hwi/interrupt/120 + {}, // #944 ti.sysbios.family.arm.m3.Hwi/interrupt/121 + {}, // #945 ti.sysbios.family.arm.m3.Hwi/interrupt/122 + {}, // #946 ti.sysbios.family.arm.m3.Hwi/interrupt/123 + {}, // #947 ti.sysbios.family.arm.m3.Hwi/interrupt/124 + {}, // #948 ti.sysbios.family.arm.m3.Hwi/interrupt/125 + {}, // #949 ti.sysbios.family.arm.m3.Hwi/interrupt/126 + {}, // #950 ti.sysbios.family.arm.m3.Hwi/interrupt/127 + {}, // #951 ti.sysbios.family.arm.m3.Hwi/interrupt/128 + {}, // #952 ti.sysbios.family.arm.m3.Hwi/interrupt/129 + {}, // #953 ti.sysbios.family.arm.m3.Hwi/interrupt/130 + {}, // #954 ti.sysbios.family.arm.m3.Hwi/interrupt/131 + {}, // #955 ti.sysbios.family.arm.m3.Hwi/interrupt/132 + {}, // #956 ti.sysbios.family.arm.m3.Hwi/interrupt/133 + {}, // #957 ti.sysbios.family.arm.m3.Hwi/interrupt/134 + {}, // #958 ti.sysbios.family.arm.m3.Hwi/interrupt/135 + {}, // #959 ti.sysbios.family.arm.m3.Hwi/interrupt/136 + {}, // #960 ti.sysbios.family.arm.m3.Hwi/interrupt/137 + {}, // #961 ti.sysbios.family.arm.m3.Hwi/interrupt/138 + {}, // #962 ti.sysbios.family.arm.m3.Hwi/interrupt/139 + {}, // #963 ti.sysbios.family.arm.m3.Hwi/interrupt/140 + {}, // #964 ti.sysbios.family.arm.m3.Hwi/interrupt/141 + {}, // #965 ti.sysbios.family.arm.m3.Hwi/interrupt/142 + {}, // #966 ti.sysbios.family.arm.m3.Hwi/interrupt/143 + {}, // #967 ti.sysbios.family.arm.m3.Hwi/interrupt/144 + {}, // #968 ti.sysbios.family.arm.m3.Hwi/interrupt/145 + {}, // #969 ti.sysbios.family.arm.m3.Hwi/interrupt/146 + {}, // #970 ti.sysbios.family.arm.m3.Hwi/interrupt/147 + {}, // #971 ti.sysbios.family.arm.m3.Hwi/interrupt/148 + {}, // #972 ti.sysbios.family.arm.m3.Hwi/interrupt/149 + {}, // #973 ti.sysbios.family.arm.m3.Hwi/interrupt/150 + {}, // #974 ti.sysbios.family.arm.m3.Hwi/interrupt/151 + {}, // #975 ti.sysbios.family.arm.m3.Hwi/interrupt/152 + {}, // #976 ti.sysbios.family.arm.m3.Hwi/interrupt/153 + {}, // #977 ti.sysbios.family.arm.m3.Hwi/interrupt/154 + {}, // #978 ti.sysbios.family.arm.m3.Hwi/interrupt/155 + {}, // #979 ti.sysbios.family.arm.m3.Hwi/interrupt/156 + {}, // #980 ti.sysbios.family.arm.m3.Hwi/interrupt/157 + {}, // #981 ti.sysbios.family.arm.m3.Hwi/interrupt/158 + {}, // #982 ti.sysbios.family.arm.m3.Hwi/interrupt/159 + {}, // #983 ti.sysbios.family.arm.m3.Hwi/interrupt/160 + {}, // #984 ti.sysbios.family.arm.m3.Hwi/interrupt/161 + {}, // #985 ti.sysbios.family.arm.m3.Hwi/interrupt/162 + {}, // #986 ti.sysbios.family.arm.m3.Hwi/interrupt/163 + {}, // #987 ti.sysbios.family.arm.m3.Hwi/interrupt/164 + {}, // #988 ti.sysbios.family.arm.m3.Hwi/interrupt/165 + {}, // #989 ti.sysbios.family.arm.m3.Hwi/interrupt/166 + {}, // #990 ti.sysbios.family.arm.m3.Hwi/interrupt/167 + {}, // #991 ti.sysbios.family.arm.m3.Hwi/interrupt/168 + {}, // #992 ti.sysbios.family.arm.m3.Hwi/interrupt/169 + {}, // #993 ti.sysbios.family.arm.m3.Hwi/interrupt/170 + {}, // #994 ti.sysbios.family.arm.m3.Hwi/interrupt/171 + {}, // #995 ti.sysbios.family.arm.m3.Hwi/interrupt/172 + {}, // #996 ti.sysbios.family.arm.m3.Hwi/interrupt/173 + {}, // #997 ti.sysbios.family.arm.m3.Hwi/interrupt/174 + {}, // #998 ti.sysbios.family.arm.m3.Hwi/interrupt/175 + {}, // #999 ti.sysbios.family.arm.m3.Hwi/interrupt/176 + {}, // #1000 ti.sysbios.family.arm.m3.Hwi/interrupt/177 + {}, // #1001 ti.sysbios.family.arm.m3.Hwi/interrupt/178 + {}, // #1002 ti.sysbios.family.arm.m3.Hwi/interrupt/179 + {}, // #1003 ti.sysbios.family.arm.m3.Hwi/interrupt/180 + {}, // #1004 ti.sysbios.family.arm.m3.Hwi/interrupt/181 + {}, // #1005 ti.sysbios.family.arm.m3.Hwi/interrupt/182 + {}, // #1006 ti.sysbios.family.arm.m3.Hwi/interrupt/183 + {}, // #1007 ti.sysbios.family.arm.m3.Hwi/interrupt/184 + {}, // #1008 ti.sysbios.family.arm.m3.Hwi/interrupt/185 + {}, // #1009 ti.sysbios.family.arm.m3.Hwi/interrupt/186 + {}, // #1010 ti.sysbios.family.arm.m3.Hwi/interrupt/187 + {}, // #1011 ti.sysbios.family.arm.m3.Hwi/interrupt/188 + {}, // #1012 ti.sysbios.family.arm.m3.Hwi/interrupt/189 + {}, // #1013 ti.sysbios.family.arm.m3.Hwi/interrupt/190 + {}, // #1014 ti.sysbios.family.arm.m3.Hwi/interrupt/191 + {}, // #1015 ti.sysbios.family.arm.m3.Hwi/interrupt/192 + {}, // #1016 ti.sysbios.family.arm.m3.Hwi/interrupt/193 + {}, // #1017 ti.sysbios.family.arm.m3.Hwi/interrupt/194 + {}, // #1018 ti.sysbios.family.arm.m3.Hwi/interrupt/195 + {}, // #1019 ti.sysbios.family.arm.m3.Hwi/interrupt/196 + {}, // #1020 ti.sysbios.family.arm.m3.Hwi/interrupt/197 + {}, // #1021 ti.sysbios.family.arm.m3.Hwi/interrupt/198 + {}, // #1022 ti.sysbios.family.arm.m3.Hwi/interrupt/199 + {}, // #1023 ti.sysbios.family.arm.m3.Hwi/interrupt/200 + {}, // #1024 ti.sysbios.family.arm.m3.Hwi/interrupt/201 + {}, // #1025 ti.sysbios.family.arm.m3.Hwi/interrupt/202 + {}, // #1026 ti.sysbios.family.arm.m3.Hwi/interrupt/203 + {}, // #1027 ti.sysbios.family.arm.m3.Hwi/interrupt/204 + {}, // #1028 ti.sysbios.family.arm.m3.Hwi/interrupt/205 + {}, // #1029 ti.sysbios.family.arm.m3.Hwi/interrupt/206 + {}, // #1030 ti.sysbios.family.arm.m3.Hwi/interrupt/207 + {}, // #1031 ti.sysbios.family.arm.m3.Hwi/interrupt/208 + {}, // #1032 ti.sysbios.family.arm.m3.Hwi/interrupt/209 + {}, // #1033 ti.sysbios.family.arm.m3.Hwi/interrupt/210 + {}, // #1034 ti.sysbios.family.arm.m3.Hwi/interrupt/211 + {}, // #1035 ti.sysbios.family.arm.m3.Hwi/interrupt/212 + {}, // #1036 ti.sysbios.family.arm.m3.Hwi/interrupt/213 + {}, // #1037 ti.sysbios.family.arm.m3.Hwi/interrupt/214 + {}, // #1038 ti.sysbios.family.arm.m3.Hwi/interrupt/215 + {}, // #1039 ti.sysbios.family.arm.m3.Hwi/nvicCCR + [], // #1040 ti.sysbios.family.arm.m3.Hwi/viewNameMap$ + {}, // #1041 ti.sysbios.hal.Hwi/common$ + [], // #1042 ti.sysbios.hal.Hwi/configNameMap$ + {}, // #1043 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Memory' + [], // #1044 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #1045 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Diagnostics' + [], // #1046 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #1047 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Concurrency' + [], // #1048 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #1049 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Log Events' + [], // #1050 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #1051 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Asserts' + [], // #1052 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #1053 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Errors' + [], // #1054 ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Errors'/fields + [], // #1055 ti.sysbios.hal.Hwi/viewNameMap$ + {}, // #1056 ti.sysbios.BIOS + [], // #1057 ti.sysbios.BIOS/$instances + {}, // #1058 ti.sysbios.BIOS/common$ + [], // #1059 ti.sysbios.BIOS/configNameMap$ + {}, // #1060 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Memory' + [], // #1061 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Memory'/fields + {}, // #1062 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Diagnostics' + [], // #1063 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Diagnostics'/fields + {}, // #1064 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Concurrency' + [], // #1065 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Concurrency'/fields + {}, // #1066 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Log Events' + [], // #1067 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Log Events'/fields + {}, // #1068 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Asserts' + [], // #1069 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Asserts'/fields + {}, // #1070 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Errors' + [], // #1071 ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Errors'/fields + {}, // #1072 ti.sysbios.BIOS/cpuFreq + [], // #1073 ti.sysbios.BIOS/startupFxns + [], // #1074 ti.sysbios.BIOS/viewNameMap$ + {}, // #1075 + {}, // #1076 + {}, // #1077 + {}, // #1078 + {}, // #1079 + {}, // #1080 + {}, // #1081 ti.targets.arm.elf.M4F + [], // #1082 ti.targets.arm.elf.M4F/$instances + {}, // #1083 ti.targets.arm.elf.M4F/ar + {}, // #1084 ti.targets.arm.elf.M4F/arOpts + {}, // #1085 ti.targets.arm.elf.M4F/asm + {}, // #1086 ti.targets.arm.elf.M4F/asmOpts + {}, // #1087 ti.targets.arm.elf.M4F/cc + {}, // #1088 ti.targets.arm.elf.M4F/ccConfigOpts + {}, // #1089 ti.targets.arm.elf.M4F/ccOpts + [], // #1090 ti.targets.arm.elf.M4F/compatibleSuffixes + {}, // #1091 ti.targets.arm.elf.M4F/debugGen + [], // #1092 ti.targets.arm.elf.M4F/extensions + {}, // #1093 ti.targets.arm.elf.M4F/extensions/'.sem4fe' + {}, // #1094 ti.targets.arm.elf.M4F/extensions/'.sem4f' + {}, // #1095 ti.targets.arm.elf.M4F/extensions/'.sv7M4' + {}, // #1096 ti.targets.arm.elf.M4F/extensions/'.sv7M' + {}, // #1097 ti.targets.arm.elf.M4F/extensions/'.asm' + {}, // #1098 ti.targets.arm.elf.M4F/extensions/'.c' + {}, // #1099 ti.targets.arm.elf.M4F/extensions/'.cpp' + {}, // #1100 ti.targets.arm.elf.M4F/extensions/'.cxx' + {}, // #1101 ti.targets.arm.elf.M4F/extensions/'.C' + {}, // #1102 ti.targets.arm.elf.M4F/extensions/'.cc' + {}, // #1103 ti.targets.arm.elf.M4F/lnk + {}, // #1104 ti.targets.arm.elf.M4F/lnkOpts + {}, // #1105 ti.targets.arm.elf.M4F/model + [], // #1106 ti.targets.arm.elf.M4F/platforms + [], // #1107 ti.targets.arm.elf.M4F/profiles + {}, // #1108 ti.targets.arm.elf.M4F/profiles/'debug' + {}, // #1109 ti.targets.arm.elf.M4F/profiles/'debug'/compileOpts + [], // #1110 ti.targets.arm.elf.M4F/profiles/'debug'/filters + {}, // #1111 ti.targets.arm.elf.M4F/profiles/'release' + {}, // #1112 ti.targets.arm.elf.M4F/profiles/'release'/compileOpts + [], // #1113 ti.targets.arm.elf.M4F/profiles/'release'/filters + {}, // #1114 ti.targets.arm.elf.M4F/profiles/'profile' + {}, // #1115 ti.targets.arm.elf.M4F/profiles/'profile'/compileOpts + [], // #1116 ti.targets.arm.elf.M4F/profiles/'profile'/filters + {}, // #1117 ti.targets.arm.elf.M4F/profiles/'coverage' + {}, // #1118 ti.targets.arm.elf.M4F/profiles/'coverage'/compileOpts + [], // #1119 ti.targets.arm.elf.M4F/profiles/'coverage'/filters + [], // #1120 ti.targets.arm.elf.M4F/sectMap + [], // #1121 ti.targets.arm.elf.M4F/splitMap + {}, // #1122 ti.targets.arm.elf.M4F/stdTypes + {}, // #1123 ti.targets.arm.elf.M4F/stdTypes/t_Char + {}, // #1124 ti.targets.arm.elf.M4F/stdTypes/t_Double + {}, // #1125 ti.targets.arm.elf.M4F/stdTypes/t_Float + {}, // #1126 ti.targets.arm.elf.M4F/stdTypes/t_Fxn + {}, // #1127 ti.targets.arm.elf.M4F/stdTypes/t_IArg + {}, // #1128 ti.targets.arm.elf.M4F/stdTypes/t_Int + {}, // #1129 ti.targets.arm.elf.M4F/stdTypes/t_Int16 + {}, // #1130 ti.targets.arm.elf.M4F/stdTypes/t_Int32 + {}, // #1131 ti.targets.arm.elf.M4F/stdTypes/t_Int40 + {}, // #1132 ti.targets.arm.elf.M4F/stdTypes/t_Int64 + {}, // #1133 ti.targets.arm.elf.M4F/stdTypes/t_Int8 + {}, // #1134 ti.targets.arm.elf.M4F/stdTypes/t_LDouble + {}, // #1135 ti.targets.arm.elf.M4F/stdTypes/t_LLong + {}, // #1136 ti.targets.arm.elf.M4F/stdTypes/t_Long + {}, // #1137 ti.targets.arm.elf.M4F/stdTypes/t_Ptr + {}, // #1138 ti.targets.arm.elf.M4F/stdTypes/t_Short + {}, // #1139 ti.targets.arm.elf.M4F/stdTypes/t_Size + {}, // #1140 ti.targets.arm.elf.M4F/vers + [], // #1141 ti.targets.arm.elf.M4F/versionMap +] + +__o = __obj[0] + __o['$modules'] = __obj[1.0] + __o['build'] = __obj[1075.0] + +__o = __obj[1] + __o['#0'] = __obj[2.0] + __o['#32770'] = __obj[157.0] + __o['#32771'] = __obj[194.0] + __o['#32772'] = __obj[212.0] + __o['#32773'] = __obj[230.0] + __o['#32774'] = __obj[247.0] + __o['#32775'] = __obj[267.0] + __o['#32776'] = __obj[284.0] + __o['#32777'] = __obj[313.0] + __o['#32778'] = __obj[330.0] + __o['#32779'] = __obj[393.0] + __o['#32780'] = __obj[410.0] + __o['#32781'] = __obj[431.0] + __o['#32782'] = __obj[434.0] + __o['#32783'] = __obj[467.0] + __o['#32789'] = __obj[533.0] + __o['#32792'] = __obj[552.0] + __o['#32793'] = __obj[600.0] + __o['#32794'] = __obj[620.0] + __o['#32795'] = __obj[654.0] + __o['#32796'] = __obj[671.0] + __o['#32797'] = __obj[695.0] + __o['#32798'] = __obj[720.0] + __o['#32800'] = __obj[781.0] + __o['#32801'] = __obj[1056.0] + __o['#32805'] = __obj[784.0] + __o['#32806'] = __obj[622.0] + __o['#32807'] = __obj[748.0] + __o['#32809'] = __obj[162.0] + __o['#32810'] = __obj[341.0] + __o['#32812'] = __obj[332.0] + __o['#32814'] = __obj[559.0] + __o['ti.catalog.arm.cortexm4.tiva.ce.Boot'] = __obj[533.0] + __o['ti.sysbios.BIOS'] = __obj[1056.0] + __o['ti.sysbios.family.arm.lm4.Timer'] = __obj[559.0] + __o['ti.sysbios.family.arm.m3.Hwi'] = __obj[784.0] + __o['ti.sysbios.family.arm.m3.IntrinsicsSupport'] = __obj[622.0] + __o['ti.sysbios.family.arm.m3.TaskSupport'] = __obj[748.0] + __o['ti.sysbios.gates.GateHwi'] = __obj[162.0] + __o['ti.sysbios.gates.GateMutex'] = __obj[341.0] + __o['ti.sysbios.hal.Hwi'] = __obj[781.0] + __o['ti.sysbios.heaps.HeapMem'] = __obj[332.0] + __o['ti.sysbios.knl.Clock'] = __obj[552.0] + __o['ti.sysbios.knl.Idle'] = __obj[600.0] + __o['ti.sysbios.knl.Intrinsics'] = __obj[620.0] + __o['ti.sysbios.knl.Queue'] = __obj[654.0] + __o['ti.sysbios.knl.Semaphore'] = __obj[671.0] + __o['ti.sysbios.knl.Swi'] = __obj[695.0] + __o['ti.sysbios.knl.Task'] = __obj[720.0] + __o['ti.tirtos.utils.UARTMon'] = __obj[2.0] + __o['xdc.runtime.Assert'] = __obj[157.0] + __o['xdc.runtime.Core'] = __obj[194.0] + __o['xdc.runtime.Defaults'] = __obj[212.0] + __o['xdc.runtime.Diags'] = __obj[230.0] + __o['xdc.runtime.Error'] = __obj[247.0] + __o['xdc.runtime.Gate'] = __obj[267.0] + __o['xdc.runtime.Log'] = __obj[284.0] + __o['xdc.runtime.Main'] = __obj[313.0] + __o['xdc.runtime.Memory'] = __obj[330.0] + __o['xdc.runtime.Registry'] = __obj[393.0] + __o['xdc.runtime.Startup'] = __obj[410.0] + __o['xdc.runtime.SysMin'] = __obj[434.0] + __o['xdc.runtime.System'] = __obj[431.0] + __o['xdc.runtime.Text'] = __obj[467.0] + +__o = __obj[2] // ti.tirtos.utils.UARTMon + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[3.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon', 'UTF-8')) + __o['Module__diagsEnabled'] = 0 + __o['Module__diagsIncluded'] = 0 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 0 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['baudRate'] = 9600 + __o['common$'] = __obj[4.0] + __o['configNameMap$'] = __obj[5.0] + __o['index'] = 0 + __o['priority'] = 1 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[18.0] + __o['stackSize'] = 1024 + __o['viewNameMap$'] = __obj[156.0] + +__o = __obj[3] // ti.tirtos.utils.UARTMon/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2F%24instances', 'UTF-8')) + +__o = __obj[4] // ti.tirtos.utils.UARTMon/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = null + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.STATIC_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = false + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[5] // ti.tirtos.utils.UARTMon/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[6.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[8.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[10.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[12.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[14.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[16.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[6] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[7.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[7] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[8] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[9.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[9] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[10] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[11.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[11] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[12] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[13.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[13] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[14] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[15.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[15] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[16] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[17.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[17] // ti.tirtos.utils.UARTMon/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[18] // xdc.rov.ViewInfo.Instance#20 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2320', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[154.0] + +__o = __obj[19] // xdc.rov.ViewInfo + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[20.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo', 'UTF-8')) + +__o = __obj[20] // xdc.rov.ViewInfo/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo%2F%24instances', 'UTF-8')) + __o['0'] = __obj[21.0] + __o['1'] = __obj[24.0] + __o['2'] = __obj[28.0] + __o['3'] = __obj[31.0] + __o['4'] = __obj[34.0] + __o['5'] = __obj[38.0] + __o['6'] = __obj[42.0] + __o['7'] = __obj[46.0] + __o['8'] = __obj[49.0] + __o['9'] = __obj[52.0] + __o['10'] = __obj[56.0] + __o['11'] = __obj[59.0] + __o['12'] = __obj[62.0] + __o['13'] = __obj[66.0] + __o['14'] = __obj[69.0] + __o['15'] = __obj[72.0] + __o['16'] = __obj[77.0] + __o['17'] = __obj[84.0] + __o['18'] = __obj[88.0] + __o['19'] = __obj[94.0] + __o['20'] = __obj[18.0] + __o['21'] = __obj[99.0] + __o['22'] = __obj[102.0] + __o['23'] = __obj[105.0] + __o['24'] = __obj[108.0] + __o['25'] = __obj[111.0] + __o['26'] = __obj[115.0] + __o['27'] = __obj[118.0] + __o['28'] = __obj[121.0] + __o['29'] = __obj[124.0] + __o['30'] = __obj[128.0] + __o['31'] = __obj[133.0] + __o['32'] = __obj[137.0] + __o['33'] = __obj[142.0] + __o['34'] = __obj[146.0] + __o['35'] = __obj[151.0] + +__o = __obj[21] // xdc.rov.ViewInfo.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%230', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[22.0] + +__o = __obj[22] // xdc.rov.ViewInfo.Instance#0/viewMap + __o.$keys = [] + __o.push(__o['DiagsMasks'] = __obj[23.0]); __o.$keys.push('DiagsMasks') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%230%2FviewMap', 'UTF-8')) + +__o = __obj[23] // xdc.rov.ViewInfo.Instance#0/viewMap/'DiagsMasks' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%230%2FviewMap%2F%27DiagsMasks%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DiagsMaskView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.TREE_TABLE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDiagsMasks', 'UTF-8')) + +__o = __obj[24] // xdc.rov.ViewInfo.Instance#1 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%231', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[25.0] + +__o = __obj[25] // xdc.rov.ViewInfo.Instance#1/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[26.0]); __o.$keys.push('Basic') + __o.push(__o['Records'] = __obj[27.0]); __o.$keys.push('Records') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%231%2FviewMap', 'UTF-8')) + +__o = __obj[26] // xdc.rov.ViewInfo.Instance#1/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%231%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[27] // xdc.rov.ViewInfo.Instance#1/viewMap/'Records' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%231%2FviewMap%2F%27Records%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('RecordView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitRecords', 'UTF-8')) + +__o = __obj[28] // xdc.rov.ViewInfo.Instance#2 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%232', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[29.0] + +__o = __obj[29] // xdc.rov.ViewInfo.Instance#2/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[30.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%232%2FviewMap', 'UTF-8')) + +__o = __obj[30] // xdc.rov.ViewInfo.Instance#2/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%232%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[31] // xdc.rov.ViewInfo.Instance#3 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%233', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[32.0] + +__o = __obj[32] // xdc.rov.ViewInfo.Instance#3/viewMap + __o.$keys = [] + __o.push(__o['Registered Modules'] = __obj[33.0]); __o.$keys.push('Registered Modules') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%233%2FviewMap', 'UTF-8')) + +__o = __obj[33] // xdc.rov.ViewInfo.Instance#3/viewMap/'Registered Modules' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%233%2FviewMap%2F%27Registered+Modules%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('RegisteredModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitRegisteredModules', 'UTF-8')) + +__o = __obj[34] // xdc.rov.ViewInfo.Instance#4 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%234', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[35.0] + +__o = __obj[35] // xdc.rov.ViewInfo.Instance#4/viewMap + __o.$keys = [] + __o.push(__o['Module'] = __obj[36.0]); __o.$keys.push('Module') + __o.push(__o['Startup State'] = __obj[37.0]); __o.$keys.push('Startup State') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%234%2FviewMap', 'UTF-8')) + +__o = __obj[36] // xdc.rov.ViewInfo.Instance#4/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%234%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[37] // xdc.rov.ViewInfo.Instance#4/viewMap/'Startup State' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%234%2FviewMap%2F%27Startup+State%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('StartupStateView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitStartupState', 'UTF-8')) + +__o = __obj[38] // xdc.rov.ViewInfo.Instance#5 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%235', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[39.0] + +__o = __obj[39] // xdc.rov.ViewInfo.Instance#5/viewMap + __o.$keys = [] + __o.push(__o['XDCROOT'] = __obj[40.0]); __o.$keys.push('XDCROOT') + __o.push(__o['XDCPATH'] = __obj[41.0]); __o.$keys.push('XDCPATH') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%235%2FviewMap', 'UTF-8')) + +__o = __obj[40] // xdc.rov.ViewInfo.Instance#5/viewMap/'XDCROOT' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%235%2FviewMap%2F%27XDCROOT%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('PathEntryView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitXdcRoot', 'UTF-8')) + +__o = __obj[41] // xdc.rov.ViewInfo.Instance#5/viewMap/'XDCPATH' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%235%2FviewMap%2F%27XDCPATH%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('PathEntryView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitXdcPath', 'UTF-8')) + +__o = __obj[42] // xdc.rov.ViewInfo.Instance#6 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%236', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[43.0] + +__o = __obj[43] // xdc.rov.ViewInfo.Instance#6/viewMap + __o.$keys = [] + __o.push(__o['Module'] = __obj[44.0]); __o.$keys.push('Module') + __o.push(__o['OutputBuffer'] = __obj[45.0]); __o.$keys.push('OutputBuffer') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%236%2FviewMap', 'UTF-8')) + +__o = __obj[44] // xdc.rov.ViewInfo.Instance#6/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%236%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[45] // xdc.rov.ViewInfo.Instance#6/viewMap/'OutputBuffer' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%236%2FviewMap%2F%27OutputBuffer%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BufferEntryView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitOutputBuffer', 'UTF-8')) + +__o = __obj[46] // xdc.rov.ViewInfo.Instance#7 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%237', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[47.0] + +__o = __obj[47] // xdc.rov.ViewInfo.Instance#7/viewMap + __o.$keys = [] + __o.push(__o['Module'] = __obj[48.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%237%2FviewMap', 'UTF-8')) + +__o = __obj[48] // xdc.rov.ViewInfo.Instance#7/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%237%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[49] // xdc.rov.ViewInfo.Instance#8 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%238', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[50.0] + +__o = __obj[50] // xdc.rov.ViewInfo.Instance#8/viewMap + __o.$keys = [] + __o.push(__o['MpuRegionAttrsView'] = __obj[51.0]); __o.$keys.push('MpuRegionAttrsView') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%238%2FviewMap', 'UTF-8')) + +__o = __obj[51] // xdc.rov.ViewInfo.Instance#8/viewMap/'MpuRegionAttrsView' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%238%2FviewMap%2F%27MpuRegionAttrsView%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('RegionAttrsView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewMpuRegionAttrs', 'UTF-8')) + +__o = __obj[52] // xdc.rov.ViewInfo.Instance#9 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%239', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[53.0] + +__o = __obj[53] // xdc.rov.ViewInfo.Instance#9/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[54.0]); __o.$keys.push('Basic') + __o.push(__o['Module'] = __obj[55.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%239%2FviewMap', 'UTF-8')) + +__o = __obj[54] // xdc.rov.ViewInfo.Instance#9/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%239%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[55] // xdc.rov.ViewInfo.Instance#9/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%239%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[56] // xdc.rov.ViewInfo.Instance#10 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2310', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[57.0] + +__o = __obj[57] // xdc.rov.ViewInfo.Instance#10/viewMap + __o.$keys = [] + __o.push(__o['Idle.funcList'] = __obj[58.0]); __o.$keys.push('Idle.funcList') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2310%2FviewMap', 'UTF-8')) + +__o = __obj[58] // xdc.rov.ViewInfo.Instance#10/viewMap/'Idle.funcList' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2310%2FviewMap%2F%27Idle.funcList%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[59] // xdc.rov.ViewInfo.Instance#11 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2311', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[60.0] + +__o = __obj[60] // xdc.rov.ViewInfo.Instance#11/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[61.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2311%2FviewMap', 'UTF-8')) + +__o = __obj[61] // xdc.rov.ViewInfo.Instance#11/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2311%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[62] // xdc.rov.ViewInfo.Instance#12 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2312', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[63.0] + +__o = __obj[63] // xdc.rov.ViewInfo.Instance#12/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[64.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[65.0]); __o.$keys.push('Detailed') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2312%2FviewMap', 'UTF-8')) + +__o = __obj[64] // xdc.rov.ViewInfo.Instance#12/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2312%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[65] // xdc.rov.ViewInfo.Instance#12/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2312%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[66] // xdc.rov.ViewInfo.Instance#13 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2313', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[67.0] + +__o = __obj[67] // xdc.rov.ViewInfo.Instance#13/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[68.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2313%2FviewMap', 'UTF-8')) + +__o = __obj[68] // xdc.rov.ViewInfo.Instance#13/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2313%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitInstance', 'UTF-8')) + +__o = __obj[69] // xdc.rov.ViewInfo.Instance#14 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2314', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[70.0] + +__o = __obj[70] // xdc.rov.ViewInfo.Instance#14/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[71.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2314%2FviewMap', 'UTF-8')) + +__o = __obj[71] // xdc.rov.ViewInfo.Instance#14/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2314%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[72] // xdc.rov.ViewInfo.Instance#15 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2315', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[73.0] + +__o = __obj[73] // xdc.rov.ViewInfo.Instance#15/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[74.0]); __o.$keys.push('Basic') + __o.push(__o['Module'] = __obj[75.0]); __o.$keys.push('Module') + __o.push(__o['ReadyQs'] = __obj[76.0]); __o.$keys.push('ReadyQs') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2315%2FviewMap', 'UTF-8')) + +__o = __obj[74] // xdc.rov.ViewInfo.Instance#15/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2315%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[75] // xdc.rov.ViewInfo.Instance#15/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2315%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[76] // xdc.rov.ViewInfo.Instance#15/viewMap/'ReadyQs' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2315%2FviewMap%2F%27ReadyQs%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ReadyQView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.TREE_TABLE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitReadyQs', 'UTF-8')) + +__o = __obj[77] // xdc.rov.ViewInfo.Instance#16 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[78.0] + +__o = __obj[78] // xdc.rov.ViewInfo.Instance#16/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[79.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[80.0]); __o.$keys.push('Detailed') + __o.push(__o['CallStacks'] = __obj[81.0]); __o.$keys.push('CallStacks') + __o.push(__o['ReadyQs'] = __obj[82.0]); __o.$keys.push('ReadyQs') + __o.push(__o['Module'] = __obj[83.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316%2FviewMap', 'UTF-8')) + +__o = __obj[79] // xdc.rov.ViewInfo.Instance#16/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[80] // xdc.rov.ViewInfo.Instance#16/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[81] // xdc.rov.ViewInfo.Instance#16/viewMap/'CallStacks' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316%2FviewMap%2F%27CallStacks%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('CallStackView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.TREE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitCallStack', 'UTF-8')) + +__o = __obj[82] // xdc.rov.ViewInfo.Instance#16/viewMap/'ReadyQs' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316%2FviewMap%2F%27ReadyQs%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ReadyQView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.TREE_TABLE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitReadyQs', 'UTF-8')) + +__o = __obj[83] // xdc.rov.ViewInfo.Instance#16/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2316%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[84] // xdc.rov.ViewInfo.Instance#17 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2317', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[85.0] + +__o = __obj[85] // xdc.rov.ViewInfo.Instance#17/viewMap + __o.$keys = [] + __o.push(__o['Module'] = __obj[86.0]); __o.$keys.push('Module') + __o.push(__o['Scan for errors...'] = __obj[87.0]); __o.$keys.push('Scan for errors...') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2317%2FviewMap', 'UTF-8')) + +__o = __obj[86] // xdc.rov.ViewInfo.Instance#17/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2317%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[87] // xdc.rov.ViewInfo.Instance#17/viewMap/'Scan for errors...' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2317%2FviewMap%2F%27Scan+for+errors...%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ErrorView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitErrorScan', 'UTF-8')) + +__o = __obj[88] // xdc.rov.ViewInfo.Instance#18 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2318', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[89.0] + +__o = __obj[89] // xdc.rov.ViewInfo.Instance#18/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[90.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[91.0]); __o.$keys.push('Detailed') + __o.push(__o['Module'] = __obj[92.0]); __o.$keys.push('Module') + __o.push(__o['Exception'] = __obj[93.0]); __o.$keys.push('Exception') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2318%2FviewMap', 'UTF-8')) + +__o = __obj[90] // xdc.rov.ViewInfo.Instance#18/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2318%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[91] // xdc.rov.ViewInfo.Instance#18/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2318%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[92] // xdc.rov.ViewInfo.Instance#18/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2318%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[93] // xdc.rov.ViewInfo.Instance#18/viewMap/'Exception' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2318%2FviewMap%2F%27Exception%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ExcContext', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.TREE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitException', 'UTF-8')) + +__o = __obj[94] // xdc.rov.ViewInfo.Instance#19 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2319', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[95.0] + +__o = __obj[95] // xdc.rov.ViewInfo.Instance#19/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[96.0]); __o.$keys.push('Basic') + __o.push(__o['Device'] = __obj[97.0]); __o.$keys.push('Device') + __o.push(__o['Module'] = __obj[98.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2319%2FviewMap', 'UTF-8')) + +__o = __obj[96] // xdc.rov.ViewInfo.Instance#19/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2319%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[97] // xdc.rov.ViewInfo.Instance#19/viewMap/'Device' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2319%2FviewMap%2F%27Device%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DeviceView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDevice', 'UTF-8')) + +__o = __obj[98] // xdc.rov.ViewInfo.Instance#19/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2319%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[99] // xdc.rov.ViewInfo.Instance#21 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2321', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[100.0] + +__o = __obj[100] // xdc.rov.ViewInfo.Instance#21/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[101.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2321%2FviewMap', 'UTF-8')) + +__o = __obj[101] // xdc.rov.ViewInfo.Instance#21/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2321%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[102] // xdc.rov.ViewInfo.Instance#22 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2322', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[103.0] + +__o = __obj[103] // xdc.rov.ViewInfo.Instance#22/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[104.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2322%2FviewMap', 'UTF-8')) + +__o = __obj[104] // xdc.rov.ViewInfo.Instance#22/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2322%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[105] // xdc.rov.ViewInfo.Instance#23 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2323', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[106.0] + +__o = __obj[106] // xdc.rov.ViewInfo.Instance#23/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[107.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2323%2FviewMap', 'UTF-8')) + +__o = __obj[107] // xdc.rov.ViewInfo.Instance#23/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2323%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[108] // xdc.rov.ViewInfo.Instance#24 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2324', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[109.0] + +__o = __obj[109] // xdc.rov.ViewInfo.Instance#24/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[110.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2324%2FviewMap', 'UTF-8')) + +__o = __obj[110] // xdc.rov.ViewInfo.Instance#24/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2324%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[111] // xdc.rov.ViewInfo.Instance#25 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2325', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[112.0] + +__o = __obj[112] // xdc.rov.ViewInfo.Instance#25/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[113.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[114.0]); __o.$keys.push('Detailed') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2325%2FviewMap', 'UTF-8')) + +__o = __obj[113] // xdc.rov.ViewInfo.Instance#25/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2325%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[114] // xdc.rov.ViewInfo.Instance#25/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2325%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[115] // xdc.rov.ViewInfo.Instance#26 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2326', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[116.0] + +__o = __obj[116] // xdc.rov.ViewInfo.Instance#26/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[117.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2326%2FviewMap', 'UTF-8')) + +__o = __obj[117] // xdc.rov.ViewInfo.Instance#26/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2326%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[118] // xdc.rov.ViewInfo.Instance#27 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2327', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[119.0] + +__o = __obj[119] // xdc.rov.ViewInfo.Instance#27/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[120.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2327%2FviewMap', 'UTF-8')) + +__o = __obj[120] // xdc.rov.ViewInfo.Instance#27/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2327%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[121] // xdc.rov.ViewInfo.Instance#28 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2328', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[122.0] + +__o = __obj[122] // xdc.rov.ViewInfo.Instance#28/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[123.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2328%2FviewMap', 'UTF-8')) + +__o = __obj[123] // xdc.rov.ViewInfo.Instance#28/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2328%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[124] // xdc.rov.ViewInfo.Instance#29 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2329', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[125.0] + +__o = __obj[125] // xdc.rov.ViewInfo.Instance#29/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[126.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[127.0]); __o.$keys.push('Detailed') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2329%2FviewMap', 'UTF-8')) + +__o = __obj[126] // xdc.rov.ViewInfo.Instance#29/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2329%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitInstance', 'UTF-8')) + +__o = __obj[127] // xdc.rov.ViewInfo.Instance#29/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2329%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[128] // xdc.rov.ViewInfo.Instance#30 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2330', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[129.0] + +__o = __obj[129] // xdc.rov.ViewInfo.Instance#30/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[130.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[131.0]); __o.$keys.push('Detailed') + __o.push(__o['FreeList'] = __obj[132.0]); __o.$keys.push('FreeList') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2330%2FviewMap', 'UTF-8')) + +__o = __obj[130] // xdc.rov.ViewInfo.Instance#30/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2330%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[131] // xdc.rov.ViewInfo.Instance#30/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2330%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[132] // xdc.rov.ViewInfo.Instance#30/viewMap/'FreeList' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2330%2FviewMap%2F%27FreeList%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('FreeBlockView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitData', 'UTF-8')) + +__o = __obj[133] // xdc.rov.ViewInfo.Instance#31 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2331', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[134.0] + +__o = __obj[134] // xdc.rov.ViewInfo.Instance#31/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[135.0]); __o.$keys.push('Basic') + __o.push(__o['Detailed'] = __obj[136.0]); __o.$keys.push('Detailed') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2331%2FviewMap', 'UTF-8')) + +__o = __obj[135] // xdc.rov.ViewInfo.Instance#31/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2331%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[136] // xdc.rov.ViewInfo.Instance#31/viewMap/'Detailed' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2331%2FviewMap%2F%27Detailed%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DetailedView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDetailed', 'UTF-8')) + +__o = __obj[137] // xdc.rov.ViewInfo.Instance#32 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2332', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[138.0] + +__o = __obj[138] // xdc.rov.ViewInfo.Instance#32/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[139.0]); __o.$keys.push('Basic') + __o.push(__o['HeapAllocList'] = __obj[140.0]); __o.$keys.push('HeapAllocList') + __o.push(__o['TaskAllocList'] = __obj[141.0]); __o.$keys.push('TaskAllocList') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2332%2FviewMap', 'UTF-8')) + +__o = __obj[139] // xdc.rov.ViewInfo.Instance#32/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2332%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[140] // xdc.rov.ViewInfo.Instance#32/viewMap/'HeapAllocList' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2332%2FviewMap%2F%27HeapAllocList%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('HeapListView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitHeapList', 'UTF-8')) + +__o = __obj[141] // xdc.rov.ViewInfo.Instance#32/viewMap/'TaskAllocList' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2332%2FviewMap%2F%27TaskAllocList%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('TaskView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.TREE_TABLE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitTask', 'UTF-8')) + +__o = __obj[142] // xdc.rov.ViewInfo.Instance#33 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2333', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[143.0] + +__o = __obj[143] // xdc.rov.ViewInfo.Instance#33/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[144.0]); __o.$keys.push('Basic') + __o.push(__o['Module'] = __obj[145.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2333%2FviewMap', 'UTF-8')) + +__o = __obj[144] // xdc.rov.ViewInfo.Instance#33/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2333%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[145] // xdc.rov.ViewInfo.Instance#33/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2333%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[146] // xdc.rov.ViewInfo.Instance#34 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2334', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[147.0] + +__o = __obj[147] // xdc.rov.ViewInfo.Instance#34/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[148.0]); __o.$keys.push('Basic') + __o.push(__o['Device'] = __obj[149.0]); __o.$keys.push('Device') + __o.push(__o['Module'] = __obj[150.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2334%2FviewMap', 'UTF-8')) + +__o = __obj[148] // xdc.rov.ViewInfo.Instance#34/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2334%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[149] // xdc.rov.ViewInfo.Instance#34/viewMap/'Device' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2334%2FviewMap%2F%27Device%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('DeviceView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.INSTANCE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitDevice', 'UTF-8')) + +__o = __obj[150] // xdc.rov.ViewInfo.Instance#34/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2334%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[151] // xdc.rov.ViewInfo.Instance#35 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[19.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2335', 'UTF-8')) + __o['showRawTab'] = true + __o['viewMap'] = __obj[152.0] + +__o = __obj[152] // xdc.rov.ViewInfo.Instance#35/viewMap + __o.$keys = [] + __o.push(__o['Module'] = __obj[153.0]); __o.$keys.push('Module') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2335%2FviewMap', 'UTF-8')) + +__o = __obj[153] // xdc.rov.ViewInfo.Instance#35/viewMap/'Module' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2335%2FviewMap%2F%27Module%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('ModuleView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitModule', 'UTF-8')) + +__o = __obj[154] // xdc.rov.ViewInfo.Instance#20/viewMap + __o.$keys = [] + __o.push(__o['Basic'] = __obj[155.0]); __o.$keys.push('Basic') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2320%2FviewMap', 'UTF-8')) + +__o = __obj[155] // xdc.rov.ViewInfo.Instance#20/viewMap/'Basic' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.Instance%2320%2FviewMap%2F%27Basic%27', 'UTF-8')) + __o['structName'] = String(java.net.URLDecoder.decode('BasicView', 'UTF-8')) + __o['type'] = String(java.net.URLDecoder.decode('xdc.rov.ViewInfo.MODULE_DATA', 'UTF-8')) + __o['viewInitFxn'] = String(java.net.URLDecoder.decode('viewInitBasic', 'UTF-8')) + +__o = __obj[156] // ti.tirtos.utils.UARTMon/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.tirtos.utils.UARTMon%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[157] // xdc.runtime.Assert + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[158.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert', 'UTF-8')) + __o['E_assertFailed'] = __obj[159.0] + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32770 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[160.0] + __o['configNameMap$'] = __obj[180.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[193.0] + +__o = __obj[158] // xdc.runtime.Assert/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2F%24instances', 'UTF-8')) + +__o = __obj[159] // xdc.runtime.Error.Desc#0 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%230', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('assertion+failure%25s%25s', 'UTF-8')) + +__o = __obj[160] // xdc.runtime.Assert/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[161] // ti.sysbios.gates.GateHwi.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[162.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi.Instance%230', 'UTF-8')) + __o['Q_BLOCKING'] = 1 + __o['Q_PREEMPTING'] = 2 + __o['instance'] = __obj[179.0] + +__o = __obj[162] // ti.sysbios.gates.GateHwi + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[163.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32809 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['Q_BLOCKING'] = 1 + __o['Q_PREEMPTING'] = 2 + __o['common$'] = __obj[164.0] + __o['configNameMap$'] = __obj[165.0] + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[99.0] + __o['viewNameMap$'] = __obj[178.0] + +__o = __obj[163] // ti.sysbios.gates.GateHwi/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2F%24instances', 'UTF-8')) + __o['0'] = __obj[161.0] + +__o = __obj[164] // ti.sysbios.gates.GateHwi/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[165] // ti.sysbios.gates.GateHwi/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[166.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[168.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[170.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[172.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[174.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[176.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[166] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[167.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[167] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[168] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[169.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[169] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[170] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[171.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[171] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[172] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[173.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[173] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[174] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[175.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[175] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[176] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[177.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[177] // ti.sysbios.gates.GateHwi/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[178] // ti.sysbios.gates.GateHwi/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[179] // ti.sysbios.gates.GateHwi.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateHwi.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[180] // xdc.runtime.Assert/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[181.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[183.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[185.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[187.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[189.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[191.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[181] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[182.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[182] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[183] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[184.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[184] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[185] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[186.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[186] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[187] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[188.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[188] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[189] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[190.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[190] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[191] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[192.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[192] // xdc.runtime.Assert/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[193] // xdc.runtime.Assert/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[194] // xdc.runtime.Core + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[195.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core', 'UTF-8')) + __o['A_initializedParams'] = __obj[196.0] + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32771 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[197.0] + __o['configNameMap$'] = __obj[198.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[211.0] + +__o = __obj[195] // xdc.runtime.Core/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2F%24instances', 'UTF-8')) + +__o = __obj[196] // xdc.runtime.Assert.Desc#0 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%230', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_initializedParams%3A+uninitialized+Params+struct', 'UTF-8')) + +__o = __obj[197] // xdc.runtime.Core/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[198] // xdc.runtime.Core/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[199.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[201.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[203.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[205.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[207.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[209.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[199] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[200.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[200] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[201] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[202.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[202] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[203] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[204.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[204] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[205] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[206.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[206] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[207] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[208.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[208] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[209] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[210.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[210] // xdc.runtime.Core/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[211] // xdc.runtime.Core/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Core%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[212] // xdc.runtime.Defaults + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[213.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32772 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[214.0] + __o['configNameMap$'] = __obj[215.0] + __o['noRuntimeCommon$'] = __obj[228.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[229.0] + +__o = __obj[213] // xdc.runtime.Defaults/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2F%24instances', 'UTF-8')) + +__o = __obj[214] // xdc.runtime.Defaults/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[215] // xdc.runtime.Defaults/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[216.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[218.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[220.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[222.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[224.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[226.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[216] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[217.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[217] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[218] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[219.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[219] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[220] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[221.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[221] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[222] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[223.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[223] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[224] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[225.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[225] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[226] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[227.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[227] // xdc.runtime.Defaults/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[228] // xdc.runtime.Defaults/noRuntimeCommon$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FnoRuntimeCommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = null + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.STATIC_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = false + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[229] // xdc.runtime.Defaults/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Defaults%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[230] // xdc.runtime.Diags + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[231.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags', 'UTF-8')) + __o['ALL'] = 65439 + __o['ALL_LOGGING'] = 65415 + __o['ANALYSIS'] = 32768 + __o['ASSERT'] = 16 + __o['CRITICAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.LEVEL2', 'UTF-8')) + __o['EMERGENCY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.LEVEL1', 'UTF-8')) + __o['ENTRY'] = 1 + __o['ERROR'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.LEVEL3', 'UTF-8')) + __o['EXIT'] = 2 + __o['INFO'] = 16384 + __o['INTERNAL'] = 8 + __o['LEVEL'] = 96 + __o['LIFECYCLE'] = 4 + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32773 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['STATUS'] = 128 + __o['USER1'] = 256 + __o['USER2'] = 512 + __o['USER3'] = 1024 + __o['USER4'] = 2048 + __o['USER5'] = 4096 + __o['USER6'] = 8192 + __o['USER7'] = 16384 + __o['USER8'] = 32768 + __o['WARNING'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.LEVEL4', 'UTF-8')) + __o['common$'] = __obj[232.0] + __o['configNameMap$'] = __obj[233.0] + __o['dictBase'] = null + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[21.0] + __o['setMaskEnabled'] = false + __o['viewNameMap$'] = __obj[246.0] + +__o = __obj[231] // xdc.runtime.Diags/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2F%24instances', 'UTF-8')) + +__o = __obj[232] // xdc.runtime.Diags/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[233] // xdc.runtime.Diags/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[234.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[236.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[238.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[240.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[242.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[244.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[234] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[235.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[235] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[236] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[237.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[237] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[238] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[239.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[239] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[240] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[241.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[241] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[242] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[243.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[243] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[244] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[245.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[245] // xdc.runtime.Diags/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[246] // xdc.runtime.Diags/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[247] // xdc.runtime.Error + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[248.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error', 'UTF-8')) + __o['E_generic'] = __obj[249.0] + __o['E_memory'] = __obj[250.0] + __o['E_msgCode'] = __obj[251.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32774 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['NUMARGS'] = 2 + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[252.0] + __o['configNameMap$'] = __obj[253.0] + __o['maxDepth'] = 2 + __o['policy'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.UNWIND', 'UTF-8')) + __o['policyFxn'] = String(java.net.URLDecoder.decode('%26xdc_runtime_Error_policyDefault__E', 'UTF-8')) + __o['raiseHook'] = String(java.net.URLDecoder.decode('%26ti_sysbios_BIOS_errorRaiseHook__I', 'UTF-8')) + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[266.0] + +__o = __obj[248] // xdc.runtime.Error/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2F%24instances', 'UTF-8')) + +__o = __obj[249] // xdc.runtime.Error.Desc#1 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%231', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('%25%24S', 'UTF-8')) + +__o = __obj[250] // xdc.runtime.Error.Desc#2 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%232', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('out+of+memory%3A+heap%3D0x%25x%2C+size%3D%25u', 'UTF-8')) + +__o = __obj[251] // xdc.runtime.Error.Desc#3 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%233', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('%25s+0x%25x', 'UTF-8')) + +__o = __obj[252] // xdc.runtime.Error/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[253] // xdc.runtime.Error/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[254.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[256.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[258.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[260.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[262.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[264.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[254] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[255.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[255] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[256] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[257.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[257] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[258] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[259.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[259] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[260] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[261.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[261] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[262] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[263.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[263] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[264] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[265.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[265] // xdc.runtime.Error/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[266] // xdc.runtime.Error/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[267] // xdc.runtime.Gate + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[268.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate', 'UTF-8')) + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32775 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[269.0] + __o['configNameMap$'] = __obj[270.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[283.0] + +__o = __obj[268] // xdc.runtime.Gate/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2F%24instances', 'UTF-8')) + +__o = __obj[269] // xdc.runtime.Gate/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[270] // xdc.runtime.Gate/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[271.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[273.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[275.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[277.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[279.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[281.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[271] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[272.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[272] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[273] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[274.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[274] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[275] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[276.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[276] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[277] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[278.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[278] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[279] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[280.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[280] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[281] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[282.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[282] // xdc.runtime.Gate/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[283] // xdc.runtime.Gate/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Gate%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[284] // xdc.runtime.Log + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[285.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log', 'UTF-8')) + __o['L_construct'] = __obj[286.0] + __o['L_create'] = __obj[287.0] + __o['L_delete'] = __obj[288.0] + __o['L_destruct'] = __obj[289.0] + __o['L_error'] = __obj[290.0] + __o['L_info'] = __obj[291.0] + __o['L_start'] = __obj[292.0] + __o['L_startInstance'] = __obj[293.0] + __o['L_stop'] = __obj[294.0] + __o['L_stopInstance'] = __obj[295.0] + __o['L_warning'] = __obj[296.0] + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32776 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['NUMARGS'] = 8 + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['PRINTFID'] = 0 + __o['common$'] = __obj[297.0] + __o['configNameMap$'] = __obj[298.0] + __o['idToInfo'] = __obj[311.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[312.0] + +__o = __obj[285] // xdc.runtime.Log/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2F%24instances', 'UTF-8')) + +__o = __obj[286] // xdc.runtime.Log.EventDesc#0 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%230', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 4 + __o['msg'] = String(java.net.URLDecoder.decode('%3C--+construct%3A+%25p%28%27%25s%27%29', 'UTF-8')) + +__o = __obj[287] // xdc.runtime.Log.EventDesc#1 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%231', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 4 + __o['msg'] = String(java.net.URLDecoder.decode('%3C--+create%3A+%25p%28%27%25s%27%29', 'UTF-8')) + +__o = __obj[288] // xdc.runtime.Log.EventDesc#3 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%233', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 4 + __o['msg'] = String(java.net.URLDecoder.decode('--%3E+delete%3A+%28%25p%29', 'UTF-8')) + +__o = __obj[289] // xdc.runtime.Log.EventDesc#2 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%232', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 4 + __o['msg'] = String(java.net.URLDecoder.decode('--%3E+destruct%3A+%28%25p%29', 'UTF-8')) + +__o = __obj[290] // xdc.runtime.Log.EventDesc#4 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%234', 'UTF-8')) + __o['level'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.LEVEL3', 'UTF-8')) + __o['mask'] = 128 + __o['msg'] = String(java.net.URLDecoder.decode('ERROR%3A+%25%24F%25%24S', 'UTF-8')) + +__o = __obj[291] // xdc.runtime.Log.EventDesc#6 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%236', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 16384 + __o['msg'] = String(java.net.URLDecoder.decode('%25%24F%25%24S', 'UTF-8')) + +__o = __obj[292] // xdc.runtime.Log.EventDesc#7 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%237', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 32768 + __o['msg'] = String(java.net.URLDecoder.decode('Start%3A+%25%24S', 'UTF-8')) + +__o = __obj[293] // xdc.runtime.Log.EventDesc#9 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%239', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 32768 + __o['msg'] = String(java.net.URLDecoder.decode('StartInstance%3A+%25%24S', 'UTF-8')) + +__o = __obj[294] // xdc.runtime.Log.EventDesc#8 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%238', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 32768 + __o['msg'] = String(java.net.URLDecoder.decode('Stop%3A+%25%24S', 'UTF-8')) + +__o = __obj[295] // xdc.runtime.Log.EventDesc#10 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2310', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 32768 + __o['msg'] = String(java.net.URLDecoder.decode('StopInstance%3A+%25%24S', 'UTF-8')) + +__o = __obj[296] // xdc.runtime.Log.EventDesc#5 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%235', 'UTF-8')) + __o['level'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.LEVEL4', 'UTF-8')) + __o['mask'] = 128 + __o['msg'] = String(java.net.URLDecoder.decode('WARNING%3A+%25%24F%25%24S', 'UTF-8')) + +__o = __obj[297] // xdc.runtime.Log/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[298] // xdc.runtime.Log/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[299.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[301.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[303.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[305.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[307.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[309.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[299] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[300.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[300] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[301] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[302.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[302] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[303] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[304.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[304] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[305] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[306.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[306] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[307] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[308.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[308] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[309] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[310.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[310] // xdc.runtime.Log/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[311] // xdc.runtime.Log/idToInfo + __o.$keys = [] + __o.push(__o['#4823'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_construct%3A%3A%3C--+construct%3A+%25p%28%27%25s%27%29', 'UTF-8'))); __o.$keys.push('#4823') + __o.push(__o['#4847'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_create%3A%3A%3C--+create%3A+%25p%28%27%25s%27%29', 'UTF-8'))); __o.$keys.push('#4847') + __o.push(__o['#4868'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_destruct%3A%3A--%3E+destruct%3A+%28%25p%29', 'UTF-8'))); __o.$keys.push('#4868') + __o.push(__o['#4887'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_delete%3A%3A--%3E+delete%3A+%28%25p%29', 'UTF-8'))); __o.$keys.push('#4887') + __o.push(__o['#4904'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_error%3A%3AERROR%3A+%25%24F%25%24S', 'UTF-8'))); __o.$keys.push('#4904') + __o.push(__o['#4918'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_warning%3A%3AWARNING%3A+%25%24F%25%24S', 'UTF-8'))); __o.$keys.push('#4918') + __o.push(__o['#4934'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_info%3A%3A%25%24F%25%24S', 'UTF-8'))); __o.$keys.push('#4934') + __o.push(__o['#4941'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_start%3A%3AStart%3A+%25%24S', 'UTF-8'))); __o.$keys.push('#4941') + __o.push(__o['#4952'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_stop%3A%3AStop%3A+%25%24S', 'UTF-8'))); __o.$keys.push('#4952') + __o.push(__o['#4962'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_startInstance%3A%3AStartInstance%3A+%25%24S', 'UTF-8'))); __o.$keys.push('#4962') + __o.push(__o['#4981'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.L_stopInstance%3A%3AStopInstance%3A+%25%24S', 'UTF-8'))); __o.$keys.push('#4981') + __o.push(__o['#4999'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock.LW_delayed%3A%3ALW_delayed%3A+delay%3A+%25d', 'UTF-8'))); __o.$keys.push('#4999') + __o.push(__o['#5021'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock.LM_tick%3A%3ALM_tick%3A+tick%3A+%25d', 'UTF-8'))); __o.$keys.push('#5021') + __o.push(__o['#5039'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock.LM_begin%3A%3ALM_begin%3A+clk%3A+0x%25x%2C+func%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5039') + __o.push(__o['#5071'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore.LM_post%3A%3ALM_post%3A+sem%3A+0x%25x%2C+count%3A+%25d', 'UTF-8'))); __o.$keys.push('#5071') + __o.push(__o['#5101'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore.LM_pend%3A%3ALM_pend%3A+sem%3A+0x%25x%2C+count%3A+%25d%2C+timeout%3A+%25d', 'UTF-8'))); __o.$keys.push('#5101') + __o.push(__o['#5144'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi.LM_begin%3A%3ALM_begin%3A+swi%3A+0x%25x%2C+func%3A+0x%25x%2C+preThread%3A+%25d', 'UTF-8'))); __o.$keys.push('#5144') + __o.push(__o['#5191'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi.LD_end%3A%3ALD_end%3A+swi%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5191') + __o.push(__o['#5209'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi.LM_post%3A%3ALM_post%3A+swi%3A+0x%25x%2C+func%3A+0x%25x%2C+pri%3A+%25d', 'UTF-8'))); __o.$keys.push('#5209') + __o.push(__o['#5249'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_switch%3A%3ALM_switch%3A+oldtsk%3A+0x%25x%2C+oldfunc%3A+0x%25x%2C+newtsk%3A+0x%25x%2C+newfunc%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5249') + __o.push(__o['#5317'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_sleep%3A%3ALM_sleep%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+timeout%3A+%25d', 'UTF-8'))); __o.$keys.push('#5317') + __o.push(__o['#5362'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LD_ready%3A%3ALD_ready%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+pri%3A+%25d', 'UTF-8'))); __o.$keys.push('#5362') + __o.push(__o['#5403'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LD_block%3A%3ALD_block%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5403') + __o.push(__o['#5435'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_yield%3A%3ALM_yield%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+currThread%3A+%25d', 'UTF-8'))); __o.$keys.push('#5435') + __o.push(__o['#5483'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_setPri%3A%3ALM_setPri%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+oldPri%3A+%25d%2C+newPri+%25d', 'UTF-8'))); __o.$keys.push('#5483') + __o.push(__o['#5539'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LD_exit%3A%3ALD_exit%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5539') + __o.push(__o['#5570'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_setAffinity%3A%3ALM_setAffinity%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+oldCore%3A+%25d%2C+oldAffinity+%25d%2C+newAffinity+%25d', 'UTF-8'))); __o.$keys.push('#5570') + __o.push(__o['#5653'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_schedule%3A%3ALD_schedule%3A+coreId%3A+%25d%2C+workFlag%3A+%25d%2C+curSetLocal%3A+%25d%2C+curSetX%3A+%25d%2C+curMaskLocal%3A+%25d', 'UTF-8'))); __o.$keys.push('#5653') + __o.push(__o['#5739'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.LM_noWork%3A%3ALD_noWork%3A+coreId%3A+%25d%2C+curSetLocal%3A+%25d%2C+curSetX%3A+%25d%2C+curMaskLocal%3A+%25d', 'UTF-8'))); __o.$keys.push('#5739') + __o.push(__o['#5809'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi.LM_begin%3A%3ALM_begin%3A+hwi%3A+0x%25x%2C+func%3A+0x%25x%2C+preThread%3A+%25d%2C+intNum%3A+%25d%2C+irp%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5809') + __o.push(__o['#5879'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi.LD_end%3A%3ALD_end%3A+hwi%3A+0x%25x', 'UTF-8'))); __o.$keys.push('#5879') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FidToInfo', 'UTF-8')) + +__o = __obj[312] // xdc.runtime.Log/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[313] // xdc.runtime.Main + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[314.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main', 'UTF-8')) + __o['Module_GateProxy'] = __obj[162.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = __obj[161.0] + __o['Module__gatePrms'] = null + __o['Module__id'] = 32777 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[315.0] + __o['configNameMap$'] = __obj[316.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[329.0] + +__o = __obj[314] // xdc.runtime.Main/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2F%24instances', 'UTF-8')) + +__o = __obj[315] // xdc.runtime.Main/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[316] // xdc.runtime.Main/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[317.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[319.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[321.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[323.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[325.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[327.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[317] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[318.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[318] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[319] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[320.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[320] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[321] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[322.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[322] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[323] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[324.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[324] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[325] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[326.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[326] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[327] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[328.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[328] // xdc.runtime.Main/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[329] // xdc.runtime.Main/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Main%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[330] // xdc.runtime.Memory + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[331.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory', 'UTF-8')) + __o['HeapProxy'] = __obj[332.0] + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32778 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['Q_BLOCKING'] = 1 + __o['common$'] = __obj[378.0] + __o['configNameMap$'] = __obj[379.0] + __o['defaultHeapInstance'] = __obj[334.0] + __o['defaultHeapSize'] = 4096 + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[392.0] + +__o = __obj[331] // xdc.runtime.Memory/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2F%24instances', 'UTF-8')) + +__o = __obj[332] // ti.sysbios.heaps.HeapMem + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[333.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem', 'UTF-8')) + __o['A_align'] = __obj[336.0] + __o['A_heapSize'] = __obj[337.0] + __o['A_invalidFree'] = __obj[338.0] + __o['A_zeroBlock'] = __obj[339.0] + __o['E_memory'] = __obj[340.0] + __o['Module_GateProxy'] = __obj[341.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = __obj[343.0] + __o['Module__gatePrms'] = null + __o['Module__id'] = 32812 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[363.0] + __o['configNameMap$'] = __obj[364.0] + __o['primaryHeapBaseAddr'] = null + __o['primaryHeapEndAddr'] = null + __o['reqAlign'] = 8 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[128.0] + __o['viewNameMap$'] = __obj[377.0] + +__o = __obj[333] // ti.sysbios.heaps.HeapMem/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2F%24instances', 'UTF-8')) + __o['0'] = __obj[334.0] + +__o = __obj[334] // ti.sysbios.heaps.HeapMem.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[332.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem.Instance%230', 'UTF-8')) + __o['align'] = 0 + __o['buf'] = 0 + __o['instance'] = __obj[335.0] + __o['minBlockAlign'] = 0 + __o['sectionName'] = null + __o['size'] = 1024 + __o['usePrimaryHeap'] = false + +__o = __obj[335] // ti.sysbios.heaps.HeapMem.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[336] // xdc.runtime.Assert.Desc#59 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2359', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_align%3A+Requested+align+is+not+a+power+of+2', 'UTF-8')) + +__o = __obj[337] // xdc.runtime.Assert.Desc#58 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2358', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_heapSize%3A+Requested+heap+size+is+too+small', 'UTF-8')) + +__o = __obj[338] // xdc.runtime.Assert.Desc#60 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2360', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_invalidFree%3A+Invalid+free', 'UTF-8')) + +__o = __obj[339] // xdc.runtime.Assert.Desc#57 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2357', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_zeroBlock%3A+Cannot+allocate+size+0', 'UTF-8')) + +__o = __obj[340] // xdc.runtime.Error.Desc#29 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2329', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('out+of+memory%3A+handle%3D0x%25x%2C+size%3D%25u', 'UTF-8')) + +__o = __obj[341] // ti.sysbios.gates.GateMutex + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[342.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex', 'UTF-8')) + __o['A_badContext'] = __obj[347.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32810 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['Q_BLOCKING'] = 1 + __o['Q_PREEMPTING'] = 2 + __o['common$'] = __obj[348.0] + __o['configNameMap$'] = __obj[349.0] + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[115.0] + __o['viewNameMap$'] = __obj[362.0] + +__o = __obj[342] // ti.sysbios.gates.GateMutex/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2F%24instances', 'UTF-8')) + __o['0'] = __obj[343.0] + __o['1'] = __obj[345.0] + +__o = __obj[343] // ti.sysbios.gates.GateMutex.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[341.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex.Instance%230', 'UTF-8')) + __o['Q_BLOCKING'] = 1 + __o['Q_PREEMPTING'] = 2 + __o['instance'] = __obj[344.0] + +__o = __obj[344] // ti.sysbios.gates.GateMutex.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[345] // ti.sysbios.gates.GateMutex.Instance#1 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[341.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex.Instance%231', 'UTF-8')) + __o['Q_BLOCKING'] = 1 + __o['Q_PREEMPTING'] = 2 + __o['instance'] = __obj[346.0] + +__o = __obj[346] // ti.sysbios.gates.GateMutex.Instance#1/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex.Instance%231%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[347] // xdc.runtime.Assert.Desc#44 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2344', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badContext%3A+bad+calling+context.+See+GateMutex+API+doc+for+details.', 'UTF-8')) + +__o = __obj[348] // ti.sysbios.gates.GateMutex/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[349] // ti.sysbios.gates.GateMutex/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[350.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[352.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[354.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[356.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[358.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[360.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[350] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[351.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[351] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[352] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[353.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[353] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[354] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[355.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[355] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[356] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[357.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[357] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[358] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[359.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[359] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[360] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[361.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[361] // ti.sysbios.gates.GateMutex/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[362] // ti.sysbios.gates.GateMutex/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.gates.GateMutex%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[363] // ti.sysbios.heaps.HeapMem/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[343.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[364] // ti.sysbios.heaps.HeapMem/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[365.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[367.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[369.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[371.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[373.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[375.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[365] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[366.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[366] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[367] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[368.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[368] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[369] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[370.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[370] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[371] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[372.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[372] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[373] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[374.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[374] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[375] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[376.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[376] // ti.sysbios.heaps.HeapMem/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[377] // ti.sysbios.heaps.HeapMem/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.heaps.HeapMem%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[378] // xdc.runtime.Memory/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[379] // xdc.runtime.Memory/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[380.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[382.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[384.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[386.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[388.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[390.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[380] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[381.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[381] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[382] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[383.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[383] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[384] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[385.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[385] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[386] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[387.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[387] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[388] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[389.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[389] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[390] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[391.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[391] // xdc.runtime.Memory/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[392] // xdc.runtime.Memory/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Memory%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[393] // xdc.runtime.Registry + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[394.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32779 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[395.0] + __o['configNameMap$'] = __obj[396.0] + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[31.0] + __o['viewNameMap$'] = __obj[409.0] + +__o = __obj[394] // xdc.runtime.Registry/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2F%24instances', 'UTF-8')) + +__o = __obj[395] // xdc.runtime.Registry/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[396] // xdc.runtime.Registry/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[397.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[399.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[401.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[403.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[405.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[407.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[397] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[398.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[398] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[399] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[400.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[400] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[401] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[402.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[402] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[403] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[404.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[404] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[405] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[406.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[406] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[407] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[408.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[408] // xdc.runtime.Registry/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[409] // xdc.runtime.Registry/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Registry%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[410] // xdc.runtime.Startup + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[411.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup', 'UTF-8')) + __o['DONE'] = -1 + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32780 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['NOTDONE'] = 0 + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[412.0] + __o['configNameMap$'] = __obj[413.0] + __o['execImpl'] = String(java.net.URLDecoder.decode('%26xdc_runtime_Startup_exec__I', 'UTF-8')) + __o['firstFxns'] = __obj[426.0] + __o['lastFxns'] = __obj[427.0] + __o['maxPasses'] = 32 + __o['resetFxn'] = null + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[34.0] + __o['sfxnRts'] = __obj[428.0] + __o['sfxnTab'] = __obj[429.0] + __o['startModsFxn'] = String(java.net.URLDecoder.decode('%26xdc_runtime_Startup_startMods__I', 'UTF-8')) + __o['viewNameMap$'] = __obj[430.0] + +__o = __obj[411] // xdc.runtime.Startup/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2F%24instances', 'UTF-8')) + +__o = __obj[412] // xdc.runtime.Startup/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[413] // xdc.runtime.Startup/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[414.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[416.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[418.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[420.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[422.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[424.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[414] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[415.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[415] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[416] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[417.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[417] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[418] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[419.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[419] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[420] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[421.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[421] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[422] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[423.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[423] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[424] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[425.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[425] // xdc.runtime.Startup/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[426] // xdc.runtime.Startup/firstFxns + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FfirstFxns', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('%26ti_sysbios_heaps_HeapMem_init__I', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('%26ti_catalog_arm_cortexm4_tiva_ce_Boot_init__I', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('%26ti_sysbios_hal_Hwi_initStack', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_initNVIC__E', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_lm4_Timer_enableTimers__I', 'UTF-8')) + +__o = __obj[427] // xdc.runtime.Startup/lastFxns + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FlastFxns', 'UTF-8')) + +__o = __obj[428] // xdc.runtime.Startup/sfxnRts + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FsfxnRts', 'UTF-8')) + __o['0'] = true + __o['1'] = true + __o['2'] = false + __o['3'] = false + __o['4'] = false + __o['5'] = false + __o['6'] = false + __o['7'] = false + +__o = __obj[429] // xdc.runtime.Startup/sfxnTab + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FsfxnTab', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('%26xdc_runtime_System_Module_startup__E', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('%26xdc_runtime_SysMin_Module_startup__E', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Clock_Module_startup__E', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Swi_Module_startup__E', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Task_Module_startup__E', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('%26ti_sysbios_hal_Hwi_Module_startup__E', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_Module_startup__E', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_lm4_Timer_Module_startup__E', 'UTF-8')) + +__o = __obj[430] // xdc.runtime.Startup/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Startup%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[431] // xdc.runtime.System + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[432.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System', 'UTF-8')) + __o['A_cannotFitIntoArg'] = __obj[433.0] + __o['Module_GateProxy'] = __obj[162.0] + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = __obj[161.0] + __o['Module__gatePrms'] = null + __o['Module__id'] = 32781 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['STATUS_UNKNOWN'] = 51966 + __o['SupportProxy'] = __obj[434.0] + __o['abortFxn'] = String(java.net.URLDecoder.decode('%26xdc_runtime_System_abortStd__E', 'UTF-8')) + __o['common$'] = __obj[451.0] + __o['configNameMap$'] = __obj[452.0] + __o['exitFxn'] = String(java.net.URLDecoder.decode('%26xdc_runtime_System_exitStd__E', 'UTF-8')) + __o['exitFxns'] = __obj[465.0] + __o['extendFxn'] = String(java.net.URLDecoder.decode('%26xdc_runtime_System_printfExtend__I', 'UTF-8')) + __o['extendedFormats'] = String(java.net.URLDecoder.decode('%25%24L%25%24S%25%24F', 'UTF-8')) + __o['maxAtexitHandlers'] = 2 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[38.0] + __o['viewNameMap$'] = __obj[466.0] + +__o = __obj[432] // xdc.runtime.System/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2F%24instances', 'UTF-8')) + +__o = __obj[433] // xdc.runtime.Assert.Desc#7 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%237', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_cannotFitIntoArg%3A+sizeof%28Float%29+%3E+sizeof%28Arg%29', 'UTF-8')) + +__o = __obj[434] // xdc.runtime.SysMin + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[435.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin', 'UTF-8')) + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32782 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['bufSize'] = 128 + __o['common$'] = __obj[436.0] + __o['configNameMap$'] = __obj[437.0] + __o['flushAtExit'] = true + __o['outputFunc'] = String(java.net.URLDecoder.decode('%26xdc_runtime_SysMin_output__I', 'UTF-8')) + __o['outputFxn'] = null + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[42.0] + __o['sectionName'] = null + __o['viewNameMap$'] = __obj[450.0] + +__o = __obj[435] // xdc.runtime.SysMin/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2F%24instances', 'UTF-8')) + +__o = __obj[436] // xdc.runtime.SysMin/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[437] // xdc.runtime.SysMin/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[438.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[440.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[442.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[444.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[446.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[448.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[438] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[439.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[439] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[440] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[441.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[441] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[442] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[443.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[443] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[444] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[445.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[445] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[446] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[447.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[447] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[448] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[449.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[449] // xdc.runtime.SysMin/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[450] // xdc.runtime.SysMin/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.SysMin%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[451] // xdc.runtime.System/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[452] // xdc.runtime.System/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[453.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[455.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[457.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[459.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[461.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[463.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[453] // xdc.runtime.System/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[454.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[454] // xdc.runtime.System/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[455] // xdc.runtime.System/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[456.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[456] // xdc.runtime.System/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[457] // xdc.runtime.System/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[458.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[458] // xdc.runtime.System/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[459] // xdc.runtime.System/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[460.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[460] // xdc.runtime.System/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[461] // xdc.runtime.System/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[462.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[462] // xdc.runtime.System/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[463] // xdc.runtime.System/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[464.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[464] // xdc.runtime.System/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[465] // xdc.runtime.System/exitFxns + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FexitFxns', 'UTF-8')) + +__o = __obj[466] // xdc.runtime.System/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.System%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[467] // xdc.runtime.Text + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[468.0] + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text', 'UTF-8')) + __o['Module__diagsEnabled'] = 16 + __o['Module__diagsIncluded'] = 16 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32783 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['charCnt'] = 6253 + __o['charTab'] = __obj[469.0] + __o['common$'] = __obj[470.0] + __o['configNameMap$'] = __obj[471.0] + __o['isLoaded'] = true + __o['nameEmpty'] = String(java.net.URLDecoder.decode('%7Bempty-instance-name%7D', 'UTF-8')) + __o['nameStatic'] = String(java.net.URLDecoder.decode('%7Bstatic-instance-name%7D', 'UTF-8')) + __o['nameUnknown'] = String(java.net.URLDecoder.decode('%7Bunknown-instance-name%7D', 'UTF-8')) + __o['nodeCnt'] = 47 + __o['nodeTab'] = __obj[484.0] + __o['registryModsLastId'] = 32767 + __o['rovShowRawTab$'] = true + __o['unnamedModsLastId'] = 16384 + __o['viewNameMap$'] = __obj[532.0] + __o['visitRopeFxn'] = String(java.net.URLDecoder.decode('%26xdc_runtime_Text_visitRope__I', 'UTF-8')) + __o['visitRopeFxn2'] = String(java.net.URLDecoder.decode('%26xdc_runtime_Text_visitRope2__I', 'UTF-8')) + +__o = __obj[468] // xdc.runtime.Text/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2F%24instances', 'UTF-8')) + +__o = __obj[469] // xdc.runtime.Text/charTab + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FcharTab', 'UTF-8')) + __o['0'] = 0 + __o['1'] = 65 + __o['2'] = 95 + __o['3'] = 105 + __o['4'] = 110 + __o['5'] = 105 + __o['6'] = 116 + __o['7'] = 105 + __o['8'] = 97 + __o['9'] = 108 + __o['10'] = 105 + __o['11'] = 122 + __o['12'] = 101 + __o['13'] = 100 + __o['14'] = 80 + __o['15'] = 97 + __o['16'] = 114 + __o['17'] = 97 + __o['18'] = 109 + __o['19'] = 115 + __o['20'] = 58 + __o['21'] = 32 + __o['22'] = 117 + __o['23'] = 110 + __o['24'] = 105 + __o['25'] = 110 + __o['26'] = 105 + __o['27'] = 116 + __o['28'] = 105 + __o['29'] = 97 + __o['30'] = 108 + __o['31'] = 105 + __o['32'] = 122 + __o['33'] = 101 + __o['34'] = 100 + __o['35'] = 32 + __o['36'] = 80 + __o['37'] = 97 + __o['38'] = 114 + __o['39'] = 97 + __o['40'] = 109 + __o['41'] = 115 + __o['42'] = 32 + __o['43'] = 115 + __o['44'] = 116 + __o['45'] = 114 + __o['46'] = 117 + __o['47'] = 99 + __o['48'] = 116 + __o['49'] = 0 + __o['50'] = 72 + __o['51'] = 101 + __o['52'] = 97 + __o['53'] = 112 + __o['54'] = 77 + __o['55'] = 105 + __o['56'] = 110 + __o['57'] = 95 + __o['58'] = 99 + __o['59'] = 114 + __o['60'] = 101 + __o['61'] = 97 + __o['62'] = 116 + __o['63'] = 101 + __o['64'] = 32 + __o['65'] = 99 + __o['66'] = 97 + __o['67'] = 110 + __o['68'] = 110 + __o['69'] = 111 + __o['70'] = 116 + __o['71'] = 32 + __o['72'] = 104 + __o['73'] = 97 + __o['74'] = 118 + __o['75'] = 101 + __o['76'] = 32 + __o['77'] = 97 + __o['78'] = 32 + __o['79'] = 122 + __o['80'] = 101 + __o['81'] = 114 + __o['82'] = 111 + __o['83'] = 32 + __o['84'] = 115 + __o['85'] = 105 + __o['86'] = 122 + __o['87'] = 101 + __o['88'] = 32 + __o['89'] = 118 + __o['90'] = 97 + __o['91'] = 108 + __o['92'] = 117 + __o['93'] = 101 + __o['94'] = 0 + __o['95'] = 72 + __o['96'] = 101 + __o['97'] = 97 + __o['98'] = 112 + __o['99'] = 83 + __o['100'] = 116 + __o['101'] = 100 + __o['102'] = 95 + __o['103'] = 99 + __o['104'] = 114 + __o['105'] = 101 + __o['106'] = 97 + __o['107'] = 116 + __o['108'] = 101 + __o['109'] = 32 + __o['110'] = 99 + __o['111'] = 97 + __o['112'] = 110 + __o['113'] = 110 + __o['114'] = 111 + __o['115'] = 116 + __o['116'] = 32 + __o['117'] = 104 + __o['118'] = 97 + __o['119'] = 118 + __o['120'] = 101 + __o['121'] = 32 + __o['122'] = 97 + __o['123'] = 32 + __o['124'] = 122 + __o['125'] = 101 + __o['126'] = 114 + __o['127'] = 111 + __o['128'] = 32 + __o['129'] = 115 + __o['130'] = 105 + __o['131'] = 122 + __o['132'] = 101 + __o['133'] = 32 + __o['134'] = 118 + __o['135'] = 97 + __o['136'] = 108 + __o['137'] = 117 + __o['138'] = 101 + __o['139'] = 0 + __o['140'] = 72 + __o['141'] = 101 + __o['142'] = 97 + __o['143'] = 112 + __o['144'] = 83 + __o['145'] = 116 + __o['146'] = 100 + __o['147'] = 95 + __o['148'] = 97 + __o['149'] = 108 + __o['150'] = 108 + __o['151'] = 111 + __o['152'] = 99 + __o['153'] = 32 + __o['154'] = 97 + __o['155'] = 108 + __o['156'] = 105 + __o['157'] = 103 + __o['158'] = 110 + __o['159'] = 109 + __o['160'] = 101 + __o['161'] = 110 + __o['162'] = 116 + __o['163'] = 32 + __o['164'] = 109 + __o['165'] = 117 + __o['166'] = 115 + __o['167'] = 116 + __o['168'] = 32 + __o['169'] = 98 + __o['170'] = 101 + __o['171'] = 32 + __o['172'] = 97 + __o['173'] = 32 + __o['174'] = 112 + __o['175'] = 111 + __o['176'] = 119 + __o['177'] = 101 + __o['178'] = 114 + __o['179'] = 32 + __o['180'] = 111 + __o['181'] = 102 + __o['182'] = 32 + __o['183'] = 50 + __o['184'] = 0 + __o['185'] = 72 + __o['186'] = 101 + __o['187'] = 97 + __o['188'] = 112 + __o['189'] = 83 + __o['190'] = 116 + __o['191'] = 100 + __o['192'] = 32 + __o['193'] = 105 + __o['194'] = 110 + __o['195'] = 115 + __o['196'] = 116 + __o['197'] = 97 + __o['198'] = 110 + __o['199'] = 99 + __o['200'] = 101 + __o['201'] = 32 + __o['202'] = 116 + __o['203'] = 111 + __o['204'] = 116 + __o['205'] = 97 + __o['206'] = 108 + __o['207'] = 70 + __o['208'] = 114 + __o['209'] = 101 + __o['210'] = 101 + __o['211'] = 83 + __o['212'] = 105 + __o['213'] = 122 + __o['214'] = 101 + __o['215'] = 32 + __o['216'] = 105 + __o['217'] = 115 + __o['218'] = 32 + __o['219'] = 103 + __o['220'] = 114 + __o['221'] = 101 + __o['222'] = 97 + __o['223'] = 116 + __o['224'] = 101 + __o['225'] = 114 + __o['226'] = 32 + __o['227'] = 116 + __o['228'] = 104 + __o['229'] = 97 + __o['230'] = 110 + __o['231'] = 32 + __o['232'] = 115 + __o['233'] = 116 + __o['234'] = 97 + __o['235'] = 114 + __o['236'] = 116 + __o['237'] = 105 + __o['238'] = 110 + __o['239'] = 103 + __o['240'] = 32 + __o['241'] = 115 + __o['242'] = 105 + __o['243'] = 122 + __o['244'] = 101 + __o['245'] = 0 + __o['246'] = 72 + __o['247'] = 101 + __o['248'] = 97 + __o['249'] = 112 + __o['250'] = 83 + __o['251'] = 116 + __o['252'] = 100 + __o['253'] = 95 + __o['254'] = 97 + __o['255'] = 108 + __o['256'] = 108 + __o['257'] = 111 + __o['258'] = 99 + __o['259'] = 32 + __o['260'] = 45 + __o['261'] = 32 + __o['262'] = 114 + __o['263'] = 101 + __o['264'] = 113 + __o['265'] = 117 + __o['266'] = 101 + __o['267'] = 115 + __o['268'] = 116 + __o['269'] = 101 + __o['270'] = 100 + __o['271'] = 32 + __o['272'] = 97 + __o['273'] = 108 + __o['274'] = 105 + __o['275'] = 103 + __o['276'] = 110 + __o['277'] = 109 + __o['278'] = 101 + __o['279'] = 110 + __o['280'] = 116 + __o['281'] = 32 + __o['282'] = 105 + __o['283'] = 115 + __o['284'] = 32 + __o['285'] = 103 + __o['286'] = 114 + __o['287'] = 101 + __o['288'] = 97 + __o['289'] = 116 + __o['290'] = 101 + __o['291'] = 114 + __o['292'] = 32 + __o['293'] = 116 + __o['294'] = 104 + __o['295'] = 97 + __o['296'] = 110 + __o['297'] = 32 + __o['298'] = 97 + __o['299'] = 108 + __o['300'] = 108 + __o['301'] = 111 + __o['302'] = 119 + __o['303'] = 101 + __o['304'] = 100 + __o['305'] = 0 + __o['306'] = 65 + __o['307'] = 95 + __o['308'] = 105 + __o['309'] = 110 + __o['310'] = 118 + __o['311'] = 97 + __o['312'] = 108 + __o['313'] = 105 + __o['314'] = 100 + __o['315'] = 76 + __o['316'] = 111 + __o['317'] = 103 + __o['318'] = 103 + __o['319'] = 101 + __o['320'] = 114 + __o['321'] = 58 + __o['322'] = 32 + __o['323'] = 84 + __o['324'] = 104 + __o['325'] = 101 + __o['326'] = 32 + __o['327'] = 108 + __o['328'] = 111 + __o['329'] = 103 + __o['330'] = 103 + __o['331'] = 101 + __o['332'] = 114 + __o['333'] = 32 + __o['334'] = 105 + __o['335'] = 100 + __o['336'] = 32 + __o['337'] = 37 + __o['338'] = 100 + __o['339'] = 32 + __o['340'] = 105 + __o['341'] = 115 + __o['342'] = 32 + __o['343'] = 105 + __o['344'] = 110 + __o['345'] = 118 + __o['346'] = 97 + __o['347'] = 108 + __o['348'] = 105 + __o['349'] = 100 + __o['350'] = 46 + __o['351'] = 0 + __o['352'] = 65 + __o['353'] = 95 + __o['354'] = 99 + __o['355'] = 97 + __o['356'] = 110 + __o['357'] = 110 + __o['358'] = 111 + __o['359'] = 116 + __o['360'] = 70 + __o['361'] = 105 + __o['362'] = 116 + __o['363'] = 73 + __o['364'] = 110 + __o['365'] = 116 + __o['366'] = 111 + __o['367'] = 65 + __o['368'] = 114 + __o['369'] = 103 + __o['370'] = 58 + __o['371'] = 32 + __o['372'] = 115 + __o['373'] = 105 + __o['374'] = 122 + __o['375'] = 101 + __o['376'] = 111 + __o['377'] = 102 + __o['378'] = 40 + __o['379'] = 70 + __o['380'] = 108 + __o['381'] = 111 + __o['382'] = 97 + __o['383'] = 116 + __o['384'] = 41 + __o['385'] = 32 + __o['386'] = 62 + __o['387'] = 32 + __o['388'] = 115 + __o['389'] = 105 + __o['390'] = 122 + __o['391'] = 101 + __o['392'] = 111 + __o['393'] = 102 + __o['394'] = 40 + __o['395'] = 65 + __o['396'] = 114 + __o['397'] = 103 + __o['398'] = 41 + __o['399'] = 0 + __o['400'] = 65 + __o['401'] = 95 + __o['402'] = 109 + __o['403'] = 117 + __o['404'] = 115 + __o['405'] = 116 + __o['406'] = 85 + __o['407'] = 115 + __o['408'] = 101 + __o['409'] = 69 + __o['410'] = 110 + __o['411'] = 104 + __o['412'] = 97 + __o['413'] = 110 + __o['414'] = 99 + __o['415'] = 101 + __o['416'] = 100 + __o['417'] = 67 + __o['418'] = 108 + __o['419'] = 111 + __o['420'] = 99 + __o['421'] = 107 + __o['422'] = 77 + __o['423'] = 111 + __o['424'] = 100 + __o['425'] = 101 + __o['426'] = 58 + __o['427'] = 32 + __o['428'] = 84 + __o['429'] = 104 + __o['430'] = 105 + __o['431'] = 115 + __o['432'] = 32 + __o['433'] = 100 + __o['434'] = 101 + __o['435'] = 118 + __o['436'] = 105 + __o['437'] = 99 + __o['438'] = 101 + __o['439'] = 32 + __o['440'] = 114 + __o['441'] = 101 + __o['442'] = 113 + __o['443'] = 117 + __o['444'] = 105 + __o['445'] = 114 + __o['446'] = 101 + __o['447'] = 115 + __o['448'] = 32 + __o['449'] = 116 + __o['450'] = 104 + __o['451'] = 101 + __o['452'] = 32 + __o['453'] = 69 + __o['454'] = 110 + __o['455'] = 104 + __o['456'] = 97 + __o['457'] = 110 + __o['458'] = 99 + __o['459'] = 101 + __o['460'] = 100 + __o['461'] = 32 + __o['462'] = 67 + __o['463'] = 108 + __o['464'] = 111 + __o['465'] = 99 + __o['466'] = 107 + __o['467'] = 32 + __o['468'] = 77 + __o['469'] = 111 + __o['470'] = 100 + __o['471'] = 101 + __o['472'] = 46 + __o['473'] = 0 + __o['474'] = 65 + __o['475'] = 95 + __o['476'] = 109 + __o['477'] = 117 + __o['478'] = 115 + __o['479'] = 116 + __o['480'] = 78 + __o['481'] = 111 + __o['482'] = 116 + __o['483'] = 85 + __o['484'] = 115 + __o['485'] = 101 + __o['486'] = 69 + __o['487'] = 110 + __o['488'] = 104 + __o['489'] = 97 + __o['490'] = 110 + __o['491'] = 99 + __o['492'] = 101 + __o['493'] = 100 + __o['494'] = 67 + __o['495'] = 108 + __o['496'] = 111 + __o['497'] = 99 + __o['498'] = 107 + __o['499'] = 77 + __o['500'] = 111 + __o['501'] = 100 + __o['502'] = 101 + __o['503'] = 58 + __o['504'] = 32 + __o['505'] = 84 + __o['506'] = 104 + __o['507'] = 105 + __o['508'] = 115 + __o['509'] = 32 + __o['510'] = 100 + __o['511'] = 101 + __o['512'] = 118 + __o['513'] = 105 + __o['514'] = 99 + __o['515'] = 101 + __o['516'] = 32 + __o['517'] = 100 + __o['518'] = 111 + __o['519'] = 101 + __o['520'] = 115 + __o['521'] = 32 + __o['522'] = 110 + __o['523'] = 111 + __o['524'] = 116 + __o['525'] = 32 + __o['526'] = 115 + __o['527'] = 117 + __o['528'] = 112 + __o['529'] = 112 + __o['530'] = 111 + __o['531'] = 114 + __o['532'] = 116 + __o['533'] = 32 + __o['534'] = 116 + __o['535'] = 104 + __o['536'] = 101 + __o['537'] = 32 + __o['538'] = 69 + __o['539'] = 110 + __o['540'] = 104 + __o['541'] = 97 + __o['542'] = 110 + __o['543'] = 99 + __o['544'] = 101 + __o['545'] = 100 + __o['546'] = 32 + __o['547'] = 67 + __o['548'] = 108 + __o['549'] = 111 + __o['550'] = 99 + __o['551'] = 107 + __o['552'] = 32 + __o['553'] = 77 + __o['554'] = 111 + __o['555'] = 100 + __o['556'] = 101 + __o['557'] = 46 + __o['558'] = 0 + __o['559'] = 65 + __o['560'] = 95 + __o['561'] = 110 + __o['562'] = 117 + __o['563'] = 108 + __o['564'] = 108 + __o['565'] = 80 + __o['566'] = 111 + __o['567'] = 105 + __o['568'] = 110 + __o['569'] = 116 + __o['570'] = 101 + __o['571'] = 114 + __o['572'] = 58 + __o['573'] = 32 + __o['574'] = 80 + __o['575'] = 111 + __o['576'] = 105 + __o['577'] = 110 + __o['578'] = 116 + __o['579'] = 101 + __o['580'] = 114 + __o['581'] = 32 + __o['582'] = 105 + __o['583'] = 115 + __o['584'] = 32 + __o['585'] = 110 + __o['586'] = 117 + __o['587'] = 108 + __o['588'] = 108 + __o['589'] = 0 + __o['590'] = 65 + __o['591'] = 95 + __o['592'] = 105 + __o['593'] = 110 + __o['594'] = 118 + __o['595'] = 97 + __o['596'] = 108 + __o['597'] = 105 + __o['598'] = 100 + __o['599'] = 82 + __o['600'] = 101 + __o['601'] = 103 + __o['602'] = 105 + __o['603'] = 111 + __o['604'] = 110 + __o['605'] = 73 + __o['606'] = 100 + __o['607'] = 58 + __o['608'] = 32 + __o['609'] = 77 + __o['610'] = 80 + __o['611'] = 85 + __o['612'] = 32 + __o['613'] = 82 + __o['614'] = 101 + __o['615'] = 103 + __o['616'] = 105 + __o['617'] = 111 + __o['618'] = 110 + __o['619'] = 32 + __o['620'] = 110 + __o['621'] = 117 + __o['622'] = 109 + __o['623'] = 98 + __o['624'] = 101 + __o['625'] = 114 + __o['626'] = 32 + __o['627'] = 112 + __o['628'] = 97 + __o['629'] = 115 + __o['630'] = 115 + __o['631'] = 101 + __o['632'] = 100 + __o['633'] = 32 + __o['634'] = 105 + __o['635'] = 115 + __o['636'] = 32 + __o['637'] = 105 + __o['638'] = 110 + __o['639'] = 118 + __o['640'] = 97 + __o['641'] = 108 + __o['642'] = 105 + __o['643'] = 100 + __o['644'] = 46 + __o['645'] = 0 + __o['646'] = 65 + __o['647'] = 95 + __o['648'] = 117 + __o['649'] = 110 + __o['650'] = 97 + __o['651'] = 108 + __o['652'] = 105 + __o['653'] = 103 + __o['654'] = 110 + __o['655'] = 101 + __o['656'] = 100 + __o['657'] = 66 + __o['658'] = 97 + __o['659'] = 115 + __o['660'] = 101 + __o['661'] = 65 + __o['662'] = 100 + __o['663'] = 100 + __o['664'] = 114 + __o['665'] = 58 + __o['666'] = 32 + __o['667'] = 77 + __o['668'] = 80 + __o['669'] = 85 + __o['670'] = 32 + __o['671'] = 114 + __o['672'] = 101 + __o['673'] = 103 + __o['674'] = 105 + __o['675'] = 111 + __o['676'] = 110 + __o['677'] = 32 + __o['678'] = 98 + __o['679'] = 97 + __o['680'] = 115 + __o['681'] = 101 + __o['682'] = 32 + __o['683'] = 97 + __o['684'] = 100 + __o['685'] = 100 + __o['686'] = 114 + __o['687'] = 101 + __o['688'] = 115 + __o['689'] = 115 + __o['690'] = 32 + __o['691'] = 110 + __o['692'] = 111 + __o['693'] = 116 + __o['694'] = 32 + __o['695'] = 97 + __o['696'] = 108 + __o['697'] = 105 + __o['698'] = 103 + __o['699'] = 110 + __o['700'] = 101 + __o['701'] = 100 + __o['702'] = 32 + __o['703'] = 116 + __o['704'] = 111 + __o['705'] = 32 + __o['706'] = 115 + __o['707'] = 105 + __o['708'] = 122 + __o['709'] = 101 + __o['710'] = 46 + __o['711'] = 0 + __o['712'] = 65 + __o['713'] = 95 + __o['714'] = 99 + __o['715'] = 108 + __o['716'] = 111 + __o['717'] = 99 + __o['718'] = 107 + __o['719'] = 68 + __o['720'] = 105 + __o['721'] = 115 + __o['722'] = 97 + __o['723'] = 98 + __o['724'] = 108 + __o['725'] = 101 + __o['726'] = 100 + __o['727'] = 58 + __o['728'] = 32 + __o['729'] = 67 + __o['730'] = 97 + __o['731'] = 110 + __o['732'] = 110 + __o['733'] = 111 + __o['734'] = 116 + __o['735'] = 32 + __o['736'] = 99 + __o['737'] = 114 + __o['738'] = 101 + __o['739'] = 97 + __o['740'] = 116 + __o['741'] = 101 + __o['742'] = 32 + __o['743'] = 97 + __o['744'] = 32 + __o['745'] = 99 + __o['746'] = 108 + __o['747'] = 111 + __o['748'] = 99 + __o['749'] = 107 + __o['750'] = 32 + __o['751'] = 105 + __o['752'] = 110 + __o['753'] = 115 + __o['754'] = 116 + __o['755'] = 97 + __o['756'] = 110 + __o['757'] = 99 + __o['758'] = 101 + __o['759'] = 32 + __o['760'] = 119 + __o['761'] = 104 + __o['762'] = 101 + __o['763'] = 110 + __o['764'] = 32 + __o['765'] = 66 + __o['766'] = 73 + __o['767'] = 79 + __o['768'] = 83 + __o['769'] = 46 + __o['770'] = 99 + __o['771'] = 108 + __o['772'] = 111 + __o['773'] = 99 + __o['774'] = 107 + __o['775'] = 69 + __o['776'] = 110 + __o['777'] = 97 + __o['778'] = 98 + __o['779'] = 108 + __o['780'] = 101 + __o['781'] = 100 + __o['782'] = 32 + __o['783'] = 105 + __o['784'] = 115 + __o['785'] = 32 + __o['786'] = 102 + __o['787'] = 97 + __o['788'] = 108 + __o['789'] = 115 + __o['790'] = 101 + __o['791'] = 46 + __o['792'] = 0 + __o['793'] = 65 + __o['794'] = 95 + __o['795'] = 98 + __o['796'] = 97 + __o['797'] = 100 + __o['798'] = 84 + __o['799'] = 104 + __o['800'] = 114 + __o['801'] = 101 + __o['802'] = 97 + __o['803'] = 100 + __o['804'] = 84 + __o['805'] = 121 + __o['806'] = 112 + __o['807'] = 101 + __o['808'] = 58 + __o['809'] = 32 + __o['810'] = 67 + __o['811'] = 97 + __o['812'] = 110 + __o['813'] = 110 + __o['814'] = 111 + __o['815'] = 116 + __o['816'] = 32 + __o['817'] = 99 + __o['818'] = 114 + __o['819'] = 101 + __o['820'] = 97 + __o['821'] = 116 + __o['822'] = 101 + __o['823'] = 47 + __o['824'] = 100 + __o['825'] = 101 + __o['826'] = 108 + __o['827'] = 101 + __o['828'] = 116 + __o['829'] = 101 + __o['830'] = 32 + __o['831'] = 97 + __o['832'] = 32 + __o['833'] = 67 + __o['834'] = 108 + __o['835'] = 111 + __o['836'] = 99 + __o['837'] = 107 + __o['838'] = 32 + __o['839'] = 102 + __o['840'] = 114 + __o['841'] = 111 + __o['842'] = 109 + __o['843'] = 32 + __o['844'] = 72 + __o['845'] = 119 + __o['846'] = 105 + __o['847'] = 32 + __o['848'] = 111 + __o['849'] = 114 + __o['850'] = 32 + __o['851'] = 83 + __o['852'] = 119 + __o['853'] = 105 + __o['854'] = 32 + __o['855'] = 116 + __o['856'] = 104 + __o['857'] = 114 + __o['858'] = 101 + __o['859'] = 97 + __o['860'] = 100 + __o['861'] = 46 + __o['862'] = 0 + __o['863'] = 65 + __o['864'] = 95 + __o['865'] = 110 + __o['866'] = 117 + __o['867'] = 108 + __o['868'] = 108 + __o['869'] = 69 + __o['870'] = 118 + __o['871'] = 101 + __o['872'] = 110 + __o['873'] = 116 + __o['874'] = 77 + __o['875'] = 97 + __o['876'] = 115 + __o['877'] = 107 + __o['878'] = 115 + __o['879'] = 58 + __o['880'] = 32 + __o['881'] = 111 + __o['882'] = 114 + __o['883'] = 77 + __o['884'] = 97 + __o['885'] = 115 + __o['886'] = 107 + __o['887'] = 32 + __o['888'] = 97 + __o['889'] = 110 + __o['890'] = 100 + __o['891'] = 32 + __o['892'] = 97 + __o['893'] = 110 + __o['894'] = 100 + __o['895'] = 77 + __o['896'] = 97 + __o['897'] = 115 + __o['898'] = 107 + __o['899'] = 32 + __o['900'] = 97 + __o['901'] = 114 + __o['902'] = 101 + __o['903'] = 32 + __o['904'] = 110 + __o['905'] = 117 + __o['906'] = 108 + __o['907'] = 108 + __o['908'] = 46 + __o['909'] = 0 + __o['910'] = 65 + __o['911'] = 95 + __o['912'] = 110 + __o['913'] = 117 + __o['914'] = 108 + __o['915'] = 108 + __o['916'] = 69 + __o['917'] = 118 + __o['918'] = 101 + __o['919'] = 110 + __o['920'] = 116 + __o['921'] = 73 + __o['922'] = 100 + __o['923'] = 58 + __o['924'] = 32 + __o['925'] = 112 + __o['926'] = 111 + __o['927'] = 115 + __o['928'] = 116 + __o['929'] = 101 + __o['930'] = 100 + __o['931'] = 32 + __o['932'] = 101 + __o['933'] = 118 + __o['934'] = 101 + __o['935'] = 110 + __o['936'] = 116 + __o['937'] = 73 + __o['938'] = 100 + __o['939'] = 32 + __o['940'] = 105 + __o['941'] = 115 + __o['942'] = 32 + __o['943'] = 110 + __o['944'] = 117 + __o['945'] = 108 + __o['946'] = 108 + __o['947'] = 46 + __o['948'] = 0 + __o['949'] = 65 + __o['950'] = 95 + __o['951'] = 101 + __o['952'] = 118 + __o['953'] = 101 + __o['954'] = 110 + __o['955'] = 116 + __o['956'] = 73 + __o['957'] = 110 + __o['958'] = 85 + __o['959'] = 115 + __o['960'] = 101 + __o['961'] = 58 + __o['962'] = 32 + __o['963'] = 69 + __o['964'] = 118 + __o['965'] = 101 + __o['966'] = 110 + __o['967'] = 116 + __o['968'] = 32 + __o['969'] = 111 + __o['970'] = 98 + __o['971'] = 106 + __o['972'] = 101 + __o['973'] = 99 + __o['974'] = 116 + __o['975'] = 32 + __o['976'] = 97 + __o['977'] = 108 + __o['978'] = 114 + __o['979'] = 101 + __o['980'] = 97 + __o['981'] = 100 + __o['982'] = 121 + __o['983'] = 32 + __o['984'] = 105 + __o['985'] = 110 + __o['986'] = 32 + __o['987'] = 117 + __o['988'] = 115 + __o['989'] = 101 + __o['990'] = 46 + __o['991'] = 0 + __o['992'] = 65 + __o['993'] = 95 + __o['994'] = 98 + __o['995'] = 97 + __o['996'] = 100 + __o['997'] = 67 + __o['998'] = 111 + __o['999'] = 110 + __o['1000'] = 116 + __o['1001'] = 101 + __o['1002'] = 120 + __o['1003'] = 116 + __o['1004'] = 58 + __o['1005'] = 32 + __o['1006'] = 98 + __o['1007'] = 97 + __o['1008'] = 100 + __o['1009'] = 32 + __o['1010'] = 99 + __o['1011'] = 97 + __o['1012'] = 108 + __o['1013'] = 108 + __o['1014'] = 105 + __o['1015'] = 110 + __o['1016'] = 103 + __o['1017'] = 32 + __o['1018'] = 99 + __o['1019'] = 111 + __o['1020'] = 110 + __o['1021'] = 116 + __o['1022'] = 101 + __o['1023'] = 120 + __o['1024'] = 116 + __o['1025'] = 46 + __o['1026'] = 32 + __o['1027'] = 77 + __o['1028'] = 117 + __o['1029'] = 115 + __o['1030'] = 116 + __o['1031'] = 32 + __o['1032'] = 98 + __o['1033'] = 101 + __o['1034'] = 32 + __o['1035'] = 99 + __o['1036'] = 97 + __o['1037'] = 108 + __o['1038'] = 108 + __o['1039'] = 101 + __o['1040'] = 100 + __o['1041'] = 32 + __o['1042'] = 102 + __o['1043'] = 114 + __o['1044'] = 111 + __o['1045'] = 109 + __o['1046'] = 32 + __o['1047'] = 97 + __o['1048'] = 32 + __o['1049'] = 84 + __o['1050'] = 97 + __o['1051'] = 115 + __o['1052'] = 107 + __o['1053'] = 46 + __o['1054'] = 0 + __o['1055'] = 65 + __o['1056'] = 95 + __o['1057'] = 112 + __o['1058'] = 101 + __o['1059'] = 110 + __o['1060'] = 100 + __o['1061'] = 84 + __o['1062'] = 97 + __o['1063'] = 115 + __o['1064'] = 107 + __o['1065'] = 68 + __o['1066'] = 105 + __o['1067'] = 115 + __o['1068'] = 97 + __o['1069'] = 98 + __o['1070'] = 108 + __o['1071'] = 101 + __o['1072'] = 100 + __o['1073'] = 58 + __o['1074'] = 32 + __o['1075'] = 67 + __o['1076'] = 97 + __o['1077'] = 110 + __o['1078'] = 110 + __o['1079'] = 111 + __o['1080'] = 116 + __o['1081'] = 32 + __o['1082'] = 99 + __o['1083'] = 97 + __o['1084'] = 108 + __o['1085'] = 108 + __o['1086'] = 32 + __o['1087'] = 69 + __o['1088'] = 118 + __o['1089'] = 101 + __o['1090'] = 110 + __o['1091'] = 116 + __o['1092'] = 95 + __o['1093'] = 112 + __o['1094'] = 101 + __o['1095'] = 110 + __o['1096'] = 100 + __o['1097'] = 40 + __o['1098'] = 41 + __o['1099'] = 32 + __o['1100'] = 119 + __o['1101'] = 104 + __o['1102'] = 105 + __o['1103'] = 108 + __o['1104'] = 101 + __o['1105'] = 32 + __o['1106'] = 116 + __o['1107'] = 104 + __o['1108'] = 101 + __o['1109'] = 32 + __o['1110'] = 84 + __o['1111'] = 97 + __o['1112'] = 115 + __o['1113'] = 107 + __o['1114'] = 32 + __o['1115'] = 111 + __o['1116'] = 114 + __o['1117'] = 32 + __o['1118'] = 83 + __o['1119'] = 119 + __o['1120'] = 105 + __o['1121'] = 32 + __o['1122'] = 115 + __o['1123'] = 99 + __o['1124'] = 104 + __o['1125'] = 101 + __o['1126'] = 100 + __o['1127'] = 117 + __o['1128'] = 108 + __o['1129'] = 101 + __o['1130'] = 114 + __o['1131'] = 32 + __o['1132'] = 105 + __o['1133'] = 115 + __o['1134'] = 32 + __o['1135'] = 100 + __o['1136'] = 105 + __o['1137'] = 115 + __o['1138'] = 97 + __o['1139'] = 98 + __o['1140'] = 108 + __o['1141'] = 101 + __o['1142'] = 100 + __o['1143'] = 46 + __o['1144'] = 0 + __o['1145'] = 77 + __o['1146'] = 97 + __o['1147'] = 105 + __o['1148'] = 108 + __o['1149'] = 98 + __o['1150'] = 111 + __o['1151'] = 120 + __o['1152'] = 95 + __o['1153'] = 99 + __o['1154'] = 114 + __o['1155'] = 101 + __o['1156'] = 97 + __o['1157'] = 116 + __o['1158'] = 101 + __o['1159'] = 39 + __o['1160'] = 115 + __o['1161'] = 32 + __o['1162'] = 98 + __o['1163'] = 117 + __o['1164'] = 102 + __o['1165'] = 83 + __o['1166'] = 105 + __o['1167'] = 122 + __o['1168'] = 101 + __o['1169'] = 32 + __o['1170'] = 112 + __o['1171'] = 97 + __o['1172'] = 114 + __o['1173'] = 97 + __o['1174'] = 109 + __o['1175'] = 101 + __o['1176'] = 116 + __o['1177'] = 101 + __o['1178'] = 114 + __o['1179'] = 32 + __o['1180'] = 105 + __o['1181'] = 115 + __o['1182'] = 32 + __o['1183'] = 105 + __o['1184'] = 110 + __o['1185'] = 118 + __o['1186'] = 97 + __o['1187'] = 108 + __o['1188'] = 105 + __o['1189'] = 100 + __o['1190'] = 32 + __o['1191'] = 40 + __o['1192'] = 116 + __o['1193'] = 111 + __o['1194'] = 111 + __o['1195'] = 32 + __o['1196'] = 115 + __o['1197'] = 109 + __o['1198'] = 97 + __o['1199'] = 108 + __o['1200'] = 108 + __o['1201'] = 41 + __o['1202'] = 0 + __o['1203'] = 65 + __o['1204'] = 95 + __o['1205'] = 110 + __o['1206'] = 111 + __o['1207'] = 69 + __o['1208'] = 118 + __o['1209'] = 101 + __o['1210'] = 110 + __o['1211'] = 116 + __o['1212'] = 115 + __o['1213'] = 58 + __o['1214'] = 32 + __o['1215'] = 84 + __o['1216'] = 104 + __o['1217'] = 101 + __o['1218'] = 32 + __o['1219'] = 69 + __o['1220'] = 118 + __o['1221'] = 101 + __o['1222'] = 110 + __o['1223'] = 116 + __o['1224'] = 46 + __o['1225'] = 115 + __o['1226'] = 117 + __o['1227'] = 112 + __o['1228'] = 112 + __o['1229'] = 111 + __o['1230'] = 114 + __o['1231'] = 116 + __o['1232'] = 115 + __o['1233'] = 69 + __o['1234'] = 118 + __o['1235'] = 101 + __o['1236'] = 110 + __o['1237'] = 116 + __o['1238'] = 115 + __o['1239'] = 32 + __o['1240'] = 102 + __o['1241'] = 108 + __o['1242'] = 97 + __o['1243'] = 103 + __o['1244'] = 32 + __o['1245'] = 105 + __o['1246'] = 115 + __o['1247'] = 32 + __o['1248'] = 100 + __o['1249'] = 105 + __o['1250'] = 115 + __o['1251'] = 97 + __o['1252'] = 98 + __o['1253'] = 108 + __o['1254'] = 101 + __o['1255'] = 100 + __o['1256'] = 46 + __o['1257'] = 0 + __o['1258'] = 65 + __o['1259'] = 95 + __o['1260'] = 105 + __o['1261'] = 110 + __o['1262'] = 118 + __o['1263'] = 84 + __o['1264'] = 105 + __o['1265'] = 109 + __o['1266'] = 101 + __o['1267'] = 111 + __o['1268'] = 117 + __o['1269'] = 116 + __o['1270'] = 58 + __o['1271'] = 32 + __o['1272'] = 67 + __o['1273'] = 97 + __o['1274'] = 110 + __o['1275'] = 39 + __o['1276'] = 116 + __o['1277'] = 32 + __o['1278'] = 117 + __o['1279'] = 115 + __o['1280'] = 101 + __o['1281'] = 32 + __o['1282'] = 66 + __o['1283'] = 73 + __o['1284'] = 79 + __o['1285'] = 83 + __o['1286'] = 95 + __o['1287'] = 69 + __o['1288'] = 86 + __o['1289'] = 69 + __o['1290'] = 78 + __o['1291'] = 84 + __o['1292'] = 95 + __o['1293'] = 65 + __o['1294'] = 67 + __o['1295'] = 81 + __o['1296'] = 85 + __o['1297'] = 73 + __o['1298'] = 82 + __o['1299'] = 69 + __o['1300'] = 68 + __o['1301'] = 32 + __o['1302'] = 119 + __o['1303'] = 105 + __o['1304'] = 116 + __o['1305'] = 104 + __o['1306'] = 32 + __o['1307'] = 116 + __o['1308'] = 104 + __o['1309'] = 105 + __o['1310'] = 115 + __o['1311'] = 32 + __o['1312'] = 83 + __o['1313'] = 101 + __o['1314'] = 109 + __o['1315'] = 97 + __o['1316'] = 112 + __o['1317'] = 104 + __o['1318'] = 111 + __o['1319'] = 114 + __o['1320'] = 101 + __o['1321'] = 46 + __o['1322'] = 0 + __o['1323'] = 65 + __o['1324'] = 95 + __o['1325'] = 111 + __o['1326'] = 118 + __o['1327'] = 101 + __o['1328'] = 114 + __o['1329'] = 102 + __o['1330'] = 108 + __o['1331'] = 111 + __o['1332'] = 119 + __o['1333'] = 58 + __o['1334'] = 32 + __o['1335'] = 67 + __o['1336'] = 111 + __o['1337'] = 117 + __o['1338'] = 110 + __o['1339'] = 116 + __o['1340'] = 32 + __o['1341'] = 104 + __o['1342'] = 97 + __o['1343'] = 115 + __o['1344'] = 32 + __o['1345'] = 101 + __o['1346'] = 120 + __o['1347'] = 99 + __o['1348'] = 101 + __o['1349'] = 101 + __o['1350'] = 100 + __o['1351'] = 101 + __o['1352'] = 100 + __o['1353'] = 32 + __o['1354'] = 54 + __o['1355'] = 53 + __o['1356'] = 53 + __o['1357'] = 51 + __o['1358'] = 53 + __o['1359'] = 32 + __o['1360'] = 97 + __o['1361'] = 110 + __o['1362'] = 100 + __o['1363'] = 32 + __o['1364'] = 114 + __o['1365'] = 111 + __o['1366'] = 108 + __o['1367'] = 108 + __o['1368'] = 101 + __o['1369'] = 100 + __o['1370'] = 32 + __o['1371'] = 111 + __o['1372'] = 118 + __o['1373'] = 101 + __o['1374'] = 114 + __o['1375'] = 46 + __o['1376'] = 0 + __o['1377'] = 65 + __o['1378'] = 95 + __o['1379'] = 112 + __o['1380'] = 101 + __o['1381'] = 110 + __o['1382'] = 100 + __o['1383'] = 84 + __o['1384'] = 97 + __o['1385'] = 115 + __o['1386'] = 107 + __o['1387'] = 68 + __o['1388'] = 105 + __o['1389'] = 115 + __o['1390'] = 97 + __o['1391'] = 98 + __o['1392'] = 108 + __o['1393'] = 101 + __o['1394'] = 100 + __o['1395'] = 58 + __o['1396'] = 32 + __o['1397'] = 67 + __o['1398'] = 97 + __o['1399'] = 110 + __o['1400'] = 110 + __o['1401'] = 111 + __o['1402'] = 116 + __o['1403'] = 32 + __o['1404'] = 99 + __o['1405'] = 97 + __o['1406'] = 108 + __o['1407'] = 108 + __o['1408'] = 32 + __o['1409'] = 83 + __o['1410'] = 101 + __o['1411'] = 109 + __o['1412'] = 97 + __o['1413'] = 112 + __o['1414'] = 104 + __o['1415'] = 111 + __o['1416'] = 114 + __o['1417'] = 101 + __o['1418'] = 95 + __o['1419'] = 112 + __o['1420'] = 101 + __o['1421'] = 110 + __o['1422'] = 100 + __o['1423'] = 40 + __o['1424'] = 41 + __o['1425'] = 32 + __o['1426'] = 119 + __o['1427'] = 104 + __o['1428'] = 105 + __o['1429'] = 108 + __o['1430'] = 101 + __o['1431'] = 32 + __o['1432'] = 116 + __o['1433'] = 104 + __o['1434'] = 101 + __o['1435'] = 32 + __o['1436'] = 84 + __o['1437'] = 97 + __o['1438'] = 115 + __o['1439'] = 107 + __o['1440'] = 32 + __o['1441'] = 111 + __o['1442'] = 114 + __o['1443'] = 32 + __o['1444'] = 83 + __o['1445'] = 119 + __o['1446'] = 105 + __o['1447'] = 32 + __o['1448'] = 115 + __o['1449'] = 99 + __o['1450'] = 104 + __o['1451'] = 101 + __o['1452'] = 100 + __o['1453'] = 117 + __o['1454'] = 108 + __o['1455'] = 101 + __o['1456'] = 114 + __o['1457'] = 32 + __o['1458'] = 105 + __o['1459'] = 115 + __o['1460'] = 32 + __o['1461'] = 100 + __o['1462'] = 105 + __o['1463'] = 115 + __o['1464'] = 97 + __o['1465'] = 98 + __o['1466'] = 108 + __o['1467'] = 101 + __o['1468'] = 100 + __o['1469'] = 46 + __o['1470'] = 0 + __o['1471'] = 65 + __o['1472'] = 95 + __o['1473'] = 115 + __o['1474'] = 119 + __o['1475'] = 105 + __o['1476'] = 68 + __o['1477'] = 105 + __o['1478'] = 115 + __o['1479'] = 97 + __o['1480'] = 98 + __o['1481'] = 108 + __o['1482'] = 101 + __o['1483'] = 100 + __o['1484'] = 58 + __o['1485'] = 32 + __o['1486'] = 67 + __o['1487'] = 97 + __o['1488'] = 110 + __o['1489'] = 110 + __o['1490'] = 111 + __o['1491'] = 116 + __o['1492'] = 32 + __o['1493'] = 99 + __o['1494'] = 114 + __o['1495'] = 101 + __o['1496'] = 97 + __o['1497'] = 116 + __o['1498'] = 101 + __o['1499'] = 32 + __o['1500'] = 97 + __o['1501'] = 32 + __o['1502'] = 83 + __o['1503'] = 119 + __o['1504'] = 105 + __o['1505'] = 32 + __o['1506'] = 119 + __o['1507'] = 104 + __o['1508'] = 101 + __o['1509'] = 110 + __o['1510'] = 32 + __o['1511'] = 83 + __o['1512'] = 119 + __o['1513'] = 105 + __o['1514'] = 32 + __o['1515'] = 105 + __o['1516'] = 115 + __o['1517'] = 32 + __o['1518'] = 100 + __o['1519'] = 105 + __o['1520'] = 115 + __o['1521'] = 97 + __o['1522'] = 98 + __o['1523'] = 108 + __o['1524'] = 101 + __o['1525'] = 100 + __o['1526'] = 46 + __o['1527'] = 0 + __o['1528'] = 65 + __o['1529'] = 95 + __o['1530'] = 98 + __o['1531'] = 97 + __o['1532'] = 100 + __o['1533'] = 80 + __o['1534'] = 114 + __o['1535'] = 105 + __o['1536'] = 111 + __o['1537'] = 114 + __o['1538'] = 105 + __o['1539'] = 116 + __o['1540'] = 121 + __o['1541'] = 58 + __o['1542'] = 32 + __o['1543'] = 65 + __o['1544'] = 110 + __o['1545'] = 32 + __o['1546'] = 105 + __o['1547'] = 110 + __o['1548'] = 118 + __o['1549'] = 97 + __o['1550'] = 108 + __o['1551'] = 105 + __o['1552'] = 100 + __o['1553'] = 32 + __o['1554'] = 83 + __o['1555'] = 119 + __o['1556'] = 105 + __o['1557'] = 32 + __o['1558'] = 112 + __o['1559'] = 114 + __o['1560'] = 105 + __o['1561'] = 111 + __o['1562'] = 114 + __o['1563'] = 105 + __o['1564'] = 116 + __o['1565'] = 121 + __o['1566'] = 32 + __o['1567'] = 119 + __o['1568'] = 97 + __o['1569'] = 115 + __o['1570'] = 32 + __o['1571'] = 117 + __o['1572'] = 115 + __o['1573'] = 101 + __o['1574'] = 100 + __o['1575'] = 46 + __o['1576'] = 0 + __o['1577'] = 65 + __o['1578'] = 95 + __o['1579'] = 98 + __o['1580'] = 97 + __o['1581'] = 100 + __o['1582'] = 84 + __o['1583'] = 104 + __o['1584'] = 114 + __o['1585'] = 101 + __o['1586'] = 97 + __o['1587'] = 100 + __o['1588'] = 84 + __o['1589'] = 121 + __o['1590'] = 112 + __o['1591'] = 101 + __o['1592'] = 58 + __o['1593'] = 32 + __o['1594'] = 67 + __o['1595'] = 97 + __o['1596'] = 110 + __o['1597'] = 110 + __o['1598'] = 111 + __o['1599'] = 116 + __o['1600'] = 32 + __o['1601'] = 99 + __o['1602'] = 114 + __o['1603'] = 101 + __o['1604'] = 97 + __o['1605'] = 116 + __o['1606'] = 101 + __o['1607'] = 47 + __o['1608'] = 100 + __o['1609'] = 101 + __o['1610'] = 108 + __o['1611'] = 101 + __o['1612'] = 116 + __o['1613'] = 101 + __o['1614'] = 32 + __o['1615'] = 97 + __o['1616'] = 32 + __o['1617'] = 116 + __o['1618'] = 97 + __o['1619'] = 115 + __o['1620'] = 107 + __o['1621'] = 32 + __o['1622'] = 102 + __o['1623'] = 114 + __o['1624'] = 111 + __o['1625'] = 109 + __o['1626'] = 32 + __o['1627'] = 72 + __o['1628'] = 119 + __o['1629'] = 105 + __o['1630'] = 32 + __o['1631'] = 111 + __o['1632'] = 114 + __o['1633'] = 32 + __o['1634'] = 83 + __o['1635'] = 119 + __o['1636'] = 105 + __o['1637'] = 32 + __o['1638'] = 116 + __o['1639'] = 104 + __o['1640'] = 114 + __o['1641'] = 101 + __o['1642'] = 97 + __o['1643'] = 100 + __o['1644'] = 46 + __o['1645'] = 0 + __o['1646'] = 65 + __o['1647'] = 95 + __o['1648'] = 98 + __o['1649'] = 97 + __o['1650'] = 100 + __o['1651'] = 84 + __o['1652'] = 97 + __o['1653'] = 115 + __o['1654'] = 107 + __o['1655'] = 83 + __o['1656'] = 116 + __o['1657'] = 97 + __o['1658'] = 116 + __o['1659'] = 101 + __o['1660'] = 58 + __o['1661'] = 32 + __o['1662'] = 67 + __o['1663'] = 97 + __o['1664'] = 110 + __o['1665'] = 39 + __o['1666'] = 116 + __o['1667'] = 32 + __o['1668'] = 100 + __o['1669'] = 101 + __o['1670'] = 108 + __o['1671'] = 101 + __o['1672'] = 116 + __o['1673'] = 101 + __o['1674'] = 32 + __o['1675'] = 97 + __o['1676'] = 32 + __o['1677'] = 116 + __o['1678'] = 97 + __o['1679'] = 115 + __o['1680'] = 107 + __o['1681'] = 32 + __o['1682'] = 105 + __o['1683'] = 110 + __o['1684'] = 32 + __o['1685'] = 82 + __o['1686'] = 85 + __o['1687'] = 78 + __o['1688'] = 78 + __o['1689'] = 73 + __o['1690'] = 78 + __o['1691'] = 71 + __o['1692'] = 32 + __o['1693'] = 115 + __o['1694'] = 116 + __o['1695'] = 97 + __o['1696'] = 116 + __o['1697'] = 101 + __o['1698'] = 46 + __o['1699'] = 0 + __o['1700'] = 65 + __o['1701'] = 95 + __o['1702'] = 110 + __o['1703'] = 111 + __o['1704'] = 80 + __o['1705'] = 101 + __o['1706'] = 110 + __o['1707'] = 100 + __o['1708'] = 69 + __o['1709'] = 108 + __o['1710'] = 101 + __o['1711'] = 109 + __o['1712'] = 58 + __o['1713'] = 32 + __o['1714'] = 78 + __o['1715'] = 111 + __o['1716'] = 116 + __o['1717'] = 32 + __o['1718'] = 101 + __o['1719'] = 110 + __o['1720'] = 111 + __o['1721'] = 117 + __o['1722'] = 103 + __o['1723'] = 104 + __o['1724'] = 32 + __o['1725'] = 105 + __o['1726'] = 110 + __o['1727'] = 102 + __o['1728'] = 111 + __o['1729'] = 32 + __o['1730'] = 116 + __o['1731'] = 111 + __o['1732'] = 32 + __o['1733'] = 100 + __o['1734'] = 101 + __o['1735'] = 108 + __o['1736'] = 101 + __o['1737'] = 116 + __o['1738'] = 101 + __o['1739'] = 32 + __o['1740'] = 66 + __o['1741'] = 76 + __o['1742'] = 79 + __o['1743'] = 67 + __o['1744'] = 75 + __o['1745'] = 69 + __o['1746'] = 68 + __o['1747'] = 32 + __o['1748'] = 116 + __o['1749'] = 97 + __o['1750'] = 115 + __o['1751'] = 107 + __o['1752'] = 46 + __o['1753'] = 0 + __o['1754'] = 65 + __o['1755'] = 95 + __o['1756'] = 116 + __o['1757'] = 97 + __o['1758'] = 115 + __o['1759'] = 107 + __o['1760'] = 68 + __o['1761'] = 105 + __o['1762'] = 115 + __o['1763'] = 97 + __o['1764'] = 98 + __o['1765'] = 108 + __o['1766'] = 101 + __o['1767'] = 100 + __o['1768'] = 58 + __o['1769'] = 32 + __o['1770'] = 67 + __o['1771'] = 97 + __o['1772'] = 110 + __o['1773'] = 110 + __o['1774'] = 111 + __o['1775'] = 116 + __o['1776'] = 32 + __o['1777'] = 99 + __o['1778'] = 114 + __o['1779'] = 101 + __o['1780'] = 97 + __o['1781'] = 116 + __o['1782'] = 101 + __o['1783'] = 32 + __o['1784'] = 97 + __o['1785'] = 32 + __o['1786'] = 116 + __o['1787'] = 97 + __o['1788'] = 115 + __o['1789'] = 107 + __o['1790'] = 32 + __o['1791'] = 119 + __o['1792'] = 104 + __o['1793'] = 101 + __o['1794'] = 110 + __o['1795'] = 32 + __o['1796'] = 116 + __o['1797'] = 97 + __o['1798'] = 115 + __o['1799'] = 107 + __o['1800'] = 105 + __o['1801'] = 110 + __o['1802'] = 103 + __o['1803'] = 32 + __o['1804'] = 105 + __o['1805'] = 115 + __o['1806'] = 32 + __o['1807'] = 100 + __o['1808'] = 105 + __o['1809'] = 115 + __o['1810'] = 97 + __o['1811'] = 98 + __o['1812'] = 108 + __o['1813'] = 101 + __o['1814'] = 100 + __o['1815'] = 46 + __o['1816'] = 0 + __o['1817'] = 65 + __o['1818'] = 95 + __o['1819'] = 98 + __o['1820'] = 97 + __o['1821'] = 100 + __o['1822'] = 80 + __o['1823'] = 114 + __o['1824'] = 105 + __o['1825'] = 111 + __o['1826'] = 114 + __o['1827'] = 105 + __o['1828'] = 116 + __o['1829'] = 121 + __o['1830'] = 58 + __o['1831'] = 32 + __o['1832'] = 65 + __o['1833'] = 110 + __o['1834'] = 32 + __o['1835'] = 105 + __o['1836'] = 110 + __o['1837'] = 118 + __o['1838'] = 97 + __o['1839'] = 108 + __o['1840'] = 105 + __o['1841'] = 100 + __o['1842'] = 32 + __o['1843'] = 116 + __o['1844'] = 97 + __o['1845'] = 115 + __o['1846'] = 107 + __o['1847'] = 32 + __o['1848'] = 112 + __o['1849'] = 114 + __o['1850'] = 105 + __o['1851'] = 111 + __o['1852'] = 114 + __o['1853'] = 105 + __o['1854'] = 116 + __o['1855'] = 121 + __o['1856'] = 32 + __o['1857'] = 119 + __o['1858'] = 97 + __o['1859'] = 115 + __o['1860'] = 32 + __o['1861'] = 117 + __o['1862'] = 115 + __o['1863'] = 101 + __o['1864'] = 100 + __o['1865'] = 46 + __o['1866'] = 0 + __o['1867'] = 65 + __o['1868'] = 95 + __o['1869'] = 98 + __o['1870'] = 97 + __o['1871'] = 100 + __o['1872'] = 84 + __o['1873'] = 105 + __o['1874'] = 109 + __o['1875'] = 101 + __o['1876'] = 111 + __o['1877'] = 117 + __o['1878'] = 116 + __o['1879'] = 58 + __o['1880'] = 32 + __o['1881'] = 67 + __o['1882'] = 97 + __o['1883'] = 110 + __o['1884'] = 39 + __o['1885'] = 116 + __o['1886'] = 32 + __o['1887'] = 115 + __o['1888'] = 108 + __o['1889'] = 101 + __o['1890'] = 101 + __o['1891'] = 112 + __o['1892'] = 32 + __o['1893'] = 70 + __o['1894'] = 79 + __o['1895'] = 82 + __o['1896'] = 69 + __o['1897'] = 86 + __o['1898'] = 69 + __o['1899'] = 82 + __o['1900'] = 46 + __o['1901'] = 0 + __o['1902'] = 65 + __o['1903'] = 95 + __o['1904'] = 98 + __o['1905'] = 97 + __o['1906'] = 100 + __o['1907'] = 65 + __o['1908'] = 102 + __o['1909'] = 102 + __o['1910'] = 105 + __o['1911'] = 110 + __o['1912'] = 105 + __o['1913'] = 116 + __o['1914'] = 121 + __o['1915'] = 58 + __o['1916'] = 32 + __o['1917'] = 73 + __o['1918'] = 110 + __o['1919'] = 118 + __o['1920'] = 97 + __o['1921'] = 108 + __o['1922'] = 105 + __o['1923'] = 100 + __o['1924'] = 32 + __o['1925'] = 97 + __o['1926'] = 102 + __o['1927'] = 102 + __o['1928'] = 105 + __o['1929'] = 110 + __o['1930'] = 105 + __o['1931'] = 116 + __o['1932'] = 121 + __o['1933'] = 46 + __o['1934'] = 0 + __o['1935'] = 65 + __o['1936'] = 95 + __o['1937'] = 115 + __o['1938'] = 108 + __o['1939'] = 101 + __o['1940'] = 101 + __o['1941'] = 112 + __o['1942'] = 84 + __o['1943'] = 97 + __o['1944'] = 115 + __o['1945'] = 107 + __o['1946'] = 68 + __o['1947'] = 105 + __o['1948'] = 115 + __o['1949'] = 97 + __o['1950'] = 98 + __o['1951'] = 108 + __o['1952'] = 101 + __o['1953'] = 100 + __o['1954'] = 58 + __o['1955'] = 32 + __o['1956'] = 67 + __o['1957'] = 97 + __o['1958'] = 110 + __o['1959'] = 110 + __o['1960'] = 111 + __o['1961'] = 116 + __o['1962'] = 32 + __o['1963'] = 99 + __o['1964'] = 97 + __o['1965'] = 108 + __o['1966'] = 108 + __o['1967'] = 32 + __o['1968'] = 84 + __o['1969'] = 97 + __o['1970'] = 115 + __o['1971'] = 107 + __o['1972'] = 95 + __o['1973'] = 115 + __o['1974'] = 108 + __o['1975'] = 101 + __o['1976'] = 101 + __o['1977'] = 112 + __o['1978'] = 40 + __o['1979'] = 41 + __o['1980'] = 32 + __o['1981'] = 119 + __o['1982'] = 104 + __o['1983'] = 105 + __o['1984'] = 108 + __o['1985'] = 101 + __o['1986'] = 32 + __o['1987'] = 116 + __o['1988'] = 104 + __o['1989'] = 101 + __o['1990'] = 32 + __o['1991'] = 84 + __o['1992'] = 97 + __o['1993'] = 115 + __o['1994'] = 107 + __o['1995'] = 32 + __o['1996'] = 115 + __o['1997'] = 99 + __o['1998'] = 104 + __o['1999'] = 101 + __o['2000'] = 100 + __o['2001'] = 117 + __o['2002'] = 108 + __o['2003'] = 101 + __o['2004'] = 114 + __o['2005'] = 32 + __o['2006'] = 105 + __o['2007'] = 115 + __o['2008'] = 32 + __o['2009'] = 100 + __o['2010'] = 105 + __o['2011'] = 115 + __o['2012'] = 97 + __o['2013'] = 98 + __o['2014'] = 108 + __o['2015'] = 101 + __o['2016'] = 100 + __o['2017'] = 46 + __o['2018'] = 0 + __o['2019'] = 65 + __o['2020'] = 95 + __o['2021'] = 105 + __o['2022'] = 110 + __o['2023'] = 118 + __o['2024'] = 97 + __o['2025'] = 108 + __o['2026'] = 105 + __o['2027'] = 100 + __o['2028'] = 67 + __o['2029'] = 111 + __o['2030'] = 114 + __o['2031'] = 101 + __o['2032'] = 73 + __o['2033'] = 100 + __o['2034'] = 58 + __o['2035'] = 32 + __o['2036'] = 67 + __o['2037'] = 97 + __o['2038'] = 110 + __o['2039'] = 110 + __o['2040'] = 111 + __o['2041'] = 116 + __o['2042'] = 32 + __o['2043'] = 112 + __o['2044'] = 97 + __o['2045'] = 115 + __o['2046'] = 115 + __o['2047'] = 32 + __o['2048'] = 97 + __o['2049'] = 32 + __o['2050'] = 110 + __o['2051'] = 111 + __o['2052'] = 110 + __o['2053'] = 45 + __o['2054'] = 122 + __o['2055'] = 101 + __o['2056'] = 114 + __o['2057'] = 111 + __o['2058'] = 32 + __o['2059'] = 67 + __o['2060'] = 111 + __o['2061'] = 114 + __o['2062'] = 101 + __o['2063'] = 73 + __o['2064'] = 100 + __o['2065'] = 32 + __o['2066'] = 105 + __o['2067'] = 110 + __o['2068'] = 32 + __o['2069'] = 97 + __o['2070'] = 32 + __o['2071'] = 110 + __o['2072'] = 111 + __o['2073'] = 110 + __o['2074'] = 45 + __o['2075'] = 83 + __o['2076'] = 77 + __o['2077'] = 80 + __o['2078'] = 32 + __o['2079'] = 97 + __o['2080'] = 112 + __o['2081'] = 112 + __o['2082'] = 108 + __o['2083'] = 105 + __o['2084'] = 99 + __o['2085'] = 97 + __o['2086'] = 116 + __o['2087'] = 105 + __o['2088'] = 111 + __o['2089'] = 110 + __o['2090'] = 46 + __o['2091'] = 0 + __o['2092'] = 65 + __o['2093'] = 95 + __o['2094'] = 117 + __o['2095'] = 110 + __o['2096'] = 115 + __o['2097'] = 117 + __o['2098'] = 112 + __o['2099'] = 112 + __o['2100'] = 111 + __o['2101'] = 114 + __o['2102'] = 116 + __o['2103'] = 101 + __o['2104'] = 100 + __o['2105'] = 77 + __o['2106'] = 97 + __o['2107'] = 115 + __o['2108'] = 107 + __o['2109'] = 105 + __o['2110'] = 110 + __o['2111'] = 103 + __o['2112'] = 79 + __o['2113'] = 112 + __o['2114'] = 116 + __o['2115'] = 105 + __o['2116'] = 111 + __o['2117'] = 110 + __o['2118'] = 58 + __o['2119'] = 32 + __o['2120'] = 117 + __o['2121'] = 110 + __o['2122'] = 115 + __o['2123'] = 117 + __o['2124'] = 112 + __o['2125'] = 112 + __o['2126'] = 111 + __o['2127'] = 114 + __o['2128'] = 116 + __o['2129'] = 101 + __o['2130'] = 100 + __o['2131'] = 32 + __o['2132'] = 109 + __o['2133'] = 97 + __o['2134'] = 115 + __o['2135'] = 107 + __o['2136'] = 83 + __o['2137'] = 101 + __o['2138'] = 116 + __o['2139'] = 116 + __o['2140'] = 105 + __o['2141'] = 110 + __o['2142'] = 103 + __o['2143'] = 46 + __o['2144'] = 0 + __o['2145'] = 65 + __o['2146'] = 95 + __o['2147'] = 122 + __o['2148'] = 101 + __o['2149'] = 114 + __o['2150'] = 111 + __o['2151'] = 84 + __o['2152'] = 105 + __o['2153'] = 109 + __o['2154'] = 101 + __o['2155'] = 111 + __o['2156'] = 117 + __o['2157'] = 116 + __o['2158'] = 58 + __o['2159'] = 32 + __o['2160'] = 84 + __o['2161'] = 105 + __o['2162'] = 109 + __o['2163'] = 101 + __o['2164'] = 111 + __o['2165'] = 117 + __o['2166'] = 116 + __o['2167'] = 32 + __o['2168'] = 118 + __o['2169'] = 97 + __o['2170'] = 108 + __o['2171'] = 117 + __o['2172'] = 101 + __o['2173'] = 32 + __o['2174'] = 97 + __o['2175'] = 110 + __o['2176'] = 110 + __o['2177'] = 111 + __o['2178'] = 116 + __o['2179'] = 32 + __o['2180'] = 98 + __o['2181'] = 101 + __o['2182'] = 32 + __o['2183'] = 122 + __o['2184'] = 101 + __o['2185'] = 114 + __o['2186'] = 111 + __o['2187'] = 0 + __o['2188'] = 65 + __o['2189'] = 95 + __o['2190'] = 105 + __o['2191'] = 110 + __o['2192'] = 118 + __o['2193'] = 97 + __o['2194'] = 108 + __o['2195'] = 105 + __o['2196'] = 100 + __o['2197'] = 75 + __o['2198'] = 101 + __o['2199'] = 121 + __o['2200'] = 58 + __o['2201'] = 32 + __o['2202'] = 116 + __o['2203'] = 104 + __o['2204'] = 101 + __o['2205'] = 32 + __o['2206'] = 107 + __o['2207'] = 101 + __o['2208'] = 121 + __o['2209'] = 32 + __o['2210'] = 109 + __o['2211'] = 117 + __o['2212'] = 115 + __o['2213'] = 116 + __o['2214'] = 32 + __o['2215'] = 98 + __o['2216'] = 101 + __o['2217'] = 32 + __o['2218'] = 115 + __o['2219'] = 101 + __o['2220'] = 116 + __o['2221'] = 32 + __o['2222'] = 116 + __o['2223'] = 111 + __o['2224'] = 32 + __o['2225'] = 97 + __o['2226'] = 32 + __o['2227'] = 110 + __o['2228'] = 111 + __o['2229'] = 110 + __o['2230'] = 45 + __o['2231'] = 100 + __o['2232'] = 101 + __o['2233'] = 102 + __o['2234'] = 97 + __o['2235'] = 117 + __o['2236'] = 108 + __o['2237'] = 116 + __o['2238'] = 32 + __o['2239'] = 118 + __o['2240'] = 97 + __o['2241'] = 108 + __o['2242'] = 117 + __o['2243'] = 101 + __o['2244'] = 0 + __o['2245'] = 65 + __o['2246'] = 95 + __o['2247'] = 98 + __o['2248'] = 97 + __o['2249'] = 100 + __o['2250'] = 67 + __o['2251'] = 111 + __o['2252'] = 110 + __o['2253'] = 116 + __o['2254'] = 101 + __o['2255'] = 120 + __o['2256'] = 116 + __o['2257'] = 58 + __o['2258'] = 32 + __o['2259'] = 98 + __o['2260'] = 97 + __o['2261'] = 100 + __o['2262'] = 32 + __o['2263'] = 99 + __o['2264'] = 97 + __o['2265'] = 108 + __o['2266'] = 108 + __o['2267'] = 105 + __o['2268'] = 110 + __o['2269'] = 103 + __o['2270'] = 32 + __o['2271'] = 99 + __o['2272'] = 111 + __o['2273'] = 110 + __o['2274'] = 116 + __o['2275'] = 101 + __o['2276'] = 120 + __o['2277'] = 116 + __o['2278'] = 46 + __o['2279'] = 32 + __o['2280'] = 77 + __o['2281'] = 97 + __o['2282'] = 121 + __o['2283'] = 32 + __o['2284'] = 110 + __o['2285'] = 111 + __o['2286'] = 116 + __o['2287'] = 32 + __o['2288'] = 98 + __o['2289'] = 101 + __o['2290'] = 32 + __o['2291'] = 101 + __o['2292'] = 110 + __o['2293'] = 116 + __o['2294'] = 101 + __o['2295'] = 114 + __o['2296'] = 101 + __o['2297'] = 100 + __o['2298'] = 32 + __o['2299'] = 102 + __o['2300'] = 114 + __o['2301'] = 111 + __o['2302'] = 109 + __o['2303'] = 32 + __o['2304'] = 97 + __o['2305'] = 32 + __o['2306'] = 104 + __o['2307'] = 97 + __o['2308'] = 114 + __o['2309'] = 100 + __o['2310'] = 119 + __o['2311'] = 97 + __o['2312'] = 114 + __o['2313'] = 101 + __o['2314'] = 32 + __o['2315'] = 105 + __o['2316'] = 110 + __o['2317'] = 116 + __o['2318'] = 101 + __o['2319'] = 114 + __o['2320'] = 114 + __o['2321'] = 117 + __o['2322'] = 112 + __o['2323'] = 116 + __o['2324'] = 32 + __o['2325'] = 116 + __o['2326'] = 104 + __o['2327'] = 114 + __o['2328'] = 101 + __o['2329'] = 97 + __o['2330'] = 100 + __o['2331'] = 46 + __o['2332'] = 0 + __o['2333'] = 65 + __o['2334'] = 95 + __o['2335'] = 98 + __o['2336'] = 97 + __o['2337'] = 100 + __o['2338'] = 67 + __o['2339'] = 111 + __o['2340'] = 110 + __o['2341'] = 116 + __o['2342'] = 101 + __o['2343'] = 120 + __o['2344'] = 116 + __o['2345'] = 58 + __o['2346'] = 32 + __o['2347'] = 98 + __o['2348'] = 97 + __o['2349'] = 100 + __o['2350'] = 32 + __o['2351'] = 99 + __o['2352'] = 97 + __o['2353'] = 108 + __o['2354'] = 108 + __o['2355'] = 105 + __o['2356'] = 110 + __o['2357'] = 103 + __o['2358'] = 32 + __o['2359'] = 99 + __o['2360'] = 111 + __o['2361'] = 110 + __o['2362'] = 116 + __o['2363'] = 101 + __o['2364'] = 120 + __o['2365'] = 116 + __o['2366'] = 46 + __o['2367'] = 32 + __o['2368'] = 77 + __o['2369'] = 97 + __o['2370'] = 121 + __o['2371'] = 32 + __o['2372'] = 110 + __o['2373'] = 111 + __o['2374'] = 116 + __o['2375'] = 32 + __o['2376'] = 98 + __o['2377'] = 101 + __o['2378'] = 32 + __o['2379'] = 101 + __o['2380'] = 110 + __o['2381'] = 116 + __o['2382'] = 101 + __o['2383'] = 114 + __o['2384'] = 101 + __o['2385'] = 100 + __o['2386'] = 32 + __o['2387'] = 102 + __o['2388'] = 114 + __o['2389'] = 111 + __o['2390'] = 109 + __o['2391'] = 32 + __o['2392'] = 97 + __o['2393'] = 32 + __o['2394'] = 115 + __o['2395'] = 111 + __o['2396'] = 102 + __o['2397'] = 116 + __o['2398'] = 119 + __o['2399'] = 97 + __o['2400'] = 114 + __o['2401'] = 101 + __o['2402'] = 32 + __o['2403'] = 111 + __o['2404'] = 114 + __o['2405'] = 32 + __o['2406'] = 104 + __o['2407'] = 97 + __o['2408'] = 114 + __o['2409'] = 100 + __o['2410'] = 119 + __o['2411'] = 97 + __o['2412'] = 114 + __o['2413'] = 101 + __o['2414'] = 32 + __o['2415'] = 105 + __o['2416'] = 110 + __o['2417'] = 116 + __o['2418'] = 101 + __o['2419'] = 114 + __o['2420'] = 114 + __o['2421'] = 117 + __o['2422'] = 112 + __o['2423'] = 116 + __o['2424'] = 32 + __o['2425'] = 116 + __o['2426'] = 104 + __o['2427'] = 114 + __o['2428'] = 101 + __o['2429'] = 97 + __o['2430'] = 100 + __o['2431'] = 46 + __o['2432'] = 0 + __o['2433'] = 65 + __o['2434'] = 95 + __o['2435'] = 98 + __o['2436'] = 97 + __o['2437'] = 100 + __o['2438'] = 67 + __o['2439'] = 111 + __o['2440'] = 110 + __o['2441'] = 116 + __o['2442'] = 101 + __o['2443'] = 120 + __o['2444'] = 116 + __o['2445'] = 58 + __o['2446'] = 32 + __o['2447'] = 98 + __o['2448'] = 97 + __o['2449'] = 100 + __o['2450'] = 32 + __o['2451'] = 99 + __o['2452'] = 97 + __o['2453'] = 108 + __o['2454'] = 108 + __o['2455'] = 105 + __o['2456'] = 110 + __o['2457'] = 103 + __o['2458'] = 32 + __o['2459'] = 99 + __o['2460'] = 111 + __o['2461'] = 110 + __o['2462'] = 116 + __o['2463'] = 101 + __o['2464'] = 120 + __o['2465'] = 116 + __o['2466'] = 46 + __o['2467'] = 32 + __o['2468'] = 83 + __o['2469'] = 101 + __o['2470'] = 101 + __o['2471'] = 32 + __o['2472'] = 71 + __o['2473'] = 97 + __o['2474'] = 116 + __o['2475'] = 101 + __o['2476'] = 77 + __o['2477'] = 117 + __o['2478'] = 116 + __o['2479'] = 101 + __o['2480'] = 120 + __o['2481'] = 80 + __o['2482'] = 114 + __o['2483'] = 105 + __o['2484'] = 32 + __o['2485'] = 65 + __o['2486'] = 80 + __o['2487'] = 73 + __o['2488'] = 32 + __o['2489'] = 100 + __o['2490'] = 111 + __o['2491'] = 99 + __o['2492'] = 32 + __o['2493'] = 102 + __o['2494'] = 111 + __o['2495'] = 114 + __o['2496'] = 32 + __o['2497'] = 100 + __o['2498'] = 101 + __o['2499'] = 116 + __o['2500'] = 97 + __o['2501'] = 105 + __o['2502'] = 108 + __o['2503'] = 115 + __o['2504'] = 46 + __o['2505'] = 0 + __o['2506'] = 65 + __o['2507'] = 95 + __o['2508'] = 101 + __o['2509'] = 110 + __o['2510'] = 116 + __o['2511'] = 101 + __o['2512'] = 114 + __o['2513'] = 84 + __o['2514'] = 97 + __o['2515'] = 115 + __o['2516'] = 107 + __o['2517'] = 68 + __o['2518'] = 105 + __o['2519'] = 115 + __o['2520'] = 97 + __o['2521'] = 98 + __o['2522'] = 108 + __o['2523'] = 101 + __o['2524'] = 100 + __o['2525'] = 58 + __o['2526'] = 32 + __o['2527'] = 67 + __o['2528'] = 97 + __o['2529'] = 110 + __o['2530'] = 110 + __o['2531'] = 111 + __o['2532'] = 116 + __o['2533'] = 32 + __o['2534'] = 99 + __o['2535'] = 97 + __o['2536'] = 108 + __o['2537'] = 108 + __o['2538'] = 32 + __o['2539'] = 71 + __o['2540'] = 97 + __o['2541'] = 116 + __o['2542'] = 101 + __o['2543'] = 77 + __o['2544'] = 117 + __o['2545'] = 116 + __o['2546'] = 101 + __o['2547'] = 120 + __o['2548'] = 80 + __o['2549'] = 114 + __o['2550'] = 105 + __o['2551'] = 95 + __o['2552'] = 101 + __o['2553'] = 110 + __o['2554'] = 116 + __o['2555'] = 101 + __o['2556'] = 114 + __o['2557'] = 40 + __o['2558'] = 41 + __o['2559'] = 32 + __o['2560'] = 119 + __o['2561'] = 104 + __o['2562'] = 105 + __o['2563'] = 108 + __o['2564'] = 101 + __o['2565'] = 32 + __o['2566'] = 116 + __o['2567'] = 104 + __o['2568'] = 101 + __o['2569'] = 32 + __o['2570'] = 84 + __o['2571'] = 97 + __o['2572'] = 115 + __o['2573'] = 107 + __o['2574'] = 32 + __o['2575'] = 111 + __o['2576'] = 114 + __o['2577'] = 32 + __o['2578'] = 83 + __o['2579'] = 119 + __o['2580'] = 105 + __o['2581'] = 32 + __o['2582'] = 115 + __o['2583'] = 99 + __o['2584'] = 104 + __o['2585'] = 101 + __o['2586'] = 100 + __o['2587'] = 117 + __o['2588'] = 108 + __o['2589'] = 101 + __o['2590'] = 114 + __o['2591'] = 32 + __o['2592'] = 105 + __o['2593'] = 115 + __o['2594'] = 32 + __o['2595'] = 100 + __o['2596'] = 105 + __o['2597'] = 115 + __o['2598'] = 97 + __o['2599'] = 98 + __o['2600'] = 108 + __o['2601'] = 101 + __o['2602'] = 100 + __o['2603'] = 46 + __o['2604'] = 0 + __o['2605'] = 65 + __o['2606'] = 95 + __o['2607'] = 98 + __o['2608'] = 97 + __o['2609'] = 100 + __o['2610'] = 67 + __o['2611'] = 111 + __o['2612'] = 110 + __o['2613'] = 116 + __o['2614'] = 101 + __o['2615'] = 120 + __o['2616'] = 116 + __o['2617'] = 58 + __o['2618'] = 32 + __o['2619'] = 98 + __o['2620'] = 97 + __o['2621'] = 100 + __o['2622'] = 32 + __o['2623'] = 99 + __o['2624'] = 97 + __o['2625'] = 108 + __o['2626'] = 108 + __o['2627'] = 105 + __o['2628'] = 110 + __o['2629'] = 103 + __o['2630'] = 32 + __o['2631'] = 99 + __o['2632'] = 111 + __o['2633'] = 110 + __o['2634'] = 116 + __o['2635'] = 101 + __o['2636'] = 120 + __o['2637'] = 116 + __o['2638'] = 46 + __o['2639'] = 32 + __o['2640'] = 83 + __o['2641'] = 101 + __o['2642'] = 101 + __o['2643'] = 32 + __o['2644'] = 71 + __o['2645'] = 97 + __o['2646'] = 116 + __o['2647'] = 101 + __o['2648'] = 77 + __o['2649'] = 117 + __o['2650'] = 116 + __o['2651'] = 101 + __o['2652'] = 120 + __o['2653'] = 32 + __o['2654'] = 65 + __o['2655'] = 80 + __o['2656'] = 73 + __o['2657'] = 32 + __o['2658'] = 100 + __o['2659'] = 111 + __o['2660'] = 99 + __o['2661'] = 32 + __o['2662'] = 102 + __o['2663'] = 111 + __o['2664'] = 114 + __o['2665'] = 32 + __o['2666'] = 100 + __o['2667'] = 101 + __o['2668'] = 116 + __o['2669'] = 97 + __o['2670'] = 105 + __o['2671'] = 108 + __o['2672'] = 115 + __o['2673'] = 46 + __o['2674'] = 0 + __o['2675'] = 65 + __o['2676'] = 95 + __o['2677'] = 98 + __o['2678'] = 97 + __o['2679'] = 100 + __o['2680'] = 67 + __o['2681'] = 111 + __o['2682'] = 110 + __o['2683'] = 116 + __o['2684'] = 101 + __o['2685'] = 120 + __o['2686'] = 116 + __o['2687'] = 58 + __o['2688'] = 32 + __o['2689'] = 98 + __o['2690'] = 97 + __o['2691'] = 100 + __o['2692'] = 32 + __o['2693'] = 99 + __o['2694'] = 97 + __o['2695'] = 108 + __o['2696'] = 108 + __o['2697'] = 105 + __o['2698'] = 110 + __o['2699'] = 103 + __o['2700'] = 32 + __o['2701'] = 99 + __o['2702'] = 111 + __o['2703'] = 110 + __o['2704'] = 116 + __o['2705'] = 101 + __o['2706'] = 120 + __o['2707'] = 116 + __o['2708'] = 46 + __o['2709'] = 32 + __o['2710'] = 83 + __o['2711'] = 101 + __o['2712'] = 101 + __o['2713'] = 32 + __o['2714'] = 71 + __o['2715'] = 97 + __o['2716'] = 116 + __o['2717'] = 101 + __o['2718'] = 83 + __o['2719'] = 112 + __o['2720'] = 105 + __o['2721'] = 110 + __o['2722'] = 108 + __o['2723'] = 111 + __o['2724'] = 99 + __o['2725'] = 107 + __o['2726'] = 32 + __o['2727'] = 65 + __o['2728'] = 80 + __o['2729'] = 73 + __o['2730'] = 32 + __o['2731'] = 100 + __o['2732'] = 111 + __o['2733'] = 99 + __o['2734'] = 32 + __o['2735'] = 102 + __o['2736'] = 111 + __o['2737'] = 114 + __o['2738'] = 32 + __o['2739'] = 100 + __o['2740'] = 101 + __o['2741'] = 116 + __o['2742'] = 97 + __o['2743'] = 105 + __o['2744'] = 108 + __o['2745'] = 115 + __o['2746'] = 46 + __o['2747'] = 0 + __o['2748'] = 65 + __o['2749'] = 95 + __o['2750'] = 105 + __o['2751'] = 110 + __o['2752'] = 118 + __o['2753'] = 97 + __o['2754'] = 108 + __o['2755'] = 105 + __o['2756'] = 100 + __o['2757'] = 81 + __o['2758'] = 117 + __o['2759'] = 97 + __o['2760'] = 108 + __o['2761'] = 105 + __o['2762'] = 116 + __o['2763'] = 121 + __o['2764'] = 58 + __o['2765'] = 32 + __o['2766'] = 83 + __o['2767'] = 101 + __o['2768'] = 101 + __o['2769'] = 32 + __o['2770'] = 71 + __o['2771'] = 97 + __o['2772'] = 116 + __o['2773'] = 101 + __o['2774'] = 83 + __o['2775'] = 112 + __o['2776'] = 105 + __o['2777'] = 110 + __o['2778'] = 108 + __o['2779'] = 111 + __o['2780'] = 99 + __o['2781'] = 107 + __o['2782'] = 32 + __o['2783'] = 65 + __o['2784'] = 80 + __o['2785'] = 73 + __o['2786'] = 32 + __o['2787'] = 100 + __o['2788'] = 111 + __o['2789'] = 99 + __o['2790'] = 32 + __o['2791'] = 102 + __o['2792'] = 111 + __o['2793'] = 114 + __o['2794'] = 32 + __o['2795'] = 100 + __o['2796'] = 101 + __o['2797'] = 116 + __o['2798'] = 97 + __o['2799'] = 105 + __o['2800'] = 108 + __o['2801'] = 115 + __o['2802'] = 46 + __o['2803'] = 0 + __o['2804'] = 98 + __o['2805'] = 117 + __o['2806'] = 102 + __o['2807'] = 32 + __o['2808'] = 112 + __o['2809'] = 97 + __o['2810'] = 114 + __o['2811'] = 97 + __o['2812'] = 109 + __o['2813'] = 101 + __o['2814'] = 116 + __o['2815'] = 101 + __o['2816'] = 114 + __o['2817'] = 32 + __o['2818'] = 99 + __o['2819'] = 97 + __o['2820'] = 110 + __o['2821'] = 110 + __o['2822'] = 111 + __o['2823'] = 116 + __o['2824'] = 32 + __o['2825'] = 98 + __o['2826'] = 101 + __o['2827'] = 32 + __o['2828'] = 110 + __o['2829'] = 117 + __o['2830'] = 108 + __o['2831'] = 108 + __o['2832'] = 0 + __o['2833'] = 98 + __o['2834'] = 117 + __o['2835'] = 102 + __o['2836'] = 32 + __o['2837'] = 110 + __o['2838'] = 111 + __o['2839'] = 116 + __o['2840'] = 32 + __o['2841'] = 112 + __o['2842'] = 114 + __o['2843'] = 111 + __o['2844'] = 112 + __o['2845'] = 101 + __o['2846'] = 114 + __o['2847'] = 108 + __o['2848'] = 121 + __o['2849'] = 32 + __o['2850'] = 97 + __o['2851'] = 108 + __o['2852'] = 105 + __o['2853'] = 103 + __o['2854'] = 110 + __o['2855'] = 101 + __o['2856'] = 100 + __o['2857'] = 0 + __o['2858'] = 97 + __o['2859'] = 108 + __o['2860'] = 105 + __o['2861'] = 103 + __o['2862'] = 110 + __o['2863'] = 32 + __o['2864'] = 112 + __o['2865'] = 97 + __o['2866'] = 114 + __o['2867'] = 97 + __o['2868'] = 109 + __o['2869'] = 101 + __o['2870'] = 116 + __o['2871'] = 101 + __o['2872'] = 114 + __o['2873'] = 32 + __o['2874'] = 109 + __o['2875'] = 117 + __o['2876'] = 115 + __o['2877'] = 116 + __o['2878'] = 32 + __o['2879'] = 98 + __o['2880'] = 101 + __o['2881'] = 32 + __o['2882'] = 48 + __o['2883'] = 32 + __o['2884'] = 111 + __o['2885'] = 114 + __o['2886'] = 32 + __o['2887'] = 97 + __o['2888'] = 32 + __o['2889'] = 112 + __o['2890'] = 111 + __o['2891'] = 119 + __o['2892'] = 101 + __o['2893'] = 114 + __o['2894'] = 32 + __o['2895'] = 111 + __o['2896'] = 102 + __o['2897'] = 32 + __o['2898'] = 50 + __o['2899'] = 32 + __o['2900'] = 62 + __o['2901'] = 61 + __o['2902'] = 32 + __o['2903'] = 116 + __o['2904'] = 104 + __o['2905'] = 101 + __o['2906'] = 32 + __o['2907'] = 118 + __o['2908'] = 97 + __o['2909'] = 108 + __o['2910'] = 117 + __o['2911'] = 101 + __o['2912'] = 32 + __o['2913'] = 111 + __o['2914'] = 102 + __o['2915'] = 32 + __o['2916'] = 77 + __o['2917'] = 101 + __o['2918'] = 109 + __o['2919'] = 111 + __o['2920'] = 114 + __o['2921'] = 121 + __o['2922'] = 95 + __o['2923'] = 103 + __o['2924'] = 101 + __o['2925'] = 116 + __o['2926'] = 77 + __o['2927'] = 97 + __o['2928'] = 120 + __o['2929'] = 68 + __o['2930'] = 101 + __o['2931'] = 102 + __o['2932'] = 97 + __o['2933'] = 117 + __o['2934'] = 108 + __o['2935'] = 116 + __o['2936'] = 84 + __o['2937'] = 121 + __o['2938'] = 112 + __o['2939'] = 101 + __o['2940'] = 65 + __o['2941'] = 108 + __o['2942'] = 105 + __o['2943'] = 103 + __o['2944'] = 110 + __o['2945'] = 40 + __o['2946'] = 41 + __o['2947'] = 0 + __o['2948'] = 97 + __o['2949'] = 108 + __o['2950'] = 105 + __o['2951'] = 103 + __o['2952'] = 110 + __o['2953'] = 32 + __o['2954'] = 112 + __o['2955'] = 97 + __o['2956'] = 114 + __o['2957'] = 97 + __o['2958'] = 109 + __o['2959'] = 101 + __o['2960'] = 116 + __o['2961'] = 101 + __o['2962'] = 114 + __o['2963'] = 32 + __o['2964'] = 49 + __o['2965'] = 41 + __o['2966'] = 32 + __o['2967'] = 109 + __o['2968'] = 117 + __o['2969'] = 115 + __o['2970'] = 116 + __o['2971'] = 32 + __o['2972'] = 98 + __o['2973'] = 101 + __o['2974'] = 32 + __o['2975'] = 48 + __o['2976'] = 32 + __o['2977'] = 111 + __o['2978'] = 114 + __o['2979'] = 32 + __o['2980'] = 97 + __o['2981'] = 32 + __o['2982'] = 112 + __o['2983'] = 111 + __o['2984'] = 119 + __o['2985'] = 101 + __o['2986'] = 114 + __o['2987'] = 32 + __o['2988'] = 111 + __o['2989'] = 102 + __o['2990'] = 32 + __o['2991'] = 50 + __o['2992'] = 32 + __o['2993'] = 97 + __o['2994'] = 110 + __o['2995'] = 100 + __o['2996'] = 32 + __o['2997'] = 50 + __o['2998'] = 41 + __o['2999'] = 32 + __o['3000'] = 110 + __o['3001'] = 111 + __o['3002'] = 116 + __o['3003'] = 32 + __o['3004'] = 103 + __o['3005'] = 114 + __o['3006'] = 101 + __o['3007'] = 97 + __o['3008'] = 116 + __o['3009'] = 101 + __o['3010'] = 114 + __o['3011'] = 32 + __o['3012'] = 116 + __o['3013'] = 104 + __o['3014'] = 97 + __o['3015'] = 110 + __o['3016'] = 32 + __o['3017'] = 116 + __o['3018'] = 104 + __o['3019'] = 101 + __o['3020'] = 32 + __o['3021'] = 104 + __o['3022'] = 101 + __o['3023'] = 97 + __o['3024'] = 112 + __o['3025'] = 115 + __o['3026'] = 32 + __o['3027'] = 97 + __o['3028'] = 108 + __o['3029'] = 105 + __o['3030'] = 103 + __o['3031'] = 110 + __o['3032'] = 109 + __o['3033'] = 101 + __o['3034'] = 110 + __o['3035'] = 116 + __o['3036'] = 0 + __o['3037'] = 98 + __o['3038'] = 108 + __o['3039'] = 111 + __o['3040'] = 99 + __o['3041'] = 107 + __o['3042'] = 83 + __o['3043'] = 105 + __o['3044'] = 122 + __o['3045'] = 101 + __o['3046'] = 32 + __o['3047'] = 109 + __o['3048'] = 117 + __o['3049'] = 115 + __o['3050'] = 116 + __o['3051'] = 32 + __o['3052'] = 98 + __o['3053'] = 101 + __o['3054'] = 32 + __o['3055'] = 108 + __o['3056'] = 97 + __o['3057'] = 114 + __o['3058'] = 103 + __o['3059'] = 101 + __o['3060'] = 32 + __o['3061'] = 101 + __o['3062'] = 110 + __o['3063'] = 111 + __o['3064'] = 117 + __o['3065'] = 103 + __o['3066'] = 104 + __o['3067'] = 32 + __o['3068'] = 116 + __o['3069'] = 111 + __o['3070'] = 32 + __o['3071'] = 104 + __o['3072'] = 111 + __o['3073'] = 108 + __o['3074'] = 100 + __o['3075'] = 32 + __o['3076'] = 97 + __o['3077'] = 116 + __o['3078'] = 108 + __o['3079'] = 101 + __o['3080'] = 97 + __o['3081'] = 115 + __o['3082'] = 116 + __o['3083'] = 32 + __o['3084'] = 116 + __o['3085'] = 119 + __o['3086'] = 111 + __o['3087'] = 32 + __o['3088'] = 112 + __o['3089'] = 111 + __o['3090'] = 105 + __o['3091'] = 110 + __o['3092'] = 116 + __o['3093'] = 101 + __o['3094'] = 114 + __o['3095'] = 115 + __o['3096'] = 0 + __o['3097'] = 110 + __o['3098'] = 117 + __o['3099'] = 109 + __o['3100'] = 66 + __o['3101'] = 108 + __o['3102'] = 111 + __o['3103'] = 99 + __o['3104'] = 107 + __o['3105'] = 115 + __o['3106'] = 32 + __o['3107'] = 99 + __o['3108'] = 97 + __o['3109'] = 110 + __o['3110'] = 110 + __o['3111'] = 111 + __o['3112'] = 116 + __o['3113'] = 32 + __o['3114'] = 98 + __o['3115'] = 101 + __o['3116'] = 32 + __o['3117'] = 122 + __o['3118'] = 101 + __o['3119'] = 114 + __o['3120'] = 111 + __o['3121'] = 0 + __o['3122'] = 98 + __o['3123'] = 117 + __o['3124'] = 102 + __o['3125'] = 83 + __o['3126'] = 105 + __o['3127'] = 122 + __o['3128'] = 101 + __o['3129'] = 32 + __o['3130'] = 99 + __o['3131'] = 97 + __o['3132'] = 110 + __o['3133'] = 110 + __o['3134'] = 111 + __o['3135'] = 116 + __o['3136'] = 32 + __o['3137'] = 98 + __o['3138'] = 101 + __o['3139'] = 32 + __o['3140'] = 122 + __o['3141'] = 101 + __o['3142'] = 114 + __o['3143'] = 111 + __o['3144'] = 0 + __o['3145'] = 72 + __o['3146'] = 101 + __o['3147'] = 97 + __o['3148'] = 112 + __o['3149'] = 66 + __o['3150'] = 117 + __o['3151'] = 102 + __o['3152'] = 95 + __o['3153'] = 99 + __o['3154'] = 114 + __o['3155'] = 101 + __o['3156'] = 97 + __o['3157'] = 116 + __o['3158'] = 101 + __o['3159'] = 39 + __o['3160'] = 115 + __o['3161'] = 32 + __o['3162'] = 98 + __o['3163'] = 117 + __o['3164'] = 102 + __o['3165'] = 83 + __o['3166'] = 105 + __o['3167'] = 122 + __o['3168'] = 101 + __o['3169'] = 32 + __o['3170'] = 112 + __o['3171'] = 97 + __o['3172'] = 114 + __o['3173'] = 97 + __o['3174'] = 109 + __o['3175'] = 101 + __o['3176'] = 116 + __o['3177'] = 101 + __o['3178'] = 114 + __o['3179'] = 32 + __o['3180'] = 105 + __o['3181'] = 115 + __o['3182'] = 32 + __o['3183'] = 105 + __o['3184'] = 110 + __o['3185'] = 118 + __o['3186'] = 97 + __o['3187'] = 108 + __o['3188'] = 105 + __o['3189'] = 100 + __o['3190'] = 32 + __o['3191'] = 40 + __o['3192'] = 116 + __o['3193'] = 111 + __o['3194'] = 111 + __o['3195'] = 32 + __o['3196'] = 115 + __o['3197'] = 109 + __o['3198'] = 97 + __o['3199'] = 108 + __o['3200'] = 108 + __o['3201'] = 41 + __o['3202'] = 0 + __o['3203'] = 67 + __o['3204'] = 97 + __o['3205'] = 110 + __o['3206'] = 110 + __o['3207'] = 111 + __o['3208'] = 116 + __o['3209'] = 32 + __o['3210'] = 99 + __o['3211'] = 97 + __o['3212'] = 108 + __o['3213'] = 108 + __o['3214'] = 32 + __o['3215'] = 72 + __o['3216'] = 101 + __o['3217'] = 97 + __o['3218'] = 112 + __o['3219'] = 66 + __o['3220'] = 117 + __o['3221'] = 102 + __o['3222'] = 95 + __o['3223'] = 102 + __o['3224'] = 114 + __o['3225'] = 101 + __o['3226'] = 101 + __o['3227'] = 32 + __o['3228'] = 119 + __o['3229'] = 104 + __o['3230'] = 101 + __o['3231'] = 110 + __o['3232'] = 32 + __o['3233'] = 110 + __o['3234'] = 111 + __o['3235'] = 32 + __o['3236'] = 98 + __o['3237'] = 108 + __o['3238'] = 111 + __o['3239'] = 99 + __o['3240'] = 107 + __o['3241'] = 115 + __o['3242'] = 32 + __o['3243'] = 104 + __o['3244'] = 97 + __o['3245'] = 118 + __o['3246'] = 101 + __o['3247'] = 32 + __o['3248'] = 98 + __o['3249'] = 101 + __o['3250'] = 101 + __o['3251'] = 110 + __o['3252'] = 32 + __o['3253'] = 97 + __o['3254'] = 108 + __o['3255'] = 108 + __o['3256'] = 111 + __o['3257'] = 99 + __o['3258'] = 97 + __o['3259'] = 116 + __o['3260'] = 101 + __o['3261'] = 100 + __o['3262'] = 0 + __o['3263'] = 65 + __o['3264'] = 95 + __o['3265'] = 105 + __o['3266'] = 110 + __o['3267'] = 118 + __o['3268'] = 97 + __o['3269'] = 108 + __o['3270'] = 105 + __o['3271'] = 100 + __o['3272'] = 70 + __o['3273'] = 114 + __o['3274'] = 101 + __o['3275'] = 101 + __o['3276'] = 58 + __o['3277'] = 32 + __o['3278'] = 73 + __o['3279'] = 110 + __o['3280'] = 118 + __o['3281'] = 97 + __o['3282'] = 108 + __o['3283'] = 105 + __o['3284'] = 100 + __o['3285'] = 32 + __o['3286'] = 102 + __o['3287'] = 114 + __o['3288'] = 101 + __o['3289'] = 101 + __o['3290'] = 0 + __o['3291'] = 65 + __o['3292'] = 95 + __o['3293'] = 122 + __o['3294'] = 101 + __o['3295'] = 114 + __o['3296'] = 111 + __o['3297'] = 66 + __o['3298'] = 108 + __o['3299'] = 111 + __o['3300'] = 99 + __o['3301'] = 107 + __o['3302'] = 58 + __o['3303'] = 32 + __o['3304'] = 67 + __o['3305'] = 97 + __o['3306'] = 110 + __o['3307'] = 110 + __o['3308'] = 111 + __o['3309'] = 116 + __o['3310'] = 32 + __o['3311'] = 97 + __o['3312'] = 108 + __o['3313'] = 108 + __o['3314'] = 111 + __o['3315'] = 99 + __o['3316'] = 97 + __o['3317'] = 116 + __o['3318'] = 101 + __o['3319'] = 32 + __o['3320'] = 115 + __o['3321'] = 105 + __o['3322'] = 122 + __o['3323'] = 101 + __o['3324'] = 32 + __o['3325'] = 48 + __o['3326'] = 0 + __o['3327'] = 65 + __o['3328'] = 95 + __o['3329'] = 104 + __o['3330'] = 101 + __o['3331'] = 97 + __o['3332'] = 112 + __o['3333'] = 83 + __o['3334'] = 105 + __o['3335'] = 122 + __o['3336'] = 101 + __o['3337'] = 58 + __o['3338'] = 32 + __o['3339'] = 82 + __o['3340'] = 101 + __o['3341'] = 113 + __o['3342'] = 117 + __o['3343'] = 101 + __o['3344'] = 115 + __o['3345'] = 116 + __o['3346'] = 101 + __o['3347'] = 100 + __o['3348'] = 32 + __o['3349'] = 104 + __o['3350'] = 101 + __o['3351'] = 97 + __o['3352'] = 112 + __o['3353'] = 32 + __o['3354'] = 115 + __o['3355'] = 105 + __o['3356'] = 122 + __o['3357'] = 101 + __o['3358'] = 32 + __o['3359'] = 105 + __o['3360'] = 115 + __o['3361'] = 32 + __o['3362'] = 116 + __o['3363'] = 111 + __o['3364'] = 111 + __o['3365'] = 32 + __o['3366'] = 115 + __o['3367'] = 109 + __o['3368'] = 97 + __o['3369'] = 108 + __o['3370'] = 108 + __o['3371'] = 0 + __o['3372'] = 65 + __o['3373'] = 95 + __o['3374'] = 97 + __o['3375'] = 108 + __o['3376'] = 105 + __o['3377'] = 103 + __o['3378'] = 110 + __o['3379'] = 58 + __o['3380'] = 32 + __o['3381'] = 82 + __o['3382'] = 101 + __o['3383'] = 113 + __o['3384'] = 117 + __o['3385'] = 101 + __o['3386'] = 115 + __o['3387'] = 116 + __o['3388'] = 101 + __o['3389'] = 100 + __o['3390'] = 32 + __o['3391'] = 97 + __o['3392'] = 108 + __o['3393'] = 105 + __o['3394'] = 103 + __o['3395'] = 110 + __o['3396'] = 32 + __o['3397'] = 105 + __o['3398'] = 115 + __o['3399'] = 32 + __o['3400'] = 110 + __o['3401'] = 111 + __o['3402'] = 116 + __o['3403'] = 32 + __o['3404'] = 97 + __o['3405'] = 32 + __o['3406'] = 112 + __o['3407'] = 111 + __o['3408'] = 119 + __o['3409'] = 101 + __o['3410'] = 114 + __o['3411'] = 32 + __o['3412'] = 111 + __o['3413'] = 102 + __o['3414'] = 32 + __o['3415'] = 50 + __o['3416'] = 0 + __o['3417'] = 73 + __o['3418'] = 110 + __o['3419'] = 118 + __o['3420'] = 97 + __o['3421'] = 108 + __o['3422'] = 105 + __o['3423'] = 100 + __o['3424'] = 32 + __o['3425'] = 98 + __o['3426'] = 108 + __o['3427'] = 111 + __o['3428'] = 99 + __o['3429'] = 107 + __o['3430'] = 32 + __o['3431'] = 97 + __o['3432'] = 100 + __o['3433'] = 100 + __o['3434'] = 114 + __o['3435'] = 101 + __o['3436'] = 115 + __o['3437'] = 115 + __o['3438'] = 32 + __o['3439'] = 111 + __o['3440'] = 110 + __o['3441'] = 32 + __o['3442'] = 116 + __o['3443'] = 104 + __o['3444'] = 101 + __o['3445'] = 32 + __o['3446'] = 102 + __o['3447'] = 114 + __o['3448'] = 101 + __o['3449'] = 101 + __o['3450'] = 46 + __o['3451'] = 32 + __o['3452'] = 70 + __o['3453'] = 97 + __o['3454'] = 105 + __o['3455'] = 108 + __o['3456'] = 101 + __o['3457'] = 100 + __o['3458'] = 32 + __o['3459'] = 116 + __o['3460'] = 111 + __o['3461'] = 32 + __o['3462'] = 102 + __o['3463'] = 114 + __o['3464'] = 101 + __o['3465'] = 101 + __o['3466'] = 32 + __o['3467'] = 98 + __o['3468'] = 108 + __o['3469'] = 111 + __o['3470'] = 99 + __o['3471'] = 107 + __o['3472'] = 32 + __o['3473'] = 98 + __o['3474'] = 97 + __o['3475'] = 99 + __o['3476'] = 107 + __o['3477'] = 32 + __o['3478'] = 116 + __o['3479'] = 111 + __o['3480'] = 32 + __o['3481'] = 104 + __o['3482'] = 101 + __o['3483'] = 97 + __o['3484'] = 112 + __o['3485'] = 46 + __o['3486'] = 0 + __o['3487'] = 65 + __o['3488'] = 95 + __o['3489'] = 100 + __o['3490'] = 111 + __o['3491'] = 117 + __o['3492'] = 98 + __o['3493'] = 108 + __o['3494'] = 101 + __o['3495'] = 70 + __o['3496'] = 114 + __o['3497'] = 101 + __o['3498'] = 101 + __o['3499'] = 58 + __o['3500'] = 32 + __o['3501'] = 66 + __o['3502'] = 117 + __o['3503'] = 102 + __o['3504'] = 102 + __o['3505'] = 101 + __o['3506'] = 114 + __o['3507'] = 32 + __o['3508'] = 97 + __o['3509'] = 108 + __o['3510'] = 114 + __o['3511'] = 101 + __o['3512'] = 97 + __o['3513'] = 100 + __o['3514'] = 121 + __o['3515'] = 32 + __o['3516'] = 102 + __o['3517'] = 114 + __o['3518'] = 101 + __o['3519'] = 101 + __o['3520'] = 0 + __o['3521'] = 65 + __o['3522'] = 95 + __o['3523'] = 98 + __o['3524'] = 117 + __o['3525'] = 102 + __o['3526'] = 79 + __o['3527'] = 118 + __o['3528'] = 101 + __o['3529'] = 114 + __o['3530'] = 102 + __o['3531'] = 108 + __o['3532'] = 111 + __o['3533'] = 119 + __o['3534'] = 58 + __o['3535'] = 32 + __o['3536'] = 66 + __o['3537'] = 117 + __o['3538'] = 102 + __o['3539'] = 102 + __o['3540'] = 101 + __o['3541'] = 114 + __o['3542'] = 32 + __o['3543'] = 111 + __o['3544'] = 118 + __o['3545'] = 101 + __o['3546'] = 114 + __o['3547'] = 102 + __o['3548'] = 108 + __o['3549'] = 111 + __o['3550'] = 119 + __o['3551'] = 0 + __o['3552'] = 65 + __o['3553'] = 95 + __o['3554'] = 110 + __o['3555'] = 111 + __o['3556'] = 116 + __o['3557'] = 69 + __o['3558'] = 109 + __o['3559'] = 112 + __o['3560'] = 116 + __o['3561'] = 121 + __o['3562'] = 58 + __o['3563'] = 32 + __o['3564'] = 72 + __o['3565'] = 101 + __o['3566'] = 97 + __o['3567'] = 112 + __o['3568'] = 32 + __o['3569'] = 110 + __o['3570'] = 111 + __o['3571'] = 116 + __o['3572'] = 32 + __o['3573'] = 101 + __o['3574'] = 109 + __o['3575'] = 112 + __o['3576'] = 116 + __o['3577'] = 121 + __o['3578'] = 0 + __o['3579'] = 65 + __o['3580'] = 95 + __o['3581'] = 110 + __o['3582'] = 117 + __o['3583'] = 108 + __o['3584'] = 108 + __o['3585'] = 79 + __o['3586'] = 98 + __o['3587'] = 106 + __o['3588'] = 101 + __o['3589'] = 99 + __o['3590'] = 116 + __o['3591'] = 58 + __o['3592'] = 32 + __o['3593'] = 72 + __o['3594'] = 101 + __o['3595'] = 97 + __o['3596'] = 112 + __o['3597'] = 84 + __o['3598'] = 114 + __o['3599'] = 97 + __o['3600'] = 99 + __o['3601'] = 107 + __o['3602'] = 95 + __o['3603'] = 112 + __o['3604'] = 114 + __o['3605'] = 105 + __o['3606'] = 110 + __o['3607'] = 116 + __o['3608'] = 72 + __o['3609'] = 101 + __o['3610'] = 97 + __o['3611'] = 112 + __o['3612'] = 32 + __o['3613'] = 99 + __o['3614'] = 97 + __o['3615'] = 108 + __o['3616'] = 108 + __o['3617'] = 101 + __o['3618'] = 100 + __o['3619'] = 32 + __o['3620'] = 119 + __o['3621'] = 105 + __o['3622'] = 116 + __o['3623'] = 104 + __o['3624'] = 32 + __o['3625'] = 110 + __o['3626'] = 117 + __o['3627'] = 108 + __o['3628'] = 108 + __o['3629'] = 32 + __o['3630'] = 111 + __o['3631'] = 98 + __o['3632'] = 106 + __o['3633'] = 0 + __o['3634'] = 97 + __o['3635'] = 115 + __o['3636'] = 115 + __o['3637'] = 101 + __o['3638'] = 114 + __o['3639'] = 116 + __o['3640'] = 105 + __o['3641'] = 111 + __o['3642'] = 110 + __o['3643'] = 32 + __o['3644'] = 102 + __o['3645'] = 97 + __o['3646'] = 105 + __o['3647'] = 108 + __o['3648'] = 117 + __o['3649'] = 114 + __o['3650'] = 101 + __o['3651'] = 37 + __o['3652'] = 115 + __o['3653'] = 37 + __o['3654'] = 115 + __o['3655'] = 0 + __o['3656'] = 37 + __o['3657'] = 36 + __o['3658'] = 83 + __o['3659'] = 0 + __o['3660'] = 111 + __o['3661'] = 117 + __o['3662'] = 116 + __o['3663'] = 32 + __o['3664'] = 111 + __o['3665'] = 102 + __o['3666'] = 32 + __o['3667'] = 109 + __o['3668'] = 101 + __o['3669'] = 109 + __o['3670'] = 111 + __o['3671'] = 114 + __o['3672'] = 121 + __o['3673'] = 58 + __o['3674'] = 32 + __o['3675'] = 104 + __o['3676'] = 101 + __o['3677'] = 97 + __o['3678'] = 112 + __o['3679'] = 61 + __o['3680'] = 48 + __o['3681'] = 120 + __o['3682'] = 37 + __o['3683'] = 120 + __o['3684'] = 44 + __o['3685'] = 32 + __o['3686'] = 115 + __o['3687'] = 105 + __o['3688'] = 122 + __o['3689'] = 101 + __o['3690'] = 61 + __o['3691'] = 37 + __o['3692'] = 117 + __o['3693'] = 0 + __o['3694'] = 37 + __o['3695'] = 115 + __o['3696'] = 32 + __o['3697'] = 48 + __o['3698'] = 120 + __o['3699'] = 37 + __o['3700'] = 120 + __o['3701'] = 0 + __o['3702'] = 69 + __o['3703'] = 95 + __o['3704'] = 98 + __o['3705'] = 97 + __o['3706'] = 100 + __o['3707'] = 76 + __o['3708'] = 101 + __o['3709'] = 118 + __o['3710'] = 101 + __o['3711'] = 108 + __o['3712'] = 58 + __o['3713'] = 32 + __o['3714'] = 66 + __o['3715'] = 97 + __o['3716'] = 100 + __o['3717'] = 32 + __o['3718'] = 102 + __o['3719'] = 105 + __o['3720'] = 108 + __o['3721'] = 116 + __o['3722'] = 101 + __o['3723'] = 114 + __o['3724'] = 32 + __o['3725'] = 108 + __o['3726'] = 101 + __o['3727'] = 118 + __o['3728'] = 101 + __o['3729'] = 108 + __o['3730'] = 32 + __o['3731'] = 118 + __o['3732'] = 97 + __o['3733'] = 108 + __o['3734'] = 117 + __o['3735'] = 101 + __o['3736'] = 58 + __o['3737'] = 32 + __o['3738'] = 37 + __o['3739'] = 100 + __o['3740'] = 0 + __o['3741'] = 102 + __o['3742'] = 114 + __o['3743'] = 101 + __o['3744'] = 101 + __o['3745'] = 40 + __o['3746'] = 41 + __o['3747'] = 32 + __o['3748'] = 105 + __o['3749'] = 110 + __o['3750'] = 118 + __o['3751'] = 97 + __o['3752'] = 108 + __o['3753'] = 105 + __o['3754'] = 100 + __o['3755'] = 32 + __o['3756'] = 105 + __o['3757'] = 110 + __o['3758'] = 32 + __o['3759'] = 103 + __o['3760'] = 114 + __o['3761'] = 111 + __o['3762'] = 119 + __o['3763'] = 116 + __o['3764'] = 104 + __o['3765'] = 45 + __o['3766'] = 111 + __o['3767'] = 110 + __o['3768'] = 108 + __o['3769'] = 121 + __o['3770'] = 32 + __o['3771'] = 72 + __o['3772'] = 101 + __o['3773'] = 97 + __o['3774'] = 112 + __o['3775'] = 77 + __o['3776'] = 105 + __o['3777'] = 110 + __o['3778'] = 0 + __o['3779'] = 84 + __o['3780'] = 104 + __o['3781'] = 101 + __o['3782'] = 32 + __o['3783'] = 82 + __o['3784'] = 84 + __o['3785'] = 83 + __o['3786'] = 32 + __o['3787'] = 104 + __o['3788'] = 101 + __o['3789'] = 97 + __o['3790'] = 112 + __o['3791'] = 32 + __o['3792'] = 105 + __o['3793'] = 115 + __o['3794'] = 32 + __o['3795'] = 117 + __o['3796'] = 115 + __o['3797'] = 101 + __o['3798'] = 100 + __o['3799'] = 32 + __o['3800'] = 117 + __o['3801'] = 112 + __o['3802'] = 46 + __o['3803'] = 32 + __o['3804'] = 69 + __o['3805'] = 120 + __o['3806'] = 97 + __o['3807'] = 109 + __o['3808'] = 105 + __o['3809'] = 110 + __o['3810'] = 101 + __o['3811'] = 32 + __o['3812'] = 80 + __o['3813'] = 114 + __o['3814'] = 111 + __o['3815'] = 103 + __o['3816'] = 114 + __o['3817'] = 97 + __o['3818'] = 109 + __o['3819'] = 46 + __o['3820'] = 104 + __o['3821'] = 101 + __o['3822'] = 97 + __o['3823'] = 112 + __o['3824'] = 46 + __o['3825'] = 0 + __o['3826'] = 69 + __o['3827'] = 95 + __o['3828'] = 98 + __o['3829'] = 97 + __o['3830'] = 100 + __o['3831'] = 67 + __o['3832'] = 111 + __o['3833'] = 109 + __o['3834'] = 109 + __o['3835'] = 97 + __o['3836'] = 110 + __o['3837'] = 100 + __o['3838'] = 58 + __o['3839'] = 32 + __o['3840'] = 82 + __o['3841'] = 101 + __o['3842'] = 99 + __o['3843'] = 101 + __o['3844'] = 105 + __o['3845'] = 118 + __o['3846'] = 101 + __o['3847'] = 100 + __o['3848'] = 32 + __o['3849'] = 105 + __o['3850'] = 110 + __o['3851'] = 118 + __o['3852'] = 97 + __o['3853'] = 108 + __o['3854'] = 105 + __o['3855'] = 100 + __o['3856'] = 32 + __o['3857'] = 99 + __o['3858'] = 111 + __o['3859'] = 109 + __o['3860'] = 109 + __o['3861'] = 97 + __o['3862'] = 110 + __o['3863'] = 100 + __o['3864'] = 44 + __o['3865'] = 32 + __o['3866'] = 105 + __o['3867'] = 100 + __o['3868'] = 58 + __o['3869'] = 32 + __o['3870'] = 37 + __o['3871'] = 100 + __o['3872'] = 46 + __o['3873'] = 0 + __o['3874'] = 69 + __o['3875'] = 95 + __o['3876'] = 115 + __o['3877'] = 116 + __o['3878'] = 97 + __o['3879'] = 99 + __o['3880'] = 107 + __o['3881'] = 79 + __o['3882'] = 118 + __o['3883'] = 101 + __o['3884'] = 114 + __o['3885'] = 102 + __o['3886'] = 108 + __o['3887'] = 111 + __o['3888'] = 119 + __o['3889'] = 58 + __o['3890'] = 32 + __o['3891'] = 84 + __o['3892'] = 97 + __o['3893'] = 115 + __o['3894'] = 107 + __o['3895'] = 32 + __o['3896'] = 48 + __o['3897'] = 120 + __o['3898'] = 37 + __o['3899'] = 120 + __o['3900'] = 32 + __o['3901'] = 115 + __o['3902'] = 116 + __o['3903'] = 97 + __o['3904'] = 99 + __o['3905'] = 107 + __o['3906'] = 32 + __o['3907'] = 111 + __o['3908'] = 118 + __o['3909'] = 101 + __o['3910'] = 114 + __o['3911'] = 102 + __o['3912'] = 108 + __o['3913'] = 111 + __o['3914'] = 119 + __o['3915'] = 46 + __o['3916'] = 0 + __o['3917'] = 69 + __o['3918'] = 95 + __o['3919'] = 115 + __o['3920'] = 112 + __o['3921'] = 79 + __o['3922'] = 117 + __o['3923'] = 116 + __o['3924'] = 79 + __o['3925'] = 102 + __o['3926'] = 66 + __o['3927'] = 111 + __o['3928'] = 117 + __o['3929'] = 110 + __o['3930'] = 100 + __o['3931'] = 115 + __o['3932'] = 58 + __o['3933'] = 32 + __o['3934'] = 84 + __o['3935'] = 97 + __o['3936'] = 115 + __o['3937'] = 107 + __o['3938'] = 32 + __o['3939'] = 48 + __o['3940'] = 120 + __o['3941'] = 37 + __o['3942'] = 120 + __o['3943'] = 32 + __o['3944'] = 115 + __o['3945'] = 116 + __o['3946'] = 97 + __o['3947'] = 99 + __o['3948'] = 107 + __o['3949'] = 32 + __o['3950'] = 101 + __o['3951'] = 114 + __o['3952'] = 114 + __o['3953'] = 111 + __o['3954'] = 114 + __o['3955'] = 44 + __o['3956'] = 32 + __o['3957'] = 83 + __o['3958'] = 80 + __o['3959'] = 32 + __o['3960'] = 61 + __o['3961'] = 32 + __o['3962'] = 48 + __o['3963'] = 120 + __o['3964'] = 37 + __o['3965'] = 120 + __o['3966'] = 46 + __o['3967'] = 0 + __o['3968'] = 69 + __o['3969'] = 95 + __o['3970'] = 100 + __o['3971'] = 101 + __o['3972'] = 108 + __o['3973'] = 101 + __o['3974'] = 116 + __o['3975'] = 101 + __o['3976'] = 78 + __o['3977'] = 111 + __o['3978'] = 116 + __o['3979'] = 65 + __o['3980'] = 108 + __o['3981'] = 108 + __o['3982'] = 111 + __o['3983'] = 119 + __o['3984'] = 101 + __o['3985'] = 100 + __o['3986'] = 58 + __o['3987'] = 32 + __o['3988'] = 84 + __o['3989'] = 97 + __o['3990'] = 115 + __o['3991'] = 107 + __o['3992'] = 32 + __o['3993'] = 48 + __o['3994'] = 120 + __o['3995'] = 37 + __o['3996'] = 120 + __o['3997'] = 46 + __o['3998'] = 0 + __o['3999'] = 69 + __o['4000'] = 95 + __o['4001'] = 115 + __o['4002'] = 116 + __o['4003'] = 97 + __o['4004'] = 99 + __o['4005'] = 107 + __o['4006'] = 79 + __o['4007'] = 118 + __o['4008'] = 101 + __o['4009'] = 114 + __o['4010'] = 102 + __o['4011'] = 108 + __o['4012'] = 111 + __o['4013'] = 119 + __o['4014'] = 58 + __o['4015'] = 32 + __o['4016'] = 73 + __o['4017'] = 83 + __o['4018'] = 82 + __o['4019'] = 32 + __o['4020'] = 115 + __o['4021'] = 116 + __o['4022'] = 97 + __o['4023'] = 99 + __o['4024'] = 107 + __o['4025'] = 32 + __o['4026'] = 111 + __o['4027'] = 118 + __o['4028'] = 101 + __o['4029'] = 114 + __o['4030'] = 102 + __o['4031'] = 108 + __o['4032'] = 111 + __o['4033'] = 119 + __o['4034'] = 46 + __o['4035'] = 0 + __o['4036'] = 69 + __o['4037'] = 95 + __o['4038'] = 97 + __o['4039'] = 108 + __o['4040'] = 114 + __o['4041'] = 101 + __o['4042'] = 97 + __o['4043'] = 100 + __o['4044'] = 121 + __o['4045'] = 68 + __o['4046'] = 101 + __o['4047'] = 102 + __o['4048'] = 105 + __o['4049'] = 110 + __o['4050'] = 101 + __o['4051'] = 100 + __o['4052'] = 58 + __o['4053'] = 32 + __o['4054'] = 72 + __o['4055'] = 119 + __o['4056'] = 105 + __o['4057'] = 32 + __o['4058'] = 97 + __o['4059'] = 108 + __o['4060'] = 114 + __o['4061'] = 101 + __o['4062'] = 97 + __o['4063'] = 100 + __o['4064'] = 121 + __o['4065'] = 32 + __o['4066'] = 100 + __o['4067'] = 101 + __o['4068'] = 102 + __o['4069'] = 105 + __o['4070'] = 110 + __o['4071'] = 101 + __o['4072'] = 100 + __o['4073'] = 58 + __o['4074'] = 32 + __o['4075'] = 105 + __o['4076'] = 110 + __o['4077'] = 116 + __o['4078'] = 114 + __o['4079'] = 35 + __o['4080'] = 32 + __o['4081'] = 37 + __o['4082'] = 100 + __o['4083'] = 0 + __o['4084'] = 69 + __o['4085'] = 95 + __o['4086'] = 104 + __o['4087'] = 119 + __o['4088'] = 105 + __o['4089'] = 76 + __o['4090'] = 105 + __o['4091'] = 109 + __o['4092'] = 105 + __o['4093'] = 116 + __o['4094'] = 69 + __o['4095'] = 120 + __o['4096'] = 99 + __o['4097'] = 101 + __o['4098'] = 101 + __o['4099'] = 100 + __o['4100'] = 101 + __o['4101'] = 100 + __o['4102'] = 58 + __o['4103'] = 32 + __o['4104'] = 84 + __o['4105'] = 111 + __o['4106'] = 111 + __o['4107'] = 32 + __o['4108'] = 109 + __o['4109'] = 97 + __o['4110'] = 110 + __o['4111'] = 121 + __o['4112'] = 32 + __o['4113'] = 105 + __o['4114'] = 110 + __o['4115'] = 116 + __o['4116'] = 101 + __o['4117'] = 114 + __o['4118'] = 114 + __o['4119'] = 117 + __o['4120'] = 112 + __o['4121'] = 116 + __o['4122'] = 115 + __o['4123'] = 32 + __o['4124'] = 100 + __o['4125'] = 101 + __o['4126'] = 102 + __o['4127'] = 105 + __o['4128'] = 110 + __o['4129'] = 101 + __o['4130'] = 100 + __o['4131'] = 0 + __o['4132'] = 69 + __o['4133'] = 95 + __o['4134'] = 101 + __o['4135'] = 120 + __o['4136'] = 99 + __o['4137'] = 101 + __o['4138'] = 112 + __o['4139'] = 116 + __o['4140'] = 105 + __o['4141'] = 111 + __o['4142'] = 110 + __o['4143'] = 58 + __o['4144'] = 32 + __o['4145'] = 105 + __o['4146'] = 100 + __o['4147'] = 32 + __o['4148'] = 61 + __o['4149'] = 32 + __o['4150'] = 37 + __o['4151'] = 100 + __o['4152'] = 44 + __o['4153'] = 32 + __o['4154'] = 112 + __o['4155'] = 99 + __o['4156'] = 32 + __o['4157'] = 61 + __o['4158'] = 32 + __o['4159'] = 37 + __o['4160'] = 48 + __o['4161'] = 56 + __o['4162'] = 120 + __o['4163'] = 46 + __o['4164'] = 10 + __o['4165'] = 84 + __o['4166'] = 111 + __o['4167'] = 32 + __o['4168'] = 115 + __o['4169'] = 101 + __o['4170'] = 101 + __o['4171'] = 32 + __o['4172'] = 109 + __o['4173'] = 111 + __o['4174'] = 114 + __o['4175'] = 101 + __o['4176'] = 32 + __o['4177'] = 101 + __o['4178'] = 120 + __o['4179'] = 99 + __o['4180'] = 101 + __o['4181'] = 112 + __o['4182'] = 116 + __o['4183'] = 105 + __o['4184'] = 111 + __o['4185'] = 110 + __o['4186'] = 32 + __o['4187'] = 100 + __o['4188'] = 101 + __o['4189'] = 116 + __o['4190'] = 97 + __o['4191'] = 105 + __o['4192'] = 108 + __o['4193'] = 44 + __o['4194'] = 32 + __o['4195'] = 115 + __o['4196'] = 101 + __o['4197'] = 116 + __o['4198'] = 32 + __o['4199'] = 116 + __o['4200'] = 105 + __o['4201'] = 46 + __o['4202'] = 115 + __o['4203'] = 121 + __o['4204'] = 115 + __o['4205'] = 98 + __o['4206'] = 105 + __o['4207'] = 111 + __o['4208'] = 115 + __o['4209'] = 46 + __o['4210'] = 102 + __o['4211'] = 97 + __o['4212'] = 109 + __o['4213'] = 105 + __o['4214'] = 108 + __o['4215'] = 121 + __o['4216'] = 46 + __o['4217'] = 97 + __o['4218'] = 114 + __o['4219'] = 109 + __o['4220'] = 46 + __o['4221'] = 109 + __o['4222'] = 51 + __o['4223'] = 46 + __o['4224'] = 72 + __o['4225'] = 119 + __o['4226'] = 105 + __o['4227'] = 46 + __o['4228'] = 101 + __o['4229'] = 110 + __o['4230'] = 97 + __o['4231'] = 98 + __o['4232'] = 108 + __o['4233'] = 101 + __o['4234'] = 69 + __o['4235'] = 120 + __o['4236'] = 99 + __o['4237'] = 101 + __o['4238'] = 112 + __o['4239'] = 116 + __o['4240'] = 105 + __o['4241'] = 111 + __o['4242'] = 110 + __o['4243'] = 32 + __o['4244'] = 61 + __o['4245'] = 32 + __o['4246'] = 116 + __o['4247'] = 114 + __o['4248'] = 117 + __o['4249'] = 101 + __o['4250'] = 32 + __o['4251'] = 111 + __o['4252'] = 114 + __o['4253'] = 44 + __o['4254'] = 10 + __o['4255'] = 101 + __o['4256'] = 120 + __o['4257'] = 97 + __o['4258'] = 109 + __o['4259'] = 105 + __o['4260'] = 110 + __o['4261'] = 101 + __o['4262'] = 32 + __o['4263'] = 116 + __o['4264'] = 104 + __o['4265'] = 101 + __o['4266'] = 32 + __o['4267'] = 69 + __o['4268'] = 120 + __o['4269'] = 99 + __o['4270'] = 101 + __o['4271'] = 112 + __o['4272'] = 116 + __o['4273'] = 105 + __o['4274'] = 111 + __o['4275'] = 110 + __o['4276'] = 32 + __o['4277'] = 118 + __o['4278'] = 105 + __o['4279'] = 101 + __o['4280'] = 119 + __o['4281'] = 32 + __o['4282'] = 102 + __o['4283'] = 111 + __o['4284'] = 114 + __o['4285'] = 32 + __o['4286'] = 116 + __o['4287'] = 104 + __o['4288'] = 101 + __o['4289'] = 32 + __o['4290'] = 116 + __o['4291'] = 105 + __o['4292'] = 46 + __o['4293'] = 115 + __o['4294'] = 121 + __o['4295'] = 115 + __o['4296'] = 98 + __o['4297'] = 105 + __o['4298'] = 111 + __o['4299'] = 115 + __o['4300'] = 46 + __o['4301'] = 102 + __o['4302'] = 97 + __o['4303'] = 109 + __o['4304'] = 105 + __o['4305'] = 108 + __o['4306'] = 121 + __o['4307'] = 46 + __o['4308'] = 97 + __o['4309'] = 114 + __o['4310'] = 109 + __o['4311'] = 46 + __o['4312'] = 109 + __o['4313'] = 51 + __o['4314'] = 46 + __o['4315'] = 72 + __o['4316'] = 119 + __o['4317'] = 105 + __o['4318'] = 32 + __o['4319'] = 109 + __o['4320'] = 111 + __o['4321'] = 100 + __o['4322'] = 117 + __o['4323'] = 108 + __o['4324'] = 101 + __o['4325'] = 32 + __o['4326'] = 117 + __o['4327'] = 115 + __o['4328'] = 105 + __o['4329'] = 110 + __o['4330'] = 103 + __o['4331'] = 32 + __o['4332'] = 82 + __o['4333'] = 79 + __o['4334'] = 86 + __o['4335'] = 46 + __o['4336'] = 0 + __o['4337'] = 69 + __o['4338'] = 95 + __o['4339'] = 110 + __o['4340'] = 111 + __o['4341'] = 73 + __o['4342'] = 115 + __o['4343'] = 114 + __o['4344'] = 58 + __o['4345'] = 32 + __o['4346'] = 105 + __o['4347'] = 100 + __o['4348'] = 32 + __o['4349'] = 61 + __o['4350'] = 32 + __o['4351'] = 37 + __o['4352'] = 100 + __o['4353'] = 44 + __o['4354'] = 32 + __o['4355'] = 112 + __o['4356'] = 99 + __o['4357'] = 32 + __o['4358'] = 61 + __o['4359'] = 32 + __o['4360'] = 37 + __o['4361'] = 48 + __o['4362'] = 56 + __o['4363'] = 120 + __o['4364'] = 0 + __o['4365'] = 69 + __o['4366'] = 95 + __o['4367'] = 78 + __o['4368'] = 77 + __o['4369'] = 73 + __o['4370'] = 58 + __o['4371'] = 32 + __o['4372'] = 37 + __o['4373'] = 115 + __o['4374'] = 0 + __o['4375'] = 69 + __o['4376'] = 95 + __o['4377'] = 104 + __o['4378'] = 97 + __o['4379'] = 114 + __o['4380'] = 100 + __o['4381'] = 70 + __o['4382'] = 97 + __o['4383'] = 117 + __o['4384'] = 108 + __o['4385'] = 116 + __o['4386'] = 58 + __o['4387'] = 32 + __o['4388'] = 37 + __o['4389'] = 115 + __o['4390'] = 0 + __o['4391'] = 69 + __o['4392'] = 95 + __o['4393'] = 109 + __o['4394'] = 101 + __o['4395'] = 109 + __o['4396'] = 70 + __o['4397'] = 97 + __o['4398'] = 117 + __o['4399'] = 108 + __o['4400'] = 116 + __o['4401'] = 58 + __o['4402'] = 32 + __o['4403'] = 37 + __o['4404'] = 115 + __o['4405'] = 44 + __o['4406'] = 32 + __o['4407'] = 97 + __o['4408'] = 100 + __o['4409'] = 100 + __o['4410'] = 114 + __o['4411'] = 101 + __o['4412'] = 115 + __o['4413'] = 115 + __o['4414'] = 58 + __o['4415'] = 32 + __o['4416'] = 37 + __o['4417'] = 48 + __o['4418'] = 56 + __o['4419'] = 120 + __o['4420'] = 0 + __o['4421'] = 69 + __o['4422'] = 95 + __o['4423'] = 98 + __o['4424'] = 117 + __o['4425'] = 115 + __o['4426'] = 70 + __o['4427'] = 97 + __o['4428'] = 117 + __o['4429'] = 108 + __o['4430'] = 116 + __o['4431'] = 58 + __o['4432'] = 32 + __o['4433'] = 37 + __o['4434'] = 115 + __o['4435'] = 44 + __o['4436'] = 32 + __o['4437'] = 97 + __o['4438'] = 100 + __o['4439'] = 100 + __o['4440'] = 114 + __o['4441'] = 101 + __o['4442'] = 115 + __o['4443'] = 115 + __o['4444'] = 58 + __o['4445'] = 32 + __o['4446'] = 37 + __o['4447'] = 48 + __o['4448'] = 56 + __o['4449'] = 120 + __o['4450'] = 0 + __o['4451'] = 69 + __o['4452'] = 95 + __o['4453'] = 117 + __o['4454'] = 115 + __o['4455'] = 97 + __o['4456'] = 103 + __o['4457'] = 101 + __o['4458'] = 70 + __o['4459'] = 97 + __o['4460'] = 117 + __o['4461'] = 108 + __o['4462'] = 116 + __o['4463'] = 58 + __o['4464'] = 32 + __o['4465'] = 37 + __o['4466'] = 115 + __o['4467'] = 0 + __o['4468'] = 69 + __o['4469'] = 95 + __o['4470'] = 115 + __o['4471'] = 118 + __o['4472'] = 67 + __o['4473'] = 97 + __o['4474'] = 108 + __o['4475'] = 108 + __o['4476'] = 58 + __o['4477'] = 32 + __o['4478'] = 115 + __o['4479'] = 118 + __o['4480'] = 78 + __o['4481'] = 117 + __o['4482'] = 109 + __o['4483'] = 32 + __o['4484'] = 61 + __o['4485'] = 32 + __o['4486'] = 37 + __o['4487'] = 100 + __o['4488'] = 0 + __o['4489'] = 69 + __o['4490'] = 95 + __o['4491'] = 100 + __o['4492'] = 101 + __o['4493'] = 98 + __o['4494'] = 117 + __o['4495'] = 103 + __o['4496'] = 77 + __o['4497'] = 111 + __o['4498'] = 110 + __o['4499'] = 58 + __o['4500'] = 32 + __o['4501'] = 37 + __o['4502'] = 115 + __o['4503'] = 0 + __o['4504'] = 69 + __o['4505'] = 95 + __o['4506'] = 114 + __o['4507'] = 101 + __o['4508'] = 115 + __o['4509'] = 101 + __o['4510'] = 114 + __o['4511'] = 118 + __o['4512'] = 101 + __o['4513'] = 100 + __o['4514'] = 58 + __o['4515'] = 32 + __o['4516'] = 37 + __o['4517'] = 115 + __o['4518'] = 32 + __o['4519'] = 37 + __o['4520'] = 100 + __o['4521'] = 0 + __o['4522'] = 69 + __o['4523'] = 95 + __o['4524'] = 105 + __o['4525'] = 110 + __o['4526'] = 118 + __o['4527'] = 97 + __o['4528'] = 108 + __o['4529'] = 105 + __o['4530'] = 100 + __o['4531'] = 84 + __o['4532'] = 105 + __o['4533'] = 109 + __o['4534'] = 101 + __o['4535'] = 114 + __o['4536'] = 58 + __o['4537'] = 32 + __o['4538'] = 73 + __o['4539'] = 110 + __o['4540'] = 118 + __o['4541'] = 97 + __o['4542'] = 108 + __o['4543'] = 105 + __o['4544'] = 100 + __o['4545'] = 32 + __o['4546'] = 84 + __o['4547'] = 105 + __o['4548'] = 109 + __o['4549'] = 101 + __o['4550'] = 114 + __o['4551'] = 32 + __o['4552'] = 73 + __o['4553'] = 100 + __o['4554'] = 32 + __o['4555'] = 37 + __o['4556'] = 100 + __o['4557'] = 0 + __o['4558'] = 69 + __o['4559'] = 95 + __o['4560'] = 110 + __o['4561'] = 111 + __o['4562'] = 116 + __o['4563'] = 65 + __o['4564'] = 118 + __o['4565'] = 97 + __o['4566'] = 105 + __o['4567'] = 108 + __o['4568'] = 97 + __o['4569'] = 98 + __o['4570'] = 108 + __o['4571'] = 101 + __o['4572'] = 58 + __o['4573'] = 32 + __o['4574'] = 84 + __o['4575'] = 105 + __o['4576'] = 109 + __o['4577'] = 101 + __o['4578'] = 114 + __o['4579'] = 32 + __o['4580'] = 110 + __o['4581'] = 111 + __o['4582'] = 116 + __o['4583'] = 32 + __o['4584'] = 97 + __o['4585'] = 118 + __o['4586'] = 97 + __o['4587'] = 105 + __o['4588'] = 108 + __o['4589'] = 97 + __o['4590'] = 98 + __o['4591'] = 108 + __o['4592'] = 101 + __o['4593'] = 32 + __o['4594'] = 37 + __o['4595'] = 100 + __o['4596'] = 0 + __o['4597'] = 69 + __o['4598'] = 95 + __o['4599'] = 99 + __o['4600'] = 97 + __o['4601'] = 110 + __o['4602'] = 110 + __o['4603'] = 111 + __o['4604'] = 116 + __o['4605'] = 83 + __o['4606'] = 117 + __o['4607'] = 112 + __o['4608'] = 112 + __o['4609'] = 111 + __o['4610'] = 114 + __o['4611'] = 116 + __o['4612'] = 58 + __o['4613'] = 32 + __o['4614'] = 84 + __o['4615'] = 105 + __o['4616'] = 109 + __o['4617'] = 101 + __o['4618'] = 114 + __o['4619'] = 32 + __o['4620'] = 99 + __o['4621'] = 97 + __o['4622'] = 110 + __o['4623'] = 110 + __o['4624'] = 111 + __o['4625'] = 116 + __o['4626'] = 32 + __o['4627'] = 115 + __o['4628'] = 117 + __o['4629'] = 112 + __o['4630'] = 112 + __o['4631'] = 111 + __o['4632'] = 114 + __o['4633'] = 116 + __o['4634'] = 32 + __o['4635'] = 114 + __o['4636'] = 101 + __o['4637'] = 113 + __o['4638'] = 117 + __o['4639'] = 101 + __o['4640'] = 115 + __o['4641'] = 116 + __o['4642'] = 101 + __o['4643'] = 100 + __o['4644'] = 32 + __o['4645'] = 112 + __o['4646'] = 101 + __o['4647'] = 114 + __o['4648'] = 105 + __o['4649'] = 111 + __o['4650'] = 100 + __o['4651'] = 32 + __o['4652'] = 37 + __o['4653'] = 100 + __o['4654'] = 0 + __o['4655'] = 69 + __o['4656'] = 95 + __o['4657'] = 112 + __o['4658'] = 114 + __o['4659'] = 105 + __o['4660'] = 111 + __o['4661'] = 114 + __o['4662'] = 105 + __o['4663'] = 116 + __o['4664'] = 121 + __o['4665'] = 58 + __o['4666'] = 32 + __o['4667'] = 84 + __o['4668'] = 104 + __o['4669'] = 114 + __o['4670'] = 101 + __o['4671'] = 97 + __o['4672'] = 100 + __o['4673'] = 32 + __o['4674'] = 112 + __o['4675'] = 114 + __o['4676'] = 105 + __o['4677'] = 111 + __o['4678'] = 114 + __o['4679'] = 105 + __o['4680'] = 116 + __o['4681'] = 121 + __o['4682'] = 32 + __o['4683'] = 105 + __o['4684'] = 115 + __o['4685'] = 32 + __o['4686'] = 105 + __o['4687'] = 110 + __o['4688'] = 118 + __o['4689'] = 97 + __o['4690'] = 108 + __o['4691'] = 105 + __o['4692'] = 100 + __o['4693'] = 32 + __o['4694'] = 37 + __o['4695'] = 100 + __o['4696'] = 0 + __o['4697'] = 114 + __o['4698'] = 101 + __o['4699'] = 113 + __o['4700'] = 117 + __o['4701'] = 101 + __o['4702'] = 115 + __o['4703'] = 116 + __o['4704'] = 101 + __o['4705'] = 100 + __o['4706'] = 32 + __o['4707'] = 115 + __o['4708'] = 105 + __o['4709'] = 122 + __o['4710'] = 101 + __o['4711'] = 32 + __o['4712'] = 105 + __o['4713'] = 115 + __o['4714'] = 32 + __o['4715'] = 116 + __o['4716'] = 111 + __o['4717'] = 111 + __o['4718'] = 32 + __o['4719'] = 98 + __o['4720'] = 105 + __o['4721'] = 103 + __o['4722'] = 58 + __o['4723'] = 32 + __o['4724'] = 104 + __o['4725'] = 97 + __o['4726'] = 110 + __o['4727'] = 100 + __o['4728'] = 108 + __o['4729'] = 101 + __o['4730'] = 61 + __o['4731'] = 48 + __o['4732'] = 120 + __o['4733'] = 37 + __o['4734'] = 120 + __o['4735'] = 44 + __o['4736'] = 32 + __o['4737'] = 115 + __o['4738'] = 105 + __o['4739'] = 122 + __o['4740'] = 101 + __o['4741'] = 61 + __o['4742'] = 37 + __o['4743'] = 117 + __o['4744'] = 0 + __o['4745'] = 111 + __o['4746'] = 117 + __o['4747'] = 116 + __o['4748'] = 32 + __o['4749'] = 111 + __o['4750'] = 102 + __o['4751'] = 32 + __o['4752'] = 109 + __o['4753'] = 101 + __o['4754'] = 109 + __o['4755'] = 111 + __o['4756'] = 114 + __o['4757'] = 121 + __o['4758'] = 58 + __o['4759'] = 32 + __o['4760'] = 104 + __o['4761'] = 97 + __o['4762'] = 110 + __o['4763'] = 100 + __o['4764'] = 108 + __o['4765'] = 101 + __o['4766'] = 61 + __o['4767'] = 48 + __o['4768'] = 120 + __o['4769'] = 37 + __o['4770'] = 120 + __o['4771'] = 44 + __o['4772'] = 32 + __o['4773'] = 115 + __o['4774'] = 105 + __o['4775'] = 122 + __o['4776'] = 101 + __o['4777'] = 61 + __o['4778'] = 37 + __o['4779'] = 117 + __o['4780'] = 0 + __o['4781'] = 69 + __o['4782'] = 95 + __o['4783'] = 110 + __o['4784'] = 111 + __o['4785'] = 97 + __o['4786'] = 108 + __o['4787'] = 116 + __o['4788'] = 99 + __o['4789'] = 108 + __o['4790'] = 107 + __o['4791'] = 58 + __o['4792'] = 32 + __o['4793'] = 84 + __o['4794'] = 105 + __o['4795'] = 109 + __o['4796'] = 101 + __o['4797'] = 114 + __o['4798'] = 32 + __o['4799'] = 100 + __o['4800'] = 111 + __o['4801'] = 101 + __o['4802'] = 115 + __o['4803'] = 32 + __o['4804'] = 110 + __o['4805'] = 111 + __o['4806'] = 116 + __o['4807'] = 32 + __o['4808'] = 115 + __o['4809'] = 117 + __o['4810'] = 112 + __o['4811'] = 112 + __o['4812'] = 111 + __o['4813'] = 114 + __o['4814'] = 116 + __o['4815'] = 32 + __o['4816'] = 97 + __o['4817'] = 108 + __o['4818'] = 116 + __o['4819'] = 99 + __o['4820'] = 108 + __o['4821'] = 107 + __o['4822'] = 0 + __o['4823'] = 60 + __o['4824'] = 45 + __o['4825'] = 45 + __o['4826'] = 32 + __o['4827'] = 99 + __o['4828'] = 111 + __o['4829'] = 110 + __o['4830'] = 115 + __o['4831'] = 116 + __o['4832'] = 114 + __o['4833'] = 117 + __o['4834'] = 99 + __o['4835'] = 116 + __o['4836'] = 58 + __o['4837'] = 32 + __o['4838'] = 37 + __o['4839'] = 112 + __o['4840'] = 40 + __o['4841'] = 39 + __o['4842'] = 37 + __o['4843'] = 115 + __o['4844'] = 39 + __o['4845'] = 41 + __o['4846'] = 0 + __o['4847'] = 60 + __o['4848'] = 45 + __o['4849'] = 45 + __o['4850'] = 32 + __o['4851'] = 99 + __o['4852'] = 114 + __o['4853'] = 101 + __o['4854'] = 97 + __o['4855'] = 116 + __o['4856'] = 101 + __o['4857'] = 58 + __o['4858'] = 32 + __o['4859'] = 37 + __o['4860'] = 112 + __o['4861'] = 40 + __o['4862'] = 39 + __o['4863'] = 37 + __o['4864'] = 115 + __o['4865'] = 39 + __o['4866'] = 41 + __o['4867'] = 0 + __o['4868'] = 45 + __o['4869'] = 45 + __o['4870'] = 62 + __o['4871'] = 32 + __o['4872'] = 100 + __o['4873'] = 101 + __o['4874'] = 115 + __o['4875'] = 116 + __o['4876'] = 114 + __o['4877'] = 117 + __o['4878'] = 99 + __o['4879'] = 116 + __o['4880'] = 58 + __o['4881'] = 32 + __o['4882'] = 40 + __o['4883'] = 37 + __o['4884'] = 112 + __o['4885'] = 41 + __o['4886'] = 0 + __o['4887'] = 45 + __o['4888'] = 45 + __o['4889'] = 62 + __o['4890'] = 32 + __o['4891'] = 100 + __o['4892'] = 101 + __o['4893'] = 108 + __o['4894'] = 101 + __o['4895'] = 116 + __o['4896'] = 101 + __o['4897'] = 58 + __o['4898'] = 32 + __o['4899'] = 40 + __o['4900'] = 37 + __o['4901'] = 112 + __o['4902'] = 41 + __o['4903'] = 0 + __o['4904'] = 69 + __o['4905'] = 82 + __o['4906'] = 82 + __o['4907'] = 79 + __o['4908'] = 82 + __o['4909'] = 58 + __o['4910'] = 32 + __o['4911'] = 37 + __o['4912'] = 36 + __o['4913'] = 70 + __o['4914'] = 37 + __o['4915'] = 36 + __o['4916'] = 83 + __o['4917'] = 0 + __o['4918'] = 87 + __o['4919'] = 65 + __o['4920'] = 82 + __o['4921'] = 78 + __o['4922'] = 73 + __o['4923'] = 78 + __o['4924'] = 71 + __o['4925'] = 58 + __o['4926'] = 32 + __o['4927'] = 37 + __o['4928'] = 36 + __o['4929'] = 70 + __o['4930'] = 37 + __o['4931'] = 36 + __o['4932'] = 83 + __o['4933'] = 0 + __o['4934'] = 37 + __o['4935'] = 36 + __o['4936'] = 70 + __o['4937'] = 37 + __o['4938'] = 36 + __o['4939'] = 83 + __o['4940'] = 0 + __o['4941'] = 83 + __o['4942'] = 116 + __o['4943'] = 97 + __o['4944'] = 114 + __o['4945'] = 116 + __o['4946'] = 58 + __o['4947'] = 32 + __o['4948'] = 37 + __o['4949'] = 36 + __o['4950'] = 83 + __o['4951'] = 0 + __o['4952'] = 83 + __o['4953'] = 116 + __o['4954'] = 111 + __o['4955'] = 112 + __o['4956'] = 58 + __o['4957'] = 32 + __o['4958'] = 37 + __o['4959'] = 36 + __o['4960'] = 83 + __o['4961'] = 0 + __o['4962'] = 83 + __o['4963'] = 116 + __o['4964'] = 97 + __o['4965'] = 114 + __o['4966'] = 116 + __o['4967'] = 73 + __o['4968'] = 110 + __o['4969'] = 115 + __o['4970'] = 116 + __o['4971'] = 97 + __o['4972'] = 110 + __o['4973'] = 99 + __o['4974'] = 101 + __o['4975'] = 58 + __o['4976'] = 32 + __o['4977'] = 37 + __o['4978'] = 36 + __o['4979'] = 83 + __o['4980'] = 0 + __o['4981'] = 83 + __o['4982'] = 116 + __o['4983'] = 111 + __o['4984'] = 112 + __o['4985'] = 73 + __o['4986'] = 110 + __o['4987'] = 115 + __o['4988'] = 116 + __o['4989'] = 97 + __o['4990'] = 110 + __o['4991'] = 99 + __o['4992'] = 101 + __o['4993'] = 58 + __o['4994'] = 32 + __o['4995'] = 37 + __o['4996'] = 36 + __o['4997'] = 83 + __o['4998'] = 0 + __o['4999'] = 76 + __o['5000'] = 87 + __o['5001'] = 95 + __o['5002'] = 100 + __o['5003'] = 101 + __o['5004'] = 108 + __o['5005'] = 97 + __o['5006'] = 121 + __o['5007'] = 101 + __o['5008'] = 100 + __o['5009'] = 58 + __o['5010'] = 32 + __o['5011'] = 100 + __o['5012'] = 101 + __o['5013'] = 108 + __o['5014'] = 97 + __o['5015'] = 121 + __o['5016'] = 58 + __o['5017'] = 32 + __o['5018'] = 37 + __o['5019'] = 100 + __o['5020'] = 0 + __o['5021'] = 76 + __o['5022'] = 77 + __o['5023'] = 95 + __o['5024'] = 116 + __o['5025'] = 105 + __o['5026'] = 99 + __o['5027'] = 107 + __o['5028'] = 58 + __o['5029'] = 32 + __o['5030'] = 116 + __o['5031'] = 105 + __o['5032'] = 99 + __o['5033'] = 107 + __o['5034'] = 58 + __o['5035'] = 32 + __o['5036'] = 37 + __o['5037'] = 100 + __o['5038'] = 0 + __o['5039'] = 76 + __o['5040'] = 77 + __o['5041'] = 95 + __o['5042'] = 98 + __o['5043'] = 101 + __o['5044'] = 103 + __o['5045'] = 105 + __o['5046'] = 110 + __o['5047'] = 58 + __o['5048'] = 32 + __o['5049'] = 99 + __o['5050'] = 108 + __o['5051'] = 107 + __o['5052'] = 58 + __o['5053'] = 32 + __o['5054'] = 48 + __o['5055'] = 120 + __o['5056'] = 37 + __o['5057'] = 120 + __o['5058'] = 44 + __o['5059'] = 32 + __o['5060'] = 102 + __o['5061'] = 117 + __o['5062'] = 110 + __o['5063'] = 99 + __o['5064'] = 58 + __o['5065'] = 32 + __o['5066'] = 48 + __o['5067'] = 120 + __o['5068'] = 37 + __o['5069'] = 120 + __o['5070'] = 0 + __o['5071'] = 76 + __o['5072'] = 77 + __o['5073'] = 95 + __o['5074'] = 112 + __o['5075'] = 111 + __o['5076'] = 115 + __o['5077'] = 116 + __o['5078'] = 58 + __o['5079'] = 32 + __o['5080'] = 115 + __o['5081'] = 101 + __o['5082'] = 109 + __o['5083'] = 58 + __o['5084'] = 32 + __o['5085'] = 48 + __o['5086'] = 120 + __o['5087'] = 37 + __o['5088'] = 120 + __o['5089'] = 44 + __o['5090'] = 32 + __o['5091'] = 99 + __o['5092'] = 111 + __o['5093'] = 117 + __o['5094'] = 110 + __o['5095'] = 116 + __o['5096'] = 58 + __o['5097'] = 32 + __o['5098'] = 37 + __o['5099'] = 100 + __o['5100'] = 0 + __o['5101'] = 76 + __o['5102'] = 77 + __o['5103'] = 95 + __o['5104'] = 112 + __o['5105'] = 101 + __o['5106'] = 110 + __o['5107'] = 100 + __o['5108'] = 58 + __o['5109'] = 32 + __o['5110'] = 115 + __o['5111'] = 101 + __o['5112'] = 109 + __o['5113'] = 58 + __o['5114'] = 32 + __o['5115'] = 48 + __o['5116'] = 120 + __o['5117'] = 37 + __o['5118'] = 120 + __o['5119'] = 44 + __o['5120'] = 32 + __o['5121'] = 99 + __o['5122'] = 111 + __o['5123'] = 117 + __o['5124'] = 110 + __o['5125'] = 116 + __o['5126'] = 58 + __o['5127'] = 32 + __o['5128'] = 37 + __o['5129'] = 100 + __o['5130'] = 44 + __o['5131'] = 32 + __o['5132'] = 116 + __o['5133'] = 105 + __o['5134'] = 109 + __o['5135'] = 101 + __o['5136'] = 111 + __o['5137'] = 117 + __o['5138'] = 116 + __o['5139'] = 58 + __o['5140'] = 32 + __o['5141'] = 37 + __o['5142'] = 100 + __o['5143'] = 0 + __o['5144'] = 76 + __o['5145'] = 77 + __o['5146'] = 95 + __o['5147'] = 98 + __o['5148'] = 101 + __o['5149'] = 103 + __o['5150'] = 105 + __o['5151'] = 110 + __o['5152'] = 58 + __o['5153'] = 32 + __o['5154'] = 115 + __o['5155'] = 119 + __o['5156'] = 105 + __o['5157'] = 58 + __o['5158'] = 32 + __o['5159'] = 48 + __o['5160'] = 120 + __o['5161'] = 37 + __o['5162'] = 120 + __o['5163'] = 44 + __o['5164'] = 32 + __o['5165'] = 102 + __o['5166'] = 117 + __o['5167'] = 110 + __o['5168'] = 99 + __o['5169'] = 58 + __o['5170'] = 32 + __o['5171'] = 48 + __o['5172'] = 120 + __o['5173'] = 37 + __o['5174'] = 120 + __o['5175'] = 44 + __o['5176'] = 32 + __o['5177'] = 112 + __o['5178'] = 114 + __o['5179'] = 101 + __o['5180'] = 84 + __o['5181'] = 104 + __o['5182'] = 114 + __o['5183'] = 101 + __o['5184'] = 97 + __o['5185'] = 100 + __o['5186'] = 58 + __o['5187'] = 32 + __o['5188'] = 37 + __o['5189'] = 100 + __o['5190'] = 0 + __o['5191'] = 76 + __o['5192'] = 68 + __o['5193'] = 95 + __o['5194'] = 101 + __o['5195'] = 110 + __o['5196'] = 100 + __o['5197'] = 58 + __o['5198'] = 32 + __o['5199'] = 115 + __o['5200'] = 119 + __o['5201'] = 105 + __o['5202'] = 58 + __o['5203'] = 32 + __o['5204'] = 48 + __o['5205'] = 120 + __o['5206'] = 37 + __o['5207'] = 120 + __o['5208'] = 0 + __o['5209'] = 76 + __o['5210'] = 77 + __o['5211'] = 95 + __o['5212'] = 112 + __o['5213'] = 111 + __o['5214'] = 115 + __o['5215'] = 116 + __o['5216'] = 58 + __o['5217'] = 32 + __o['5218'] = 115 + __o['5219'] = 119 + __o['5220'] = 105 + __o['5221'] = 58 + __o['5222'] = 32 + __o['5223'] = 48 + __o['5224'] = 120 + __o['5225'] = 37 + __o['5226'] = 120 + __o['5227'] = 44 + __o['5228'] = 32 + __o['5229'] = 102 + __o['5230'] = 117 + __o['5231'] = 110 + __o['5232'] = 99 + __o['5233'] = 58 + __o['5234'] = 32 + __o['5235'] = 48 + __o['5236'] = 120 + __o['5237'] = 37 + __o['5238'] = 120 + __o['5239'] = 44 + __o['5240'] = 32 + __o['5241'] = 112 + __o['5242'] = 114 + __o['5243'] = 105 + __o['5244'] = 58 + __o['5245'] = 32 + __o['5246'] = 37 + __o['5247'] = 100 + __o['5248'] = 0 + __o['5249'] = 76 + __o['5250'] = 77 + __o['5251'] = 95 + __o['5252'] = 115 + __o['5253'] = 119 + __o['5254'] = 105 + __o['5255'] = 116 + __o['5256'] = 99 + __o['5257'] = 104 + __o['5258'] = 58 + __o['5259'] = 32 + __o['5260'] = 111 + __o['5261'] = 108 + __o['5262'] = 100 + __o['5263'] = 116 + __o['5264'] = 115 + __o['5265'] = 107 + __o['5266'] = 58 + __o['5267'] = 32 + __o['5268'] = 48 + __o['5269'] = 120 + __o['5270'] = 37 + __o['5271'] = 120 + __o['5272'] = 44 + __o['5273'] = 32 + __o['5274'] = 111 + __o['5275'] = 108 + __o['5276'] = 100 + __o['5277'] = 102 + __o['5278'] = 117 + __o['5279'] = 110 + __o['5280'] = 99 + __o['5281'] = 58 + __o['5282'] = 32 + __o['5283'] = 48 + __o['5284'] = 120 + __o['5285'] = 37 + __o['5286'] = 120 + __o['5287'] = 44 + __o['5288'] = 32 + __o['5289'] = 110 + __o['5290'] = 101 + __o['5291'] = 119 + __o['5292'] = 116 + __o['5293'] = 115 + __o['5294'] = 107 + __o['5295'] = 58 + __o['5296'] = 32 + __o['5297'] = 48 + __o['5298'] = 120 + __o['5299'] = 37 + __o['5300'] = 120 + __o['5301'] = 44 + __o['5302'] = 32 + __o['5303'] = 110 + __o['5304'] = 101 + __o['5305'] = 119 + __o['5306'] = 102 + __o['5307'] = 117 + __o['5308'] = 110 + __o['5309'] = 99 + __o['5310'] = 58 + __o['5311'] = 32 + __o['5312'] = 48 + __o['5313'] = 120 + __o['5314'] = 37 + __o['5315'] = 120 + __o['5316'] = 0 + __o['5317'] = 76 + __o['5318'] = 77 + __o['5319'] = 95 + __o['5320'] = 115 + __o['5321'] = 108 + __o['5322'] = 101 + __o['5323'] = 101 + __o['5324'] = 112 + __o['5325'] = 58 + __o['5326'] = 32 + __o['5327'] = 116 + __o['5328'] = 115 + __o['5329'] = 107 + __o['5330'] = 58 + __o['5331'] = 32 + __o['5332'] = 48 + __o['5333'] = 120 + __o['5334'] = 37 + __o['5335'] = 120 + __o['5336'] = 44 + __o['5337'] = 32 + __o['5338'] = 102 + __o['5339'] = 117 + __o['5340'] = 110 + __o['5341'] = 99 + __o['5342'] = 58 + __o['5343'] = 32 + __o['5344'] = 48 + __o['5345'] = 120 + __o['5346'] = 37 + __o['5347'] = 120 + __o['5348'] = 44 + __o['5349'] = 32 + __o['5350'] = 116 + __o['5351'] = 105 + __o['5352'] = 109 + __o['5353'] = 101 + __o['5354'] = 111 + __o['5355'] = 117 + __o['5356'] = 116 + __o['5357'] = 58 + __o['5358'] = 32 + __o['5359'] = 37 + __o['5360'] = 100 + __o['5361'] = 0 + __o['5362'] = 76 + __o['5363'] = 68 + __o['5364'] = 95 + __o['5365'] = 114 + __o['5366'] = 101 + __o['5367'] = 97 + __o['5368'] = 100 + __o['5369'] = 121 + __o['5370'] = 58 + __o['5371'] = 32 + __o['5372'] = 116 + __o['5373'] = 115 + __o['5374'] = 107 + __o['5375'] = 58 + __o['5376'] = 32 + __o['5377'] = 48 + __o['5378'] = 120 + __o['5379'] = 37 + __o['5380'] = 120 + __o['5381'] = 44 + __o['5382'] = 32 + __o['5383'] = 102 + __o['5384'] = 117 + __o['5385'] = 110 + __o['5386'] = 99 + __o['5387'] = 58 + __o['5388'] = 32 + __o['5389'] = 48 + __o['5390'] = 120 + __o['5391'] = 37 + __o['5392'] = 120 + __o['5393'] = 44 + __o['5394'] = 32 + __o['5395'] = 112 + __o['5396'] = 114 + __o['5397'] = 105 + __o['5398'] = 58 + __o['5399'] = 32 + __o['5400'] = 37 + __o['5401'] = 100 + __o['5402'] = 0 + __o['5403'] = 76 + __o['5404'] = 68 + __o['5405'] = 95 + __o['5406'] = 98 + __o['5407'] = 108 + __o['5408'] = 111 + __o['5409'] = 99 + __o['5410'] = 107 + __o['5411'] = 58 + __o['5412'] = 32 + __o['5413'] = 116 + __o['5414'] = 115 + __o['5415'] = 107 + __o['5416'] = 58 + __o['5417'] = 32 + __o['5418'] = 48 + __o['5419'] = 120 + __o['5420'] = 37 + __o['5421'] = 120 + __o['5422'] = 44 + __o['5423'] = 32 + __o['5424'] = 102 + __o['5425'] = 117 + __o['5426'] = 110 + __o['5427'] = 99 + __o['5428'] = 58 + __o['5429'] = 32 + __o['5430'] = 48 + __o['5431'] = 120 + __o['5432'] = 37 + __o['5433'] = 120 + __o['5434'] = 0 + __o['5435'] = 76 + __o['5436'] = 77 + __o['5437'] = 95 + __o['5438'] = 121 + __o['5439'] = 105 + __o['5440'] = 101 + __o['5441'] = 108 + __o['5442'] = 100 + __o['5443'] = 58 + __o['5444'] = 32 + __o['5445'] = 116 + __o['5446'] = 115 + __o['5447'] = 107 + __o['5448'] = 58 + __o['5449'] = 32 + __o['5450'] = 48 + __o['5451'] = 120 + __o['5452'] = 37 + __o['5453'] = 120 + __o['5454'] = 44 + __o['5455'] = 32 + __o['5456'] = 102 + __o['5457'] = 117 + __o['5458'] = 110 + __o['5459'] = 99 + __o['5460'] = 58 + __o['5461'] = 32 + __o['5462'] = 48 + __o['5463'] = 120 + __o['5464'] = 37 + __o['5465'] = 120 + __o['5466'] = 44 + __o['5467'] = 32 + __o['5468'] = 99 + __o['5469'] = 117 + __o['5470'] = 114 + __o['5471'] = 114 + __o['5472'] = 84 + __o['5473'] = 104 + __o['5474'] = 114 + __o['5475'] = 101 + __o['5476'] = 97 + __o['5477'] = 100 + __o['5478'] = 58 + __o['5479'] = 32 + __o['5480'] = 37 + __o['5481'] = 100 + __o['5482'] = 0 + __o['5483'] = 76 + __o['5484'] = 77 + __o['5485'] = 95 + __o['5486'] = 115 + __o['5487'] = 101 + __o['5488'] = 116 + __o['5489'] = 80 + __o['5490'] = 114 + __o['5491'] = 105 + __o['5492'] = 58 + __o['5493'] = 32 + __o['5494'] = 116 + __o['5495'] = 115 + __o['5496'] = 107 + __o['5497'] = 58 + __o['5498'] = 32 + __o['5499'] = 48 + __o['5500'] = 120 + __o['5501'] = 37 + __o['5502'] = 120 + __o['5503'] = 44 + __o['5504'] = 32 + __o['5505'] = 102 + __o['5506'] = 117 + __o['5507'] = 110 + __o['5508'] = 99 + __o['5509'] = 58 + __o['5510'] = 32 + __o['5511'] = 48 + __o['5512'] = 120 + __o['5513'] = 37 + __o['5514'] = 120 + __o['5515'] = 44 + __o['5516'] = 32 + __o['5517'] = 111 + __o['5518'] = 108 + __o['5519'] = 100 + __o['5520'] = 80 + __o['5521'] = 114 + __o['5522'] = 105 + __o['5523'] = 58 + __o['5524'] = 32 + __o['5525'] = 37 + __o['5526'] = 100 + __o['5527'] = 44 + __o['5528'] = 32 + __o['5529'] = 110 + __o['5530'] = 101 + __o['5531'] = 119 + __o['5532'] = 80 + __o['5533'] = 114 + __o['5534'] = 105 + __o['5535'] = 32 + __o['5536'] = 37 + __o['5537'] = 100 + __o['5538'] = 0 + __o['5539'] = 76 + __o['5540'] = 68 + __o['5541'] = 95 + __o['5542'] = 101 + __o['5543'] = 120 + __o['5544'] = 105 + __o['5545'] = 116 + __o['5546'] = 58 + __o['5547'] = 32 + __o['5548'] = 116 + __o['5549'] = 115 + __o['5550'] = 107 + __o['5551'] = 58 + __o['5552'] = 32 + __o['5553'] = 48 + __o['5554'] = 120 + __o['5555'] = 37 + __o['5556'] = 120 + __o['5557'] = 44 + __o['5558'] = 32 + __o['5559'] = 102 + __o['5560'] = 117 + __o['5561'] = 110 + __o['5562'] = 99 + __o['5563'] = 58 + __o['5564'] = 32 + __o['5565'] = 48 + __o['5566'] = 120 + __o['5567'] = 37 + __o['5568'] = 120 + __o['5569'] = 0 + __o['5570'] = 76 + __o['5571'] = 77 + __o['5572'] = 95 + __o['5573'] = 115 + __o['5574'] = 101 + __o['5575'] = 116 + __o['5576'] = 65 + __o['5577'] = 102 + __o['5578'] = 102 + __o['5579'] = 105 + __o['5580'] = 110 + __o['5581'] = 105 + __o['5582'] = 116 + __o['5583'] = 121 + __o['5584'] = 58 + __o['5585'] = 32 + __o['5586'] = 116 + __o['5587'] = 115 + __o['5588'] = 107 + __o['5589'] = 58 + __o['5590'] = 32 + __o['5591'] = 48 + __o['5592'] = 120 + __o['5593'] = 37 + __o['5594'] = 120 + __o['5595'] = 44 + __o['5596'] = 32 + __o['5597'] = 102 + __o['5598'] = 117 + __o['5599'] = 110 + __o['5600'] = 99 + __o['5601'] = 58 + __o['5602'] = 32 + __o['5603'] = 48 + __o['5604'] = 120 + __o['5605'] = 37 + __o['5606'] = 120 + __o['5607'] = 44 + __o['5608'] = 32 + __o['5609'] = 111 + __o['5610'] = 108 + __o['5611'] = 100 + __o['5612'] = 67 + __o['5613'] = 111 + __o['5614'] = 114 + __o['5615'] = 101 + __o['5616'] = 58 + __o['5617'] = 32 + __o['5618'] = 37 + __o['5619'] = 100 + __o['5620'] = 44 + __o['5621'] = 32 + __o['5622'] = 111 + __o['5623'] = 108 + __o['5624'] = 100 + __o['5625'] = 65 + __o['5626'] = 102 + __o['5627'] = 102 + __o['5628'] = 105 + __o['5629'] = 110 + __o['5630'] = 105 + __o['5631'] = 116 + __o['5632'] = 121 + __o['5633'] = 32 + __o['5634'] = 37 + __o['5635'] = 100 + __o['5636'] = 44 + __o['5637'] = 32 + __o['5638'] = 110 + __o['5639'] = 101 + __o['5640'] = 119 + __o['5641'] = 65 + __o['5642'] = 102 + __o['5643'] = 102 + __o['5644'] = 105 + __o['5645'] = 110 + __o['5646'] = 105 + __o['5647'] = 116 + __o['5648'] = 121 + __o['5649'] = 32 + __o['5650'] = 37 + __o['5651'] = 100 + __o['5652'] = 0 + __o['5653'] = 76 + __o['5654'] = 68 + __o['5655'] = 95 + __o['5656'] = 115 + __o['5657'] = 99 + __o['5658'] = 104 + __o['5659'] = 101 + __o['5660'] = 100 + __o['5661'] = 117 + __o['5662'] = 108 + __o['5663'] = 101 + __o['5664'] = 58 + __o['5665'] = 32 + __o['5666'] = 99 + __o['5667'] = 111 + __o['5668'] = 114 + __o['5669'] = 101 + __o['5670'] = 73 + __o['5671'] = 100 + __o['5672'] = 58 + __o['5673'] = 32 + __o['5674'] = 37 + __o['5675'] = 100 + __o['5676'] = 44 + __o['5677'] = 32 + __o['5678'] = 119 + __o['5679'] = 111 + __o['5680'] = 114 + __o['5681'] = 107 + __o['5682'] = 70 + __o['5683'] = 108 + __o['5684'] = 97 + __o['5685'] = 103 + __o['5686'] = 58 + __o['5687'] = 32 + __o['5688'] = 37 + __o['5689'] = 100 + __o['5690'] = 44 + __o['5691'] = 32 + __o['5692'] = 99 + __o['5693'] = 117 + __o['5694'] = 114 + __o['5695'] = 83 + __o['5696'] = 101 + __o['5697'] = 116 + __o['5698'] = 76 + __o['5699'] = 111 + __o['5700'] = 99 + __o['5701'] = 97 + __o['5702'] = 108 + __o['5703'] = 58 + __o['5704'] = 32 + __o['5705'] = 37 + __o['5706'] = 100 + __o['5707'] = 44 + __o['5708'] = 32 + __o['5709'] = 99 + __o['5710'] = 117 + __o['5711'] = 114 + __o['5712'] = 83 + __o['5713'] = 101 + __o['5714'] = 116 + __o['5715'] = 88 + __o['5716'] = 58 + __o['5717'] = 32 + __o['5718'] = 37 + __o['5719'] = 100 + __o['5720'] = 44 + __o['5721'] = 32 + __o['5722'] = 99 + __o['5723'] = 117 + __o['5724'] = 114 + __o['5725'] = 77 + __o['5726'] = 97 + __o['5727'] = 115 + __o['5728'] = 107 + __o['5729'] = 76 + __o['5730'] = 111 + __o['5731'] = 99 + __o['5732'] = 97 + __o['5733'] = 108 + __o['5734'] = 58 + __o['5735'] = 32 + __o['5736'] = 37 + __o['5737'] = 100 + __o['5738'] = 0 + __o['5739'] = 76 + __o['5740'] = 68 + __o['5741'] = 95 + __o['5742'] = 110 + __o['5743'] = 111 + __o['5744'] = 87 + __o['5745'] = 111 + __o['5746'] = 114 + __o['5747'] = 107 + __o['5748'] = 58 + __o['5749'] = 32 + __o['5750'] = 99 + __o['5751'] = 111 + __o['5752'] = 114 + __o['5753'] = 101 + __o['5754'] = 73 + __o['5755'] = 100 + __o['5756'] = 58 + __o['5757'] = 32 + __o['5758'] = 37 + __o['5759'] = 100 + __o['5760'] = 44 + __o['5761'] = 32 + __o['5762'] = 99 + __o['5763'] = 117 + __o['5764'] = 114 + __o['5765'] = 83 + __o['5766'] = 101 + __o['5767'] = 116 + __o['5768'] = 76 + __o['5769'] = 111 + __o['5770'] = 99 + __o['5771'] = 97 + __o['5772'] = 108 + __o['5773'] = 58 + __o['5774'] = 32 + __o['5775'] = 37 + __o['5776'] = 100 + __o['5777'] = 44 + __o['5778'] = 32 + __o['5779'] = 99 + __o['5780'] = 117 + __o['5781'] = 114 + __o['5782'] = 83 + __o['5783'] = 101 + __o['5784'] = 116 + __o['5785'] = 88 + __o['5786'] = 58 + __o['5787'] = 32 + __o['5788'] = 37 + __o['5789'] = 100 + __o['5790'] = 44 + __o['5791'] = 32 + __o['5792'] = 99 + __o['5793'] = 117 + __o['5794'] = 114 + __o['5795'] = 77 + __o['5796'] = 97 + __o['5797'] = 115 + __o['5798'] = 107 + __o['5799'] = 76 + __o['5800'] = 111 + __o['5801'] = 99 + __o['5802'] = 97 + __o['5803'] = 108 + __o['5804'] = 58 + __o['5805'] = 32 + __o['5806'] = 37 + __o['5807'] = 100 + __o['5808'] = 0 + __o['5809'] = 76 + __o['5810'] = 77 + __o['5811'] = 95 + __o['5812'] = 98 + __o['5813'] = 101 + __o['5814'] = 103 + __o['5815'] = 105 + __o['5816'] = 110 + __o['5817'] = 58 + __o['5818'] = 32 + __o['5819'] = 104 + __o['5820'] = 119 + __o['5821'] = 105 + __o['5822'] = 58 + __o['5823'] = 32 + __o['5824'] = 48 + __o['5825'] = 120 + __o['5826'] = 37 + __o['5827'] = 120 + __o['5828'] = 44 + __o['5829'] = 32 + __o['5830'] = 102 + __o['5831'] = 117 + __o['5832'] = 110 + __o['5833'] = 99 + __o['5834'] = 58 + __o['5835'] = 32 + __o['5836'] = 48 + __o['5837'] = 120 + __o['5838'] = 37 + __o['5839'] = 120 + __o['5840'] = 44 + __o['5841'] = 32 + __o['5842'] = 112 + __o['5843'] = 114 + __o['5844'] = 101 + __o['5845'] = 84 + __o['5846'] = 104 + __o['5847'] = 114 + __o['5848'] = 101 + __o['5849'] = 97 + __o['5850'] = 100 + __o['5851'] = 58 + __o['5852'] = 32 + __o['5853'] = 37 + __o['5854'] = 100 + __o['5855'] = 44 + __o['5856'] = 32 + __o['5857'] = 105 + __o['5858'] = 110 + __o['5859'] = 116 + __o['5860'] = 78 + __o['5861'] = 117 + __o['5862'] = 109 + __o['5863'] = 58 + __o['5864'] = 32 + __o['5865'] = 37 + __o['5866'] = 100 + __o['5867'] = 44 + __o['5868'] = 32 + __o['5869'] = 105 + __o['5870'] = 114 + __o['5871'] = 112 + __o['5872'] = 58 + __o['5873'] = 32 + __o['5874'] = 48 + __o['5875'] = 120 + __o['5876'] = 37 + __o['5877'] = 120 + __o['5878'] = 0 + __o['5879'] = 76 + __o['5880'] = 68 + __o['5881'] = 95 + __o['5882'] = 101 + __o['5883'] = 110 + __o['5884'] = 100 + __o['5885'] = 58 + __o['5886'] = 32 + __o['5887'] = 104 + __o['5888'] = 119 + __o['5889'] = 105 + __o['5890'] = 58 + __o['5891'] = 32 + __o['5892'] = 48 + __o['5893'] = 120 + __o['5894'] = 37 + __o['5895'] = 120 + __o['5896'] = 0 + __o['5897'] = 120 + __o['5898'] = 100 + __o['5899'] = 99 + __o['5900'] = 46 + __o['5901'] = 0 + __o['5902'] = 114 + __o['5903'] = 117 + __o['5904'] = 110 + __o['5905'] = 116 + __o['5906'] = 105 + __o['5907'] = 109 + __o['5908'] = 101 + __o['5909'] = 46 + __o['5910'] = 0 + __o['5911'] = 65 + __o['5912'] = 115 + __o['5913'] = 115 + __o['5914'] = 101 + __o['5915'] = 114 + __o['5916'] = 116 + __o['5917'] = 0 + __o['5918'] = 67 + __o['5919'] = 111 + __o['5920'] = 114 + __o['5921'] = 101 + __o['5922'] = 0 + __o['5923'] = 68 + __o['5924'] = 101 + __o['5925'] = 102 + __o['5926'] = 97 + __o['5927'] = 117 + __o['5928'] = 108 + __o['5929'] = 116 + __o['5930'] = 115 + __o['5931'] = 0 + __o['5932'] = 68 + __o['5933'] = 105 + __o['5934'] = 97 + __o['5935'] = 103 + __o['5936'] = 115 + __o['5937'] = 0 + __o['5938'] = 69 + __o['5939'] = 114 + __o['5940'] = 114 + __o['5941'] = 111 + __o['5942'] = 114 + __o['5943'] = 0 + __o['5944'] = 71 + __o['5945'] = 97 + __o['5946'] = 116 + __o['5947'] = 101 + __o['5948'] = 0 + __o['5949'] = 76 + __o['5950'] = 111 + __o['5951'] = 103 + __o['5952'] = 0 + __o['5953'] = 77 + __o['5954'] = 97 + __o['5955'] = 105 + __o['5956'] = 110 + __o['5957'] = 0 + __o['5958'] = 77 + __o['5959'] = 101 + __o['5960'] = 109 + __o['5961'] = 111 + __o['5962'] = 114 + __o['5963'] = 121 + __o['5964'] = 0 + __o['5965'] = 82 + __o['5966'] = 101 + __o['5967'] = 103 + __o['5968'] = 105 + __o['5969'] = 115 + __o['5970'] = 116 + __o['5971'] = 114 + __o['5972'] = 121 + __o['5973'] = 0 + __o['5974'] = 83 + __o['5975'] = 116 + __o['5976'] = 97 + __o['5977'] = 114 + __o['5978'] = 116 + __o['5979'] = 117 + __o['5980'] = 112 + __o['5981'] = 0 + __o['5982'] = 83 + __o['5983'] = 121 + __o['5984'] = 115 + __o['5985'] = 116 + __o['5986'] = 101 + __o['5987'] = 109 + __o['5988'] = 0 + __o['5989'] = 83 + __o['5990'] = 121 + __o['5991'] = 115 + __o['5992'] = 77 + __o['5993'] = 105 + __o['5994'] = 110 + __o['5995'] = 0 + __o['5996'] = 84 + __o['5997'] = 101 + __o['5998'] = 120 + __o['5999'] = 116 + __o['6000'] = 0 + __o['6001'] = 116 + __o['6002'] = 105 + __o['6003'] = 46 + __o['6004'] = 0 + __o['6005'] = 99 + __o['6006'] = 97 + __o['6007'] = 116 + __o['6008'] = 97 + __o['6009'] = 108 + __o['6010'] = 111 + __o['6011'] = 103 + __o['6012'] = 46 + __o['6013'] = 0 + __o['6014'] = 97 + __o['6015'] = 114 + __o['6016'] = 109 + __o['6017'] = 46 + __o['6018'] = 0 + __o['6019'] = 99 + __o['6020'] = 111 + __o['6021'] = 114 + __o['6022'] = 116 + __o['6023'] = 101 + __o['6024'] = 120 + __o['6025'] = 109 + __o['6026'] = 52 + __o['6027'] = 46 + __o['6028'] = 0 + __o['6029'] = 116 + __o['6030'] = 105 + __o['6031'] = 118 + __o['6032'] = 97 + __o['6033'] = 46 + __o['6034'] = 0 + __o['6035'] = 99 + __o['6036'] = 101 + __o['6037'] = 46 + __o['6038'] = 0 + __o['6039'] = 66 + __o['6040'] = 111 + __o['6041'] = 111 + __o['6042'] = 116 + __o['6043'] = 0 + __o['6044'] = 115 + __o['6045'] = 121 + __o['6046'] = 115 + __o['6047'] = 98 + __o['6048'] = 105 + __o['6049'] = 111 + __o['6050'] = 115 + __o['6051'] = 46 + __o['6052'] = 0 + __o['6053'] = 107 + __o['6054'] = 110 + __o['6055'] = 108 + __o['6056'] = 46 + __o['6057'] = 0 + __o['6058'] = 67 + __o['6059'] = 108 + __o['6060'] = 111 + __o['6061'] = 99 + __o['6062'] = 107 + __o['6063'] = 0 + __o['6064'] = 73 + __o['6065'] = 100 + __o['6066'] = 108 + __o['6067'] = 101 + __o['6068'] = 0 + __o['6069'] = 73 + __o['6070'] = 110 + __o['6071'] = 116 + __o['6072'] = 114 + __o['6073'] = 105 + __o['6074'] = 110 + __o['6075'] = 115 + __o['6076'] = 105 + __o['6077'] = 99 + __o['6078'] = 115 + __o['6079'] = 0 + __o['6080'] = 81 + __o['6081'] = 117 + __o['6082'] = 101 + __o['6083'] = 117 + __o['6084'] = 101 + __o['6085'] = 0 + __o['6086'] = 83 + __o['6087'] = 101 + __o['6088'] = 109 + __o['6089'] = 97 + __o['6090'] = 112 + __o['6091'] = 104 + __o['6092'] = 111 + __o['6093'] = 114 + __o['6094'] = 101 + __o['6095'] = 0 + __o['6096'] = 83 + __o['6097'] = 119 + __o['6098'] = 105 + __o['6099'] = 0 + __o['6100'] = 84 + __o['6101'] = 97 + __o['6102'] = 115 + __o['6103'] = 107 + __o['6104'] = 0 + __o['6105'] = 104 + __o['6106'] = 97 + __o['6107'] = 108 + __o['6108'] = 46 + __o['6109'] = 0 + __o['6110'] = 72 + __o['6111'] = 119 + __o['6112'] = 105 + __o['6113'] = 0 + __o['6114'] = 66 + __o['6115'] = 73 + __o['6116'] = 79 + __o['6117'] = 83 + __o['6118'] = 0 + __o['6119'] = 102 + __o['6120'] = 97 + __o['6121'] = 109 + __o['6122'] = 105 + __o['6123'] = 108 + __o['6124'] = 121 + __o['6125'] = 46 + __o['6126'] = 0 + __o['6127'] = 109 + __o['6128'] = 51 + __o['6129'] = 46 + __o['6130'] = 0 + __o['6131'] = 73 + __o['6132'] = 110 + __o['6133'] = 116 + __o['6134'] = 114 + __o['6135'] = 105 + __o['6136'] = 110 + __o['6137'] = 115 + __o['6138'] = 105 + __o['6139'] = 99 + __o['6140'] = 115 + __o['6141'] = 83 + __o['6142'] = 117 + __o['6143'] = 112 + __o['6144'] = 112 + __o['6145'] = 111 + __o['6146'] = 114 + __o['6147'] = 116 + __o['6148'] = 0 + __o['6149'] = 84 + __o['6150'] = 97 + __o['6151'] = 115 + __o['6152'] = 107 + __o['6153'] = 83 + __o['6154'] = 117 + __o['6155'] = 112 + __o['6156'] = 112 + __o['6157'] = 111 + __o['6158'] = 114 + __o['6159'] = 116 + __o['6160'] = 0 + __o['6161'] = 103 + __o['6162'] = 97 + __o['6163'] = 116 + __o['6164'] = 101 + __o['6165'] = 115 + __o['6166'] = 46 + __o['6167'] = 0 + __o['6168'] = 71 + __o['6169'] = 97 + __o['6170'] = 116 + __o['6171'] = 101 + __o['6172'] = 72 + __o['6173'] = 119 + __o['6174'] = 105 + __o['6175'] = 0 + __o['6176'] = 71 + __o['6177'] = 97 + __o['6178'] = 116 + __o['6179'] = 101 + __o['6180'] = 77 + __o['6181'] = 117 + __o['6182'] = 116 + __o['6183'] = 101 + __o['6184'] = 120 + __o['6185'] = 0 + __o['6186'] = 104 + __o['6187'] = 101 + __o['6188'] = 97 + __o['6189'] = 112 + __o['6190'] = 115 + __o['6191'] = 46 + __o['6192'] = 0 + __o['6193'] = 72 + __o['6194'] = 101 + __o['6195'] = 97 + __o['6196'] = 112 + __o['6197'] = 77 + __o['6198'] = 101 + __o['6199'] = 109 + __o['6200'] = 0 + __o['6201'] = 108 + __o['6202'] = 109 + __o['6203'] = 52 + __o['6204'] = 46 + __o['6205'] = 0 + __o['6206'] = 84 + __o['6207'] = 105 + __o['6208'] = 109 + __o['6209'] = 101 + __o['6210'] = 114 + __o['6211'] = 0 + __o['6212'] = 85 + __o['6213'] = 65 + __o['6214'] = 82 + __o['6215'] = 84 + __o['6216'] = 77 + __o['6217'] = 111 + __o['6218'] = 110 + __o['6219'] = 84 + __o['6220'] = 97 + __o['6221'] = 115 + __o['6222'] = 107 + __o['6223'] = 0 + __o['6224'] = 116 + __o['6225'] = 105 + __o['6226'] = 46 + __o['6227'] = 115 + __o['6228'] = 121 + __o['6229'] = 115 + __o['6230'] = 98 + __o['6231'] = 105 + __o['6232'] = 111 + __o['6233'] = 115 + __o['6234'] = 46 + __o['6235'] = 107 + __o['6236'] = 110 + __o['6237'] = 108 + __o['6238'] = 46 + __o['6239'] = 84 + __o['6240'] = 97 + __o['6241'] = 115 + __o['6242'] = 107 + __o['6243'] = 46 + __o['6244'] = 73 + __o['6245'] = 100 + __o['6246'] = 108 + __o['6247'] = 101 + __o['6248'] = 84 + __o['6249'] = 97 + __o['6250'] = 115 + __o['6251'] = 107 + __o['6252'] = 0 + +__o = __obj[470] // xdc.runtime.Text/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[471] // xdc.runtime.Text/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[472.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[474.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[476.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[478.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[480.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[482.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[472] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[473.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[473] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[474] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[475.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[475] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[476] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[477.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[477] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[478] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[479.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[479] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[480] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[481.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[481] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[482] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[483.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[483] // xdc.runtime.Text/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[484] // xdc.runtime.Text/nodeTab + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab', 'UTF-8')) + __o['0'] = __obj[485.0] + __o['1'] = __obj[486.0] + __o['2'] = __obj[487.0] + __o['3'] = __obj[488.0] + __o['4'] = __obj[489.0] + __o['5'] = __obj[490.0] + __o['6'] = __obj[491.0] + __o['7'] = __obj[492.0] + __o['8'] = __obj[493.0] + __o['9'] = __obj[494.0] + __o['10'] = __obj[495.0] + __o['11'] = __obj[496.0] + __o['12'] = __obj[497.0] + __o['13'] = __obj[498.0] + __o['14'] = __obj[499.0] + __o['15'] = __obj[500.0] + __o['16'] = __obj[501.0] + __o['17'] = __obj[502.0] + __o['18'] = __obj[503.0] + __o['19'] = __obj[504.0] + __o['20'] = __obj[505.0] + __o['21'] = __obj[506.0] + __o['22'] = __obj[507.0] + __o['23'] = __obj[508.0] + __o['24'] = __obj[509.0] + __o['25'] = __obj[510.0] + __o['26'] = __obj[511.0] + __o['27'] = __obj[512.0] + __o['28'] = __obj[513.0] + __o['29'] = __obj[514.0] + __o['30'] = __obj[515.0] + __o['31'] = __obj[516.0] + __o['32'] = __obj[517.0] + __o['33'] = __obj[518.0] + __o['34'] = __obj[519.0] + __o['35'] = __obj[520.0] + __o['36'] = __obj[521.0] + __o['37'] = __obj[522.0] + __o['38'] = __obj[523.0] + __o['39'] = __obj[524.0] + __o['40'] = __obj[525.0] + __o['41'] = __obj[526.0] + __o['42'] = __obj[527.0] + __o['43'] = __obj[528.0] + __o['44'] = __obj[529.0] + __o['45'] = __obj[530.0] + __o['46'] = __obj[531.0] + +__o = __obj[485] // xdc.runtime.Text/nodeTab/0 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F0', 'UTF-8')) + __o['left'] = 0 + __o['right'] = 0 + +__o = __obj[486] // xdc.runtime.Text/nodeTab/1 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F1', 'UTF-8')) + __o['left'] = 5897 + __o['right'] = 5902 + +__o = __obj[487] // xdc.runtime.Text/nodeTab/2 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F2', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5911 + +__o = __obj[488] // xdc.runtime.Text/nodeTab/3 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F3', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5918 + +__o = __obj[489] // xdc.runtime.Text/nodeTab/4 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F4', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5923 + +__o = __obj[490] // xdc.runtime.Text/nodeTab/5 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F5', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5932 + +__o = __obj[491] // xdc.runtime.Text/nodeTab/6 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F6', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5938 + +__o = __obj[492] // xdc.runtime.Text/nodeTab/7 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F7', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5944 + +__o = __obj[493] // xdc.runtime.Text/nodeTab/8 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F8', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5949 + +__o = __obj[494] // xdc.runtime.Text/nodeTab/9 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F9', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5953 + +__o = __obj[495] // xdc.runtime.Text/nodeTab/10 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F10', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5958 + +__o = __obj[496] // xdc.runtime.Text/nodeTab/11 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F11', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5965 + +__o = __obj[497] // xdc.runtime.Text/nodeTab/12 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F12', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5974 + +__o = __obj[498] // xdc.runtime.Text/nodeTab/13 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F13', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5982 + +__o = __obj[499] // xdc.runtime.Text/nodeTab/14 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F14', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5989 + +__o = __obj[500] // xdc.runtime.Text/nodeTab/15 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F15', 'UTF-8')) + __o['left'] = 32769 + __o['right'] = 5996 + +__o = __obj[501] // xdc.runtime.Text/nodeTab/16 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F16', 'UTF-8')) + __o['left'] = 6001 + __o['right'] = 6005 + +__o = __obj[502] // xdc.runtime.Text/nodeTab/17 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F17', 'UTF-8')) + __o['left'] = 32784 + __o['right'] = 6014 + +__o = __obj[503] // xdc.runtime.Text/nodeTab/18 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F18', 'UTF-8')) + __o['left'] = 32785 + __o['right'] = 6019 + +__o = __obj[504] // xdc.runtime.Text/nodeTab/19 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F19', 'UTF-8')) + __o['left'] = 32786 + __o['right'] = 6029 + +__o = __obj[505] // xdc.runtime.Text/nodeTab/20 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F20', 'UTF-8')) + __o['left'] = 32787 + __o['right'] = 6035 + +__o = __obj[506] // xdc.runtime.Text/nodeTab/21 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F21', 'UTF-8')) + __o['left'] = 32788 + __o['right'] = 6039 + +__o = __obj[507] // xdc.runtime.Text/nodeTab/22 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F22', 'UTF-8')) + __o['left'] = 6001 + __o['right'] = 6044 + +__o = __obj[508] // xdc.runtime.Text/nodeTab/23 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F23', 'UTF-8')) + __o['left'] = 32790 + __o['right'] = 6053 + +__o = __obj[509] // xdc.runtime.Text/nodeTab/24 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F24', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6058 + +__o = __obj[510] // xdc.runtime.Text/nodeTab/25 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F25', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6064 + +__o = __obj[511] // xdc.runtime.Text/nodeTab/26 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F26', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6069 + +__o = __obj[512] // xdc.runtime.Text/nodeTab/27 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F27', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6080 + +__o = __obj[513] // xdc.runtime.Text/nodeTab/28 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F28', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6086 + +__o = __obj[514] // xdc.runtime.Text/nodeTab/29 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F29', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6096 + +__o = __obj[515] // xdc.runtime.Text/nodeTab/30 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F30', 'UTF-8')) + __o['left'] = 32791 + __o['right'] = 6100 + +__o = __obj[516] // xdc.runtime.Text/nodeTab/31 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F31', 'UTF-8')) + __o['left'] = 32790 + __o['right'] = 6105 + +__o = __obj[517] // xdc.runtime.Text/nodeTab/32 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F32', 'UTF-8')) + __o['left'] = 32799 + __o['right'] = 6110 + +__o = __obj[518] // xdc.runtime.Text/nodeTab/33 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F33', 'UTF-8')) + __o['left'] = 32790 + __o['right'] = 6114 + +__o = __obj[519] // xdc.runtime.Text/nodeTab/34 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F34', 'UTF-8')) + __o['left'] = 32790 + __o['right'] = 6119 + +__o = __obj[520] // xdc.runtime.Text/nodeTab/35 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F35', 'UTF-8')) + __o['left'] = 32802 + __o['right'] = 6014 + +__o = __obj[521] // xdc.runtime.Text/nodeTab/36 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F36', 'UTF-8')) + __o['left'] = 32803 + __o['right'] = 6127 + +__o = __obj[522] // xdc.runtime.Text/nodeTab/37 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F37', 'UTF-8')) + __o['left'] = 32804 + __o['right'] = 6110 + +__o = __obj[523] // xdc.runtime.Text/nodeTab/38 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F38', 'UTF-8')) + __o['left'] = 32804 + __o['right'] = 6131 + +__o = __obj[524] // xdc.runtime.Text/nodeTab/39 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F39', 'UTF-8')) + __o['left'] = 32804 + __o['right'] = 6149 + +__o = __obj[525] // xdc.runtime.Text/nodeTab/40 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F40', 'UTF-8')) + __o['left'] = 32790 + __o['right'] = 6161 + +__o = __obj[526] // xdc.runtime.Text/nodeTab/41 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F41', 'UTF-8')) + __o['left'] = 32808 + __o['right'] = 6168 + +__o = __obj[527] // xdc.runtime.Text/nodeTab/42 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F42', 'UTF-8')) + __o['left'] = 32808 + __o['right'] = 6176 + +__o = __obj[528] // xdc.runtime.Text/nodeTab/43 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F43', 'UTF-8')) + __o['left'] = 32790 + __o['right'] = 6186 + +__o = __obj[529] // xdc.runtime.Text/nodeTab/44 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F44', 'UTF-8')) + __o['left'] = 32811 + __o['right'] = 6193 + +__o = __obj[530] // xdc.runtime.Text/nodeTab/45 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F45', 'UTF-8')) + __o['left'] = 32803 + __o['right'] = 6201 + +__o = __obj[531] // xdc.runtime.Text/nodeTab/46 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FnodeTab%2F46', 'UTF-8')) + __o['left'] = 32813 + __o['right'] = 6206 + +__o = __obj[532] // xdc.runtime.Text/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Text%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[533] // ti.catalog.arm.cortexm4.tiva.ce.Boot + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[534.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot', 'UTF-8')) + __o['A_mustNotUseEnhancedClockMode'] = __obj[535.0] + __o['A_mustUseEnhancedClockMode'] = __obj[536.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32789 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[537.0] + __o['computedCpuFrequency'] = 80000000 + __o['configNameMap$'] = __obj[538.0] + __o['configureClock'] = true + __o['configureLdo'] = false + __o['cpuFrequency'] = 80000000 + __o['enhancedClockMode'] = false + __o['ioscDisable'] = false + __o['ldoOut'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot.LDOPCTL_2_50V', 'UTF-8')) + __o['moscDisable'] = false + __o['oscSrc'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot.OSCSRC_MAIN', 'UTF-8')) + __o['pllBypass'] = false + __o['pllOutEnable'] = false + __o['pwmClockDiv'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot.PWMDIV_1', 'UTF-8')) + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[46.0] + __o['sysClockDiv'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot.SYSDIV_2_5', 'UTF-8')) + __o['ulConfig'] = -1056963264 + __o['vcoFreq'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot.VCO_320', 'UTF-8')) + __o['viewNameMap$'] = __obj[551.0] + __o['xtal'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot.XTAL_16MHZ', 'UTF-8')) + +__o = __obj[534] // ti.catalog.arm.cortexm4.tiva.ce.Boot/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2F%24instances', 'UTF-8')) + +__o = __obj[535] // xdc.runtime.Assert.Desc#9 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%239', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_mustNotUseEnhancedClockMode%3A+This+device+does+not+support+the+Enhanced+Clock+Mode.', 'UTF-8')) + +__o = __obj[536] // xdc.runtime.Assert.Desc#8 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%238', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_mustUseEnhancedClockMode%3A+This+device+requires+the+Enhanced+Clock+Mode.', 'UTF-8')) + +__o = __obj[537] // ti.catalog.arm.cortexm4.tiva.ce.Boot/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[538] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[539.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[541.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[543.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[545.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[547.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[549.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[539] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[540.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[540] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[541] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[542.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[542] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[543] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[544.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[544] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[545] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[546.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[546] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[547] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[548.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[548] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[549] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[550.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[550] // ti.catalog.arm.cortexm4.tiva.ce.Boot/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[551] // ti.catalog.arm.cortexm4.tiva.ce.Boot/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.catalog.arm.cortexm4.tiva.ce.Boot%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[552] // ti.sysbios.knl.Clock + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[553.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock', 'UTF-8')) + __o['A_badThreadType'] = __obj[554.0] + __o['A_clockDisabled'] = __obj[555.0] + __o['LM_begin'] = __obj[556.0] + __o['LM_tick'] = __obj[557.0] + __o['LW_delayed'] = __obj[558.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32792 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['TimerProxy'] = __obj[559.0] + __o['common$'] = __obj[585.0] + __o['configNameMap$'] = __obj[586.0] + __o['doTickFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Clock_doTick__I', 'UTF-8')) + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[52.0] + __o['serviceMargin'] = 0 + __o['stopCheckNext'] = false + __o['swiPriority'] = 15 + __o['tickMode'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock.TickMode_PERIODIC', 'UTF-8')) + __o['tickPeriod'] = 1000 + __o['tickSource'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock.TickSource_TIMER', 'UTF-8')) + __o['timerId'] = -1 + __o['timerSupportsDynamic'] = true + __o['triggerClock'] = null + __o['viewNameMap$'] = __obj[599.0] + +__o = __obj[553] // ti.sysbios.knl.Clock/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2F%24instances', 'UTF-8')) + +__o = __obj[554] // xdc.runtime.Assert.Desc#14 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2314', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badThreadType%3A+Cannot+create%2Fdelete+a+Clock+from+Hwi+or+Swi+thread.', 'UTF-8')) + +__o = __obj[555] // xdc.runtime.Assert.Desc#13 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2313', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_clockDisabled%3A+Cannot+create+a+clock+instance+when+BIOS.clockEnabled+is+false.', 'UTF-8')) + +__o = __obj[556] // xdc.runtime.Log.EventDesc#15 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2315', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_begin%3A+clk%3A+0x%25x%2C+func%3A+0x%25x', 'UTF-8')) + +__o = __obj[557] // xdc.runtime.Log.EventDesc#14 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2314', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_tick%3A+tick%3A+%25d', 'UTF-8')) + +__o = __obj[558] // xdc.runtime.Log.EventDesc#13 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2313', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 1024 + __o['msg'] = String(java.net.URLDecoder.decode('LW_delayed%3A+delay%3A+%25d', 'UTF-8')) + +__o = __obj[559] // ti.sysbios.family.arm.lm4.Timer + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[560.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer', 'UTF-8')) + __o['ANY'] = -1 + __o['E_cannotSupport'] = __obj[566.0] + __o['E_invalidTimer'] = __obj[567.0] + __o['E_noaltclk'] = __obj[568.0] + __o['E_notAvailable'] = __obj[569.0] + __o['MAX_PERIOD'] = 4294967295 + __o['MIN_SWEEP_PERIOD'] = 1 + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32814 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['TIMER_CLOCK_DIVIDER'] = 1 + __o['anyMask'] = 63 + __o['common$'] = __obj[570.0] + __o['configNameMap$'] = __obj[571.0] + __o['defaultDynamic'] = false + __o['disableFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_lm4_Timer_disableTiva', 'UTF-8')) + __o['enableFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_lm4_Timer_enableTiva', 'UTF-8')) + __o['numTimerDevices'] = 6 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[146.0] + __o['startupNeeded'] = 1 + __o['supportsAltclk'] = true + __o['supportsDynamic'] = true + __o['viewNameMap$'] = __obj[584.0] + +__o = __obj[560] // ti.sysbios.family.arm.lm4.Timer/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2F%24instances', 'UTF-8')) + __o['0'] = __obj[561.0] + +__o = __obj[561] // ti.sysbios.family.arm.lm4.Timer.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[559.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer.Instance%230', 'UTF-8')) + __o['ANY'] = -1 + __o['MAX_PERIOD'] = 4294967295 + __o['MIN_SWEEP_PERIOD'] = 1 + __o['TIMER_CLOCK_DIVIDER'] = 1 + __o['altclk'] = false + __o['arg'] = null + __o['extFreq'] = __obj[562.0] + __o['hwiParams'] = __obj[563.0] + __o['instance'] = __obj[565.0] + __o['period'] = 1000 + __o['periodType'] = String(java.net.URLDecoder.decode('ti.sysbios.interfaces.ITimer.PeriodType_MICROSECS', 'UTF-8')) + __o['prevThreshold'] = 4294967295 + __o['runMode'] = String(java.net.URLDecoder.decode('ti.sysbios.interfaces.ITimer.RunMode_CONTINUOUS', 'UTF-8')) + __o['startMode'] = String(java.net.URLDecoder.decode('ti.sysbios.interfaces.ITimer.StartMode_AUTO', 'UTF-8')) + +__o = __obj[562] // ti.sysbios.family.arm.lm4.Timer.Instance#0/extFreq + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer.Instance%230%2FextFreq', 'UTF-8')) + __o['hi'] = 0 + __o['lo'] = 0 + +__o = __obj[563] // ti.sysbios.family.arm.m3.Hwi.Params#1 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi.Params%231', 'UTF-8')) + __o['arg'] = __obj[561.0] + __o['enableInt'] = true + __o['eventId'] = -1 + __o['instance'] = __obj[564.0] + __o['maskSetting'] = String(java.net.URLDecoder.decode('ti.sysbios.interfaces.IHwi.MaskingOption_LOWER', 'UTF-8')) + __o['priority'] = 255 + __o['useDispatcher'] = true + +__o = __obj[564] // ti.sysbios.family.arm.m3.Hwi.Params#1/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi.Params%231%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[565] // ti.sysbios.family.arm.lm4.Timer.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[566] // xdc.runtime.Error.Desc#33 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2333', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_cannotSupport%3A+Timer+cannot+support+requested+period+%25d', 'UTF-8')) + +__o = __obj[567] // xdc.runtime.Error.Desc#31 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2331', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_invalidTimer%3A+Invalid+Timer+Id+%25d', 'UTF-8')) + +__o = __obj[568] // xdc.runtime.Error.Desc#34 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2334', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_noaltclk%3A+Timer+does+not+support+altclk', 'UTF-8')) + +__o = __obj[569] // xdc.runtime.Error.Desc#32 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2332', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_notAvailable%3A+Timer+not+available+%25d', 'UTF-8')) + +__o = __obj[570] // ti.sysbios.family.arm.lm4.Timer/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[571] // ti.sysbios.family.arm.lm4.Timer/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[572.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[574.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[576.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[578.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[580.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[582.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[572] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[573.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[573] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[574] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[575.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[575] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[576] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[577.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[577] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[578] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[579.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[579] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[580] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[581.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[581] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[582] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[583.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[583] // ti.sysbios.family.arm.lm4.Timer/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[584] // ti.sysbios.family.arm.lm4.Timer/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.lm4.Timer%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[585] // ti.sysbios.knl.Clock/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[586] // ti.sysbios.knl.Clock/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[587.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[589.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[591.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[593.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[595.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[597.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[587] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[588.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[588] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[589] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[590.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[590] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[591] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[592.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[592] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[593] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[594.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[594] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[595] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[596.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[596] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[597] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[598.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[598] // ti.sysbios.knl.Clock/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[599] // ti.sysbios.knl.Clock/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Clock%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[600] // ti.sysbios.knl.Idle + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[601.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32793 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[602.0] + __o['configNameMap$'] = __obj[603.0] + __o['coreList'] = __obj[616.0] + __o['funcList'] = __obj[617.0] + __o['idleFxns'] = __obj[618.0] + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[56.0] + __o['viewNameMap$'] = __obj[619.0] + +__o = __obj[601] // ti.sysbios.knl.Idle/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2F%24instances', 'UTF-8')) + +__o = __obj[602] // ti.sysbios.knl.Idle/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[603] // ti.sysbios.knl.Idle/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[604.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[606.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[608.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[610.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[612.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[614.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[604] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[605.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[605] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[606] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[607.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[607] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[608] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[609.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[609] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[610] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[611.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[611] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[612] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[613.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[613] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[614] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[615.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[615] // ti.sysbios.knl.Idle/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[616] // ti.sysbios.knl.Idle/coreList + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FcoreList', 'UTF-8')) + __o['0'] = 0 + +__o = __obj[617] // ti.sysbios.knl.Idle/funcList + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FfuncList', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('%26ti_sysbios_hal_Hwi_checkStack', 'UTF-8')) + +__o = __obj[618] // ti.sysbios.knl.Idle/idleFxns + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FidleFxns', 'UTF-8')) + __o['0'] = null + __o['1'] = null + __o['2'] = null + __o['3'] = null + __o['4'] = null + __o['5'] = null + __o['6'] = null + __o['7'] = null + +__o = __obj[619] // ti.sysbios.knl.Idle/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Idle%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[620] // ti.sysbios.knl.Intrinsics + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[621.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32794 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['SupportProxy'] = __obj[622.0] + __o['common$'] = __obj[639.0] + __o['configNameMap$'] = __obj[640.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[653.0] + +__o = __obj[621] // ti.sysbios.knl.Intrinsics/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2F%24instances', 'UTF-8')) + +__o = __obj[622] // ti.sysbios.family.arm.m3.IntrinsicsSupport + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[623.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32806 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[624.0] + __o['configNameMap$'] = __obj[625.0] + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[638.0] + +__o = __obj[623] // ti.sysbios.family.arm.m3.IntrinsicsSupport/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2F%24instances', 'UTF-8')) + +__o = __obj[624] // ti.sysbios.family.arm.m3.IntrinsicsSupport/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[625] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[626.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[628.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[630.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[632.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[634.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[636.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[626] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[627.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[627] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[628] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[629.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[629] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[630] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[631.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[631] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[632] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[633.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[633] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[634] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[635.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[635] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[636] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[637.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[637] // ti.sysbios.family.arm.m3.IntrinsicsSupport/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[638] // ti.sysbios.family.arm.m3.IntrinsicsSupport/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.IntrinsicsSupport%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[639] // ti.sysbios.knl.Intrinsics/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[640] // ti.sysbios.knl.Intrinsics/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[641.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[643.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[645.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[647.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[649.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[651.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[641] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[642.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[642] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[643] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[644.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[644] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[645] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[646.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[646] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[647] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[648.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[648] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[649] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[650.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[650] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[651] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[652.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[652] // ti.sysbios.knl.Intrinsics/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[653] // ti.sysbios.knl.Intrinsics/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Intrinsics%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[654] // ti.sysbios.knl.Queue + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[655.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32795 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[656.0] + __o['configNameMap$'] = __obj[657.0] + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[66.0] + __o['viewNameMap$'] = __obj[670.0] + +__o = __obj[655] // ti.sysbios.knl.Queue/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2F%24instances', 'UTF-8')) + +__o = __obj[656] // ti.sysbios.knl.Queue/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[657] // ti.sysbios.knl.Queue/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[658.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[660.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[662.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[664.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[666.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[668.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[658] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[659.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[659] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[660] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[661.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[661] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[662] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[663.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[663] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[664] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[665.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[665] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[666] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[667.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[667] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[668] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[669.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[669] // ti.sysbios.knl.Queue/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[670] // ti.sysbios.knl.Queue/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Queue%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[671] // ti.sysbios.knl.Semaphore + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[672.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore', 'UTF-8')) + __o['A_badContext'] = __obj[673.0] + __o['A_invTimeout'] = __obj[674.0] + __o['A_noEvents'] = __obj[675.0] + __o['A_overflow'] = __obj[676.0] + __o['A_pendTaskDisabled'] = __obj[677.0] + __o['LM_pend'] = __obj[678.0] + __o['LM_post'] = __obj[679.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32796 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[680.0] + __o['configNameMap$'] = __obj[681.0] + __o['eventPost'] = null + __o['eventSync'] = null + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[69.0] + __o['supportsEvents'] = false + __o['supportsPriority'] = false + __o['viewNameMap$'] = __obj[694.0] + +__o = __obj[672] // ti.sysbios.knl.Semaphore/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2F%24instances', 'UTF-8')) + +__o = __obj[673] // xdc.runtime.Assert.Desc#23 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2323', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badContext%3A+bad+calling+context.+Must+be+called+from+a+Task.', 'UTF-8')) + +__o = __obj[674] // xdc.runtime.Assert.Desc#22 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2322', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_invTimeout%3A+Can%27t+use+BIOS_EVENT_ACQUIRED+with+this+Semaphore.', 'UTF-8')) + +__o = __obj[675] // xdc.runtime.Assert.Desc#21 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2321', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_noEvents%3A+The+Event.supportsEvents+flag+is+disabled.', 'UTF-8')) + +__o = __obj[676] // xdc.runtime.Assert.Desc#24 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2324', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_overflow%3A+Count+has+exceeded+65535+and+rolled+over.', 'UTF-8')) + +__o = __obj[677] // xdc.runtime.Assert.Desc#25 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2325', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_pendTaskDisabled%3A+Cannot+call+Semaphore_pend%28%29+while+the+Task+or+Swi+scheduler+is+disabled.', 'UTF-8')) + +__o = __obj[678] // xdc.runtime.Log.EventDesc#19 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2319', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_pend%3A+sem%3A+0x%25x%2C+count%3A+%25d%2C+timeout%3A+%25d', 'UTF-8')) + +__o = __obj[679] // xdc.runtime.Log.EventDesc#18 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2318', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_post%3A+sem%3A+0x%25x%2C+count%3A+%25d', 'UTF-8')) + +__o = __obj[680] // ti.sysbios.knl.Semaphore/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[681] // ti.sysbios.knl.Semaphore/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[682.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[684.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[686.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[688.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[690.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[692.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[682] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[683.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[683] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[684] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[685.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[685] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[686] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[687.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[687] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[688] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[689.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[689] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[690] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[691.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[691] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[692] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[693.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[693] // ti.sysbios.knl.Semaphore/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[694] // ti.sysbios.knl.Semaphore/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Semaphore%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[695] // ti.sysbios.knl.Swi + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[696.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi', 'UTF-8')) + __o['A_badPriority'] = __obj[699.0] + __o['A_swiDisabled'] = __obj[700.0] + __o['LD_end'] = __obj[701.0] + __o['LM_begin'] = __obj[702.0] + __o['LM_post'] = __obj[703.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32797 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[704.0] + __o['configNameMap$'] = __obj[705.0] + __o['hooks'] = __obj[718.0] + __o['numConstructedSwis'] = 0 + __o['numPriorities'] = 16 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[72.0] + __o['taskDisable'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Task_disable__E', 'UTF-8')) + __o['taskRestore'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Task_restore__E', 'UTF-8')) + __o['viewNameMap$'] = __obj[719.0] + +__o = __obj[696] // ti.sysbios.knl.Swi/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2F%24instances', 'UTF-8')) + __o['0'] = __obj[697.0] + +__o = __obj[697] // ti.sysbios.knl.Swi.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[695.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi.Instance%230', 'UTF-8')) + __o['arg0'] = 0 + __o['arg1'] = 0 + __o['instance'] = __obj[698.0] + __o['priority'] = 15 + __o['trigger'] = 0 + +__o = __obj[698] // ti.sysbios.knl.Swi.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[699] // xdc.runtime.Assert.Desc#27 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2327', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badPriority%3A+An+invalid+Swi+priority+was+used.', 'UTF-8')) + +__o = __obj[700] // xdc.runtime.Assert.Desc#26 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2326', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_swiDisabled%3A+Cannot+create+a+Swi+when+Swi+is+disabled.', 'UTF-8')) + +__o = __obj[701] // xdc.runtime.Log.EventDesc#21 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2321', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 512 + __o['msg'] = String(java.net.URLDecoder.decode('LD_end%3A+swi%3A+0x%25x', 'UTF-8')) + +__o = __obj[702] // xdc.runtime.Log.EventDesc#20 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2320', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_begin%3A+swi%3A+0x%25x%2C+func%3A+0x%25x%2C+preThread%3A+%25d', 'UTF-8')) + +__o = __obj[703] // xdc.runtime.Log.EventDesc#22 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2322', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_post%3A+swi%3A+0x%25x%2C+func%3A+0x%25x%2C+pri%3A+%25d', 'UTF-8')) + +__o = __obj[704] // ti.sysbios.knl.Swi/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[705] // ti.sysbios.knl.Swi/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[706.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[708.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[710.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[712.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[714.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[716.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[706] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[707.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[707] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[708] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[709.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[709] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[710] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[711.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[711] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[712] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[713.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[713] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[714] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[715.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[715] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[716] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[717.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[717] // ti.sysbios.knl.Swi/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[718] // ti.sysbios.knl.Swi/hooks + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2Fhooks', 'UTF-8')) + +__o = __obj[719] // ti.sysbios.knl.Swi/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Swi%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[720] // ti.sysbios.knl.Task + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[721.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task', 'UTF-8')) + __o['AFFINITY_NONE'] = -1 + __o['A_badAffinity'] = __obj[726.0] + __o['A_badPriority'] = __obj[727.0] + __o['A_badTaskState'] = __obj[728.0] + __o['A_badThreadType'] = __obj[729.0] + __o['A_badTimeout'] = __obj[730.0] + __o['A_invalidCoreId'] = __obj[731.0] + __o['A_noPendElem'] = __obj[732.0] + __o['A_sleepTaskDisabled'] = __obj[733.0] + __o['A_taskDisabled'] = __obj[734.0] + __o['E_deleteNotAllowed'] = __obj[735.0] + __o['E_spOutOfBounds'] = __obj[736.0] + __o['E_stackOverflow'] = __obj[737.0] + __o['LD_block'] = __obj[738.0] + __o['LD_exit'] = __obj[739.0] + __o['LD_ready'] = __obj[740.0] + __o['LM_noWork'] = __obj[741.0] + __o['LM_schedule'] = __obj[742.0] + __o['LM_setAffinity'] = __obj[743.0] + __o['LM_setPri'] = __obj[744.0] + __o['LM_sleep'] = __obj[745.0] + __o['LM_switch'] = __obj[746.0] + __o['LM_yield'] = __obj[747.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32798 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['SupportProxy'] = __obj[748.0] + __o['allBlockedFunc'] = null + __o['checkStackFlag'] = true + __o['common$'] = __obj[765.0] + __o['configNameMap$'] = __obj[766.0] + __o['defaultAffinity'] = 0 + __o['defaultStackHeap'] = null + __o['defaultStackSection'] = String(java.net.URLDecoder.decode('.bss%3AtaskStackSection', 'UTF-8')) + __o['defaultStackSize'] = 512 + __o['deleteTerminatedTasks'] = false + __o['enableIdleTask'] = true + __o['hooks'] = __obj[779.0] + __o['idleTaskStackSection'] = String(java.net.URLDecoder.decode('.bss%3AtaskStackSection', 'UTF-8')) + __o['idleTaskStackSize'] = 512 + __o['idleTaskVitalTaskFlag'] = true + __o['initStackFlag'] = true + __o['minimizeLatency'] = false + __o['numConstructedTasks'] = 0 + __o['numPriorities'] = 16 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[77.0] + __o['startupHookFunc'] = null + __o['viewNameMap$'] = __obj[780.0] + +__o = __obj[721] // ti.sysbios.knl.Task/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2F%24instances', 'UTF-8')) + __o['0'] = __obj[722.0] + __o['1'] = __obj[724.0] + +__o = __obj[722] // ti.sysbios.knl.Task.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[720.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.Instance%230', 'UTF-8')) + __o['AFFINITY_NONE'] = -1 + __o['affinity'] = 0 + __o['arg0'] = 0 + __o['arg1'] = 9600 + __o['env'] = null + __o['instance'] = __obj[723.0] + __o['priority'] = 1 + __o['stack'] = null + __o['stackHeap'] = null + __o['stackSection'] = String(java.net.URLDecoder.decode('.bss%3AtaskStackSection', 'UTF-8')) + __o['stackSize'] = 1024 + __o['vitalTaskFlag'] = true + +__o = __obj[723] // ti.sysbios.knl.Task.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = String(java.net.URLDecoder.decode('UARTMonTask', 'UTF-8')) + +__o = __obj[724] // ti.sysbios.knl.Task.Instance#1 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[720.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.Instance%231', 'UTF-8')) + __o['AFFINITY_NONE'] = -1 + __o['affinity'] = 0 + __o['arg0'] = 0 + __o['arg1'] = 0 + __o['env'] = null + __o['instance'] = __obj[725.0] + __o['priority'] = 0 + __o['stack'] = null + __o['stackHeap'] = null + __o['stackSection'] = String(java.net.URLDecoder.decode('.bss%3AtaskStackSection', 'UTF-8')) + __o['stackSize'] = 512 + __o['vitalTaskFlag'] = true + +__o = __obj[725] // ti.sysbios.knl.Task.Instance#1/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.Instance%231%2Finstance', 'UTF-8')) + __o['name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task.IdleTask', 'UTF-8')) + +__o = __obj[726] // xdc.runtime.Assert.Desc#34 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2334', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badAffinity%3A+Invalid+affinity.', 'UTF-8')) + +__o = __obj[727] // xdc.runtime.Assert.Desc#32 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2332', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badPriority%3A+An+invalid+task+priority+was+used.', 'UTF-8')) + +__o = __obj[728] // xdc.runtime.Assert.Desc#29 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2329', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badTaskState%3A+Can%27t+delete+a+task+in+RUNNING+state.', 'UTF-8')) + +__o = __obj[729] // xdc.runtime.Assert.Desc#28 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2328', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badThreadType%3A+Cannot+create%2Fdelete+a+task+from+Hwi+or+Swi+thread.', 'UTF-8')) + +__o = __obj[730] // xdc.runtime.Assert.Desc#33 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2333', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_badTimeout%3A+Can%27t+sleep+FOREVER.', 'UTF-8')) + +__o = __obj[731] // xdc.runtime.Assert.Desc#36 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2336', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_invalidCoreId%3A+Cannot+pass+a+non-zero+CoreId+in+a+non-SMP+application.', 'UTF-8')) + +__o = __obj[732] // xdc.runtime.Assert.Desc#30 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2330', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_noPendElem%3A+Not+enough+info+to+delete+BLOCKED+task.', 'UTF-8')) + +__o = __obj[733] // xdc.runtime.Assert.Desc#35 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2335', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_sleepTaskDisabled%3A+Cannot+call+Task_sleep%28%29+while+the+Task+scheduler+is+disabled.', 'UTF-8')) + +__o = __obj[734] // xdc.runtime.Assert.Desc#31 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2331', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_taskDisabled%3A+Cannot+create+a+task+when+tasking+is+disabled.', 'UTF-8')) + +__o = __obj[735] // xdc.runtime.Error.Desc#10 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2310', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_deleteNotAllowed%3A+Task+0x%25x.', 'UTF-8')) + +__o = __obj[736] // xdc.runtime.Error.Desc#9 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%239', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_spOutOfBounds%3A+Task+0x%25x+stack+error%2C+SP+%3D+0x%25x.', 'UTF-8')) + +__o = __obj[737] // xdc.runtime.Error.Desc#8 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%238', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_stackOverflow%3A+Task+0x%25x+stack+overflow.', 'UTF-8')) + +__o = __obj[738] // xdc.runtime.Log.EventDesc#26 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2326', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 512 + __o['msg'] = String(java.net.URLDecoder.decode('LD_block%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x', 'UTF-8')) + +__o = __obj[739] // xdc.runtime.Log.EventDesc#29 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2329', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 512 + __o['msg'] = String(java.net.URLDecoder.decode('LD_exit%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x', 'UTF-8')) + +__o = __obj[740] // xdc.runtime.Log.EventDesc#25 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2325', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 512 + __o['msg'] = String(java.net.URLDecoder.decode('LD_ready%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+pri%3A+%25d', 'UTF-8')) + +__o = __obj[741] // xdc.runtime.Log.EventDesc#32 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2332', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 1024 + __o['msg'] = String(java.net.URLDecoder.decode('LD_noWork%3A+coreId%3A+%25d%2C+curSetLocal%3A+%25d%2C+curSetX%3A+%25d%2C+curMaskLocal%3A+%25d', 'UTF-8')) + +__o = __obj[742] // xdc.runtime.Log.EventDesc#31 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2331', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 1024 + __o['msg'] = String(java.net.URLDecoder.decode('LD_schedule%3A+coreId%3A+%25d%2C+workFlag%3A+%25d%2C+curSetLocal%3A+%25d%2C+curSetX%3A+%25d%2C+curMaskLocal%3A+%25d', 'UTF-8')) + +__o = __obj[743] // xdc.runtime.Log.EventDesc#30 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2330', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_setAffinity%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+oldCore%3A+%25d%2C+oldAffinity+%25d%2C+newAffinity+%25d', 'UTF-8')) + +__o = __obj[744] // xdc.runtime.Log.EventDesc#28 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2328', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_setPri%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+oldPri%3A+%25d%2C+newPri+%25d', 'UTF-8')) + +__o = __obj[745] // xdc.runtime.Log.EventDesc#24 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2324', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_sleep%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+timeout%3A+%25d', 'UTF-8')) + +__o = __obj[746] // xdc.runtime.Log.EventDesc#23 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2323', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_switch%3A+oldtsk%3A+0x%25x%2C+oldfunc%3A+0x%25x%2C+newtsk%3A+0x%25x%2C+newfunc%3A+0x%25x', 'UTF-8')) + +__o = __obj[747] // xdc.runtime.Log.EventDesc#27 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2327', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_yield%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+currThread%3A+%25d', 'UTF-8')) + +__o = __obj[748] // ti.sysbios.family.arm.m3.TaskSupport + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[749.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32807 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['common$'] = __obj[750.0] + __o['configNameMap$'] = __obj[751.0] + __o['defaultStackSize'] = 2048 + __o['rovShowRawTab$'] = true + __o['stackAlignment'] = 8 + __o['viewNameMap$'] = __obj[764.0] + +__o = __obj[749] // ti.sysbios.family.arm.m3.TaskSupport/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2F%24instances', 'UTF-8')) + +__o = __obj[750] // ti.sysbios.family.arm.m3.TaskSupport/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[751] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[752.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[754.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[756.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[758.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[760.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[762.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[752] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[753.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[753] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[754] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[755.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[755] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[756] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[757.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[757] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[758] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[759.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[759] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[760] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[761.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[761] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[762] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[763.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[763] // ti.sysbios.family.arm.m3.TaskSupport/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[764] // ti.sysbios.family.arm.m3.TaskSupport/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.TaskSupport%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[765] // ti.sysbios.knl.Task/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[766] // ti.sysbios.knl.Task/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[767.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[769.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[771.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[773.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[775.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[777.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[767] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[768.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[768] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[769] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[770.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[770] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[771] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[772.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[772] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[773] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[774.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[774] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[775] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[776.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[776] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[777] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[778.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[778] // ti.sysbios.knl.Task/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[779] // ti.sysbios.knl.Task/hooks + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2Fhooks', 'UTF-8')) + +__o = __obj[780] // ti.sysbios.knl.Task/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.knl.Task%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[781] // ti.sysbios.hal.Hwi + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[782.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi', 'UTF-8')) + __o['E_stackOverflow'] = __obj[783.0] + __o['HwiProxy'] = __obj[784.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32800 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['checkStackFlag'] = true + __o['common$'] = __obj[1041.0] + __o['configNameMap$'] = __obj[1042.0] + __o['dispatcherAutoNestingSupport'] = true + __o['dispatcherIrpTrackingSupport'] = true + __o['dispatcherSwiSupport'] = true + __o['dispatcherTaskSupport'] = true + __o['initStackFlag'] = true + __o['numHooks'] = 0 + __o['rovShowRawTab$'] = true + __o['viewNameMap$'] = __obj[1055.0] + +__o = __obj[782] // ti.sysbios.hal.Hwi/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2F%24instances', 'UTF-8')) + +__o = __obj[783] // xdc.runtime.Error.Desc#11 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2311', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_stackOverflow%3A+ISR+stack+overflow.', 'UTF-8')) + +__o = __obj[784] // ti.sysbios.family.arm.m3.Hwi + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[785.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi', 'UTF-8')) + __o['A_unsupportedMaskingOption'] = __obj[788.0] + __o['E_NMI'] = __obj[789.0] + __o['E_alreadyDefined'] = __obj[790.0] + __o['E_busFault'] = __obj[791.0] + __o['E_debugMon'] = __obj[792.0] + __o['E_exception'] = __obj[793.0] + __o['E_hardFault'] = __obj[794.0] + __o['E_hwiLimitExceeded'] = __obj[795.0] + __o['E_memFault'] = __obj[796.0] + __o['E_noIsr'] = __obj[797.0] + __o['E_reserved'] = __obj[798.0] + __o['E_svCall'] = __obj[799.0] + __o['E_usageFault'] = __obj[800.0] + __o['LD_end'] = __obj[801.0] + __o['LM_begin'] = __obj[802.0] + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32805 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['NUM_INTERRUPTS'] = 216 + __o['NUM_PRIORITIES'] = 8 + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['busFaultFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['ccr'] = 512 + __o['common$'] = __obj[803.0] + __o['configNameMap$'] = __obj[804.0] + __o['debugMonFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['disablePriority'] = 32 + __o['dispatchTableSize'] = 216 + __o['dispatcherAutoNestingSupport'] = true + __o['dispatcherIrpTrackingSupport'] = true + __o['dispatcherSwiSupport'] = true + __o['dispatcherTaskSupport'] = true + __o['enableException'] = true + __o['enableWA1_1'] = false + __o['excContextBuffer'] = 0 + __o['excContextBuffers'] = __obj[817.0] + __o['excHandlerFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerMax__I', 'UTF-8')) + __o['excHookFunc'] = null + __o['excHookFuncs'] = __obj[818.0] + __o['excStackBuffer'] = null + __o['excStackBuffers'] = __obj[819.0] + __o['hardFaultFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['hooks'] = __obj[820.0] + __o['intAffinity'] = __obj[821.0] + __o['interrupt'] = __obj[822.0] + __o['isTiva'] = true + __o['memFaultFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['nmiFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['nullIsrFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['numSparseInterrupts'] = 0 + __o['nvicCCR'] = __obj[1039.0] + __o['priGroup'] = 0 + __o['reservedFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['resetFunc'] = String(java.net.URLDecoder.decode('%26_c_int00', 'UTF-8')) + __o['resetVectorAddress'] = 0 + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[88.0] + __o['svCallFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['swiDisable'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Swi_disable__E', 'UTF-8')) + __o['swiRestoreHwi'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Swi_restoreHwi__E', 'UTF-8')) + __o['taskDisable'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Task_disable__E', 'UTF-8')) + __o['taskRestoreHwi'] = String(java.net.URLDecoder.decode('%26ti_sysbios_knl_Task_restoreHwi__E', 'UTF-8')) + __o['usageFaultFunc'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_m3_Hwi_excHandlerAsm__I', 'UTF-8')) + __o['vectorTableAddress'] = 536870912 + __o['viewNameMap$'] = __obj[1040.0] + +__o = __obj[785] // ti.sysbios.family.arm.m3.Hwi/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2F%24instances', 'UTF-8')) + __o['0'] = __obj[786.0] + +__o = __obj[786] // ti.sysbios.family.arm.m3.Hwi.Instance#0 + __o['$category'] = String(java.net.URLDecoder.decode('Instance', 'UTF-8')) + __o['$module'] = __obj[784.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi.Instance%230', 'UTF-8')) + __o['arg'] = __obj[561.0] + __o['enableInt'] = true + __o['eventId'] = -1 + __o['instance'] = __obj[787.0] + __o['maskSetting'] = String(java.net.URLDecoder.decode('ti.sysbios.interfaces.IHwi.MaskingOption_LOWER', 'UTF-8')) + __o['priority'] = 255 + __o['useDispatcher'] = true + +__o = __obj[787] // ti.sysbios.family.arm.m3.Hwi.Instance#0/instance + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi.Instance%230%2Finstance', 'UTF-8')) + __o['name'] = null + +__o = __obj[788] // xdc.runtime.Assert.Desc#37 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Assert.Desc%2337', 'UTF-8')) + __o['mask'] = 16 + __o['msg'] = String(java.net.URLDecoder.decode('A_unsupportedMaskingOption%3A+unsupported+maskSetting.', 'UTF-8')) + +__o = __obj[789] // xdc.runtime.Error.Desc#16 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2316', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_NMI%3A+%25s', 'UTF-8')) + +__o = __obj[790] // xdc.runtime.Error.Desc#12 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2312', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_alreadyDefined%3A+Hwi+already+defined%3A+intr%23+%25d', 'UTF-8')) + +__o = __obj[791] // xdc.runtime.Error.Desc#19 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2319', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_busFault%3A+%25s%2C+address%3A+%2508x', 'UTF-8')) + +__o = __obj[792] // xdc.runtime.Error.Desc#22 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2322', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_debugMon%3A+%25s', 'UTF-8')) + +__o = __obj[793] // xdc.runtime.Error.Desc#14 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2314', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_exception%3A+id+%3D+%25d%2C+pc+%3D+%2508x.%0ATo+see+more+exception+detail%2C+set+ti.sysbios.family.arm.m3.Hwi.enableException+%3D+true+or%2C%0Aexamine+the+Exception+view+for+the+ti.sysbios.family.arm.m3.Hwi+module+using+ROV.', 'UTF-8')) + +__o = __obj[794] // xdc.runtime.Error.Desc#17 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2317', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_hardFault%3A+%25s', 'UTF-8')) + +__o = __obj[795] // xdc.runtime.Error.Desc#13 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2313', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_hwiLimitExceeded%3A+Too+many+interrupts+defined', 'UTF-8')) + +__o = __obj[796] // xdc.runtime.Error.Desc#18 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2318', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_memFault%3A+%25s%2C+address%3A+%2508x', 'UTF-8')) + +__o = __obj[797] // xdc.runtime.Error.Desc#15 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2315', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_noIsr%3A+id+%3D+%25d%2C+pc+%3D+%2508x', 'UTF-8')) + +__o = __obj[798] // xdc.runtime.Error.Desc#23 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2323', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_reserved%3A+%25s+%25d', 'UTF-8')) + +__o = __obj[799] // xdc.runtime.Error.Desc#21 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2321', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_svCall%3A+svNum+%3D+%25d', 'UTF-8')) + +__o = __obj[800] // xdc.runtime.Error.Desc#20 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Error.Desc%2320', 'UTF-8')) + __o['code'] = 0 + __o['msg'] = String(java.net.URLDecoder.decode('E_usageFault%3A+%25s', 'UTF-8')) + +__o = __obj[801] // xdc.runtime.Log.EventDesc#34 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2334', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 512 + __o['msg'] = String(java.net.URLDecoder.decode('LD_end%3A+hwi%3A+0x%25x', 'UTF-8')) + +__o = __obj[802] // xdc.runtime.Log.EventDesc#33 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('xdc.runtime.Log.EventDesc%2333', 'UTF-8')) + __o['level'] = undefined + __o['mask'] = 768 + __o['msg'] = String(java.net.URLDecoder.decode('LM_begin%3A+hwi%3A+0x%25x%2C+func%3A+0x%25x%2C+preThread%3A+%25d%2C+intNum%3A+%25d%2C+irp%3A+0x%25x', 'UTF-8')) + +__o = __obj[803] // ti.sysbios.family.arm.m3.Hwi/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[804] // ti.sysbios.family.arm.m3.Hwi/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[805.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[807.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[809.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[811.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[813.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[815.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[805] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[806.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[806] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[807] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[808.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[808] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[809] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[810.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[810] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[811] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[812.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[812] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[813] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[814.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[814] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[815] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[816.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[816] // ti.sysbios.family.arm.m3.Hwi/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[817] // ti.sysbios.family.arm.m3.Hwi/excContextBuffers + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FexcContextBuffers', 'UTF-8')) + __o['0'] = 0 + __o['1'] = 0 + +__o = __obj[818] // ti.sysbios.family.arm.m3.Hwi/excHookFuncs + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FexcHookFuncs', 'UTF-8')) + __o['0'] = null + __o['1'] = null + +__o = __obj[819] // ti.sysbios.family.arm.m3.Hwi/excStackBuffers + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FexcStackBuffers', 'UTF-8')) + __o['0'] = null + __o['1'] = null + +__o = __obj[820] // ti.sysbios.family.arm.m3.Hwi/hooks + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Fhooks', 'UTF-8')) + +__o = __obj[821] // ti.sysbios.family.arm.m3.Hwi/intAffinity + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FintAffinity', 'UTF-8')) + __o['0'] = 0 + __o['1'] = 0 + __o['2'] = 0 + __o['3'] = 0 + __o['4'] = 0 + __o['5'] = 0 + __o['6'] = 0 + __o['7'] = 0 + __o['8'] = 0 + __o['9'] = 0 + __o['10'] = 0 + __o['11'] = 0 + __o['12'] = 0 + __o['13'] = 0 + __o['14'] = 0 + __o['15'] = 0 + __o['16'] = 0 + __o['17'] = 0 + __o['18'] = 0 + __o['19'] = 0 + __o['20'] = 0 + __o['21'] = 0 + __o['22'] = 0 + __o['23'] = 0 + __o['24'] = 0 + __o['25'] = 0 + __o['26'] = 0 + __o['27'] = 0 + __o['28'] = 0 + __o['29'] = 0 + __o['30'] = 0 + __o['31'] = 0 + __o['32'] = 0 + __o['33'] = 0 + __o['34'] = 0 + __o['35'] = 0 + __o['36'] = 0 + __o['37'] = 0 + __o['38'] = 0 + __o['39'] = 0 + __o['40'] = 0 + __o['41'] = 0 + __o['42'] = 0 + __o['43'] = 0 + __o['44'] = 0 + __o['45'] = 0 + __o['46'] = 0 + __o['47'] = 0 + __o['48'] = 0 + __o['49'] = 0 + __o['50'] = 0 + __o['51'] = 0 + __o['52'] = 0 + __o['53'] = 0 + __o['54'] = 0 + __o['55'] = 0 + __o['56'] = 0 + __o['57'] = 0 + __o['58'] = 0 + __o['59'] = 0 + __o['60'] = 0 + __o['61'] = 0 + __o['62'] = 0 + __o['63'] = 0 + __o['64'] = 0 + __o['65'] = 0 + __o['66'] = 0 + __o['67'] = 0 + __o['68'] = 0 + __o['69'] = 0 + __o['70'] = 0 + __o['71'] = 0 + __o['72'] = 0 + __o['73'] = 0 + __o['74'] = 0 + __o['75'] = 0 + __o['76'] = 0 + __o['77'] = 0 + __o['78'] = 0 + __o['79'] = 0 + __o['80'] = 0 + __o['81'] = 0 + __o['82'] = 0 + __o['83'] = 0 + __o['84'] = 0 + __o['85'] = 0 + __o['86'] = 0 + __o['87'] = 0 + __o['88'] = 0 + __o['89'] = 0 + __o['90'] = 0 + __o['91'] = 0 + __o['92'] = 0 + __o['93'] = 0 + __o['94'] = 0 + __o['95'] = 0 + __o['96'] = 0 + __o['97'] = 0 + __o['98'] = 0 + __o['99'] = 0 + __o['100'] = 0 + __o['101'] = 0 + __o['102'] = 0 + __o['103'] = 0 + __o['104'] = 0 + __o['105'] = 0 + __o['106'] = 0 + __o['107'] = 0 + __o['108'] = 0 + __o['109'] = 0 + __o['110'] = 0 + __o['111'] = 0 + __o['112'] = 0 + __o['113'] = 0 + __o['114'] = 0 + __o['115'] = 0 + __o['116'] = 0 + __o['117'] = 0 + __o['118'] = 0 + __o['119'] = 0 + __o['120'] = 0 + __o['121'] = 0 + __o['122'] = 0 + __o['123'] = 0 + __o['124'] = 0 + __o['125'] = 0 + __o['126'] = 0 + __o['127'] = 0 + __o['128'] = 0 + __o['129'] = 0 + __o['130'] = 0 + __o['131'] = 0 + __o['132'] = 0 + __o['133'] = 0 + __o['134'] = 0 + __o['135'] = 0 + __o['136'] = 0 + __o['137'] = 0 + __o['138'] = 0 + __o['139'] = 0 + __o['140'] = 0 + __o['141'] = 0 + __o['142'] = 0 + __o['143'] = 0 + __o['144'] = 0 + __o['145'] = 0 + __o['146'] = 0 + __o['147'] = 0 + __o['148'] = 0 + __o['149'] = 0 + __o['150'] = 0 + __o['151'] = 0 + __o['152'] = 0 + __o['153'] = 0 + __o['154'] = 0 + __o['155'] = 0 + __o['156'] = 0 + __o['157'] = 0 + __o['158'] = 0 + __o['159'] = 0 + __o['160'] = 0 + __o['161'] = 0 + __o['162'] = 0 + __o['163'] = 0 + __o['164'] = 0 + __o['165'] = 0 + __o['166'] = 0 + __o['167'] = 0 + __o['168'] = 0 + __o['169'] = 0 + __o['170'] = 0 + __o['171'] = 0 + __o['172'] = 0 + __o['173'] = 0 + __o['174'] = 0 + __o['175'] = 0 + __o['176'] = 0 + __o['177'] = 0 + __o['178'] = 0 + __o['179'] = 0 + __o['180'] = 0 + __o['181'] = 0 + __o['182'] = 0 + __o['183'] = 0 + __o['184'] = 0 + __o['185'] = 0 + __o['186'] = 0 + __o['187'] = 0 + __o['188'] = 0 + __o['189'] = 0 + __o['190'] = 0 + __o['191'] = 0 + __o['192'] = 0 + __o['193'] = 0 + __o['194'] = 0 + __o['195'] = 0 + __o['196'] = 0 + __o['197'] = 0 + __o['198'] = 0 + __o['199'] = 0 + __o['200'] = 0 + __o['201'] = 0 + __o['202'] = 0 + __o['203'] = 0 + __o['204'] = 0 + __o['205'] = 0 + __o['206'] = 0 + __o['207'] = 0 + __o['208'] = 0 + __o['209'] = 0 + __o['210'] = 0 + __o['211'] = 0 + __o['212'] = 0 + __o['213'] = 0 + __o['214'] = 0 + __o['215'] = 0 + __o['216'] = 0 + __o['217'] = 0 + __o['218'] = 0 + __o['219'] = 0 + __o['220'] = 0 + __o['221'] = 0 + __o['222'] = 0 + __o['223'] = 0 + __o['224'] = 0 + __o['225'] = 0 + __o['226'] = 0 + __o['227'] = 0 + __o['228'] = 0 + __o['229'] = 0 + __o['230'] = 0 + __o['231'] = 0 + __o['232'] = 0 + __o['233'] = 0 + __o['234'] = 0 + __o['235'] = 0 + __o['236'] = 0 + __o['237'] = 0 + __o['238'] = 0 + __o['239'] = 0 + __o['240'] = 0 + __o['241'] = 0 + __o['242'] = 0 + __o['243'] = 0 + __o['244'] = 0 + __o['245'] = 0 + __o['246'] = 0 + __o['247'] = 0 + __o['248'] = 0 + __o['249'] = 0 + __o['250'] = 0 + __o['251'] = 0 + __o['252'] = 0 + __o['253'] = 0 + __o['254'] = 0 + __o['255'] = 0 + +__o = __obj[822] // ti.sysbios.family.arm.m3.Hwi/interrupt + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt', 'UTF-8')) + __o['0'] = __obj[823.0] + __o['1'] = __obj[824.0] + __o['2'] = __obj[825.0] + __o['3'] = __obj[826.0] + __o['4'] = __obj[827.0] + __o['5'] = __obj[828.0] + __o['6'] = __obj[829.0] + __o['7'] = __obj[830.0] + __o['8'] = __obj[831.0] + __o['9'] = __obj[832.0] + __o['10'] = __obj[833.0] + __o['11'] = __obj[834.0] + __o['12'] = __obj[835.0] + __o['13'] = __obj[836.0] + __o['14'] = __obj[837.0] + __o['15'] = __obj[838.0] + __o['16'] = __obj[839.0] + __o['17'] = __obj[840.0] + __o['18'] = __obj[841.0] + __o['19'] = __obj[842.0] + __o['20'] = __obj[843.0] + __o['21'] = __obj[844.0] + __o['22'] = __obj[845.0] + __o['23'] = __obj[846.0] + __o['24'] = __obj[847.0] + __o['25'] = __obj[848.0] + __o['26'] = __obj[849.0] + __o['27'] = __obj[850.0] + __o['28'] = __obj[851.0] + __o['29'] = __obj[852.0] + __o['30'] = __obj[853.0] + __o['31'] = __obj[854.0] + __o['32'] = __obj[855.0] + __o['33'] = __obj[856.0] + __o['34'] = __obj[857.0] + __o['35'] = __obj[858.0] + __o['36'] = __obj[859.0] + __o['37'] = __obj[860.0] + __o['38'] = __obj[861.0] + __o['39'] = __obj[862.0] + __o['40'] = __obj[863.0] + __o['41'] = __obj[864.0] + __o['42'] = __obj[865.0] + __o['43'] = __obj[866.0] + __o['44'] = __obj[867.0] + __o['45'] = __obj[868.0] + __o['46'] = __obj[869.0] + __o['47'] = __obj[870.0] + __o['48'] = __obj[871.0] + __o['49'] = __obj[872.0] + __o['50'] = __obj[873.0] + __o['51'] = __obj[874.0] + __o['52'] = __obj[875.0] + __o['53'] = __obj[876.0] + __o['54'] = __obj[877.0] + __o['55'] = __obj[878.0] + __o['56'] = __obj[879.0] + __o['57'] = __obj[880.0] + __o['58'] = __obj[881.0] + __o['59'] = __obj[882.0] + __o['60'] = __obj[883.0] + __o['61'] = __obj[884.0] + __o['62'] = __obj[885.0] + __o['63'] = __obj[886.0] + __o['64'] = __obj[887.0] + __o['65'] = __obj[888.0] + __o['66'] = __obj[889.0] + __o['67'] = __obj[890.0] + __o['68'] = __obj[891.0] + __o['69'] = __obj[892.0] + __o['70'] = __obj[893.0] + __o['71'] = __obj[894.0] + __o['72'] = __obj[895.0] + __o['73'] = __obj[896.0] + __o['74'] = __obj[897.0] + __o['75'] = __obj[898.0] + __o['76'] = __obj[899.0] + __o['77'] = __obj[900.0] + __o['78'] = __obj[901.0] + __o['79'] = __obj[902.0] + __o['80'] = __obj[903.0] + __o['81'] = __obj[904.0] + __o['82'] = __obj[905.0] + __o['83'] = __obj[906.0] + __o['84'] = __obj[907.0] + __o['85'] = __obj[908.0] + __o['86'] = __obj[909.0] + __o['87'] = __obj[910.0] + __o['88'] = __obj[911.0] + __o['89'] = __obj[912.0] + __o['90'] = __obj[913.0] + __o['91'] = __obj[914.0] + __o['92'] = __obj[915.0] + __o['93'] = __obj[916.0] + __o['94'] = __obj[917.0] + __o['95'] = __obj[918.0] + __o['96'] = __obj[919.0] + __o['97'] = __obj[920.0] + __o['98'] = __obj[921.0] + __o['99'] = __obj[922.0] + __o['100'] = __obj[923.0] + __o['101'] = __obj[924.0] + __o['102'] = __obj[925.0] + __o['103'] = __obj[926.0] + __o['104'] = __obj[927.0] + __o['105'] = __obj[928.0] + __o['106'] = __obj[929.0] + __o['107'] = __obj[930.0] + __o['108'] = __obj[931.0] + __o['109'] = __obj[932.0] + __o['110'] = __obj[933.0] + __o['111'] = __obj[934.0] + __o['112'] = __obj[935.0] + __o['113'] = __obj[936.0] + __o['114'] = __obj[937.0] + __o['115'] = __obj[938.0] + __o['116'] = __obj[939.0] + __o['117'] = __obj[940.0] + __o['118'] = __obj[941.0] + __o['119'] = __obj[942.0] + __o['120'] = __obj[943.0] + __o['121'] = __obj[944.0] + __o['122'] = __obj[945.0] + __o['123'] = __obj[946.0] + __o['124'] = __obj[947.0] + __o['125'] = __obj[948.0] + __o['126'] = __obj[949.0] + __o['127'] = __obj[950.0] + __o['128'] = __obj[951.0] + __o['129'] = __obj[952.0] + __o['130'] = __obj[953.0] + __o['131'] = __obj[954.0] + __o['132'] = __obj[955.0] + __o['133'] = __obj[956.0] + __o['134'] = __obj[957.0] + __o['135'] = __obj[958.0] + __o['136'] = __obj[959.0] + __o['137'] = __obj[960.0] + __o['138'] = __obj[961.0] + __o['139'] = __obj[962.0] + __o['140'] = __obj[963.0] + __o['141'] = __obj[964.0] + __o['142'] = __obj[965.0] + __o['143'] = __obj[966.0] + __o['144'] = __obj[967.0] + __o['145'] = __obj[968.0] + __o['146'] = __obj[969.0] + __o['147'] = __obj[970.0] + __o['148'] = __obj[971.0] + __o['149'] = __obj[972.0] + __o['150'] = __obj[973.0] + __o['151'] = __obj[974.0] + __o['152'] = __obj[975.0] + __o['153'] = __obj[976.0] + __o['154'] = __obj[977.0] + __o['155'] = __obj[978.0] + __o['156'] = __obj[979.0] + __o['157'] = __obj[980.0] + __o['158'] = __obj[981.0] + __o['159'] = __obj[982.0] + __o['160'] = __obj[983.0] + __o['161'] = __obj[984.0] + __o['162'] = __obj[985.0] + __o['163'] = __obj[986.0] + __o['164'] = __obj[987.0] + __o['165'] = __obj[988.0] + __o['166'] = __obj[989.0] + __o['167'] = __obj[990.0] + __o['168'] = __obj[991.0] + __o['169'] = __obj[992.0] + __o['170'] = __obj[993.0] + __o['171'] = __obj[994.0] + __o['172'] = __obj[995.0] + __o['173'] = __obj[996.0] + __o['174'] = __obj[997.0] + __o['175'] = __obj[998.0] + __o['176'] = __obj[999.0] + __o['177'] = __obj[1000.0] + __o['178'] = __obj[1001.0] + __o['179'] = __obj[1002.0] + __o['180'] = __obj[1003.0] + __o['181'] = __obj[1004.0] + __o['182'] = __obj[1005.0] + __o['183'] = __obj[1006.0] + __o['184'] = __obj[1007.0] + __o['185'] = __obj[1008.0] + __o['186'] = __obj[1009.0] + __o['187'] = __obj[1010.0] + __o['188'] = __obj[1011.0] + __o['189'] = __obj[1012.0] + __o['190'] = __obj[1013.0] + __o['191'] = __obj[1014.0] + __o['192'] = __obj[1015.0] + __o['193'] = __obj[1016.0] + __o['194'] = __obj[1017.0] + __o['195'] = __obj[1018.0] + __o['196'] = __obj[1019.0] + __o['197'] = __obj[1020.0] + __o['198'] = __obj[1021.0] + __o['199'] = __obj[1022.0] + __o['200'] = __obj[1023.0] + __o['201'] = __obj[1024.0] + __o['202'] = __obj[1025.0] + __o['203'] = __obj[1026.0] + __o['204'] = __obj[1027.0] + __o['205'] = __obj[1028.0] + __o['206'] = __obj[1029.0] + __o['207'] = __obj[1030.0] + __o['208'] = __obj[1031.0] + __o['209'] = __obj[1032.0] + __o['210'] = __obj[1033.0] + __o['211'] = __obj[1034.0] + __o['212'] = __obj[1035.0] + __o['213'] = __obj[1036.0] + __o['214'] = __obj[1037.0] + __o['215'] = __obj[1038.0] + +__o = __obj[823] // ti.sysbios.family.arm.m3.Hwi/interrupt/0 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F0', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[824] // ti.sysbios.family.arm.m3.Hwi/interrupt/1 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F1', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[825] // ti.sysbios.family.arm.m3.Hwi/interrupt/2 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F2', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[826] // ti.sysbios.family.arm.m3.Hwi/interrupt/3 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F3', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[827] // ti.sysbios.family.arm.m3.Hwi/interrupt/4 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F4', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[828] // ti.sysbios.family.arm.m3.Hwi/interrupt/5 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F5', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[829] // ti.sysbios.family.arm.m3.Hwi/interrupt/6 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F6', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[830] // ti.sysbios.family.arm.m3.Hwi/interrupt/7 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F7', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[831] // ti.sysbios.family.arm.m3.Hwi/interrupt/8 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F8', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[832] // ti.sysbios.family.arm.m3.Hwi/interrupt/9 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F9', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[833] // ti.sysbios.family.arm.m3.Hwi/interrupt/10 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F10', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[834] // ti.sysbios.family.arm.m3.Hwi/interrupt/11 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F11', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[835] // ti.sysbios.family.arm.m3.Hwi/interrupt/12 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F12', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[836] // ti.sysbios.family.arm.m3.Hwi/interrupt/13 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F13', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[837] // ti.sysbios.family.arm.m3.Hwi/interrupt/14 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F14', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[838] // ti.sysbios.family.arm.m3.Hwi/interrupt/15 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F15', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[839] // ti.sysbios.family.arm.m3.Hwi/interrupt/16 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F16', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[840] // ti.sysbios.family.arm.m3.Hwi/interrupt/17 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F17', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[841] // ti.sysbios.family.arm.m3.Hwi/interrupt/18 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F18', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[842] // ti.sysbios.family.arm.m3.Hwi/interrupt/19 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F19', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[843] // ti.sysbios.family.arm.m3.Hwi/interrupt/20 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F20', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[844] // ti.sysbios.family.arm.m3.Hwi/interrupt/21 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F21', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[845] // ti.sysbios.family.arm.m3.Hwi/interrupt/22 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F22', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[846] // ti.sysbios.family.arm.m3.Hwi/interrupt/23 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F23', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[847] // ti.sysbios.family.arm.m3.Hwi/interrupt/24 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F24', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[848] // ti.sysbios.family.arm.m3.Hwi/interrupt/25 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F25', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[849] // ti.sysbios.family.arm.m3.Hwi/interrupt/26 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F26', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[850] // ti.sysbios.family.arm.m3.Hwi/interrupt/27 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F27', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[851] // ti.sysbios.family.arm.m3.Hwi/interrupt/28 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F28', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[852] // ti.sysbios.family.arm.m3.Hwi/interrupt/29 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F29', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[853] // ti.sysbios.family.arm.m3.Hwi/interrupt/30 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F30', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[854] // ti.sysbios.family.arm.m3.Hwi/interrupt/31 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F31', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[855] // ti.sysbios.family.arm.m3.Hwi/interrupt/32 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F32', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[856] // ti.sysbios.family.arm.m3.Hwi/interrupt/33 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F33', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[857] // ti.sysbios.family.arm.m3.Hwi/interrupt/34 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F34', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[858] // ti.sysbios.family.arm.m3.Hwi/interrupt/35 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F35', 'UTF-8')) + __o['fxn'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_lm4_Timer_isrStub__E', 'UTF-8')) + __o['hwi'] = __obj[786.0] + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = 255 + __o['useDispatcher'] = true + __o['used'] = true + +__o = __obj[859] // ti.sysbios.family.arm.m3.Hwi/interrupt/36 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F36', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[860] // ti.sysbios.family.arm.m3.Hwi/interrupt/37 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F37', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[861] // ti.sysbios.family.arm.m3.Hwi/interrupt/38 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F38', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[862] // ti.sysbios.family.arm.m3.Hwi/interrupt/39 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F39', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[863] // ti.sysbios.family.arm.m3.Hwi/interrupt/40 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F40', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[864] // ti.sysbios.family.arm.m3.Hwi/interrupt/41 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F41', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[865] // ti.sysbios.family.arm.m3.Hwi/interrupt/42 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F42', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[866] // ti.sysbios.family.arm.m3.Hwi/interrupt/43 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F43', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[867] // ti.sysbios.family.arm.m3.Hwi/interrupt/44 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F44', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[868] // ti.sysbios.family.arm.m3.Hwi/interrupt/45 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F45', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[869] // ti.sysbios.family.arm.m3.Hwi/interrupt/46 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F46', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[870] // ti.sysbios.family.arm.m3.Hwi/interrupt/47 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F47', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[871] // ti.sysbios.family.arm.m3.Hwi/interrupt/48 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F48', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[872] // ti.sysbios.family.arm.m3.Hwi/interrupt/49 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F49', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[873] // ti.sysbios.family.arm.m3.Hwi/interrupt/50 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F50', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[874] // ti.sysbios.family.arm.m3.Hwi/interrupt/51 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F51', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[875] // ti.sysbios.family.arm.m3.Hwi/interrupt/52 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F52', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[876] // ti.sysbios.family.arm.m3.Hwi/interrupt/53 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F53', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[877] // ti.sysbios.family.arm.m3.Hwi/interrupt/54 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F54', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[878] // ti.sysbios.family.arm.m3.Hwi/interrupt/55 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F55', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[879] // ti.sysbios.family.arm.m3.Hwi/interrupt/56 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F56', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[880] // ti.sysbios.family.arm.m3.Hwi/interrupt/57 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F57', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[881] // ti.sysbios.family.arm.m3.Hwi/interrupt/58 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F58', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[882] // ti.sysbios.family.arm.m3.Hwi/interrupt/59 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F59', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[883] // ti.sysbios.family.arm.m3.Hwi/interrupt/60 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F60', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[884] // ti.sysbios.family.arm.m3.Hwi/interrupt/61 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F61', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[885] // ti.sysbios.family.arm.m3.Hwi/interrupt/62 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F62', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[886] // ti.sysbios.family.arm.m3.Hwi/interrupt/63 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F63', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[887] // ti.sysbios.family.arm.m3.Hwi/interrupt/64 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F64', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[888] // ti.sysbios.family.arm.m3.Hwi/interrupt/65 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F65', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[889] // ti.sysbios.family.arm.m3.Hwi/interrupt/66 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F66', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[890] // ti.sysbios.family.arm.m3.Hwi/interrupt/67 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F67', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[891] // ti.sysbios.family.arm.m3.Hwi/interrupt/68 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F68', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[892] // ti.sysbios.family.arm.m3.Hwi/interrupt/69 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F69', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[893] // ti.sysbios.family.arm.m3.Hwi/interrupt/70 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F70', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[894] // ti.sysbios.family.arm.m3.Hwi/interrupt/71 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F71', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[895] // ti.sysbios.family.arm.m3.Hwi/interrupt/72 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F72', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[896] // ti.sysbios.family.arm.m3.Hwi/interrupt/73 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F73', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[897] // ti.sysbios.family.arm.m3.Hwi/interrupt/74 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F74', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[898] // ti.sysbios.family.arm.m3.Hwi/interrupt/75 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F75', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[899] // ti.sysbios.family.arm.m3.Hwi/interrupt/76 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F76', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[900] // ti.sysbios.family.arm.m3.Hwi/interrupt/77 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F77', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[901] // ti.sysbios.family.arm.m3.Hwi/interrupt/78 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F78', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[902] // ti.sysbios.family.arm.m3.Hwi/interrupt/79 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F79', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[903] // ti.sysbios.family.arm.m3.Hwi/interrupt/80 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F80', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[904] // ti.sysbios.family.arm.m3.Hwi/interrupt/81 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F81', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[905] // ti.sysbios.family.arm.m3.Hwi/interrupt/82 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F82', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[906] // ti.sysbios.family.arm.m3.Hwi/interrupt/83 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F83', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[907] // ti.sysbios.family.arm.m3.Hwi/interrupt/84 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F84', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[908] // ti.sysbios.family.arm.m3.Hwi/interrupt/85 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F85', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[909] // ti.sysbios.family.arm.m3.Hwi/interrupt/86 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F86', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[910] // ti.sysbios.family.arm.m3.Hwi/interrupt/87 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F87', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[911] // ti.sysbios.family.arm.m3.Hwi/interrupt/88 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F88', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[912] // ti.sysbios.family.arm.m3.Hwi/interrupt/89 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F89', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[913] // ti.sysbios.family.arm.m3.Hwi/interrupt/90 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F90', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[914] // ti.sysbios.family.arm.m3.Hwi/interrupt/91 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F91', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[915] // ti.sysbios.family.arm.m3.Hwi/interrupt/92 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F92', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[916] // ti.sysbios.family.arm.m3.Hwi/interrupt/93 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F93', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[917] // ti.sysbios.family.arm.m3.Hwi/interrupt/94 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F94', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[918] // ti.sysbios.family.arm.m3.Hwi/interrupt/95 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F95', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[919] // ti.sysbios.family.arm.m3.Hwi/interrupt/96 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F96', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[920] // ti.sysbios.family.arm.m3.Hwi/interrupt/97 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F97', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[921] // ti.sysbios.family.arm.m3.Hwi/interrupt/98 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F98', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[922] // ti.sysbios.family.arm.m3.Hwi/interrupt/99 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F99', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[923] // ti.sysbios.family.arm.m3.Hwi/interrupt/100 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F100', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[924] // ti.sysbios.family.arm.m3.Hwi/interrupt/101 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F101', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[925] // ti.sysbios.family.arm.m3.Hwi/interrupt/102 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F102', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[926] // ti.sysbios.family.arm.m3.Hwi/interrupt/103 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F103', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[927] // ti.sysbios.family.arm.m3.Hwi/interrupt/104 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F104', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[928] // ti.sysbios.family.arm.m3.Hwi/interrupt/105 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F105', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[929] // ti.sysbios.family.arm.m3.Hwi/interrupt/106 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F106', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[930] // ti.sysbios.family.arm.m3.Hwi/interrupt/107 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F107', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[931] // ti.sysbios.family.arm.m3.Hwi/interrupt/108 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F108', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[932] // ti.sysbios.family.arm.m3.Hwi/interrupt/109 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F109', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[933] // ti.sysbios.family.arm.m3.Hwi/interrupt/110 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F110', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[934] // ti.sysbios.family.arm.m3.Hwi/interrupt/111 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F111', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[935] // ti.sysbios.family.arm.m3.Hwi/interrupt/112 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F112', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[936] // ti.sysbios.family.arm.m3.Hwi/interrupt/113 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F113', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[937] // ti.sysbios.family.arm.m3.Hwi/interrupt/114 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F114', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[938] // ti.sysbios.family.arm.m3.Hwi/interrupt/115 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F115', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[939] // ti.sysbios.family.arm.m3.Hwi/interrupt/116 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F116', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[940] // ti.sysbios.family.arm.m3.Hwi/interrupt/117 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F117', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[941] // ti.sysbios.family.arm.m3.Hwi/interrupt/118 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F118', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[942] // ti.sysbios.family.arm.m3.Hwi/interrupt/119 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F119', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[943] // ti.sysbios.family.arm.m3.Hwi/interrupt/120 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F120', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[944] // ti.sysbios.family.arm.m3.Hwi/interrupt/121 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F121', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[945] // ti.sysbios.family.arm.m3.Hwi/interrupt/122 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F122', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[946] // ti.sysbios.family.arm.m3.Hwi/interrupt/123 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F123', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[947] // ti.sysbios.family.arm.m3.Hwi/interrupt/124 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F124', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[948] // ti.sysbios.family.arm.m3.Hwi/interrupt/125 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F125', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[949] // ti.sysbios.family.arm.m3.Hwi/interrupt/126 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F126', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[950] // ti.sysbios.family.arm.m3.Hwi/interrupt/127 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F127', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[951] // ti.sysbios.family.arm.m3.Hwi/interrupt/128 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F128', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[952] // ti.sysbios.family.arm.m3.Hwi/interrupt/129 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F129', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[953] // ti.sysbios.family.arm.m3.Hwi/interrupt/130 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F130', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[954] // ti.sysbios.family.arm.m3.Hwi/interrupt/131 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F131', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[955] // ti.sysbios.family.arm.m3.Hwi/interrupt/132 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F132', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[956] // ti.sysbios.family.arm.m3.Hwi/interrupt/133 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F133', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[957] // ti.sysbios.family.arm.m3.Hwi/interrupt/134 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F134', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[958] // ti.sysbios.family.arm.m3.Hwi/interrupt/135 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F135', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[959] // ti.sysbios.family.arm.m3.Hwi/interrupt/136 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F136', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[960] // ti.sysbios.family.arm.m3.Hwi/interrupt/137 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F137', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[961] // ti.sysbios.family.arm.m3.Hwi/interrupt/138 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F138', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[962] // ti.sysbios.family.arm.m3.Hwi/interrupt/139 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F139', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[963] // ti.sysbios.family.arm.m3.Hwi/interrupt/140 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F140', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[964] // ti.sysbios.family.arm.m3.Hwi/interrupt/141 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F141', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[965] // ti.sysbios.family.arm.m3.Hwi/interrupt/142 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F142', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[966] // ti.sysbios.family.arm.m3.Hwi/interrupt/143 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F143', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[967] // ti.sysbios.family.arm.m3.Hwi/interrupt/144 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F144', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[968] // ti.sysbios.family.arm.m3.Hwi/interrupt/145 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F145', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[969] // ti.sysbios.family.arm.m3.Hwi/interrupt/146 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F146', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[970] // ti.sysbios.family.arm.m3.Hwi/interrupt/147 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F147', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[971] // ti.sysbios.family.arm.m3.Hwi/interrupt/148 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F148', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[972] // ti.sysbios.family.arm.m3.Hwi/interrupt/149 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F149', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[973] // ti.sysbios.family.arm.m3.Hwi/interrupt/150 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F150', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[974] // ti.sysbios.family.arm.m3.Hwi/interrupt/151 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F151', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[975] // ti.sysbios.family.arm.m3.Hwi/interrupt/152 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F152', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[976] // ti.sysbios.family.arm.m3.Hwi/interrupt/153 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F153', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[977] // ti.sysbios.family.arm.m3.Hwi/interrupt/154 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F154', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[978] // ti.sysbios.family.arm.m3.Hwi/interrupt/155 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F155', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[979] // ti.sysbios.family.arm.m3.Hwi/interrupt/156 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F156', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[980] // ti.sysbios.family.arm.m3.Hwi/interrupt/157 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F157', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[981] // ti.sysbios.family.arm.m3.Hwi/interrupt/158 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F158', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[982] // ti.sysbios.family.arm.m3.Hwi/interrupt/159 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F159', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[983] // ti.sysbios.family.arm.m3.Hwi/interrupt/160 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F160', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[984] // ti.sysbios.family.arm.m3.Hwi/interrupt/161 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F161', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[985] // ti.sysbios.family.arm.m3.Hwi/interrupt/162 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F162', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[986] // ti.sysbios.family.arm.m3.Hwi/interrupt/163 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F163', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[987] // ti.sysbios.family.arm.m3.Hwi/interrupt/164 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F164', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[988] // ti.sysbios.family.arm.m3.Hwi/interrupt/165 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F165', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[989] // ti.sysbios.family.arm.m3.Hwi/interrupt/166 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F166', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[990] // ti.sysbios.family.arm.m3.Hwi/interrupt/167 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F167', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[991] // ti.sysbios.family.arm.m3.Hwi/interrupt/168 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F168', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[992] // ti.sysbios.family.arm.m3.Hwi/interrupt/169 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F169', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[993] // ti.sysbios.family.arm.m3.Hwi/interrupt/170 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F170', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[994] // ti.sysbios.family.arm.m3.Hwi/interrupt/171 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F171', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[995] // ti.sysbios.family.arm.m3.Hwi/interrupt/172 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F172', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[996] // ti.sysbios.family.arm.m3.Hwi/interrupt/173 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F173', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[997] // ti.sysbios.family.arm.m3.Hwi/interrupt/174 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F174', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[998] // ti.sysbios.family.arm.m3.Hwi/interrupt/175 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F175', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[999] // ti.sysbios.family.arm.m3.Hwi/interrupt/176 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F176', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1000] // ti.sysbios.family.arm.m3.Hwi/interrupt/177 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F177', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1001] // ti.sysbios.family.arm.m3.Hwi/interrupt/178 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F178', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1002] // ti.sysbios.family.arm.m3.Hwi/interrupt/179 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F179', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1003] // ti.sysbios.family.arm.m3.Hwi/interrupt/180 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F180', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1004] // ti.sysbios.family.arm.m3.Hwi/interrupt/181 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F181', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1005] // ti.sysbios.family.arm.m3.Hwi/interrupt/182 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F182', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1006] // ti.sysbios.family.arm.m3.Hwi/interrupt/183 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F183', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1007] // ti.sysbios.family.arm.m3.Hwi/interrupt/184 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F184', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1008] // ti.sysbios.family.arm.m3.Hwi/interrupt/185 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F185', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1009] // ti.sysbios.family.arm.m3.Hwi/interrupt/186 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F186', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1010] // ti.sysbios.family.arm.m3.Hwi/interrupt/187 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F187', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1011] // ti.sysbios.family.arm.m3.Hwi/interrupt/188 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F188', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1012] // ti.sysbios.family.arm.m3.Hwi/interrupt/189 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F189', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1013] // ti.sysbios.family.arm.m3.Hwi/interrupt/190 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F190', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1014] // ti.sysbios.family.arm.m3.Hwi/interrupt/191 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F191', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1015] // ti.sysbios.family.arm.m3.Hwi/interrupt/192 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F192', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1016] // ti.sysbios.family.arm.m3.Hwi/interrupt/193 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F193', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1017] // ti.sysbios.family.arm.m3.Hwi/interrupt/194 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F194', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1018] // ti.sysbios.family.arm.m3.Hwi/interrupt/195 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F195', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1019] // ti.sysbios.family.arm.m3.Hwi/interrupt/196 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F196', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1020] // ti.sysbios.family.arm.m3.Hwi/interrupt/197 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F197', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1021] // ti.sysbios.family.arm.m3.Hwi/interrupt/198 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F198', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1022] // ti.sysbios.family.arm.m3.Hwi/interrupt/199 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F199', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1023] // ti.sysbios.family.arm.m3.Hwi/interrupt/200 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F200', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1024] // ti.sysbios.family.arm.m3.Hwi/interrupt/201 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F201', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1025] // ti.sysbios.family.arm.m3.Hwi/interrupt/202 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F202', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1026] // ti.sysbios.family.arm.m3.Hwi/interrupt/203 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F203', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1027] // ti.sysbios.family.arm.m3.Hwi/interrupt/204 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F204', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1028] // ti.sysbios.family.arm.m3.Hwi/interrupt/205 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F205', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1029] // ti.sysbios.family.arm.m3.Hwi/interrupt/206 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F206', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1030] // ti.sysbios.family.arm.m3.Hwi/interrupt/207 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F207', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1031] // ti.sysbios.family.arm.m3.Hwi/interrupt/208 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F208', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1032] // ti.sysbios.family.arm.m3.Hwi/interrupt/209 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F209', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1033] // ti.sysbios.family.arm.m3.Hwi/interrupt/210 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F210', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1034] // ti.sysbios.family.arm.m3.Hwi/interrupt/211 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F211', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1035] // ti.sysbios.family.arm.m3.Hwi/interrupt/212 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F212', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1036] // ti.sysbios.family.arm.m3.Hwi/interrupt/213 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F213', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1037] // ti.sysbios.family.arm.m3.Hwi/interrupt/214 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F214', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1038] // ti.sysbios.family.arm.m3.Hwi/interrupt/215 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2Finterrupt%2F215', 'UTF-8')) + __o['fxn'] = null + __o['hwi'] = undefined + __o['name'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['priority'] = undefined + __o['useDispatcher'] = false + __o['used'] = false + +__o = __obj[1039] // ti.sysbios.family.arm.m3.Hwi/nvicCCR + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FnvicCCR', 'UTF-8')) + __o['BFHFNMIGN'] = 0 + __o['DIV_0_TRP'] = 0 + __o['NONEBASETHRDENA'] = 0 + __o['STKALIGN'] = 1 + __o['UNALIGN_TRP'] = 0 + __o['USERSETMPEND'] = 0 + +__o = __obj[1040] // ti.sysbios.family.arm.m3.Hwi/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.family.arm.m3.Hwi%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[1041] // ti.sysbios.hal.Hwi/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = false + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[1042] // ti.sysbios.hal.Hwi/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[1043.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[1045.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[1047.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[1049.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[1051.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[1053.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[1043] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[1044.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[1044] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[1045] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[1046.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[1046] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[1047] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[1048.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[1048] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[1049] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[1050.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[1050] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[1051] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[1052.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[1052] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[1053] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[1054.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[1054] // ti.sysbios.hal.Hwi/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[1055] // ti.sysbios.hal.Hwi/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.hal.Hwi%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[1056] // ti.sysbios.BIOS + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[1057.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS', 'UTF-8')) + __o['Module__diagsEnabled'] = 144 + __o['Module__diagsIncluded'] = 144 + __o['Module__diagsMask'] = null + __o['Module__gateObj'] = null + __o['Module__gatePrms'] = null + __o['Module__id'] = 32801 + __o['Module__loggerDefined'] = false + __o['Module__loggerFxn0'] = null + __o['Module__loggerFxn1'] = null + __o['Module__loggerFxn2'] = null + __o['Module__loggerFxn4'] = null + __o['Module__loggerFxn8'] = null + __o['Module__loggerObj'] = null + __o['Module__startupDoneFxn'] = null + __o['NO_WAIT'] = 0 + __o['Object__count'] = 0 + __o['Object__heap'] = null + __o['Object__sizeof'] = 0 + __o['Object__table'] = null + __o['RtsGateProxy'] = __obj[341.0] + __o['WAIT_FOREVER'] = -1 + __o['assertsEnabled'] = false + __o['bitsPerInt'] = 32 + __o['buildingAppLib'] = true + __o['clockEnabled'] = true + __o['common$'] = __obj[1058.0] + __o['configNameMap$'] = __obj[1059.0] + __o['cpuFreq'] = __obj[1072.0] + __o['customCCOpts'] = String(java.net.URLDecoder.decode('--endian%3Dlittle+-mv7M4+--abi%3Deabi+--float_support%3Dfpv4spd16+-q+-ms+--opt_for_speed%3D2++--program_level_compile+-o3+-g+--optimize_with_debug+', 'UTF-8')) + __o['heapSection'] = null + __o['heapSize'] = 1024 + __o['heapTrackEnabled'] = false + __o['includeXdcRuntime'] = false + __o['installedErrorHook'] = String(java.net.URLDecoder.decode('%26xdc_runtime_Error_print__E', 'UTF-8')) + __o['libDir'] = null + __o['libType'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS.LibType_Custom', 'UTF-8')) + __o['logsEnabled'] = false + __o['rovShowRawTab$'] = true + __o['rovViewInfo'] = __obj[84.0] + __o['rtsGateType'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS.GateMutex', 'UTF-8')) + __o['runtimeCreatesEnabled'] = true + __o['setupSecureContext'] = false + __o['smpEnabled'] = false + __o['startupFxns'] = __obj[1073.0] + __o['swiEnabled'] = true + __o['taskEnabled'] = true + __o['useSK'] = false + __o['version'] = 410881 + __o['viewNameMap$'] = __obj[1074.0] + +__o = __obj[1057] // ti.sysbios.BIOS/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2F%24instances', 'UTF-8')) + +__o = __obj[1058] // ti.sysbios.BIOS/common$ + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2Fcommon%24', 'UTF-8')) + __o['diags_ANALYSIS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_ASSERT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_ENTRY'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_EXIT'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INFO'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_INTERNAL'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_LIFECYCLE'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_STATUS'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_ON', 'UTF-8')) + __o['diags_USER1'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER2'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER3'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER4'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER5'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER6'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER7'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['diags_USER8'] = String(java.net.URLDecoder.decode('xdc.runtime.Diags.ALWAYS_OFF', 'UTF-8')) + __o['fxntab'] = true + __o['gate'] = __obj[161.0] + __o['gateParams'] = null + __o['instanceHeap'] = null + __o['instanceSection'] = null + __o['logger'] = null + __o['memoryPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.DELETE_POLICY', 'UTF-8')) + __o['namedInstance'] = false + __o['namedModule'] = true + __o['outPolicy'] = String(java.net.URLDecoder.decode('xdc.runtime.Types.COMMON_FILE', 'UTF-8')) + __o['romPatchTable'] = false + +__o = __obj[1059] // ti.sysbios.BIOS/configNameMap$ + __o.$keys = [] + __o.push(__o['xdc.runtime/Memory'] = __obj[1060.0]); __o.$keys.push('xdc.runtime/Memory') + __o.push(__o['xdc.runtime/Diagnostics'] = __obj[1062.0]); __o.$keys.push('xdc.runtime/Diagnostics') + __o.push(__o['xdc.runtime/Concurrency'] = __obj[1064.0]); __o.$keys.push('xdc.runtime/Concurrency') + __o.push(__o['xdc.runtime/Log Events'] = __obj[1066.0]); __o.$keys.push('xdc.runtime/Log Events') + __o.push(__o['xdc.runtime/Asserts'] = __obj[1068.0]); __o.$keys.push('xdc.runtime/Asserts') + __o.push(__o['xdc.runtime/Errors'] = __obj[1070.0]); __o.$keys.push('xdc.runtime/Errors') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24', 'UTF-8')) + +__o = __obj[1060] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Memory' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27', 'UTF-8')) + __o['fields'] = __obj[1061.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[1061] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Memory'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FMemory%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.instanceHeap', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.instanceSection', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.memoryPolicy', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.namedModule', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.namedInstance', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.fxntab', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.romPatchTable', 'UTF-8')) + +__o = __obj[1062] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Diagnostics' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27', 'UTF-8')) + __o['fields'] = __obj[1063.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[1063] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Diagnostics'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FDiagnostics%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.logger', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.diags_ASSERT', 'UTF-8')) + __o['2'] = String(java.net.URLDecoder.decode('common%24.diags_ENTRY', 'UTF-8')) + __o['3'] = String(java.net.URLDecoder.decode('common%24.diags_EXIT', 'UTF-8')) + __o['4'] = String(java.net.URLDecoder.decode('common%24.diags_INTERNAL', 'UTF-8')) + __o['5'] = String(java.net.URLDecoder.decode('common%24.diags_LIFECYCLE', 'UTF-8')) + __o['6'] = String(java.net.URLDecoder.decode('common%24.diags_STATUS', 'UTF-8')) + __o['7'] = String(java.net.URLDecoder.decode('common%24.diags_USER1', 'UTF-8')) + __o['8'] = String(java.net.URLDecoder.decode('common%24.diags_USER2', 'UTF-8')) + __o['9'] = String(java.net.URLDecoder.decode('common%24.diags_USER3', 'UTF-8')) + __o['10'] = String(java.net.URLDecoder.decode('common%24.diags_USER4', 'UTF-8')) + __o['11'] = String(java.net.URLDecoder.decode('common%24.diags_USER5', 'UTF-8')) + __o['12'] = String(java.net.URLDecoder.decode('common%24.diags_USER6', 'UTF-8')) + __o['13'] = String(java.net.URLDecoder.decode('common%24.diags_INFO', 'UTF-8')) + __o['14'] = String(java.net.URLDecoder.decode('common%24.diags_ANALYSIS', 'UTF-8')) + +__o = __obj[1064] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Concurrency' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27', 'UTF-8')) + __o['fields'] = __obj[1065.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('module', 'UTF-8')) + +__o = __obj[1065] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Concurrency'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FConcurrency%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('common%24.gate', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('common%24.gateParams', 'UTF-8')) + +__o = __obj[1066] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Log Events' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27', 'UTF-8')) + __o['fields'] = __obj[1067.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[1067] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Log Events'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FLog+Events%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Log.Event', 'UTF-8')) + +__o = __obj[1068] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Asserts' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27', 'UTF-8')) + __o['fields'] = __obj[1069.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[1069] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Asserts'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FAsserts%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Assert.Id', 'UTF-8')) + +__o = __obj[1070] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Errors' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27', 'UTF-8')) + __o['fields'] = __obj[1071.0] + __o['viewFxn'] = undefined + __o['viewType'] = String(java.net.URLDecoder.decode('instance', 'UTF-8')) + +__o = __obj[1071] // ti.sysbios.BIOS/configNameMap$/'xdc.runtime/Errors'/fields + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FconfigNameMap%24%2F%27xdc.runtime%2FErrors%27%2Ffields', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('Error.Id', 'UTF-8')) + +__o = __obj[1072] // ti.sysbios.BIOS/cpuFreq + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FcpuFreq', 'UTF-8')) + __o['hi'] = 0 + __o['lo'] = 80000000 + +__o = __obj[1073] // ti.sysbios.BIOS/startupFxns + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FstartupFxns', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('%26ti_sysbios_BIOS_registerRTSLock', 'UTF-8')) + __o['1'] = String(java.net.URLDecoder.decode('%26ti_sysbios_family_arm_lm4_Timer_startup__E', 'UTF-8')) + +__o = __obj[1074] // ti.sysbios.BIOS/viewNameMap$ + __o.$keys = [] + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.sysbios.BIOS%2FviewNameMap%24', 'UTF-8')) + +__o = __obj[1075] + __o['cfgArgs'] = null + __o['cfgArgsEncoded'] = true + __o['cfgHome'] = String(java.net.URLDecoder.decode('configPkg', 'UTF-8')) + __o['cfgScript'] = String(java.net.URLDecoder.decode('C%3A%2FUsers%2FAllen%2FDocuments%2FGitHub%2Fmm20%2FCCS%2Fmm%2Fgpiointerrupt.cfg', 'UTF-8')) + __o['prelink'] = false + __o['profile'] = String(java.net.URLDecoder.decode('release', 'UTF-8')) + __o['releases'] = __obj[1076.0] + __o['target'] = __obj[1081.0] + +__o = __obj[1076] + __o['0'] = __obj[1077.0] + +__o = __obj[1077] + __o['attrs'] = __obj[1078.0] + __o['excludeDirs'] = __obj[1079.0] + __o['name'] = String(java.net.URLDecoder.decode('configPkg', 'UTF-8')) + __o['otherFiles'] = __obj[1080.0] + +__o = __obj[1078] + __o['label'] = String(java.net.URLDecoder.decode('default', 'UTF-8')) + __o['prefix'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + +__o = __obj[1079] + +__o = __obj[1080] + +__o = __obj[1081] // ti.targets.arm.elf.M4F + __o['$category'] = String(java.net.URLDecoder.decode('Module', 'UTF-8')) + __o['$instances'] = __obj[1082.0] + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F', 'UTF-8')) + __o['alignDirectiveSupported'] = true + __o['ar'] = __obj[1083.0] + __o['arOpts'] = __obj[1084.0] + __o['asm'] = __obj[1085.0] + __o['asmOpts'] = __obj[1086.0] + __o['base'] = undefined + __o['binDir'] = String(java.net.URLDecoder.decode('%24%28rootDir%29%2Fbin%2F', 'UTF-8')) + __o['binaryParser'] = String(java.net.URLDecoder.decode('ti.targets.omf.elf.Elf32', 'UTF-8')) + __o['bitsPerChar'] = 8 + __o['cc'] = __obj[1087.0] + __o['ccConfigOpts'] = __obj[1088.0] + __o['ccOpts'] = __obj[1089.0] + __o['compatibleSuffixes'] = __obj[1090.0] + __o['debugGen'] = __obj[1091.0] + __o['dllExt'] = undefined + __o['execExt'] = undefined + __o['extensions'] = __obj[1092.0] + __o['includeOpts'] = String(java.net.URLDecoder.decode('-I%24%28rootDir%29%2Finclude%2Frts+-I%24%28rootDir%29%2Finclude+', 'UTF-8')) + __o['isa'] = String(java.net.URLDecoder.decode('v7M4', 'UTF-8')) + __o['lnk'] = __obj[1103.0] + __o['lnkOpts'] = __obj[1104.0] + __o['model'] = __obj[1105.0] + __o['name'] = String(java.net.URLDecoder.decode('M4F', 'UTF-8')) + __o['os'] = undefined + __o['pathPrefix'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['platform'] = String(java.net.URLDecoder.decode('ti.platforms.tiva%3ATM4C1294NCPDT%3A1', 'UTF-8')) + __o['platforms'] = __obj[1106.0] + __o['profiles'] = __obj[1107.0] + __o['rawVersion'] = String(java.net.URLDecoder.decode('18.12.4', 'UTF-8')) + __o['rootDir'] = String(java.net.URLDecoder.decode('C%3A%2Fti%2Fccs930%2Fccs%2Ftools%2Fcompiler%2Fti-cgt-arm_18.12.4.LTS', 'UTF-8')) + __o['rts'] = String(java.net.URLDecoder.decode('ti.targets.arm.rtsarm', 'UTF-8')) + __o['sectMap'] = __obj[1120.0] + __o['splitMap'] = __obj[1121.0] + __o['stdInclude'] = String(java.net.URLDecoder.decode('ti%2Ftargets%2Farm%2Felf%2Fstd.h', 'UTF-8')) + __o['stdTypes'] = __obj[1122.0] + __o['suffix'] = String(java.net.URLDecoder.decode('em4f', 'UTF-8')) + __o['vers'] = __obj[1140.0] + __o['version'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%7B1%2C0%2C18.12%2C4', 'UTF-8')) + __o['versionMap'] = __obj[1141.0] + __o['versionRaw'] = undefined + +__o = __obj[1082] // ti.targets.arm.elf.M4F/$instances + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2F%24instances', 'UTF-8')) + +__o = __obj[1083] // ti.targets.arm.elf.M4F/ar + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Far', 'UTF-8')) + __o['cmd'] = String(java.net.URLDecoder.decode('armar', 'UTF-8')) + __o['opts'] = String(java.net.URLDecoder.decode('rq', 'UTF-8')) + +__o = __obj[1084] // ti.targets.arm.elf.M4F/arOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FarOpts', 'UTF-8')) + __o['prefix'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + __o['suffix'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + +__o = __obj[1085] // ti.targets.arm.elf.M4F/asm + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fasm', 'UTF-8')) + __o['cmd'] = String(java.net.URLDecoder.decode('armcl+-c', 'UTF-8')) + __o['opts'] = String(java.net.URLDecoder.decode('--endian%3Dlittle+-mv7M4+--abi%3Deabi+--float_support%3Dfpv4spd16', 'UTF-8')) + +__o = __obj[1086] // ti.targets.arm.elf.M4F/asmOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FasmOpts', 'UTF-8')) + __o['prefix'] = String(java.net.URLDecoder.decode('-qq', 'UTF-8')) + __o['suffix'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + +__o = __obj[1087] // ti.targets.arm.elf.M4F/cc + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fcc', 'UTF-8')) + __o['cmd'] = String(java.net.URLDecoder.decode('armcl+-c', 'UTF-8')) + __o['opts'] = String(java.net.URLDecoder.decode('--endian%3Dlittle+-mv7M4+--abi%3Deabi+--float_support%3Dfpv4spd16', 'UTF-8')) + +__o = __obj[1088] // ti.targets.arm.elf.M4F/ccConfigOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FccConfigOpts', 'UTF-8')) + __o['prefix'] = String(java.net.URLDecoder.decode('%24%28ccOpts.prefix%29+-ms+--fp_mode%3Dstrict', 'UTF-8')) + __o['suffix'] = String(java.net.URLDecoder.decode('%24%28ccOpts.suffix%29', 'UTF-8')) + +__o = __obj[1089] // ti.targets.arm.elf.M4F/ccOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FccOpts', 'UTF-8')) + __o['prefix'] = String(java.net.URLDecoder.decode('-mv7M4+--code_state%3D16+--float_support%3DFPv4SPD16+-me+--include_path%3D%22C%3A%2FUsers%2FAllen%2FDocuments%2FGitHub%2Fmm20%2FCCS%2Fmm%22+--include_path%3D%22C%3A%2FUsers%2FAllen%2FDocuments%2FGitHub%2Fmm20%2FCCS%2Fmm%2Finc%22+--include_path%3D%22C%3A%2FUsers%2FAllen%2FDocuments%2FGitHub%2Fmm20%2FCCS%2Fmm%22+--include_path%3D%22C%3A%2Fti%2Ftirtos_tivac_2_16_00_08%2Fproducts%2FTivaWare_C_Series-2.1.1.71b%22+--include_path%3D%22C%3A%2Fti%2Ftirtos_tivac_2_16_00_08%2Fproducts%2Fbios_6_45_01_29%2Fpackages%2Fti%2Fsysbios%2Fposix%22+--include_path%3D%22C%3A%2Fti%2Fccs930%2Fccs%2Ftools%2Fcompiler%2Fti-cgt-arm_18.12.4.LTS%2Finclude%22+--define%3Dccs%3D%22ccs%22+--define%3DPART_TM4C123GH6PM+--define%3Dccs+--define%3DTIVAWARE+-g+--c99+--gcc+--diag_warning%3D225+--diag_warning%3D255+--diag_wrap%3Doff+--display_error_number+--gen_func_subsections%3Don+--abi%3Deabi+++-qq+-pdsw225', 'UTF-8')) + __o['suffix'] = String(java.net.URLDecoder.decode('', 'UTF-8')) + +__o = __obj[1090] // ti.targets.arm.elf.M4F/compatibleSuffixes + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FcompatibleSuffixes', 'UTF-8')) + +__o = __obj[1091] // ti.targets.arm.elf.M4F/debugGen + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FdebugGen', 'UTF-8')) + __o['execPattern'] = null + __o['execTemplate'] = null + __o['packagePattern'] = null + __o['packageTemplate'] = null + +__o = __obj[1092] // ti.targets.arm.elf.M4F/extensions + __o.$keys = [] + __o.push(__o['.sem4fe'] = __obj[1093.0]); __o.$keys.push('.sem4fe') + __o.push(__o['.sem4f'] = __obj[1094.0]); __o.$keys.push('.sem4f') + __o.push(__o['.sv7M4'] = __obj[1095.0]); __o.$keys.push('.sv7M4') + __o.push(__o['.sv7M'] = __obj[1096.0]); __o.$keys.push('.sv7M') + __o.push(__o['.asm'] = __obj[1097.0]); __o.$keys.push('.asm') + __o.push(__o['.c'] = __obj[1098.0]); __o.$keys.push('.c') + __o.push(__o['.cpp'] = __obj[1099.0]); __o.$keys.push('.cpp') + __o.push(__o['.cxx'] = __obj[1100.0]); __o.$keys.push('.cxx') + __o.push(__o['.C'] = __obj[1101.0]); __o.$keys.push('.C') + __o.push(__o['.cc'] = __obj[1102.0]); __o.$keys.push('.cc') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions', 'UTF-8')) + +__o = __obj[1093] // ti.targets.arm.elf.M4F/extensions/'.sem4fe' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.sem4fe%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.sem4fe', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('asm', 'UTF-8')) + +__o = __obj[1094] // ti.targets.arm.elf.M4F/extensions/'.sem4f' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.sem4f%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.sem4f', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('asm', 'UTF-8')) + +__o = __obj[1095] // ti.targets.arm.elf.M4F/extensions/'.sv7M4' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.sv7M4%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.sv7M4', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('asm', 'UTF-8')) + +__o = __obj[1096] // ti.targets.arm.elf.M4F/extensions/'.sv7M' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.sv7M%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.sv7M', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('asm', 'UTF-8')) + +__o = __obj[1097] // ti.targets.arm.elf.M4F/extensions/'.asm' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.asm%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.asm', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('asm', 'UTF-8')) + +__o = __obj[1098] // ti.targets.arm.elf.M4F/extensions/'.c' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.c%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.c', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('c', 'UTF-8')) + +__o = __obj[1099] // ti.targets.arm.elf.M4F/extensions/'.cpp' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.cpp%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.cpp', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('cpp', 'UTF-8')) + +__o = __obj[1100] // ti.targets.arm.elf.M4F/extensions/'.cxx' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.cxx%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.cxx', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('cpp', 'UTF-8')) + +__o = __obj[1101] // ti.targets.arm.elf.M4F/extensions/'.C' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.C%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.C', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('cpp', 'UTF-8')) + +__o = __obj[1102] // ti.targets.arm.elf.M4F/extensions/'.cc' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fextensions%2F%27.cc%27', 'UTF-8')) + __o['suf'] = String(java.net.URLDecoder.decode('.cc', 'UTF-8')) + __o['typ'] = String(java.net.URLDecoder.decode('cpp', 'UTF-8')) + +__o = __obj[1103] // ti.targets.arm.elf.M4F/lnk + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Flnk', 'UTF-8')) + __o['cmd'] = String(java.net.URLDecoder.decode('armcl', 'UTF-8')) + __o['opts'] = String(java.net.URLDecoder.decode('--silicon_version%3D7M4+-z+--strict_compatibility%3Don', 'UTF-8')) + +__o = __obj[1104] // ti.targets.arm.elf.M4F/lnkOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FlnkOpts', 'UTF-8')) + __o['prefix'] = String(java.net.URLDecoder.decode('-q+-u+_c_int00', 'UTF-8')) + __o['suffix'] = String(java.net.URLDecoder.decode('-w+-c+-m+%24%28XDCCFGDIR%29%2F%24%40.map+-l+%24%28rootDir%29%2Flib%2Flibc.a', 'UTF-8')) + +__o = __obj[1105] // ti.targets.arm.elf.M4F/model + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fmodel', 'UTF-8')) + __o['codeModel'] = String(java.net.URLDecoder.decode('thumb2', 'UTF-8')) + __o['dataModel'] = undefined + __o['endian'] = String(java.net.URLDecoder.decode('little', 'UTF-8')) + __o['shortEnums'] = true + +__o = __obj[1106] // ti.targets.arm.elf.M4F/platforms + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fplatforms', 'UTF-8')) + __o['0'] = String(java.net.URLDecoder.decode('ti.platforms.tiva%3ATM4C1294NCPDT%3A1', 'UTF-8')) + +__o = __obj[1107] // ti.targets.arm.elf.M4F/profiles + __o.$keys = [] + __o.push(__o['debug'] = __obj[1108.0]); __o.$keys.push('debug') + __o.push(__o['release'] = __obj[1111.0]); __o.$keys.push('release') + __o.push(__o['profile'] = __obj[1114.0]); __o.$keys.push('profile') + __o.push(__o['coverage'] = __obj[1117.0]); __o.$keys.push('coverage') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles', 'UTF-8')) + +__o = __obj[1108] // ti.targets.arm.elf.M4F/profiles/'debug' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27debug%27', 'UTF-8')) + __o['archiveOpts'] = undefined + __o['compileOpts'] = __obj[1109.0] + __o['filters'] = __obj[1110.0] + __o['linkOpts'] = undefined + +__o = __obj[1109] // ti.targets.arm.elf.M4F/profiles/'debug'/compileOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27debug%27%2FcompileOpts', 'UTF-8')) + __o['aopts'] = undefined + __o['cfgcopts'] = undefined + __o['copts'] = String(java.net.URLDecoder.decode('--symdebug%3Adwarf', 'UTF-8')) + __o['defs'] = String(java.net.URLDecoder.decode('-D_DEBUG_%3D1', 'UTF-8')) + __o['incs'] = undefined + +__o = __obj[1110] // ti.targets.arm.elf.M4F/profiles/'debug'/filters + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27debug%27%2Ffilters', 'UTF-8')) + +__o = __obj[1111] // ti.targets.arm.elf.M4F/profiles/'release' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27release%27', 'UTF-8')) + __o['archiveOpts'] = undefined + __o['compileOpts'] = __obj[1112.0] + __o['filters'] = __obj[1113.0] + __o['linkOpts'] = undefined + +__o = __obj[1112] // ti.targets.arm.elf.M4F/profiles/'release'/compileOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27release%27%2FcompileOpts', 'UTF-8')) + __o['aopts'] = undefined + __o['cfgcopts'] = undefined + __o['copts'] = String(java.net.URLDecoder.decode('-O2', 'UTF-8')) + __o['defs'] = undefined + __o['incs'] = undefined + +__o = __obj[1113] // ti.targets.arm.elf.M4F/profiles/'release'/filters + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27release%27%2Ffilters', 'UTF-8')) + +__o = __obj[1114] // ti.targets.arm.elf.M4F/profiles/'profile' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27profile%27', 'UTF-8')) + __o['archiveOpts'] = undefined + __o['compileOpts'] = __obj[1115.0] + __o['filters'] = __obj[1116.0] + __o['linkOpts'] = undefined + +__o = __obj[1115] // ti.targets.arm.elf.M4F/profiles/'profile'/compileOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27profile%27%2FcompileOpts', 'UTF-8')) + __o['aopts'] = undefined + __o['cfgcopts'] = undefined + __o['copts'] = String(java.net.URLDecoder.decode('--symdebug%3Adwarf', 'UTF-8')) + __o['defs'] = undefined + __o['incs'] = undefined + +__o = __obj[1116] // ti.targets.arm.elf.M4F/profiles/'profile'/filters + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27profile%27%2Ffilters', 'UTF-8')) + +__o = __obj[1117] // ti.targets.arm.elf.M4F/profiles/'coverage' + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27coverage%27', 'UTF-8')) + __o['archiveOpts'] = undefined + __o['compileOpts'] = __obj[1118.0] + __o['filters'] = __obj[1119.0] + __o['linkOpts'] = undefined + +__o = __obj[1118] // ti.targets.arm.elf.M4F/profiles/'coverage'/compileOpts + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27coverage%27%2FcompileOpts', 'UTF-8')) + __o['aopts'] = undefined + __o['cfgcopts'] = undefined + __o['copts'] = String(java.net.URLDecoder.decode('--symdebug%3Adwarf', 'UTF-8')) + __o['defs'] = undefined + __o['incs'] = undefined + +__o = __obj[1119] // ti.targets.arm.elf.M4F/profiles/'coverage'/filters + __o['$category'] = String(java.net.URLDecoder.decode('Vector', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fprofiles%2F%27coverage%27%2Ffilters', 'UTF-8')) + +__o = __obj[1120] // ti.targets.arm.elf.M4F/sectMap + __o.$keys = [] + __o.push(__o['.text'] = String(java.net.URLDecoder.decode('code', 'UTF-8'))); __o.$keys.push('.text') + __o.push(__o['.stack'] = String(java.net.URLDecoder.decode('stack', 'UTF-8'))); __o.$keys.push('.stack') + __o.push(__o['.bss'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.bss') + __o.push(__o['.binit'] = String(java.net.URLDecoder.decode('code', 'UTF-8'))); __o.$keys.push('.binit') + __o.push(__o['.cinit'] = String(java.net.URLDecoder.decode('code', 'UTF-8'))); __o.$keys.push('.cinit') + __o.push(__o['.init_array'] = String(java.net.URLDecoder.decode('code', 'UTF-8'))); __o.$keys.push('.init_array') + __o.push(__o['.const'] = String(java.net.URLDecoder.decode('code', 'UTF-8'))); __o.$keys.push('.const') + __o.push(__o['.data'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.data') + __o.push(__o['.rodata'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.rodata') + __o.push(__o['.neardata'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.neardata') + __o.push(__o['.fardata'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.fardata') + __o.push(__o['.switch'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.switch') + __o.push(__o['.sysmem'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.sysmem') + __o.push(__o['.far'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.far') + __o.push(__o['.args'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.args') + __o.push(__o['.cio'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.cio') + __o.push(__o['.ARM.exidx'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.ARM.exidx') + __o.push(__o['.ARM.extab'] = String(java.net.URLDecoder.decode('data', 'UTF-8'))); __o.$keys.push('.ARM.extab') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FsectMap', 'UTF-8')) + +__o = __obj[1121] // ti.targets.arm.elf.M4F/splitMap + __o.$keys = [] + __o.push(__o['.text'] = true); __o.$keys.push('.text') + __o.push(__o['.const'] = true); __o.$keys.push('.const') + __o.push(__o['.data'] = true); __o.$keys.push('.data') + __o.push(__o['.fardata'] = true); __o.$keys.push('.fardata') + __o.push(__o['.switch'] = true); __o.$keys.push('.switch') + __o.push(__o['.far'] = true); __o.$keys.push('.far') + __o.push(__o['.args'] = true); __o.$keys.push('.args') + __o.push(__o['.cio'] = true); __o.$keys.push('.cio') + __o.push(__o['.ARM.extab'] = true); __o.$keys.push('.ARM.extab') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FsplitMap', 'UTF-8')) + +__o = __obj[1122] // ti.targets.arm.elf.M4F/stdTypes + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes', 'UTF-8')) + __o['t_Char'] = __obj[1123.0] + __o['t_Double'] = __obj[1124.0] + __o['t_Float'] = __obj[1125.0] + __o['t_Fxn'] = __obj[1126.0] + __o['t_IArg'] = __obj[1127.0] + __o['t_Int'] = __obj[1128.0] + __o['t_Int16'] = __obj[1129.0] + __o['t_Int32'] = __obj[1130.0] + __o['t_Int40'] = __obj[1131.0] + __o['t_Int64'] = __obj[1132.0] + __o['t_Int8'] = __obj[1133.0] + __o['t_LDouble'] = __obj[1134.0] + __o['t_LLong'] = __obj[1135.0] + __o['t_Long'] = __obj[1136.0] + __o['t_Ptr'] = __obj[1137.0] + __o['t_Short'] = __obj[1138.0] + __o['t_Size'] = __obj[1139.0] + +__o = __obj[1123] // ti.targets.arm.elf.M4F/stdTypes/t_Char + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Char', 'UTF-8')) + __o['align'] = 1 + __o['size'] = 1 + +__o = __obj[1124] // ti.targets.arm.elf.M4F/stdTypes/t_Double + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Double', 'UTF-8')) + __o['align'] = 8 + __o['size'] = 8 + +__o = __obj[1125] // ti.targets.arm.elf.M4F/stdTypes/t_Float + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Float', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1126] // ti.targets.arm.elf.M4F/stdTypes/t_Fxn + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Fxn', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1127] // ti.targets.arm.elf.M4F/stdTypes/t_IArg + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_IArg', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1128] // ti.targets.arm.elf.M4F/stdTypes/t_Int + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Int', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1129] // ti.targets.arm.elf.M4F/stdTypes/t_Int16 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Int16', 'UTF-8')) + __o['align'] = 2 + __o['size'] = 2 + +__o = __obj[1130] // ti.targets.arm.elf.M4F/stdTypes/t_Int32 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Int32', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1131] // ti.targets.arm.elf.M4F/stdTypes/t_Int40 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Int40', 'UTF-8')) + __o['align'] = undefined + __o['size'] = undefined + +__o = __obj[1132] // ti.targets.arm.elf.M4F/stdTypes/t_Int64 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Int64', 'UTF-8')) + __o['align'] = 8 + __o['size'] = 8 + +__o = __obj[1133] // ti.targets.arm.elf.M4F/stdTypes/t_Int8 + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Int8', 'UTF-8')) + __o['align'] = 1 + __o['size'] = 1 + +__o = __obj[1134] // ti.targets.arm.elf.M4F/stdTypes/t_LDouble + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_LDouble', 'UTF-8')) + __o['align'] = 8 + __o['size'] = 8 + +__o = __obj[1135] // ti.targets.arm.elf.M4F/stdTypes/t_LLong + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_LLong', 'UTF-8')) + __o['align'] = 8 + __o['size'] = 8 + +__o = __obj[1136] // ti.targets.arm.elf.M4F/stdTypes/t_Long + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Long', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1137] // ti.targets.arm.elf.M4F/stdTypes/t_Ptr + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Ptr', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1138] // ti.targets.arm.elf.M4F/stdTypes/t_Short + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Short', 'UTF-8')) + __o['align'] = 2 + __o['size'] = 2 + +__o = __obj[1139] // ti.targets.arm.elf.M4F/stdTypes/t_Size + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FstdTypes%2Ft_Size', 'UTF-8')) + __o['align'] = 4 + __o['size'] = 4 + +__o = __obj[1140] // ti.targets.arm.elf.M4F/vers + __o['$category'] = String(java.net.URLDecoder.decode('Struct', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2Fvers', 'UTF-8')) + __o['cmd'] = String(java.net.URLDecoder.decode('armcl', 'UTF-8')) + __o['opts'] = String(java.net.URLDecoder.decode('--compiler_revision', 'UTF-8')) + +__o = __obj[1141] // ti.targets.arm.elf.M4F/versionMap + __o.$keys = [] + __o.push(__o['TMS320C6x_4.32'] = String(java.net.URLDecoder.decode('1%2C0%2C4.32%2C0', 'UTF-8'))); __o.$keys.push('TMS320C6x_4.32') + __o.push(__o['TMS320C2000_3.07'] = String(java.net.URLDecoder.decode('1%2C0%2C3.07%2C0', 'UTF-8'))); __o.$keys.push('TMS320C2000_3.07') + __o['$category'] = String(java.net.URLDecoder.decode('Map', 'UTF-8')) + __o['$name'] = String(java.net.URLDecoder.decode('ti.targets.arm.elf.M4F%2FversionMap', 'UTF-8')) + +delete __o +delete __obj \ No newline at end of file diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.rta.xml b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.rta.xml new file mode 100644 index 0000000..2eefeea --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.rta.xml @@ -0,0 +1,292 @@ + + ti.targets.arm.elf.M4F + ti.targets.omf.elf.Elf32 + little + 8 + 4 + 48 + undefined + undefined + 0 + 31 + + 32770 + null + 0000100000000000 + + + 32771 + null + 0000100000000000 + + + 32772 + null + 0000110000000000 + + + 32773 + null + 0000100000000000 + + + 32774 + null + 0000110000000000 + + + 32775 + null + 0000100000000000 + + + 32776 + null + 0000100000000000 + + + 32777 + null + 0000110000000000 + + + 32778 + null + 0000100000000000 + + + 32779 + null + 0000110000000000 + + + 32780 + null + 0000100000000000 + + + 32781 + null + 0000100000000000 + + + 32782 + null + 0000100000000000 + + + 32783 + null + 0000100000000000 + + + 32789 + null + 0000110000000000 + + + 32792 + null + 0000110000000000 + + + 32793 + null + 0000110000000000 + + + 32794 + null + 0000110000000000 + + + 32795 + null + 0000110000000000 + + + 32796 + null + 0000110000000000 + + + 32797 + null + 0000110000000000 + + + 32798 + null + 0000110000000000 + + + 32800 + null + 0000110000000000 + + + 32801 + null + 0000110000000000 + + + 32805 + null + 0000110000000000 + + + 32806 + null + 0000110000000000 + + + 32807 + null + 0000110000000000 + + + 32809 + null + 0000110000000000 + + + 32810 + null + 0000110000000000 + + + 32812 + null + 0000110000000000 + + + 32814 + null + 0000110000000000 + + 31 + + 4823 + %3C--+construct%3A+%25p%28%27%25s%27%29 + + + 4847 + %3C--+create%3A+%25p%28%27%25s%27%29 + + + 4868 + --%3E+destruct%3A+%28%25p%29 + + + 4887 + --%3E+delete%3A+%28%25p%29 + + + 4904 + ERROR%3A+%25%24F%25%24S + + + 4918 + WARNING%3A+%25%24F%25%24S + + + 4934 + %25%24F%25%24S + + + 4941 + Start%3A+%25%24S + + + 4952 + Stop%3A+%25%24S + + + 4962 + StartInstance%3A+%25%24S + + + 4981 + StopInstance%3A+%25%24S + + + 4999 + LW_delayed%3A+delay%3A+%25d + + + 5021 + LM_tick%3A+tick%3A+%25d + + + 5039 + LM_begin%3A+clk%3A+0x%25x%2C+func%3A+0x%25x + + + 5071 + LM_post%3A+sem%3A+0x%25x%2C+count%3A+%25d + + + 5101 + LM_pend%3A+sem%3A+0x%25x%2C+count%3A+%25d%2C+timeout%3A+%25d + + + 5144 + LM_begin%3A+swi%3A+0x%25x%2C+func%3A+0x%25x%2C+preThread%3A+%25d + + + 5191 + LD_end%3A+swi%3A+0x%25x + + + 5209 + LM_post%3A+swi%3A+0x%25x%2C+func%3A+0x%25x%2C+pri%3A+%25d + + + 5249 + LM_switch%3A+oldtsk%3A+0x%25x%2C+oldfunc%3A+0x%25x%2C+newtsk%3A+0x%25x%2C+newfunc%3A+0x%25x + + + 5317 + LM_sleep%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+timeout%3A+%25d + + + 5362 + LD_ready%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+pri%3A+%25d + + + 5403 + LD_block%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x + + + 5435 + LM_yield%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+currThread%3A+%25d + + + 5483 + LM_setPri%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+oldPri%3A+%25d%2C+newPri+%25d + + + 5539 + LD_exit%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x + + + 5570 + LM_setAffinity%3A+tsk%3A+0x%25x%2C+func%3A+0x%25x%2C+oldCore%3A+%25d%2C+oldAffinity+%25d%2C+newAffinity+%25d + + + 5653 + LD_schedule%3A+coreId%3A+%25d%2C+workFlag%3A+%25d%2C+curSetLocal%3A+%25d%2C+curSetX%3A+%25d%2C+curMaskLocal%3A+%25d + + + 5739 + LD_noWork%3A+coreId%3A+%25d%2C+curSetLocal%3A+%25d%2C+curSetX%3A+%25d%2C+curMaskLocal%3A+%25d + + + 5809 + LM_begin%3A+hwi%3A+0x%25x%2C+func%3A+0x%25x%2C+preThread%3A+%25d%2C+intNum%3A+%25d%2C+irp%3A+0x%25x + + + 5879 + LD_end%3A+hwi%3A+0x%25x + + diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.xdc.inc b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.xdc.inc new file mode 100644 index 0000000..402b3cc --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.xdc.inc @@ -0,0 +1,2 @@ +package.xs +package/cfg/gpiointerrupt_pem4f.cfg diff --git a/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.xdl b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.xdl new file mode 100644 index 0000000..8a5b87e --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/cfg/gpiointerrupt_pem4f.xdl @@ -0,0 +1,156 @@ +/* + * Do not modify this file; it is automatically generated from the template + * linkcmd.xdt in the ti.platforms.tiva package and will be overwritten. + */ + +/* + * put '"'s around paths because, without this, the linker + * considers '-' as minus operator, not a file name character. + */ + + +-l"C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\Debug\configPkg\package\cfg\gpiointerrupt_pem4f.oem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\packages\ti\tirtos\utils\lib\release\ti.tirtos.utils.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/mw/wifi/cc3x00/lib/cc3x00_host_driver.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_tivaware.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_wifi_tivaware.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\tidrivers_tivac_2_16_00_08\packages\ti\mw\fatfs\lib\release\ti.mw.fatfs.aem4f" +-l"C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/ports/lib/tirtosport.aem4f" +-l"C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\src\sysbios\sysbios.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\catalog\arm\cortexm4\tiva\ce\lib\Boot.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\ti.targets.arm.rtsarm.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\boot.aem4f" +-l"C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\auto_init.aem4f" + +--retain="*(xdc.meta)" + +/* C6x Elf symbols */ +--symbol_map __TI_STACK_SIZE=__STACK_SIZE +--symbol_map __TI_STACK_BASE=__stack +--symbol_map _stack=__stack + + +--args 0x0 +-heap 0x0 +-stack 0x300 + +/* + * Linker command file contributions from all loaded packages: + */ + +/* Content from xdc.services.global (null): */ + +/* Content from xdc (null): */ + +/* Content from xdc.corevers (null): */ + +/* Content from xdc.shelf (null): */ + +/* Content from xdc.services.spec (null): */ + +/* Content from xdc.services.intern.xsr (null): */ + +/* Content from xdc.services.intern.gen (null): */ + +/* Content from xdc.services.intern.cmd (null): */ + +/* Content from xdc.bld (null): */ + +/* Content from ti.targets (null): */ + +/* Content from ti.targets.arm.elf (null): */ + +/* Content from xdc.rov (null): */ + +/* Content from xdc.runtime (null): */ + +/* Content from xdc.services.getset (null): */ + +/* Content from ti.targets.arm.rtsarm (null): */ + +/* Content from ti.sysbios.interfaces (null): */ + +/* Content from ti.sysbios.family (null): */ + +/* Content from ti.sysbios.family.arm (ti/sysbios/family/arm/linkcmd.xdt): */ +--retain "*(.vecs)" + +/* Content from ti.sysbios.rts (ti/sysbios/rts/linkcmd.xdt): */ + +/* Content from xdc.runtime.knl (null): */ + +/* Content from ti.catalog.arm.peripherals.timers (null): */ + +/* Content from ti.catalog.arm.cortexm4 (null): */ + +/* Content from ti.catalog (null): */ + +/* Content from ti.catalog.peripherals.hdvicp2 (null): */ + +/* Content from xdc.platform (null): */ + +/* Content from xdc.cfg (null): */ + +/* Content from ti.catalog.arm.cortexm3 (null): */ + +/* Content from ti.catalog.arm.cortexm4.tiva.ce (null): */ + +/* Content from ti.platforms.tiva (null): */ + +/* Content from ti.sysbios (null): */ + +/* Content from ti.drivers.ports (null): */ + +/* Content from ti.mw.fatfs (null): */ + +/* Content from ti.drivers (null): */ + +/* Content from ti.mw.wifi.cc3x00 (null): */ + +/* Content from ti.mw (null): */ + +/* Content from ti.sysbios.hal (null): */ + +/* Content from ti.sysbios.family.arm.m3 (ti/sysbios/family/arm/m3/linkcmd.xdt): */ +-u _c_int00 +--retain "*(.resetVecs)" +ti_sysbios_family_arm_m3_Hwi_nvic = 0xe000e000; + +/* Content from ti.sysbios.knl (null): */ + +/* Content from ti.sysbios.family.arm.lm4 (null): */ + +/* Content from ti.tirtos.utils (null): */ + +/* Content from ti.sysbios.gates (null): */ + +/* Content from ti.sysbios.xdcruntime (null): */ + +/* Content from ti.sysbios.heaps (null): */ + +/* Content from ti.sysbios.utils (null): */ + +/* Content from configPkg (null): */ + +/* Content from xdc.services.io (null): */ + + + +/* + * symbolic aliases for static instance objects + */ +xdc_runtime_Startup__EXECFXN__C = 1; +xdc_runtime_Startup__RESETFXN__C = 1; + + +SECTIONS +{ + .bootVecs: type = DSECT + .vecs: load > 0x20000000 + .resetVecs: load > 0x0 + + + + xdc.meta: type = COPY +} + diff --git a/CCS/mm/Debug/configPkg/package/configPkg.ccs b/CCS/mm/Debug/configPkg/package/configPkg.ccs new file mode 100644 index 0000000..d8129eb Binary files /dev/null and b/CCS/mm/Debug/configPkg/package/configPkg.ccs differ diff --git a/CCS/mm/Debug/configPkg/package/configPkg.class b/CCS/mm/Debug/configPkg/package/configPkg.class new file mode 100644 index 0000000..3e89b6e Binary files /dev/null and b/CCS/mm/Debug/configPkg/package/configPkg.class differ diff --git a/CCS/mm/Debug/configPkg/package/configPkg.java b/CCS/mm/Debug/configPkg/package/configPkg.java new file mode 100644 index 0000000..1ba49f9 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/configPkg.java @@ -0,0 +1,143 @@ +/* + * Do not modify this file; it is automatically + * generated and any modifications will be overwritten. + * + * @(#) xdc-B21 + */ +import java.util.*; +import org.mozilla.javascript.*; +import xdc.services.intern.xsr.*; +import xdc.services.spec.Session; + +public class configPkg +{ + static final String VERS = "@(#) xdc-B21\n"; + + static final Proto.Elm $$T_Bool = Proto.Elm.newBool(); + static final Proto.Elm $$T_Num = Proto.Elm.newNum(); + static final Proto.Elm $$T_Str = Proto.Elm.newStr(); + static final Proto.Elm $$T_Obj = Proto.Elm.newObj(); + + static final Proto.Fxn $$T_Met = new Proto.Fxn(null, null, 0, -1, false); + static final Proto.Map $$T_Map = new Proto.Map($$T_Obj); + static final Proto.Arr $$T_Vec = new Proto.Arr($$T_Obj); + + static final XScriptO $$DEFAULT = Value.DEFAULT; + static final Object $$UNDEF = Undefined.instance; + + static final Proto.Obj $$Package = (Proto.Obj)Global.get("$$Package"); + static final Proto.Obj $$Module = (Proto.Obj)Global.get("$$Module"); + static final Proto.Obj $$Instance = (Proto.Obj)Global.get("$$Instance"); + static final Proto.Obj $$Params = (Proto.Obj)Global.get("$$Params"); + + static final Object $$objFldGet = Global.get("$$objFldGet"); + static final Object $$objFldSet = Global.get("$$objFldSet"); + static final Object $$proxyGet = Global.get("$$proxyGet"); + static final Object $$proxySet = Global.get("$$proxySet"); + static final Object $$delegGet = Global.get("$$delegGet"); + static final Object $$delegSet = Global.get("$$delegSet"); + + Scriptable xdcO; + Session ses; + Value.Obj om; + + boolean isROV; + boolean isCFG; + + Proto.Obj pkgP; + Value.Obj pkgV; + + ArrayList imports = new ArrayList(); + ArrayList loggables = new ArrayList(); + ArrayList mcfgs = new ArrayList(); + ArrayList icfgs = new ArrayList(); + ArrayList inherits = new ArrayList(); + ArrayList proxies = new ArrayList(); + ArrayList sizes = new ArrayList(); + ArrayList tdefs = new ArrayList(); + + void $$IMPORTS() + { + Global.callFxn("loadPackage", xdcO, "xdc"); + Global.callFxn("loadPackage", xdcO, "xdc.corevers"); + } + + void $$OBJECTS() + { + pkgP = (Proto.Obj)om.bind("configPkg.Package", new Proto.Obj()); + pkgV = (Value.Obj)om.bind("configPkg", new Value.Obj("configPkg", pkgP)); + } + + void $$SINGLETONS() + { + pkgP.init("configPkg.Package", (Proto.Obj)om.findStrict("xdc.IPackage.Module", "configPkg")); + Scriptable cap = (Scriptable)Global.callFxn("loadCapsule", xdcO, "configPkg/package.xs"); + om.bind("xdc.IPackage$$capsule", cap); + Object fxn; + fxn = Global.get(cap, "init"); + if (fxn != null) pkgP.addFxn("init", (Proto.Fxn)om.findStrict("xdc.IPackage$$init", "configPkg"), fxn); + fxn = Global.get(cap, "close"); + if (fxn != null) pkgP.addFxn("close", (Proto.Fxn)om.findStrict("xdc.IPackage$$close", "configPkg"), fxn); + fxn = Global.get(cap, "validate"); + if (fxn != null) pkgP.addFxn("validate", (Proto.Fxn)om.findStrict("xdc.IPackage$$validate", "configPkg"), fxn); + fxn = Global.get(cap, "exit"); + if (fxn != null) pkgP.addFxn("exit", (Proto.Fxn)om.findStrict("xdc.IPackage$$exit", "configPkg"), fxn); + fxn = Global.get(cap, "getLibs"); + if (fxn != null) pkgP.addFxn("getLibs", (Proto.Fxn)om.findStrict("xdc.IPackage$$getLibs", "configPkg"), fxn); + fxn = Global.get(cap, "getSects"); + if (fxn != null) pkgP.addFxn("getSects", (Proto.Fxn)om.findStrict("xdc.IPackage$$getSects", "configPkg"), fxn); + pkgP.bind("$capsule", cap); + pkgV.init2(pkgP, "configPkg", Value.DEFAULT, false); + pkgV.bind("$name", "configPkg"); + pkgV.bind("$category", "Package"); + pkgV.bind("$$qn", "configPkg."); + pkgV.bind("$vers", Global.newArray()); + Value.Map atmap = (Value.Map)pkgV.getv("$attr"); + atmap.seal("length"); + imports.clear(); + pkgV.bind("$imports", imports); + StringBuilder sb = new StringBuilder(); + sb.append("var pkg = xdc.om['configPkg'];\n"); + sb.append("if (pkg.$vers.length >= 3) {\n"); + sb.append("pkg.$vers.push(Packages.xdc.services.global.Vers.getDate(xdc.csd() + '/..'));\n"); + sb.append("}\n"); + sb.append("if ('configPkg$$stat$base' in xdc.om) {\n"); + sb.append("pkg.packageBase = xdc.om['configPkg$$stat$base'];\n"); + sb.append("pkg.packageRepository = xdc.om['configPkg$$stat$root'];\n"); + sb.append("}\n"); + sb.append("pkg.build.libraries = [\n"); + sb.append("];\n"); + sb.append("pkg.build.libDesc = [\n"); + sb.append("];\n"); + Global.eval(sb.toString()); + } + + void $$INITIALIZATION() + { + Value.Obj vo; + + if (isCFG) { + }//isCFG + Global.callFxn("init", pkgV); + ((Value.Arr)om.findStrict("$packages", "configPkg")).add(pkgV); + } + + public void exec( Scriptable xdcO, Session ses ) + { + this.xdcO = xdcO; + this.ses = ses; + om = (Value.Obj)xdcO.get("om", null); + + Object o = om.geto("$name"); + String s = o instanceof String ? (String)o : null; + isCFG = s != null && s.equals("cfg"); + isROV = s != null && s.equals("rov"); + + $$IMPORTS(); + $$OBJECTS(); + if (isROV) { + }//isROV + $$SINGLETONS(); + $$INITIALIZATION(); + } +} diff --git a/CCS/mm/Debug/configPkg/package/configPkg.sch b/CCS/mm/Debug/configPkg/package/configPkg.sch new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/configPkg/package/package.bld.xml b/CCS/mm/Debug/configPkg/package/package.bld.xml new file mode 100644 index 0000000..9714515 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/package.bld.xml @@ -0,0 +1,84 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CCS/mm/Debug/configPkg/package/package.defs.h b/CCS/mm/Debug/configPkg/package/package.defs.h new file mode 100644 index 0000000..4689122 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/package.defs.h @@ -0,0 +1,13 @@ +/* + * Do not modify this file; it is automatically + * generated and any modifications will be overwritten. + * + * @(#) xdc-B21 + */ + +#ifndef configPkg__ +#define configPkg__ + + + +#endif /* configPkg__ */ diff --git a/CCS/mm/Debug/configPkg/package/package.xdc.dep b/CCS/mm/Debug/configPkg/package/package.xdc.dep new file mode 100644 index 0000000..2b621e5 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/package.xdc.dep @@ -0,0 +1,53 @@ +clean:: + $(RM) package/configPkg.sch + $(RM) package/.vers_g180 + $(RM) package/.vers_r170 + $(RM) package/.vers_b160 + $(RM) package/.xdc-B21 + $(RM) package/configPkg.java + $(RM) package/configPkg.class + $(RM) package/package_configPkg.c + $(RM) package/package.defs.h + $(RM) package/configPkg.ccs + +.interfaces: package/configPkg.sch package/.vers_g180 package/.vers_r170 package/.vers_b160 package/.xdc-B21 package/configPkg.java package/package_configPkg.c package/package.defs.h package/configPkg.ccs +package/package.xdc.inc: package/.vers_g180 +package/.vers_g180: +package/package.xdc.inc: package/.vers_r170 +package/.vers_r170: +package/package.xdc.inc: package/.vers_b160 +package/.vers_b160: + +.interfaces: + +# schema include file dependencies +package.xs: +package/package.xdc.inc: package.xs + +# schema update dependencies +package/package.xdc.inc: xdc/IPackage.xdc +xdc/IPackage.xdc: +vpath xdc/IPackage.xdc $(XPKGVPATH) + +ifneq (clean,$(MAKECMDGOALS)) +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/js.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/js.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/java/package.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/global/java/package.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/spec/java/package.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/spec/java/package.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/intern/gen/java/package.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/intern/gen/java/package.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/antlr.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/antlr.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/intern/cmd/java/package.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/intern/cmd/java/package.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/intern/xsr/java/package.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/services/intern/xsr/java/package.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/ecj.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/ecj.jar +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/tar.jar: +package/package.xdc.inc: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/shelf/java/tar.jar +endif +# goals for files generated during schema generation but unspecified by schema's pattern rule + diff --git a/CCS/mm/Debug/configPkg/package/package.xdc.inc b/CCS/mm/Debug/configPkg/package/package.xdc.inc new file mode 100644 index 0000000..534fa14 --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/package.xdc.inc @@ -0,0 +1,12 @@ +package.xdc +package.xs +package/configPkg.sch +package/.vers_g180 +package/.vers_r170 +package/.vers_b160 +package/.xdc-B21 +package/configPkg.java +package/configPkg.class +package/package_configPkg.c +package/package.defs.h +package/configPkg.ccs diff --git a/CCS/mm/Debug/configPkg/package/package_configPkg.c b/CCS/mm/Debug/configPkg/package/package_configPkg.c new file mode 100644 index 0000000..16533ca --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/package_configPkg.c @@ -0,0 +1,21 @@ +/* + * Do not modify this file; it is automatically + * generated and any modifications will be overwritten. + * + * @(#) xdc-B21 + */ + +#include + +__FAR__ char configPkg__dummy__; + +#define __xdc_PKGVERS null +#define __xdc_PKGNAME configPkg +#define __xdc_PKGPREFIX configPkg_ + +#ifdef __xdc_bld_pkg_c__ +#define __stringify(a) #a +#define __local_include(a) __stringify(a) +#include __local_include(__xdc_bld_pkg_c__) +#endif + diff --git a/CCS/mm/Debug/configPkg/package/rel/configPkg.xdc.inc b/CCS/mm/Debug/configPkg/package/rel/configPkg.xdc.inc new file mode 100644 index 0000000..0f839ef --- /dev/null +++ b/CCS/mm/Debug/configPkg/package/rel/configPkg.xdc.inc @@ -0,0 +1,3 @@ +package/package.bld.xml +package/build.cfg +package/package.xdc.inc diff --git a/CCS/mm/Debug/configPkg/package/rel/configPkg.xdc.ninc b/CCS/mm/Debug/configPkg/package/rel/configPkg.xdc.ninc new file mode 100644 index 0000000..e69de29 diff --git a/CCS/mm/Debug/gpiointerrupt.d b/CCS/mm/Debug/gpiointerrupt.d new file mode 100644 index 0000000..b3105cc --- /dev/null +++ b/CCS/mm/Debug/gpiointerrupt.d @@ -0,0 +1,339 @@ +# FIXED + +gpiointerrupt.obj: ../gpiointerrupt.c +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stddef.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h +gpiointerrupt.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/std.h +gpiointerrupt.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/M4F.h +gpiointerrupt.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/std.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +gpiointerrupt.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/xdc.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__prologue.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__epilogue.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__prologue.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Main_Module_GateProxy.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__epilogue.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Memory.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Memory_HeapProxy.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__prologue.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +gpiointerrupt.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h 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+C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/GPIO.h: +../Board.h: +../EK_TM4C123GXL.h: diff --git a/CCS/mm/Debug/gpiointerrupt_EK_TM4C123GXL_TI.map b/CCS/mm/Debug/gpiointerrupt_EK_TM4C123GXL_TI.map new file mode 100644 index 0000000..4b72f1e --- /dev/null +++ b/CCS/mm/Debug/gpiointerrupt_EK_TM4C123GXL_TI.map @@ -0,0 +1,1873 @@ +****************************************************************************** + TI ARM Linker PC v18.12.4 +****************************************************************************** +>> Linked Sat Sep 12 20:41:27 2020 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00" address: 00003489 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + FLASH 00000000 00040000 00007600 00038a00 R X + SRAM 20000000 00008000 00001b42 000064be RW X + + +SEGMENT ALLOCATION MAP + +run origin load origin length init length attrs members +---------- ----------- ---------- ----------- ----- ------- +00000000 00000000 00007608 00007608 r-x + 00000000 00000000 0000003c 0000003c r-- .resetVecs + 00000040 00000040 00005442 00005442 r-x .text + 00005484 00005484 00001f5a 00001f5a r-- .const + 000073e0 000073e0 00000228 00000228 r-- .cinit +20000000 20000000 00001b48 00000000 rw- + 20000000 20000000 00000360 00000000 rw- .vecs + 20000360 20000360 00001088 00000000 rw- .bss + 200013e8 200013e8 0000045a 00000000 rw- .data + 20001848 20001848 00000300 00000000 rw- .stack + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.text 0 00000040 00005442 + 00000040 00000430 sysbios.aem4f : BIOS.obj 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(.const:xdc_runtime_Log_L_error__C) + 0000737c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Memory_defaultHeapInstance__C) + 00007380 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_execImpl__C) + 00007384 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_maxPasses__C) + 00007388 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_sfxnRts__C) + 0000738c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_sfxnTab__C) + 00007390 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_SysMin_bufSize__C) + 00007394 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_SysMin_outputFunc__C) + 00007398 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_Module__gateObj__C) + 0000739c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_abortFxn__C) + 000073a0 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_exitFxn__C) + 000073a4 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_extendFxn__C) + 000073a8 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_maxAtexitHandlers__C) + 000073ac 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_charTab__C) + 000073b0 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nameEmpty__C) + 000073b4 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nameStatic__C) + 000073b8 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nameUnknown__C) + 000073bc 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nodeTab__C) + 000073c0 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_visitRopeFxn__C) + 000073c4 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_Module__id__C) + 000073c6 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_hal_Hwi_Module__id__C) + 000073c8 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_heaps_HeapMem_Module__id__C) + 000073ca 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_Module__id__C) + 000073cc 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Core_Module__id__C) + 000073ce 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__loggerDefined__C) + 000073d0 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_maxDepth__C) + 000073d2 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Memory_Module__id__C) + 000073d4 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_SysMin_flushAtExit__C) + 000073d6 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_charCnt__C) + 000073d8 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_isLoaded__C) + 000073da 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_registryModsLastId__C) + 000073dc 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_unnamedModsLastId__C) + +.cinit 0 000073e0 00000228 + 000073e0 000001f1 (.cinit..data.load) [load image, compression = lzss] + 000075d1 00000003 --HOLE-- [fill = 0] + 000075d4 0000000c (__TI_handler_table) + 000075e0 00000008 (.cinit..bss.load) [load image, compression = zero_init] + 000075e8 00000008 (.cinit..vecs.load) [load image, compression = zero_init] + 000075f0 00000018 (__TI_cinit_table) + +.init_array +* 0 00000000 00000000 UNINITIALIZED + +.resetVecs +* 0 00000000 0000003c + 00000000 0000003c gpiointerrupt_pem4f.oem4f (.resetVecs) + +.bss 0 20000360 00001088 UNINITIALIZED + 20000360 00000600 gpiointerrupt_pem4f.oem4f (.bss:taskStackSection) + 20000960 00000400 (.common:ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A) + 20000d60 00000360 (.common:ti_sysbios_family_arm_m3_Hwi_dispatchTable) + 200010c0 00000120 rtsv7M4_T_le_v4SPD16_eabi.lib : trgmsg.c.obj (.bss:_CIOBUF_) + 200011e0 000000cc (.common:uartTivaObjects) + 200012ac 00000090 drivers_tivaware.aem4f : GPIOTiva.oem4f (.bss:gpioCallbackInfo) + 2000133c 00000080 (.common:xdc_runtime_SysMin_Module_State_0_outbuf__A) + 200013bc 00000020 (.common:uartTivaRingBuffer) + 200013dc 00000008 (.common:parmbuf) + 200013e4 00000004 (.common:gpioInterruptVectors) + +.data 0 200013e8 0000045a UNINITIALIZED + 200013e8 00000098 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Object__table__V) + 20001480 00000080 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Swi_Module_State_0_readyQ__A) + 20001500 00000080 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module_State_0_readyQ__A) + 20001580 00000044 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module__state__V) + 200015c4 00000040 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Object__table__V) + 20001604 00000038 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateMutex_Object__table__V) + 2000163c 00000034 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module__state__V) + 20001670 00000030 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A) + 200016a0 00000030 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Swi_Object__table__V) + 200016d0 0000002c gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Clock_Module__state__V) + 200016fc 00000024 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_BIOS_Module__state__V) + 20001720 0000001c gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Swi_Module__state__V) + 2000173c 00000018 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A) + 20001754 00000018 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Object__table__V) + 2000176c 00000018 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_heaps_HeapMem_Object__table__V) + 20001784 00000014 EK_TM4C123GXL.obj (.data:gpioPinConfigs) + 20001798 0000000c gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Module__state__V) + 200017a4 0000000c gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_SysMin_Module__state__V) + 200017b0 00000008 rtsv7M4_T_le_v4SPD16_eabi.lib : _lock.c.obj (.data:$O1$$) + 200017b8 00000008 EK_TM4C123GXL.obj (.data:gpioCallbackFunctions) + 200017c0 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module__root__V) + 200017c8 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateHwi_Module__root__V) + 200017d0 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateMutex_Module__root__V) + 200017d8 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_heaps_HeapMem_Module__root__V) + 200017e0 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Clock_Module__root__V) + 200017e8 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Queue_Module__root__V) + 200017f0 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Semaphore_Module__root__V) + 200017f8 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Registry_Module__state__V) + 20001800 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Startup_Module__state__V) + 20001808 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_System_Module_State_0_atexitHandlers__A) + 20001810 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_System_Module__state__V) + 20001818 00000005 drivers_tivaware.aem4f : GPIOTiva.oem4f (.data) + 2000181d 00000001 --HOLE-- + 2000181e 00000002 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A) + 20001820 00000004 drivers_tivaware.aem4f : UART.oem4f (.data) + 20001824 00000004 gpiointerrupt.obj (.data) + 20001828 00000004 rtsv7M4_T_le_v4SPD16_eabi.lib : stkdepth_vars.c.obj (.data) + 2000182c 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A) + 20001830 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A) + 20001834 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateHwi_Object__table__V) + 20001838 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module_State_0_idleTask__A) + 2000183c 00000004 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Memory_Module__state__V) + 20001840 00000002 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Error_Module__state__V) + +.stack 0 20001848 00000300 UNINITIALIZED + 20001848 00000300 --HOLE-- + +.bootVecs +* 0 00000000 00000008 DSECT + 00000000 00000008 boot.aem4f : boot.oem4f (.bootVecs) + +.vecs 0 20000000 00000360 UNINITIALIZED + 20000000 00000360 gpiointerrupt_pem4f.oem4f (.vecs) + +xdc.meta 0 00000000 000000fb COPY SECTION + 00000000 000000fb gpiointerrupt_pem4f.oem4f (xdc.meta) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + .\ + EK_TM4C123GXL.obj 156 68 264 + gpiointerrupt.obj 272 0 4 + +--+----------------------------+-------+---------+---------+ + Total: 428 68 268 + + C:\Users\zachr\workspace_v9\gpiointerrupt_EK_TM4C123GXL_TI\Debug\configPkg\package\cfg\ + gpiointerrupt_pem4f.oem4f 1790 7566 5476 + +--+----------------------------+-------+---------+---------+ + Total: 1790 7566 5476 + + C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/ccs/Debug/driverlib.lib + gpio.obj 584 144 0 + uart.obj 226 0 0 + sysctl.obj 52 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 862 144 0 + + C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_tivaware.aem4f + UARTTiva.oem4f 2262 116 0 + GPIOTiva.oem4f 892 156 153 + UART.oem4f 148 36 4 + RingBuf.oem4f 164 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 3466 308 157 + + C:\Users\zachr\workspace_v9\gpiointerrupt_EK_TM4C123GXL_TI\src\sysbios\sysbios.aem4f + BIOS.obj 8572 0 0 + m3_Hwi_asm.obj 314 0 0 + m3_TaskSupport_asm.obj 180 0 0 + m3_Hwi_asm_switch.obj 118 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 9184 0 0 + + C:\ti\ccs930\ccs\tools\compiler\ti-cgt-arm_18.12.4.LTS\lib\rtsv7M4_T_le_v4SPD16_eabi.lib + trgmsg.c.obj 108 0 288 + memcpy_t2.asm.obj 156 0 0 + memset_t2.asm.obj 122 0 0 + copy_decompress_lzss.c.obj 104 0 0 + hostwrite.c.obj 88 0 0 + cpy_tbl.c.obj 76 0 0 + u_divt2.asm.obj 64 0 0 + _lock.c.obj 26 0 8 + args_main.c.obj 24 0 0 + strlen.c.obj 20 0 0 + copy_decompress_none.c.obj 14 0 0 + copy_zero_init.c.obj 12 0 0 + hostopen.c.obj 0 0 8 + exit.c.obj 4 0 0 + stkdepth_vars.c.obj 0 0 4 + div0.asm.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 820 0 308 + + C:\ti\tirtos_tivac_2_16_00_08\packages\ti\tirtos\utils\lib\release\ti.tirtos.utils.aem4f + UARTMon.oem4f 186 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 186 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\catalog\arm\cortexm4\tiva\ce\lib\Boot.aem4f + Boot_sysctl.oem4f 262 0 0 + Boot.oem4f 152 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 414 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\auto_init.aem4f + auto_init.oem4f 160 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 160 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\boot.aem4f + boot.oem4f 88 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 88 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\ti.targets.arm.rtsarm.aem4f + System.oem4f 1255 0 0 + Text.oem4f 672 0 0 + Error.oem4f 524 0 0 + Core-mem.oem4f 358 0 0 + Startup.oem4f 328 0 0 + SysMin.oem4f 248 0 0 + Core-smem.oem4f 204 0 0 + Memory.oem4f 176 0 0 + Assert.oem4f 84 0 0 + Core-params.oem4f 70 0 0 + Core-label.oem4f 52 0 0 + Registry.oem4f 32 0 0 + Gate.oem4f 28 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 4031 0 0 + + Stack: 0 0 768 + Linker Generated: 0 549 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 21429 8635 6977 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000075f0 records: 3, size/record: 8, table size: 24 + .data: load addr=000073e0, load size=000001f1 bytes, run addr=200013e8, run size=0000045a bytes, compression=lzss + .bss: load addr=000075e0, load size=00000008 bytes, run addr=20000360, run size=00001088 bytes, compression=zero_init + .vecs: load addr=000075e8, load size=00000008 bytes, run addr=20000000, run size=00000360 bytes, compression=zero_init + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 000075d4 records: 3, size/record: 4, table size: 12 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + index: 2, handler: __TI_zero_init + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +address name +------- ---- +00000d35 C$$EXIT +0000424b C$$IO$$ +0000454d EK_TM4C123GXL_initGPIO +00003fa9 EK_TM4C123GXL_initGeneral +00004821 EK_TM4C123GXL_initUART +00004901 GPIODirModeSet +000029a3 GPIOIntClear +0000529d GPIOIntEnable +00005239 GPIOIntStatus +000035e9 GPIOIntTypeSet +00001291 GPIOPadConfigSet +00003b45 GPIOPinConfigure +00003693 GPIOPinRead +000050e5 GPIOPinTypeGPIOInput +000050f7 GPIOPinTypeUART +0000511b GPIOPinWrite +00007240 GPIOTiva_config +0000457d GPIO_enableInt +00002ff1 GPIO_hwiIntFxn +00002775 GPIO_init +00003741 GPIO_setCallback +00000ff5 GPIO_setConfig +00003791 GPIO_toggle +000037e1 GPIO_write +000034e1 HOSTwrite +00005109 RingBuf_construct +00003fe9 RingBuf_get +000052a9 RingBuf_peek +00003cb1 RingBuf_put +UNDEFED SHT$$INIT_ARRAY$$Base +UNDEFED SHT$$INIT_ARRAY$$Limit +00004371 SysCtlPeripheralEnable +00005389 UARTCharGet +00005247 UARTCharGetNonBlocking +00005393 UARTCharPut +00005255 UARTCharPutNonBlocking +00003ee1 UARTConfigSetExpClk +00004d31 UARTDisable +00005067 UARTEnable +00005411 UARTFIFOLevelSet +000052b5 UARTFlowControlSet +00000bbd UARTIntClear +0000539d UARTIntDisable +000053d9 UARTIntEnable +000053a7 UARTIntStatus +00001ead UARTMon_taskFxn +00005417 UARTRxErrorClear +000053e1 UARTRxErrorGet +000039c1 UARTTiva_close +00002801 UARTTiva_control +00006fa0 UARTTiva_fxnTable +000052c1 UARTTiva_init +000007bd UARTTiva_open +00004029 UARTTiva_read +00004339 UARTTiva_readCancel +000023eb UARTTiva_readPolling +0000251d UARTTiva_write +00003831 UARTTiva_writeCancel +00003f65 UARTTiva_writePolling +00004f5d UART_Params_init +000071c8 UART_config +00006ff0 UART_defaultParams +000041e5 UART_init +000045ad UART_open +000053b1 UART_read +000053bb UART_write +00000000 __ASM__ +200010c0 __CIOBUF_ +00000079 __ISA__ +0000008c __PLAT__ +20001b48 __STACK_END +00000300 __STACK_SIZE +000000ad __TARG__ +000075f0 __TI_CINIT_Base +00007608 __TI_CINIT_Limit +000075d4 __TI_Handler_Table_Base +000075e0 __TI_Handler_Table_Limit +00002175 __TI_auto_init +00002f21 __TI_decompress_lzss +00005263 __TI_decompress_none +ffffffff __TI_pprof_out_hndl +ffffffff __TI_prof_data_size +ffffffff __TI_prof_data_start +000043a5 __TI_readmsg +000073e0 __TI_static_base__ +0000421d __TI_writemsg +000052e5 __TI_zero_init +000000d3 __TRDR__ +00002483 __aeabi_idiv0 +00002483 __aeabi_ldiv0 +00002ba7 __aeabi_memclr +00002ba7 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ti_sysbios_family_arm_m3_TaskSupport_swap__E + 0x4fd5 + + + + ti_catalog_arm_cortexm4_tiva_ce_Boot_sysCtlClockSet__E + 0x2485 + + + + ti_catalog_arm_cortexm4_tiva_ce_Boot_sysCtlClockSetI__I + 0x15e1 + + + + ti_catalog_arm_cortexm4_tiva_ce_Boot_sysCtlDelayI__I + 0x541d + + + + xdc_runtime_Assert_raise__I + 0x36ed + + + + xdc_runtime_Core_deleteObject__I + 0x2f89 + + + + xdc_runtime_Core_createObject__I + 0x16e1 + + + + xdc_runtime_Core_constructObject__I + 0x1b9d + + + + xdc_runtime_Core_assignLabel__I + 0x44b1 + + + + xdc_runtime_Core_assignParams__I + 0x3cf7 + + + + xdc_runtime_Error_getSite__E + 0x33cd + + + + xdc_runtime_Error_raiseX__E + 0x4e1d + + + + xdc_runtime_Error_print__E + 0x2e49 + + + + xdc_runtime_Error_init__E + 0x5359 + + + + xdc_runtime_Error_check__E + 0x5009 + + + + xdc_runtime_Error_policyDefault__E + 0x13c1 + + + + xdc_runtime_Error_setX__E + 0x3e15 + + + + xdc_runtime_Gate_leaveSystem__E + 0x51e9 + + + + xdc_runtime_Gate_enterSystem__E + 0x5365 + + + + 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+ ti_sysbios_hal_Hwi_HwiProxy_restore__E + 0x5431 + + + ti_sysbios_hal_Hwi_HwiProxy_switchFromBootStack__E + 0x50a9 + + + ti_sysbios_hal_Hwi_HwiProxy_disableInterrupt__E + 0x3bd9 + + + ti_sysbios_hal_Hwi_HwiProxy_enableInterrupt__E + 0x3c21 + + + ti_sysbios_heaps_HeapMem_Module_GateProxy_query__E + 0x5469 + + + ti_sysbios_knl_Clock_TimerProxy_startup__E + 0x40a9 + + + ti_sysbios_knl_Task_SupportProxy_start__E + 0x4641 + + + ti_sysbios_knl_Task_SupportProxy_swap__E + 0x4fd5 + + + ti_sysbios_knl_Task_SupportProxy_checkStack__E + 0x5319 + + + xdc_runtime_Main_Module_GateProxy_query__E + 0x5461 + + + xdc_runtime_System_Module_GateProxy_query__E + 0x5461 + + + xdc_runtime_System_SupportProxy_abort__E + 0x47c1 + + + xdc_runtime_System_SupportProxy_exit__E + 0x4e55 + + + xdc_runtime_System_SupportProxy_flush__E + 0x3e59 + + + xdc_runtime_System_SupportProxy_putch__E + 0x42c9 + + + xdc_runtime_System_SupportProxy_ready__E + 0x5209 + + + osi_start + 0x5179 + + + osi_TaskDisable + 0x51d9 + + + ti_sysbios_hal_Hwi_switchFromBootStack__E + 0x50a9 + + + ti_sysbios_hal_Hwi_disableInterrupt__E + 0x3bd9 + + + ti_sysbios_hal_Hwi_enableInterrupt__E + 0x3c21 + + + ti_sysbios_hal_Hwi_getStackInfo__E + 0x3d89 + + + ti_sysbios_hal_Hwi_startup__E + 0x5401 + + + xdc_runtime_System_abortStd__E + 0xd35 + + + xdc_runtime_System_exitStd__E + 0xd35 + + + xdc_runtime_System_flush__E + 0x3e59 + + + Link successful + diff --git a/CCS/mm/Debug/launchpad.asm b/CCS/mm/Debug/launchpad.asm new file mode 100644 index 0000000..78971c2 --- /dev/null +++ b/CCS/mm/Debug/launchpad.asm @@ -0,0 +1,2316 @@ +;****************************************************************************** +;* TI ARM G3 C/C++ Codegen PC v18.12.4.LTS * +;* Date/Time created: Sat Sep 19 20:39:24 2020 * +;****************************************************************************** + .compiler_opts --abi=eabi --arm_vmrs_si_workaround=off --code_state=16 --diag_wrap=off --embedded_constants=on --endian=little --float_support=FPv4SPD16 --hll_source=on --object_format=elf --silicon_version=7M4 --symdebug:dwarf --symdebug:dwarf_version=3 --unaligned_access=on + .thumb + +$C$DW$CU .dwtag DW_TAG_compile_unit + .dwattr $C$DW$CU, DW_AT_name("../lib/launchpad.c") + .dwattr $C$DW$CU, DW_AT_producer("TI TI ARM G3 C/C++ Codegen PC v18.12.4.LTS Copyright (c) 1996-2018 Texas Instruments Incorporated") + .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + .dwattr $C$DW$CU, DW_AT_comp_dir("C:\Users\zachr\workspace_v9\mm\Debug") +$C$DW$1 .dwtag DW_TAG_variable + .dwattr $C$DW$1, DW_AT_name("_ftable") + .dwattr $C$DW$1, DW_AT_TI_symbol_name("_ftable") + .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$170) + .dwattr $C$DW$1, DW_AT_declaration + .dwattr $C$DW$1, DW_AT_external + .dwattr $C$DW$1, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h") + .dwattr $C$DW$1, DW_AT_decl_line(0xcf) + .dwattr $C$DW$1, DW_AT_decl_column(0x1a) + + +$C$DW$2 .dwtag DW_TAG_subprogram + .dwattr $C$DW$2, DW_AT_name("setvbuf") + .dwattr $C$DW$2, DW_AT_TI_symbol_name("setvbuf") + .dwattr $C$DW$2, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$2, DW_AT_declaration + .dwattr $C$DW$2, DW_AT_external + .dwattr $C$DW$2, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h") + .dwattr $C$DW$2, DW_AT_decl_line(0xe8) + .dwattr $C$DW$2, DW_AT_decl_column(0x1d) +$C$DW$3 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$3, DW_AT_type(*$C$DW$T$69) + +$C$DW$4 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$4, DW_AT_type(*$C$DW$T$72) + +$C$DW$5 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$5, DW_AT_type(*$C$DW$T$10) + +$C$DW$6 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$6, DW_AT_type(*$C$DW$T$73) + + .dwendtag $C$DW$2 + +; C:\ti\ccs930\ccs\tools\compiler\ti-cgt-arm_18.12.4.LTS\bin\armacpia.exe -@C:\\Users\\zachr\\AppData\\Local\\Temp\\{878C3537-347E-4247-9E95-44051B68F7EF} + .sect ".text:launchpad_init" + .clink + .thumbfunc launchpad_init + .thumb + .global launchpad_init + +$C$DW$7 .dwtag DW_TAG_subprogram + .dwattr $C$DW$7, DW_AT_name("launchpad_init") + .dwattr $C$DW$7, DW_AT_low_pc(launchpad_init) + .dwattr $C$DW$7, DW_AT_high_pc(0x00) + .dwattr $C$DW$7, DW_AT_TI_symbol_name("launchpad_init") + .dwattr $C$DW$7, DW_AT_external + .dwattr $C$DW$7, DW_AT_TI_begin_file("../lib/launchpad.c") + .dwattr $C$DW$7, DW_AT_TI_begin_line(0x09) + .dwattr $C$DW$7, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$7, DW_AT_decl_file("../lib/launchpad.c") + .dwattr $C$DW$7, DW_AT_decl_line(0x09) + .dwattr $C$DW$7, DW_AT_decl_column(0x06) + .dwattr $C$DW$7, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/launchpad.c",line 9,column 27,is_stmt,address launchpad_init,isa 1 + + .dwfde $C$DW$CIE, launchpad_init +;---------------------------------------------------------------------- +; 9 | void launchpad_init(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: launchpad_init * +;* * +;* Regs Modified : A1,A2,A3,A4,V1,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2, * +;* D2_hi,D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7, * +;* D7_hi,FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V1,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2, * +;* D2_hi,D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7, * +;* D7_hi,FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 8 Save = 8 byte * +;***************************************************************************** +launchpad_init: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {V1, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 4, -8 + .dwpsn file "../lib/launchpad.c",line 10,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 10 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |10| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |10| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |10| + MOV A2, A1 ; [DPU_V7M3_PIPE] |10| + LDR A1, $C$CON2 ; [DPU_V7M3_PIPE] |10| +$C$DW$8 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$8, DW_AT_low_pc(0x00) + .dwattr $C$DW$8, DW_AT_TI_call + .dwattr $C$DW$8, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |10| + ; CALL OCCURS {} ; [] |10| + .dwpsn file "../lib/launchpad.c",line 11,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 11 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |11| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |11| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |11| + MOV A2, A1 ; [DPU_V7M3_PIPE] |11| + LDR A1, $C$CON3 ; [DPU_V7M3_PIPE] |11| +$C$DW$9 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$9, DW_AT_low_pc(0x00) + .dwattr $C$DW$9, DW_AT_TI_call + .dwattr $C$DW$9, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |11| + ; CALL OCCURS {} ; [] |11| + .dwpsn file "../lib/launchpad.c",line 12,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 12 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); +; 13 | // Port F +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |12| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |12| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |12| + MOV A2, A1 ; [DPU_V7M3_PIPE] |12| + LDR A1, $C$CON4 ; [DPU_V7M3_PIPE] |12| +$C$DW$10 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$10, DW_AT_low_pc(0x00) + .dwattr $C$DW$10, DW_AT_TI_call + .dwattr $C$DW$10, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |12| + ; CALL OCCURS {} ; [] |12| + .dwpsn file "../lib/launchpad.c",line 14,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 14 | ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, 0xE); +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |14| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |14| + LDR A1, [A1, #60] ; [DPU_V7M3_PIPE] |14| + MOV A3, A1 ; [DPU_V7M3_PIPE] |14| + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |14| + MOVS A2, #14 ; [DPU_V7M3_PIPE] |14| +$C$DW$11 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$11, DW_AT_low_pc(0x00) + .dwattr $C$DW$11, DW_AT_TI_call + .dwattr $C$DW$11, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |14| + ; CALL OCCURS {} ; [] |14| + .dwpsn file "../lib/launchpad.c",line 15,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 15 | ROM_GPIOPinTypeGPIOInput(GPIO_PORTF_BASE, 0x11); +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |15| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |15| + LDR A1, [A1, #56] ; [DPU_V7M3_PIPE] |15| + MOV A3, A1 ; [DPU_V7M3_PIPE] |15| + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |15| + MOVS A2, #17 ; [DPU_V7M3_PIPE] |15| +$C$DW$12 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$12, DW_AT_low_pc(0x00) + .dwattr $C$DW$12, DW_AT_TI_call + .dwattr $C$DW$12, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |15| + ; CALL OCCURS {} ; [] |15| + .dwpsn file "../lib/launchpad.c",line 16,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 16 | ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, 0x11, GPIO_STRENGTH_2MA, +; 17 | GPIO_PIN_TYPE_STD_WPU); +; 18 | // UART +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |16| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |16| + LDR A1, [A1, #20] ; [DPU_V7M3_PIPE] |16| + MOV V1, A1 ; [DPU_V7M3_PIPE] |16| + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |16| + MOVS A2, #17 ; [DPU_V7M3_PIPE] |16| + MOVS A3, #1 ; [DPU_V7M3_PIPE] |16| + MOVS A4, #10 ; [DPU_V7M3_PIPE] |16| +$C$DW$13 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$13, DW_AT_low_pc(0x00) + .dwattr $C$DW$13, DW_AT_TI_call + .dwattr $C$DW$13, DW_AT_TI_indirect + + BLX V1 ; [DPU_V7M3_PIPE] |16| + ; CALL OCCURS {} ; [] |16| + .dwpsn file "../lib/launchpad.c",line 19,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 19 | ROM_GPIOPinConfigure(GPIO_PA0_U0RX); +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |19| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |19| + LDR A1, [A1, #104] ; [DPU_V7M3_PIPE] |19| + MOV A2, A1 ; [DPU_V7M3_PIPE] |19| + MOVS A1, #1 ; [DPU_V7M3_PIPE] |19| +$C$DW$14 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$14, DW_AT_low_pc(0x00) + .dwattr $C$DW$14, DW_AT_TI_call + .dwattr $C$DW$14, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |19| + ; CALL OCCURS {} ; [] |19| + .dwpsn file "../lib/launchpad.c",line 20,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 20 | ROM_GPIOPinConfigure(GPIO_PA1_U0TX); +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |20| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |20| + LDR A1, [A1, #104] ; [DPU_V7M3_PIPE] |20| + MOV A2, A1 ; [DPU_V7M3_PIPE] |20| + MOV A1, #1025 ; [DPU_V7M3_PIPE] |20| +$C$DW$15 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$15, DW_AT_low_pc(0x00) + .dwattr $C$DW$15, DW_AT_TI_call + .dwattr $C$DW$15, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |20| + ; CALL OCCURS {} ; [] |20| +;* --------------------------------------------------------------------------* + .dwpsn file "../lib/launchpad.c",line 21,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 21 | ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_1 | GPIO_PIN_0); +;---------------------------------------------------------------------- + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |21| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |21| + LDR A1, [A1, #84] ; [DPU_V7M3_PIPE] |21| + MOVS A2, #3 ; [DPU_V7M3_PIPE] |21| + MOV A3, A1 ; [DPU_V7M3_PIPE] |21| + MOV A1, #1073758208 ; [DPU_V7M3_PIPE] |21| +$C$DW$16 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$16, DW_AT_low_pc(0x00) + .dwattr $C$DW$16, DW_AT_TI_call + .dwattr $C$DW$16, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |21| + ; CALL OCCURS {} ; [] |21| + .dwpsn file "../lib/launchpad.c",line 22,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 22 | ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200, +; 23 | UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | +; 24 | UART_CONFIG_PAR_NONE); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |22| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |22| + LDR A1, [A1, #96] ; [DPU_V7M3_PIPE] |22| +$C$DW$17 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$17, DW_AT_low_pc(0x00) + .dwattr $C$DW$17, DW_AT_TI_call + .dwattr $C$DW$17, DW_AT_TI_indirect + + BLX A1 ; [DPU_V7M3_PIPE] |22| + ; CALL OCCURS {} ; [] |22| + MOV A2, A1 ; [DPU_V7M3_PIPE] |22| + LDR A1, $C$CON7 ; [DPU_V7M3_PIPE] |22| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |22| + LDR A1, [A1, #20] ; [DPU_V7M3_PIPE] |22| + MOV V1, A1 ; [DPU_V7M3_PIPE] |22| + LDR A1, $C$CON8 ; [DPU_V7M3_PIPE] |22| + MOV A3, #115200 ; [DPU_V7M3_PIPE] |22| + MOVS A4, #96 ; [DPU_V7M3_PIPE] |22| +$C$DW$18 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$18, DW_AT_low_pc(0x00) + .dwattr $C$DW$18, DW_AT_TI_call + .dwattr $C$DW$18, DW_AT_TI_indirect + + BLX V1 ; [DPU_V7M3_PIPE] |22| + ; CALL OCCURS {} ; [] |22| + .dwpsn file "../lib/launchpad.c",line 25,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 25 | ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8); +;---------------------------------------------------------------------- + LDR A1, $C$CON7 ; [DPU_V7M3_PIPE] |25| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |25| + LDR A1, [A1, #12] ; [DPU_V7M3_PIPE] |25| + MOV A4, A1 ; [DPU_V7M3_PIPE] |25| + LDR A1, $C$CON8 ; [DPU_V7M3_PIPE] |25| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |25| + MOVS A3, #0 ; [DPU_V7M3_PIPE] |25| +$C$DW$19 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$19, DW_AT_low_pc(0x00) + .dwattr $C$DW$19, DW_AT_TI_call + .dwattr $C$DW$19, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |25| + ; CALL OCCURS {} ; [] |25| + .dwpsn file "../lib/launchpad.c",line 26,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 26 | ROM_UARTFIFOEnable(UART0_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON7 ; [DPU_V7M3_PIPE] |26| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |26| + LDR A1, [A1, #96] ; [DPU_V7M3_PIPE] |26| + MOV A2, A1 ; [DPU_V7M3_PIPE] |26| + LDR A1, $C$CON8 ; [DPU_V7M3_PIPE] |26| +$C$DW$20 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$20, DW_AT_low_pc(0x00) + .dwattr $C$DW$20, DW_AT_TI_call + .dwattr $C$DW$20, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |26| + ; CALL OCCURS {} ; [] |26| + .dwpsn file "../lib/launchpad.c",line 27,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 27 | ROM_UARTEnable(UART0_BASE); +; 28 | // Disable buffered output +;---------------------------------------------------------------------- + LDR A1, $C$CON7 ; [DPU_V7M3_PIPE] |27| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |27| + LDR A1, [A1, #28] ; [DPU_V7M3_PIPE] |27| + MOV A2, A1 ; [DPU_V7M3_PIPE] |27| + LDR A1, $C$CON8 ; [DPU_V7M3_PIPE] |27| +$C$DW$21 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$21, DW_AT_low_pc(0x00) + .dwattr $C$DW$21, DW_AT_TI_call + .dwattr $C$DW$21, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |27| + ; CALL OCCURS {} ; [] |27| + .dwpsn file "../lib/launchpad.c",line 29,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 29 | setvbuf(stdout, NULL, _IONBF, 0); +;---------------------------------------------------------------------- + LDR A1, $C$CON9 ; [DPU_V7M3_PIPE] |29| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |29| + MOVS A3, #4 ; [DPU_V7M3_PIPE] |29| + MOVS A4, #0 ; [DPU_V7M3_PIPE] |29| +$C$DW$22 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$22, DW_AT_low_pc(0x00) + .dwattr $C$DW$22, DW_AT_name("setvbuf") + .dwattr $C$DW$22, DW_AT_TI_call + + BL setvbuf ; [DPU_V7M3_PIPE] |29| + ; CALL OCCURS {setvbuf } ; [] |29| + .dwpsn file "../lib/launchpad.c",line 30,column 1,is_stmt,isa 1 +$C$DW$23 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$23, DW_AT_low_pc(0x00) + .dwattr $C$DW$23, DW_AT_TI_return + + POP {V1, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 4 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$7, DW_AT_TI_end_file("../lib/launchpad.c") + .dwattr $C$DW$7, DW_AT_TI_end_line(0x1e) + .dwattr $C$DW$7, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$7 + + .sect ".text:left_switch" + .clink + .thumbfunc left_switch + .thumb + .global left_switch + +$C$DW$24 .dwtag DW_TAG_subprogram + .dwattr $C$DW$24, DW_AT_name("left_switch") + .dwattr $C$DW$24, DW_AT_low_pc(left_switch) + .dwattr $C$DW$24, DW_AT_high_pc(0x00) + .dwattr $C$DW$24, DW_AT_TI_symbol_name("left_switch") + .dwattr $C$DW$24, DW_AT_external + .dwattr $C$DW$24, DW_AT_type(*$C$DW$T$30) + .dwattr $C$DW$24, DW_AT_TI_begin_file("../lib/launchpad.c") + .dwattr $C$DW$24, DW_AT_TI_begin_line(0x20) + .dwattr $C$DW$24, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$24, DW_AT_decl_file("../lib/launchpad.c") + .dwattr $C$DW$24, DW_AT_decl_line(0x20) + .dwattr $C$DW$24, DW_AT_decl_column(0x06) + .dwattr $C$DW$24, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/launchpad.c",line 32,column 24,is_stmt,address left_switch,isa 1 + + .dwfde $C$DW$CIE, left_switch +;---------------------------------------------------------------------- +; 32 | bool left_switch(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: left_switch * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +left_switch: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/launchpad.c",line 33,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 33 | return !ROM_GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_4); +;---------------------------------------------------------------------- + LDR A1, $C$CON10 ; [DPU_V7M3_PIPE] |33| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |33| + LDR A1, [A1, #44] ; [DPU_V7M3_PIPE] |33| + MOV A3, A1 ; [DPU_V7M3_PIPE] |33| + LDR A1, $C$CON11 ; [DPU_V7M3_PIPE] |33| + MOVS A2, #16 ; [DPU_V7M3_PIPE] |33| +$C$DW$25 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$25, DW_AT_low_pc(0x00) + .dwattr $C$DW$25, DW_AT_TI_call + .dwattr $C$DW$25, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |33| + ; CALL OCCURS {} ; [] |33| + MOVS A4, #0 ; [DPU_V7M3_PIPE] |33| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |33| + MOVS A3, #0 ; [DPU_V7M3_PIPE] |33| + CBZ A1, ||$C$L1|| ; [] + ; BRANCHCC OCCURS {||$C$L1||} ; [] |33| +;* --------------------------------------------------------------------------* + MOVS A3, #1 ; [DPU_V7M3_PIPE] |33| +;* --------------------------------------------------------------------------* +||$C$L1||: + CBNZ A3, ||$C$L2|| ; [] + ; BRANCHCC OCCURS {||$C$L2||} ; [] |33| +;* --------------------------------------------------------------------------* + MOVS A2, #1 ; [DPU_V7M3_PIPE] |33| +;* --------------------------------------------------------------------------* +||$C$L2||: + CBZ A2, ||$C$L3|| ; [] + ; BRANCHCC OCCURS {||$C$L3||} ; [] |33| +;* --------------------------------------------------------------------------* + MOVS A4, #1 ; [DPU_V7M3_PIPE] |33| +;* --------------------------------------------------------------------------* +||$C$L3||: + MOV A1, A4 ; [DPU_V7M3_PIPE] |33| + .dwpsn file "../lib/launchpad.c",line 34,column 1,is_stmt,isa 1 +$C$DW$26 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$26, DW_AT_low_pc(0x00) + .dwattr $C$DW$26, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$24, DW_AT_TI_end_file("../lib/launchpad.c") + .dwattr $C$DW$24, DW_AT_TI_end_line(0x22) + .dwattr $C$DW$24, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$24 + + .sect ".text:right_switch" + .clink + .thumbfunc right_switch + .thumb + .global right_switch + +$C$DW$27 .dwtag DW_TAG_subprogram + .dwattr $C$DW$27, DW_AT_name("right_switch") + .dwattr $C$DW$27, DW_AT_low_pc(right_switch) + .dwattr $C$DW$27, DW_AT_high_pc(0x00) + .dwattr $C$DW$27, DW_AT_TI_symbol_name("right_switch") + .dwattr $C$DW$27, DW_AT_external + .dwattr $C$DW$27, DW_AT_type(*$C$DW$T$30) + .dwattr $C$DW$27, DW_AT_TI_begin_file("../lib/launchpad.c") + .dwattr $C$DW$27, DW_AT_TI_begin_line(0x24) + .dwattr $C$DW$27, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$27, DW_AT_decl_file("../lib/launchpad.c") + .dwattr $C$DW$27, DW_AT_decl_line(0x24) + .dwattr $C$DW$27, DW_AT_decl_column(0x06) + .dwattr $C$DW$27, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/launchpad.c",line 36,column 25,is_stmt,address right_switch,isa 1 + + .dwfde $C$DW$CIE, right_switch +;---------------------------------------------------------------------- +; 36 | bool right_switch(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: right_switch * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +right_switch: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/launchpad.c",line 37,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 37 | return !ROM_GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_0); +;---------------------------------------------------------------------- + LDR A1, $C$CON12 ; [DPU_V7M3_PIPE] |37| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |37| + LDR A1, [A1, #44] ; [DPU_V7M3_PIPE] |37| + MOV A3, A1 ; [DPU_V7M3_PIPE] |37| + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |37| + MOVS A2, #1 ; [DPU_V7M3_PIPE] |37| +$C$DW$28 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$28, DW_AT_low_pc(0x00) + .dwattr $C$DW$28, DW_AT_TI_call + .dwattr $C$DW$28, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |37| + ; CALL OCCURS {} ; [] |37| + MOVS A4, #0 ; [DPU_V7M3_PIPE] |37| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |37| + MOVS A3, #0 ; [DPU_V7M3_PIPE] |37| + CBZ A1, ||$C$L4|| ; [] + ; BRANCHCC OCCURS {||$C$L4||} ; [] |37| +;* --------------------------------------------------------------------------* + MOVS A3, #1 ; [DPU_V7M3_PIPE] |37| +;* --------------------------------------------------------------------------* +||$C$L4||: + CBNZ A3, ||$C$L5|| ; [] + ; BRANCHCC OCCURS {||$C$L5||} ; [] |37| +;* --------------------------------------------------------------------------* + MOVS A2, #1 ; [DPU_V7M3_PIPE] |37| +;* --------------------------------------------------------------------------* +||$C$L5||: + CBZ A2, ||$C$L6|| ; [] + ; BRANCHCC OCCURS {||$C$L6||} ; [] |37| +;* --------------------------------------------------------------------------* + MOVS A4, #1 ; [DPU_V7M3_PIPE] |37| +;* --------------------------------------------------------------------------* +||$C$L6||: + MOV A1, A4 ; [DPU_V7M3_PIPE] |37| + .dwpsn file "../lib/launchpad.c",line 38,column 1,is_stmt,isa 1 +$C$DW$29 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$29, DW_AT_low_pc(0x00) + .dwattr $C$DW$29, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$27, DW_AT_TI_end_file("../lib/launchpad.c") + .dwattr $C$DW$27, DW_AT_TI_end_line(0x26) + .dwattr $C$DW$27, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$27 + + .sect ".text:led_toggle" + .clink + .thumbfunc led_toggle + .thumb + .global led_toggle + +$C$DW$30 .dwtag DW_TAG_subprogram + .dwattr $C$DW$30, DW_AT_name("led_toggle") + .dwattr $C$DW$30, DW_AT_low_pc(led_toggle) + .dwattr $C$DW$30, DW_AT_high_pc(0x00) + .dwattr $C$DW$30, DW_AT_TI_symbol_name("led_toggle") + .dwattr $C$DW$30, DW_AT_external + .dwattr $C$DW$30, DW_AT_TI_begin_file("../lib/launchpad.c") + .dwattr $C$DW$30, DW_AT_TI_begin_line(0x28) + .dwattr $C$DW$30, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$30, DW_AT_decl_file("../lib/launchpad.c") + .dwattr $C$DW$30, DW_AT_decl_line(0x28) + .dwattr $C$DW$30, DW_AT_decl_column(0x06) + .dwattr $C$DW$30, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/launchpad.c",line 40,column 30,is_stmt,address led_toggle,isa 1 + + .dwfde $C$DW$CIE, led_toggle +$C$DW$31 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$31, DW_AT_name("led") + .dwattr $C$DW$31, DW_AT_TI_symbol_name("led") + .dwattr $C$DW$31, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$31, DW_AT_location[DW_OP_reg0] + + +;***************************************************************************** +;* FUNCTION NAME: led_toggle * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 4 Auto + 4 Save = 8 byte * +;***************************************************************************** +led_toggle: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 +$C$DW$32 .dwtag DW_TAG_variable + .dwattr $C$DW$32, DW_AT_name("led") + .dwattr $C$DW$32, DW_AT_TI_symbol_name("led") + .dwattr $C$DW$32, DW_AT_type(*$C$DW$T$28) + .dwattr $C$DW$32, DW_AT_location[DW_OP_breg13 0] + +;---------------------------------------------------------------------- +; 40 | void led_toggle(uint8_t led) { +;---------------------------------------------------------------------- + STRB A1, [SP, #0] ; [DPU_V7M3_PIPE] |40| + .dwpsn file "../lib/launchpad.c",line 41,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 41 | ROM_GPIOPinWrite(GPIO_PORTF_BASE, led, +; 42 | ~ROM_GPIOPinRead(GPIO_PORTF_BASE, led)); +;---------------------------------------------------------------------- + LDR A1, $C$CON14 ; [DPU_V7M3_PIPE] |41| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |41| + LDRB A2, [SP, #0] ; [DPU_V7M3_PIPE] |41| + LDR A1, [A1, #44] ; [DPU_V7M3_PIPE] |41| + MOV A3, A1 ; [DPU_V7M3_PIPE] |41| + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |41| +$C$DW$33 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$33, DW_AT_low_pc(0x00) + .dwattr $C$DW$33, DW_AT_TI_call + .dwattr $C$DW$33, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |41| + ; CALL OCCURS {} ; [] |41| + LDR A2, $C$CON14 ; [DPU_V7M3_PIPE] |41| + MVNS A1, A1 ; [DPU_V7M3_PIPE] |41| + UXTB A3, A1 ; [DPU_V7M3_PIPE] |41| + LDR A2, [A2, #0] ; [DPU_V7M3_PIPE] |41| + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |41| + LDR A4, [A2, #0] ; [DPU_V7M3_PIPE] |41| + LDRB A2, [SP, #0] ; [DPU_V7M3_PIPE] |41| +$C$DW$34 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$34, DW_AT_low_pc(0x00) + .dwattr $C$DW$34, DW_AT_TI_call + .dwattr $C$DW$34, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |41| + ; CALL OCCURS {} ; [] |41| + .dwpsn file "../lib/launchpad.c",line 43,column 1,is_stmt,isa 1 +$C$DW$35 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$35, DW_AT_low_pc(0x00) + .dwattr $C$DW$35, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$30, DW_AT_TI_end_file("../lib/launchpad.c") + .dwattr $C$DW$30, DW_AT_TI_end_line(0x2b) + .dwattr $C$DW$30, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$30 + + .sect ".text:led_write" + .clink + .thumbfunc led_write + .thumb + .global led_write + +$C$DW$36 .dwtag DW_TAG_subprogram + .dwattr $C$DW$36, DW_AT_name("led_write") + .dwattr $C$DW$36, DW_AT_low_pc(led_write) + .dwattr $C$DW$36, DW_AT_high_pc(0x00) + .dwattr $C$DW$36, DW_AT_TI_symbol_name("led_write") + .dwattr $C$DW$36, DW_AT_external + .dwattr $C$DW$36, DW_AT_TI_begin_file("../lib/launchpad.c") + .dwattr $C$DW$36, DW_AT_TI_begin_line(0x2d) + .dwattr $C$DW$36, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$36, DW_AT_decl_file("../lib/launchpad.c") + .dwattr $C$DW$36, DW_AT_decl_line(0x2d) + .dwattr $C$DW$36, DW_AT_decl_column(0x06) + .dwattr $C$DW$36, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/launchpad.c",line 45,column 41,is_stmt,address led_write,isa 1 + + .dwfde $C$DW$CIE, led_write +$C$DW$37 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$37, DW_AT_name("led") + .dwattr $C$DW$37, DW_AT_TI_symbol_name("led") + .dwattr $C$DW$37, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$37, DW_AT_location[DW_OP_reg0] + +$C$DW$38 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$38, DW_AT_name("value") + .dwattr $C$DW$38, DW_AT_TI_symbol_name("value") + .dwattr $C$DW$38, DW_AT_type(*$C$DW$T$10) + .dwattr $C$DW$38, DW_AT_location[DW_OP_reg1] + + +;***************************************************************************** +;* FUNCTION NAME: led_write * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 4 Auto + 4 Save = 8 byte * +;***************************************************************************** +led_write: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 +$C$DW$39 .dwtag DW_TAG_variable + .dwattr $C$DW$39, DW_AT_name("led") + .dwattr $C$DW$39, DW_AT_TI_symbol_name("led") + .dwattr $C$DW$39, DW_AT_type(*$C$DW$T$28) + .dwattr $C$DW$39, DW_AT_location[DW_OP_breg13 0] + +$C$DW$40 .dwtag DW_TAG_variable + .dwattr $C$DW$40, DW_AT_name("value") + .dwattr $C$DW$40, DW_AT_TI_symbol_name("value") + .dwattr $C$DW$40, DW_AT_type(*$C$DW$T$30) + .dwattr $C$DW$40, DW_AT_location[DW_OP_breg13 1] + +;---------------------------------------------------------------------- +; 45 | void led_write(uint8_t led, bool value) { +;---------------------------------------------------------------------- + STRB A2, [SP, #1] ; [DPU_V7M3_PIPE] |45| + STRB A1, [SP, #0] ; [DPU_V7M3_PIPE] |45| + .dwpsn file "../lib/launchpad.c",line 46,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 46 | ROM_GPIOPinWrite(GPIO_PORTF_BASE, led, value ? led : 0); +;---------------------------------------------------------------------- + LDR A1, $C$CON16 ; [DPU_V7M3_PIPE] |46| + LDR A3, [A1, #0] ; [DPU_V7M3_PIPE] |46| + LDRB A2, [SP, #0] ; [DPU_V7M3_PIPE] |46| + LDRB A1, [SP, #1] ; [DPU_V7M3_PIPE] |46| + LDR A4, [A3, #0] ; [DPU_V7M3_PIPE] |46| + CBZ A1, ||$C$L7|| ; [] + ; BRANCHCC OCCURS {||$C$L7||} ; [] |46| +;* --------------------------------------------------------------------------* + LDRB A3, [SP, #0] ; [DPU_V7M3_PIPE] |46| + B ||$C$L8|| ; [DPU_V7M3_PIPE] |46| + ; BRANCH OCCURS {||$C$L8||} ; [] |46| +;* --------------------------------------------------------------------------* +||$C$L7||: + MOVS A3, #0 ; [DPU_V7M3_PIPE] |46| +;* --------------------------------------------------------------------------* +||$C$L8||: + LDR A1, $C$CON17 ; [DPU_V7M3_PIPE] |46| +$C$DW$41 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$41, DW_AT_low_pc(0x00) + .dwattr $C$DW$41, DW_AT_TI_call + .dwattr $C$DW$41, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |46| + ; CALL OCCURS {} ; [] |46| + .dwpsn file "../lib/launchpad.c",line 47,column 1,is_stmt,isa 1 +$C$DW$42 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$42, DW_AT_low_pc(0x00) + .dwattr $C$DW$42, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$36, DW_AT_TI_end_file("../lib/launchpad.c") + .dwattr $C$DW$36, DW_AT_TI_end_line(0x2f) + .dwattr $C$DW$36, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$36 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:launchpad_init" + .align 4 +||$C$CON1||: .bits 0x1000044,32 + + .align 4 +||$C$CON2||: .bits 0xf0000805,32 + + .align 4 +||$C$CON3||: .bits 0xf0000800,32 + + .align 4 +||$C$CON4||: .bits 0xf0001800,32 + + .align 4 +||$C$CON5||: .bits 0x1000020,32 + + .align 4 +||$C$CON6||: .bits 0x40025000,32 + + .align 4 +||$C$CON7||: .bits 0x1000014,32 + + .align 4 +||$C$CON8||: .bits 0x4000c000,32 + + .align 4 +||$C$CON9||: .bits _ftable+24,32 +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:left_switch" + .align 4 +||$C$CON10||: .bits 0x1000020,32 + + .align 4 +||$C$CON11||: .bits 0x40025000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:right_switch" + .align 4 +||$C$CON12||: .bits 0x1000020,32 + + .align 4 +||$C$CON13||: .bits 0x40025000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:led_toggle" + .align 4 +||$C$CON14||: .bits 0x1000020,32 + + .align 4 +||$C$CON15||: .bits 0x40025000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:led_write" + .align 4 +||$C$CON16||: .bits 0x1000020,32 + + .align 4 +||$C$CON17||: .bits 0x40025000,32 + +;***************************************************************************** +;* UNDEFINED EXTERNAL REFERENCES * +;***************************************************************************** + .global _ftable + .global setvbuf + +;****************************************************************************** +;* BUILD ATTRIBUTES * +;****************************************************************************** + .battr "aeabi", Tag_File, 1, Tag_ABI_PCS_wchar_t(2) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_rounding(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_denormal(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_exceptions(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_number_model(1) + .battr "aeabi", Tag_File, 1, Tag_ABI_enum_size(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_optimization_goals(5) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_optimization_goals(0) + .battr "TI", Tag_File, 1, Tag_Bitfield_layout(2) + .battr "aeabi", Tag_File, 1, Tag_ABI_VFP_args(3) + .battr "TI", Tag_File, 1, Tag_FP_interface(1) + +;****************************************************************************** +;* TYPE INFORMATION * +;****************************************************************************** + +$C$DW$T$21 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) +$C$DW$43 .dwtag DW_TAG_member + .dwattr $C$DW$43, DW_AT_type(*$C$DW$T$14) + .dwattr $C$DW$43, DW_AT_name("__max_align1") + .dwattr $C$DW$43, DW_AT_TI_symbol_name("__max_align1") + .dwattr $C$DW$43, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$43, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$43, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$43, DW_AT_decl_line(0x7a) + .dwattr $C$DW$43, DW_AT_decl_column(0x0c) + +$C$DW$44 .dwtag DW_TAG_member + .dwattr $C$DW$44, DW_AT_type(*$C$DW$T$18) + .dwattr $C$DW$44, DW_AT_name("__max_align2") + .dwattr $C$DW$44, DW_AT_TI_symbol_name("__max_align2") + .dwattr $C$DW$44, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$44, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$44, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$44, DW_AT_decl_line(0x7b) + .dwattr $C$DW$44, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$21, DW_AT_decl_line(0x79) + .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$21 + +$C$DW$T$25 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$25, DW_AT_name("__max_align_t") + .dwattr $C$DW$T$25, DW_AT_type(*$C$DW$T$21) + .dwattr $C$DW$T$25, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$25, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$25, DW_AT_decl_line(0x7c) + .dwattr $C$DW$T$25, DW_AT_decl_column(0x03) + +$C$DW$T$2 .dwtag DW_TAG_unspecified_type + .dwattr $C$DW$T$2, DW_AT_name("void") + +$C$DW$T$3 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$3, DW_AT_type(*$C$DW$T$2) + .dwattr $C$DW$T$3, DW_AT_address_class(0x20) + +$C$DW$T$4 .dwtag DW_TAG_base_type + .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + .dwattr $C$DW$T$4, DW_AT_name("bool") + .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + +$C$DW$T$5 .dwtag DW_TAG_base_type + .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + .dwattr $C$DW$T$5, DW_AT_name("signed char") + .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + +$C$DW$T$46 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$46, DW_AT_name("__int8_t") + .dwattr $C$DW$T$46, DW_AT_type(*$C$DW$T$5) + .dwattr $C$DW$T$46, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$46, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$46, DW_AT_decl_line(0x39) + .dwattr $C$DW$T$46, DW_AT_decl_column(0x16) + +$C$DW$T$47 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$47, DW_AT_name("__int_least8_t") + .dwattr $C$DW$T$47, DW_AT_type(*$C$DW$T$46) + .dwattr $C$DW$T$47, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$47, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$47, DW_AT_decl_line(0x58) + .dwattr $C$DW$T$47, DW_AT_decl_column(0x12) + +$C$DW$T$48 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$48, DW_AT_name("int_least8_t") + .dwattr $C$DW$T$48, DW_AT_type(*$C$DW$T$47) + .dwattr $C$DW$T$48, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$48, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h") + .dwattr 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DW_TAG_typedef + .dwattr $C$DW$T$172, DW_AT_name("__timer_t") + .dwattr $C$DW$T$172, DW_AT_type(*$C$DW$T$171) + .dwattr $C$DW$T$172, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$172, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$172, DW_AT_decl_line(0x4a) + .dwattr $C$DW$T$172, DW_AT_decl_column(0x19) + + +$C$DW$T$24 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$24, DW_AT_name("__va_list_t") + .dwattr $C$DW$T$24, DW_AT_byte_size(0x04) +$C$DW$52 .dwtag DW_TAG_member + .dwattr $C$DW$52, DW_AT_type(*$C$DW$T$3) + .dwattr $C$DW$52, DW_AT_name("__ap") + .dwattr $C$DW$52, DW_AT_TI_symbol_name("__ap") + .dwattr $C$DW$52, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$52, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$52, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$52, DW_AT_decl_line(0x8c) + .dwattr $C$DW$52, DW_AT_decl_column(0x0c) + + .dwattr $C$DW$T$24, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$24, DW_AT_decl_line(0x8b) + .dwattr $C$DW$T$24, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$24 + +$C$DW$T$173 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$173, DW_AT_name("__va_list") + .dwattr $C$DW$T$173, DW_AT_type(*$C$DW$T$24) + .dwattr $C$DW$T$173, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$173, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$173, DW_AT_decl_line(0x8d) + .dwattr $C$DW$T$173, DW_AT_decl_column(0x03) + +$C$DW$T$174 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$174, DW_AT_name("va_list") + .dwattr $C$DW$T$174, DW_AT_type(*$C$DW$T$173) + .dwattr $C$DW$T$174, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$174, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h") + .dwattr $C$DW$T$174, DW_AT_decl_line(0x33) + .dwattr $C$DW$T$174, DW_AT_decl_column(0x13) + + .dwattr $C$DW$CU, DW_AT_language(DW_LANG_C) + +;*************************************************************** +;* DWARF CIE ENTRIES * +;*************************************************************** + +$C$DW$CIE .dwcie 14 + .dwcfi cfa_register, 13 + .dwcfi cfa_offset, 0 + .dwcfi same_value, 4 + .dwcfi same_value, 5 + .dwcfi same_value, 6 + .dwcfi same_value, 7 + .dwcfi same_value, 8 + .dwcfi same_value, 9 + .dwcfi same_value, 10 + .dwcfi same_value, 11 + .dwcfi same_value, 80 + .dwcfi same_value, 81 + .dwcfi same_value, 82 + .dwcfi same_value, 83 + .dwcfi same_value, 84 + .dwcfi same_value, 85 + .dwcfi same_value, 86 + .dwcfi same_value, 87 + .dwcfi same_value, 88 + .dwcfi same_value, 89 + .dwcfi same_value, 90 + .dwcfi same_value, 91 + .dwcfi same_value, 92 + .dwcfi same_value, 93 + .dwcfi same_value, 94 + .dwcfi same_value, 95 + .dwendentry + +;*************************************************************** +;* DWARF REGISTER MAP * +;*************************************************************** + +$C$DW$53 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$53, DW_AT_name("A1") + .dwattr $C$DW$53, DW_AT_location[DW_OP_reg0] + +$C$DW$54 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$54, DW_AT_name("A2") + .dwattr $C$DW$54, DW_AT_location[DW_OP_reg1] + +$C$DW$55 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$55, DW_AT_name("A3") + .dwattr $C$DW$55, DW_AT_location[DW_OP_reg2] + +$C$DW$56 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$56, DW_AT_name("A4") + .dwattr $C$DW$56, DW_AT_location[DW_OP_reg3] + +$C$DW$57 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$57, DW_AT_name("V1") + .dwattr $C$DW$57, DW_AT_location[DW_OP_reg4] + +$C$DW$58 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$58, DW_AT_name("V2") + .dwattr $C$DW$58, DW_AT_location[DW_OP_reg5] + +$C$DW$59 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$59, DW_AT_name("V3") + .dwattr $C$DW$59, DW_AT_location[DW_OP_reg6] + +$C$DW$60 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$60, DW_AT_name("V4") + .dwattr $C$DW$60, DW_AT_location[DW_OP_reg7] + +$C$DW$61 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$61, DW_AT_name("V5") + .dwattr $C$DW$61, DW_AT_location[DW_OP_reg8] + +$C$DW$62 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$62, DW_AT_name("V6") + .dwattr $C$DW$62, DW_AT_location[DW_OP_reg9] + +$C$DW$63 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$63, DW_AT_name("V7") + .dwattr $C$DW$63, DW_AT_location[DW_OP_reg10] + +$C$DW$64 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$64, DW_AT_name("V8") + .dwattr $C$DW$64, DW_AT_location[DW_OP_reg11] + +$C$DW$65 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$65, DW_AT_name("V9") + .dwattr $C$DW$65, DW_AT_location[DW_OP_reg12] + +$C$DW$66 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$66, DW_AT_name("SP") + .dwattr $C$DW$66, DW_AT_location[DW_OP_reg13] + +$C$DW$67 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$67, DW_AT_name("LR") + .dwattr $C$DW$67, DW_AT_location[DW_OP_reg14] + +$C$DW$68 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$68, DW_AT_name("PC") + .dwattr $C$DW$68, DW_AT_location[DW_OP_reg15] + +$C$DW$69 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$69, DW_AT_name("SR") + .dwattr $C$DW$69, DW_AT_location[DW_OP_reg17] + +$C$DW$70 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$70, DW_AT_name("AP") + .dwattr $C$DW$70, DW_AT_location[DW_OP_reg7] + +$C$DW$71 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$71, DW_AT_name("D0") + .dwattr $C$DW$71, DW_AT_location[DW_OP_regx 0x40] + +$C$DW$72 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$72, DW_AT_name("D0_hi") + .dwattr $C$DW$72, DW_AT_location[DW_OP_regx 0x41] + +$C$DW$73 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$73, DW_AT_name("D1") + .dwattr $C$DW$73, DW_AT_location[DW_OP_regx 0x42] + +$C$DW$74 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$74, DW_AT_name("D1_hi") + .dwattr $C$DW$74, DW_AT_location[DW_OP_regx 0x43] + +$C$DW$75 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$75, DW_AT_name("D2") + .dwattr $C$DW$75, DW_AT_location[DW_OP_regx 0x44] + +$C$DW$76 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$76, DW_AT_name("D2_hi") + .dwattr $C$DW$76, DW_AT_location[DW_OP_regx 0x45] + +$C$DW$77 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$77, DW_AT_name("D3") + .dwattr $C$DW$77, DW_AT_location[DW_OP_regx 0x46] + +$C$DW$78 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$78, DW_AT_name("D3_hi") + .dwattr $C$DW$78, DW_AT_location[DW_OP_regx 0x47] + +$C$DW$79 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$79, DW_AT_name("D4") + .dwattr $C$DW$79, DW_AT_location[DW_OP_regx 0x48] + +$C$DW$80 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$80, DW_AT_name("D4_hi") + .dwattr $C$DW$80, DW_AT_location[DW_OP_regx 0x49] + +$C$DW$81 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$81, DW_AT_name("D5") + .dwattr $C$DW$81, DW_AT_location[DW_OP_regx 0x4a] + +$C$DW$82 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$82, DW_AT_name("D5_hi") + .dwattr $C$DW$82, DW_AT_location[DW_OP_regx 0x4b] + +$C$DW$83 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$83, DW_AT_name("D6") + .dwattr $C$DW$83, DW_AT_location[DW_OP_regx 0x4c] + +$C$DW$84 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$84, DW_AT_name("D6_hi") + .dwattr $C$DW$84, DW_AT_location[DW_OP_regx 0x4d] + +$C$DW$85 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$85, DW_AT_name("D7") + .dwattr $C$DW$85, DW_AT_location[DW_OP_regx 0x4e] + +$C$DW$86 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$86, DW_AT_name("D7_hi") + .dwattr $C$DW$86, DW_AT_location[DW_OP_regx 0x4f] + +$C$DW$87 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$87, DW_AT_name("D8") + .dwattr $C$DW$87, DW_AT_location[DW_OP_regx 0x50] + +$C$DW$88 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$88, DW_AT_name("D8_hi") + .dwattr $C$DW$88, DW_AT_location[DW_OP_regx 0x51] + +$C$DW$89 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$89, DW_AT_name("D9") + .dwattr $C$DW$89, DW_AT_location[DW_OP_regx 0x52] + +$C$DW$90 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$90, DW_AT_name("D9_hi") + .dwattr $C$DW$90, DW_AT_location[DW_OP_regx 0x53] + +$C$DW$91 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$91, DW_AT_name("D10") + .dwattr $C$DW$91, DW_AT_location[DW_OP_regx 0x54] + +$C$DW$92 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$92, DW_AT_name("D10_hi") + .dwattr $C$DW$92, DW_AT_location[DW_OP_regx 0x55] + +$C$DW$93 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$93, DW_AT_name("D11") + .dwattr $C$DW$93, DW_AT_location[DW_OP_regx 0x56] + +$C$DW$94 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$94, DW_AT_name("D11_hi") + .dwattr $C$DW$94, DW_AT_location[DW_OP_regx 0x57] + +$C$DW$95 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$95, DW_AT_name("D12") + .dwattr $C$DW$95, DW_AT_location[DW_OP_regx 0x58] + +$C$DW$96 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$96, DW_AT_name("D12_hi") + .dwattr $C$DW$96, DW_AT_location[DW_OP_regx 0x59] + +$C$DW$97 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$97, DW_AT_name("D13") + .dwattr $C$DW$97, DW_AT_location[DW_OP_regx 0x5a] + +$C$DW$98 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$98, DW_AT_name("D13_hi") + .dwattr $C$DW$98, DW_AT_location[DW_OP_regx 0x5b] + +$C$DW$99 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$99, DW_AT_name("D14") + .dwattr $C$DW$99, DW_AT_location[DW_OP_regx 0x5c] + +$C$DW$100 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$100, DW_AT_name("D14_hi") + .dwattr $C$DW$100, DW_AT_location[DW_OP_regx 0x5d] + +$C$DW$101 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$101, DW_AT_name("D15") + .dwattr $C$DW$101, DW_AT_location[DW_OP_regx 0x5e] + +$C$DW$102 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$102, DW_AT_name("D15_hi") + .dwattr $C$DW$102, DW_AT_location[DW_OP_regx 0x5f] + +$C$DW$103 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$103, DW_AT_name("FPEXC") + .dwattr $C$DW$103, DW_AT_location[DW_OP_reg18] + +$C$DW$104 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$104, DW_AT_name("FPSCR") + .dwattr $C$DW$104, DW_AT_location[DW_OP_reg19] + + .dwendtag $C$DW$CU + diff --git a/CCS/mm/Debug/lib/io.d b/CCS/mm/Debug/lib/io.d new file mode 100644 index 0000000..4d18747 --- /dev/null +++ b/CCS/mm/Debug/lib/io.d @@ -0,0 +1,35 @@ +# FIXED + +lib/io.obj: ../lib/io.c +lib/io.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_memmap.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h +lib/io.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/rom.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h +lib/io.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h + +../lib/io.c: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_memmap.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/rom.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h: diff --git a/CCS/mm/Debug/lib/io.obj b/CCS/mm/Debug/lib/io.obj new file mode 100644 index 0000000..1a6a21b Binary files /dev/null and b/CCS/mm/Debug/lib/io.obj differ diff --git a/CCS/mm/Debug/lib/launchpad.d b/CCS/mm/Debug/lib/launchpad.d new file mode 100644 index 0000000..bc257b4 --- /dev/null +++ b/CCS/mm/Debug/lib/launchpad.d @@ -0,0 +1,47 @@ +# FIXED + +lib/launchpad.obj: ../lib/launchpad.c +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/gpio.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_memmap.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/pin_map.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/rom.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/sysctl.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/uart.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h +lib/launchpad.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/v_tm4c123gh6pm.h +lib/launchpad.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/adc.h + +../lib/launchpad.c: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/gpio.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_memmap.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/pin_map.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/rom.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/sysctl.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/uart.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/v_tm4c123gh6pm.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/adc.h: diff --git a/CCS/mm/Debug/lib/launchpad.obj b/CCS/mm/Debug/lib/launchpad.obj new file mode 100644 index 0000000..bba52d7 Binary files /dev/null and b/CCS/mm/Debug/lib/launchpad.obj differ diff --git a/CCS/mm/Debug/lib/main.d b/CCS/mm/Debug/lib/main.d new file mode 100644 index 0000000..d7fbbb7 --- /dev/null +++ b/CCS/mm/Debug/lib/main.d @@ -0,0 +1,379 @@ +# FIXED + +lib/main.obj: ../lib/main.c +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/launchpad.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/gpio.h +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_ints.h +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_memmap.h +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/rom.h +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/sysctl.h +lib/main.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/timer.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/adc.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/debug.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/fpu.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/gpio.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/pin_map.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/sysctl.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/math.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_defs.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_limits.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdio.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h +lib/main.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stddef.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/std.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/M4F.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/std.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/xdc.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__prologue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__epilogue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__prologue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Main_Module_GateProxy.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__epilogue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Memory.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Memory_HeapProxy.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__prologue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags__prologue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags__epilogue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__epilogue.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/ISystemSupport.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_SupportProxy.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/ISystemSupport.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_Module_GateProxy.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_SupportProxy.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/System_Module_GateProxy.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS.h +lib/main.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/main.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/BIOS__prologue.h +lib/main.obj: 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+C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__prologue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/package.defs.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log__prologue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: 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+C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/package/package.defs.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Swi.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Clock_TimerProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/GPIO.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Board.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/EK_TM4C123GXL.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/v_tm4c123gh6pm.h: diff --git a/CCS/mm/Debug/lib/main.obj b/CCS/mm/Debug/lib/main.obj new file mode 100644 index 0000000..75c394e Binary files /dev/null and b/CCS/mm/Debug/lib/main.obj differ diff --git a/CCS/mm/Debug/lib/motors.d b/CCS/mm/Debug/lib/motors.d new file mode 100644 index 0000000..a212147 --- /dev/null +++ b/CCS/mm/Debug/lib/motors.d @@ -0,0 +1,357 @@ +# FIXED + +lib/motors.obj: ../lib/motors.c +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/motors.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/gpio.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdbool.h +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/hw_memmap.h +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/pin_map.h +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/qei.h +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/rom.h +lib/motors.obj: C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc/tivaware/sysctl.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/std.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdarg.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stddef.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_ti_config.h +lib/motors.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/linkage.h +lib/motors.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/std.h +lib/motors.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/M4F.h +lib/motors.obj: C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/std.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/System.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/xdc.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__prologue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/package.defs.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types__epilogue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__prologue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Main_Module_GateProxy.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IGateProvider.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error__epilogue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Memory.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/package/Memory_HeapProxy.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert__prologue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags__prologue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Main.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags__epilogue.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h +lib/motors.obj: C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h +lib/motors.obj: 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+C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Text.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log__epilogue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IHeap.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Queue.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/package/package.defs.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Error.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Clock.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Assert.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Diags.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Log.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IModule.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: 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+C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/IInstance.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITimer.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/ccs930/xdctools_3_60_02_34_core/packages/xdc/runtime/Types.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/interfaces/ITaskSupport.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/Task__epilogue.h: +C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/knl/package/Task_SupportProxy.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/GPIO.h: +C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/PWM.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/Board.h: +C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/EK_TM4C123GXL.h: diff --git a/CCS/mm/Debug/lib/motors.obj b/CCS/mm/Debug/lib/motors.obj new file mode 100644 index 0000000..c33697d Binary files /dev/null and b/CCS/mm/Debug/lib/motors.obj differ diff --git a/CCS/mm/Debug/lib/startup.d b/CCS/mm/Debug/lib/startup.d new file mode 100644 index 0000000..a656d99 --- /dev/null +++ b/CCS/mm/Debug/lib/startup.d @@ -0,0 +1,21 @@ +# FIXED + +lib/startup.obj: ../lib/startup.c +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h +lib/startup.obj: C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h + +../lib/startup.c: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/_stdint40.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/cdefs.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_stdint.h: +C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_stdint.h: diff --git a/CCS/mm/Debug/lib/subdir_rules.mk b/CCS/mm/Debug/lib/subdir_rules.mk new file mode 100644 index 0000000..55b87b3 --- /dev/null +++ b/CCS/mm/Debug/lib/subdir_rules.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +lib/%.obj: ../lib/%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: ARM Compiler' + "C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/bin/armcl" -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM --define=ccs --define=TIVAWARE -g --c99 --gcc --diag_warning=225 --diag_warning=255 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi --preproc_with_compile --preproc_dependency="lib/$(basename $(> Linked Sat Nov 7 19:50:40 2020 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "_c_int00" address: 00003f61 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- + FLASH 00000000 00040000 000085dc 00037a24 R X + SRAM 20000000 00008000 00002236 00005dca RW X + + +SEGMENT ALLOCATION MAP + +run origin load origin length init length attrs members +---------- ----------- ---------- ----------- ----- ------- +00000000 00000000 000085e8 000085e8 r-x + 00000000 00000000 0000003c 0000003c r-- .resetVecs + 00000040 00000040 0000630a 0000630a r-x .text + 0000634c 0000634c 0000201e 0000201e r-- .const + 00008370 00008370 00000278 00000278 r-- .cinit +20000000 20000000 00002238 00000000 rw- + 20000000 20000000 00000360 00000000 rw- .vecs + 20000360 20000360 00001588 00000000 rw- .bss + 200018e8 200018e8 0000064e 00000000 rw- .data + 20001f38 20001f38 00000300 00000000 rw- .stack + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +.text 0 00000040 0000630a + 00000040 00000430 BIOS.obj (.text:ti_sysbios_family_arm_m3_Hwi_excDumpRegs__I) + 00000470 0000034c ti.targets.arm.rtsarm.aem4f : System.oem4f (.text:xdc_runtime_System_doPrint__I) + 000007bc 0000020c drivers_tivaware.aem4f : UARTTiva.oem4f (.text:UARTTiva_open) + 000009c8 000001f4 BIOS.obj (.text:ti_sysbios_family_arm_m3_Hwi_excHandlerMax__I) + 00000bbc 00000198 launchpad.obj (.text:launchpad_init) + 00000d54 00000004 driverlib.lib : uart.obj (.text:UARTIntClear) + 00000d58 00000174 BIOS.obj (.text:ti_sysbios_family_arm_m3_Hwi_excBusFault__I) + 00000ecc 00000170 drivers_tivaware.aem4f : PWMTiva.oem4f (.text:PWMTiva_open) + 0000103c 00000004 rtsv7M4_T_le_v4SPD16_eabi.lib : exit.c.obj (.text:abort:abort) + 00001040 00000164 BIOS.obj (.text:ti_sysbios_family_arm_m3_Hwi_excUsageFault__I) + 000011a4 00000004 gpiointerrupt_pem4f.oem4f (.text:ti_sysbios_BIOS_RtsGateProxy_enter__E) + 000011a8 00000154 BIOS.obj (.text:ti_sysbios_knl_Semaphore_pend__E) + 000012fc 00000150 drivers_tivaware.aem4f : GPIOTiva.oem4f (.text:GPIO_setConfig) + 0000144c 00000004 gpiointerrupt_pem4f.oem4f (.text:ti_sysbios_BIOS_RtsGateProxy_leave__E) + 00001450 00000148 BIOS.obj (.text:ti_sysbios_family_arm_m3_Hwi_excMemFault__I) + 00001598 00000130 driverlib.lib : gpio.obj (.text:GPIOPadConfigSet) + 000016c8 00000118 ti.targets.arm.rtsarm.aem4f : Error.oem4f (.text:xdc_runtime_Error_policyDefault__E) + 000017e0 00000108 BIOS.obj (.text:ti_sysbios_family_arm_lm4_Timer_start__E) + 000018e8 00000100 Boot.aem4f : Boot_sysctl.oem4f (.text:ti_catalog_arm_cortexm4_tiva_ce_Boot_sysCtlClockSetI__I) + 000019e8 00000100 ti.targets.arm.rtsarm.aem4f : Core-mem.oem4f (.text:xdc_runtime_Core_createObject__I) + 00001ae8 000000f8 : Startup.oem4f (.text:xdc_runtime_Startup_startMods__I) + 00001be0 000000f8 gpiointerrupt_pem4f.oem4f (.text:xdc_runtime_System_printfExtend__I) + 00001cd8 000000f4 m3_Hwi_asm.obj (.text:ti_sysbios_family_arm_m3_Hwi_dispatch__I) + 00001dcc 000000f0 drivers_tivaware.aem4f : PWMTiva.oem4f (.text:PWMTiva_setDuty) + 00001ebc 000000dc rtsv7M4_T_le_v4SPD16_eabi.lib : setvbuf.c.obj (.text:setvbuf) + 00001f98 000000dc BIOS.obj (.text:ti_sysbios_knl_Task_sleep__E) + 00002074 00000004 BIOS.obj (.text:ti_sysbios_family_arm_lm4_Timer_masterEnable__I) + 00002078 000000d4 BIOS.obj (.text:ti_sysbios_heaps_HeapMem_alloc__E) + 0000214c 00000004 gpiointerrupt_pem4f.oem4f (.text:ti_sysbios_family_arm_m3_Hwi_destruct) + 00002150 000000cc BIOS.obj (.text:ti_sysbios_knl_Task_Instance_init__E) + 0000221c 000000cc ti.targets.arm.rtsarm.aem4f : Core-smem.oem4f (.text:xdc_runtime_Core_constructObject__I) + 000022e8 000000bc BIOS.obj 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gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_lm4_Timer_enableFunc__C) + 0000822c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_lm4_Timer_numTimerDevices__C) + 00008230 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_lm4_Timer_startupNeeded__C) + 00008234 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_NMI__C) + 00008238 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_alreadyDefined__C) + 0000823c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_busFault__C) + 00008240 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_debugMon__C) + 00008244 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_hardFault__C) + 00008248 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_memFault__C) + 0000824c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_noIsr__C) + 00008250 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_reserved__C) + 00008254 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_svCall__C) + 00008258 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_E_usageFault__C) + 0000825c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_NUM_INTERRUPTS__C) + 00008260 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_Object__count__C) + 00008264 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_ccr__C) + 00008268 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_excHandlerFunc__C) + 0000826c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_excHookFuncs__C) + 00008270 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_nullIsrFunc__C) + 00008274 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_priGroup__C) + 00008278 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_TaskSupport_stackAlignment__C) + 0000827c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_gates_GateMutex_Instance_State_sem__O) + 00008280 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_hal_Hwi_E_stackOverflow__C) + 00008284 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_heaps_HeapMem_E_memory__C) + 00008288 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_heaps_HeapMem_Module__gateObj__C) + 0000828c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_heaps_HeapMem_Object__count__C) + 00008290 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_heaps_HeapMem_reqAlign__C) + 00008294 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Clock_Module_State_clockQ__O) + 00008298 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Idle_funcList__A) + 0000829c 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Semaphore_Instance_State_pendQ__O) + 000082a0 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Swi_Object__count__C) + 000082a4 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_E_spOutOfBounds__C) + 000082a8 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_E_stackOverflow__C) + 000082ac 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_Module_State_inactiveQ__O) + 000082b0 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_Object__count__C) + 000082b4 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_allBlockedFunc__C) + 000082b8 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_defaultStackHeap__C) + 000082bc 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_defaultStackSize__C) + 000082c0 00000004 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_numConstructedTasks__C) + 000082c4 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Assert_E_assertFailed__C) + 000082c8 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Core_A_initializedParams__C) + 000082cc 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Core_Module__diagsEnabled__C) + 000082d0 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Core_Module__diagsIncluded__C) + 000082d4 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Core_Module__diagsMask__C) + 000082d8 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_E_memory__C) + 000082dc 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__diagsEnabled__C) + 000082e0 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__diagsIncluded__C) + 000082e4 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__diagsMask__C) + 000082e8 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__loggerFxn8__C) + 000082ec 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__loggerObj__C) + 000082f0 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_policyFxn__C) + 000082f4 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_raiseHook__C) + 000082f8 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_IGateProvider_Interface__BASE__C) + 000082fc 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_IHeap_Interface__BASE__C) + 00008300 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_IModule_Interface__BASE__C) + 00008304 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Log_L_error__C) + 00008308 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Memory_defaultHeapInstance__C) + 0000830c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_execImpl__C) + 00008310 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_maxPasses__C) + 00008314 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_sfxnRts__C) + 00008318 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Startup_sfxnTab__C) + 0000831c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_SysMin_bufSize__C) + 00008320 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_SysMin_outputFunc__C) + 00008324 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_Module__gateObj__C) + 00008328 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_abortFxn__C) + 0000832c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_exitFxn__C) + 00008330 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_extendFxn__C) + 00008334 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_System_maxAtexitHandlers__C) + 00008338 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_charTab__C) + 0000833c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nameEmpty__C) + 00008340 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nameStatic__C) + 00008344 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nameUnknown__C) + 00008348 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_nodeTab__C) + 0000834c 00000004 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_visitRopeFxn__C) + 00008350 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_family_arm_m3_Hwi_Module__id__C) + 00008352 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_hal_Hwi_Module__id__C) + 00008354 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_heaps_HeapMem_Module__id__C) + 00008356 00000002 gpiointerrupt_pem4f.oem4f (.const:ti_sysbios_knl_Task_Module__id__C) + 00008358 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Core_Module__id__C) + 0000835a 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_Module__loggerDefined__C) + 0000835c 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Error_maxDepth__C) + 0000835e 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Memory_Module__id__C) + 00008360 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_SysMin_flushAtExit__C) + 00008362 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_charCnt__C) + 00008364 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_isLoaded__C) + 00008366 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_registryModsLastId__C) + 00008368 00000002 gpiointerrupt_pem4f.oem4f (.const:xdc_runtime_Text_unnamedModsLastId__C) + +.cinit 0 00008370 00000278 + 00008370 00000243 (.cinit..data.load) [load image, compression = lzss] + 000085b3 00000001 --HOLE-- [fill = 0] + 000085b4 0000000c (__TI_handler_table) + 000085c0 00000008 (.cinit..bss.load) [load image, compression = zero_init] + 000085c8 00000008 (.cinit..vecs.load) [load image, compression = zero_init] + 000085d0 00000018 (__TI_cinit_table) + +.init_array +* 0 00000000 00000000 UNINITIALIZED + +.resetVecs +* 0 00000000 0000003c + 00000000 0000003c gpiointerrupt_pem4f.oem4f (.resetVecs) + +.bss 0 20000360 00001588 UNINITIALIZED + 20000360 00000600 gpiointerrupt_pem4f.oem4f (.bss:taskStackSection) + 20000960 00000400 (.common:ti_sysbios_heaps_HeapMem_Instance_State_0_buf__A) + 20000d60 00000400 (.common:tsk0Stack) + 20001160 00000360 (.common:ti_sysbios_family_arm_m3_Hwi_dispatchTable) + 200014c0 00000120 rtsv7M4_T_le_v4SPD16_eabi.lib : trgmsg.c.obj (.bss:_CIOBUF_) + 200015e0 000000cc (.common:uartTivaObjects) + 200016ac 000000a0 (.common:__TI_tmpnams) + 2000174c 00000090 drivers_tivaware.aem4f : GPIOTiva.oem4f (.bss:gpioCallbackInfo) + 200017dc 00000080 (.common:xdc_runtime_SysMin_Module_State_0_outbuf__A) + 2000185c 00000050 (.common:tsk1Struct) + 200018ac 00000020 (.common:uartTivaRingBuffer) + 200018cc 00000010 (.common:pwmTivaObjects) + 200018dc 00000008 (.common:parmbuf) + 200018e4 00000004 (.common:gpioInterruptVectors) + +.data 0 200018e8 0000064e UNINITIALIZED + 200018e8 000000f0 rtsv7M4_T_le_v4SPD16_eabi.lib : defs.c.obj (.data:_ftable) + 200019d8 00000098 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Object__table__V) + 20001a70 00000080 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Swi_Module_State_0_readyQ__A) + 20001af0 00000080 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module_State_0_readyQ__A) + 20001b70 00000078 rtsv7M4_T_le_v4SPD16_eabi.lib : host_device.c.obj (.data:_device) + 20001be8 00000050 : host_device.c.obj (.data:_stream) + 20001c38 00000044 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module__state__V) + 20001c7c 00000040 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Object__table__V) + 20001cbc 00000038 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateMutex_Object__table__V) + 20001cf4 00000034 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module__state__V) + 20001d28 00000030 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Module_State_0_device__A) + 20001d58 00000030 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Swi_Object__table__V) + 20001d88 0000002c gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Clock_Module__state__V) + 20001db4 00000024 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_BIOS_Module__state__V) + 20001dd8 0000001c gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Swi_Module__state__V) + 20001df4 00000018 drivers_tivaware.aem4f : PWMTiva.oem4f (.data) + 20001e0c 00000018 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Module_State_0_handles__A) + 20001e24 00000018 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Object__table__V) + 20001e3c 00000018 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_heaps_HeapMem_Object__table__V) + 20001e54 00000014 EK_TM4C123GXL.obj (.data:gpioPinConfigs) + 20001e68 00000010 rtsv7M4_T_le_v4SPD16_eabi.lib : defs.c.obj (.data) + 20001e78 0000000c : exit.c.obj (.data:$O1$$) + 20001e84 0000000c gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_lm4_Timer_Module__state__V) + 20001e90 0000000c gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_SysMin_Module__state__V) + 20001e9c 00000008 rtsv7M4_T_le_v4SPD16_eabi.lib : _lock.c.obj (.data:$O1$$) + 20001ea4 00000008 EK_TM4C123GXL.obj (.data:gpioCallbackFunctions) + 20001eac 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module__root__V) + 20001eb4 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateHwi_Module__root__V) + 20001ebc 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateMutex_Module__root__V) + 20001ec4 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_heaps_HeapMem_Module__root__V) + 20001ecc 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Clock_Module__root__V) + 20001ed4 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Queue_Module__root__V) + 20001edc 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Semaphore_Module__root__V) + 20001ee4 00000008 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module__root__V) + 20001eec 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Registry_Module__state__V) + 20001ef4 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Startup_Module__state__V) + 20001efc 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_System_Module_State_0_atexitHandlers__A) + 20001f04 00000008 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_System_Module__state__V) + 20001f0c 00000005 drivers_tivaware.aem4f : GPIOTiva.oem4f (.data) + 20001f11 00000001 --HOLE-- + 20001f12 00000002 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module_State_0_excActive__A) + 20001f14 00000004 drivers_tivaware.aem4f : PWM.oem4f (.data) + 20001f18 00000004 : UART.oem4f (.data) + 20001f1c 00000004 rtsv7M4_T_le_v4SPD16_eabi.lib : stkdepth_vars.c.obj (.data) + 20001f20 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module_State_0_excContext__A) + 20001f24 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_family_arm_m3_Hwi_Module_State_0_excStack__A) + 20001f28 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_gates_GateHwi_Object__table__V) + 20001f2c 00000004 gpiointerrupt_pem4f.oem4f (.data:ti_sysbios_knl_Task_Module_State_0_idleTask__A) + 20001f30 00000004 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Memory_Module__state__V) + 20001f34 00000002 gpiointerrupt_pem4f.oem4f (.data:xdc_runtime_Error_Module__state__V) + +.stack 0 20001f38 00000300 UNINITIALIZED + 20001f38 00000300 --HOLE-- + +.bootVecs +* 0 00000000 00000008 DSECT + 00000000 00000008 boot.aem4f : boot.oem4f (.bootVecs) + +.vecs 0 20000000 00000360 UNINITIALIZED + 20000000 00000360 gpiointerrupt_pem4f.oem4f (.vecs) + +xdc.meta 0 00000000 000000ec COPY SECTION + 00000000 000000ec gpiointerrupt_pem4f.oem4f (xdc.meta) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + ..\src\sysbios\ + BIOS.obj 9220 0 0 + m3_Hwi_asm.obj 314 0 0 + m3_TaskSupport_asm.obj 180 0 0 + m3_Hwi_asm_switch.obj 118 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 9832 0 0 + + .\ + EK_TM4C123GXL.obj 164 128 280 + +--+----------------------------+-------+---------+---------+ + Total: 164 128 280 + + .\lib\ + main.obj 370 0 1104 + launchpad.obj 408 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 778 0 1104 + + C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\Debug\configPkg\package\cfg\ + gpiointerrupt_pem4f.oem4f 1958 7670 5484 + +--+----------------------------+-------+---------+---------+ + Total: 1958 7670 5484 + + C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/ccs/Debug/driverlib.lib + gpio.obj 566 144 0 + uart.obj 226 0 0 + pwm.obj 178 0 0 + sysctl.obj 72 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 1042 144 0 + + C:/ti/tirtos_tivac_2_16_00_08/products/tidrivers_tivac_2_16_00_08/packages/ti/drivers/lib/drivers_tivaware.aem4f + UARTTiva.oem4f 2262 116 0 + PWMTiva.oem4f 962 32 24 + GPIOTiva.oem4f 684 156 153 + RingBuf.oem4f 164 0 0 + UART.oem4f 92 36 4 + PWM.oem4f 56 0 4 + +--+----------------------------+-------+---------+---------+ + Total: 4220 340 185 + + C:\ti\ccs930\ccs\tools\compiler\ti-cgt-arm_18.12.4.LTS\lib\rtsv7M4_T_le_v4SPD16_eabi.lib + defs.c.obj 0 0 416 + trgmsg.c.obj 108 0 288 + setvbuf.c.obj 220 0 0 + host_device.c.obj 0 0 200 + memcpy_t2.asm.obj 156 0 0 + memset_t2.asm.obj 122 0 0 + fclose.c.obj 116 0 0 + getdevice.c.obj 116 0 0 + hostrename.c.obj 108 0 0 + copy_decompress_lzss.c.obj 104 0 0 + hostlseek.c.obj 104 0 0 + hostopen.c.obj 96 0 8 + close.c.obj 92 0 0 + exit.c.obj 76 0 12 + hostread.c.obj 88 0 0 + hostwrite.c.obj 88 0 0 + cpy_tbl.c.obj 76 0 0 + fflush.c.obj 76 0 0 + hostclose.c.obj 68 0 0 + hostunlink.c.obj 68 0 0 + u_divt2.asm.obj 64 0 0 + strncpy.c.obj 54 0 0 + fopen.c.obj 52 0 0 + unlink.c.obj 44 0 0 + write.c.obj 40 0 0 + _lock.c.obj 26 0 8 + args_main.c.obj 24 0 0 + strcmp.c.obj 24 0 0 + strchr.c.obj 22 0 0 + strcpy.c.obj 20 0 0 + strlen.c.obj 20 0 0 + copy_decompress_none.c.obj 14 0 0 + copy_zero_init.c.obj 12 0 0 + stkdepth_vars.c.obj 0 0 4 + div0.asm.obj 2 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 2300 0 936 + + C:\ti\tirtos_tivac_2_16_00_08\packages\ti\tirtos\utils\lib\release\ti.tirtos.utils.aem4f + UARTMon.oem4f 186 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 186 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\catalog\arm\cortexm4\tiva\ce\lib\Boot.aem4f + Boot_sysctl.oem4f 262 0 0 + Boot.oem4f 152 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 414 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\auto_init.aem4f + auto_init.oem4f 160 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 160 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\boot.aem4f + boot.oem4f 88 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 88 0 0 + + C:\ti\tirtos_tivac_2_16_00_08\products\bios_6_45_01_29\packages\ti\targets\arm\rtsarm\lib\ti.targets.arm.rtsarm.aem4f + System.oem4f 1255 0 0 + Text.oem4f 672 0 0 + Error.oem4f 524 0 0 + Core-mem.oem4f 358 0 0 + Startup.oem4f 328 0 0 + SysMin.oem4f 248 0 0 + Core-smem.oem4f 204 0 0 + Memory.oem4f 176 0 0 + Assert.oem4f 84 0 0 + Core-params.oem4f 70 0 0 + Core-label.oem4f 52 0 0 + Registry.oem4f 32 0 0 + Gate.oem4f 28 0 0 + +--+----------------------------+-------+---------+---------+ + Total: 4031 0 0 + + Stack: 0 0 768 + Linker Generated: 0 631 0 + +--+----------------------------+-------+---------+---------+ + Grand Total: 25173 8913 8757 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 000085d0 records: 3, size/record: 8, table size: 24 + .data: load addr=00008370, load size=00000243 bytes, run addr=200018e8, run size=0000064e bytes, compression=lzss + .bss: load addr=000085c0, load size=00000008 bytes, run addr=20000360, run size=00001588 bytes, compression=zero_init + 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+ + + close + 0x3d29 + + + + unlink + 0x55ed + + + + __TI_static_base__ + 0x8370 + + + SHT$$INIT_ARRAY$$Base + 0x0 + + + SHT$$INIT_ARRAY$$Limit + 0x0 + + + ti_sysbios_hal_Hwi_switchFromBootStack__E + 0x5ef9 + + + ti_sysbios_hal_Hwi_disableInterrupt__E + 0x4759 + + + ti_sysbios_hal_Hwi_enableInterrupt__E + 0x47a1 + + + ti_sysbios_hal_Hwi_getStackInfo__E + 0x49d1 + + + ti_sysbios_hal_Hwi_startup__E + 0x62c1 + + + ti_sysbios_BIOS_RtsGateProxy_query__E + 0x6331 + + + ti_sysbios_hal_Hwi_HwiProxy_getStackInfo__E + 0x49d1 + + + ti_sysbios_hal_Hwi_HwiProxy_startup__E + 0x62c1 + + + ti_sysbios_hal_Hwi_HwiProxy_disable__E + 0x61a9 + + + ti_sysbios_hal_Hwi_HwiProxy_restore__E + 0x62f1 + + + ti_sysbios_hal_Hwi_HwiProxy_switchFromBootStack__E + 0x5ef9 + + + ti_sysbios_hal_Hwi_HwiProxy_disableInterrupt__E + 0x4759 + + + ti_sysbios_hal_Hwi_HwiProxy_enableInterrupt__E + 0x47a1 + + + ti_sysbios_heaps_HeapMem_Module_GateProxy_query__E + 0x6331 + + + ti_sysbios_knl_Clock_TimerProxy_startup__E + 0x4cf1 + + + ti_sysbios_knl_Task_SupportProxy_start__E + 0x5359 + + + ti_sysbios_knl_Task_SupportProxy_swap__E + 0x5da9 + + + ti_sysbios_knl_Task_SupportProxy_checkStack__E + 0x61b9 + + + ti_sysbios_knl_Task_SupportProxy_getStackAlignment__E + 0x61c9 + + + xdc_runtime_Main_Module_GateProxy_query__E + 0x6329 + + + xdc_runtime_System_Module_GateProxy_query__E + 0x6329 + + + xdc_runtime_System_SupportProxy_abort__E + 0x54d9 + + + xdc_runtime_System_SupportProxy_exit__E + 0x5bf5 + + + xdc_runtime_System_SupportProxy_flush__E + 0x4aa1 + + + xdc_runtime_System_SupportProxy_putch__E + 0x4f11 + + + xdc_runtime_System_SupportProxy_ready__E + 0x6099 + + + mem_Free + 0x5c2d + + + osi_start + 0x6009 + + + osi_TaskDisable + 0x6069 + + + ff_memalloc + 0x5539 + + + ff_memfree + 0x5c2d + + + xdc_runtime_System_abortStd__E + 0x103d + + + xdc_runtime_System_exitStd__E + 0x46c5 + + + xdc_runtime_System_flush__E + 0x4aa1 + + + remove + 0x55ed + + + Link successful + diff --git a/CCS/mm/Debug/motors.asm b/CCS/mm/Debug/motors.asm new file mode 100644 index 0000000..63bb06b --- /dev/null +++ b/CCS/mm/Debug/motors.asm @@ -0,0 +1,2362 @@ +;****************************************************************************** +;* TI ARM G3 C/C++ Codegen PC v18.12.4.LTS * +;* Date/Time created: Sat Sep 19 20:39:24 2020 * +;****************************************************************************** + .compiler_opts --abi=eabi --arm_vmrs_si_workaround=off --code_state=16 --diag_wrap=off --embedded_constants=on --endian=little --float_support=FPv4SPD16 --hll_source=on --object_format=elf --silicon_version=7M4 --symdebug:dwarf --symdebug:dwarf_version=3 --unaligned_access=on + .thumb + +$C$DW$CU .dwtag DW_TAG_compile_unit + .dwattr $C$DW$CU, DW_AT_name("../lib/motors.c") + .dwattr $C$DW$CU, DW_AT_producer("TI TI ARM G3 C/C++ Codegen PC v18.12.4.LTS Copyright (c) 1996-2018 Texas Instruments Incorporated") + .dwattr $C$DW$CU, DW_AT_TI_version(0x01) + .dwattr $C$DW$CU, DW_AT_comp_dir("C:\Users\zachr\workspace_v9\mm\Debug") + .global VELOCITY_PERIOD + .sect ".const" + .align 4 + .elfsym VELOCITY_PERIOD,SYM_SIZE(4) +VELOCITY_PERIOD: + .bits 0xfa0,32 + ; VELOCITY_PERIOD @ 0 + +$C$DW$1 .dwtag DW_TAG_variable + .dwattr $C$DW$1, DW_AT_name("VELOCITY_PERIOD") + .dwattr $C$DW$1, DW_AT_TI_symbol_name("VELOCITY_PERIOD") + .dwattr $C$DW$1, DW_AT_location[DW_OP_addr VELOCITY_PERIOD] + .dwattr $C$DW$1, DW_AT_type(*$C$DW$T$59) + .dwattr $C$DW$1, DW_AT_external + .dwattr $C$DW$1, DW_AT_decl_file("C:/Users/zachr/workspace_v9/mm/inc/motors.h") + .dwattr $C$DW$1, DW_AT_decl_line(0x03) + .dwattr $C$DW$1, DW_AT_decl_column(0x0b) + +; C:\ti\ccs930\ccs\tools\compiler\ti-cgt-arm_18.12.4.LTS\bin\armacpia.exe -@C:\\Users\\zachr\\AppData\\Local\\Temp\\{D3969CD1-5236-41A6-98DC-42EBB1694E03} + .sect ".text:init_motors" + .clink + .thumbfunc init_motors + .thumb + .global init_motors + +$C$DW$2 .dwtag DW_TAG_subprogram + .dwattr $C$DW$2, DW_AT_name("init_motors") + .dwattr $C$DW$2, DW_AT_low_pc(init_motors) + .dwattr $C$DW$2, DW_AT_high_pc(0x00) + .dwattr $C$DW$2, DW_AT_TI_symbol_name("init_motors") + .dwattr $C$DW$2, DW_AT_external + .dwattr $C$DW$2, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$2, DW_AT_TI_begin_line(0x0a) + .dwattr $C$DW$2, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$2, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$2, DW_AT_decl_line(0x0a) + .dwattr $C$DW$2, DW_AT_decl_column(0x06) + .dwattr $C$DW$2, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 10,column 20,is_stmt,address init_motors,isa 1 + + .dwfde $C$DW$CIE, init_motors +;---------------------------------------------------------------------- +; 10 | void init_motors() { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: init_motors * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +init_motors: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/motors.c",line 11,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 11 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_QEI0); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |11| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |11| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |11| + MOV A2, A1 ; [DPU_V7M3_PIPE] |11| + LDR A1, $C$CON2 ; [DPU_V7M3_PIPE] |11| +$C$DW$3 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$3, DW_AT_low_pc(0x00) + .dwattr $C$DW$3, DW_AT_TI_call + .dwattr $C$DW$3, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |11| + ; CALL OCCURS {} ; [] |11| + .dwpsn file "../lib/motors.c",line 12,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 12 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_QEI1); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |12| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |12| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |12| + MOV A2, A1 ; [DPU_V7M3_PIPE] |12| + LDR A1, $C$CON3 ; [DPU_V7M3_PIPE] |12| +$C$DW$4 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$4, DW_AT_low_pc(0x00) + .dwattr $C$DW$4, DW_AT_TI_call + .dwattr $C$DW$4, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |12| + ; CALL OCCURS {} ; [] |12| + .dwpsn file "../lib/motors.c",line 13,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 13 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |13| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |13| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |13| + MOV A2, A1 ; [DPU_V7M3_PIPE] |13| + LDR A1, $C$CON4 ; [DPU_V7M3_PIPE] |13| +$C$DW$5 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$5, DW_AT_low_pc(0x00) + .dwattr $C$DW$5, DW_AT_TI_call + .dwattr $C$DW$5, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |13| + ; CALL OCCURS {} ; [] |13| + .dwpsn file "../lib/motors.c",line 14,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 14 | ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); +;---------------------------------------------------------------------- + LDR A1, $C$CON1 ; [DPU_V7M3_PIPE] |14| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |14| + LDR A1, [A1, #24] ; [DPU_V7M3_PIPE] |14| + MOV A2, A1 ; [DPU_V7M3_PIPE] |14| + LDR A1, $C$CON5 ; [DPU_V7M3_PIPE] |14| +$C$DW$6 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$6, DW_AT_low_pc(0x00) + .dwattr $C$DW$6, DW_AT_TI_call + .dwattr $C$DW$6, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |14| + ; CALL OCCURS {} ; [] |14| + .dwpsn file "../lib/motors.c",line 15,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 15 | ROM_GPIOPinConfigure(GPIO_PD6_PHA0); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |15| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |15| + LDR A1, [A1, #104] ; [DPU_V7M3_PIPE] |15| + MOV A2, A1 ; [DPU_V7M3_PIPE] |15| + LDR A1, $C$CON7 ; [DPU_V7M3_PIPE] |15| +$C$DW$7 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$7, DW_AT_low_pc(0x00) + .dwattr $C$DW$7, DW_AT_TI_call + .dwattr $C$DW$7, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |15| + ; CALL OCCURS {} ; [] |15| + .dwpsn file "../lib/motors.c",line 16,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 16 | ROM_GPIOPinConfigure(GPIO_PD7_PHB0); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |16| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |16| + LDR A1, [A1, #104] ; [DPU_V7M3_PIPE] |16| + MOV A2, A1 ; [DPU_V7M3_PIPE] |16| + LDR A1, $C$CON8 ; [DPU_V7M3_PIPE] |16| +$C$DW$8 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$8, DW_AT_low_pc(0x00) + .dwattr $C$DW$8, DW_AT_TI_call + .dwattr $C$DW$8, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |16| + ; CALL OCCURS {} ; [] |16| + .dwpsn file "../lib/motors.c",line 17,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 17 | ROM_GPIOPinConfigure(GPIO_PC5_PHA1); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |17| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |17| + LDR A1, [A1, #104] ; [DPU_V7M3_PIPE] |17| + MOV A2, A1 ; [DPU_V7M3_PIPE] |17| + LDR A1, $C$CON9 ; [DPU_V7M3_PIPE] |17| +$C$DW$9 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$9, DW_AT_low_pc(0x00) + .dwattr $C$DW$9, DW_AT_TI_call + .dwattr $C$DW$9, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |17| + ; CALL OCCURS {} ; [] |17| + .dwpsn file "../lib/motors.c",line 18,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 18 | ROM_GPIOPinConfigure(GPIO_PC6_PHB1); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |18| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |18| + LDR A1, [A1, #104] ; [DPU_V7M3_PIPE] |18| + MOV A2, A1 ; [DPU_V7M3_PIPE] |18| + LDR A1, $C$CON10 ; [DPU_V7M3_PIPE] |18| +$C$DW$10 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$10, DW_AT_low_pc(0x00) + .dwattr $C$DW$10, DW_AT_TI_call + .dwattr $C$DW$10, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |18| + ; CALL OCCURS {} ; [] |18| + .dwpsn file "../lib/motors.c",line 19,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 19 | ROM_GPIOPinTypeQEI(GPIO_PORTD_BASE, GPIO_PIN_6 | GPIO_PIN_7); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |19| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |19| + LDR A1, [A1, #72] ; [DPU_V7M3_PIPE] |19| + MOV A3, A1 ; [DPU_V7M3_PIPE] |19| + LDR A1, $C$CON11 ; [DPU_V7M3_PIPE] |19| + MOVS A2, #192 ; [DPU_V7M3_PIPE] |19| +$C$DW$11 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$11, DW_AT_low_pc(0x00) + .dwattr $C$DW$11, DW_AT_TI_call + .dwattr $C$DW$11, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |19| + ; CALL OCCURS {} ; [] |19| +;* --------------------------------------------------------------------------* + .dwpsn file "../lib/motors.c",line 20,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 20 | ROM_GPIOPinTypeQEI(GPIO_PORTC_BASE, GPIO_PIN_5 | GPIO_PIN_6); +;---------------------------------------------------------------------- + LDR A1, $C$CON6 ; [DPU_V7M3_PIPE] |20| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |20| + LDR A1, [A1, #72] ; [DPU_V7M3_PIPE] |20| + MOV A3, A1 ; [DPU_V7M3_PIPE] |20| + LDR A1, $C$CON12 ; [DPU_V7M3_PIPE] |20| + MOVS A2, #96 ; [DPU_V7M3_PIPE] |20| +$C$DW$12 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$12, DW_AT_low_pc(0x00) + .dwattr $C$DW$12, DW_AT_TI_call + .dwattr $C$DW$12, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |20| + ; CALL OCCURS {} ; [] |20| + .dwpsn file "../lib/motors.c",line 21,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 21 | ROM_QEIConfigure(QEI0_BASE, QEI_CONFIG_CAPTURE_A_B | QEI_CONFIG_SWAP, +; 22 | UINT32_MAX); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |21| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |21| + LDR A1, [A1, #12] ; [DPU_V7M3_PIPE] |21| + MOV A4, A1 ; [DPU_V7M3_PIPE] |21| + LDR A1, $C$CON14 ; [DPU_V7M3_PIPE] |21| + MOVS A2, #10 ; [DPU_V7M3_PIPE] |21| + MOV A3, #-1 ; [DPU_V7M3_PIPE] |21| +$C$DW$13 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$13, DW_AT_low_pc(0x00) + .dwattr $C$DW$13, DW_AT_TI_call + .dwattr $C$DW$13, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |21| + ; CALL OCCURS {} ; [] |21| + .dwpsn file "../lib/motors.c",line 23,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 23 | ROM_QEIConfigure(QEI1_BASE, QEI_CONFIG_CAPTURE_A_B | QEI_CONFIG_NO_SWAP +; | , +; 24 | UINT32_MAX); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |23| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |23| + LDR A1, [A1, #12] ; [DPU_V7M3_PIPE] |23| + MOV A4, A1 ; [DPU_V7M3_PIPE] |23| + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |23| + MOVS A2, #8 ; [DPU_V7M3_PIPE] |23| + MOV A3, #-1 ; [DPU_V7M3_PIPE] |23| +$C$DW$14 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$14, DW_AT_low_pc(0x00) + .dwattr $C$DW$14, DW_AT_TI_call + .dwattr $C$DW$14, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |23| + ; CALL OCCURS {} ; [] |23| + .dwpsn file "../lib/motors.c",line 25,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 25 | ROM_QEIVelocityConfigure(QEI0_BASE, QEI_VELDIV_1, VELOCITY_PERIOD); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |25| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |25| + LDR A1, [A1, #36] ; [DPU_V7M3_PIPE] |25| + MOV A4, A1 ; [DPU_V7M3_PIPE] |25| + LDR A1, $C$CON14 ; [DPU_V7M3_PIPE] |25| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |25| + MOV A3, #4000 ; [DPU_V7M3_PIPE] |25| +$C$DW$15 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$15, DW_AT_low_pc(0x00) + .dwattr $C$DW$15, DW_AT_TI_call + .dwattr $C$DW$15, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |25| + ; CALL OCCURS {} ; [] |25| + .dwpsn file "../lib/motors.c",line 26,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 26 | ROM_QEIVelocityConfigure(QEI1_BASE, QEI_VELDIV_1, VELOCITY_PERIOD); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |26| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |26| + LDR A1, [A1, #36] ; [DPU_V7M3_PIPE] |26| + MOV A4, A1 ; [DPU_V7M3_PIPE] |26| + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |26| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |26| + MOV A3, #4000 ; [DPU_V7M3_PIPE] |26| +$C$DW$16 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$16, DW_AT_low_pc(0x00) + .dwattr $C$DW$16, DW_AT_TI_call + .dwattr $C$DW$16, DW_AT_TI_indirect + + BLX A4 ; [DPU_V7M3_PIPE] |26| + ; CALL OCCURS {} ; [] |26| + .dwpsn file "../lib/motors.c",line 27,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 27 | ROM_QEIEnable(QEI0_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |27| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |27| + LDR A1, [A1, #4] ; [DPU_V7M3_PIPE] |27| + MOV A2, A1 ; [DPU_V7M3_PIPE] |27| + LDR A1, $C$CON14 ; [DPU_V7M3_PIPE] |27| +$C$DW$17 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$17, DW_AT_low_pc(0x00) + .dwattr $C$DW$17, DW_AT_TI_call + .dwattr $C$DW$17, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |27| + ; CALL OCCURS {} ; [] |27| + .dwpsn file "../lib/motors.c",line 28,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 28 | ROM_QEIEnable(QEI1_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |28| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |28| + LDR A1, [A1, #4] ; [DPU_V7M3_PIPE] |28| + MOV A2, A1 ; [DPU_V7M3_PIPE] |28| + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |28| +$C$DW$18 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$18, DW_AT_low_pc(0x00) + .dwattr $C$DW$18, DW_AT_TI_call + .dwattr $C$DW$18, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |28| + ; CALL OCCURS {} ; [] |28| + .dwpsn file "../lib/motors.c",line 29,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 29 | ROM_QEIVelocityEnable(QEI0_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |29| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |29| + LDR A1, [A1, #28] ; [DPU_V7M3_PIPE] |29| + MOV A2, A1 ; [DPU_V7M3_PIPE] |29| + LDR A1, $C$CON14 ; [DPU_V7M3_PIPE] |29| +$C$DW$19 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$19, DW_AT_low_pc(0x00) + .dwattr $C$DW$19, DW_AT_TI_call + .dwattr $C$DW$19, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |29| + ; CALL OCCURS {} ; [] |29| + .dwpsn file "../lib/motors.c",line 30,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 30 | ROM_QEIVelocityEnable(QEI1_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON13 ; [DPU_V7M3_PIPE] |30| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |30| + LDR A1, [A1, #28] ; [DPU_V7M3_PIPE] |30| + MOV A2, A1 ; [DPU_V7M3_PIPE] |30| + LDR A1, $C$CON15 ; [DPU_V7M3_PIPE] |30| +$C$DW$20 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$20, DW_AT_low_pc(0x00) + .dwattr $C$DW$20, DW_AT_TI_call + .dwattr $C$DW$20, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |30| + ; CALL OCCURS {} ; [] |30| + .dwpsn file "../lib/motors.c",line 31,column 1,is_stmt,isa 1 +$C$DW$21 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$21, DW_AT_low_pc(0x00) + .dwattr $C$DW$21, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$2, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$2, DW_AT_TI_end_line(0x1f) + .dwattr $C$DW$2, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$2 + + .sect ".text:left_pos" + .clink + .thumbfunc left_pos + .thumb + .global left_pos + +$C$DW$22 .dwtag DW_TAG_subprogram + .dwattr $C$DW$22, DW_AT_name("left_pos") + .dwattr $C$DW$22, DW_AT_low_pc(left_pos) + .dwattr $C$DW$22, DW_AT_high_pc(0x00) + .dwattr $C$DW$22, DW_AT_TI_symbol_name("left_pos") + .dwattr $C$DW$22, DW_AT_external + .dwattr $C$DW$22, DW_AT_type(*$C$DW$T$87) + .dwattr $C$DW$22, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$22, DW_AT_TI_begin_line(0x21) + .dwattr $C$DW$22, DW_AT_TI_begin_column(0x09) + .dwattr $C$DW$22, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$22, DW_AT_decl_line(0x21) + .dwattr $C$DW$22, DW_AT_decl_column(0x09) + .dwattr $C$DW$22, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 33,column 24,is_stmt,address left_pos,isa 1 + + .dwfde $C$DW$CIE, left_pos +;---------------------------------------------------------------------- +; 33 | int32_t left_pos(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: left_pos * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +left_pos: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/motors.c",line 34,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 34 | return ROM_QEIPositionGet(QEI0_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON16 ; [DPU_V7M3_PIPE] |34| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |34| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |34| + MOV A2, A1 ; [DPU_V7M3_PIPE] |34| + LDR A1, $C$CON17 ; [DPU_V7M3_PIPE] |34| +$C$DW$23 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$23, DW_AT_low_pc(0x00) + .dwattr $C$DW$23, DW_AT_TI_call + .dwattr $C$DW$23, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |34| + ; CALL OCCURS {} ; [] |34| + .dwpsn file "../lib/motors.c",line 35,column 1,is_stmt,isa 1 +$C$DW$24 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$24, DW_AT_low_pc(0x00) + .dwattr $C$DW$24, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$22, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$22, DW_AT_TI_end_line(0x23) + .dwattr $C$DW$22, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$22 + + .sect ".text:right_pos" + .clink + .thumbfunc right_pos + .thumb + .global right_pos + +$C$DW$25 .dwtag DW_TAG_subprogram + .dwattr $C$DW$25, DW_AT_name("right_pos") + .dwattr $C$DW$25, DW_AT_low_pc(right_pos) + .dwattr $C$DW$25, DW_AT_high_pc(0x00) + .dwattr $C$DW$25, DW_AT_TI_symbol_name("right_pos") + .dwattr $C$DW$25, DW_AT_external + .dwattr $C$DW$25, DW_AT_type(*$C$DW$T$87) + .dwattr $C$DW$25, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$25, DW_AT_TI_begin_line(0x25) + .dwattr $C$DW$25, DW_AT_TI_begin_column(0x09) + .dwattr $C$DW$25, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$25, DW_AT_decl_line(0x25) + .dwattr $C$DW$25, DW_AT_decl_column(0x09) + .dwattr $C$DW$25, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 37,column 25,is_stmt,address right_pos,isa 1 + + .dwfde $C$DW$CIE, right_pos +;---------------------------------------------------------------------- +; 37 | int32_t right_pos(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: right_pos * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +right_pos: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/motors.c",line 38,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 38 | return ROM_QEIPositionGet(QEI1_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON18 ; [DPU_V7M3_PIPE] |38| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |38| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |38| + MOV A2, A1 ; [DPU_V7M3_PIPE] |38| + LDR A1, $C$CON19 ; [DPU_V7M3_PIPE] |38| +$C$DW$26 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$26, DW_AT_low_pc(0x00) + .dwattr $C$DW$26, DW_AT_TI_call + .dwattr $C$DW$26, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |38| + ; CALL OCCURS {} ; [] |38| + .dwpsn file "../lib/motors.c",line 39,column 1,is_stmt,isa 1 +$C$DW$27 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$27, DW_AT_low_pc(0x00) + .dwattr $C$DW$27, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$25, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$25, DW_AT_TI_end_line(0x27) + .dwattr $C$DW$25, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$25 + + .sect ".text:left_speed" + .clink + .thumbfunc left_speed + .thumb + .global left_speed + +$C$DW$28 .dwtag DW_TAG_subprogram + .dwattr $C$DW$28, DW_AT_name("left_speed") + .dwattr $C$DW$28, DW_AT_low_pc(left_speed) + .dwattr $C$DW$28, DW_AT_high_pc(0x00) + .dwattr $C$DW$28, DW_AT_TI_symbol_name("left_speed") + .dwattr $C$DW$28, DW_AT_external + .dwattr $C$DW$28, DW_AT_type(*$C$DW$T$27) + .dwattr $C$DW$28, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$28, DW_AT_TI_begin_line(0x29) + .dwattr $C$DW$28, DW_AT_TI_begin_column(0x0a) + .dwattr $C$DW$28, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$28, DW_AT_decl_line(0x29) + .dwattr $C$DW$28, DW_AT_decl_column(0x0a) + .dwattr $C$DW$28, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 41,column 27,is_stmt,address left_speed,isa 1 + + .dwfde $C$DW$CIE, left_speed +;---------------------------------------------------------------------- +; 41 | uint32_t left_speed(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: left_speed * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +left_speed: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/motors.c",line 42,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 42 | return ROM_QEIVelocityGet(QEI0_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON20 ; [DPU_V7M3_PIPE] |42| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |42| + LDR A1, [A1, #40] ; [DPU_V7M3_PIPE] |42| + MOV A2, A1 ; [DPU_V7M3_PIPE] |42| + LDR A1, $C$CON21 ; [DPU_V7M3_PIPE] |42| +$C$DW$29 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$29, DW_AT_low_pc(0x00) + .dwattr $C$DW$29, DW_AT_TI_call + .dwattr $C$DW$29, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |42| + ; CALL OCCURS {} ; [] |42| + .dwpsn file "../lib/motors.c",line 43,column 1,is_stmt,isa 1 +$C$DW$30 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$30, DW_AT_low_pc(0x00) + .dwattr $C$DW$30, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$28, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$28, DW_AT_TI_end_line(0x2b) + .dwattr $C$DW$28, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$28 + + .sect ".text:right_speed" + .clink + .thumbfunc right_speed + .thumb + .global right_speed + +$C$DW$31 .dwtag DW_TAG_subprogram + .dwattr $C$DW$31, DW_AT_name("right_speed") + .dwattr $C$DW$31, DW_AT_low_pc(right_speed) + .dwattr $C$DW$31, DW_AT_high_pc(0x00) + .dwattr $C$DW$31, DW_AT_TI_symbol_name("right_speed") + .dwattr $C$DW$31, DW_AT_external + .dwattr $C$DW$31, DW_AT_type(*$C$DW$T$27) + .dwattr $C$DW$31, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$31, DW_AT_TI_begin_line(0x2c) + .dwattr $C$DW$31, DW_AT_TI_begin_column(0x0a) + .dwattr $C$DW$31, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$31, DW_AT_decl_line(0x2c) + .dwattr $C$DW$31, DW_AT_decl_column(0x0a) + .dwattr $C$DW$31, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 44,column 28,is_stmt,address right_speed,isa 1 + + .dwfde $C$DW$CIE, right_speed +;---------------------------------------------------------------------- +; 44 | uint32_t right_speed(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: right_speed * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +right_speed: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/motors.c",line 45,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 45 | return ROM_QEIVelocityGet(QEI1_BASE); +;---------------------------------------------------------------------- + LDR A1, $C$CON22 ; [DPU_V7M3_PIPE] |45| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |45| + LDR A1, [A1, #40] ; [DPU_V7M3_PIPE] |45| + MOV A2, A1 ; [DPU_V7M3_PIPE] |45| + LDR A1, $C$CON23 ; [DPU_V7M3_PIPE] |45| +$C$DW$32 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$32, DW_AT_low_pc(0x00) + .dwattr $C$DW$32, DW_AT_TI_call + .dwattr $C$DW$32, DW_AT_TI_indirect + + BLX A2 ; [DPU_V7M3_PIPE] |45| + ; CALL OCCURS {} ; [] |45| + .dwpsn file "../lib/motors.c",line 46,column 1,is_stmt,isa 1 +$C$DW$33 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$33, DW_AT_low_pc(0x00) + .dwattr $C$DW$33, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$31, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$31, DW_AT_TI_end_line(0x2e) + .dwattr $C$DW$31, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$31 + + .sect ".text:reset_enc" + .clink + .thumbfunc reset_enc + .thumb + .global reset_enc + +$C$DW$34 .dwtag DW_TAG_subprogram + .dwattr $C$DW$34, DW_AT_name("reset_enc") + .dwattr $C$DW$34, DW_AT_low_pc(reset_enc) + .dwattr $C$DW$34, DW_AT_high_pc(0x00) + .dwattr $C$DW$34, DW_AT_TI_symbol_name("reset_enc") + .dwattr $C$DW$34, DW_AT_external + .dwattr $C$DW$34, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$34, DW_AT_TI_begin_line(0x30) + .dwattr $C$DW$34, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$34, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$34, DW_AT_decl_line(0x30) + .dwattr $C$DW$34, DW_AT_decl_column(0x06) + .dwattr $C$DW$34, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 48,column 22,is_stmt,address reset_enc,isa 1 + + .dwfde $C$DW$CIE, reset_enc +;---------------------------------------------------------------------- +; 48 | void reset_enc(void) { +;---------------------------------------------------------------------- + +;***************************************************************************** +;* FUNCTION NAME: reset_enc * +;* * +;* Regs Modified : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Regs Used : A1,A2,A3,A4,V9,SP,LR,SR,D0,D0_hi,D1,D1_hi,D2,D2_hi, * +;* D3,D3_hi,D4,D4_hi,D5,D5_hi,D6,D6_hi,D7,D7_hi, * +;* FPEXC,FPSCR * +;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte * +;***************************************************************************** +reset_enc: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + PUSH {A4, LR} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 + .dwcfi save_reg_to_mem, 14, -4 + .dwcfi save_reg_to_mem, 3, -8 + .dwpsn file "../lib/motors.c",line 49,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 49 | ROM_QEIPositionSet(QEI0_BASE, 0); +;---------------------------------------------------------------------- + LDR A1, $C$CON24 ; [DPU_V7M3_PIPE] |49| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |49| + LDR A1, [A1, #16] ; [DPU_V7M3_PIPE] |49| + MOV A3, A1 ; [DPU_V7M3_PIPE] |49| + LDR A1, $C$CON25 ; [DPU_V7M3_PIPE] |49| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |49| +$C$DW$35 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$35, DW_AT_low_pc(0x00) + .dwattr $C$DW$35, DW_AT_TI_call + .dwattr $C$DW$35, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |49| + ; CALL OCCURS {} ; [] |49| + .dwpsn file "../lib/motors.c",line 50,column 5,is_stmt,isa 1 +;---------------------------------------------------------------------- +; 50 | ROM_QEIPositionSet(QEI1_BASE, 0); +;---------------------------------------------------------------------- + LDR A1, $C$CON24 ; [DPU_V7M3_PIPE] |50| + LDR A1, [A1, #0] ; [DPU_V7M3_PIPE] |50| + LDR A1, [A1, #16] ; [DPU_V7M3_PIPE] |50| + MOV A3, A1 ; [DPU_V7M3_PIPE] |50| + LDR A1, $C$CON26 ; [DPU_V7M3_PIPE] |50| + MOVS A2, #0 ; [DPU_V7M3_PIPE] |50| +$C$DW$36 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$36, DW_AT_low_pc(0x00) + .dwattr $C$DW$36, DW_AT_TI_call + .dwattr $C$DW$36, DW_AT_TI_indirect + + BLX A3 ; [DPU_V7M3_PIPE] |50| + ; CALL OCCURS {} ; [] |50| + .dwpsn file "../lib/motors.c",line 51,column 1,is_stmt,isa 1 +$C$DW$37 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$37, DW_AT_low_pc(0x00) + .dwattr $C$DW$37, DW_AT_TI_return + + POP {A4, PC} ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 + .dwcfi restore_reg, 3 + ; BRANCH OCCURS ; [] + .dwattr $C$DW$34, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$34, DW_AT_TI_end_line(0x33) + .dwattr $C$DW$34, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$34 + + .sect ".text:set_left" + .clink + .thumbfunc set_left + .thumb + .global set_left + +$C$DW$38 .dwtag DW_TAG_subprogram + .dwattr $C$DW$38, DW_AT_name("set_left") + .dwattr $C$DW$38, DW_AT_low_pc(set_left) + .dwattr $C$DW$38, DW_AT_high_pc(0x00) + .dwattr $C$DW$38, DW_AT_TI_symbol_name("set_left") + .dwattr $C$DW$38, DW_AT_external + .dwattr $C$DW$38, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$38, DW_AT_TI_begin_line(0x35) + .dwattr $C$DW$38, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$38, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$38, DW_AT_decl_line(0x35) + .dwattr $C$DW$38, DW_AT_decl_column(0x06) + .dwattr $C$DW$38, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 53,column 28,is_stmt,address set_left,isa 1 + + .dwfde $C$DW$CIE, set_left +$C$DW$39 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$39, DW_AT_name("speed") + .dwattr $C$DW$39, DW_AT_TI_symbol_name("speed") + .dwattr $C$DW$39, DW_AT_type(*$C$DW$T$16) + .dwattr $C$DW$39, DW_AT_location[DW_OP_regx 0x40] + + +;***************************************************************************** +;* FUNCTION NAME: set_left * +;* * +;* Regs Modified : SP * +;* Regs Used : SP,LR,D0 * +;* Local Frame Size : 0 Args + 4 Auto + 0 Save = 4 byte * +;***************************************************************************** +set_left: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + SUB SP, SP, #8 ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 +$C$DW$40 .dwtag DW_TAG_variable + .dwattr $C$DW$40, DW_AT_name("speed") + .dwattr $C$DW$40, DW_AT_TI_symbol_name("speed") + .dwattr $C$DW$40, DW_AT_type(*$C$DW$T$16) + .dwattr $C$DW$40, DW_AT_location[DW_OP_breg13 0] + +;---------------------------------------------------------------------- +; 53 | void set_left(float speed) { +; 54 | // TODO +;---------------------------------------------------------------------- + VSTR.32 S0, [SP, #0] ; [DPU_MERLIN_PIPE] |53| + .dwpsn file "../lib/motors.c",line 55,column 1,is_stmt,isa 1 + ADD SP, SP, #8 ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 +$C$DW$41 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$41, DW_AT_low_pc(0x00) + .dwattr $C$DW$41, DW_AT_TI_return + + BX LR ; [DPU_V7M3_PIPE] + ; BRANCH OCCURS ; [] + .dwattr $C$DW$38, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$38, DW_AT_TI_end_line(0x37) + .dwattr $C$DW$38, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$38 + + .sect ".text:set_right" + .clink + .thumbfunc set_right + .thumb + .global set_right + +$C$DW$42 .dwtag DW_TAG_subprogram + .dwattr $C$DW$42, DW_AT_name("set_right") + .dwattr $C$DW$42, DW_AT_low_pc(set_right) + .dwattr $C$DW$42, DW_AT_high_pc(0x00) + .dwattr $C$DW$42, DW_AT_TI_symbol_name("set_right") + .dwattr $C$DW$42, DW_AT_external + .dwattr $C$DW$42, DW_AT_TI_begin_file("../lib/motors.c") + .dwattr $C$DW$42, DW_AT_TI_begin_line(0x39) + .dwattr $C$DW$42, DW_AT_TI_begin_column(0x06) + .dwattr $C$DW$42, DW_AT_decl_file("../lib/motors.c") + .dwattr $C$DW$42, DW_AT_decl_line(0x39) + .dwattr $C$DW$42, DW_AT_decl_column(0x06) + .dwattr $C$DW$42, DW_AT_TI_max_frame_size(0x08) + .dwpsn file "../lib/motors.c",line 57,column 29,is_stmt,address set_right,isa 1 + + .dwfde $C$DW$CIE, set_right +$C$DW$43 .dwtag DW_TAG_formal_parameter + .dwattr $C$DW$43, DW_AT_name("speed") + .dwattr $C$DW$43, DW_AT_TI_symbol_name("speed") + .dwattr $C$DW$43, DW_AT_type(*$C$DW$T$16) + .dwattr $C$DW$43, DW_AT_location[DW_OP_regx 0x40] + + +;***************************************************************************** +;* FUNCTION NAME: set_right * +;* * +;* Regs Modified : SP * +;* Regs Used : SP,LR,D0 * +;* Local Frame Size : 0 Args + 4 Auto + 0 Save = 4 byte * +;***************************************************************************** +set_right: +;* --------------------------------------------------------------------------* + .dwcfi cfa_offset, 0 + SUB SP, SP, #8 ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 8 +$C$DW$44 .dwtag DW_TAG_variable + .dwattr $C$DW$44, DW_AT_name("speed") + .dwattr $C$DW$44, DW_AT_TI_symbol_name("speed") + .dwattr $C$DW$44, DW_AT_type(*$C$DW$T$16) + .dwattr $C$DW$44, DW_AT_location[DW_OP_breg13 0] + +;---------------------------------------------------------------------- +; 57 | void set_right(float speed) { +; 58 | // TODO +;---------------------------------------------------------------------- + VSTR.32 S0, [SP, #0] ; [DPU_MERLIN_PIPE] |57| + .dwpsn file "../lib/motors.c",line 59,column 1,is_stmt,isa 1 + ADD SP, SP, #8 ; [DPU_V7M3_PIPE] + .dwcfi cfa_offset, 0 +$C$DW$45 .dwtag DW_TAG_TI_branch + .dwattr $C$DW$45, DW_AT_low_pc(0x00) + .dwattr $C$DW$45, DW_AT_TI_return + + BX LR ; [DPU_V7M3_PIPE] + ; BRANCH OCCURS ; [] + .dwattr $C$DW$42, DW_AT_TI_end_file("../lib/motors.c") + .dwattr $C$DW$42, DW_AT_TI_end_line(0x3b) + .dwattr $C$DW$42, DW_AT_TI_end_column(0x01) + .dwendentry + .dwendtag $C$DW$42 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:init_motors" + .align 4 +||$C$CON1||: .bits 0x1000044,32 + + .align 4 +||$C$CON2||: .bits 0xf0004400,32 + + .align 4 +||$C$CON3||: .bits 0xf0004401,32 + + .align 4 +||$C$CON4||: .bits 0xf0000802,32 + + .align 4 +||$C$CON5||: .bits 0xf0000803,32 + + .align 4 +||$C$CON6||: .bits 0x1000020,32 + + .align 4 +||$C$CON7||: .bits 0x31806,32 + + .align 4 +||$C$CON8||: .bits 0x31c06,32 + + .align 4 +||$C$CON9||: .bits 0x21406,32 + + .align 4 +||$C$CON10||: .bits 0x21806,32 + + .align 4 +||$C$CON11||: .bits 0x40007000,32 + + .align 4 +||$C$CON12||: .bits 0x40006000,32 + + .align 4 +||$C$CON13||: .bits 0x1000034,32 + + .align 4 +||$C$CON14||: .bits 0x4002c000,32 + + .align 4 +||$C$CON15||: .bits 0x4002d000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:left_pos" + .align 4 +||$C$CON16||: .bits 0x1000034,32 + + .align 4 +||$C$CON17||: .bits 0x4002c000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:right_pos" + .align 4 +||$C$CON18||: .bits 0x1000034,32 + + .align 4 +||$C$CON19||: .bits 0x4002d000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:left_speed" + .align 4 +||$C$CON20||: .bits 0x1000034,32 + + .align 4 +||$C$CON21||: .bits 0x4002c000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:right_speed" + .align 4 +||$C$CON22||: .bits 0x1000034,32 + + .align 4 +||$C$CON23||: .bits 0x4002d000,32 + +;****************************************************************************** +;* CONSTANT TABLE * +;****************************************************************************** + .sect ".text:reset_enc" + .align 4 +||$C$CON24||: .bits 0x1000034,32 + + .align 4 +||$C$CON25||: .bits 0x4002c000,32 + + .align 4 +||$C$CON26||: .bits 0x4002d000,32 + + +;****************************************************************************** +;* BUILD ATTRIBUTES * +;****************************************************************************** + .battr "aeabi", Tag_File, 1, Tag_ABI_PCS_wchar_t(2) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_rounding(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_denormal(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_exceptions(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_number_model(1) + .battr "aeabi", Tag_File, 1, Tag_ABI_enum_size(0) + .battr "aeabi", Tag_File, 1, Tag_ABI_optimization_goals(5) + .battr "aeabi", Tag_File, 1, Tag_ABI_FP_optimization_goals(0) + .battr "TI", Tag_File, 1, Tag_Bitfield_layout(2) + .battr "TI", Tag_File, 1, Tag_FP_interface(0) + +;****************************************************************************** +;* TYPE INFORMATION * +;****************************************************************************** + +$C$DW$T$21 .dwtag DW_TAG_structure_type + .dwattr $C$DW$T$21, DW_AT_byte_size(0x10) +$C$DW$46 .dwtag DW_TAG_member + .dwattr $C$DW$46, DW_AT_type(*$C$DW$T$14) + .dwattr $C$DW$46, DW_AT_name("__max_align1") + .dwattr $C$DW$46, DW_AT_TI_symbol_name("__max_align1") + .dwattr $C$DW$46, DW_AT_data_member_location[DW_OP_plus_uconst 0x0] + .dwattr $C$DW$46, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$46, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$46, DW_AT_decl_line(0x7a) + .dwattr $C$DW$46, DW_AT_decl_column(0x0c) + +$C$DW$47 .dwtag DW_TAG_member + .dwattr $C$DW$47, DW_AT_type(*$C$DW$T$18) + .dwattr $C$DW$47, DW_AT_name("__max_align2") + .dwattr $C$DW$47, DW_AT_TI_symbol_name("__max_align2") + .dwattr $C$DW$47, DW_AT_data_member_location[DW_OP_plus_uconst 0x8] + .dwattr $C$DW$47, DW_AT_accessibility(DW_ACCESS_public) + .dwattr $C$DW$47, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$47, DW_AT_decl_line(0x7b) + .dwattr $C$DW$47, DW_AT_decl_column(0x0e) + + .dwattr $C$DW$T$21, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$21, DW_AT_decl_line(0x79) + .dwattr $C$DW$T$21, DW_AT_decl_column(0x10) + .dwendtag $C$DW$T$21 + +$C$DW$T$23 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$23, DW_AT_name("__max_align_t") + .dwattr $C$DW$T$23, DW_AT_type(*$C$DW$T$21) + .dwattr $C$DW$T$23, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$23, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/_types.h") + .dwattr $C$DW$T$23, DW_AT_decl_line(0x7c) + .dwattr $C$DW$T$23, DW_AT_decl_column(0x03) + +$C$DW$T$2 .dwtag DW_TAG_unspecified_type + .dwattr $C$DW$T$2, DW_AT_name("void") + +$C$DW$T$3 .dwtag DW_TAG_pointer_type + .dwattr $C$DW$T$3, DW_AT_type(*$C$DW$T$2) + .dwattr $C$DW$T$3, DW_AT_address_class(0x20) + +$C$DW$T$4 .dwtag DW_TAG_base_type + .dwattr $C$DW$T$4, DW_AT_encoding(DW_ATE_boolean) + .dwattr $C$DW$T$4, DW_AT_name("bool") + .dwattr $C$DW$T$4, DW_AT_byte_size(0x01) + +$C$DW$T$5 .dwtag DW_TAG_base_type + .dwattr $C$DW$T$5, DW_AT_encoding(DW_ATE_signed_char) + .dwattr $C$DW$T$5, DW_AT_name("signed char") + .dwattr $C$DW$T$5, DW_AT_byte_size(0x01) + +$C$DW$T$38 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$38, DW_AT_name("__int8_t") + .dwattr $C$DW$T$38, DW_AT_type(*$C$DW$T$5) + .dwattr $C$DW$T$38, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$38, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$38, DW_AT_decl_line(0x39) + .dwattr $C$DW$T$38, DW_AT_decl_column(0x16) + +$C$DW$T$39 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$39, DW_AT_name("__int_least8_t") + .dwattr $C$DW$T$39, DW_AT_type(*$C$DW$T$38) + .dwattr $C$DW$T$39, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$39, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/machine/_types.h") + .dwattr $C$DW$T$39, DW_AT_decl_line(0x58) + .dwattr $C$DW$T$39, DW_AT_decl_column(0x12) + +$C$DW$T$40 .dwtag DW_TAG_typedef + .dwattr $C$DW$T$40, DW_AT_name("int_least8_t") + .dwattr $C$DW$T$40, DW_AT_type(*$C$DW$T$39) + .dwattr $C$DW$T$40, DW_AT_language(DW_LANG_C) + .dwattr $C$DW$T$40, DW_AT_decl_file("C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include/sys/stdint.h") + .dwattr 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$C$DW$75, DW_AT_location[DW_OP_regx 0x48] + +$C$DW$76 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$76, DW_AT_name("D4_hi") + .dwattr $C$DW$76, DW_AT_location[DW_OP_regx 0x49] + +$C$DW$77 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$77, DW_AT_name("D5") + .dwattr $C$DW$77, DW_AT_location[DW_OP_regx 0x4a] + +$C$DW$78 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$78, DW_AT_name("D5_hi") + .dwattr $C$DW$78, DW_AT_location[DW_OP_regx 0x4b] + +$C$DW$79 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$79, DW_AT_name("D6") + .dwattr $C$DW$79, DW_AT_location[DW_OP_regx 0x4c] + +$C$DW$80 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$80, DW_AT_name("D6_hi") + .dwattr $C$DW$80, DW_AT_location[DW_OP_regx 0x4d] + +$C$DW$81 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$81, DW_AT_name("D7") + .dwattr $C$DW$81, DW_AT_location[DW_OP_regx 0x4e] + +$C$DW$82 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$82, DW_AT_name("D7_hi") + .dwattr $C$DW$82, DW_AT_location[DW_OP_regx 0x4f] + +$C$DW$83 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$83, DW_AT_name("D8") + .dwattr $C$DW$83, DW_AT_location[DW_OP_regx 0x50] + +$C$DW$84 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$84, DW_AT_name("D8_hi") + .dwattr $C$DW$84, DW_AT_location[DW_OP_regx 0x51] + +$C$DW$85 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$85, DW_AT_name("D9") + .dwattr $C$DW$85, DW_AT_location[DW_OP_regx 0x52] + +$C$DW$86 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$86, DW_AT_name("D9_hi") + .dwattr $C$DW$86, DW_AT_location[DW_OP_regx 0x53] + +$C$DW$87 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$87, DW_AT_name("D10") + .dwattr $C$DW$87, DW_AT_location[DW_OP_regx 0x54] + +$C$DW$88 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$88, DW_AT_name("D10_hi") + .dwattr $C$DW$88, DW_AT_location[DW_OP_regx 0x55] + +$C$DW$89 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$89, DW_AT_name("D11") + .dwattr $C$DW$89, DW_AT_location[DW_OP_regx 0x56] + +$C$DW$90 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$90, DW_AT_name("D11_hi") + .dwattr $C$DW$90, DW_AT_location[DW_OP_regx 0x57] + +$C$DW$91 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$91, DW_AT_name("D12") + .dwattr $C$DW$91, DW_AT_location[DW_OP_regx 0x58] + +$C$DW$92 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$92, DW_AT_name("D12_hi") + .dwattr $C$DW$92, DW_AT_location[DW_OP_regx 0x59] + +$C$DW$93 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$93, DW_AT_name("D13") + .dwattr $C$DW$93, DW_AT_location[DW_OP_regx 0x5a] + +$C$DW$94 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$94, DW_AT_name("D13_hi") + .dwattr $C$DW$94, DW_AT_location[DW_OP_regx 0x5b] + +$C$DW$95 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$95, DW_AT_name("D14") + .dwattr $C$DW$95, DW_AT_location[DW_OP_regx 0x5c] + +$C$DW$96 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$96, DW_AT_name("D14_hi") + .dwattr $C$DW$96, DW_AT_location[DW_OP_regx 0x5d] + +$C$DW$97 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$97, DW_AT_name("D15") + .dwattr $C$DW$97, DW_AT_location[DW_OP_regx 0x5e] + +$C$DW$98 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$98, DW_AT_name("D15_hi") + .dwattr $C$DW$98, DW_AT_location[DW_OP_regx 0x5f] + +$C$DW$99 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$99, DW_AT_name("FPEXC") + .dwattr $C$DW$99, DW_AT_location[DW_OP_reg18] + +$C$DW$100 .dwtag DW_TAG_TI_assign_register + .dwattr $C$DW$100, DW_AT_name("FPSCR") + .dwattr $C$DW$100, DW_AT_location[DW_OP_reg19] + + .dwendtag $C$DW$CU + diff --git a/CCS/mm/Debug/objects.mk b/CCS/mm/Debug/objects.mk new file mode 100644 index 0000000..0273a3d --- /dev/null +++ b/CCS/mm/Debug/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -l"C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/grlib/ccs/Debug/grlib.lib" -l"C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/usblib/ccs/Debug/usblib.lib" -l"C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b/driverlib/ccs/Debug/driverlib.lib" -llibc.a + diff --git a/CCS/mm/Debug/sources.mk b/CCS/mm/Debug/sources.mk new file mode 100644 index 0000000..7cdb361 --- /dev/null +++ b/CCS/mm/Debug/sources.mk @@ -0,0 +1,129 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +CFG_UPPER_SRCS := +CFG_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +PDE_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +INO_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +INO_DEPS := +GEN_CMDS := +GEN_FILES := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +PDE_DEPS := +GEN_MISC_DIRS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +GEN_OPTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +GEN_MISC_FILES := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +SA_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +GEN_MISC_DIRS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +GEN_CMDS__QUOTED := +GEN_MISC_FILES__QUOTED := +INO_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +GEN_FILES__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := +PDE_DEPS__QUOTED := +GEN_OPTS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ +lib \ +src/sysbios \ + diff --git a/CCS/mm/Debug/src/sysbios/subdir_rules.mk b/CCS/mm/Debug/src/sysbios/subdir_rules.mk new file mode 100644 index 0000000..c379752 --- /dev/null +++ b/CCS/mm/Debug/src/sysbios/subdir_rules.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes + diff --git a/CCS/mm/Debug/src/sysbios/subdir_vars.mk b/CCS/mm/Debug/src/sysbios/subdir_vars.mk new file mode 100644 index 0000000..b7693c7 --- /dev/null +++ b/CCS/mm/Debug/src/sysbios/subdir_vars.mk @@ -0,0 +1,15 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Add inputs and outputs from these tool invocations to the build variables +OBJ_SRCS += \ +../src/sysbios/BIOS.obj \ +../src/sysbios/m3_Hwi_asm.obj \ +../src/sysbios/m3_Hwi_asm_switch.obj \ +../src/sysbios/m3_IntrinsicsSupport_asm.obj \ +../src/sysbios/m3_TaskSupport_asm.obj + + diff --git a/CCS/mm/Debug/subdir_rules.mk b/CCS/mm/Debug/subdir_rules.mk new file mode 100644 index 0000000..0fc7c1b --- /dev/null +++ b/CCS/mm/Debug/subdir_rules.mk @@ -0,0 +1,29 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL = cmd.exe + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'Building file: "$<"' + @echo 'Invoking: ARM Compiler' + "C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/bin/armcl" -mv7M4 --code_state=16 --float_support=FPv4SPD16 -me --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" --define=ccs="ccs" --define=PART_TM4C123GH6PM --define=ccs --define=TIVAWARE -g --c99 --gcc --diag_warning=225 --diag_warning=255 --diag_wrap=off --display_error_number --gen_func_subsections=on --abi=eabi --preproc_with_compile --preproc_dependency="$(basename $( +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "EK_TM4C123GXL.h" + +#ifndef TI_DRIVERS_UART_DMA +#define TI_DRIVERS_UART_DMA 0 +#endif + +/* + * =============================== DMA =============================== + */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(dmaControlTable, 1024) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=1024 +#elif defined(__GNUC__) +__attribute__ ((aligned (1024))) +#endif +static tDMAControlTable dmaControlTable[32]; +static bool dmaInitialized = false; + +/* Hwi_Struct used in the initDMA Hwi_construct call */ +static Hwi_Struct dmaHwiStruct; + +/* + * ======== dmaErrorHwi ======== + */ +static Void dmaErrorHwi(UArg arg) +{ + System_printf("DMA error code: %d\n", uDMAErrorStatusGet()); + uDMAErrorStatusClear(); + System_abort("DMA error!!"); +} + +/* + * ======== EK_TM4C123GXL_initDMA ======== + */ +void EK_TM4C123GXL_initDMA(void) +{ + Error_Block eb; + Hwi_Params hwiParams; + + if (!dmaInitialized) { + Error_init(&eb); + Hwi_Params_init(&hwiParams); + Hwi_construct(&(dmaHwiStruct), INT_UDMAERR, dmaErrorHwi, + &hwiParams, &eb); + if (Error_check(&eb)) { + System_abort("Couldn't construct DMA error hwi"); + } + + SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA); + uDMAEnable(); + uDMAControlBaseSet(dmaControlTable); + + dmaInitialized = true; + } +} + +/* + * =============================== General =============================== + */ +/* + * ======== EK_TM4C123GXL_initGeneral ======== + */ +void EK_TM4C123GXL_initGeneral(void) +{ + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); + SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); +} + +/* + * =============================== GPIO =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(GPIOTiva_config, ".const:GPIOTiva_config") +#endif + +#include +#include + +/* + * Array of Pin configurations + * NOTE: The order of the pin configurations must coincide with what was + * defined in EK_TM4C123GXL.h + * NOTE: Pins not used for interrupts should be placed at the end of the + * array. Callback entries can be omitted from callbacks array to + * reduce memory usage. + */ +GPIO_PinConfig gpioPinConfigs[] = { + /* Input pins */ + /* EK_TM4C123GXL_GPIO_SW1 */ + GPIOTiva_PF_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_RISING, + /* EK_TM4C123GXL_GPIO_SW2 */ + GPIOTiva_PF_0 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_RISING, + + /* Output pins */ + /* EK_TM4C123GXL_LED_RED */ + GPIOTiva_PF_1 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + /* EK_TM4C123GXL_LED_BLUE */ + GPIOTiva_PF_2 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + /* EK_TM4C123GXL_LED_GREEN */ + GPIOTiva_PF_3 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW +}; + +/* + * Array of callback function pointers + * NOTE: The order of the pin configurations must coincide with what was + * defined in EK_TM4C123GXL.h + * NOTE: Pins not used for interrupts can be omitted from callbacks array to + * reduce memory usage (if placed at end of gpioPinConfigs array). + */ +GPIO_CallbackFxn gpioCallbackFunctions[] = { + NULL, /* EK_TM4C123GXL_GPIO_SW1 */ + NULL /* EK_TM4C123GXL_GPIO_SW2 */ +}; + +/* The device-specific GPIO_config structure */ +const GPIOTiva_Config GPIOTiva_config = { + .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + .intPriority = (~0) +}; + +/* + * ======== EK_TM4C123GXL_initGPIO ======== + */ +void EK_TM4C123GXL_initGPIO(void) +{ + /* EK_TM4C123GXL_GPIO_SW2 - PF0 requires unlocking before configuration */ + HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= GPIO_PIN_0; + GPIOPinTypeGPIOInput(GPIO_PORTF_BASE, GPIO_PIN_0); + + /* Initialize peripheral and pins */ + GPIO_init(); +} + +/* + * =============================== I2C =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(I2C_config, ".const:I2C_config") +#pragma DATA_SECTION(i2cTivaHWAttrs, ".const:i2cTivaHWAttrs") +#endif + +#include +#include + +I2CTiva_Object i2cTivaObjects[EK_TM4C123GXL_I2CCOUNT]; + +const I2CTiva_HWAttrs i2cTivaHWAttrs[EK_TM4C123GXL_I2CCOUNT] = { + { + .baseAddr = I2C1_BASE, + .intNum = INT_I2C1, + .intPriority = (~0) + }, + { + .baseAddr = I2C3_BASE, + .intNum = INT_I2C3, + .intPriority = (~0) + }, +}; + +const I2C_Config I2C_config[] = { + { + .fxnTablePtr = &I2CTiva_fxnTable, + .object = &i2cTivaObjects[0], + .hwAttrs = &i2cTivaHWAttrs[0] + }, + { + .fxnTablePtr = &I2CTiva_fxnTable, + .object = &i2cTivaObjects[1], + .hwAttrs = &i2cTivaHWAttrs[1] + }, + {NULL, NULL, NULL} +}; + +/* + * ======== EK_TM4C123GXL_initI2C ======== + */ +void EK_TM4C123GXL_initI2C(void) +{ + /* I2C1 Init */ + /* Enable the peripheral */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C1); + + /* Configure the appropriate pins to be I2C instead of GPIO. */ + GPIOPinConfigure(GPIO_PA6_I2C1SCL); + GPIOPinConfigure(GPIO_PA7_I2C1SDA); + GPIOPinTypeI2CSCL(GPIO_PORTA_BASE, GPIO_PIN_6); + GPIOPinTypeI2C(GPIO_PORTA_BASE, GPIO_PIN_7); + + /* I2C3 Init */ + /* + * NOTE: TI-RTOS examples configure pins PD0 & PD1 for SSI3 or I2C3. Thus, + * a conflict occurs when the I2C & SPI drivers are used simultaneously in + * an application. Modify the pin mux settings in this file and resolve the + * conflict before running your the application. + */ + /* Enable the peripheral */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C3); + + /* Configure the appropriate pins to be I2C instead of GPIO. */ + GPIOPinConfigure(GPIO_PD0_I2C3SCL); + GPIOPinConfigure(GPIO_PD1_I2C3SDA); + GPIOPinTypeI2CSCL(GPIO_PORTD_BASE, GPIO_PIN_0); + GPIOPinTypeI2C(GPIO_PORTD_BASE, GPIO_PIN_1); + + /* + * These GPIOs are connected to PD0 and PD1 and need to be brought into a + * GPIO input state so they don't interfere with I2C communications. + */ + GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_6); + GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_7); + + I2C_init(); +} + +/* + * =============================== PWM =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(PWM_config, ".const:PWM_config") +#pragma DATA_SECTION(pwmTivaHWAttrs, ".const:pwmTivaHWAttrs") +#endif + +#include +#include + +PWMTiva_Object pwmTivaObjects[EK_TM4C123GXL_PWMCOUNT]; + +const PWMTiva_HWAttrs pwmTivaHWAttrs[EK_TM4C123GXL_PWMCOUNT] = { + { + .baseAddr = PWM1_BASE, + .pwmOutput = PWM_OUT_6, + .pwmGenOpts = PWM_GEN_MODE_DOWN | PWM_GEN_MODE_DBG_RUN + }, + { + .baseAddr = PWM1_BASE, + .pwmOutput = PWM_OUT_7, + .pwmGenOpts = PWM_GEN_MODE_DOWN | PWM_GEN_MODE_DBG_RUN + } +}; + +const PWM_Config PWM_config[] = { + { + .fxnTablePtr = &PWMTiva_fxnTable, + .object = &pwmTivaObjects[0], + .hwAttrs = &pwmTivaHWAttrs[0] + }, + { + .fxnTablePtr = &PWMTiva_fxnTable, + .object = &pwmTivaObjects[1], + .hwAttrs = &pwmTivaHWAttrs[1] + }, + {NULL, NULL, NULL} +}; + +/* + * ======== EK_TM4C123GXL_initPWM ======== + */ +void EK_TM4C123GXL_initPWM(void) +{ + /* Enable PWM peripherals */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM1); + + /* + * Enable PWM output on GPIO pins. Board_LED1 and Board_LED2 are now + * controlled by PWM peripheral - Do not use GPIO APIs. + */ + GPIOPinConfigure(GPIO_PF2_M1PWM6); + GPIOPinConfigure(GPIO_PF3_M1PWM7); + GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_2 |GPIO_PIN_3); + + PWM_init(); +} + +/* + * =============================== SDSPI =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(SDSPI_config, ".const:SDSPI_config") +#pragma DATA_SECTION(sdspiTivaHWattrs, ".const:sdspiTivaHWattrs") +#endif + +#include +#include + +SDSPITiva_Object sdspiTivaObjects[EK_TM4C123GXL_SDSPICOUNT]; + +const SDSPITiva_HWAttrs sdspiTivaHWattrs[EK_TM4C123GXL_SDSPICOUNT] = { + { + .baseAddr = SSI2_BASE, + + .portSCK = GPIO_PORTB_BASE, + .pinSCK = GPIO_PIN_4, + .portMISO = GPIO_PORTB_BASE, + .pinMISO = GPIO_PIN_6, + .portMOSI = GPIO_PORTB_BASE, + .pinMOSI = GPIO_PIN_7, + .portCS = GPIO_PORTA_BASE, + .pinCS = GPIO_PIN_5, + } +}; + +const SDSPI_Config SDSPI_config[] = { + { + .fxnTablePtr = &SDSPITiva_fxnTable, + .object = &sdspiTivaObjects[0], + .hwAttrs = &sdspiTivaHWattrs[0] + }, + {NULL, NULL, NULL} +}; + +/* + * ======== EK_TM4C123GXL_initSDSPI ======== + */ +void EK_TM4C123GXL_initSDSPI(void) +{ + /* Enable the peripherals used by the SD Card */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); + + /* Configure pad settings */ + GPIOPadConfigSet(GPIO_PORTB_BASE, + GPIO_PIN_4 | GPIO_PIN_7, + GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD); + + GPIOPadConfigSet(GPIO_PORTB_BASE, + GPIO_PIN_6, + GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU); + + GPIOPadConfigSet(GPIO_PORTA_BASE, + GPIO_PIN_5, + GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD); + + GPIOPinConfigure(GPIO_PB4_SSI2CLK); + GPIOPinConfigure(GPIO_PB6_SSI2RX); + GPIOPinConfigure(GPIO_PB7_SSI2TX); + + /* + * These GPIOs are connected to PB6 and PB7 and need to be brought into a + * GPIO input state so they don't interfere with SPI communications. + */ + GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_0); + GPIOPinTypeGPIOInput(GPIO_PORTD_BASE, GPIO_PIN_1); + + SDSPI_init(); +} + +/* + * =============================== SPI =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(SPI_config, ".const:SPI_config") +#pragma DATA_SECTION(spiTivaDMAHWAttrs, ".const:spiTivaDMAHWAttrs") +#endif + +#include +#include + +SPITivaDMA_Object spiTivaDMAObjects[EK_TM4C123GXL_SPICOUNT]; + +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_ALIGN(spiTivaDMAscratchBuf, 32) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma data_alignment=32 +#elif defined(__GNUC__) +__attribute__ ((aligned (32))) +#endif +uint32_t spiTivaDMAscratchBuf[EK_TM4C123GXL_SPICOUNT]; + +const SPITivaDMA_HWAttrs spiTivaDMAHWAttrs[EK_TM4C123GXL_SPICOUNT] = { + { + .baseAddr = SSI0_BASE, + .intNum = INT_SSI0, + .intPriority = (~0), + .scratchBufPtr = &spiTivaDMAscratchBuf[0], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CHANNEL_SSI0RX, + .txChannelIndex = UDMA_CHANNEL_SSI0TX, + .channelMappingFxn = uDMAChannelAssign, + .rxChannelMappingFxnArg = UDMA_CH10_SSI0RX, + .txChannelMappingFxnArg = UDMA_CH11_SSI0TX + }, + { + .baseAddr = SSI2_BASE, + .intNum = INT_SSI2, + .intPriority = (~0), + .scratchBufPtr = &spiTivaDMAscratchBuf[1], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_SEC_CHANNEL_UART2RX_12, + .txChannelIndex = UDMA_SEC_CHANNEL_UART2TX_13, + .channelMappingFxn = uDMAChannelAssign, + .rxChannelMappingFxnArg = UDMA_CH12_SSI2RX, + .txChannelMappingFxnArg = UDMA_CH13_SSI2TX + }, + { + .baseAddr = SSI3_BASE, + .intNum = INT_SSI3, + .intPriority = (~0), + .scratchBufPtr = &spiTivaDMAscratchBuf[2], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_SEC_CHANNEL_TMR2A_14, + .txChannelIndex = UDMA_SEC_CHANNEL_TMR2B_15, + .channelMappingFxn = uDMAChannelAssign, + .rxChannelMappingFxnArg = UDMA_CH14_SSI3RX, + .txChannelMappingFxnArg = UDMA_CH15_SSI3TX + } +}; + +const SPI_Config SPI_config[] = { + { + .fxnTablePtr = &SPITivaDMA_fxnTable, + .object = &spiTivaDMAObjects[0], + .hwAttrs = &spiTivaDMAHWAttrs[0] + }, + { + .fxnTablePtr = &SPITivaDMA_fxnTable, + .object = &spiTivaDMAObjects[1], + .hwAttrs = &spiTivaDMAHWAttrs[1] + }, + { + .fxnTablePtr = &SPITivaDMA_fxnTable, + .object = &spiTivaDMAObjects[2], + .hwAttrs = &spiTivaDMAHWAttrs[2] + }, + {NULL, NULL, NULL}, +}; + +/* + * ======== EK_TM4C123GXL_initSPI ======== + */ +void EK_TM4C123GXL_initSPI(void) +{ + /* SPI0 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); + + /* Need to unlock PF0 */ + GPIOPinConfigure(GPIO_PA2_SSI0CLK); + GPIOPinConfigure(GPIO_PA3_SSI0FSS); + GPIOPinConfigure(GPIO_PA4_SSI0RX); + GPIOPinConfigure(GPIO_PA5_SSI0TX); + + GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | + GPIO_PIN_4 | GPIO_PIN_5); + + /* SSI2 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); + + GPIOPinConfigure(GPIO_PB4_SSI2CLK); + GPIOPinConfigure(GPIO_PB5_SSI2FSS); + GPIOPinConfigure(GPIO_PB6_SSI2RX); + GPIOPinConfigure(GPIO_PB7_SSI2TX); + + GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_5 | + GPIO_PIN_6 | GPIO_PIN_7); + + /* SSI3 */ + /* + * NOTE: TI-RTOS examples configure pins PD0 & PD1 for SSI3 or I2C3. Thus, + * a conflict occurs when the I2C & SPI drivers are used simultaneously in + * an application. Modify the pin mux settings in this file and resolve the + * conflict before running your the application. + */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); + + GPIOPinConfigure(GPIO_PD0_SSI3CLK); + GPIOPinConfigure(GPIO_PD1_SSI3FSS); + GPIOPinConfigure(GPIO_PD2_SSI3RX); + GPIOPinConfigure(GPIO_PD3_SSI3TX); + + GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | + GPIO_PIN_2 | GPIO_PIN_3); + + EK_TM4C123GXL_initDMA(); + SPI_init(); +} + +/* + * =============================== UART =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(UART_config, ".const:UART_config") +#pragma DATA_SECTION(uartTivaHWAttrs, ".const:uartTivaHWAttrs") +#endif + +#include +#if TI_DRIVERS_UART_DMA +#include + +UARTTivaDMA_Object uartTivaObjects[EK_TM4C123GXL_UARTCOUNT]; + +const UARTTivaDMA_HWAttrs uartTivaHWAttrs[EK_TM4C123GXL_UARTCOUNT] = { + { + .baseAddr = UART0_BASE, + .intNum = INT_UART0, + .intPriority = (~0), + .rxChannelIndex = UDMA_CH8_UART0RX, + .txChannelIndex = UDMA_CH9_UART0TX, + } +}; + +const UART_Config UART_config[] = { + { + .fxnTablePtr = &UARTTivaDMA_fxnTable, + .object = &uartTivaObjects[0], + .hwAttrs = &uartTivaHWAttrs[0] + }, + {NULL, NULL, NULL} +}; +#else +#include + +UARTTiva_Object uartTivaObjects[EK_TM4C123GXL_UARTCOUNT]; +unsigned char uartTivaRingBuffer[EK_TM4C123GXL_UARTCOUNT][32]; + +/* UART configuration structure */ +const UARTTiva_HWAttrs uartTivaHWAttrs[EK_TM4C123GXL_UARTCOUNT] = { + { + .baseAddr = UART0_BASE, + .intNum = INT_UART0, + .intPriority = (~0), + .flowControl = UART_FLOWCONTROL_NONE, + .ringBufPtr = uartTivaRingBuffer[0], + .ringBufSize = sizeof(uartTivaRingBuffer[0]) + } +}; + +const UART_Config UART_config[] = { + { + .fxnTablePtr = &UARTTiva_fxnTable, + .object = &uartTivaObjects[0], + .hwAttrs = &uartTivaHWAttrs[0] + }, + {NULL, NULL, NULL} +}; +#endif /* TI_DRIVERS_UART_DMA */ + +/* + * ======== EK_TM4C123GXL_initUART ======== + */ +void EK_TM4C123GXL_initUART(void) +{ + /* Enable and configure the peripherals used by the uart. */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + GPIOPinConfigure(GPIO_PA0_U0RX); + GPIOPinConfigure(GPIO_PA1_U0TX); + GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); + + /* Initialize the UART driver */ +#if TI_DRIVERS_UART_DMA + EK_TM4C123GXL_initDMA(); +#endif + UART_init(); +} + +/* + * =============================== USB =============================== + */ +/* + * ======== EK_TM4C123GXL_initUSB ======== + * This function just turns on the USB + */ +void EK_TM4C123GXL_initUSB(EK_TM4C123GXL_USBMode usbMode) +{ + /* Enable the USB peripheral and PLL */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_USB0); + SysCtlUSBPLLEnable(); + + /* Setup pins for USB operation */ + GPIOPinTypeUSBAnalog(GPIO_PORTD_BASE, GPIO_PIN_4 | GPIO_PIN_5); + + if (usbMode == EK_TM4C123GXL_USBHOST) { + System_abort("USB host not supported\n"); + } +} + +/* + * =============================== Watchdog =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(Watchdog_config, ".const:Watchdog_config") +#pragma DATA_SECTION(watchdogTivaHWAttrs, ".const:watchdogTivaHWAttrs") +#endif + +#include +#include + +WatchdogTiva_Object watchdogTivaObjects[EK_TM4C123GXL_WATCHDOGCOUNT]; + +const WatchdogTiva_HWAttrs watchdogTivaHWAttrs[EK_TM4C123GXL_WATCHDOGCOUNT] = { + { + .baseAddr = WATCHDOG0_BASE, + .intNum = INT_WATCHDOG, + .intPriority = (~0), + .reloadValue = 80000000 // 1 second period at default CPU clock freq + }, +}; + +const Watchdog_Config Watchdog_config[] = { + { + .fxnTablePtr = &WatchdogTiva_fxnTable, + .object = &watchdogTivaObjects[0], + .hwAttrs = &watchdogTivaHWAttrs[0] + }, + {NULL, NULL, NULL}, +}; + +/* + * ======== EK_TM4C123GXL_initWatchdog ======== + * + * NOTE: To use the other watchdog timer with base address WATCHDOG1_BASE, + * an additional function call may need be made to enable PIOSC. Enabling + * WDOG1 does not do this. Enabling another peripheral that uses PIOSC + * such as ADC0 or SSI0, however, will do so. Example: + * + * SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); + * SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG1); + * + * See the following forum post for more information: + * http://e2e.ti.com/support/microcontrollers/stellaris_arm_cortex-m3_microcontroller/f/471/p/176487/654390.aspx#654390 + */ +void EK_TM4C123GXL_initWatchdog(void) +{ + /* Enable peripherals used by Watchdog */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_WDOG0); + + Watchdog_init(); +} + +/* + * =============================== WiFi =============================== + */ +/* Place into subsections to allow the TI linker to remove items properly */ +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(WiFi_config, ".const:WiFi_config") +#pragma DATA_SECTION(wiFiCC3100HWAttrs, ".const:wiFiCC3100HWAttrs") +#endif + +#include +#include + +WiFiCC3100_Object wiFiCC3100Objects[EK_TM4C123GXL_WIFICOUNT]; + +const WiFiCC3100_HWAttrs wiFiCC3100HWAttrs[EK_TM4C123GXL_WIFICOUNT] = { + { + .irqPort = GPIO_PORTB_BASE, + .irqPin = GPIO_PIN_2, + .irqIntNum = INT_GPIOB, + + .csPort = GPIO_PORTE_BASE, + .csPin = GPIO_PIN_0, + + .enPort = GPIO_PORTE_BASE, + .enPin = GPIO_PIN_4 + } +}; + +const WiFi_Config WiFi_config[] = { + { + .fxnTablePtr = &WiFiCC3100_fxnTable, + .object = &wiFiCC3100Objects[0], + .hwAttrs = &wiFiCC3100HWAttrs[0] + }, + {NULL,NULL, NULL}, +}; + +/* + * ======== EK_TM4C123GXL_initWiFi ======== + */ +void EK_TM4C123GXL_initWiFi(void) +{ + /* Configure EN & CS pins to disable CC3100 */ + GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_4); + GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, GPIO_PIN_0); + GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_4, 0); + + /* Configure SSI2 for CC3100 */ + SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); + GPIOPinConfigure(GPIO_PB4_SSI2CLK); + GPIOPinConfigure(GPIO_PB6_SSI2RX); + GPIOPinConfigure(GPIO_PB7_SSI2TX); + GPIOPinTypeSSI(GPIO_PORTB_BASE, GPIO_PIN_4 | GPIO_PIN_6 | GPIO_PIN_7); + + /* Configure IRQ pin */ + GPIOPinTypeGPIOInput(GPIO_PORTB_BASE, GPIO_PIN_2); + GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_STD_WPD); + GPIOIntTypeSet(GPIO_PORTB_BASE, GPIO_PIN_2, GPIO_RISING_EDGE); + + SPI_init(); + EK_TM4C123GXL_initDMA(); + + WiFi_init(); +} diff --git a/CCS/mm/EK_TM4C123GXL.cmd b/CCS/mm/EK_TM4C123GXL.cmd new file mode 100644 index 0000000..95aba1d --- /dev/null +++ b/CCS/mm/EK_TM4C123GXL.cmd @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * ======== EK_TM4C123GXL.cmd ======== + * Define the memory block start/length for the EK_TM4C123GXL M4 + */ + +MEMORY +{ + FLASH (RX) : origin = 0x00000000, length = 0x00040000 + SRAM (RWX) : origin = 0x20000000, length = 0x00008000 +} + +/* Section allocation in memory */ + +SECTIONS +{ + .text : > FLASH + .const : > FLASH + .cinit : > FLASH + .pinit : > FLASH + .init_array : > FLASH + + .data : > SRAM + .bss : > SRAM + .sysmem : > SRAM + .stack : > SRAM +} diff --git a/CCS/mm/EK_TM4C123GXL.h b/CCS/mm/EK_TM4C123GXL.h new file mode 100644 index 0000000..162f4a5 --- /dev/null +++ b/CCS/mm/EK_TM4C123GXL.h @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** ============================================================================ + * @file EK_TM4C123GXL.h + * + * @brief EK_TM4C123GXL Board Specific APIs + * + * The EK_TM4C123GXL header file should be included in an application as + * follows: + * @code + * #include + * @endcode + * + * ============================================================================ + */ +#ifndef __EK_TM4C123GXL_H +#define __EK_TM4C123GXL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* LEDs on EK_TM4C123GXL are active high. */ +#define EK_TM4C123GXL_LED_OFF (0) +#define EK_TM4C123GXL_LED_ON (1) + +/*! + * @def EK_TM4C123GXL_GPIOName + * @brief Enum of GPIO names on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_GPIOName { + EK_TM4C123GXL_SW1 = 0, + EK_TM4C123GXL_SW2, + EK_TM4C123GXL_LED_RED, + EK_TM4C123GXL_LED_BLUE, + EK_TM4C123GXL_LED_GREEN, + + EK_TM4C123GXL_GPIOCOUNT +} EK_TM4C123GXL_GPIOName; + +/*! + * @def EK_TM4C123GXL_I2CName + * @brief Enum of I2C names on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_I2CName { + EK_TM4C123GXL_I2C0 = 0, + EK_TM4C123GXL_I2C3, + + EK_TM4C123GXL_I2CCOUNT +} EK_TM4C123GXL_I2CName; + +/*! + * @def EK_TM4C123GXL_PWMName + * @brief Enum of PWM names on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_PWMName { + EK_TM4C123GXL_PWM6 = 0, + EK_TM4C123GXL_PWM7, + + EK_TM4C123GXL_PWMCOUNT +} EK_TM4C123GXL_PWMName; + +/*! + * @def EK_TM4C123GXL_SDSPIName + * @brief Enum of SDSPI names on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_SDSPIName { + EK_TM4C123GXL_SDSPI0 = 0, + + EK_TM4C123GXL_SDSPICOUNT +} EK_TM4C123GXL_SDSPIName; + +/*! + * @def EK_TM4C123GXL_SPIName + * @brief Enum of SPI names on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_SPIName { + EK_TM4C123GXL_SPI0 = 0, + EK_TM4C123GXL_SPI2, + EK_TM4C123GXL_SPI3, + + EK_TM4C123GXL_SPICOUNT +} EK_TM4C123GXL_SPIName; + +/*! + * @def EK_TM4C123GXL_UARTName + * @brief Enum of UARTs on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_UARTName { + EK_TM4C123GXL_UART0 = 0, + + EK_TM4C123GXL_UARTCOUNT +} EK_TM4C123GXL_UARTName; + +/*! + * @def EK_TM4C123GXL_USBMode + * @brief Enum of USB setup function on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_USBMode { + EK_TM4C123GXL_USBDEVICE, + EK_TM4C123GXL_USBHOST +} EK_TM4C123GXL_USBMode; + +/*! + * @def EK_TM4C123GXL_WatchdogName + * @brief Enum of Watchdogs on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_WatchdogName { + EK_TM4C123GXL_WATCHDOG0 = 0, + + EK_TM4C123GXL_WATCHDOGCOUNT +} EK_TM4C123GXL_WatchdogName; + +/*! + * @def EK_TM4C123GXL_WiFiName + * @brief Enum of WiFi names on the EK_TM4C123GXL dev board + */ +typedef enum EK_TM4C123GXL_WiFiName { + EK_TM4C123GXL_WIFI = 0, + + EK_TM4C123GXL_WIFICOUNT +} EK_TM4C123GXL_WiFiName; + +/*! + * @brief Initialize board specific DMA settings + * + * This function creates a hwi in case the DMA controller creates an error + * interrrupt, enables the DMA and supplies it with a uDMA control table. + */ +extern void EK_TM4C123GXL_initDMA(void); + +/*! + * @brief Initialize the general board specific settings + * + * This function initializes the general board specific settings. + * This includes: + * - Flash wait states based on the process + * - Disable clock source to watchdog module + * - Enable clock sources for peripherals + */ +extern void EK_TM4C123GXL_initGeneral(void); + +/*! + * @brief Initialize board specific GPIO settings + * + * This function initializes the board specific GPIO settings and + * then calls the GPIO_init API to initialize the GPIO module. + * + * The GPIOs controlled by the GPIO module are determined by the GPIO_PinConfig + * variable. + */ +extern void EK_TM4C123GXL_initGPIO(void); + +/*! + * @brief Initialize board specific I2C settings + * + * This function initializes the board specific I2C settings and then calls + * the I2C_init API to initialize the I2C module. + * + * The I2C peripherals controlled by the I2C module are determined by the + * I2C_config variable. + */ +extern void EK_TM4C123GXL_initI2C(void); + +/*! + * @brief Initialize board specific PWM settings + * + * This function initializes the board specific PWM settings and then calls + * the PWM_init API to initialize the PWM module. + * + * The PWM peripherals controlled by the PWM module are determined by the + * PWM_config variable. + */ +extern void EK_TM4C123GXL_initPWM(void); + +/*! + * @brief Initialize board specific SDSPI settings + * + * This function initializes the board specific SDSPI settings and then calls + * the SDSPI_init API to initialize the SDSPI module. + * + * The SDSPI peripherals controlled by the SDSPI module are determined by the + * SDSPI_config variable. + */ +extern void EK_TM4C123GXL_initSDSPI(void); + +/*! + * @brief Initialize board specific SPI settings + * + * This function initializes the board specific SPI settings and then calls + * the SPI_init API to initialize the SPI module. + * + * The SPI peripherals controlled by the SPI module are determined by the + * SPI_config variable. + */ +extern void EK_TM4C123GXL_initSPI(void); + +/*! + * @brief Initialize board specific UART settings + * + * This function initializes the board specific UART settings and then calls + * the UART_init API to initialize the UART module. + * + * The UART peripherals controlled by the UART module are determined by the + * UART_config variable. + */ +extern void EK_TM4C123GXL_initUART(void); + +/*! + * @brief Initialize board specific USB settings + * + * This function initializes the board specific USB settings and pins based on + * the USB mode of operation. + * + * @param usbMode USB mode of operation + */ +extern void EK_TM4C123GXL_initUSB(EK_TM4C123GXL_USBMode usbMode); + +/*! + * @brief Initialize board specific Watchdog settings + * + * This function initializes the board specific Watchdog settings and then + * calls the Watchdog_init API to initialize the Watchdog module. + * + * The Watchdog peripherals controlled by the Watchdog module are determined + * by the Watchdog_config variable. + */ +extern void EK_TM4C123GXL_initWatchdog(void); + +/*! + * @brief Initialize board specific WiFi settings + * + * This function initializes the board specific WiFi settings and then calls + * the WiFi_init API to initialize the WiFi module. + * + * The hardware resources controlled by the WiFi module are determined by the + * WiFi_config variable. + * + * A SimpleLink CC3100 device or module is required and must be connected to + * use the WiFi driver. + */ +extern void EK_TM4C123GXL_initWiFi(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __EK_TM4C123GXL_H */ diff --git a/CCS/mm/gpiointerrupt.cfg b/CCS/mm/gpiointerrupt.cfg new file mode 100644 index 0000000..969a384 --- /dev/null +++ b/CCS/mm/gpiointerrupt.cfg @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2015-2016, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + + +/* ================ Clock configuration ================ */ +var Clock = xdc.useModule('ti.sysbios.knl.Clock'); +/* + * Default value is family dependent. For example, Linux systems often only + * support a minimum period of 10000 us and multiples of 10000 us. + * TI platforms have a default of 1000 us. + */ +Clock.tickPeriod = 1000; + + + +/* ================ Defaults (module) configuration ================ */ +var Defaults = xdc.useModule('xdc.runtime.Defaults'); +/* + * A flag to allow module names to be loaded on the target. Module name + * strings are placed in the .const section for debugging purposes. + * + * Pick one: + * - true (default) + * Setting this parameter to true will include name strings in the .const + * section so that Errors and Asserts are easier to debug. + * - false + * Setting this parameter to false will reduce footprint in the .const + * section. As a result, Error and Assert messages will contain an + * "unknown module" prefix instead of the actual module name. + */ +Defaults.common$.namedModule = true; +//Defaults.common$.namedModule = false; + + + +/* ================ Error configuration ================ */ +var Error = xdc.useModule('xdc.runtime.Error'); +/* + * This function is called to handle all raised errors, but unlike + * Error.raiseHook, this function is responsible for completely handling the + * error with an appropriately initialized Error_Block. + * + * Pick one: + * - Error.policyDefault (default) + * Calls Error.raiseHook with an initialized Error_Block structure and logs + * the error using the module's logger. + * - Error.policySpin + * Simple alternative that traps on a while(1) loop for minimized target + * footprint. + * Using Error.policySpin, the Error.raiseHook will NOT called. + */ +Error.policyFxn = Error.policyDefault; +//Error.policyFxn = Error.policySpin; + +/* + * If Error.policyFxn is set to Error.policyDefault, this function is called + * whenever an error is raised by the Error module. + * + * Pick one: + * - Error.print (default) + * Errors are formatted and output via System_printf() for easier + * debugging. + * - null + * Errors are not formatted or logged. This option reduces code footprint. + * - non-null function + * Errors invoke custom user function. See the Error module documentation + * for more details. + */ +Error.raiseHook = Error.print; +//Error.raiseHook = null; +//Error.raiseHook = "&myErrorFxn"; + +/* + * If Error.policyFxn is set to Error.policyDefault, this option applies to the + * maximum number of times the Error.raiseHook function can be recursively + * invoked. This option limits the possibility of an infinite recursion that + * could lead to a stack overflow. + * The default value is 16. + */ +Error.maxDepth = 2; + + + +/* ================ Hwi configuration ================ */ +var halHwi = xdc.useModule('ti.sysbios.hal.Hwi'); +var m3Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi'); +/* + * Checks for Hwi (system) stack overruns while in the Idle loop. + * + * Pick one: + * - true (default) + * Checks the top word for system stack overflows during the idle loop and + * raises an Error if one is detected. + * - false + * Disabling the runtime check improves runtime performance and yields a + * reduced flash footprint. + */ +halHwi.checkStackFlag = true; +//halHwi.checkStackFlag = false; + +/* + * The following options alter the system's behavior when a hardware exception + * is detected. + * + * Pick one: + * - Hwi.enableException = true + * This option causes the default m3Hwi.excHandlerFunc function to fully + * decode an exception and dump the registers to the system console. + * This option raises errors in the Error module and displays the + * exception in ROV. + * - Hwi.enableException = false + * This option reduces code footprint by not decoding or printing the + * exception to the system console. + * It however still raises errors in the Error module and displays the + * exception in ROV. + * - Hwi.excHandlerFunc = null + * This is the most aggressive option for code footprint savings; but it + * can difficult to debug exceptions. It reduces flash footprint by + * plugging in a default while(1) trap when exception occur. This option + * does not raise an error with the Error module. + */ +m3Hwi.enableException = true; +//m3Hwi.enableException = false; +//m3Hwi.excHandlerFunc = null; + +/* + * Enable hardware exception generation when dividing by zero. + * + * Pick one: + * - 0 (default) + * Disables hardware exceptions when dividing by zero + * - 1 + * Enables hardware exceptions when dividing by zero + */ +m3Hwi.nvicCCR.DIV_0_TRP = 0; +//m3Hwi.nvicCCR.DIV_0_TRP = 1; + +/* + * Enable hardware exception generation for invalid data alignment. + * + * Pick one: + * - 0 (default) + * Disables hardware exceptions for data alignment + * - 1 + * Enables hardware exceptions for data alignment + */ +m3Hwi.nvicCCR.UNALIGN_TRP = 0; +//m3Hwi.nvicCCR.UNALIGN_TRP = 1; + + + +/* ================ Idle configuration ================ */ +var Idle = xdc.useModule('ti.sysbios.knl.Idle'); +/* + * The Idle module is used to specify a list of functions to be called when no + * other tasks are running in the system. + * + * Functions added here will be run continuously within the idle task. + * + * Function signature: + * Void func(Void); + */ +//Idle.addFunc("&myIdleFunc"); + + + +/* ================ Kernel (SYS/BIOS) configuration ================ */ +var BIOS = xdc.useModule('ti.sysbios.BIOS'); +/* + * Enable asserts in the BIOS library. + * + * Pick one: + * - true (default) + * Enables asserts for debugging purposes. + * - false + * Disables asserts for a reduced code footprint and better performance. + */ +//BIOS.assertsEnabled = true; +BIOS.assertsEnabled = false; + +/* + * Specify default heap size for BIOS. + */ +BIOS.heapSize = 1024; + +/* + * A flag to determine if xdc.runtime sources are to be included in a custom + * built BIOS library. + * + * Pick one: + * - false (default) + * The pre-built xdc.runtime library is provided by the respective target + * used to build the application. + * - true + * xdc.runtime library sources are to be included in the custom BIOS + * library. This option yields the most efficient library in both code + * footprint and runtime performance. + */ +BIOS.includeXdcRuntime = false; +//BIOS.includeXdcRuntime = true; + +/* + * The SYS/BIOS runtime is provided in the form of a library that is linked + * with the application. Several forms of this library are provided with the + * SYS/BIOS product. + * + * Pick one: + * - BIOS.LibType_Custom + * Custom built library that is highly optimized for code footprint and + * runtime performance. + * - BIOS.LibType_Debug + * Custom built library that is non-optimized that can be used to + * single-step through APIs with a debugger. + * + */ +BIOS.libType = BIOS.LibType_Custom; +//BIOS.libType = BIOS.LibType_Debug; + +/* + * Runtime instance creation enable flag. + * + * Pick one: + * - true (default) + * Allows Mod_create() and Mod_delete() to be called at runtime which + * requires a default heap for dynamic memory allocation. + * - false + * Reduces code footprint by disallowing Mod_create() and Mod_delete() to + * be called at runtime. Object instances are constructed via + * Mod_construct() and destructed via Mod_destruct(). + */ +BIOS.runtimeCreatesEnabled = true; +//BIOS.runtimeCreatesEnabled = false; + +/* + * Enable logs in the BIOS library. + * + * Pick one: + * - true (default) + * Enables logs for debugging purposes. + * - false + * Disables logging for reduced code footprint and improved runtime + * performance. + */ +//BIOS.logsEnabled = true; +BIOS.logsEnabled = false; + + + +/* ================ Memory configuration ================ */ +var Memory = xdc.useModule('xdc.runtime.Memory'); +/* + * The Memory module itself simply provides a common interface for any + * variety of system and application specific memory management policies + * implemented by the IHeap modules(Ex. HeapMem, HeapBuf). + */ + + + +/* ================ Program configuration ================ */ +/* + * Program.stack is ignored with IAR. Use the project options in + * IAR Embedded Workbench to alter the system stack size. + */ +if (!Program.build.target.$name.match(/iar/)) { + /* + * Reducing the system stack size (used by ISRs and Swis) to reduce + * RAM usage. + */ + Program.stack = 768; +} + + + +/* + * Enable Semihosting for GNU targets to print to CCS console + */ +if (Program.build.target.$name.match(/gnu/)) { + var SemiHost = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport'); +} +/* ================ Semaphore configuration ================ */ +var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore'); +/* + * Enables global support for Task priority pend queuing. + * + * Pick one: + * - true (default) + * This allows pending tasks to be serviced based on their task priority. + * - false + * Pending tasks are services based on first in, first out basis. + * + * When using BIOS in ROM: + * This option must be set to false. + */ +//Semaphore.supportsPriority = true; +Semaphore.supportsPriority = false; + +/* + * Allows for the implicit posting of events through the semaphore, + * disable for additional code saving. + * + * Pick one: + * - true + * This allows the Semaphore module to post semaphores and events + * simultaneously. + * - false (default) + * Events must be explicitly posted to unblock tasks. + * + */ +//Semaphore.supportsEvents = true; +Semaphore.supportsEvents = false; + + + +/* ================ Swi configuration ================ */ +var Swi = xdc.useModule('ti.sysbios.knl.Swi'); +/* + * A software interrupt is an object that encapsulates a function to be + * executed and a priority. Software interrupts are prioritized, preempt tasks + * and are preempted by hardware interrupt service routines. + * + * This module is included to allow Swi's in a users' application. + */ + + + +/* ================ System configuration ================ */ +var System = xdc.useModule('xdc.runtime.System'); +/* + * The Abort handler is called when the system exits abnormally. + * + * Pick one: + * - System.abortStd (default) + * Call the ANSI C Standard 'abort()' to terminate the application. + * - System.abortSpin + * A lightweight abort function that loops indefinitely in a while(1) trap + * function. + * - A custom abort handler + * A user-defined function. See the System module documentation for + * details. + */ +System.abortFxn = System.abortStd; +//System.abortFxn = System.abortSpin; +//System.abortFxn = "&myAbortSystem"; + +/* + * The Exit handler is called when the system exits normally. + * + * Pick one: + * - System.exitStd (default) + * Call the ANSI C Standard 'exit()' to terminate the application. + * - System.exitSpin + * A lightweight exit function that loops indefinitely in a while(1) trap + * function. + * - A custom exit function + * A user-defined function. See the System module documentation for + * details. + */ +System.exitFxn = System.exitStd; +//System.exitFxn = System.exitSpin; +//System.exitFxn = "&myExitSystem"; + +/* + * Minimize exit handler array in the System module. The System module includes + * an array of functions that are registered with System_atexit() which is + * called by System_exit(). The default value is 8. + */ +System.maxAtexitHandlers = 2; + +/* + * The System.SupportProxy defines a low-level implementation of System + * functions such as System_printf(), System_flush(), etc. + * + * Pick one pair: + * - SysMin + * This module maintains an internal configurable circular buffer that + * stores the output until System_flush() is called. + * The size of the circular buffer is set via SysMin.bufSize. + * - SysCallback + * SysCallback allows for user-defined implementations for System APIs. + * The SysCallback support proxy has a smaller code footprint and can be + * used to supply custom System_printf services. + * The default SysCallback functions point to stub functions. See the + * SysCallback module's documentation. + */ +var SysMin = xdc.useModule('xdc.runtime.SysMin'); +SysMin.bufSize = 128; +System.SupportProxy = SysMin; +//var SysCallback = xdc.useModule('xdc.runtime.SysCallback'); +//System.SupportProxy = SysCallback; +//SysCallback.abortFxn = "&myUserAbort"; +//SysCallback.exitFxn = "&myUserExit"; +//SysCallback.flushFxn = "&myUserFlush"; +//SysCallback.putchFxn = "&myUserPutch"; +//SysCallback.readyFxn = "&myUserReady"; + + + + +/* ================ Task configuration ================ */ +var Task = xdc.useModule('ti.sysbios.knl.Task'); +/* + * Check task stacks for overflow conditions. + * + * Pick one: + * - true (default) + * Enables runtime checks for task stack overflow conditions during + * context switching ("from" and "to") + * - false + * Disables runtime checks for task stack overflow conditions. + */ +Task.checkStackFlag = true; +//Task.checkStackFlag = false; + +/* + * Set the default task stack size when creating tasks. + * + * The default is dependent on the device being used. Reducing the default stack + * size yields greater memory savings. + */ +Task.defaultStackSize = 512; + +/* + * Enables the idle task. + * + * Pick one: + * - true (default) + * Creates a task with priority of 0 which calls idle hook functions. This + * option must be set to true to gain power savings provided by the Power + * module. + * - false + * No idle task is created. This option consumes less memory as no + * additional default task stack is needed. + * To gain power savings by the Power module without having the idle task, + * add Idle.run as the Task.allBlockedFunc. + */ +Task.enableIdleTask = true; +//Task.enableIdleTask = false; +//Task.allBlockedFunc = Idle.run; + +/* + * If Task.enableIdleTask is set to true, this option sets the idle task's + * stack size. + * + * Reducing the idle stack size yields greater memory savings. + */ +Task.idleTaskStackSize = 512; + +/* + * Reduce the number of task priorities. + * The default is 16. + * Decreasing the number of task priorities yield memory savings. + */ +Task.numPriorities = 16; + + + +/* ================ Text configuration ================ */ +var Text = xdc.useModule('xdc.runtime.Text'); +/* + * These strings are placed in the .const section. Setting this parameter to + * false will save space in the .const section. Error, Assert and Log messages + * will print raw ids and args instead of a formatted message. + * + * Pick one: + * - true (default) + * This option loads test string into the .const for easier debugging. + * - false + * This option reduces the .const footprint. + */ +Text.isLoaded = true; +//Text.isLoaded = false; + + + +/* ================ Types configuration ================ */ +var Types = xdc.useModule('xdc.runtime.Types'); +/* + * This module defines basic constants and types used throughout the + * xdc.runtime package. + */ + + + +/* ================ TI-RTOS middleware configuration ================ */ +var mwConfig = xdc.useModule('ti.mw.Config'); +/* + * Include TI-RTOS middleware libraries + */ + + + +/* ================ TI-RTOS drivers' configuration ================ */ +var driversConfig = xdc.useModule('ti.drivers.Config'); +/* + * Include TI-RTOS drivers + * + * Pick one: + * - driversConfig.LibType_NonInstrumented (default) + * Use TI-RTOS drivers library optimized for footprint and performance + * without asserts or logs. + * - driversConfig.LibType_Instrumented + * Use TI-RTOS drivers library for debugging with asserts and logs enabled. + */ +driversConfig.libType = driversConfig.LibType_NonInstrumented; +//driversConfig.libType = driversConfig.LibType_Instrumented; + + + +/* ================ Application Specific Instances ================ */ + +/* Use UARTMon with TI and GCC toolchains only */ +if (!Program.build.target.$name.match(/iar/)) { + var UARTMon = xdc.useModule('ti.tirtos.utils.UARTMon'); + UARTMon.stackSize = 1024; +} \ No newline at end of file diff --git a/CCS/mm/gpiointerrupt_readme.txt b/CCS/mm/gpiointerrupt_readme.txt new file mode 100644 index 0000000..c989028 --- /dev/null +++ b/CCS/mm/gpiointerrupt_readme.txt @@ -0,0 +1,78 @@ +Example Summary +--------------- +Application that toggles an LED using a GPIO pin interrupt. It also demonstrates +how the UARTMon module can be used with GUI Composer within CCS. + +Peripherals Exercised +--------------------- +Board_LED0 Indicates that the board was initialized within main(), + Also toggled by Board_BUTTON0 +Board_LED1 Toggled by Board_BUTTON1 +Board_BUTTON0 Toggles Board_LED0 +Board_BUTTON1 Toggles Board_LED1 +Board_UART0 Used by UARTMon to communicate with GUI Composer + +Resources & Jumper Settings +--------------------------- +Please refer to the development board's specific "Settings and Resources" +section in the Getting Started Guide. For convenience, a short summary is also +shown below. + +| Development board | Notes | +| ================= | ====================================================== | +| CC3200 | Close Jumpers J2 and J3 | +| | Both Board_BUTTON0 and Board_BUTTON1 toggle Board_LED0 | +| ----------------- | ------------------------------------------------------ | +| DK-TM4C123G | N/A | +| ----------------- | ------------------------------------------------------ | +| DK-TM4C129X | J37: Close SEL, DOWN, UP (enables Switches) | +| | J36: Close GREEN, BLUE, RED (enables LEDs) | +| ----------------- | ------------------------------------------------------ | +| EK-TM4C123GXL | N/A | +| EK-TM4C1294XL | | +| EK-TM4C129EXL | | +| MSP-EXP430F5529LP | | +| ----------------- | ------------------------------------------------------ | +| MSP-EXP430FR5969 | Close J6 | +| | Board_BUTTON0 toggles Board_LED1 and Board_BUTTON1 | +| | toggles Board_LED0 | +| ----------------- | ------------------------------------------------------ | +| MSP-EXP430FR6989 | Close J7 and J8 | +| ----------------- | ------------------------------------------------------ | +| MSP-EXP432P401R | N/A | +| TMDXDOCK28M36 | | +| TMDXDOCKH52C1 | | +| ----------------- | ------------------------------------------------------ | + +Example Usage +------------- +Run the example. Board_LED0 turns ON to indicate TI-RTOS driver initialization +is complete. + +Board_LED0 is toggled by pushing Board_BUTTON0. +Board_LED1 is toggled by pushing Board_BUTTON1. + +Application Design Details +-------------------------- +The gpioButtonFxn0/1 functions are configured in the "Board.c" file. These functions +are called in the context of the GPIO interrupt. + +There is no application source code needed for UARTMon other than the UART +configuration in the "Board.c" and the initialization of the TI-RTOS UART driver +which is accomplished by calling Board_initUART(). + +Notes +------ +Not all boards have more than one button, so Board_LED1 may not be toggled. + +Please refer to the TI-RTOS User's Guide for an explanation on how to configure +and use UARTMon with GUI Composer. + +There is no button de-bounce logic in the example. So the +count may increase faster. + +References +--------------- +For GNU and IAR users, please read the following website for details about +semi-hosting: + http://processors.wiki.ti.com/index.php/TI-RTOS_Examples_SemiHosting diff --git a/CCS/mm/inc/launchpad.h b/CCS/mm/inc/launchpad.h new file mode 100644 index 0000000..0b8ffb2 --- /dev/null +++ b/CCS/mm/inc/launchpad.h @@ -0,0 +1,26 @@ +#include +#include + +// PF0 - Left button +// PF1 - Red LED +// PF2 - Blue LED +// PF3 - Green LED +// PF4 - Right button +// PA0 - USB UART RX +// PA1 - USB UART TX + +// Initializes the LED and button pins on the launchpad, as well as +// UART <-> USB through the debugger. +void launchpad_init(void); + +#define RED_LED 2 +#define BLUE_LED 4 +#define GREEN_LED 8 + +bool left_switch(void); + +bool right_switch(void); + +void led_toggle(uint8_t led); + +void led_write(uint8_t led, bool value); diff --git a/CCS/mm/inc/motors.h b/CCS/mm/inc/motors.h new file mode 100644 index 0000000..aedee56 --- /dev/null +++ b/CCS/mm/inc/motors.h @@ -0,0 +1,16 @@ +#include + +const int VELOCITY_PERIOD = 4000; // TODO: investigate accuracy/latency tradeoff + +void init_motors(void); + +void reset_enc(void); + +int32_t left_pos(void); +int32_t right_pos(void); + +uint32_t left_speed(void); +uint32_t right_speed(void); + +void set_left(float speed); +void set_right(float speed); diff --git a/CCS/mm/inc/tivaware/adc.h b/CCS/mm/inc/tivaware/adc.h new file mode 100644 index 0000000..5fda3df --- /dev/null +++ b/CCS/mm/inc/tivaware/adc.h @@ -0,0 +1,329 @@ +#include +#include +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ADC_H__ +#define __DRIVERLIB_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ui32Trigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event +#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event +#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0 +#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1 + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ui32Config +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 +#define ADC_CTL_CH8 0x00000008 // Input channel 8 +#define ADC_CTL_CH9 0x00000009 // Input channel 9 +#define ADC_CTL_CH10 0x0000000A // Input channel 10 +#define ADC_CTL_CH11 0x0000000B // Input channel 11 +#define ADC_CTL_CH12 0x0000000C // Input channel 12 +#define ADC_CTL_CH13 0x0000000D // Input channel 13 +#define ADC_CTL_CH14 0x0000000E // Input channel 14 +#define ADC_CTL_CH15 0x0000000F // Input channel 15 +#define ADC_CTL_CH16 0x00000100 // Input channel 16 +#define ADC_CTL_CH17 0x00000101 // Input channel 17 +#define ADC_CTL_CH18 0x00000102 // Input channel 18 +#define ADC_CTL_CH19 0x00000103 // Input channel 19 +#define ADC_CTL_CH20 0x00000104 // Input channel 20 +#define ADC_CTL_CH21 0x00000105 // Input channel 21 +#define ADC_CTL_CH22 0x00000106 // Input channel 22 +#define ADC_CTL_CH23 0x00000107 // Input channel 23 +#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 +#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 +#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 +#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 +#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 +#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 +#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 +#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 +#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks +#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks +#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks +#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks +#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks +#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks +#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks + +//***************************************************************************** +// +// Values that can be passed to ADCComparatorConfigure as part of the +// ui32Config parameter. +// +//***************************************************************************** +#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled +#define ADC_COMP_TRIG_LOW_ALWAYS \ + 0x00001000 // Trigger Low Always +#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once +#define ADC_COMP_TRIG_LOW_HALWAYS \ + 0x00001200 // Trigger Low Always (Hysteresis) +#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) +#define ADC_COMP_TRIG_MID_ALWAYS \ + 0x00001400 // Trigger Mid Always +#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once +#define ADC_COMP_TRIG_HIGH_ALWAYS \ + 0x00001C00 // Trigger High Always +#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once +#define ADC_COMP_TRIG_HIGH_HALWAYS \ + 0x00001E00 // Trigger High Always (Hysteresis) +#define ADC_COMP_TRIG_HIGH_HONCE \ + 0x00001F00 // Trigger High Once (Hysteresis) + +#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled +#define ADC_COMP_INT_LOW_ALWAYS \ + 0x00000010 // Interrupt Low Always +#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once +#define ADC_COMP_INT_LOW_HALWAYS \ + 0x00000012 // Interrupt Low Always + // (Hysteresis) +#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) +#define ADC_COMP_INT_MID_ALWAYS \ + 0x00000014 // Interrupt Mid Always +#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once +#define ADC_COMP_INT_HIGH_ALWAYS \ + 0x0000001C // Interrupt High Always +#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once +#define ADC_COMP_INT_HIGH_HALWAYS \ + 0x0000001E // Interrupt High Always + // (Hysteresis) +#define ADC_COMP_INT_HIGH_HONCE \ + 0x0000001F // Interrupt High Once (Hysteresis) + +//***************************************************************************** +// +// Values that can be used to modify the sequence number passed to +// ADCProcessorTrigger in order to get cross-module synchronous processor +// triggers. +// +//***************************************************************************** +#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger +#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger + +//***************************************************************************** +// +// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and +// returned from ADCPhaseDelayGet. +// +//***************************************************************************** +#define ADC_PHASE_0 0x00000000 // 0 degrees +#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees +#define ADC_PHASE_45 0x00000002 // 45 degrees +#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees +#define ADC_PHASE_90 0x00000004 // 90 degrees +#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees +#define ADC_PHASE_135 0x00000006 // 135 degrees +#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees +#define ADC_PHASE_180 0x00000008 // 180 degrees +#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees +#define ADC_PHASE_225 0x0000000A // 225 degrees +#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees +#define ADC_PHASE_270 0x0000000C // 270 degrees +#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees +#define ADC_PHASE_315 0x0000000E // 315 degrees +#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees + +//***************************************************************************** +// +// Values that can be passed to ADCReferenceSet as the ui32Ref parameter. +// +//***************************************************************************** +#define ADC_REF_INT 0x00000000 // Internal reference +#define ADC_REF_EXT_3V 0x00000001 // External 3V reference + +//***************************************************************************** +// +// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), +// ADCIntClearEx() and ADCIntStatusEx(). +// +//***************************************************************************** +#define ADC_INT_SS0 0x00000001 +#define ADC_INT_SS1 0x00000002 +#define ADC_INT_SS2 0x00000004 +#define ADC_INT_SS3 0x00000008 +#define ADC_INT_DMA_SS0 0x00000100 +#define ADC_INT_DMA_SS1 0x00000200 +#define ADC_INT_DMA_SS2 0x00000400 +#define ADC_INT_DMA_SS3 0x00000800 +#define ADC_INT_DCON_SS0 0x00010000 +#define ADC_INT_DCON_SS1 0x00020000 +#define ADC_INT_DCON_SS2 0x00040000 +#define ADC_INT_DCON_SS3 0x00080000 + +//***************************************************************************** +// +// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet(). +// +//***************************************************************************** +#define ADC_CLOCK_RATE_FULL 0x00000070 +#define ADC_CLOCK_RATE_HALF 0x00000050 +#define ADC_CLOCK_RATE_FOURTH 0x00000030 +#define ADC_CLOCK_RATE_EIGHTH 0x00000010 +#define ADC_CLOCK_SRC_PLL 0x00000000 +#define ADC_CLOCK_SRC_PIOSC 0x00000001 +#define ADC_CLOCK_SRC_ALTCLK 0x00000001 +#define ADC_CLOCK_SRC_MOSC 0x00000002 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, + bool bMasked); +extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Trigger, uint32_t ui32Priority); +extern void ADCSequenceStepConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Step, uint32_t ui32Config); +extern int32_t ADCSequenceOverflow(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCSequenceOverflowClear(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern int32_t ADCSequenceUnderflow(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCSequenceUnderflowClear(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t *pui32Buffer); +extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Factor); +extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Step, + uint32_t ui32Config); +extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t *pui32Buffer, + uint32_t ui32Count); +extern void ADCHardwareOversampleConfigure(uint32_t ui32Base, + uint32_t ui32Factor); +extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32ClockDiv); +extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv); + +extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32Config); +extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32LowRef, uint32_t ui32HighRef); +extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, + bool bTrigger, bool bInterrupt); +extern void ADCComparatorIntDisable(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCComparatorIntEnable(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base); +extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status); +extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked); +extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern bool ADCBusy(uint32_t ui32Base); +extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref); +extern uint32_t ADCReferenceGet(uint32_t ui32Base); +extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase); +extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base); +extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock, + uint32_t ui32Rate); +extern uint32_t ADCSampleRateGet(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_ADC_H__ diff --git a/CCS/mm/inc/tivaware/gpio.h b/CCS/mm/inc/tivaware/gpio.h new file mode 100644 index 0000000..1de14e8 --- /dev/null +++ b/CCS/mm/inc/tivaware/gpio.h @@ -0,0 +1,206 @@ +#include +#include +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_GPIO_H__ +#define __DRIVERLIB_GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ui8Pins argument to +// several of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, +// and returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, +// and returned by GPIOPadConfigGet in the *pui32Strength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength +#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control +#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength +#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, +// and returned by GPIOPadConfigGet in the *pui32PadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator +#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high +#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low + +//***************************************************************************** +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ui32IntFlags parameter. +// +//***************************************************************************** +#define GPIO_INT_PIN_0 0x00000001 +#define GPIO_INT_PIN_1 0x00000002 +#define GPIO_INT_PIN_2 0x00000004 +#define GPIO_INT_PIN_3 0x00000008 +#define GPIO_INT_PIN_4 0x00000010 +#define GPIO_INT_PIN_5 0x00000020 +#define GPIO_INT_PIN_6 0x00000040 +#define GPIO_INT_PIN_7 0x00000080 +#define GPIO_INT_DMA 0x00000100 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32PinIO); +extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32IntType); +extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32Strength, uint32_t ui32PadType); +extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, + uint32_t *pui32Strength, uint32_t *pui32PadType); +extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); +extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); +extern void GPIOIntUnregister(uint32_t ui32Port); +extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, + void (*pfnIntHandler)(void)); +extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin); +extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); +extern void GPIOPinConfigure(uint32_t ui32PinConfig); +extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); +extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); +extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_GPIO_H__ diff --git a/CCS/mm/inc/tivaware/hw_ints.h b/CCS/mm/inc/tivaware/hw_ints.h new file mode 100644 index 0000000..54c655d --- /dev/null +++ b/CCS/mm/inc/tivaware/hw_ints.h @@ -0,0 +1,493 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series +// MCUs. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +#define TARGET_IS_TM4C123_RB1 + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// TM4C123 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C123 16 // GPIO Port A +#define INT_GPIOB_TM4C123 17 // GPIO Port B +#define INT_GPIOC_TM4C123 18 // GPIO Port C +#define INT_GPIOD_TM4C123 19 // GPIO Port D +#define INT_GPIOE_TM4C123 20 // GPIO Port E +#define INT_UART0_TM4C123 21 // UART0 +#define INT_UART1_TM4C123 22 // UART1 +#define INT_SSI0_TM4C123 23 // SSI0 +#define INT_I2C0_TM4C123 24 // I2C0 +#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault +#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 +#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 +#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 +#define INT_QEI0_TM4C123 29 // QEI0 +#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C123 41 // Analog Comparator 0 +#define INT_COMP1_TM4C123 42 // Analog Comparator 1 +#define INT_COMP2_TM4C123 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C123 44 // System Control +#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF_TM4C123 46 // GPIO Port F +#define INT_GPIOG_TM4C123 47 // GPIO Port G +#define INT_GPIOH_TM4C123 48 // GPIO Port H +#define INT_UART2_TM4C123 49 // UART2 +#define INT_SSI1_TM4C123 50 // SSI1 +#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C123 52 // Timer 3B +#define INT_I2C1_TM4C123 53 // I2C1 +#define INT_QEI1_TM4C123 54 // QEI1 +#define INT_CAN0_TM4C123 55 // CAN0 +#define INT_CAN1_TM4C123 56 // CAN1 +#define INT_HIBERNATE_TM4C123 59 // Hibernation Module +#define INT_USB0_TM4C123 60 // USB +#define INT_PWM0_3_TM4C123 61 // PWM Generator 3 +#define INT_UDMA_TM4C123 62 // uDMA Software +#define INT_UDMAERR_TM4C123 63 // uDMA Error +#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 +#define INT_GPIOJ_TM4C123 70 // GPIO Port J +#define INT_GPIOK_TM4C123 71 // GPIO Port K +#define INT_GPIOL_TM4C123 72 // GPIO Port L +#define INT_SSI2_TM4C123 73 // SSI2 +#define INT_SSI3_TM4C123 74 // SSI3 +#define INT_UART3_TM4C123 75 // UART3 +#define INT_UART4_TM4C123 76 // UART4 +#define INT_UART5_TM4C123 77 // UART5 +#define INT_UART6_TM4C123 78 // UART6 +#define INT_UART7_TM4C123 79 // UART7 +#define INT_I2C2_TM4C123 84 // I2C2 +#define INT_I2C3_TM4C123 85 // I2C3 +#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) +#define INT_I2C4_TM4C123 125 // I2C4 +#define INT_I2C5_TM4C123 126 // I2C5 +#define INT_GPIOM_TM4C123 127 // GPIO Port M +#define INT_GPION_TM4C123 128 // GPIO Port N +#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C123 133 // GPIO Port P1 +#define INT_GPIOP2_TM4C123 134 // GPIO Port P2 +#define INT_GPIOP3_TM4C123 135 // GPIO Port P3 +#define INT_GPIOP4_TM4C123 136 // GPIO Port P4 +#define INT_GPIOP5_TM4C123 137 // GPIO Port P5 +#define INT_GPIOP6_TM4C123 138 // GPIO Port P6 +#define INT_GPIOP7_TM4C123 139 // GPIO Port P7 +#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 +#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 +#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 +#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 +#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault +#define NUM_INTERRUPTS_TM4C123 155 + +//***************************************************************************** +// +// TM4C129 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C129 16 // GPIO Port A +#define INT_GPIOB_TM4C129 17 // GPIO Port B +#define INT_GPIOC_TM4C129 18 // GPIO Port C +#define INT_GPIOD_TM4C129 19 // GPIO Port D +#define INT_GPIOE_TM4C129 20 // GPIO Port E +#define INT_UART0_TM4C129 21 // UART0 +#define INT_UART1_TM4C129 22 // UART1 +#define INT_SSI0_TM4C129 23 // SSI0 +#define INT_I2C0_TM4C129 24 // I2C0 +#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault +#define INT_PWM0_0_TM4C129 26 // PWM Generator 0 +#define INT_PWM0_1_TM4C129 27 // PWM Generator 1 +#define INT_PWM0_2_TM4C129 28 // PWM Generator 2 +#define INT_QEI0_TM4C129 29 // QEI0 +#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C129 41 // Analog Comparator 0 +#define INT_COMP1_TM4C129 42 // Analog Comparator 1 +#define INT_COMP2_TM4C129 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C129 44 // System Control +#define INT_FLASH_TM4C129 45 // Flash Memory Control +#define INT_GPIOF_TM4C129 46 // GPIO Port F +#define INT_GPIOG_TM4C129 47 // GPIO Port G +#define INT_GPIOH_TM4C129 48 // GPIO Port H +#define INT_UART2_TM4C129 49 // UART2 +#define INT_SSI1_TM4C129 50 // SSI1 +#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B +#define INT_I2C1_TM4C129 53 // I2C1 +#define INT_CAN0_TM4C129 54 // CAN 0 +#define INT_CAN1_TM4C129 55 // CAN1 +#define INT_EMAC0_TM4C129 56 // Ethernet MAC +#define INT_HIBERNATE_TM4C129 57 // HIB +#define INT_USB0_TM4C129 58 // USB MAC +#define INT_PWM0_3_TM4C129 59 // PWM Generator 3 +#define INT_UDMA_TM4C129 60 // uDMA 0 Software +#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error +#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 +#define INT_EPI0_TM4C129 66 // EPI 0 +#define INT_GPIOJ_TM4C129 67 // GPIO Port J +#define INT_GPIOK_TM4C129 68 // GPIO Port K +#define INT_GPIOL_TM4C129 69 // GPIO Port L +#define INT_SSI2_TM4C129 70 // SSI 2 +#define INT_SSI3_TM4C129 71 // SSI 3 +#define INT_UART3_TM4C129 72 // UART 3 +#define INT_UART4_TM4C129 73 // UART 4 +#define INT_UART5_TM4C129 74 // UART 5 +#define INT_UART6_TM4C129 75 // UART 6 +#define INT_UART7_TM4C129 76 // UART 7 +#define INT_I2C2_TM4C129 77 // I2C 2 +#define INT_I2C3_TM4C129 78 // I2C 3 +#define INT_TIMER4A_TM4C129 79 // Timer 4A +#define INT_TIMER4B_TM4C129 80 // Timer 4B +#define INT_TIMER5A_TM4C129 81 // Timer 5A +#define INT_TIMER5B_TM4C129 82 // Timer 5B +#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception + // (imprecise) +#define INT_I2C4_TM4C129 86 // I2C 4 +#define INT_I2C5_TM4C129 87 // I2C 5 +#define INT_GPIOM_TM4C129 88 // GPIO Port M +#define INT_GPION_TM4C129 89 // GPIO Port N +#define INT_TAMPER0_TM4C129 91 // Tamper +#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C129 93 // GPIO Port P1 +#define INT_GPIOP2_TM4C129 94 // GPIO Port P2 +#define INT_GPIOP3_TM4C129 95 // GPIO Port P3 +#define INT_GPIOP4_TM4C129 96 // GPIO Port P4 +#define INT_GPIOP5_TM4C129 97 // GPIO Port P5 +#define INT_GPIOP6_TM4C129 98 // GPIO Port P6 +#define INT_GPIOP7_TM4C129 99 // GPIO Port P7 +#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 +#define INT_GPIOR_TM4C129 108 // GPIO Port R +#define INT_GPIOS_TM4C129 109 // GPIO Port S +#define INT_SHA0_TM4C129 110 // SHA/MD5 +#define INT_AES0_TM4C129 111 // AES +#define INT_DES0_TM4C129 112 // DES +#define INT_LCD0_TM4C129 113 // LCD +#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A +#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B +#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A +#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B +#define INT_I2C6_TM4C129 118 // I2C 6 +#define INT_I2C7_TM4C129 119 // I2C 7 +#define INT_ONEWIRE0_TM4C129 121 // 1-Wire +#define INT_I2C8_TM4C129 125 // I2C 8 +#define INT_I2C9_TM4C129 126 // I2C 9 +#define INT_GPIOT_TM4C129 127 // GPIO T +#define NUM_INTERRUPTS_TM4C129 129 + +//***************************************************************************** +// +// TM4C123 Interrupt Class Definition +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ + defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ + defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ + defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ + defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ + defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ + defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ + defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ + defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ + defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ + defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ + defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ + defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ + defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ + defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ + defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ + defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ + defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ + defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ + defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ + defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ + defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ + defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ + defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ + defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ + defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) +#define INT_RESOLVE(intname, class) intname##TM4C123 + +//***************************************************************************** +// +// TM4C129 Interrupt Class Definition +// +//***************************************************************************** +#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ + defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ + defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ + defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ + defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ + defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ + defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ + defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ + defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ + defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ + defined(PART_TM4C129XNCZAD) +#define INT_RESOLVE(intname, class) intname##TM4C129 +#else +#define INT_DEVICE_CLASS "UNKNOWN" +#endif + +//***************************************************************************** +// +// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. +// +//***************************************************************************** +#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) +#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) +#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) +#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) +#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) +#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) +#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) +#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) +#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) +#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) +#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) +#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) +#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) +#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) +#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) +#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) +#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) +#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) +#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) +#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) +#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) +#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) +#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) +#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) +#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) +#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) +#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) +#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) +#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) +#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) +#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) +#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) +#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) +#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) +#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) +#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) +#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) +#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) +#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) +#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) +#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) +#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) +#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) +#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) +#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) +#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) +#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) +#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) +#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) +#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) +#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) +#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) +#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) +#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) +#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) +#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) +#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) +#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) +#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) +#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) +#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) +#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) +#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) +#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) +#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) +#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) +#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) +#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) +#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) +#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) +#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) +#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) +#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) +#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) +#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) +#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) +#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) +#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) +#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) +#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) +#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) +#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) +#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) +#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) +#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) +#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) +#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) +#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) +#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) +#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) +#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) +#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) +#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) +#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) +#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) +#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) +#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) +#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) +#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) +#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) +#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) +#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) +#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) +#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) +#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) +#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) +#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) +#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) +#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) +#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) +#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) +#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) +#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) +#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) +#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) +#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) +#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) +#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) +#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) +#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) +#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) +#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) +#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/CCS/mm/inc/tivaware/hw_memmap.h b/CCS/mm/inc/tivaware/hw_memmap.h new file mode 100644 index 0000000..780789d --- /dev/null +++ b/CCS/mm/inc/tivaware/hw_memmap.h @@ -0,0 +1,153 @@ +#include +#include +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of the device. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG0_BASE 0x40000000 // Watchdog0 +#define WATCHDOG1_BASE 0x40001000 // Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define SSI2_BASE 0x4000A000 // SSI2 +#define SSI3_BASE 0x4000B000 // SSI3 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define UART3_BASE 0x4000F000 // UART3 +#define UART4_BASE 0x40010000 // UART4 +#define UART5_BASE 0x40011000 // UART5 +#define UART6_BASE 0x40012000 // UART6 +#define UART7_BASE 0x40013000 // UART7 +#define I2C0_BASE 0x40020000 // I2C0 +#define I2C1_BASE 0x40021000 // I2C1 +#define I2C2_BASE 0x40022000 // I2C2 +#define I2C3_BASE 0x40023000 // I2C3 +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) +#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define TIMER4_BASE 0x40034000 // Timer4 +#define TIMER5_BASE 0x40035000 // Timer5 +#define WTIMER0_BASE 0x40036000 // Wide Timer0 +#define WTIMER1_BASE 0x40037000 // Wide Timer1 +#define ADC0_BASE 0x40038000 // ADC0 +#define ADC1_BASE 0x40039000 // ADC1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define WTIMER2_BASE 0x4004C000 // Wide Timer2 +#define WTIMER3_BASE 0x4004D000 // Wide Timer3 +#define WTIMER4_BASE 0x4004E000 // Wide Timer4 +#define WTIMER5_BASE 0x4004F000 // Wide Timer5 +#define USB0_BASE 0x40050000 // USB 0 Controller +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K +#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L +#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M +#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N +#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P +#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q +#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs + // (GPIOs) +#define EEPROM_BASE 0x400AF000 // EEPROM memory +#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module +#define I2C8_BASE 0x400B8000 // I2C8 +#define I2C9_BASE 0x400B9000 // I2C9 +#define I2C4_BASE 0x400C0000 // I2C4 +#define I2C5_BASE 0x400C1000 // I2C5 +#define I2C6_BASE 0x400C2000 // I2C6 +#define I2C7_BASE 0x400C3000 // I2C7 +#define EPI0_BASE 0x400D0000 // EPI0 +#define TIMER6_BASE 0x400E0000 // General-Purpose Timers +#define TIMER7_BASE 0x400E1000 // General-Purpose Timers +#define EMAC0_BASE 0x400EC000 // Ethernet Controller +#define SYSEXC_BASE 0x400F9000 // System Exception Module +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC) +#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator +#define AES_BASE 0x44036000 // Advance Encryption + // Hardware-Accelerated Module +#define DES_BASE 0x44038000 // Data Encryption Standard + // Accelerator (DES) +#define LCD0_BASE 0x44050000 // LCD Controller +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/CCS/mm/inc/tivaware/i2c.h b/CCS/mm/inc/tivaware/i2c.h new file mode 100644 index 0000000..068c00c --- /dev/null +++ b/CCS/mm/inc/tivaware/i2c.h @@ -0,0 +1,364 @@ +#include +#include +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_I2C_H__ +#define __DRIVERLIB_I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000013 +#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ + 0x00000042 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ + 0x00000040 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ + 0x0000004a +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ + 0x00000048 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master glitch filter configuration. +// +//***************************************************************************** +#define I2C_MASTER_GLITCH_FILTER_DISABLED \ + 0 +#define I2C_MASTER_GLITCH_FILTER_1 \ + 0x00010000 +#define I2C_MASTER_GLITCH_FILTER_2 \ + 0x00020000 +#define I2C_MASTER_GLITCH_FILTER_3 \ + 0x00030000 +#define I2C_MASTER_GLITCH_FILTER_4 \ + 0x00040000 +#define I2C_MASTER_GLITCH_FILTER_8 \ + 0x00050000 +#define I2C_MASTER_GLITCH_FILTER_16 \ + 0x00060000 +#define I2C_MASTER_GLITCH_FILTER_32 \ + 0x00070000 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_RX_FIFO_FULL \ + 0x00000800 // RX FIFO Full Interrupt +#define I2C_MASTER_INT_TX_FIFO_EMPTY \ + 0x00000400 // TX FIFO Empty Interrupt +#define I2C_MASTER_INT_RX_FIFO_REQ \ + 0x00000200 // RX FIFO Request Interrupt +#define I2C_MASTER_INT_TX_FIFO_REQ \ + 0x00000100 // TX FIFO Request Interrupt +#define I2C_MASTER_INT_ARB_LOST \ + 0x00000080 // Arb Lost Interrupt +#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt +#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt +#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt +#define I2C_MASTER_INT_TX_DMA_DONE \ + 0x00000008 // TX DMA Complete Interrupt +#define I2C_MASTER_INT_RX_DMA_DONE \ + 0x00000004 // RX DMA Complete Interrupt +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_RX_FIFO_FULL \ + 0x00000100 // RX FIFO Full Interrupt +#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ + 0x00000080 // TX FIFO Empty Interrupt +#define I2C_SLAVE_INT_RX_FIFO_REQ \ + 0x00000040 // RX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_FIFO_REQ \ + 0x00000020 // TX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_DMA_DONE \ + 0x00000010 // TX DMA Complete Interrupt +#define I2C_SLAVE_INT_RX_DMA_DONE \ + 0x00000008 // RX DMA Complete Interrupt +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave FIFO configuration macros. +// +//***************************************************************************** +#define I2C_SLAVE_TX_FIFO_ENABLE \ + 0x00000002 +#define I2C_SLAVE_RX_FIFO_ENABLE \ + 0x00000004 + +//***************************************************************************** +// +// I2C FIFO configuration macros. +// +//***************************************************************************** +#define I2C_FIFO_CFG_TX_MASTER 0x00000000 +#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 +#define I2C_FIFO_CFG_RX_MASTER 0x00000000 +#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 +#define I2C_FIFO_CFG_TX_MASTER_DMA \ + 0x00002000 +#define I2C_FIFO_CFG_TX_SLAVE_DMA \ + 0x0000a000 +#define I2C_FIFO_CFG_RX_MASTER_DMA \ + 0x20000000 +#define I2C_FIFO_CFG_RX_SLAVE_DMA \ + 0xa0000000 +#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 +#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 +#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 +#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 +#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 +#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 +#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 +#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 +#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 +#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 +#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 +#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 +#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 +#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 +#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 +#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 + +//***************************************************************************** +// +// I2C FIFO status. +// +//***************************************************************************** +#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ + 0x00040000 +#define I2C_FIFO_RX_FULL 0x00020000 +#define I2C_FIFO_RX_EMPTY 0x00010000 +#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ + 0x00000004 +#define I2C_FIFO_TX_FULL 0x00000002 +#define I2C_FIFO_TX_EMPTY 0x00000001 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void I2CIntUnregister(uint32_t ui32Base); +extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CTxFIFOFlush(uint32_t ui32Base); +extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CRxFIFOFlush(uint32_t ui32Base); +extern uint32_t I2CFIFOStatus(uint32_t ui32Base); +extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); +extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, + uint8_t ui8Data); +extern uint32_t I2CFIFODataGet(uint32_t ui32Base); +extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, + uint8_t *pui8Data); +extern void I2CMasterBurstLengthSet(uint32_t ui32Base, + uint8_t ui8Length); +extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); +extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, + uint32_t ui32Config); +extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CSlaveFIFODisable(uint32_t ui32Base); +extern bool I2CMasterBusBusy(uint32_t ui32Base); +extern bool I2CMasterBusy(uint32_t ui32Base); +extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); +extern uint32_t I2CMasterDataGet(uint32_t ui32Base); +extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CMasterDisable(uint32_t ui32Base); +extern void I2CMasterEnable(uint32_t ui32Base); +extern uint32_t I2CMasterErr(uint32_t ui32Base); +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); +extern void I2CMasterIntClear(uint32_t ui32Base); +extern void I2CMasterIntDisable(uint32_t ui32Base); +extern void I2CMasterIntEnable(uint32_t ui32Base); +extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); +extern void I2CMasterIntEnableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern void I2CMasterIntClearEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); +extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); +extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); +extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); +extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, + uint8_t ui8SlaveAddr, + bool bReceive); +extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); +extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CSlaveDisable(uint32_t ui32Base); +extern void I2CSlaveEnable(uint32_t ui32Base); +extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); +extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, + uint8_t ui8SlaveAddr); +extern void I2CSlaveIntClear(uint32_t ui32Base); +extern void I2CSlaveIntDisable(uint32_t ui32Base); +extern void I2CSlaveIntEnable(uint32_t ui32Base); +extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void I2CSlaveIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); +extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern uint32_t I2CSlaveStatus(uint32_t ui32Base); +extern void I2CLoopbackEnable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_I2C_H__ diff --git a/CCS/mm/inc/tivaware/pin_map.h b/CCS/mm/inc/tivaware/pin_map.h new file mode 100644 index 0000000..dd0b7b1 --- /dev/null +++ b/CCS/mm/inc/tivaware/pin_map.h @@ -0,0 +1,20956 @@ +#include +#include +#define PART_TM4C123GH6PM +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_PIN_MAP_H__ +#define __DRIVERLIB_PIN_MAP_H__ + +//***************************************************************************** +// +// TM4C1230C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230C3PM + +//***************************************************************************** +// +// TM4C1230D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230D5PM + +//***************************************************************************** +// +// TM4C1230E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230E6PM + +//***************************************************************************** +// +// TM4C1230H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230H6PM + +//***************************************************************************** +// +// TM4C1231C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231C3PM + +//***************************************************************************** +// +// TM4C1231D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231D5PM + +//***************************************************************************** +// +// TM4C1231D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231D5PZ + +//***************************************************************************** +// +// TM4C1231E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231E6PM + +//***************************************************************************** +// +// TM4C1231E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231E6PZ + +//***************************************************************************** +// +// TM4C1231H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231H6PM + +//***************************************************************************** +// +// TM4C1231H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231H6PZ + +//***************************************************************************** +// +// TM4C1232C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232C3PM + +//***************************************************************************** +// +// TM4C1232D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232D5PM + +//***************************************************************************** +// +// TM4C1232E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232E6PM + +//***************************************************************************** +// +// TM4C1232H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232H6PM + +//***************************************************************************** +// +// TM4C1233C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233C3PM + +//***************************************************************************** +// +// TM4C1233D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233D5PM + +//***************************************************************************** +// +// TM4C1233D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233D5PZ + +//***************************************************************************** +// +// TM4C1233E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233E6PM + +//***************************************************************************** +// +// TM4C1233E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233E6PZ + +//***************************************************************************** +// +// TM4C1233H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233H6PM + +//***************************************************************************** +// +// TM4C1233H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233H6PZ + +//***************************************************************************** +// +// TM4C1236D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236D5PM + +//***************************************************************************** +// +// TM4C1236E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236E6PM + +//***************************************************************************** +// +// TM4C1236H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236H6PM + +//***************************************************************************** +// +// TM4C1237D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237D5PM + +//***************************************************************************** +// +// TM4C1237D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237D5PZ + +//***************************************************************************** +// +// TM4C1237E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237E6PM + +//***************************************************************************** +// +// TM4C1237E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237E6PZ + +//***************************************************************************** +// +// TM4C1237H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237H6PM + +//***************************************************************************** +// +// TM4C1237H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237H6PZ + +//***************************************************************************** +// +// TM4C123AE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123AE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C123AE6PM + +//***************************************************************************** +// +// TM4C123AH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123AH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C123AH6PM + +//***************************************************************************** +// +// TM4C123BE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C123BE6PM + +//***************************************************************************** +// +// TM4C123BE6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BE6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123BE6PZ + +//***************************************************************************** +// +// TM4C123BH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C123BH6PM + +//***************************************************************************** +// +// TM4C123BH6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123BH6PZ + +//***************************************************************************** +// +// TM4C123FE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123FE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C123FE6PM + +//***************************************************************************** +// +// TM4C123FH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123FH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C123FH6PM + +//***************************************************************************** +// +// TM4C123GE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C123GE6PM + +//***************************************************************************** +// +// TM4C123GE6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GE6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123GE6PZ + +//***************************************************************************** +// +// TM4C123GH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C123GH6PM + +//***************************************************************************** +// +// TM4C123GH6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123GH6PZ + +//***************************************************************************** +// +// TM4C1231H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1231H6PGE + +//***************************************************************************** +// +// TM4C1233H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1233H6PGE + +//***************************************************************************** +// +// TM4C1237H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1237H6PGE + +//***************************************************************************** +// +// TM4C123BH6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PGE + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C123BH6PGE + +//***************************************************************************** +// +// TM4C123BH6ZRB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6ZRB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123BH6ZRB + +//***************************************************************************** +// +// TM4C123GH6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PGE + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C123GH6PGE + +//***************************************************************************** +// +// TM4C123GH6ZRB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZRB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZRB + +//***************************************************************************** +// +// TM4C123GH6ZXR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZXR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZXR + +//***************************************************************************** +// +// TM4C1290NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1290NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#endif // PART_TM4C1290NCPDT + +//***************************************************************************** +// +// TM4C1290NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1290NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1290NCZAD + +//***************************************************************************** +// +// TM4C1292NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1292NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#endif // PART_TM4C1292NCPDT + +//***************************************************************************** +// +// TM4C1292NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1292NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1292NCZAD + +//***************************************************************************** +// +// TM4C1294KCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294KCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C1294KCPDT + +//***************************************************************************** +// +// TM4C1294NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C1294NCPDT + +//***************************************************************************** +// +// TM4C1294NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1294NCZAD + +//***************************************************************************** +// +// TM4C1297NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1297NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1297NCZAD + +//***************************************************************************** +// +// TM4C1299KCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1299KCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1299KCZAD + +//***************************************************************************** +// +// TM4C1299NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1299NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1299NCZAD + +//***************************************************************************** +// +// TM4C129CNCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129CNCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#endif // PART_TM4C129CNCPDT + +//***************************************************************************** +// +// TM4C129CNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129CNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129CNCZAD + +//***************************************************************************** +// +// TM4C129DNCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129DNCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#endif // PART_TM4C129DNCPDT + +//***************************************************************************** +// +// TM4C129DNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129DNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129DNCZAD + +//***************************************************************************** +// +// TM4C129EKCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129EKCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C129EKCPDT + +//***************************************************************************** +// +// TM4C129ENCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129ENCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C129ENCPDT + +//***************************************************************************** +// +// TM4C129ENCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129ENCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129ENCZAD + +//***************************************************************************** +// +// TM4C129LNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129LNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129LNCZAD + +//***************************************************************************** +// +// TM4C129XKCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129XKCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 +#define GPIO_PE3_OWIRE 0x00040C05 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_OWIRE 0x00061005 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_OWALT 0x00061405 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_OWIRE 0x00061805 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_OWIRE 0x00061C05 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_OWIRE 0x000D1004 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_OWALT 0x000D1404 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PP7_OWIRE 0x000D1C05 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129XKCZAD + +//***************************************************************************** +// +// TM4C129XNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129XNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 +#define GPIO_PE3_OWIRE 0x00040C05 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_OWIRE 0x00061005 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_OWALT 0x00061405 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_OWIRE 0x00061805 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_OWIRE 0x00061C05 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_OWIRE 0x000D1004 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_OWALT 0x000D1404 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PP7_OWIRE 0x000D1C05 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129XNCZAD + +#endif // __DRIVERLIB_PIN_MAP_H__ diff --git a/CCS/mm/inc/tivaware/pwm.h b/CCS/mm/inc/tivaware/pwm.h new file mode 100644 index 0000000..d473161 --- /dev/null +++ b/CCS/mm/inc/tivaware/pwm.h @@ -0,0 +1,328 @@ +#include +#include +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_PWM_H__ +#define __DRIVERLIB_PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ui32Config +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_1 1 + +#define PWM_FAULT_DCMP0 0x00000001 +#define PWM_FAULT_DCMP1 0x00000002 +#define PWM_FAULT_DCMP2 0x00000004 +#define PWM_FAULT_DCMP3 0x00000008 +#define PWM_FAULT_DCMP4 0x00000010 +#define PWM_FAULT_DCMP5 0x00000020 +#define PWM_FAULT_DCMP6 0x00000040 +#define PWM_FAULT_DCMP7 0x00000080 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// Defines that can be passed to the PWMClockSet() API as the ui32Config +// parameter, and can be returned by the PWMClockGet() API. +// +//***************************************************************************** +#define PWM_SYSCLK_DIV_1 0x00000000 // PWM clock is system clock +#define PWM_SYSCLK_DIV_2 0x00000100 // PWM clock is system clock /2 +#define PWM_SYSCLK_DIV_4 0x00000101 // PWM clock is system clock /4 +#define PWM_SYSCLK_DIV_8 0x00000102 // PWM clock is system clock /8 +#define PWM_SYSCLK_DIV_16 0x00000103 // PWM clock is system clock /16 +#define PWM_SYSCLK_DIV_32 0x00000104 // PWM clock is system clock /32 +#define PWM_SYSCLK_DIV_64 0x00000105 // PWM clock is system clock /64 + +//***************************************************************************** +// +// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode +// to use when enabling or disabling outputs using PWMOutputState(). +// +//***************************************************************************** +#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately +#define PWM_OUTPUT_MODE_SYNC_LOCAL \ + 0x00000002 // Updates are locally synchronized +#define PWM_OUTPUT_MODE_SYNC_GLOBAL \ + 0x00000003 // Updates are globally synchronized + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Config); +extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Period); +extern uint32_t PWMGenPeriodGet(uint32_t ui32Base, + uint32_t ui32Gen); +extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, + uint32_t ui32Width); +extern uint32_t PWMPulseWidthGet(uint32_t ui32Base, + uint32_t ui32PWMOut); +extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint16_t ui16Rise, uint16_t ui16Fall); +extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits); +extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits); +extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bEnable); +extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bInvert); +extern void PWMOutputFaultLevel(uint32_t ui32Base, + uint32_t ui32PWMOutBits, + bool bDriveHigh); +extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bFaultSuppress); +extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMFaultIntRegister(uint32_t ui32Base, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(uint32_t ui32Base); +extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig); +extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig); +extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, + bool bMasked); +extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Ints); +extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault); +extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault); +extern void PWMFaultIntClear(uint32_t ui32Base); +extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked); +extern void PWMFaultIntClearExt(uint32_t ui32Base, + uint32_t ui32FaultInts); +extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32MinFaultPeriod, + uint32_t ui32FaultSenses); +extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, + uint32_t ui32FaultTriggers); +extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base, + uint32_t ui32Gen, + uint32_t ui32Group); +extern uint32_t PWMGenFaultStatus(uint32_t ui32Base, + uint32_t ui32Gen, + uint32_t ui32Group); +extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, + uint32_t ui32FaultTriggers); +extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config); +extern uint32_t PWMClockGet(uint32_t ui32Base); +extern void PWMOutputUpdateMode(uint32_t ui32Base, + uint32_t ui32PWMOutBits, + uint32_t ui32Mode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_PWM_H__ diff --git a/CCS/mm/inc/tivaware/qei.h b/CCS/mm/inc/tivaware/qei.h new file mode 100644 index 0000000..3f9b020 --- /dev/null +++ b/CCS/mm/inc/tivaware/qei.h @@ -0,0 +1,156 @@ +#include +#include +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_QEI_H__ +#define __DRIVERLIB_QEI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ui32Config paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIFilterConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks +#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks +#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks +#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks +#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks +#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks +#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks +#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks +#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks +#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks +#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks +#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks +#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks +#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks +#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks +#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ui32IntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(uint32_t ui32Base); +extern void QEIDisable(uint32_t ui32Base); +extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxPosition); +extern uint32_t QEIPositionGet(uint32_t ui32Base); +extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position); +extern int32_t QEIDirectionGet(uint32_t ui32Base); +extern bool QEIErrorGet(uint32_t ui32Base); +extern void QEIFilterEnable(uint32_t ui32Base); +extern void QEIFilterDisable(uint32_t ui32Base); +extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt); +extern void QEIVelocityEnable(uint32_t ui32Base); +extern void QEIVelocityDisable(uint32_t ui32Base); +extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, + uint32_t ui32Period); +extern uint32_t QEIVelocityGet(uint32_t ui32Base); +extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void QEIIntUnregister(uint32_t ui32Base); +extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked); +extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_QEI_H__ diff --git a/CCS/mm/inc/tivaware/rom.h b/CCS/mm/inc/tivaware/rom.h new file mode 100644 index 0000000..df53398 --- /dev/null +++ b/CCS/mm/inc/tivaware/rom.h @@ -0,0 +1,8350 @@ +#include +#include +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ROM_H__ +#define __DRIVERLIB_ROM_H__ + +#define TARGET_IS_TM4C123_RB1 + +#ifndef DEPRECATED +//***************************************************************************** +// +// ROM selection labels changed between TivaWare 2.0.1 and 2.1. The following +// labels are intended to ensure backwards compatibility for applications +// which have not yet been updated to use the replacement labels. +// +//***************************************************************************** +#ifdef TARGET_IS_SNOWFLAKE_RA0 +#define TARGET_IS_TM4C129_RA0 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA1 +#define TARGET_IS_TM4C129_RA1 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA2 +#define TARGET_IS_TM4C129_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA1 +#define TARGET_IS_TM4C123_RA1 +#endif +#ifdef TARGET_IS_BLIZZARD_RA2 +#define TARGET_IS_TM4C123_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA3 +#define TARGET_IS_TM4C123_RA3 +#endif +#ifdef TARGET_IS_BLIZZARD_RB0 +#define TARGET_IS_TM4C123_RB0 +#endif +#ifdef TARGET_IS_BLIZZARD_RB1 +#define TARGET_IS_TM4C123_RB1 +#endif +#endif + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((uint32_t *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((uint32_t *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((uint32_t *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((uint32_t *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((uint32_t *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((uint32_t *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((uint32_t *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((uint32_t *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((uint32_t *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((uint32_t *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((uint32_t *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((uint32_t *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((uint32_t *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((uint32_t *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((uint32_t *)(ROM_APITABLE[14])) +#define ROM_USBTABLE ((uint32_t *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((uint32_t *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((uint32_t *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((uint32_t *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((uint32_t *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((uint32_t *)(ROM_APITABLE[21])) +#define ROM_EPITABLE ((uint32_t *)(ROM_APITABLE[23])) +#define ROM_EEPROMTABLE ((uint32_t *)(ROM_APITABLE[24])) +#define ROM_FPUTABLE ((uint32_t *)(ROM_APITABLE[26])) +#define ROM_SMBUSTABLE ((uint32_t *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((uint32_t *)(ROM_APITABLE[30])) +#define ROM_ONEWIRETABLE ((uint32_t *)(ROM_APITABLE[34])) +#define ROM_SPIFLASHTABLE ((uint32_t *)(ROM_APITABLE[38])) +#define ROM_LCDTABLE ((uint32_t *)(ROM_APITABLE[41])) +#define ROM_EMACTABLE ((uint32_t *)(ROM_APITABLE[42])) +#define ROM_AESTABLE ((uint32_t *)(ROM_APITABLE[43])) +#define ROM_CRCTABLE ((uint32_t *)(ROM_APITABLE[44])) +#define ROM_DESTABLE ((uint32_t *)(ROM_APITABLE[45])) +#define ROM_SHAMD5TABLE ((uint32_t *)(ROM_APITABLE[46])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t *pui32Buffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + bool bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Trigger, \ + uint32_t ui32Priority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Step, \ + uint32_t ui32Config))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCProcessorTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Factor))ROM_ADCTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_ADCTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorRegionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32LowRef, \ + uint32_t ui32HighRef))ROM_ADCTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bTrigger, \ + bool bInterrupt))ROM_ADCTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Status))ROM_ADCTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Phase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelayGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ADCTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCBusy \ + ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the AES API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_AESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESAuthLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_AESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_AESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t ui32Length, \ + uint32_t *pui32Tag))ROM_AESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_AESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcessAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length, \ + uint32_t *pui32AuthSrc, \ + uint32_t ui32AuthLength, \ + uint32_t *pui32Tag))ROM_AESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey1Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey2Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey3Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_AESTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Length))ROM_AESTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESReset \ + ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESTagRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TagData))ROM_AESTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAN API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANInit \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANEnable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANDisable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingSet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingGet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + bool bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANStatusGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetryGet \ + ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetrySet \ + ((void (*)(uint32_t ui32Base, \ + bool bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANErrCntrGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32RxCount, \ + uint32_t *pui32TxCount))ROM_CANTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitRateSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SourceClock, \ + uint32_t ui32BitRate))ROM_CANTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorRefSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorValueGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CRC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataProcess \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32DataIn, \ + uint32_t ui32DataLength, \ + bool bPPResult))ROM_CRCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_CRCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCResultRead \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bPPResult))ROM_CRCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCSeedSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seed))ROM_CRCTABLE[4]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the DES API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_DESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_DESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_DESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIVSet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_DESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_DESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_DESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESReset \ + ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EEPROM API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMRead \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockCountGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockHide \ + ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockLock \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockPasswordSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectGet \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t ui32Protect))ROM_EEPROMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockUnlock \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) +#define ROM_EEPROMMassErase \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgram \ + ((uint32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgramNonBlocking \ + ((uint32_t (*)(uint32_t ui32Data, \ + uint32_t ui32Address))ROM_EEPROMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMSizeGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMStatusGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMInit \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EPI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EPITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_EPITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Divider))ROM_EPITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigSDRAMSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32Refresh))ROM_EPITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigGPModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32FrameCount, \ + uint32_t ui32MaxWait))ROM_EPITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIAddressMapSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Map))ROM_EPITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32DataSize, \ + uint32_t ui32Address))ROM_EPITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStart \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Count))ROM_EPITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStop \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadCount \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadAvail \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet32 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t *pui32Buf))ROM_EPITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet16 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint16_t *pui16Buf))ROM_EPITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet8 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint8_t *pui8Buf))ROM_EPITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIFIFOConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EPITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIWriteFIFOCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ErrFlags))ROM_EPITABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerCSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Divider))ROM_EPITABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDMATxCount \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count))ROM_EPITABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32CR))ROM_EPITABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t *pui32CR))ROM_EPITABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[31]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EMAC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EMACTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Config, \ + uint32_t *pui32Mode, \ + uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32ModeFlags, \ + uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACDMAStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SysClk, \ + uint32_t ui32BusConfig, \ + uint32_t ui32RxBurst, \ + uint32_t ui32TxBurst, \ + uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOff \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOn \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr))ROM_EMACTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACReset \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxWatchdogTimerSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Timeout))ROM_EMACTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxFlush \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Index))ROM_EMACTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint32_t ui32Config))ROM_EMACTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterBitCalculate \ + ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32HashHi, \ + uint32_t *pui32HashLo))ROM_EMACTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32HashHi, \ + uint32_t ui32HashLo))ROM_EMACTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACNumAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr))ROM_EMACTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_EMACTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterGet \ + ((void (*)(uint32_t ui32Base, \ + tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampAddendSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds))ROM_EMACTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommand \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Cmd))ROM_EMACTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommandModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Period, \ + uint32_t ui32Width))ROM_EMACTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSSimpleModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Seconds, \ + uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds, \ + bool bInc))ROM_EMACTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterBitCalculate \ + ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Hash))ROM_EMACTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateEMAC \ + ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProgram \ + ((int32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashErase \ + ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSet \ + ((int32_t (*)(uint32_t ui32Address, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserGet \ + ((int32_t (*)(uint32_t *pui32User0, \ + uint32_t *pui32User1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSet \ + ((int32_t (*)(uint32_t ui32User0, \ + uint32_t ui32User1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUNaNModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPURoundingModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinWrite \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint8_t ui8Val))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32PinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32IntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPadConfigSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32Strength, \ + uint32_t ui32PadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPadConfigGet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pin, \ + uint32_t *pui32Strength, \ + uint32_t *pui32PadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinRead \ + ((int32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypePWM \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUART \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeADC \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinConfigure \ + ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBAnalog \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2CSCL \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeOneWire \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeHigh \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeLow \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntClear \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntDisable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntEnable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntStatus \ + ((uint32_t (*)(uint32_t ui32Port, \ + bool bMasked))ROM_GPIOTABLE[54]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Hibernate API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateEnableExpClk \ + ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeSet \ + ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatSet \ + ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSet \ + ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataSet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataGet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIsActive \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateClockConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckDone \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionGet \ + ((bool (*)(void))ROM_HIBERNATETABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCounterMode \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarSet \ + ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarGet \ + ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchSet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchGet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsClear \ + ((void (*)(void))ROM_HIBERNATETABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsGet \ + ((bool (*)(uint32_t ui32Index, \ + uint32_t *pui32RTC, \ + uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscValid \ + ((bool (*)(void))ROM_HIBERNATETABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscRecover \ + ((void (*)(void))ROM_HIBERNATETABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIODisable \ + ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIOEnable \ + ((void (*)(uint32_t ui32Input, \ + uint32_t ui32Config))ROM_HIBERNATETABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperStatusGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[52]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32I2CClk, \ + bool bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveInit \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr, \ + bool bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Cmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Value))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(uint32_t ui32Base, \ + bool bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8AddrNum, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterLineStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFOStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPutNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGetNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t *pui8Data))ROM_I2CTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Length))ROM_I2CTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFOEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterGlitchFilterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[54]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterEnable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterDisable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, \ + uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskSet \ + ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntIsEnabled \ + ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntTrigger \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the LCD API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_LCDTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDClockReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clocks))ROM_LCDTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDCommandWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Cmd))ROM_LCDTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Data))ROM_LCDTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMADisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMAWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_LCDTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr))ROM_LCDTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr, \ + uint16_t ui16Data))ROM_LCDTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDStatusRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDTimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDModeSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Mode, \ + uint32_t ui32PixClk, \ + uint32_t ui32SysClk))ROM_LCDTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterACBiasIntCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Count))ROM_LCDTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterFrameBufferSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Buffer, \ + uint32_t *pui32Addr, \ + uint32_t ui32NumBytes))ROM_LCDTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterPaletteSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type, \ + uint32_t *pui32PalAddr, \ + const uint32_t *pui32SrcColors, \ + uint32_t ui32Start, \ + uint32_t ui32Count))ROM_LCDTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags, \ + uint32_t ui32BottomLines, \ + uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterTimingSet \ + ((void (*)(uint32_t ui32Base, \ + const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the MPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUEnable \ + ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionCountGet \ + ((uint32_t (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionEnable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionDisable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionSet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionGet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t *pui32Addr, \ + uint32_t *pui32Flags))ROM_MPUTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the OneWire API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ONEWIRETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusReset \ + ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGet \ + ((void (*)(uint32_t u3i2Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireTransaction \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32OpFlags, \ + uint32_t ui32Data, \ + uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut, \ + uint32_t ui32Width))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Config))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Period))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint16_t ui16Rise, \ + uint16_t ui16Fall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncTimeBase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputState \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputInvert \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFault \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + bool bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Ints))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClear \ + ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32MinFaultPeriod, \ + uint32_t ui32FaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_PWMTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputUpdateMode \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + uint32_t ui32Mode))ROM_PWMTABLE[31]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Position))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDirectionGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIErrorGet \ + ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PreDiv, \ + uint32_t ui32Period))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SHAMD5 API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SHAMD5TABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMADisable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMAEnable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HashLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_SHAMD5TABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeyGenerate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5Reset \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ResultRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SMBus API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t *pui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t ui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Data))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8OwnSlaveAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData, \ + uint8_t ui8RxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase, \ + uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + bool bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusRxPacketSizeGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *psSMBus, \ + bool bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8AddressNum, \ + uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveCommandGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *psSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveDataSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFOEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFODisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMAEnable \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8TxChannel, \ + uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMADisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SPIFlash API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashIntHandler \ + ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clock, \ + uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteStatus \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgram \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgramNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteDisable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadStatus \ + ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteEnable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashSectorErase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase32 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadID \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8ManufacturerID, \ + uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashChipErase \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase64 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SSIClk, \ + uint32_t ui32Protocol, \ + uint32_t ui32Mode, \ + uint32_t ui32BitRate, \ + uint32_t ui32DataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIBusy \ + ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_SSITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SSITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEnd \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEndNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSRAMSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPresent \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntEnable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntDisable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntClear \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDelay \ + ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReady \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPIOSCCalibrate \ + ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleepClockConfigSet \ + ((void (*)(uint32_t ui32Div, \ + uint32_t ui32Config))ROM_SYSCTLTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorSet \ + ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSectorSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlClockOutConfig \ + ((void (*)(uint32_t ui32Config, \ + uint32_t ui32Div))ROM_SYSCTLTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlAltClkConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysExc API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickValueGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodSet \ + ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA1) +#define ROM_TimerControlTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlEvent \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Event))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCEnable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCDisable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerValueGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_TIMERTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerValueGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_TIMERTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerSynchronize \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timers))ROM_TIMERTABLE[34]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Parity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32TxLevel, \ + uint32_t ui32RxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TxLevel, \ + uint32_t *pui32RxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t ui32Baud, \ + uint32_t ui32Config))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t *pui32Baud, \ + uint32_t *pui32Config))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnableSIR \ + ((void (*)(uint32_t ui32Base, \ + bool bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisableSIR \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharsAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSpaceAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBreakCtl \ + ((void (*)(uint32_t ui32Base, \ + bool bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBusy \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorClear \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr, \ + uint8_t ui8Mask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSend \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr))ROM_UARTTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[44]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Mode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + uint32_t ui32TransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusGet \ + ((uint32_t (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelEnable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelDisable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelIsEnabled \ + ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelRequest \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Control))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectSecondary \ + ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectDefault \ + ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntStatus \ + ((uint32_t (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntClear \ + ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32TaskCount, \ + void *pvTaskList, \ + uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAssign \ + ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the USB API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevConnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevDisconnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32Flags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t *pui32Size))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataPut \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t ui32Size))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataSend \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32TransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32FIFOAddress, \ + uint32_t *pui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32FIFOAddress, \ + uint32_t ui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOFlush \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFrameNumberGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32NAKPollInterval, \ + uint32_t ui32TargetEndpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bDataToggle, \ + uint32_t ui32Flags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestIN \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestStatus \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostReset \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostResume \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSuspend \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32MaxPacketSize, \ + uint32_t *pui32Flags))ROM_USBTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataAvail \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAChannel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Channel))ROM_USBTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusControl \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusEndpoint \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOff \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOn \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUSB \ + ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestINClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBNumEndpointsGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Div, \ + uint32_t ui32Flags))ROM_USBTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBControllerVersion \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMRemoteWake \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressGet \ + ((void * (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + void *pvAddress))ROM_USBTABLE[71]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[72]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[73]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[74]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[75]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[76]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[77]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t ui32Channel))ROM_USBTABLE[78]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[80]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Status))ROM_USBTABLE[81]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHighSpeed \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_USBTABLE[82]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointPing \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bEnable))ROM_USBTABLE[83]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointSpeed \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[84]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ResumeTime, \ + uint32_t ui32Config))ROM_USBTABLE[85]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMResume \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMSend \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address, \ + uint32_t uiEndpoint))ROM_USBTABLE[87]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[88]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[89]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMLinkStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointPacketCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Count))ROM_USBTABLE[92]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[93]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegRead \ + ((uint8_t (*)(uint32_t ui32Base, \ + uint8_t ui8Reg))ROM_USBTABLE[96]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Reg, \ + uint8_t ui8Data))ROM_USBTABLE[97]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGSessionRequest \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[98]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMANumChannels \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[100]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMRemoteWakeEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_USBTABLE[103]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntClear \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogRunning \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogUnlock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLockState \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogValueGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Software API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array \ + ((uint16_t (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array3 \ + ((void (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data, \ + uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16 \ + ((uint16_t (*)(uint16_t ui16Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc8CCITT \ + ((uint8_t (*)(uint8_t ui8Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc32 \ + ((uint32_t (*)(uint32_t ui32Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +#endif // __DRIVERLIB_ROM_H__ diff --git a/CCS/mm/inc/tivaware/ssi.h b/CCS/mm/inc/tivaware/ssi.h new file mode 100644 index 0000000..322e278 --- /dev/null +++ b/CCS/mm/inc/tivaware/ssi.h @@ -0,0 +1,159 @@ +#include +#include +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SSI_H__ +#define __DRIVERLIB_SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXEOT 0x00000040 // Transmit FIFO is empty +#define SSI_DMATX 0x00000020 // DMA Transmit complete +#define SSI_DMARX 0x00000010 // DMA Receive complete +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +#define SSI_CLOCK_SYSTEM 0x00000000 +#define SSI_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// Values that can be passed to SSIAdvModeSet(). +// +//***************************************************************************** +#define SSI_ADV_MODE_LEGACY 0x00000000 +#define SSI_ADV_MODE_READ_WRITE 0x000001c0 +#define SSI_ADV_MODE_WRITE 0x000000c0 +#define SSI_ADV_MODE_BI_READ 0x00000140 +#define SSI_ADV_MODE_BI_WRITE 0x00000040 +#define SSI_ADV_MODE_QUAD_READ 0x00000180 +#define SSI_ADV_MODE_QUAD_WRITE 0x00000080 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, + uint32_t ui32DataWidth); +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, + uint32_t *pui32Data); +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); +extern void SSIDisable(uint32_t ui32Base); +extern void SSIEnable(uint32_t ui32Base); +extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked); +extern void SSIIntUnregister(uint32_t ui32Base); +extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern bool SSIBusy(uint32_t ui32Base); +extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t SSIClockSourceGet(uint32_t ui32Base); +extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data); +extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, + uint32_t ui32Data); +extern void SSIAdvFrameHoldEnable(uint32_t ui32Base); +extern void SSIAdvFrameHoldDisable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SSI_H__ diff --git a/CCS/mm/inc/tivaware/sysctl.h b/CCS/mm/inc/tivaware/sysctl.h new file mode 100644 index 0000000..33b1072 --- /dev/null +++ b/CCS/mm/inc/tivaware/sysctl.h @@ -0,0 +1,661 @@ +#include +#include +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSCTL_H__ +#define __DRIVERLIB_SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0 +#define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0 +#define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0 +#define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1 +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T +#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6 +#define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7 +#define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8 +#define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9 +#define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0 +#define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0 +#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6 +#define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7 +#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSleepSet() and +// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the +// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. +// +//***************************************************************************** +#define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V +#define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V +#define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V +#define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V +#define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V +#define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V +#define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0 +#define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1 +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request +#define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset +#ifndef DEPRECATED +#define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0 + // Watchdog reset(Deprecated) +#endif +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz +#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep +#define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPIOSCCalibrate() +// API as the ui32Type parameter. +// +//***************************************************************************** +#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration +#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration +#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlMOSCConfigSet() API +// as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation +#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail +#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC +#define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC. +#define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz +#define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz +#define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source. + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlSleepPowerSet() and +// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode + // (Deep Sleep Only) +#define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode + // (Deep Sleep Only) +#define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode +#define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode +#define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode +#define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode +#define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode + +//***************************************************************************** +// +// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. +// +//***************************************************************************** +#define SYSCTL_ONRST_WDOG0_POR 0x00000030 +#define SYSCTL_ONRST_WDOG0_SYS 0x00000020 +#define SYSCTL_ONRST_WDOG1_POR 0x000000C0 +#define SYSCTL_ONRST_WDOG1_SYS 0x00000080 +#define SYSCTL_ONRST_BOR_POR 0x0000000C +#define SYSCTL_ONRST_BOR_SYS 0x00000008 +#define SYSCTL_ONRST_EXT_POR 0x00000003 +#define SYSCTL_ONRST_EXT_SYS 0x00000002 + +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventConfig() API. +// +//***************************************************************************** +#define SYSCTL_VEVENT_VDDABO_NONE \ + 0x00000000 +#define SYSCTL_VEVENT_VDDABO_INT \ + 0x00000100 +#define SYSCTL_VEVENT_VDDABO_NMI \ + 0x00000200 +#define SYSCTL_VEVENT_VDDABO_RST \ + 0x00000300 +#define SYSCTL_VEVENT_VDDBO_NONE \ + 0x00000000 +#define SYSCTL_VEVENT_VDDBO_INT 0x00000001 +#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002 +#define SYSCTL_VEVENT_VDDBO_RST 0x00000003 + +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventStatus() and +// SysCtlVoltageEventClear() APIs. +// +//***************************************************************************** +#define SYSCTL_VESTAT_VDDBOR 0x00000040 +#define SYSCTL_VESTAT_VDDABOR 0x00000010 + +//***************************************************************************** +// +// Values used with the SysCtlNMIStatus() API. +// +//***************************************************************************** +#define SYSCTL_NMI_MOSCFAIL 0x00010000 +#define SYSCTL_NMI_TAMPER 0x00000200 +#define SYSCTL_NMI_WDT1 0x00000020 +#define SYSCTL_NMI_WDT0 0x00000008 +#define SYSCTL_NMI_POWER 0x00000004 +#define SYSCTL_NMI_EXTERNAL 0x00000001 + +//***************************************************************************** +// +// The defines for the SysCtlClockOutConfig() API. +// +//***************************************************************************** +#define SYSCTL_CLKOUT_EN 0x80000000 +#define SYSCTL_CLKOUT_DIS 0x00000000 +#define SYSCTL_CLKOUT_SYSCLK 0x00000000 +#define SYSCTL_CLKOUT_PIOSC 0x00010000 +#define SYSCTL_CLKOUT_MOSC 0x00020000 + +//***************************************************************************** +// +// The following defines are used with the SysCtlAltClkConfig() function. +// +//***************************************************************************** +#define SYSCTL_ALTCLK_PIOSC 0x00000000 +#define SYSCTL_ALTCLK_RTCOSC 0x00000003 +#define SYSCTL_ALTCLK_LFIOSC 0x00000004 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t SysCtlSRAMSizeGet(void); +extern uint32_t SysCtlFlashSizeGet(void); +extern uint32_t SysCtlFlashSectorSizeGet(void); +extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); +extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral); +extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral); +extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral); +extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); +extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralClockGating(bool bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(uint32_t ui32Ints); +extern void SysCtlIntDisable(uint32_t ui32Ints); +extern void SysCtlIntClear(uint32_t ui32Ints); +extern uint32_t SysCtlIntStatus(bool bMasked); +extern void SysCtlLDOSleepSet(uint32_t ui32Voltage); +extern uint32_t SysCtlLDOSleepGet(void); +extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage); +extern uint32_t SysCtlLDODeepSleepGet(void); +extern void SysCtlSleepPowerSet(uint32_t ui32Config); +extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern uint32_t SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(uint32_t ui32Causes); +extern void SysCtlBrownOutConfigSet(uint32_t ui32Config, + uint32_t ui32Delay); +extern void SysCtlDelay(uint32_t ui32Count); +extern void SysCtlMOSCConfigSet(uint32_t ui32Config); +extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type); +extern void SysCtlClockSet(uint32_t ui32Config); +extern uint32_t SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(uint32_t ui32Config); +extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, + uint32_t ui32Config); +extern void SysCtlPWMClockSet(uint32_t ui32Config); +extern uint32_t SysCtlPWMClockGet(void); +extern void SysCtlIOSCVerificationSet(bool bEnable); +extern void SysCtlMOSCVerificationSet(bool bEnable); +extern void SysCtlPLLVerificationSet(bool bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral); +extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config, + uint32_t ui32SysClock); +extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior); +extern uint32_t SysCtlResetBehaviorGet(void); +extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div); +extern void SysCtlAltClkConfig(uint32_t ui32Config); +extern uint32_t SysCtlNMIStatus(void); +extern void SysCtlNMIClear(uint32_t ui32Status); +extern void SysCtlVoltageEventConfig(uint32_t ui32Config); +extern uint32_t SysCtlVoltageEventStatus(void); +extern void SysCtlVoltageEventClear(uint32_t ui32Status); +extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSCTL_H__ diff --git a/CCS/mm/inc/tivaware/systick.h b/CCS/mm/inc/tivaware/systick.h new file mode 100644 index 0000000..c261b80 --- /dev/null +++ b/CCS/mm/inc/tivaware/systick.h @@ -0,0 +1,82 @@ +#include +#include +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSTICK_H__ +#define __DRIVERLIB_SYSTICK_H__ + +#include + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(uint32_t ui32Period); +extern uint32_t SysTickPeriodGet(void); +extern uint32_t SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSTICK_H__ diff --git a/CCS/mm/inc/tivaware/timer.h b/CCS/mm/inc/tivaware/timer.h new file mode 100644 index 0000000..b8f9d2e --- /dev/null +++ b/CCS/mm/inc/tivaware/timer.h @@ -0,0 +1,303 @@ +#include +#include +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_TIMER_H__ +#define __DRIVERLIB_TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_A_ACT_TOINTD 0x00010000 // Timer A compare action disable + // time-out interrupt. +#define TIMER_CFG_A_ACT_NONE 0x00000000 // Timer A compare action none. +#define TIMER_CFG_A_ACT_TOGGLE 0x00020000 // Timer A compare action toggle. +#define TIMER_CFG_A_ACT_CLRTO 0x00040000 // Timer A compare action CCP + // clear on time-out. +#define TIMER_CFG_A_ACT_SETTO 0x00060000 // Timer A compare action CCP set + // on time-out. +#define TIMER_CFG_A_ACT_SETTOGTO 0x00080000 // Timer A compare action set CCP + // toggle on time-out. +#define TIMER_CFG_A_ACT_CLRTOGTO 0x000A0000 // Timer A compare action clear + // CCP toggle on time-out. +#define TIMER_CFG_A_ACT_SETCLRTO 0x000C0000 // Timer A compare action set CCP + // clear on time-out. +#define TIMER_CFG_A_ACT_CLRSETTO 0x000E0000 // Timer A compare action clear + // CCP set on time-out. +#define TIMER_CFG_B_ACT_TOINTD 0x00100000 // Timer B compare action disable + // time-out interrupt. +#define TIMER_CFG_B_ACT_NONE 0x00000000 // Timer A compare action none. +#define TIMER_CFG_B_ACT_TOGGLE 0x00200000 // Timer A compare action toggle. +#define TIMER_CFG_B_ACT_CLRTO 0x00400000 // Timer A compare action CCP + // clear on time-out. +#define TIMER_CFG_B_ACT_SETTO 0x00600000 // Timer A compare action CCP set + // on time-out. +#define TIMER_CFG_B_ACT_SETTOGTO 0x00800000 // Timer A compare action set CCP + // toggle on time-out. +#define TIMER_CFG_B_ACT_CLRTOGTO 0x00A00000 // Timer A compare action clear + // CCP toggle on time-out. +#define TIMER_CFG_B_ACT_SETCLRTO 0x00C00000 // Timer A compare action set CCP + // clear on time-out. +#define TIMER_CFG_B_ACT_CLRSETTO 0x0000E000 // Timer A compare action clear + // CCP set on time-out. + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Complete Interrupt. +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Complete Interrupt. +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ui32Timers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A +#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B +#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A +#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B +#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A +#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B +#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A +#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B +#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A +#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B +#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A +#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B +#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A +#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B +#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A +#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B + +//***************************************************************************** +// +// Values that can be passed to TimerClockSourceSet() or returned from +// TimerClockSourceGet(). +// +//***************************************************************************** +#define TIMER_CLOCK_SYSTEM 0x00000000 +#define TIMER_CLOCK_PIOSC 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerDMAEventSet() or returned from +// TimerDMAEventGet(). +// +//***************************************************************************** +#define TIMER_DMA_MODEMATCH_B 0x00000800 +#define TIMER_DMA_CAPEVENT_B 0x00000400 +#define TIMER_DMA_CAPMATCH_B 0x00000200 +#define TIMER_DMA_TIMEOUT_B 0x00000100 +#define TIMER_DMA_MODEMATCH_A 0x00000010 +#define TIMER_DMA_RTC_A 0x00000008 +#define TIMER_DMA_CAPEVENT_A 0x00000004 +#define TIMER_DMA_CAPMATCH_A 0x00000002 +#define TIMER_DMA_TIMEOUT_A 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerADCEventSet() or returned from +// TimerADCEventGet(). +// +//***************************************************************************** +#define TIMER_ADC_MODEMATCH_B 0x00000800 +#define TIMER_ADC_CAPEVENT_B 0x00000400 +#define TIMER_ADC_CAPMATCH_B 0x00000200 +#define TIMER_ADC_TIMEOUT_B 0x00000100 +#define TIMER_ADC_MODEMATCH_A 0x00000010 +#define TIMER_ADC_RTC_A 0x00000008 +#define TIMER_ADC_CAPEVENT_A 0x00000004 +#define TIMER_ADC_CAPMATCH_A 0x00000002 +#define TIMER_ADC_TIMEOUT_A 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerUpdateMode(). +// +//***************************************************************************** +#define TIMER_UP_LOAD_IMMEDIATE 0x00000000 +#define TIMER_UP_LOAD_TIMEOUT 0x00000100 +#define TIMER_UP_MATCH_IMMEDIATE \ + 0x00000000 +#define TIMER_UP_MATCH_TIMEOUT 0x00000400 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); +extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); +extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bEnable); +extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Event); +extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); +extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); +extern void TimerRTCEnable(uint32_t ui32Base); +extern void TimerRTCDisable(uint32_t ui32Base); +extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value); +extern uint64_t TimerLoadGet64(uint32_t ui32Base); +extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer); +extern uint64_t TimerValueGet64(uint32_t ui32Base); +extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value); +extern uint64_t TimerMatchGet64(uint32_t ui32Base); +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked); +extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers); +extern uint32_t TimerClockSourceGet(uint32_t ui32Base); +extern void TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t TimerADCEventGet(uint32_t ui32Base); +extern void TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent); +extern uint32_t TimerDMAEventGet(uint32_t ui32Base); +extern void TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent); +extern void TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Config); +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_TIMER_H__ diff --git a/CCS/mm/inc/tivaware/uart.h b/CCS/mm/inc/tivaware/uart.h new file mode 100644 index 0000000..ea3fb44 --- /dev/null +++ b/CCS/mm/inc/tivaware/uart.h @@ -0,0 +1,258 @@ +#include +#include +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_UART_H__ +#define __DRIVERLIB_UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_DMATX 0x20000 // DMA TX interrupt +#define UART_INT_DMARX 0x10000 // DMA RX interrupt +#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask +#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask +#define UART_INT_RI 0x001 // RI Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +#define UART_CLOCK_SYSTEM 0x00000000 +#define UART_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity); +extern uint32_t UARTParityModeGet(uint32_t ui32Base); +extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel); +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); +extern void UARTEnable(uint32_t ui32Base); +extern void UARTDisable(uint32_t ui32Base); +extern void UARTFIFOEnable(uint32_t ui32Base); +extern void UARTFIFODisable(uint32_t ui32Base); +extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower); +extern void UARTDisableSIR(uint32_t ui32Base); +extern bool UARTCharsAvail(uint32_t ui32Base); +extern bool UARTSpaceAvail(uint32_t ui32Base); +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); +extern int32_t UARTCharGet(uint32_t ui32Base); +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData); +extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData); +extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState); +extern bool UARTBusy(uint32_t ui32Base); +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void UARTIntUnregister(uint32_t ui32Base); +extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked); +extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern uint32_t UARTRxErrorGet(uint32_t ui32Base); +extern void UARTRxErrorClear(uint32_t ui32Base); +extern void UARTSmartCardEnable(uint32_t ui32Base); +extern void UARTSmartCardDisable(uint32_t ui32Base); +extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control); +extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control); +extern uint32_t UARTModemControlGet(uint32_t ui32Base); +extern uint32_t UARTModemStatusGet(uint32_t ui32Base); +extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTFlowControlGet(uint32_t ui32Base); +extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTTxIntModeGet(uint32_t ui32Base); +extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t UARTClockSourceGet(uint32_t ui32Base); +extern void UART9BitEnable(uint32_t ui32Base); +extern void UART9BitDisable(uint32_t ui32Base); +extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, + uint8_t ui8Mask); +extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr); +extern void UARTLoopbackEnable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_UART_H__ diff --git a/CCS/mm/inc/v_tm4c123gh6pm.h b/CCS/mm/inc/v_tm4c123gh6pm.h new file mode 100644 index 0000000..ede66cf --- /dev/null +++ b/CCS/mm/inc/v_tm4c123gh6pm.h @@ -0,0 +1,12870 @@ +//***************************************************************************** +// +// tm4c123gh6pm.h - TM4C123GH6PM Register Definitions +// +// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.0.12573 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __TM4C123GH6PM_H__ +#define __TM4C123GH6PM_H__ + +//***************************************************************************** +// +// Interrupt assignments +// +//***************************************************************************** +#define INT_GPIOA 16 // GPIO Port A +#define INT_GPIOB 17 // GPIO Port B +#define INT_GPIOC 18 // GPIO Port C +#define INT_GPIOD 19 // GPIO Port D +#define INT_GPIOE 20 // GPIO Port E +#define INT_UART0 21 // UART0 +#define INT_UART1 22 // UART1 +#define INT_SSI0 23 // SSI0 +#define INT_I2C0 24 // I2C0 +#define INT_PWM0_FAULT 25 // PWM0 Fault +#define INT_PWM0_0 26 // PWM0 Generator 0 +#define INT_PWM0_1 27 // PWM0 Generator 1 +#define INT_PWM0_2 28 // PWM0 Generator 2 +#define INT_QEI0 29 // QEI0 +#define INT_ADC0SS0 30 // ADC0 Sequence 0 +#define INT_ADC0SS1 31 // ADC0 Sequence 1 +#define INT_ADC0SS2 32 // ADC0 Sequence 2 +#define INT_ADC0SS3 33 // ADC0 Sequence 3 +#define INT_WATCHDOG 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B 40 // 16/32-Bit Timer 2B +#define INT_COMP0 41 // Analog Comparator 0 +#define INT_COMP1 42 // Analog Comparator 1 +#define INT_SYSCTL 44 // System Control +#define INT_FLASH 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF 46 // GPIO Port F +#define INT_UART2 49 // UART2 +#define INT_SSI1 50 // SSI1 +#define INT_TIMER3A 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B 52 // Timer 3B +#define INT_I2C1 53 // I2C1 +#define INT_QEI1 54 // QEI1 +#define INT_CAN0 55 // CAN0 +#define INT_CAN1 56 // CAN1 +#define INT_HIBERNATE 59 // Hibernation Module +#define INT_USB0 60 // USB +#define INT_PWM0_3 61 // PWM Generator 3 +#define INT_UDMA 62 // uDMA Software +#define INT_UDMAERR 63 // uDMA Error +#define INT_ADC1SS0 64 // ADC1 Sequence 0 +#define INT_ADC1SS1 65 // ADC1 Sequence 1 +#define INT_ADC1SS2 66 // ADC1 Sequence 2 +#define INT_ADC1SS3 67 // ADC1 Sequence 3 +#define INT_SSI2 73 // SSI2 +#define INT_SSI3 74 // SSI3 +#define INT_UART3 75 // UART3 +#define INT_UART4 76 // UART4 +#define INT_UART5 77 // UART5 +#define INT_UART6 78 // UART6 +#define INT_UART7 79 // UART7 +#define INT_I2C2 84 // I2C2 +#define INT_I2C3 85 // I2C3 +#define INT_TIMER4A 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC 122 // System Exception (imprecise) +#define INT_PWM1_0 150 // PWM1 Generator 0 +#define INT_PWM1_1 151 // PWM1 Generator 1 +#define INT_PWM1_2 152 // PWM1 Generator 2 +#define INT_PWM1_3 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT 154 // PWM1 Fault + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG0) +// +//***************************************************************************** +#define WATCHDOG0_LOAD_R (*((volatile uint32_t *)0x40000000)) +#define WATCHDOG0_VALUE_R (*((volatile uint32_t *)0x40000004)) +#define WATCHDOG0_CTL_R (*((volatile uint32_t *)0x40000008)) +#define WATCHDOG0_ICR_R (*((volatile uint32_t *)0x4000000C)) +#define WATCHDOG0_RIS_R (*((volatile uint32_t *)0x40000010)) +#define WATCHDOG0_MIS_R (*((volatile uint32_t *)0x40000014)) +#define WATCHDOG0_TEST_R (*((volatile uint32_t *)0x40000418)) +#define WATCHDOG0_LOCK_R (*((volatile uint32_t *)0x40000C00)) + +//***************************************************************************** +// +// Watchdog Timer registers (WATCHDOG1) +// +//***************************************************************************** +#define WATCHDOG1_LOAD_R (*((volatile uint32_t *)0x40001000)) +#define WATCHDOG1_VALUE_R (*((volatile uint32_t *)0x40001004)) +#define WATCHDOG1_CTL_R (*((volatile uint32_t *)0x40001008)) +#define WATCHDOG1_ICR_R (*((volatile uint32_t *)0x4000100C)) +#define WATCHDOG1_RIS_R (*((volatile uint32_t *)0x40001010)) +#define WATCHDOG1_MIS_R (*((volatile uint32_t *)0x40001014)) +#define WATCHDOG1_TEST_R (*((volatile uint32_t *)0x40001418)) +#define WATCHDOG1_LOCK_R (*((volatile uint32_t *)0x40001C00)) + +//***************************************************************************** +// +// GPIO registers (PORTA) +// +//***************************************************************************** +#define GPIO_PORTA_DATA_BITS_R ((volatile uint32_t *)0x40004000) +#define GPIO_PORTA_DATA_R (*((volatile uint32_t *)0x400043FC)) +#define GPIO_PORTA_DIR_R (*((volatile uint32_t *)0x40004400)) +#define GPIO_PORTA_IS_R (*((volatile uint32_t *)0x40004404)) +#define GPIO_PORTA_IBE_R (*((volatile uint32_t *)0x40004408)) +#define GPIO_PORTA_IEV_R (*((volatile uint32_t *)0x4000440C)) +#define GPIO_PORTA_IM_R (*((volatile uint32_t *)0x40004410)) +#define GPIO_PORTA_RIS_R (*((volatile uint32_t *)0x40004414)) +#define GPIO_PORTA_MIS_R (*((volatile uint32_t *)0x40004418)) +#define GPIO_PORTA_ICR_R (*((volatile uint32_t *)0x4000441C)) +#define GPIO_PORTA_AFSEL_R (*((volatile uint32_t *)0x40004420)) +#define GPIO_PORTA_DR2R_R (*((volatile uint32_t *)0x40004500)) +#define GPIO_PORTA_DR4R_R (*((volatile uint32_t *)0x40004504)) +#define GPIO_PORTA_DR8R_R (*((volatile uint32_t *)0x40004508)) +#define GPIO_PORTA_ODR_R (*((volatile uint32_t *)0x4000450C)) +#define GPIO_PORTA_PUR_R (*((volatile uint32_t *)0x40004510)) +#define GPIO_PORTA_PDR_R (*((volatile uint32_t *)0x40004514)) +#define GPIO_PORTA_SLR_R (*((volatile uint32_t *)0x40004518)) +#define GPIO_PORTA_DEN_R (*((volatile uint32_t *)0x4000451C)) +#define GPIO_PORTA_LOCK_R (*((volatile uint32_t *)0x40004520)) +#define GPIO_PORTA_CR_R (*((volatile uint32_t *)0x40004524)) +#define GPIO_PORTA_AMSEL_R (*((volatile uint32_t *)0x40004528)) +#define GPIO_PORTA_PCTL_R (*((volatile uint32_t *)0x4000452C)) +#define GPIO_PORTA_ADCCTL_R (*((volatile uint32_t *)0x40004530)) +#define GPIO_PORTA_DMACTL_R (*((volatile uint32_t *)0x40004534)) + +//***************************************************************************** +// +// GPIO registers (PORTB) +// +//***************************************************************************** +#define GPIO_PORTB_DATA_BITS_R ((volatile uint32_t *)0x40005000) +#define GPIO_PORTB_DATA_R (*((volatile uint32_t *)0x400053FC)) +#define GPIO_PORTB_DIR_R (*((volatile uint32_t *)0x40005400)) +#define GPIO_PORTB_IS_R (*((volatile uint32_t *)0x40005404)) +#define GPIO_PORTB_IBE_R (*((volatile uint32_t *)0x40005408)) +#define GPIO_PORTB_IEV_R (*((volatile uint32_t *)0x4000540C)) +#define GPIO_PORTB_IM_R (*((volatile uint32_t *)0x40005410)) +#define GPIO_PORTB_RIS_R (*((volatile uint32_t *)0x40005414)) +#define GPIO_PORTB_MIS_R (*((volatile uint32_t *)0x40005418)) +#define GPIO_PORTB_ICR_R (*((volatile uint32_t *)0x4000541C)) +#define GPIO_PORTB_AFSEL_R (*((volatile uint32_t *)0x40005420)) +#define GPIO_PORTB_DR2R_R (*((volatile uint32_t *)0x40005500)) +#define GPIO_PORTB_DR4R_R (*((volatile uint32_t *)0x40005504)) +#define GPIO_PORTB_DR8R_R (*((volatile uint32_t *)0x40005508)) +#define GPIO_PORTB_ODR_R (*((volatile uint32_t *)0x4000550C)) +#define GPIO_PORTB_PUR_R (*((volatile uint32_t *)0x40005510)) +#define GPIO_PORTB_PDR_R (*((volatile uint32_t *)0x40005514)) +#define GPIO_PORTB_SLR_R (*((volatile uint32_t *)0x40005518)) +#define GPIO_PORTB_DEN_R (*((volatile uint32_t *)0x4000551C)) +#define GPIO_PORTB_LOCK_R (*((volatile uint32_t *)0x40005520)) +#define GPIO_PORTB_CR_R (*((volatile uint32_t *)0x40005524)) +#define GPIO_PORTB_AMSEL_R (*((volatile uint32_t *)0x40005528)) +#define GPIO_PORTB_PCTL_R (*((volatile uint32_t *)0x4000552C)) +#define GPIO_PORTB_ADCCTL_R (*((volatile uint32_t *)0x40005530)) +#define GPIO_PORTB_DMACTL_R (*((volatile uint32_t *)0x40005534)) + +//***************************************************************************** +// +// GPIO registers (PORTC) +// +//***************************************************************************** +#define GPIO_PORTC_DATA_BITS_R ((volatile uint32_t *)0x40006000) +#define GPIO_PORTC_DATA_R (*((volatile uint32_t *)0x400063FC)) +#define GPIO_PORTC_DIR_R (*((volatile uint32_t *)0x40006400)) +#define GPIO_PORTC_IS_R (*((volatile uint32_t *)0x40006404)) +#define GPIO_PORTC_IBE_R (*((volatile uint32_t *)0x40006408)) +#define GPIO_PORTC_IEV_R (*((volatile uint32_t *)0x4000640C)) +#define GPIO_PORTC_IM_R (*((volatile uint32_t *)0x40006410)) +#define GPIO_PORTC_RIS_R (*((volatile uint32_t *)0x40006414)) +#define GPIO_PORTC_MIS_R (*((volatile uint32_t *)0x40006418)) +#define GPIO_PORTC_ICR_R (*((volatile uint32_t *)0x4000641C)) +#define GPIO_PORTC_AFSEL_R (*((volatile uint32_t *)0x40006420)) +#define GPIO_PORTC_DR2R_R (*((volatile uint32_t *)0x40006500)) +#define GPIO_PORTC_DR4R_R (*((volatile uint32_t *)0x40006504)) +#define GPIO_PORTC_DR8R_R (*((volatile uint32_t *)0x40006508)) +#define GPIO_PORTC_ODR_R (*((volatile uint32_t *)0x4000650C)) +#define GPIO_PORTC_PUR_R (*((volatile uint32_t *)0x40006510)) +#define GPIO_PORTC_PDR_R (*((volatile uint32_t *)0x40006514)) +#define GPIO_PORTC_SLR_R (*((volatile uint32_t *)0x40006518)) +#define GPIO_PORTC_DEN_R (*((volatile uint32_t *)0x4000651C)) +#define GPIO_PORTC_LOCK_R (*((volatile uint32_t *)0x40006520)) +#define GPIO_PORTC_CR_R (*((volatile uint32_t *)0x40006524)) +#define GPIO_PORTC_AMSEL_R (*((volatile uint32_t *)0x40006528)) +#define GPIO_PORTC_PCTL_R (*((volatile uint32_t *)0x4000652C)) +#define GPIO_PORTC_ADCCTL_R (*((volatile uint32_t *)0x40006530)) +#define GPIO_PORTC_DMACTL_R (*((volatile uint32_t *)0x40006534)) + +//***************************************************************************** +// +// GPIO registers (PORTD) +// +//***************************************************************************** +#define GPIO_PORTD_DATA_BITS_R ((volatile uint32_t *)0x40007000) +#define GPIO_PORTD_DATA_R (*((volatile uint32_t *)0x400073FC)) +#define GPIO_PORTD_DIR_R (*((volatile uint32_t *)0x40007400)) +#define GPIO_PORTD_IS_R (*((volatile uint32_t *)0x40007404)) +#define GPIO_PORTD_IBE_R (*((volatile uint32_t *)0x40007408)) +#define GPIO_PORTD_IEV_R (*((volatile uint32_t *)0x4000740C)) +#define GPIO_PORTD_IM_R (*((volatile uint32_t *)0x40007410)) +#define GPIO_PORTD_RIS_R (*((volatile uint32_t *)0x40007414)) +#define GPIO_PORTD_MIS_R (*((volatile uint32_t *)0x40007418)) +#define GPIO_PORTD_ICR_R (*((volatile uint32_t *)0x4000741C)) +#define GPIO_PORTD_AFSEL_R (*((volatile uint32_t *)0x40007420)) +#define GPIO_PORTD_DR2R_R (*((volatile uint32_t *)0x40007500)) +#define GPIO_PORTD_DR4R_R (*((volatile uint32_t *)0x40007504)) +#define GPIO_PORTD_DR8R_R (*((volatile uint32_t *)0x40007508)) +#define GPIO_PORTD_ODR_R (*((volatile uint32_t *)0x4000750C)) +#define GPIO_PORTD_PUR_R (*((volatile uint32_t *)0x40007510)) +#define GPIO_PORTD_PDR_R (*((volatile uint32_t *)0x40007514)) +#define GPIO_PORTD_SLR_R (*((volatile uint32_t *)0x40007518)) +#define GPIO_PORTD_DEN_R (*((volatile uint32_t *)0x4000751C)) +#define GPIO_PORTD_LOCK_R (*((volatile uint32_t *)0x40007520)) +#define GPIO_PORTD_CR_R (*((volatile uint32_t *)0x40007524)) +#define GPIO_PORTD_AMSEL_R (*((volatile uint32_t *)0x40007528)) +#define GPIO_PORTD_PCTL_R (*((volatile uint32_t *)0x4000752C)) +#define GPIO_PORTD_ADCCTL_R (*((volatile uint32_t *)0x40007530)) +#define GPIO_PORTD_DMACTL_R (*((volatile uint32_t *)0x40007534)) + +//***************************************************************************** +// +// SSI registers (SSI0) +// +//***************************************************************************** +#define SSI0_CR0_R (*((volatile uint32_t *)0x40008000)) +#define SSI0_CR1_R (*((volatile uint32_t *)0x40008004)) +#define SSI0_DR_R (*((volatile uint32_t *)0x40008008)) +#define SSI0_SR_R (*((volatile uint32_t *)0x4000800C)) +#define SSI0_CPSR_R (*((volatile uint32_t *)0x40008010)) +#define SSI0_IM_R (*((volatile uint32_t *)0x40008014)) +#define SSI0_RIS_R (*((volatile uint32_t *)0x40008018)) +#define SSI0_MIS_R (*((volatile uint32_t *)0x4000801C)) +#define SSI0_ICR_R (*((volatile uint32_t *)0x40008020)) +#define SSI0_DMACTL_R (*((volatile uint32_t *)0x40008024)) +#define SSI0_CC_R (*((volatile uint32_t *)0x40008FC8)) + +//***************************************************************************** +// +// SSI registers (SSI1) +// +//***************************************************************************** +#define SSI1_CR0_R (*((volatile uint32_t *)0x40009000)) +#define SSI1_CR1_R (*((volatile uint32_t *)0x40009004)) +#define SSI1_DR_R (*((volatile uint32_t *)0x40009008)) +#define SSI1_SR_R (*((volatile uint32_t *)0x4000900C)) +#define SSI1_CPSR_R (*((volatile uint32_t *)0x40009010)) +#define SSI1_IM_R (*((volatile uint32_t *)0x40009014)) +#define SSI1_RIS_R (*((volatile uint32_t *)0x40009018)) +#define SSI1_MIS_R (*((volatile uint32_t *)0x4000901C)) +#define SSI1_ICR_R (*((volatile uint32_t *)0x40009020)) +#define SSI1_DMACTL_R (*((volatile uint32_t *)0x40009024)) +#define SSI1_CC_R (*((volatile uint32_t *)0x40009FC8)) + +//***************************************************************************** +// +// SSI registers (SSI2) +// +//***************************************************************************** +#define SSI2_CR0_R (*((volatile uint32_t *)0x4000A000)) +#define SSI2_CR1_R (*((volatile uint32_t *)0x4000A004)) +#define SSI2_DR_R (*((volatile uint32_t *)0x4000A008)) +#define SSI2_SR_R (*((volatile uint32_t *)0x4000A00C)) +#define SSI2_CPSR_R (*((volatile uint32_t *)0x4000A010)) +#define SSI2_IM_R (*((volatile uint32_t *)0x4000A014)) +#define SSI2_RIS_R (*((volatile uint32_t *)0x4000A018)) +#define SSI2_MIS_R (*((volatile uint32_t *)0x4000A01C)) +#define SSI2_ICR_R (*((volatile uint32_t *)0x4000A020)) +#define SSI2_DMACTL_R (*((volatile uint32_t *)0x4000A024)) +#define SSI2_CC_R (*((volatile uint32_t *)0x4000AFC8)) + +//***************************************************************************** +// +// SSI registers (SSI3) +// +//***************************************************************************** +#define SSI3_CR0_R (*((volatile uint32_t *)0x4000B000)) +#define SSI3_CR1_R (*((volatile uint32_t *)0x4000B004)) +#define SSI3_DR_R (*((volatile uint32_t *)0x4000B008)) +#define SSI3_SR_R (*((volatile uint32_t *)0x4000B00C)) +#define SSI3_CPSR_R (*((volatile uint32_t *)0x4000B010)) +#define SSI3_IM_R (*((volatile uint32_t *)0x4000B014)) +#define SSI3_RIS_R (*((volatile uint32_t *)0x4000B018)) +#define SSI3_MIS_R (*((volatile uint32_t *)0x4000B01C)) +#define SSI3_ICR_R (*((volatile uint32_t *)0x4000B020)) +#define SSI3_DMACTL_R (*((volatile uint32_t *)0x4000B024)) +#define SSI3_CC_R (*((volatile uint32_t *)0x4000BFC8)) + +//***************************************************************************** +// +// UART registers (UART0) +// +//***************************************************************************** +#define UART0_DR_R (*((volatile uint32_t *)0x4000C000)) +#define UART0_RSR_R (*((volatile uint32_t *)0x4000C004)) +#define UART0_ECR_R (*((volatile uint32_t *)0x4000C004)) +#define UART0_FR_R (*((volatile uint32_t *)0x4000C018)) +#define UART0_ILPR_R (*((volatile uint32_t *)0x4000C020)) +#define UART0_IBRD_R (*((volatile uint32_t *)0x4000C024)) +#define UART0_FBRD_R (*((volatile uint32_t *)0x4000C028)) +#define UART0_LCRH_R (*((volatile uint32_t *)0x4000C02C)) +#define UART0_CTL_R (*((volatile uint32_t *)0x4000C030)) +#define UART0_IFLS_R (*((volatile uint32_t *)0x4000C034)) +#define UART0_IM_R (*((volatile uint32_t *)0x4000C038)) +#define UART0_RIS_R (*((volatile uint32_t *)0x4000C03C)) +#define UART0_MIS_R (*((volatile uint32_t *)0x4000C040)) +#define UART0_ICR_R (*((volatile uint32_t *)0x4000C044)) +#define UART0_DMACTL_R (*((volatile uint32_t *)0x4000C048)) +#define UART0_9BITADDR_R (*((volatile uint32_t *)0x4000C0A4)) +#define UART0_9BITAMASK_R (*((volatile uint32_t *)0x4000C0A8)) +#define UART0_PP_R (*((volatile uint32_t *)0x4000CFC0)) +#define UART0_CC_R (*((volatile uint32_t *)0x4000CFC8)) + +//***************************************************************************** +// +// UART registers (UART1) +// +//***************************************************************************** +#define UART1_DR_R (*((volatile uint32_t *)0x4000D000)) +#define UART1_RSR_R (*((volatile uint32_t *)0x4000D004)) +#define UART1_ECR_R (*((volatile uint32_t *)0x4000D004)) +#define UART1_FR_R (*((volatile uint32_t *)0x4000D018)) +#define UART1_ILPR_R (*((volatile uint32_t *)0x4000D020)) +#define UART1_IBRD_R (*((volatile uint32_t *)0x4000D024)) +#define UART1_FBRD_R (*((volatile uint32_t *)0x4000D028)) +#define UART1_LCRH_R (*((volatile uint32_t *)0x4000D02C)) +#define UART1_CTL_R (*((volatile uint32_t *)0x4000D030)) +#define UART1_IFLS_R (*((volatile uint32_t *)0x4000D034)) +#define UART1_IM_R (*((volatile uint32_t *)0x4000D038)) +#define UART1_RIS_R (*((volatile uint32_t *)0x4000D03C)) +#define UART1_MIS_R (*((volatile uint32_t *)0x4000D040)) +#define UART1_ICR_R (*((volatile uint32_t *)0x4000D044)) +#define UART1_DMACTL_R (*((volatile uint32_t *)0x4000D048)) +#define UART1_9BITADDR_R (*((volatile uint32_t *)0x4000D0A4)) +#define UART1_9BITAMASK_R (*((volatile uint32_t *)0x4000D0A8)) +#define UART1_PP_R (*((volatile uint32_t *)0x4000DFC0)) +#define UART1_CC_R (*((volatile uint32_t *)0x4000DFC8)) + +//***************************************************************************** +// +// UART registers (UART2) +// +//***************************************************************************** +#define UART2_DR_R (*((volatile uint32_t *)0x4000E000)) +#define UART2_RSR_R (*((volatile uint32_t *)0x4000E004)) +#define UART2_ECR_R (*((volatile uint32_t *)0x4000E004)) +#define UART2_FR_R (*((volatile uint32_t *)0x4000E018)) +#define UART2_ILPR_R (*((volatile uint32_t *)0x4000E020)) +#define UART2_IBRD_R (*((volatile uint32_t *)0x4000E024)) +#define UART2_FBRD_R (*((volatile uint32_t *)0x4000E028)) +#define UART2_LCRH_R (*((volatile uint32_t *)0x4000E02C)) +#define UART2_CTL_R (*((volatile uint32_t *)0x4000E030)) +#define UART2_IFLS_R (*((volatile uint32_t *)0x4000E034)) +#define UART2_IM_R (*((volatile uint32_t *)0x4000E038)) +#define UART2_RIS_R (*((volatile uint32_t *)0x4000E03C)) +#define UART2_MIS_R (*((volatile uint32_t *)0x4000E040)) +#define UART2_ICR_R (*((volatile uint32_t *)0x4000E044)) +#define UART2_DMACTL_R (*((volatile uint32_t *)0x4000E048)) +#define UART2_9BITADDR_R (*((volatile uint32_t *)0x4000E0A4)) +#define UART2_9BITAMASK_R (*((volatile uint32_t *)0x4000E0A8)) +#define UART2_PP_R (*((volatile uint32_t *)0x4000EFC0)) +#define UART2_CC_R (*((volatile uint32_t *)0x4000EFC8)) + +//***************************************************************************** +// +// UART registers (UART3) +// +//***************************************************************************** +#define UART3_DR_R (*((volatile uint32_t *)0x4000F000)) +#define UART3_RSR_R (*((volatile uint32_t *)0x4000F004)) +#define UART3_ECR_R (*((volatile uint32_t *)0x4000F004)) +#define UART3_FR_R (*((volatile uint32_t *)0x4000F018)) +#define UART3_ILPR_R (*((volatile uint32_t *)0x4000F020)) +#define UART3_IBRD_R (*((volatile uint32_t *)0x4000F024)) +#define UART3_FBRD_R (*((volatile uint32_t *)0x4000F028)) +#define UART3_LCRH_R (*((volatile uint32_t *)0x4000F02C)) +#define UART3_CTL_R (*((volatile uint32_t *)0x4000F030)) +#define UART3_IFLS_R (*((volatile uint32_t *)0x4000F034)) +#define UART3_IM_R (*((volatile uint32_t *)0x4000F038)) +#define UART3_RIS_R (*((volatile uint32_t *)0x4000F03C)) +#define UART3_MIS_R (*((volatile uint32_t *)0x4000F040)) +#define UART3_ICR_R (*((volatile uint32_t *)0x4000F044)) +#define UART3_DMACTL_R (*((volatile uint32_t *)0x4000F048)) +#define UART3_9BITADDR_R (*((volatile uint32_t *)0x4000F0A4)) +#define UART3_9BITAMASK_R (*((volatile uint32_t *)0x4000F0A8)) +#define UART3_PP_R (*((volatile uint32_t *)0x4000FFC0)) +#define UART3_CC_R (*((volatile uint32_t *)0x4000FFC8)) + +//***************************************************************************** +// +// UART registers (UART4) +// +//***************************************************************************** +#define UART4_DR_R (*((volatile uint32_t *)0x40010000)) +#define UART4_RSR_R (*((volatile uint32_t *)0x40010004)) +#define UART4_ECR_R (*((volatile uint32_t *)0x40010004)) +#define UART4_FR_R (*((volatile uint32_t *)0x40010018)) +#define UART4_ILPR_R (*((volatile uint32_t *)0x40010020)) +#define UART4_IBRD_R (*((volatile uint32_t *)0x40010024)) +#define UART4_FBRD_R (*((volatile uint32_t *)0x40010028)) +#define UART4_LCRH_R (*((volatile uint32_t *)0x4001002C)) +#define UART4_CTL_R (*((volatile uint32_t *)0x40010030)) +#define UART4_IFLS_R (*((volatile uint32_t *)0x40010034)) +#define UART4_IM_R (*((volatile uint32_t *)0x40010038)) +#define UART4_RIS_R (*((volatile uint32_t *)0x4001003C)) +#define UART4_MIS_R (*((volatile uint32_t *)0x40010040)) +#define UART4_ICR_R (*((volatile uint32_t *)0x40010044)) +#define UART4_DMACTL_R (*((volatile uint32_t *)0x40010048)) +#define UART4_9BITADDR_R (*((volatile uint32_t *)0x400100A4)) +#define UART4_9BITAMASK_R (*((volatile uint32_t *)0x400100A8)) +#define UART4_PP_R (*((volatile uint32_t *)0x40010FC0)) +#define UART4_CC_R (*((volatile uint32_t *)0x40010FC8)) + +//***************************************************************************** +// +// UART registers (UART5) +// +//***************************************************************************** +#define UART5_DR_R (*((volatile uint32_t *)0x40011000)) +#define UART5_RSR_R (*((volatile uint32_t *)0x40011004)) +#define UART5_ECR_R (*((volatile uint32_t *)0x40011004)) +#define UART5_FR_R (*((volatile uint32_t *)0x40011018)) +#define UART5_ILPR_R (*((volatile uint32_t *)0x40011020)) +#define UART5_IBRD_R (*((volatile uint32_t *)0x40011024)) +#define UART5_FBRD_R (*((volatile uint32_t *)0x40011028)) +#define UART5_LCRH_R (*((volatile uint32_t *)0x4001102C)) +#define UART5_CTL_R (*((volatile uint32_t *)0x40011030)) +#define UART5_IFLS_R (*((volatile uint32_t *)0x40011034)) +#define UART5_IM_R (*((volatile uint32_t *)0x40011038)) +#define UART5_RIS_R (*((volatile uint32_t *)0x4001103C)) +#define UART5_MIS_R (*((volatile uint32_t *)0x40011040)) +#define UART5_ICR_R (*((volatile uint32_t *)0x40011044)) +#define UART5_DMACTL_R (*((volatile uint32_t *)0x40011048)) +#define UART5_9BITADDR_R (*((volatile uint32_t *)0x400110A4)) +#define UART5_9BITAMASK_R (*((volatile uint32_t *)0x400110A8)) +#define UART5_PP_R (*((volatile uint32_t *)0x40011FC0)) +#define UART5_CC_R (*((volatile uint32_t *)0x40011FC8)) + +//***************************************************************************** +// +// UART registers (UART6) +// +//***************************************************************************** +#define UART6_DR_R (*((volatile uint32_t *)0x40012000)) +#define UART6_RSR_R (*((volatile uint32_t *)0x40012004)) +#define UART6_ECR_R (*((volatile uint32_t *)0x40012004)) +#define UART6_FR_R (*((volatile uint32_t *)0x40012018)) +#define UART6_ILPR_R (*((volatile uint32_t *)0x40012020)) +#define UART6_IBRD_R (*((volatile uint32_t *)0x40012024)) +#define UART6_FBRD_R (*((volatile uint32_t *)0x40012028)) +#define UART6_LCRH_R (*((volatile uint32_t *)0x4001202C)) +#define UART6_CTL_R (*((volatile uint32_t *)0x40012030)) +#define UART6_IFLS_R (*((volatile uint32_t *)0x40012034)) +#define UART6_IM_R (*((volatile uint32_t *)0x40012038)) +#define UART6_RIS_R (*((volatile uint32_t *)0x4001203C)) +#define UART6_MIS_R (*((volatile uint32_t *)0x40012040)) +#define UART6_ICR_R (*((volatile uint32_t *)0x40012044)) +#define UART6_DMACTL_R (*((volatile uint32_t *)0x40012048)) +#define UART6_9BITADDR_R (*((volatile uint32_t *)0x400120A4)) +#define UART6_9BITAMASK_R (*((volatile uint32_t *)0x400120A8)) +#define UART6_PP_R (*((volatile uint32_t *)0x40012FC0)) +#define UART6_CC_R (*((volatile uint32_t *)0x40012FC8)) + +//***************************************************************************** +// +// UART registers (UART7) +// +//***************************************************************************** +#define UART7_DR_R (*((volatile uint32_t *)0x40013000)) +#define UART7_RSR_R (*((volatile uint32_t *)0x40013004)) +#define UART7_ECR_R (*((volatile uint32_t *)0x40013004)) +#define UART7_FR_R (*((volatile uint32_t *)0x40013018)) +#define UART7_ILPR_R (*((volatile uint32_t *)0x40013020)) +#define UART7_IBRD_R (*((volatile uint32_t *)0x40013024)) +#define UART7_FBRD_R (*((volatile uint32_t *)0x40013028)) +#define UART7_LCRH_R (*((volatile uint32_t *)0x4001302C)) +#define UART7_CTL_R (*((volatile uint32_t *)0x40013030)) +#define UART7_IFLS_R (*((volatile uint32_t *)0x40013034)) +#define UART7_IM_R (*((volatile uint32_t *)0x40013038)) +#define UART7_RIS_R (*((volatile uint32_t *)0x4001303C)) +#define UART7_MIS_R (*((volatile uint32_t *)0x40013040)) +#define UART7_ICR_R (*((volatile uint32_t *)0x40013044)) +#define UART7_DMACTL_R (*((volatile uint32_t *)0x40013048)) +#define UART7_9BITADDR_R (*((volatile uint32_t *)0x400130A4)) +#define UART7_9BITAMASK_R (*((volatile uint32_t *)0x400130A8)) +#define UART7_PP_R (*((volatile uint32_t *)0x40013FC0)) +#define UART7_CC_R (*((volatile uint32_t *)0x40013FC8)) + +//***************************************************************************** +// +// I2C registers (I2C0) +// +//***************************************************************************** +#define I2C0_MSA_R (*((volatile uint32_t *)0x40020000)) +#define I2C0_MCS_R (*((volatile uint32_t *)0x40020004)) +#define I2C0_MDR_R (*((volatile uint32_t *)0x40020008)) +#define I2C0_MTPR_R (*((volatile uint32_t *)0x4002000C)) +#define I2C0_MIMR_R (*((volatile uint32_t *)0x40020010)) +#define I2C0_MRIS_R (*((volatile uint32_t *)0x40020014)) +#define I2C0_MMIS_R (*((volatile uint32_t *)0x40020018)) +#define I2C0_MICR_R (*((volatile uint32_t *)0x4002001C)) +#define I2C0_MCR_R (*((volatile uint32_t *)0x40020020)) +#define I2C0_MCLKOCNT_R (*((volatile uint32_t *)0x40020024)) +#define I2C0_MBMON_R (*((volatile uint32_t *)0x4002002C)) +#define I2C0_MCR2_R (*((volatile uint32_t *)0x40020038)) +#define I2C0_SOAR_R (*((volatile uint32_t *)0x40020800)) +#define I2C0_SCSR_R (*((volatile uint32_t *)0x40020804)) +#define I2C0_SDR_R (*((volatile uint32_t *)0x40020808)) +#define I2C0_SIMR_R (*((volatile uint32_t *)0x4002080C)) +#define I2C0_SRIS_R (*((volatile uint32_t *)0x40020810)) +#define I2C0_SMIS_R (*((volatile uint32_t *)0x40020814)) +#define I2C0_SICR_R (*((volatile uint32_t *)0x40020818)) +#define I2C0_SOAR2_R (*((volatile uint32_t *)0x4002081C)) +#define I2C0_SACKCTL_R (*((volatile uint32_t *)0x40020820)) +#define I2C0_PP_R (*((volatile uint32_t *)0x40020FC0)) +#define I2C0_PC_R (*((volatile uint32_t *)0x40020FC4)) + +//***************************************************************************** +// +// I2C registers (I2C1) +// +//***************************************************************************** +#define I2C1_MSA_R (*((volatile uint32_t *)0x40021000)) +#define I2C1_MCS_R (*((volatile uint32_t *)0x40021004)) +#define I2C1_MDR_R (*((volatile uint32_t *)0x40021008)) +#define I2C1_MTPR_R (*((volatile uint32_t *)0x4002100C)) +#define I2C1_MIMR_R (*((volatile uint32_t *)0x40021010)) +#define I2C1_MRIS_R (*((volatile uint32_t *)0x40021014)) +#define I2C1_MMIS_R (*((volatile uint32_t *)0x40021018)) +#define I2C1_MICR_R (*((volatile uint32_t *)0x4002101C)) +#define I2C1_MCR_R (*((volatile uint32_t *)0x40021020)) +#define I2C1_MCLKOCNT_R (*((volatile uint32_t *)0x40021024)) +#define I2C1_MBMON_R (*((volatile uint32_t *)0x4002102C)) +#define I2C1_MCR2_R (*((volatile uint32_t *)0x40021038)) +#define I2C1_SOAR_R (*((volatile uint32_t *)0x40021800)) +#define I2C1_SCSR_R (*((volatile uint32_t *)0x40021804)) +#define I2C1_SDR_R (*((volatile uint32_t *)0x40021808)) +#define I2C1_SIMR_R (*((volatile uint32_t *)0x4002180C)) +#define I2C1_SRIS_R (*((volatile uint32_t *)0x40021810)) +#define I2C1_SMIS_R (*((volatile uint32_t *)0x40021814)) +#define I2C1_SICR_R (*((volatile uint32_t *)0x40021818)) +#define I2C1_SOAR2_R (*((volatile uint32_t *)0x4002181C)) +#define I2C1_SACKCTL_R (*((volatile uint32_t *)0x40021820)) +#define I2C1_PP_R (*((volatile uint32_t *)0x40021FC0)) +#define I2C1_PC_R (*((volatile uint32_t *)0x40021FC4)) + +//***************************************************************************** +// +// I2C registers (I2C2) +// +//***************************************************************************** +#define I2C2_MSA_R (*((volatile uint32_t *)0x40022000)) +#define I2C2_MCS_R (*((volatile uint32_t *)0x40022004)) +#define I2C2_MDR_R (*((volatile uint32_t *)0x40022008)) +#define I2C2_MTPR_R (*((volatile uint32_t *)0x4002200C)) +#define I2C2_MIMR_R (*((volatile uint32_t *)0x40022010)) +#define I2C2_MRIS_R (*((volatile uint32_t *)0x40022014)) +#define I2C2_MMIS_R (*((volatile uint32_t *)0x40022018)) +#define I2C2_MICR_R (*((volatile uint32_t *)0x4002201C)) +#define I2C2_MCR_R (*((volatile uint32_t *)0x40022020)) +#define I2C2_MCLKOCNT_R (*((volatile uint32_t *)0x40022024)) +#define I2C2_MBMON_R (*((volatile uint32_t *)0x4002202C)) +#define I2C2_MCR2_R (*((volatile uint32_t *)0x40022038)) +#define I2C2_SOAR_R (*((volatile uint32_t *)0x40022800)) +#define I2C2_SCSR_R (*((volatile uint32_t *)0x40022804)) +#define I2C2_SDR_R (*((volatile uint32_t *)0x40022808)) +#define I2C2_SIMR_R (*((volatile uint32_t *)0x4002280C)) +#define I2C2_SRIS_R (*((volatile uint32_t *)0x40022810)) +#define I2C2_SMIS_R (*((volatile uint32_t *)0x40022814)) +#define I2C2_SICR_R (*((volatile uint32_t *)0x40022818)) +#define I2C2_SOAR2_R (*((volatile uint32_t *)0x4002281C)) +#define I2C2_SACKCTL_R (*((volatile uint32_t *)0x40022820)) +#define I2C2_PP_R (*((volatile uint32_t *)0x40022FC0)) +#define I2C2_PC_R (*((volatile uint32_t *)0x40022FC4)) + +//***************************************************************************** +// +// I2C registers (I2C3) +// +//***************************************************************************** +#define I2C3_MSA_R (*((volatile uint32_t *)0x40023000)) +#define I2C3_MCS_R (*((volatile uint32_t *)0x40023004)) +#define I2C3_MDR_R (*((volatile uint32_t *)0x40023008)) +#define I2C3_MTPR_R (*((volatile uint32_t *)0x4002300C)) +#define I2C3_MIMR_R (*((volatile uint32_t *)0x40023010)) +#define I2C3_MRIS_R (*((volatile uint32_t *)0x40023014)) +#define I2C3_MMIS_R (*((volatile uint32_t *)0x40023018)) +#define I2C3_MICR_R (*((volatile uint32_t *)0x4002301C)) +#define I2C3_MCR_R (*((volatile uint32_t *)0x40023020)) +#define I2C3_MCLKOCNT_R (*((volatile uint32_t *)0x40023024)) +#define I2C3_MBMON_R (*((volatile uint32_t *)0x4002302C)) +#define I2C3_MCR2_R (*((volatile uint32_t *)0x40023038)) +#define I2C3_SOAR_R (*((volatile uint32_t *)0x40023800)) +#define I2C3_SCSR_R (*((volatile uint32_t *)0x40023804)) +#define I2C3_SDR_R (*((volatile uint32_t *)0x40023808)) +#define I2C3_SIMR_R (*((volatile uint32_t *)0x4002380C)) +#define I2C3_SRIS_R (*((volatile uint32_t *)0x40023810)) +#define I2C3_SMIS_R (*((volatile uint32_t *)0x40023814)) +#define I2C3_SICR_R (*((volatile uint32_t *)0x40023818)) +#define I2C3_SOAR2_R (*((volatile uint32_t *)0x4002381C)) +#define I2C3_SACKCTL_R (*((volatile uint32_t *)0x40023820)) +#define I2C3_PP_R (*((volatile uint32_t *)0x40023FC0)) +#define I2C3_PC_R (*((volatile uint32_t *)0x40023FC4)) + +//***************************************************************************** +// +// GPIO registers (PORTE) +// +//***************************************************************************** +#define GPIO_PORTE_DATA_BITS_R ((volatile uint32_t *)0x40024000) +#define GPIO_PORTE_DATA_R (*((volatile uint32_t *)0x400243FC)) +#define GPIO_PORTE_DIR_R (*((volatile uint32_t *)0x40024400)) +#define GPIO_PORTE_IS_R (*((volatile uint32_t *)0x40024404)) +#define GPIO_PORTE_IBE_R (*((volatile uint32_t *)0x40024408)) +#define GPIO_PORTE_IEV_R (*((volatile uint32_t *)0x4002440C)) +#define GPIO_PORTE_IM_R (*((volatile uint32_t *)0x40024410)) +#define GPIO_PORTE_RIS_R (*((volatile uint32_t *)0x40024414)) +#define GPIO_PORTE_MIS_R (*((volatile uint32_t *)0x40024418)) +#define GPIO_PORTE_ICR_R (*((volatile uint32_t *)0x4002441C)) +#define GPIO_PORTE_AFSEL_R (*((volatile uint32_t *)0x40024420)) +#define GPIO_PORTE_DR2R_R (*((volatile uint32_t *)0x40024500)) +#define GPIO_PORTE_DR4R_R (*((volatile uint32_t *)0x40024504)) +#define GPIO_PORTE_DR8R_R (*((volatile uint32_t *)0x40024508)) +#define GPIO_PORTE_ODR_R (*((volatile uint32_t *)0x4002450C)) +#define GPIO_PORTE_PUR_R (*((volatile uint32_t *)0x40024510)) +#define GPIO_PORTE_PDR_R (*((volatile uint32_t *)0x40024514)) +#define GPIO_PORTE_SLR_R (*((volatile uint32_t *)0x40024518)) +#define GPIO_PORTE_DEN_R (*((volatile uint32_t *)0x4002451C)) +#define GPIO_PORTE_LOCK_R (*((volatile uint32_t *)0x40024520)) +#define GPIO_PORTE_CR_R (*((volatile uint32_t *)0x40024524)) +#define GPIO_PORTE_AMSEL_R (*((volatile uint32_t *)0x40024528)) +#define GPIO_PORTE_PCTL_R (*((volatile uint32_t *)0x4002452C)) +#define GPIO_PORTE_ADCCTL_R (*((volatile uint32_t *)0x40024530)) +#define GPIO_PORTE_DMACTL_R (*((volatile uint32_t *)0x40024534)) + +//***************************************************************************** +// +// GPIO registers (PORTF) +// +//***************************************************************************** +#define GPIO_PORTF_DATA_BITS_R ((volatile uint32_t *)0x40025000) +#define GPIO_PORTF_DATA_R (*((volatile uint32_t *)0x400253FC)) +#define GPIO_PORTF_DIR_R (*((volatile uint32_t *)0x40025400)) +#define GPIO_PORTF_IS_R (*((volatile uint32_t *)0x40025404)) +#define GPIO_PORTF_IBE_R (*((volatile uint32_t *)0x40025408)) +#define GPIO_PORTF_IEV_R (*((volatile uint32_t *)0x4002540C)) +#define GPIO_PORTF_IM_R (*((volatile uint32_t *)0x40025410)) +#define GPIO_PORTF_RIS_R (*((volatile uint32_t *)0x40025414)) +#define GPIO_PORTF_MIS_R (*((volatile uint32_t *)0x40025418)) +#define GPIO_PORTF_ICR_R (*((volatile uint32_t *)0x4002541C)) +#define GPIO_PORTF_AFSEL_R (*((volatile uint32_t *)0x40025420)) +#define GPIO_PORTF_DR2R_R (*((volatile uint32_t *)0x40025500)) +#define GPIO_PORTF_DR4R_R (*((volatile uint32_t *)0x40025504)) +#define GPIO_PORTF_DR8R_R (*((volatile uint32_t *)0x40025508)) +#define GPIO_PORTF_ODR_R (*((volatile uint32_t *)0x4002550C)) +#define GPIO_PORTF_PUR_R (*((volatile uint32_t *)0x40025510)) +#define GPIO_PORTF_PDR_R (*((volatile uint32_t *)0x40025514)) +#define GPIO_PORTF_SLR_R (*((volatile uint32_t *)0x40025518)) +#define GPIO_PORTF_DEN_R (*((volatile uint32_t *)0x4002551C)) +#define GPIO_PORTF_LOCK_R (*((volatile uint32_t *)0x40025520)) +#define GPIO_PORTF_CR_R (*((volatile uint32_t *)0x40025524)) +#define GPIO_PORTF_AMSEL_R (*((volatile uint32_t *)0x40025528)) +#define GPIO_PORTF_PCTL_R (*((volatile uint32_t *)0x4002552C)) +#define GPIO_PORTF_ADCCTL_R (*((volatile uint32_t *)0x40025530)) +#define GPIO_PORTF_DMACTL_R (*((volatile uint32_t *)0x40025534)) + +//***************************************************************************** +// +// PWM registers (PWM0) +// +//***************************************************************************** +#define PWM0_CTL_R (*((volatile uint32_t *)0x40028000)) +#define PWM0_SYNC_R (*((volatile uint32_t *)0x40028004)) +#define PWM0_ENABLE_R (*((volatile uint32_t *)0x40028008)) +#define PWM0_INVERT_R (*((volatile uint32_t *)0x4002800C)) +#define PWM0_FAULT_R (*((volatile uint32_t *)0x40028010)) +#define PWM0_INTEN_R (*((volatile uint32_t *)0x40028014)) +#define PWM0_RIS_R (*((volatile uint32_t *)0x40028018)) +#define PWM0_ISC_R (*((volatile uint32_t *)0x4002801C)) +#define PWM0_STATUS_R (*((volatile uint32_t *)0x40028020)) +#define PWM0_FAULTVAL_R (*((volatile uint32_t *)0x40028024)) +#define PWM0_ENUPD_R (*((volatile uint32_t *)0x40028028)) +#define PWM0_0_CTL_R (*((volatile uint32_t *)0x40028040)) +#define PWM0_0_INTEN_R (*((volatile uint32_t *)0x40028044)) +#define PWM0_0_RIS_R (*((volatile uint32_t *)0x40028048)) +#define PWM0_0_ISC_R (*((volatile uint32_t *)0x4002804C)) +#define PWM0_0_LOAD_R (*((volatile uint32_t *)0x40028050)) +#define PWM0_0_COUNT_R (*((volatile uint32_t *)0x40028054)) +#define PWM0_0_CMPA_R (*((volatile uint32_t *)0x40028058)) +#define PWM0_0_CMPB_R (*((volatile uint32_t *)0x4002805C)) +#define PWM0_0_GENA_R (*((volatile uint32_t *)0x40028060)) +#define PWM0_0_GENB_R (*((volatile uint32_t *)0x40028064)) +#define PWM0_0_DBCTL_R (*((volatile uint32_t *)0x40028068)) +#define PWM0_0_DBRISE_R (*((volatile uint32_t *)0x4002806C)) +#define PWM0_0_DBFALL_R (*((volatile uint32_t *)0x40028070)) +#define PWM0_0_FLTSRC0_R (*((volatile uint32_t *)0x40028074)) +#define PWM0_0_FLTSRC1_R (*((volatile uint32_t *)0x40028078)) +#define PWM0_0_MINFLTPER_R (*((volatile uint32_t *)0x4002807C)) +#define PWM0_1_CTL_R (*((volatile uint32_t *)0x40028080)) +#define PWM0_1_INTEN_R (*((volatile uint32_t *)0x40028084)) +#define PWM0_1_RIS_R (*((volatile uint32_t *)0x40028088)) +#define PWM0_1_ISC_R (*((volatile uint32_t *)0x4002808C)) +#define PWM0_1_LOAD_R (*((volatile uint32_t *)0x40028090)) +#define PWM0_1_COUNT_R (*((volatile uint32_t *)0x40028094)) +#define PWM0_1_CMPA_R (*((volatile uint32_t *)0x40028098)) +#define PWM0_1_CMPB_R (*((volatile uint32_t *)0x4002809C)) +#define PWM0_1_GENA_R (*((volatile uint32_t *)0x400280A0)) +#define PWM0_1_GENB_R (*((volatile uint32_t *)0x400280A4)) +#define PWM0_1_DBCTL_R (*((volatile uint32_t *)0x400280A8)) +#define PWM0_1_DBRISE_R (*((volatile uint32_t *)0x400280AC)) +#define PWM0_1_DBFALL_R (*((volatile uint32_t *)0x400280B0)) +#define PWM0_1_FLTSRC0_R (*((volatile uint32_t *)0x400280B4)) +#define PWM0_1_FLTSRC1_R (*((volatile uint32_t *)0x400280B8)) +#define PWM0_1_MINFLTPER_R (*((volatile uint32_t *)0x400280BC)) +#define PWM0_2_CTL_R (*((volatile uint32_t *)0x400280C0)) +#define PWM0_2_INTEN_R (*((volatile uint32_t *)0x400280C4)) +#define PWM0_2_RIS_R (*((volatile uint32_t *)0x400280C8)) +#define PWM0_2_ISC_R (*((volatile uint32_t *)0x400280CC)) +#define PWM0_2_LOAD_R (*((volatile uint32_t *)0x400280D0)) +#define PWM0_2_COUNT_R (*((volatile uint32_t *)0x400280D4)) +#define PWM0_2_CMPA_R (*((volatile uint32_t *)0x400280D8)) +#define PWM0_2_CMPB_R (*((volatile uint32_t *)0x400280DC)) +#define PWM0_2_GENA_R (*((volatile uint32_t *)0x400280E0)) +#define PWM0_2_GENB_R (*((volatile uint32_t *)0x400280E4)) +#define PWM0_2_DBCTL_R (*((volatile uint32_t *)0x400280E8)) +#define PWM0_2_DBRISE_R (*((volatile uint32_t *)0x400280EC)) +#define PWM0_2_DBFALL_R (*((volatile uint32_t *)0x400280F0)) +#define PWM0_2_FLTSRC0_R (*((volatile uint32_t *)0x400280F4)) +#define PWM0_2_FLTSRC1_R (*((volatile uint32_t *)0x400280F8)) +#define PWM0_2_MINFLTPER_R (*((volatile uint32_t *)0x400280FC)) +#define PWM0_3_CTL_R (*((volatile uint32_t *)0x40028100)) +#define PWM0_3_INTEN_R (*((volatile uint32_t *)0x40028104)) +#define PWM0_3_RIS_R (*((volatile uint32_t *)0x40028108)) +#define PWM0_3_ISC_R (*((volatile uint32_t *)0x4002810C)) +#define PWM0_3_LOAD_R (*((volatile uint32_t *)0x40028110)) +#define PWM0_3_COUNT_R (*((volatile uint32_t *)0x40028114)) +#define PWM0_3_CMPA_R (*((volatile uint32_t *)0x40028118)) +#define PWM0_3_CMPB_R (*((volatile uint32_t *)0x4002811C)) +#define PWM0_3_GENA_R (*((volatile uint32_t *)0x40028120)) +#define PWM0_3_GENB_R (*((volatile uint32_t *)0x40028124)) +#define PWM0_3_DBCTL_R (*((volatile uint32_t *)0x40028128)) +#define PWM0_3_DBRISE_R (*((volatile uint32_t *)0x4002812C)) +#define PWM0_3_DBFALL_R (*((volatile uint32_t *)0x40028130)) +#define PWM0_3_FLTSRC0_R (*((volatile uint32_t *)0x40028134)) +#define PWM0_3_FLTSRC1_R (*((volatile uint32_t *)0x40028138)) +#define PWM0_3_MINFLTPER_R (*((volatile uint32_t *)0x4002813C)) +#define PWM0_0_FLTSEN_R (*((volatile uint32_t *)0x40028800)) +#define PWM0_0_FLTSTAT0_R (*((volatile uint32_t *)0x40028804)) +#define PWM0_0_FLTSTAT1_R (*((volatile uint32_t *)0x40028808)) +#define PWM0_1_FLTSEN_R (*((volatile uint32_t *)0x40028880)) +#define PWM0_1_FLTSTAT0_R (*((volatile uint32_t *)0x40028884)) +#define PWM0_1_FLTSTAT1_R (*((volatile uint32_t *)0x40028888)) +#define PWM0_2_FLTSTAT0_R (*((volatile uint32_t *)0x40028904)) +#define PWM0_2_FLTSTAT1_R (*((volatile uint32_t *)0x40028908)) +#define PWM0_3_FLTSTAT0_R (*((volatile uint32_t *)0x40028984)) +#define PWM0_3_FLTSTAT1_R (*((volatile uint32_t *)0x40028988)) +#define PWM0_PP_R (*((volatile uint32_t *)0x40028FC0)) + +//***************************************************************************** +// +// PWM registers (PWM1) +// +//***************************************************************************** +#define PWM1_CTL_R (*((volatile uint32_t *)0x40029000)) +#define PWM1_SYNC_R (*((volatile uint32_t *)0x40029004)) +#define PWM1_ENABLE_R (*((volatile uint32_t *)0x40029008)) +#define PWM1_INVERT_R (*((volatile uint32_t *)0x4002900C)) +#define PWM1_FAULT_R (*((volatile uint32_t *)0x40029010)) +#define PWM1_INTEN_R (*((volatile uint32_t *)0x40029014)) +#define PWM1_RIS_R (*((volatile uint32_t *)0x40029018)) +#define PWM1_ISC_R (*((volatile uint32_t *)0x4002901C)) +#define PWM1_STATUS_R (*((volatile uint32_t *)0x40029020)) +#define PWM1_FAULTVAL_R (*((volatile uint32_t *)0x40029024)) +#define PWM1_ENUPD_R (*((volatile uint32_t *)0x40029028)) +#define PWM1_0_CTL_R (*((volatile uint32_t *)0x40029040)) +#define PWM1_0_INTEN_R (*((volatile uint32_t *)0x40029044)) +#define PWM1_0_RIS_R (*((volatile uint32_t *)0x40029048)) +#define PWM1_0_ISC_R (*((volatile uint32_t *)0x4002904C)) +#define PWM1_0_LOAD_R (*((volatile uint32_t *)0x40029050)) +#define PWM1_0_COUNT_R (*((volatile uint32_t *)0x40029054)) +#define PWM1_0_CMPA_R (*((volatile uint32_t *)0x40029058)) +#define PWM1_0_CMPB_R (*((volatile uint32_t *)0x4002905C)) +#define PWM1_0_GENA_R (*((volatile uint32_t *)0x40029060)) +#define PWM1_0_GENB_R (*((volatile uint32_t *)0x40029064)) +#define PWM1_0_DBCTL_R (*((volatile uint32_t *)0x40029068)) +#define PWM1_0_DBRISE_R (*((volatile uint32_t *)0x4002906C)) +#define PWM1_0_DBFALL_R (*((volatile uint32_t *)0x40029070)) +#define PWM1_0_FLTSRC0_R (*((volatile uint32_t *)0x40029074)) +#define PWM1_0_FLTSRC1_R (*((volatile uint32_t *)0x40029078)) +#define PWM1_0_MINFLTPER_R (*((volatile uint32_t *)0x4002907C)) +#define PWM1_1_CTL_R (*((volatile uint32_t *)0x40029080)) +#define PWM1_1_INTEN_R (*((volatile uint32_t *)0x40029084)) +#define PWM1_1_RIS_R (*((volatile uint32_t *)0x40029088)) +#define PWM1_1_ISC_R (*((volatile uint32_t *)0x4002908C)) +#define PWM1_1_LOAD_R (*((volatile uint32_t *)0x40029090)) +#define PWM1_1_COUNT_R (*((volatile uint32_t *)0x40029094)) +#define PWM1_1_CMPA_R (*((volatile uint32_t *)0x40029098)) +#define PWM1_1_CMPB_R (*((volatile uint32_t *)0x4002909C)) +#define PWM1_1_GENA_R (*((volatile uint32_t *)0x400290A0)) +#define PWM1_1_GENB_R (*((volatile uint32_t *)0x400290A4)) +#define PWM1_1_DBCTL_R (*((volatile uint32_t *)0x400290A8)) +#define PWM1_1_DBRISE_R (*((volatile uint32_t *)0x400290AC)) +#define PWM1_1_DBFALL_R (*((volatile uint32_t *)0x400290B0)) +#define PWM1_1_FLTSRC0_R (*((volatile uint32_t *)0x400290B4)) +#define PWM1_1_FLTSRC1_R (*((volatile uint32_t *)0x400290B8)) +#define PWM1_1_MINFLTPER_R (*((volatile uint32_t *)0x400290BC)) +#define PWM1_2_CTL_R (*((volatile uint32_t *)0x400290C0)) +#define PWM1_2_INTEN_R (*((volatile uint32_t *)0x400290C4)) +#define PWM1_2_RIS_R (*((volatile uint32_t *)0x400290C8)) +#define PWM1_2_ISC_R (*((volatile uint32_t *)0x400290CC)) +#define PWM1_2_LOAD_R (*((volatile uint32_t *)0x400290D0)) +#define PWM1_2_COUNT_R (*((volatile uint32_t *)0x400290D4)) +#define PWM1_2_CMPA_R (*((volatile uint32_t *)0x400290D8)) +#define PWM1_2_CMPB_R (*((volatile uint32_t *)0x400290DC)) +#define PWM1_2_GENA_R (*((volatile uint32_t *)0x400290E0)) +#define PWM1_2_GENB_R (*((volatile uint32_t *)0x400290E4)) +#define PWM1_2_DBCTL_R (*((volatile uint32_t *)0x400290E8)) +#define PWM1_2_DBRISE_R (*((volatile uint32_t *)0x400290EC)) +#define PWM1_2_DBFALL_R (*((volatile uint32_t *)0x400290F0)) +#define PWM1_2_FLTSRC0_R (*((volatile uint32_t *)0x400290F4)) +#define PWM1_2_FLTSRC1_R (*((volatile uint32_t *)0x400290F8)) +#define PWM1_2_MINFLTPER_R (*((volatile uint32_t *)0x400290FC)) +#define PWM1_3_CTL_R (*((volatile uint32_t *)0x40029100)) +#define PWM1_3_INTEN_R (*((volatile uint32_t *)0x40029104)) +#define PWM1_3_RIS_R (*((volatile uint32_t *)0x40029108)) +#define PWM1_3_ISC_R (*((volatile uint32_t *)0x4002910C)) +#define PWM1_3_LOAD_R (*((volatile uint32_t *)0x40029110)) +#define PWM1_3_COUNT_R (*((volatile uint32_t *)0x40029114)) +#define PWM1_3_CMPA_R (*((volatile uint32_t *)0x40029118)) +#define PWM1_3_CMPB_R (*((volatile uint32_t *)0x4002911C)) +#define PWM1_3_GENA_R (*((volatile uint32_t *)0x40029120)) +#define PWM1_3_GENB_R (*((volatile uint32_t *)0x40029124)) +#define PWM1_3_DBCTL_R (*((volatile uint32_t *)0x40029128)) +#define PWM1_3_DBRISE_R (*((volatile uint32_t *)0x4002912C)) +#define PWM1_3_DBFALL_R (*((volatile uint32_t *)0x40029130)) +#define PWM1_3_FLTSRC0_R (*((volatile uint32_t *)0x40029134)) +#define PWM1_3_FLTSRC1_R (*((volatile uint32_t *)0x40029138)) +#define PWM1_3_MINFLTPER_R (*((volatile uint32_t *)0x4002913C)) +#define PWM1_0_FLTSEN_R (*((volatile uint32_t *)0x40029800)) +#define PWM1_0_FLTSTAT0_R (*((volatile uint32_t *)0x40029804)) +#define PWM1_0_FLTSTAT1_R (*((volatile uint32_t *)0x40029808)) +#define PWM1_1_FLTSEN_R (*((volatile uint32_t *)0x40029880)) +#define PWM1_1_FLTSTAT0_R (*((volatile uint32_t *)0x40029884)) +#define PWM1_1_FLTSTAT1_R (*((volatile uint32_t *)0x40029888)) +#define PWM1_2_FLTSTAT0_R (*((volatile uint32_t *)0x40029904)) +#define PWM1_2_FLTSTAT1_R (*((volatile uint32_t *)0x40029908)) +#define PWM1_3_FLTSTAT0_R (*((volatile uint32_t *)0x40029984)) +#define PWM1_3_FLTSTAT1_R (*((volatile uint32_t *)0x40029988)) +#define PWM1_PP_R (*((volatile uint32_t *)0x40029FC0)) + +//***************************************************************************** +// +// QEI registers (QEI0) +// +//***************************************************************************** +#define QEI0_CTL_R (*((volatile uint32_t *)0x4002C000)) +#define QEI0_STAT_R (*((volatile uint32_t *)0x4002C004)) +#define QEI0_POS_R (*((volatile uint32_t *)0x4002C008)) +#define QEI0_MAXPOS_R (*((volatile uint32_t *)0x4002C00C)) +#define QEI0_LOAD_R (*((volatile uint32_t *)0x4002C010)) +#define QEI0_TIME_R (*((volatile uint32_t *)0x4002C014)) +#define QEI0_COUNT_R (*((volatile uint32_t *)0x4002C018)) +#define QEI0_SPEED_R (*((volatile uint32_t *)0x4002C01C)) +#define QEI0_INTEN_R (*((volatile uint32_t *)0x4002C020)) +#define QEI0_RIS_R (*((volatile uint32_t *)0x4002C024)) +#define QEI0_ISC_R (*((volatile uint32_t *)0x4002C028)) + +//***************************************************************************** +// +// QEI registers (QEI1) +// +//***************************************************************************** +#define QEI1_CTL_R (*((volatile uint32_t *)0x4002D000)) +#define QEI1_STAT_R (*((volatile uint32_t *)0x4002D004)) +#define QEI1_POS_R (*((volatile uint32_t *)0x4002D008)) +#define QEI1_MAXPOS_R (*((volatile uint32_t *)0x4002D00C)) +#define QEI1_LOAD_R (*((volatile uint32_t *)0x4002D010)) +#define QEI1_TIME_R (*((volatile uint32_t *)0x4002D014)) +#define QEI1_COUNT_R (*((volatile uint32_t *)0x4002D018)) +#define QEI1_SPEED_R (*((volatile uint32_t *)0x4002D01C)) +#define QEI1_INTEN_R (*((volatile uint32_t *)0x4002D020)) +#define QEI1_RIS_R (*((volatile uint32_t *)0x4002D024)) +#define QEI1_ISC_R (*((volatile uint32_t *)0x4002D028)) + +//***************************************************************************** +// +// Timer registers (TIMER0) +// +//***************************************************************************** +#define TIMER0_CFG_R (*((volatile uint32_t *)0x40030000)) +#define TIMER0_TAMR_R (*((volatile uint32_t *)0x40030004)) +#define TIMER0_TBMR_R (*((volatile uint32_t *)0x40030008)) +#define TIMER0_CTL_R (*((volatile uint32_t *)0x4003000C)) +#define TIMER0_SYNC_R (*((volatile uint32_t *)0x40030010)) +#define TIMER0_IMR_R (*((volatile uint32_t *)0x40030018)) +#define TIMER0_RIS_R (*((volatile uint32_t *)0x4003001C)) +#define TIMER0_MIS_R (*((volatile uint32_t *)0x40030020)) +#define TIMER0_ICR_R (*((volatile uint32_t *)0x40030024)) +#define TIMER0_TAILR_R (*((volatile uint32_t *)0x40030028)) +#define TIMER0_TBILR_R (*((volatile uint32_t *)0x4003002C)) +#define TIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40030030)) +#define TIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40030034)) +#define TIMER0_TAPR_R (*((volatile uint32_t *)0x40030038)) +#define TIMER0_TBPR_R (*((volatile uint32_t *)0x4003003C)) +#define TIMER0_TAPMR_R (*((volatile uint32_t *)0x40030040)) +#define TIMER0_TBPMR_R (*((volatile uint32_t *)0x40030044)) +#define TIMER0_TAR_R (*((volatile uint32_t *)0x40030048)) +#define TIMER0_TBR_R (*((volatile uint32_t *)0x4003004C)) +#define TIMER0_TAV_R (*((volatile uint32_t *)0x40030050)) +#define TIMER0_TBV_R (*((volatile uint32_t *)0x40030054)) +#define TIMER0_RTCPD_R (*((volatile uint32_t *)0x40030058)) +#define TIMER0_TAPS_R (*((volatile uint32_t *)0x4003005C)) +#define TIMER0_TBPS_R (*((volatile uint32_t *)0x40030060)) +#define TIMER0_TAPV_R (*((volatile uint32_t *)0x40030064)) +#define TIMER0_TBPV_R (*((volatile uint32_t *)0x40030068)) +#define TIMER0_PP_R (*((volatile uint32_t *)0x40030FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER1) +// +//***************************************************************************** +#define TIMER1_CFG_R (*((volatile uint32_t *)0x40031000)) +#define TIMER1_TAMR_R (*((volatile uint32_t *)0x40031004)) +#define TIMER1_TBMR_R (*((volatile uint32_t *)0x40031008)) +#define TIMER1_CTL_R (*((volatile uint32_t *)0x4003100C)) +#define TIMER1_SYNC_R (*((volatile uint32_t *)0x40031010)) +#define TIMER1_IMR_R (*((volatile uint32_t *)0x40031018)) +#define TIMER1_RIS_R (*((volatile uint32_t *)0x4003101C)) +#define TIMER1_MIS_R (*((volatile uint32_t *)0x40031020)) +#define TIMER1_ICR_R (*((volatile uint32_t *)0x40031024)) +#define TIMER1_TAILR_R (*((volatile uint32_t *)0x40031028)) +#define TIMER1_TBILR_R (*((volatile uint32_t *)0x4003102C)) +#define TIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40031030)) +#define TIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40031034)) +#define TIMER1_TAPR_R (*((volatile uint32_t *)0x40031038)) +#define TIMER1_TBPR_R (*((volatile uint32_t *)0x4003103C)) +#define TIMER1_TAPMR_R (*((volatile uint32_t *)0x40031040)) +#define TIMER1_TBPMR_R (*((volatile uint32_t *)0x40031044)) +#define TIMER1_TAR_R (*((volatile uint32_t *)0x40031048)) +#define TIMER1_TBR_R (*((volatile uint32_t *)0x4003104C)) +#define TIMER1_TAV_R (*((volatile uint32_t *)0x40031050)) +#define TIMER1_TBV_R (*((volatile uint32_t *)0x40031054)) +#define TIMER1_RTCPD_R (*((volatile uint32_t *)0x40031058)) +#define TIMER1_TAPS_R (*((volatile uint32_t *)0x4003105C)) +#define TIMER1_TBPS_R (*((volatile uint32_t *)0x40031060)) +#define TIMER1_TAPV_R (*((volatile uint32_t *)0x40031064)) +#define TIMER1_TBPV_R (*((volatile uint32_t *)0x40031068)) +#define TIMER1_PP_R (*((volatile uint32_t *)0x40031FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER2) +// +//***************************************************************************** +#define TIMER2_CFG_R (*((volatile uint32_t *)0x40032000)) +#define TIMER2_TAMR_R (*((volatile uint32_t *)0x40032004)) +#define TIMER2_TBMR_R (*((volatile uint32_t *)0x40032008)) +#define TIMER2_CTL_R (*((volatile uint32_t *)0x4003200C)) +#define TIMER2_SYNC_R (*((volatile uint32_t *)0x40032010)) +#define TIMER2_IMR_R (*((volatile uint32_t *)0x40032018)) +#define TIMER2_RIS_R (*((volatile uint32_t *)0x4003201C)) +#define TIMER2_MIS_R (*((volatile uint32_t *)0x40032020)) +#define TIMER2_ICR_R (*((volatile uint32_t *)0x40032024)) +#define TIMER2_TAILR_R (*((volatile uint32_t *)0x40032028)) +#define TIMER2_TBILR_R (*((volatile uint32_t *)0x4003202C)) +#define TIMER2_TAMATCHR_R (*((volatile uint32_t *)0x40032030)) +#define TIMER2_TBMATCHR_R (*((volatile uint32_t *)0x40032034)) +#define TIMER2_TAPR_R (*((volatile uint32_t *)0x40032038)) +#define TIMER2_TBPR_R (*((volatile uint32_t *)0x4003203C)) +#define TIMER2_TAPMR_R (*((volatile uint32_t *)0x40032040)) +#define TIMER2_TBPMR_R (*((volatile uint32_t *)0x40032044)) +#define TIMER2_TAR_R (*((volatile uint32_t *)0x40032048)) +#define TIMER2_TBR_R (*((volatile uint32_t *)0x4003204C)) +#define TIMER2_TAV_R (*((volatile uint32_t *)0x40032050)) +#define TIMER2_TBV_R (*((volatile uint32_t *)0x40032054)) +#define TIMER2_RTCPD_R (*((volatile uint32_t *)0x40032058)) +#define TIMER2_TAPS_R (*((volatile uint32_t *)0x4003205C)) +#define TIMER2_TBPS_R (*((volatile uint32_t *)0x40032060)) +#define TIMER2_TAPV_R (*((volatile uint32_t *)0x40032064)) +#define TIMER2_TBPV_R (*((volatile uint32_t *)0x40032068)) +#define TIMER2_PP_R (*((volatile uint32_t *)0x40032FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER3) +// +//***************************************************************************** +#define TIMER3_CFG_R (*((volatile uint32_t *)0x40033000)) +#define TIMER3_TAMR_R (*((volatile uint32_t *)0x40033004)) +#define TIMER3_TBMR_R (*((volatile uint32_t *)0x40033008)) +#define TIMER3_CTL_R (*((volatile uint32_t *)0x4003300C)) +#define TIMER3_SYNC_R (*((volatile uint32_t *)0x40033010)) +#define TIMER3_IMR_R (*((volatile uint32_t *)0x40033018)) +#define TIMER3_RIS_R (*((volatile uint32_t *)0x4003301C)) +#define TIMER3_MIS_R (*((volatile uint32_t *)0x40033020)) +#define TIMER3_ICR_R (*((volatile uint32_t *)0x40033024)) +#define TIMER3_TAILR_R (*((volatile uint32_t *)0x40033028)) +#define TIMER3_TBILR_R (*((volatile uint32_t *)0x4003302C)) +#define TIMER3_TAMATCHR_R (*((volatile uint32_t *)0x40033030)) +#define TIMER3_TBMATCHR_R (*((volatile uint32_t *)0x40033034)) +#define TIMER3_TAPR_R (*((volatile uint32_t *)0x40033038)) +#define TIMER3_TBPR_R (*((volatile uint32_t *)0x4003303C)) +#define TIMER3_TAPMR_R (*((volatile uint32_t *)0x40033040)) +#define TIMER3_TBPMR_R (*((volatile uint32_t *)0x40033044)) +#define TIMER3_TAR_R (*((volatile uint32_t *)0x40033048)) +#define TIMER3_TBR_R (*((volatile uint32_t *)0x4003304C)) +#define TIMER3_TAV_R (*((volatile uint32_t *)0x40033050)) +#define TIMER3_TBV_R (*((volatile uint32_t *)0x40033054)) +#define TIMER3_RTCPD_R (*((volatile uint32_t *)0x40033058)) +#define TIMER3_TAPS_R (*((volatile uint32_t *)0x4003305C)) +#define TIMER3_TBPS_R (*((volatile uint32_t *)0x40033060)) +#define TIMER3_TAPV_R (*((volatile uint32_t *)0x40033064)) +#define TIMER3_TBPV_R (*((volatile uint32_t *)0x40033068)) +#define TIMER3_PP_R (*((volatile uint32_t *)0x40033FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER4) +// +//***************************************************************************** +#define TIMER4_CFG_R (*((volatile uint32_t *)0x40034000)) +#define TIMER4_TAMR_R (*((volatile uint32_t *)0x40034004)) +#define TIMER4_TBMR_R (*((volatile uint32_t *)0x40034008)) +#define TIMER4_CTL_R (*((volatile uint32_t *)0x4003400C)) +#define TIMER4_SYNC_R (*((volatile uint32_t *)0x40034010)) +#define TIMER4_IMR_R (*((volatile uint32_t *)0x40034018)) +#define TIMER4_RIS_R (*((volatile uint32_t *)0x4003401C)) +#define TIMER4_MIS_R (*((volatile uint32_t *)0x40034020)) +#define TIMER4_ICR_R (*((volatile uint32_t *)0x40034024)) +#define TIMER4_TAILR_R (*((volatile uint32_t *)0x40034028)) +#define TIMER4_TBILR_R (*((volatile uint32_t *)0x4003402C)) +#define TIMER4_TAMATCHR_R (*((volatile uint32_t *)0x40034030)) +#define TIMER4_TBMATCHR_R (*((volatile uint32_t *)0x40034034)) +#define TIMER4_TAPR_R (*((volatile uint32_t *)0x40034038)) +#define TIMER4_TBPR_R (*((volatile uint32_t *)0x4003403C)) +#define TIMER4_TAPMR_R (*((volatile uint32_t *)0x40034040)) +#define TIMER4_TBPMR_R (*((volatile uint32_t *)0x40034044)) +#define TIMER4_TAR_R (*((volatile uint32_t *)0x40034048)) +#define TIMER4_TBR_R (*((volatile uint32_t *)0x4003404C)) +#define TIMER4_TAV_R (*((volatile uint32_t *)0x40034050)) +#define TIMER4_TBV_R (*((volatile uint32_t *)0x40034054)) +#define TIMER4_RTCPD_R (*((volatile uint32_t *)0x40034058)) +#define TIMER4_TAPS_R (*((volatile uint32_t *)0x4003405C)) +#define TIMER4_TBPS_R (*((volatile uint32_t *)0x40034060)) +#define TIMER4_TAPV_R (*((volatile uint32_t *)0x40034064)) +#define TIMER4_TBPV_R (*((volatile uint32_t *)0x40034068)) +#define TIMER4_PP_R (*((volatile uint32_t *)0x40034FC0)) + +//***************************************************************************** +// +// Timer registers (TIMER5) +// +//***************************************************************************** +#define TIMER5_CFG_R (*((volatile uint32_t *)0x40035000)) +#define TIMER5_TAMR_R (*((volatile uint32_t *)0x40035004)) +#define TIMER5_TBMR_R (*((volatile uint32_t *)0x40035008)) +#define TIMER5_CTL_R (*((volatile uint32_t *)0x4003500C)) +#define TIMER5_SYNC_R (*((volatile uint32_t *)0x40035010)) +#define TIMER5_IMR_R (*((volatile uint32_t *)0x40035018)) +#define TIMER5_RIS_R (*((volatile uint32_t *)0x4003501C)) +#define TIMER5_MIS_R (*((volatile uint32_t *)0x40035020)) +#define TIMER5_ICR_R (*((volatile uint32_t *)0x40035024)) +#define TIMER5_TAILR_R (*((volatile uint32_t *)0x40035028)) +#define TIMER5_TBILR_R (*((volatile uint32_t *)0x4003502C)) +#define TIMER5_TAMATCHR_R (*((volatile uint32_t *)0x40035030)) +#define TIMER5_TBMATCHR_R (*((volatile uint32_t *)0x40035034)) +#define TIMER5_TAPR_R (*((volatile uint32_t *)0x40035038)) +#define TIMER5_TBPR_R (*((volatile uint32_t *)0x4003503C)) +#define TIMER5_TAPMR_R (*((volatile uint32_t *)0x40035040)) +#define TIMER5_TBPMR_R (*((volatile uint32_t *)0x40035044)) +#define TIMER5_TAR_R (*((volatile uint32_t *)0x40035048)) +#define TIMER5_TBR_R (*((volatile uint32_t *)0x4003504C)) +#define TIMER5_TAV_R (*((volatile uint32_t *)0x40035050)) +#define TIMER5_TBV_R (*((volatile uint32_t *)0x40035054)) +#define TIMER5_RTCPD_R (*((volatile uint32_t *)0x40035058)) +#define TIMER5_TAPS_R (*((volatile uint32_t *)0x4003505C)) +#define TIMER5_TBPS_R (*((volatile uint32_t *)0x40035060)) +#define TIMER5_TAPV_R (*((volatile uint32_t *)0x40035064)) +#define TIMER5_TBPV_R (*((volatile uint32_t *)0x40035068)) +#define TIMER5_PP_R (*((volatile uint32_t *)0x40035FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER0) +// +//***************************************************************************** +#define WTIMER0_CFG_R (*((volatile uint32_t *)0x40036000)) +#define WTIMER0_TAMR_R (*((volatile uint32_t *)0x40036004)) +#define WTIMER0_TBMR_R (*((volatile uint32_t *)0x40036008)) +#define WTIMER0_CTL_R (*((volatile uint32_t *)0x4003600C)) +#define WTIMER0_SYNC_R (*((volatile uint32_t *)0x40036010)) +#define WTIMER0_IMR_R (*((volatile uint32_t *)0x40036018)) +#define WTIMER0_RIS_R (*((volatile uint32_t *)0x4003601C)) +#define WTIMER0_MIS_R (*((volatile uint32_t *)0x40036020)) +#define WTIMER0_ICR_R (*((volatile uint32_t *)0x40036024)) +#define WTIMER0_TAILR_R (*((volatile uint32_t *)0x40036028)) +#define WTIMER0_TBILR_R (*((volatile uint32_t *)0x4003602C)) +#define WTIMER0_TAMATCHR_R (*((volatile uint32_t *)0x40036030)) +#define WTIMER0_TBMATCHR_R (*((volatile uint32_t *)0x40036034)) +#define WTIMER0_TAPR_R (*((volatile uint32_t *)0x40036038)) +#define WTIMER0_TBPR_R (*((volatile uint32_t *)0x4003603C)) +#define WTIMER0_TAPMR_R (*((volatile uint32_t *)0x40036040)) +#define WTIMER0_TBPMR_R (*((volatile uint32_t *)0x40036044)) +#define WTIMER0_TAR_R (*((volatile uint32_t *)0x40036048)) +#define WTIMER0_TBR_R (*((volatile uint32_t *)0x4003604C)) +#define WTIMER0_TAV_R (*((volatile uint32_t *)0x40036050)) +#define WTIMER0_TBV_R (*((volatile uint32_t *)0x40036054)) +#define WTIMER0_RTCPD_R (*((volatile uint32_t *)0x40036058)) +#define WTIMER0_TAPS_R (*((volatile uint32_t *)0x4003605C)) +#define WTIMER0_TBPS_R (*((volatile uint32_t *)0x40036060)) +#define WTIMER0_TAPV_R (*((volatile uint32_t *)0x40036064)) +#define WTIMER0_TBPV_R (*((volatile uint32_t *)0x40036068)) +#define WTIMER0_PP_R (*((volatile uint32_t *)0x40036FC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER1) +// +//***************************************************************************** +#define WTIMER1_CFG_R (*((volatile uint32_t *)0x40037000)) +#define WTIMER1_TAMR_R (*((volatile uint32_t *)0x40037004)) +#define WTIMER1_TBMR_R (*((volatile uint32_t *)0x40037008)) +#define WTIMER1_CTL_R (*((volatile uint32_t *)0x4003700C)) +#define WTIMER1_SYNC_R (*((volatile uint32_t *)0x40037010)) +#define WTIMER1_IMR_R (*((volatile uint32_t *)0x40037018)) +#define WTIMER1_RIS_R (*((volatile uint32_t *)0x4003701C)) +#define WTIMER1_MIS_R (*((volatile uint32_t *)0x40037020)) +#define WTIMER1_ICR_R (*((volatile uint32_t *)0x40037024)) +#define WTIMER1_TAILR_R (*((volatile uint32_t *)0x40037028)) +#define WTIMER1_TBILR_R (*((volatile uint32_t *)0x4003702C)) +#define WTIMER1_TAMATCHR_R (*((volatile uint32_t *)0x40037030)) +#define WTIMER1_TBMATCHR_R (*((volatile uint32_t *)0x40037034)) +#define WTIMER1_TAPR_R (*((volatile uint32_t *)0x40037038)) +#define WTIMER1_TBPR_R (*((volatile uint32_t *)0x4003703C)) +#define WTIMER1_TAPMR_R (*((volatile uint32_t *)0x40037040)) +#define WTIMER1_TBPMR_R (*((volatile uint32_t *)0x40037044)) +#define WTIMER1_TAR_R (*((volatile uint32_t *)0x40037048)) +#define WTIMER1_TBR_R (*((volatile uint32_t *)0x4003704C)) +#define WTIMER1_TAV_R (*((volatile uint32_t *)0x40037050)) +#define WTIMER1_TBV_R (*((volatile uint32_t *)0x40037054)) +#define WTIMER1_RTCPD_R (*((volatile uint32_t *)0x40037058)) +#define WTIMER1_TAPS_R (*((volatile uint32_t *)0x4003705C)) +#define WTIMER1_TBPS_R (*((volatile uint32_t *)0x40037060)) +#define WTIMER1_TAPV_R (*((volatile uint32_t *)0x40037064)) +#define WTIMER1_TBPV_R (*((volatile uint32_t *)0x40037068)) +#define WTIMER1_PP_R (*((volatile uint32_t *)0x40037FC0)) + +//***************************************************************************** +// +// ADC registers (ADC0) +// +//***************************************************************************** +#define ADC0_ACTSS_R (*((volatile uint32_t *)0x40038000)) +#define ADC0_RIS_R (*((volatile uint32_t *)0x40038004)) +#define ADC0_IM_R (*((volatile uint32_t *)0x40038008)) +#define ADC0_ISC_R (*((volatile uint32_t *)0x4003800C)) +#define ADC0_OSTAT_R (*((volatile uint32_t *)0x40038010)) +#define ADC0_EMUX_R (*((volatile uint32_t *)0x40038014)) +#define ADC0_USTAT_R (*((volatile uint32_t *)0x40038018)) +#define ADC0_TSSEL_R (*((volatile uint32_t *)0x4003801C)) +#define ADC0_SSPRI_R (*((volatile uint32_t *)0x40038020)) +#define ADC0_SPC_R (*((volatile uint32_t *)0x40038024)) +#define ADC0_PSSI_R (*((volatile uint32_t *)0x40038028)) +#define ADC0_SAC_R (*((volatile uint32_t *)0x40038030)) +#define ADC0_DCISC_R (*((volatile uint32_t *)0x40038034)) +#define ADC0_CTL_R (*((volatile uint32_t *)0x40038038)) +#define ADC0_SSMUX0_R (*((volatile uint32_t *)0x40038040)) +#define ADC0_SSCTL0_R (*((volatile uint32_t *)0x40038044)) +#define ADC0_SSFIFO0_R (*((volatile uint32_t *)0x40038048)) +#define ADC0_SSFSTAT0_R (*((volatile uint32_t *)0x4003804C)) +#define ADC0_SSOP0_R (*((volatile uint32_t *)0x40038050)) +#define ADC0_SSDC0_R (*((volatile uint32_t *)0x40038054)) +#define ADC0_SSMUX1_R (*((volatile uint32_t *)0x40038060)) +#define ADC0_SSCTL1_R (*((volatile uint32_t *)0x40038064)) +#define ADC0_SSFIFO1_R (*((volatile uint32_t *)0x40038068)) +#define ADC0_SSFSTAT1_R (*((volatile uint32_t *)0x4003806C)) +#define ADC0_SSOP1_R (*((volatile uint32_t *)0x40038070)) +#define ADC0_SSDC1_R (*((volatile uint32_t *)0x40038074)) +#define ADC0_SSMUX2_R (*((volatile uint32_t *)0x40038080)) +#define ADC0_SSCTL2_R (*((volatile uint32_t *)0x40038084)) +#define ADC0_SSFIFO2_R (*((volatile uint32_t *)0x40038088)) +#define ADC0_SSFSTAT2_R (*((volatile uint32_t *)0x4003808C)) +#define ADC0_SSOP2_R (*((volatile uint32_t *)0x40038090)) +#define ADC0_SSDC2_R (*((volatile uint32_t *)0x40038094)) +#define ADC0_SSMUX3_R (*((volatile uint32_t *)0x400380A0)) +#define ADC0_SSCTL3_R (*((volatile uint32_t *)0x400380A4)) +#define ADC0_SSFIFO3_R (*((volatile uint32_t *)0x400380A8)) +#define ADC0_SSFSTAT3_R (*((volatile uint32_t *)0x400380AC)) +#define ADC0_SSOP3_R (*((volatile uint32_t *)0x400380B0)) +#define ADC0_SSDC3_R (*((volatile uint32_t *)0x400380B4)) +#define ADC0_DCRIC_R (*((volatile uint32_t *)0x40038D00)) +#define ADC0_DCCTL0_R (*((volatile uint32_t *)0x40038E00)) +#define ADC0_DCCTL1_R (*((volatile uint32_t *)0x40038E04)) +#define ADC0_DCCTL2_R (*((volatile uint32_t *)0x40038E08)) +#define ADC0_DCCTL3_R (*((volatile uint32_t *)0x40038E0C)) +#define ADC0_DCCTL4_R (*((volatile uint32_t *)0x40038E10)) +#define ADC0_DCCTL5_R (*((volatile uint32_t *)0x40038E14)) +#define ADC0_DCCTL6_R (*((volatile uint32_t *)0x40038E18)) +#define ADC0_DCCTL7_R (*((volatile uint32_t *)0x40038E1C)) +#define ADC0_DCCMP0_R (*((volatile uint32_t *)0x40038E40)) +#define ADC0_DCCMP1_R (*((volatile uint32_t *)0x40038E44)) +#define ADC0_DCCMP2_R (*((volatile uint32_t *)0x40038E48)) +#define ADC0_DCCMP3_R (*((volatile uint32_t *)0x40038E4C)) +#define ADC0_DCCMP4_R (*((volatile uint32_t *)0x40038E50)) +#define ADC0_DCCMP5_R (*((volatile uint32_t *)0x40038E54)) +#define ADC0_DCCMP6_R (*((volatile uint32_t *)0x40038E58)) +#define ADC0_DCCMP7_R (*((volatile uint32_t *)0x40038E5C)) +#define ADC0_PP_R (*((volatile uint32_t *)0x40038FC0)) +#define ADC0_PC_R (*((volatile uint32_t *)0x40038FC4)) +#define ADC0_CC_R (*((volatile uint32_t *)0x40038FC8)) + +//***************************************************************************** +// +// ADC registers (ADC1) +// +//***************************************************************************** +#define ADC1_ACTSS_R (*((volatile uint32_t *)0x40039000)) +#define ADC1_RIS_R (*((volatile uint32_t *)0x40039004)) +#define ADC1_IM_R (*((volatile uint32_t *)0x40039008)) +#define ADC1_ISC_R (*((volatile uint32_t *)0x4003900C)) +#define ADC1_OSTAT_R (*((volatile uint32_t *)0x40039010)) +#define ADC1_EMUX_R (*((volatile uint32_t *)0x40039014)) +#define ADC1_USTAT_R (*((volatile uint32_t *)0x40039018)) +#define ADC1_TSSEL_R (*((volatile uint32_t *)0x4003901C)) +#define ADC1_SSPRI_R (*((volatile uint32_t *)0x40039020)) +#define ADC1_SPC_R (*((volatile uint32_t *)0x40039024)) +#define ADC1_PSSI_R (*((volatile uint32_t *)0x40039028)) +#define ADC1_SAC_R (*((volatile uint32_t *)0x40039030)) +#define ADC1_DCISC_R (*((volatile uint32_t *)0x40039034)) +#define ADC1_CTL_R (*((volatile uint32_t *)0x40039038)) +#define ADC1_SSMUX0_R (*((volatile uint32_t *)0x40039040)) +#define ADC1_SSCTL0_R (*((volatile uint32_t *)0x40039044)) +#define ADC1_SSFIFO0_R (*((volatile uint32_t *)0x40039048)) +#define ADC1_SSFSTAT0_R (*((volatile uint32_t *)0x4003904C)) +#define ADC1_SSOP0_R (*((volatile uint32_t *)0x40039050)) +#define ADC1_SSDC0_R (*((volatile uint32_t *)0x40039054)) +#define ADC1_SSMUX1_R (*((volatile uint32_t *)0x40039060)) +#define ADC1_SSCTL1_R (*((volatile uint32_t *)0x40039064)) +#define ADC1_SSFIFO1_R (*((volatile uint32_t *)0x40039068)) +#define ADC1_SSFSTAT1_R (*((volatile uint32_t *)0x4003906C)) +#define ADC1_SSOP1_R (*((volatile uint32_t *)0x40039070)) +#define ADC1_SSDC1_R (*((volatile uint32_t *)0x40039074)) +#define ADC1_SSMUX2_R (*((volatile uint32_t *)0x40039080)) +#define ADC1_SSCTL2_R (*((volatile uint32_t *)0x40039084)) +#define ADC1_SSFIFO2_R (*((volatile uint32_t *)0x40039088)) +#define ADC1_SSFSTAT2_R (*((volatile uint32_t *)0x4003908C)) +#define ADC1_SSOP2_R (*((volatile uint32_t *)0x40039090)) +#define ADC1_SSDC2_R (*((volatile uint32_t *)0x40039094)) +#define ADC1_SSMUX3_R (*((volatile uint32_t *)0x400390A0)) +#define ADC1_SSCTL3_R (*((volatile uint32_t *)0x400390A4)) +#define ADC1_SSFIFO3_R (*((volatile uint32_t *)0x400390A8)) +#define ADC1_SSFSTAT3_R (*((volatile uint32_t *)0x400390AC)) +#define ADC1_SSOP3_R (*((volatile uint32_t *)0x400390B0)) +#define ADC1_SSDC3_R (*((volatile uint32_t *)0x400390B4)) +#define ADC1_DCRIC_R (*((volatile uint32_t *)0x40039D00)) +#define ADC1_DCCTL0_R (*((volatile uint32_t *)0x40039E00)) +#define ADC1_DCCTL1_R (*((volatile uint32_t *)0x40039E04)) +#define ADC1_DCCTL2_R (*((volatile uint32_t *)0x40039E08)) +#define ADC1_DCCTL3_R (*((volatile uint32_t *)0x40039E0C)) +#define ADC1_DCCTL4_R (*((volatile uint32_t *)0x40039E10)) +#define ADC1_DCCTL5_R (*((volatile uint32_t *)0x40039E14)) +#define ADC1_DCCTL6_R (*((volatile uint32_t *)0x40039E18)) +#define ADC1_DCCTL7_R (*((volatile uint32_t *)0x40039E1C)) +#define ADC1_DCCMP0_R (*((volatile uint32_t *)0x40039E40)) +#define ADC1_DCCMP1_R (*((volatile uint32_t *)0x40039E44)) +#define ADC1_DCCMP2_R (*((volatile uint32_t *)0x40039E48)) +#define ADC1_DCCMP3_R (*((volatile uint32_t *)0x40039E4C)) +#define ADC1_DCCMP4_R (*((volatile uint32_t *)0x40039E50)) +#define ADC1_DCCMP5_R (*((volatile uint32_t *)0x40039E54)) +#define ADC1_DCCMP6_R (*((volatile uint32_t *)0x40039E58)) +#define ADC1_DCCMP7_R (*((volatile uint32_t *)0x40039E5C)) +#define ADC1_PP_R (*((volatile uint32_t *)0x40039FC0)) +#define ADC1_PC_R (*((volatile uint32_t *)0x40039FC4)) +#define ADC1_CC_R (*((volatile uint32_t *)0x40039FC8)) + +//***************************************************************************** +// +// Comparator registers (COMP) +// +//***************************************************************************** +#define COMP_ACMIS_R (*((volatile uint32_t *)0x4003C000)) +#define COMP_ACRIS_R (*((volatile uint32_t *)0x4003C004)) +#define COMP_ACINTEN_R (*((volatile uint32_t *)0x4003C008)) +#define COMP_ACREFCTL_R (*((volatile uint32_t *)0x4003C010)) +#define COMP_ACSTAT0_R (*((volatile uint32_t *)0x4003C020)) +#define COMP_ACCTL0_R (*((volatile uint32_t *)0x4003C024)) +#define COMP_ACSTAT1_R (*((volatile uint32_t *)0x4003C040)) +#define COMP_ACCTL1_R (*((volatile uint32_t *)0x4003C044)) +#define COMP_PP_R (*((volatile uint32_t *)0x4003CFC0)) + +//***************************************************************************** +// +// CAN registers (CAN0) +// +//***************************************************************************** +#define CAN0_CTL_R (*((volatile uint32_t *)0x40040000)) +#define CAN0_STS_R (*((volatile uint32_t *)0x40040004)) +#define CAN0_ERR_R (*((volatile uint32_t *)0x40040008)) +#define CAN0_BIT_R (*((volatile uint32_t *)0x4004000C)) +#define CAN0_INT_R (*((volatile uint32_t *)0x40040010)) +#define CAN0_TST_R (*((volatile uint32_t *)0x40040014)) +#define CAN0_BRPE_R (*((volatile uint32_t *)0x40040018)) +#define CAN0_IF1CRQ_R (*((volatile uint32_t *)0x40040020)) +#define CAN0_IF1CMSK_R (*((volatile uint32_t *)0x40040024)) +#define CAN0_IF1MSK1_R (*((volatile uint32_t *)0x40040028)) +#define CAN0_IF1MSK2_R (*((volatile uint32_t *)0x4004002C)) +#define CAN0_IF1ARB1_R (*((volatile uint32_t *)0x40040030)) +#define CAN0_IF1ARB2_R (*((volatile uint32_t *)0x40040034)) +#define CAN0_IF1MCTL_R (*((volatile uint32_t *)0x40040038)) +#define CAN0_IF1DA1_R (*((volatile uint32_t *)0x4004003C)) +#define CAN0_IF1DA2_R (*((volatile uint32_t *)0x40040040)) +#define CAN0_IF1DB1_R (*((volatile uint32_t *)0x40040044)) +#define CAN0_IF1DB2_R (*((volatile uint32_t *)0x40040048)) +#define CAN0_IF2CRQ_R (*((volatile uint32_t *)0x40040080)) +#define CAN0_IF2CMSK_R (*((volatile uint32_t *)0x40040084)) +#define CAN0_IF2MSK1_R (*((volatile uint32_t *)0x40040088)) +#define CAN0_IF2MSK2_R (*((volatile uint32_t *)0x4004008C)) +#define CAN0_IF2ARB1_R (*((volatile uint32_t *)0x40040090)) +#define CAN0_IF2ARB2_R (*((volatile uint32_t *)0x40040094)) +#define CAN0_IF2MCTL_R (*((volatile uint32_t *)0x40040098)) +#define CAN0_IF2DA1_R (*((volatile uint32_t *)0x4004009C)) +#define CAN0_IF2DA2_R (*((volatile uint32_t *)0x400400A0)) +#define CAN0_IF2DB1_R (*((volatile uint32_t *)0x400400A4)) +#define CAN0_IF2DB2_R (*((volatile uint32_t *)0x400400A8)) +#define CAN0_TXRQ1_R (*((volatile uint32_t *)0x40040100)) +#define CAN0_TXRQ2_R (*((volatile uint32_t *)0x40040104)) +#define CAN0_NWDA1_R (*((volatile uint32_t *)0x40040120)) +#define CAN0_NWDA2_R (*((volatile uint32_t *)0x40040124)) +#define CAN0_MSG1INT_R (*((volatile uint32_t *)0x40040140)) +#define CAN0_MSG2INT_R (*((volatile uint32_t *)0x40040144)) +#define CAN0_MSG1VAL_R (*((volatile uint32_t *)0x40040160)) +#define CAN0_MSG2VAL_R (*((volatile uint32_t *)0x40040164)) + +//***************************************************************************** +// +// CAN registers (CAN1) +// +//***************************************************************************** +#define CAN1_CTL_R (*((volatile uint32_t *)0x40041000)) +#define CAN1_STS_R (*((volatile uint32_t *)0x40041004)) +#define CAN1_ERR_R (*((volatile uint32_t *)0x40041008)) +#define CAN1_BIT_R (*((volatile uint32_t *)0x4004100C)) +#define CAN1_INT_R (*((volatile uint32_t *)0x40041010)) +#define CAN1_TST_R (*((volatile uint32_t *)0x40041014)) +#define CAN1_BRPE_R (*((volatile uint32_t *)0x40041018)) +#define CAN1_IF1CRQ_R (*((volatile uint32_t *)0x40041020)) +#define CAN1_IF1CMSK_R (*((volatile uint32_t *)0x40041024)) +#define CAN1_IF1MSK1_R (*((volatile uint32_t *)0x40041028)) +#define CAN1_IF1MSK2_R (*((volatile uint32_t *)0x4004102C)) +#define CAN1_IF1ARB1_R (*((volatile uint32_t *)0x40041030)) +#define CAN1_IF1ARB2_R (*((volatile uint32_t *)0x40041034)) +#define CAN1_IF1MCTL_R (*((volatile uint32_t *)0x40041038)) +#define CAN1_IF1DA1_R (*((volatile uint32_t *)0x4004103C)) +#define CAN1_IF1DA2_R (*((volatile uint32_t *)0x40041040)) +#define CAN1_IF1DB1_R (*((volatile uint32_t *)0x40041044)) +#define CAN1_IF1DB2_R (*((volatile uint32_t *)0x40041048)) +#define CAN1_IF2CRQ_R (*((volatile uint32_t *)0x40041080)) +#define CAN1_IF2CMSK_R (*((volatile uint32_t *)0x40041084)) +#define CAN1_IF2MSK1_R (*((volatile uint32_t *)0x40041088)) +#define CAN1_IF2MSK2_R (*((volatile uint32_t *)0x4004108C)) +#define CAN1_IF2ARB1_R (*((volatile uint32_t *)0x40041090)) +#define CAN1_IF2ARB2_R (*((volatile uint32_t *)0x40041094)) +#define CAN1_IF2MCTL_R (*((volatile uint32_t *)0x40041098)) +#define CAN1_IF2DA1_R (*((volatile uint32_t *)0x4004109C)) +#define CAN1_IF2DA2_R (*((volatile uint32_t *)0x400410A0)) +#define CAN1_IF2DB1_R (*((volatile uint32_t *)0x400410A4)) +#define CAN1_IF2DB2_R (*((volatile uint32_t *)0x400410A8)) +#define CAN1_TXRQ1_R (*((volatile uint32_t *)0x40041100)) +#define CAN1_TXRQ2_R (*((volatile uint32_t *)0x40041104)) +#define CAN1_NWDA1_R (*((volatile uint32_t *)0x40041120)) +#define CAN1_NWDA2_R (*((volatile uint32_t *)0x40041124)) +#define CAN1_MSG1INT_R (*((volatile uint32_t *)0x40041140)) +#define CAN1_MSG2INT_R (*((volatile uint32_t *)0x40041144)) +#define CAN1_MSG1VAL_R (*((volatile uint32_t *)0x40041160)) +#define CAN1_MSG2VAL_R (*((volatile uint32_t *)0x40041164)) + +//***************************************************************************** +// +// Timer registers (WTIMER2) +// +//***************************************************************************** +#define WTIMER2_CFG_R (*((volatile uint32_t *)0x4004C000)) +#define WTIMER2_TAMR_R (*((volatile uint32_t *)0x4004C004)) +#define WTIMER2_TBMR_R (*((volatile uint32_t *)0x4004C008)) +#define WTIMER2_CTL_R (*((volatile uint32_t *)0x4004C00C)) +#define WTIMER2_SYNC_R (*((volatile uint32_t *)0x4004C010)) +#define WTIMER2_IMR_R (*((volatile uint32_t *)0x4004C018)) +#define WTIMER2_RIS_R (*((volatile uint32_t *)0x4004C01C)) +#define WTIMER2_MIS_R (*((volatile uint32_t *)0x4004C020)) +#define WTIMER2_ICR_R (*((volatile uint32_t *)0x4004C024)) +#define WTIMER2_TAILR_R (*((volatile uint32_t *)0x4004C028)) +#define WTIMER2_TBILR_R (*((volatile uint32_t *)0x4004C02C)) +#define WTIMER2_TAMATCHR_R (*((volatile uint32_t *)0x4004C030)) +#define WTIMER2_TBMATCHR_R (*((volatile uint32_t *)0x4004C034)) +#define WTIMER2_TAPR_R (*((volatile uint32_t *)0x4004C038)) +#define WTIMER2_TBPR_R (*((volatile uint32_t *)0x4004C03C)) +#define WTIMER2_TAPMR_R (*((volatile uint32_t *)0x4004C040)) +#define WTIMER2_TBPMR_R (*((volatile uint32_t *)0x4004C044)) +#define WTIMER2_TAR_R (*((volatile uint32_t *)0x4004C048)) +#define WTIMER2_TBR_R (*((volatile uint32_t *)0x4004C04C)) +#define WTIMER2_TAV_R (*((volatile uint32_t *)0x4004C050)) +#define WTIMER2_TBV_R (*((volatile uint32_t *)0x4004C054)) +#define WTIMER2_RTCPD_R (*((volatile uint32_t *)0x4004C058)) +#define WTIMER2_TAPS_R (*((volatile uint32_t *)0x4004C05C)) +#define WTIMER2_TBPS_R (*((volatile uint32_t *)0x4004C060)) +#define WTIMER2_TAPV_R (*((volatile uint32_t *)0x4004C064)) +#define WTIMER2_TBPV_R (*((volatile uint32_t *)0x4004C068)) +#define WTIMER2_PP_R (*((volatile uint32_t *)0x4004CFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER3) +// +//***************************************************************************** +#define WTIMER3_CFG_R (*((volatile uint32_t *)0x4004D000)) +#define WTIMER3_TAMR_R (*((volatile uint32_t *)0x4004D004)) +#define WTIMER3_TBMR_R (*((volatile uint32_t *)0x4004D008)) +#define WTIMER3_CTL_R (*((volatile uint32_t *)0x4004D00C)) +#define WTIMER3_SYNC_R (*((volatile uint32_t *)0x4004D010)) +#define WTIMER3_IMR_R (*((volatile uint32_t *)0x4004D018)) +#define WTIMER3_RIS_R (*((volatile uint32_t *)0x4004D01C)) +#define WTIMER3_MIS_R (*((volatile uint32_t *)0x4004D020)) +#define WTIMER3_ICR_R (*((volatile uint32_t *)0x4004D024)) +#define WTIMER3_TAILR_R (*((volatile uint32_t *)0x4004D028)) +#define WTIMER3_TBILR_R (*((volatile uint32_t *)0x4004D02C)) +#define WTIMER3_TAMATCHR_R (*((volatile uint32_t *)0x4004D030)) +#define WTIMER3_TBMATCHR_R (*((volatile uint32_t *)0x4004D034)) +#define WTIMER3_TAPR_R (*((volatile uint32_t *)0x4004D038)) +#define WTIMER3_TBPR_R (*((volatile uint32_t *)0x4004D03C)) +#define WTIMER3_TAPMR_R (*((volatile uint32_t *)0x4004D040)) +#define WTIMER3_TBPMR_R (*((volatile uint32_t *)0x4004D044)) +#define WTIMER3_TAR_R (*((volatile uint32_t *)0x4004D048)) +#define WTIMER3_TBR_R (*((volatile uint32_t *)0x4004D04C)) +#define WTIMER3_TAV_R (*((volatile uint32_t *)0x4004D050)) +#define WTIMER3_TBV_R (*((volatile uint32_t *)0x4004D054)) +#define WTIMER3_RTCPD_R (*((volatile uint32_t *)0x4004D058)) +#define WTIMER3_TAPS_R (*((volatile uint32_t *)0x4004D05C)) +#define WTIMER3_TBPS_R (*((volatile uint32_t *)0x4004D060)) +#define WTIMER3_TAPV_R (*((volatile uint32_t *)0x4004D064)) +#define WTIMER3_TBPV_R (*((volatile uint32_t *)0x4004D068)) +#define WTIMER3_PP_R (*((volatile uint32_t *)0x4004DFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER4) +// +//***************************************************************************** +#define WTIMER4_CFG_R (*((volatile uint32_t *)0x4004E000)) +#define WTIMER4_TAMR_R (*((volatile uint32_t *)0x4004E004)) +#define WTIMER4_TBMR_R (*((volatile uint32_t *)0x4004E008)) +#define WTIMER4_CTL_R (*((volatile uint32_t *)0x4004E00C)) +#define WTIMER4_SYNC_R (*((volatile uint32_t *)0x4004E010)) +#define WTIMER4_IMR_R (*((volatile uint32_t *)0x4004E018)) +#define WTIMER4_RIS_R (*((volatile uint32_t *)0x4004E01C)) +#define WTIMER4_MIS_R (*((volatile uint32_t *)0x4004E020)) +#define WTIMER4_ICR_R (*((volatile uint32_t *)0x4004E024)) +#define WTIMER4_TAILR_R (*((volatile uint32_t *)0x4004E028)) +#define WTIMER4_TBILR_R (*((volatile uint32_t *)0x4004E02C)) +#define WTIMER4_TAMATCHR_R (*((volatile uint32_t *)0x4004E030)) +#define WTIMER4_TBMATCHR_R (*((volatile uint32_t *)0x4004E034)) +#define WTIMER4_TAPR_R (*((volatile uint32_t *)0x4004E038)) +#define WTIMER4_TBPR_R (*((volatile uint32_t *)0x4004E03C)) +#define WTIMER4_TAPMR_R (*((volatile uint32_t *)0x4004E040)) +#define WTIMER4_TBPMR_R (*((volatile uint32_t *)0x4004E044)) +#define WTIMER4_TAR_R (*((volatile uint32_t *)0x4004E048)) +#define WTIMER4_TBR_R (*((volatile uint32_t *)0x4004E04C)) +#define WTIMER4_TAV_R (*((volatile uint32_t *)0x4004E050)) +#define WTIMER4_TBV_R (*((volatile uint32_t *)0x4004E054)) +#define WTIMER4_RTCPD_R (*((volatile uint32_t *)0x4004E058)) +#define WTIMER4_TAPS_R (*((volatile uint32_t *)0x4004E05C)) +#define WTIMER4_TBPS_R (*((volatile uint32_t *)0x4004E060)) +#define WTIMER4_TAPV_R (*((volatile uint32_t *)0x4004E064)) +#define WTIMER4_TBPV_R (*((volatile uint32_t *)0x4004E068)) +#define WTIMER4_PP_R (*((volatile uint32_t *)0x4004EFC0)) + +//***************************************************************************** +// +// Timer registers (WTIMER5) +// +//***************************************************************************** +#define WTIMER5_CFG_R (*((volatile uint32_t *)0x4004F000)) +#define WTIMER5_TAMR_R (*((volatile uint32_t *)0x4004F004)) +#define WTIMER5_TBMR_R (*((volatile uint32_t *)0x4004F008)) +#define WTIMER5_CTL_R (*((volatile uint32_t *)0x4004F00C)) +#define WTIMER5_SYNC_R (*((volatile uint32_t *)0x4004F010)) +#define WTIMER5_IMR_R (*((volatile uint32_t *)0x4004F018)) +#define WTIMER5_RIS_R (*((volatile uint32_t *)0x4004F01C)) +#define WTIMER5_MIS_R (*((volatile uint32_t *)0x4004F020)) +#define WTIMER5_ICR_R (*((volatile uint32_t *)0x4004F024)) +#define WTIMER5_TAILR_R (*((volatile uint32_t *)0x4004F028)) +#define WTIMER5_TBILR_R (*((volatile uint32_t *)0x4004F02C)) +#define WTIMER5_TAMATCHR_R (*((volatile uint32_t *)0x4004F030)) +#define WTIMER5_TBMATCHR_R (*((volatile uint32_t *)0x4004F034)) +#define WTIMER5_TAPR_R (*((volatile uint32_t *)0x4004F038)) +#define WTIMER5_TBPR_R (*((volatile uint32_t *)0x4004F03C)) +#define WTIMER5_TAPMR_R (*((volatile uint32_t *)0x4004F040)) +#define WTIMER5_TBPMR_R (*((volatile uint32_t *)0x4004F044)) +#define WTIMER5_TAR_R (*((volatile uint32_t *)0x4004F048)) +#define WTIMER5_TBR_R (*((volatile uint32_t *)0x4004F04C)) +#define WTIMER5_TAV_R (*((volatile uint32_t *)0x4004F050)) +#define WTIMER5_TBV_R (*((volatile uint32_t *)0x4004F054)) +#define WTIMER5_RTCPD_R (*((volatile uint32_t *)0x4004F058)) +#define WTIMER5_TAPS_R (*((volatile uint32_t *)0x4004F05C)) +#define WTIMER5_TBPS_R (*((volatile uint32_t *)0x4004F060)) +#define WTIMER5_TAPV_R (*((volatile uint32_t *)0x4004F064)) +#define WTIMER5_TBPV_R (*((volatile uint32_t *)0x4004F068)) +#define WTIMER5_PP_R (*((volatile uint32_t *)0x4004FFC0)) + +//***************************************************************************** +// +// Univeral Serial Bus registers (USB0) +// +//***************************************************************************** +#define USB0_FADDR_R (*((volatile uint8_t *)0x40050000)) +#define USB0_POWER_R (*((volatile uint8_t *)0x40050001)) +#define USB0_TXIS_R (*((volatile uint16_t *)0x40050002)) +#define USB0_RXIS_R (*((volatile uint16_t *)0x40050004)) +#define USB0_TXIE_R (*((volatile uint16_t *)0x40050006)) +#define USB0_RXIE_R (*((volatile uint16_t *)0x40050008)) +#define USB0_IS_R (*((volatile uint8_t *)0x4005000A)) +#define USB0_IE_R (*((volatile uint8_t *)0x4005000B)) +#define USB0_FRAME_R (*((volatile uint16_t *)0x4005000C)) +#define USB0_EPIDX_R (*((volatile uint8_t *)0x4005000E)) +#define USB0_TEST_R (*((volatile uint8_t *)0x4005000F)) +#define USB0_FIFO0_R (*((volatile uint32_t *)0x40050020)) +#define USB0_FIFO1_R (*((volatile uint32_t *)0x40050024)) +#define USB0_FIFO2_R (*((volatile uint32_t *)0x40050028)) +#define USB0_FIFO3_R (*((volatile uint32_t *)0x4005002C)) +#define USB0_FIFO4_R (*((volatile uint32_t *)0x40050030)) +#define USB0_FIFO5_R (*((volatile uint32_t *)0x40050034)) +#define USB0_FIFO6_R (*((volatile uint32_t *)0x40050038)) +#define USB0_FIFO7_R (*((volatile uint32_t *)0x4005003C)) +#define USB0_DEVCTL_R (*((volatile uint8_t *)0x40050060)) +#define USB0_TXFIFOSZ_R (*((volatile uint8_t *)0x40050062)) +#define USB0_RXFIFOSZ_R (*((volatile uint8_t *)0x40050063)) +#define USB0_TXFIFOADD_R (*((volatile uint16_t *)0x40050064)) +#define USB0_RXFIFOADD_R (*((volatile uint16_t *)0x40050066)) +#define USB0_CONTIM_R (*((volatile uint8_t *)0x4005007A)) +#define USB0_VPLEN_R (*((volatile uint8_t *)0x4005007B)) +#define USB0_FSEOF_R (*((volatile uint8_t *)0x4005007D)) +#define USB0_LSEOF_R (*((volatile uint8_t *)0x4005007E)) +#define USB0_TXFUNCADDR0_R (*((volatile uint8_t *)0x40050080)) +#define USB0_TXHUBADDR0_R (*((volatile uint8_t *)0x40050082)) +#define USB0_TXHUBPORT0_R (*((volatile uint8_t *)0x40050083)) +#define USB0_TXFUNCADDR1_R (*((volatile uint8_t *)0x40050088)) +#define USB0_TXHUBADDR1_R (*((volatile uint8_t *)0x4005008A)) +#define USB0_TXHUBPORT1_R (*((volatile uint8_t *)0x4005008B)) +#define USB0_RXFUNCADDR1_R (*((volatile uint8_t *)0x4005008C)) +#define USB0_RXHUBADDR1_R (*((volatile uint8_t *)0x4005008E)) +#define USB0_RXHUBPORT1_R (*((volatile uint8_t *)0x4005008F)) +#define USB0_TXFUNCADDR2_R (*((volatile uint8_t *)0x40050090)) +#define USB0_TXHUBADDR2_R (*((volatile uint8_t *)0x40050092)) +#define USB0_TXHUBPORT2_R (*((volatile uint8_t *)0x40050093)) +#define USB0_RXFUNCADDR2_R (*((volatile uint8_t *)0x40050094)) +#define USB0_RXHUBADDR2_R (*((volatile uint8_t *)0x40050096)) +#define USB0_RXHUBPORT2_R (*((volatile uint8_t *)0x40050097)) +#define USB0_TXFUNCADDR3_R (*((volatile uint8_t *)0x40050098)) +#define USB0_TXHUBADDR3_R (*((volatile uint8_t *)0x4005009A)) +#define USB0_TXHUBPORT3_R (*((volatile uint8_t *)0x4005009B)) +#define USB0_RXFUNCADDR3_R (*((volatile uint8_t *)0x4005009C)) +#define USB0_RXHUBADDR3_R (*((volatile uint8_t *)0x4005009E)) +#define USB0_RXHUBPORT3_R (*((volatile uint8_t *)0x4005009F)) +#define USB0_TXFUNCADDR4_R (*((volatile uint8_t *)0x400500A0)) +#define USB0_TXHUBADDR4_R (*((volatile uint8_t *)0x400500A2)) +#define USB0_TXHUBPORT4_R (*((volatile uint8_t *)0x400500A3)) +#define USB0_RXFUNCADDR4_R (*((volatile uint8_t *)0x400500A4)) +#define USB0_RXHUBADDR4_R (*((volatile uint8_t *)0x400500A6)) +#define USB0_RXHUBPORT4_R (*((volatile uint8_t *)0x400500A7)) +#define USB0_TXFUNCADDR5_R (*((volatile uint8_t *)0x400500A8)) +#define USB0_TXHUBADDR5_R (*((volatile uint8_t *)0x400500AA)) +#define USB0_TXHUBPORT5_R (*((volatile uint8_t *)0x400500AB)) +#define USB0_RXFUNCADDR5_R (*((volatile uint8_t *)0x400500AC)) +#define USB0_RXHUBADDR5_R (*((volatile uint8_t *)0x400500AE)) +#define USB0_RXHUBPORT5_R (*((volatile uint8_t *)0x400500AF)) +#define USB0_TXFUNCADDR6_R (*((volatile uint8_t *)0x400500B0)) +#define USB0_TXHUBADDR6_R (*((volatile uint8_t *)0x400500B2)) +#define USB0_TXHUBPORT6_R (*((volatile uint8_t *)0x400500B3)) +#define USB0_RXFUNCADDR6_R (*((volatile uint8_t *)0x400500B4)) +#define USB0_RXHUBADDR6_R (*((volatile uint8_t *)0x400500B6)) +#define USB0_RXHUBPORT6_R (*((volatile uint8_t *)0x400500B7)) +#define USB0_TXFUNCADDR7_R (*((volatile uint8_t *)0x400500B8)) +#define USB0_TXHUBADDR7_R (*((volatile uint8_t *)0x400500BA)) +#define USB0_TXHUBPORT7_R (*((volatile uint8_t *)0x400500BB)) +#define USB0_RXFUNCADDR7_R (*((volatile uint8_t *)0x400500BC)) +#define USB0_RXHUBADDR7_R (*((volatile uint8_t *)0x400500BE)) +#define USB0_RXHUBPORT7_R (*((volatile uint8_t *)0x400500BF)) +#define USB0_CSRL0_R (*((volatile uint8_t *)0x40050102)) +#define USB0_CSRH0_R (*((volatile uint8_t *)0x40050103)) +#define USB0_COUNT0_R (*((volatile uint8_t *)0x40050108)) +#define USB0_TYPE0_R (*((volatile uint8_t *)0x4005010A)) +#define USB0_NAKLMT_R (*((volatile uint8_t *)0x4005010B)) +#define USB0_TXMAXP1_R (*((volatile uint16_t *)0x40050110)) +#define USB0_TXCSRL1_R (*((volatile uint8_t *)0x40050112)) +#define USB0_TXCSRH1_R (*((volatile uint8_t *)0x40050113)) +#define USB0_RXMAXP1_R (*((volatile uint16_t *)0x40050114)) +#define USB0_RXCSRL1_R (*((volatile uint8_t *)0x40050116)) +#define USB0_RXCSRH1_R (*((volatile uint8_t *)0x40050117)) +#define USB0_RXCOUNT1_R (*((volatile uint16_t *)0x40050118)) +#define USB0_TXTYPE1_R (*((volatile uint8_t *)0x4005011A)) +#define USB0_TXINTERVAL1_R (*((volatile uint8_t *)0x4005011B)) +#define USB0_RXTYPE1_R (*((volatile uint8_t *)0x4005011C)) +#define USB0_RXINTERVAL1_R (*((volatile uint8_t *)0x4005011D)) +#define USB0_TXMAXP2_R (*((volatile uint16_t *)0x40050120)) +#define USB0_TXCSRL2_R (*((volatile uint8_t *)0x40050122)) +#define USB0_TXCSRH2_R (*((volatile uint8_t *)0x40050123)) +#define USB0_RXMAXP2_R (*((volatile uint16_t *)0x40050124)) +#define USB0_RXCSRL2_R (*((volatile uint8_t *)0x40050126)) +#define USB0_RXCSRH2_R (*((volatile uint8_t *)0x40050127)) +#define USB0_RXCOUNT2_R (*((volatile uint16_t *)0x40050128)) +#define USB0_TXTYPE2_R (*((volatile uint8_t *)0x4005012A)) +#define USB0_TXINTERVAL2_R (*((volatile uint8_t *)0x4005012B)) +#define USB0_RXTYPE2_R (*((volatile uint8_t *)0x4005012C)) +#define USB0_RXINTERVAL2_R (*((volatile uint8_t *)0x4005012D)) +#define USB0_TXMAXP3_R (*((volatile uint16_t *)0x40050130)) +#define USB0_TXCSRL3_R (*((volatile uint8_t *)0x40050132)) +#define USB0_TXCSRH3_R (*((volatile uint8_t *)0x40050133)) +#define USB0_RXMAXP3_R (*((volatile uint16_t *)0x40050134)) +#define USB0_RXCSRL3_R (*((volatile uint8_t *)0x40050136)) +#define USB0_RXCSRH3_R (*((volatile uint8_t *)0x40050137)) +#define USB0_RXCOUNT3_R (*((volatile uint16_t *)0x40050138)) +#define USB0_TXTYPE3_R (*((volatile uint8_t *)0x4005013A)) +#define USB0_TXINTERVAL3_R (*((volatile uint8_t *)0x4005013B)) +#define USB0_RXTYPE3_R (*((volatile uint8_t *)0x4005013C)) +#define USB0_RXINTERVAL3_R (*((volatile uint8_t *)0x4005013D)) +#define USB0_TXMAXP4_R (*((volatile uint16_t *)0x40050140)) +#define USB0_TXCSRL4_R (*((volatile uint8_t *)0x40050142)) +#define USB0_TXCSRH4_R (*((volatile uint8_t *)0x40050143)) +#define USB0_RXMAXP4_R (*((volatile uint16_t *)0x40050144)) +#define USB0_RXCSRL4_R (*((volatile uint8_t *)0x40050146)) +#define USB0_RXCSRH4_R (*((volatile uint8_t *)0x40050147)) +#define USB0_RXCOUNT4_R (*((volatile uint16_t *)0x40050148)) +#define USB0_TXTYPE4_R (*((volatile uint8_t *)0x4005014A)) +#define USB0_TXINTERVAL4_R (*((volatile uint8_t *)0x4005014B)) +#define USB0_RXTYPE4_R (*((volatile uint8_t *)0x4005014C)) +#define USB0_RXINTERVAL4_R (*((volatile uint8_t *)0x4005014D)) +#define USB0_TXMAXP5_R (*((volatile uint16_t *)0x40050150)) +#define USB0_TXCSRL5_R (*((volatile uint8_t *)0x40050152)) +#define USB0_TXCSRH5_R (*((volatile uint8_t *)0x40050153)) +#define USB0_RXMAXP5_R (*((volatile uint16_t *)0x40050154)) +#define USB0_RXCSRL5_R (*((volatile uint8_t *)0x40050156)) +#define USB0_RXCSRH5_R (*((volatile uint8_t *)0x40050157)) +#define USB0_RXCOUNT5_R (*((volatile uint16_t *)0x40050158)) +#define USB0_TXTYPE5_R (*((volatile uint8_t *)0x4005015A)) +#define USB0_TXINTERVAL5_R (*((volatile uint8_t *)0x4005015B)) +#define USB0_RXTYPE5_R (*((volatile uint8_t *)0x4005015C)) +#define USB0_RXINTERVAL5_R (*((volatile uint8_t *)0x4005015D)) +#define USB0_TXMAXP6_R (*((volatile uint16_t *)0x40050160)) +#define USB0_TXCSRL6_R (*((volatile uint8_t *)0x40050162)) +#define USB0_TXCSRH6_R (*((volatile uint8_t *)0x40050163)) +#define USB0_RXMAXP6_R (*((volatile uint16_t *)0x40050164)) +#define USB0_RXCSRL6_R (*((volatile uint8_t *)0x40050166)) +#define USB0_RXCSRH6_R (*((volatile uint8_t *)0x40050167)) +#define USB0_RXCOUNT6_R (*((volatile uint16_t *)0x40050168)) +#define USB0_TXTYPE6_R (*((volatile uint8_t *)0x4005016A)) +#define USB0_TXINTERVAL6_R (*((volatile uint8_t *)0x4005016B)) +#define USB0_RXTYPE6_R (*((volatile uint8_t *)0x4005016C)) +#define USB0_RXINTERVAL6_R (*((volatile uint8_t *)0x4005016D)) +#define USB0_TXMAXP7_R (*((volatile uint16_t *)0x40050170)) +#define USB0_TXCSRL7_R (*((volatile uint8_t *)0x40050172)) +#define USB0_TXCSRH7_R (*((volatile uint8_t *)0x40050173)) +#define USB0_RXMAXP7_R (*((volatile uint16_t *)0x40050174)) +#define USB0_RXCSRL7_R (*((volatile uint8_t *)0x40050176)) +#define USB0_RXCSRH7_R (*((volatile uint8_t *)0x40050177)) +#define USB0_RXCOUNT7_R (*((volatile uint16_t *)0x40050178)) +#define USB0_TXTYPE7_R (*((volatile uint8_t *)0x4005017A)) +#define USB0_TXINTERVAL7_R (*((volatile uint8_t *)0x4005017B)) +#define USB0_RXTYPE7_R (*((volatile uint8_t *)0x4005017C)) +#define USB0_RXINTERVAL7_R (*((volatile uint8_t *)0x4005017D)) +#define USB0_RQPKTCOUNT1_R (*((volatile uint16_t *)0x40050304)) +#define USB0_RQPKTCOUNT2_R (*((volatile uint16_t *)0x40050308)) +#define USB0_RQPKTCOUNT3_R (*((volatile uint16_t *)0x4005030C)) +#define USB0_RQPKTCOUNT4_R (*((volatile uint16_t *)0x40050310)) +#define USB0_RQPKTCOUNT5_R (*((volatile uint16_t *)0x40050314)) +#define USB0_RQPKTCOUNT6_R (*((volatile uint16_t *)0x40050318)) +#define USB0_RQPKTCOUNT7_R (*((volatile uint16_t *)0x4005031C)) +#define USB0_RXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050340)) +#define USB0_TXDPKTBUFDIS_R (*((volatile uint16_t *)0x40050342)) +#define USB0_EPC_R (*((volatile uint32_t *)0x40050400)) +#define USB0_EPCRIS_R (*((volatile uint32_t *)0x40050404)) +#define USB0_EPCIM_R (*((volatile uint32_t *)0x40050408)) +#define USB0_EPCISC_R (*((volatile uint32_t *)0x4005040C)) +#define USB0_DRRIS_R (*((volatile uint32_t *)0x40050410)) +#define USB0_DRIM_R (*((volatile uint32_t *)0x40050414)) +#define USB0_DRISC_R (*((volatile uint32_t *)0x40050418)) +#define USB0_GPCS_R (*((volatile uint32_t *)0x4005041C)) +#define USB0_VDC_R (*((volatile uint32_t *)0x40050430)) +#define USB0_VDCRIS_R (*((volatile uint32_t *)0x40050434)) +#define USB0_VDCIM_R (*((volatile uint32_t *)0x40050438)) +#define USB0_VDCISC_R (*((volatile uint32_t *)0x4005043C)) +#define USB0_IDVRIS_R (*((volatile uint32_t *)0x40050444)) +#define USB0_IDVIM_R (*((volatile uint32_t *)0x40050448)) +#define USB0_IDVISC_R (*((volatile uint32_t *)0x4005044C)) +#define USB0_DMASEL_R (*((volatile uint32_t *)0x40050450)) +#define USB0_PP_R (*((volatile uint32_t *)0x40050FC0)) + +//***************************************************************************** +// +// GPIO registers (PORTA AHB) +// +//***************************************************************************** +#define GPIO_PORTA_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40058000) +#define GPIO_PORTA_AHB_DATA_R (*((volatile uint32_t *)0x400583FC)) +#define GPIO_PORTA_AHB_DIR_R (*((volatile uint32_t *)0x40058400)) +#define GPIO_PORTA_AHB_IS_R (*((volatile uint32_t *)0x40058404)) +#define GPIO_PORTA_AHB_IBE_R (*((volatile uint32_t *)0x40058408)) +#define GPIO_PORTA_AHB_IEV_R (*((volatile uint32_t *)0x4005840C)) +#define GPIO_PORTA_AHB_IM_R (*((volatile uint32_t *)0x40058410)) +#define GPIO_PORTA_AHB_RIS_R (*((volatile uint32_t *)0x40058414)) +#define GPIO_PORTA_AHB_MIS_R (*((volatile uint32_t *)0x40058418)) +#define GPIO_PORTA_AHB_ICR_R (*((volatile uint32_t *)0x4005841C)) +#define GPIO_PORTA_AHB_AFSEL_R (*((volatile uint32_t *)0x40058420)) +#define GPIO_PORTA_AHB_DR2R_R (*((volatile uint32_t *)0x40058500)) +#define GPIO_PORTA_AHB_DR4R_R (*((volatile uint32_t *)0x40058504)) +#define GPIO_PORTA_AHB_DR8R_R (*((volatile uint32_t *)0x40058508)) +#define GPIO_PORTA_AHB_ODR_R (*((volatile uint32_t *)0x4005850C)) +#define GPIO_PORTA_AHB_PUR_R (*((volatile uint32_t *)0x40058510)) +#define GPIO_PORTA_AHB_PDR_R (*((volatile uint32_t *)0x40058514)) +#define GPIO_PORTA_AHB_SLR_R (*((volatile uint32_t *)0x40058518)) +#define GPIO_PORTA_AHB_DEN_R (*((volatile uint32_t *)0x4005851C)) +#define GPIO_PORTA_AHB_LOCK_R (*((volatile uint32_t *)0x40058520)) +#define GPIO_PORTA_AHB_CR_R (*((volatile uint32_t *)0x40058524)) +#define GPIO_PORTA_AHB_AMSEL_R (*((volatile uint32_t *)0x40058528)) +#define GPIO_PORTA_AHB_PCTL_R (*((volatile uint32_t *)0x4005852C)) +#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530)) +#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534)) + +//***************************************************************************** +// +// GPIO registers (PORTB AHB) +// +//***************************************************************************** +#define GPIO_PORTB_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x40059000) +#define GPIO_PORTB_AHB_DATA_R (*((volatile uint32_t *)0x400593FC)) +#define GPIO_PORTB_AHB_DIR_R (*((volatile uint32_t *)0x40059400)) +#define GPIO_PORTB_AHB_IS_R (*((volatile uint32_t *)0x40059404)) +#define GPIO_PORTB_AHB_IBE_R (*((volatile uint32_t *)0x40059408)) +#define GPIO_PORTB_AHB_IEV_R (*((volatile uint32_t *)0x4005940C)) +#define GPIO_PORTB_AHB_IM_R (*((volatile uint32_t *)0x40059410)) +#define GPIO_PORTB_AHB_RIS_R (*((volatile uint32_t *)0x40059414)) +#define GPIO_PORTB_AHB_MIS_R (*((volatile uint32_t *)0x40059418)) +#define GPIO_PORTB_AHB_ICR_R (*((volatile uint32_t *)0x4005941C)) +#define GPIO_PORTB_AHB_AFSEL_R (*((volatile uint32_t *)0x40059420)) +#define GPIO_PORTB_AHB_DR2R_R (*((volatile uint32_t *)0x40059500)) +#define GPIO_PORTB_AHB_DR4R_R (*((volatile uint32_t *)0x40059504)) +#define GPIO_PORTB_AHB_DR8R_R (*((volatile uint32_t *)0x40059508)) +#define GPIO_PORTB_AHB_ODR_R (*((volatile uint32_t *)0x4005950C)) +#define GPIO_PORTB_AHB_PUR_R (*((volatile uint32_t *)0x40059510)) +#define GPIO_PORTB_AHB_PDR_R (*((volatile uint32_t *)0x40059514)) +#define GPIO_PORTB_AHB_SLR_R (*((volatile uint32_t *)0x40059518)) +#define GPIO_PORTB_AHB_DEN_R (*((volatile uint32_t *)0x4005951C)) +#define GPIO_PORTB_AHB_LOCK_R (*((volatile uint32_t *)0x40059520)) +#define GPIO_PORTB_AHB_CR_R (*((volatile uint32_t *)0x40059524)) +#define GPIO_PORTB_AHB_AMSEL_R (*((volatile uint32_t *)0x40059528)) +#define GPIO_PORTB_AHB_PCTL_R (*((volatile uint32_t *)0x4005952C)) +#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530)) +#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534)) + +//***************************************************************************** +// +// GPIO registers (PORTC AHB) +// +//***************************************************************************** +#define GPIO_PORTC_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005A000) +#define GPIO_PORTC_AHB_DATA_R (*((volatile uint32_t *)0x4005A3FC)) +#define GPIO_PORTC_AHB_DIR_R (*((volatile uint32_t *)0x4005A400)) +#define GPIO_PORTC_AHB_IS_R (*((volatile uint32_t *)0x4005A404)) +#define GPIO_PORTC_AHB_IBE_R (*((volatile uint32_t *)0x4005A408)) +#define GPIO_PORTC_AHB_IEV_R (*((volatile uint32_t *)0x4005A40C)) +#define GPIO_PORTC_AHB_IM_R (*((volatile uint32_t *)0x4005A410)) +#define GPIO_PORTC_AHB_RIS_R (*((volatile uint32_t *)0x4005A414)) +#define GPIO_PORTC_AHB_MIS_R (*((volatile uint32_t *)0x4005A418)) +#define GPIO_PORTC_AHB_ICR_R (*((volatile uint32_t *)0x4005A41C)) +#define GPIO_PORTC_AHB_AFSEL_R (*((volatile uint32_t *)0x4005A420)) +#define GPIO_PORTC_AHB_DR2R_R (*((volatile uint32_t *)0x4005A500)) +#define GPIO_PORTC_AHB_DR4R_R (*((volatile uint32_t *)0x4005A504)) +#define GPIO_PORTC_AHB_DR8R_R (*((volatile uint32_t *)0x4005A508)) +#define GPIO_PORTC_AHB_ODR_R (*((volatile uint32_t *)0x4005A50C)) +#define GPIO_PORTC_AHB_PUR_R (*((volatile uint32_t *)0x4005A510)) +#define GPIO_PORTC_AHB_PDR_R (*((volatile uint32_t *)0x4005A514)) +#define GPIO_PORTC_AHB_SLR_R (*((volatile uint32_t *)0x4005A518)) +#define GPIO_PORTC_AHB_DEN_R (*((volatile uint32_t *)0x4005A51C)) +#define GPIO_PORTC_AHB_LOCK_R (*((volatile uint32_t *)0x4005A520)) +#define GPIO_PORTC_AHB_CR_R (*((volatile uint32_t *)0x4005A524)) +#define GPIO_PORTC_AHB_AMSEL_R (*((volatile uint32_t *)0x4005A528)) +#define GPIO_PORTC_AHB_PCTL_R (*((volatile uint32_t *)0x4005A52C)) +#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530)) +#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534)) + +//***************************************************************************** +// +// GPIO registers (PORTD AHB) +// +//***************************************************************************** +#define GPIO_PORTD_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005B000) +#define GPIO_PORTD_AHB_DATA_R (*((volatile uint32_t *)0x4005B3FC)) +#define GPIO_PORTD_AHB_DIR_R (*((volatile uint32_t *)0x4005B400)) +#define GPIO_PORTD_AHB_IS_R (*((volatile uint32_t *)0x4005B404)) +#define GPIO_PORTD_AHB_IBE_R (*((volatile uint32_t *)0x4005B408)) +#define GPIO_PORTD_AHB_IEV_R (*((volatile uint32_t *)0x4005B40C)) +#define GPIO_PORTD_AHB_IM_R (*((volatile uint32_t *)0x4005B410)) +#define GPIO_PORTD_AHB_RIS_R (*((volatile uint32_t *)0x4005B414)) +#define GPIO_PORTD_AHB_MIS_R (*((volatile uint32_t *)0x4005B418)) +#define GPIO_PORTD_AHB_ICR_R (*((volatile uint32_t *)0x4005B41C)) +#define GPIO_PORTD_AHB_AFSEL_R (*((volatile uint32_t *)0x4005B420)) +#define GPIO_PORTD_AHB_DR2R_R (*((volatile uint32_t *)0x4005B500)) +#define GPIO_PORTD_AHB_DR4R_R (*((volatile uint32_t *)0x4005B504)) +#define GPIO_PORTD_AHB_DR8R_R (*((volatile uint32_t *)0x4005B508)) +#define GPIO_PORTD_AHB_ODR_R (*((volatile uint32_t *)0x4005B50C)) +#define GPIO_PORTD_AHB_PUR_R (*((volatile uint32_t *)0x4005B510)) +#define GPIO_PORTD_AHB_PDR_R (*((volatile uint32_t *)0x4005B514)) +#define GPIO_PORTD_AHB_SLR_R (*((volatile uint32_t *)0x4005B518)) +#define GPIO_PORTD_AHB_DEN_R (*((volatile uint32_t *)0x4005B51C)) +#define GPIO_PORTD_AHB_LOCK_R (*((volatile uint32_t *)0x4005B520)) +#define GPIO_PORTD_AHB_CR_R (*((volatile uint32_t *)0x4005B524)) +#define GPIO_PORTD_AHB_AMSEL_R (*((volatile uint32_t *)0x4005B528)) +#define GPIO_PORTD_AHB_PCTL_R (*((volatile uint32_t *)0x4005B52C)) +#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530)) +#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534)) + +//***************************************************************************** +// +// GPIO registers (PORTE AHB) +// +//***************************************************************************** +#define GPIO_PORTE_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005C000) +#define GPIO_PORTE_AHB_DATA_R (*((volatile uint32_t *)0x4005C3FC)) +#define GPIO_PORTE_AHB_DIR_R (*((volatile uint32_t *)0x4005C400)) +#define GPIO_PORTE_AHB_IS_R (*((volatile uint32_t *)0x4005C404)) +#define GPIO_PORTE_AHB_IBE_R (*((volatile uint32_t *)0x4005C408)) +#define GPIO_PORTE_AHB_IEV_R (*((volatile uint32_t *)0x4005C40C)) +#define GPIO_PORTE_AHB_IM_R (*((volatile uint32_t *)0x4005C410)) +#define GPIO_PORTE_AHB_RIS_R (*((volatile uint32_t *)0x4005C414)) +#define GPIO_PORTE_AHB_MIS_R (*((volatile uint32_t *)0x4005C418)) +#define GPIO_PORTE_AHB_ICR_R (*((volatile uint32_t *)0x4005C41C)) +#define GPIO_PORTE_AHB_AFSEL_R (*((volatile uint32_t *)0x4005C420)) +#define GPIO_PORTE_AHB_DR2R_R (*((volatile uint32_t *)0x4005C500)) +#define GPIO_PORTE_AHB_DR4R_R (*((volatile uint32_t *)0x4005C504)) +#define GPIO_PORTE_AHB_DR8R_R (*((volatile uint32_t *)0x4005C508)) +#define GPIO_PORTE_AHB_ODR_R (*((volatile uint32_t *)0x4005C50C)) +#define GPIO_PORTE_AHB_PUR_R (*((volatile uint32_t *)0x4005C510)) +#define GPIO_PORTE_AHB_PDR_R (*((volatile uint32_t *)0x4005C514)) +#define GPIO_PORTE_AHB_SLR_R (*((volatile uint32_t *)0x4005C518)) +#define GPIO_PORTE_AHB_DEN_R (*((volatile uint32_t *)0x4005C51C)) +#define GPIO_PORTE_AHB_LOCK_R (*((volatile uint32_t *)0x4005C520)) +#define GPIO_PORTE_AHB_CR_R (*((volatile uint32_t *)0x4005C524)) +#define GPIO_PORTE_AHB_AMSEL_R (*((volatile uint32_t *)0x4005C528)) +#define GPIO_PORTE_AHB_PCTL_R (*((volatile uint32_t *)0x4005C52C)) +#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530)) +#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534)) + +//***************************************************************************** +// +// GPIO registers (PORTF AHB) +// +//***************************************************************************** +#define GPIO_PORTF_AHB_DATA_BITS_R \ + ((volatile uint32_t *)0x4005D000) +#define GPIO_PORTF_AHB_DATA_R (*((volatile uint32_t *)0x4005D3FC)) +#define GPIO_PORTF_AHB_DIR_R (*((volatile uint32_t *)0x4005D400)) +#define GPIO_PORTF_AHB_IS_R (*((volatile uint32_t *)0x4005D404)) +#define GPIO_PORTF_AHB_IBE_R (*((volatile uint32_t *)0x4005D408)) +#define GPIO_PORTF_AHB_IEV_R (*((volatile uint32_t *)0x4005D40C)) +#define GPIO_PORTF_AHB_IM_R (*((volatile uint32_t *)0x4005D410)) +#define GPIO_PORTF_AHB_RIS_R (*((volatile uint32_t *)0x4005D414)) +#define GPIO_PORTF_AHB_MIS_R (*((volatile uint32_t *)0x4005D418)) +#define GPIO_PORTF_AHB_ICR_R (*((volatile uint32_t *)0x4005D41C)) +#define GPIO_PORTF_AHB_AFSEL_R (*((volatile uint32_t *)0x4005D420)) +#define GPIO_PORTF_AHB_DR2R_R (*((volatile uint32_t *)0x4005D500)) +#define GPIO_PORTF_AHB_DR4R_R (*((volatile uint32_t *)0x4005D504)) +#define GPIO_PORTF_AHB_DR8R_R (*((volatile uint32_t *)0x4005D508)) +#define GPIO_PORTF_AHB_ODR_R (*((volatile uint32_t *)0x4005D50C)) +#define GPIO_PORTF_AHB_PUR_R (*((volatile uint32_t *)0x4005D510)) +#define GPIO_PORTF_AHB_PDR_R (*((volatile uint32_t *)0x4005D514)) +#define GPIO_PORTF_AHB_SLR_R (*((volatile uint32_t *)0x4005D518)) +#define GPIO_PORTF_AHB_DEN_R (*((volatile uint32_t *)0x4005D51C)) +#define GPIO_PORTF_AHB_LOCK_R (*((volatile uint32_t *)0x4005D520)) +#define GPIO_PORTF_AHB_CR_R (*((volatile uint32_t *)0x4005D524)) +#define GPIO_PORTF_AHB_AMSEL_R (*((volatile uint32_t *)0x4005D528)) +#define GPIO_PORTF_AHB_PCTL_R (*((volatile uint32_t *)0x4005D52C)) +#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530)) +#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534)) + +//***************************************************************************** +// +// EEPROM registers (EEPROM) +// +//***************************************************************************** +#define EEPROM_EESIZE_R (*((volatile uint32_t *)0x400AF000)) +#define EEPROM_EEBLOCK_R (*((volatile uint32_t *)0x400AF004)) +#define EEPROM_EEOFFSET_R (*((volatile uint32_t *)0x400AF008)) +#define EEPROM_EERDWR_R (*((volatile uint32_t *)0x400AF010)) +#define EEPROM_EERDWRINC_R (*((volatile uint32_t *)0x400AF014)) +#define EEPROM_EEDONE_R (*((volatile uint32_t *)0x400AF018)) +#define EEPROM_EESUPP_R (*((volatile uint32_t *)0x400AF01C)) +#define EEPROM_EEUNLOCK_R (*((volatile uint32_t *)0x400AF020)) +#define EEPROM_EEPROT_R (*((volatile uint32_t *)0x400AF030)) +#define EEPROM_EEPASS0_R (*((volatile uint32_t *)0x400AF034)) +#define EEPROM_EEPASS1_R (*((volatile uint32_t *)0x400AF038)) +#define EEPROM_EEPASS2_R (*((volatile uint32_t *)0x400AF03C)) +#define EEPROM_EEINT_R (*((volatile uint32_t *)0x400AF040)) +#define EEPROM_EEHIDE_R (*((volatile uint32_t *)0x400AF050)) +#define EEPROM_EEDBGME_R (*((volatile uint32_t *)0x400AF080)) +#define EEPROM_PP_R (*((volatile uint32_t *)0x400AFFC0)) + +//***************************************************************************** +// +// System Exception Module registers (SYSEXC) +// +//***************************************************************************** +#define SYSEXC_RIS_R (*((volatile uint32_t *)0x400F9000)) +#define SYSEXC_IM_R (*((volatile uint32_t *)0x400F9004)) +#define SYSEXC_MIS_R (*((volatile uint32_t *)0x400F9008)) +#define SYSEXC_IC_R (*((volatile uint32_t *)0x400F900C)) + +//***************************************************************************** +// +// Hibernation module registers (HIB) +// +//***************************************************************************** +#define HIB_RTCC_R (*((volatile uint32_t *)0x400FC000)) +#define HIB_RTCM0_R (*((volatile uint32_t *)0x400FC004)) +#define HIB_RTCLD_R (*((volatile uint32_t *)0x400FC00C)) +#define HIB_CTL_R (*((volatile uint32_t *)0x400FC010)) +#define HIB_IM_R (*((volatile uint32_t *)0x400FC014)) +#define HIB_RIS_R (*((volatile uint32_t *)0x400FC018)) +#define HIB_MIS_R (*((volatile uint32_t *)0x400FC01C)) +#define HIB_IC_R (*((volatile uint32_t *)0x400FC020)) +#define HIB_RTCT_R (*((volatile uint32_t *)0x400FC024)) +#define HIB_RTCSS_R (*((volatile uint32_t *)0x400FC028)) +#define HIB_DATA_R (*((volatile uint32_t *)0x400FC030)) + +//***************************************************************************** +// +// FLASH registers (FLASH CTRL) +// +//***************************************************************************** +#define FLASH_FMA_R (*((volatile uint32_t *)0x400FD000)) +#define FLASH_FMD_R (*((volatile uint32_t *)0x400FD004)) +#define FLASH_FMC_R (*((volatile uint32_t *)0x400FD008)) +#define FLASH_FCRIS_R (*((volatile uint32_t *)0x400FD00C)) +#define FLASH_FCIM_R (*((volatile uint32_t *)0x400FD010)) +#define FLASH_FCMISC_R (*((volatile uint32_t *)0x400FD014)) +#define FLASH_FMC2_R (*((volatile uint32_t *)0x400FD020)) +#define FLASH_FWBVAL_R (*((volatile uint32_t *)0x400FD030)) +#define FLASH_FWBN_R (*((volatile uint32_t *)0x400FD100)) +#define FLASH_FSIZE_R (*((volatile uint32_t *)0x400FDFC0)) +#define FLASH_SSIZE_R (*((volatile uint32_t *)0x400FDFC4)) +#define FLASH_ROMSWMAP_R (*((volatile uint32_t *)0x400FDFCC)) +#define FLASH_RMCTL_R (*((volatile uint32_t *)0x400FE0F0)) +#define FLASH_BOOTCFG_R (*((volatile uint32_t *)0x400FE1D0)) +#define FLASH_USERREG0_R (*((volatile uint32_t *)0x400FE1E0)) +#define FLASH_USERREG1_R (*((volatile uint32_t *)0x400FE1E4)) +#define FLASH_USERREG2_R (*((volatile uint32_t *)0x400FE1E8)) +#define FLASH_USERREG3_R (*((volatile uint32_t *)0x400FE1EC)) +#define FLASH_FMPRE0_R (*((volatile uint32_t *)0x400FE200)) +#define FLASH_FMPRE1_R (*((volatile uint32_t *)0x400FE204)) +#define FLASH_FMPRE2_R (*((volatile uint32_t *)0x400FE208)) +#define FLASH_FMPRE3_R (*((volatile uint32_t *)0x400FE20C)) +#define FLASH_FMPPE0_R (*((volatile uint32_t *)0x400FE400)) +#define FLASH_FMPPE1_R (*((volatile uint32_t *)0x400FE404)) +#define FLASH_FMPPE2_R (*((volatile uint32_t *)0x400FE408)) +#define FLASH_FMPPE3_R (*((volatile uint32_t *)0x400FE40C)) + +//***************************************************************************** +// +// System Control registers (SYSCTL) +// +//***************************************************************************** +#define SYSCTL_DID0_R (*((volatile uint32_t *)0x400FE000)) +#define SYSCTL_DID1_R (*((volatile uint32_t *)0x400FE004)) +#define SYSCTL_DC0_R (*((volatile uint32_t *)0x400FE008)) +#define SYSCTL_DC1_R (*((volatile uint32_t *)0x400FE010)) +#define SYSCTL_DC2_R (*((volatile uint32_t *)0x400FE014)) +#define SYSCTL_DC3_R (*((volatile uint32_t *)0x400FE018)) +#define SYSCTL_DC4_R (*((volatile uint32_t *)0x400FE01C)) +#define SYSCTL_DC5_R (*((volatile uint32_t *)0x400FE020)) +#define SYSCTL_DC6_R (*((volatile uint32_t *)0x400FE024)) +#define SYSCTL_DC7_R (*((volatile uint32_t *)0x400FE028)) +#define SYSCTL_DC8_R (*((volatile uint32_t *)0x400FE02C)) +#define SYSCTL_PBORCTL_R (*((volatile uint32_t *)0x400FE030)) +#define SYSCTL_SRCR0_R (*((volatile uint32_t *)0x400FE040)) +#define SYSCTL_SRCR1_R (*((volatile uint32_t *)0x400FE044)) +#define SYSCTL_SRCR2_R (*((volatile uint32_t *)0x400FE048)) +#define SYSCTL_RIS_R (*((volatile uint32_t *)0x400FE050)) +#define SYSCTL_IMC_R (*((volatile uint32_t *)0x400FE054)) +#define SYSCTL_MISC_R (*((volatile uint32_t *)0x400FE058)) +#define SYSCTL_RESC_R (*((volatile uint32_t *)0x400FE05C)) +#define SYSCTL_RCC_R (*((volatile uint32_t *)0x400FE060)) +#define SYSCTL_GPIOHBCTL_R (*((volatile uint32_t *)0x400FE06C)) +#define SYSCTL_RCC2_R (*((volatile uint32_t *)0x400FE070)) +#define SYSCTL_MOSCCTL_R (*((volatile uint32_t *)0x400FE07C)) +#define SYSCTL_RCGC0_R (*((volatile uint32_t *)0x400FE100)) +#define SYSCTL_RCGC1_R (*((volatile uint32_t *)0x400FE104)) +#define SYSCTL_RCGC2_R (*((volatile uint32_t *)0x400FE108)) +#define SYSCTL_SCGC0_R (*((volatile uint32_t *)0x400FE110)) +#define SYSCTL_SCGC1_R (*((volatile uint32_t *)0x400FE114)) +#define SYSCTL_SCGC2_R (*((volatile uint32_t *)0x400FE118)) +#define SYSCTL_DCGC0_R (*((volatile uint32_t *)0x400FE120)) +#define SYSCTL_DCGC1_R (*((volatile uint32_t *)0x400FE124)) +#define SYSCTL_DCGC2_R (*((volatile uint32_t *)0x400FE128)) +#define SYSCTL_DSLPCLKCFG_R (*((volatile uint32_t *)0x400FE144)) +#define SYSCTL_SYSPROP_R (*((volatile uint32_t *)0x400FE14C)) +#define SYSCTL_PIOSCCAL_R (*((volatile uint32_t *)0x400FE150)) +#define SYSCTL_PIOSCSTAT_R (*((volatile uint32_t *)0x400FE154)) +#define SYSCTL_PLLFREQ0_R (*((volatile uint32_t *)0x400FE160)) +#define SYSCTL_PLLFREQ1_R (*((volatile uint32_t *)0x400FE164)) +#define SYSCTL_PLLSTAT_R (*((volatile uint32_t *)0x400FE168)) +#define SYSCTL_SLPPWRCFG_R (*((volatile uint32_t *)0x400FE188)) +#define SYSCTL_DSLPPWRCFG_R (*((volatile uint32_t *)0x400FE18C)) +#define SYSCTL_DC9_R (*((volatile uint32_t *)0x400FE190)) +#define SYSCTL_NVMSTAT_R (*((volatile uint32_t *)0x400FE1A0)) +#define SYSCTL_LDOSPCTL_R (*((volatile uint32_t *)0x400FE1B4)) +#define SYSCTL_LDODPCTL_R (*((volatile uint32_t *)0x400FE1BC)) +#define SYSCTL_PPWD_R (*((volatile uint32_t *)0x400FE300)) +#define SYSCTL_PPTIMER_R (*((volatile uint32_t *)0x400FE304)) +#define SYSCTL_PPGPIO_R (*((volatile uint32_t *)0x400FE308)) +#define SYSCTL_PPDMA_R (*((volatile uint32_t *)0x400FE30C)) +#define SYSCTL_PPHIB_R (*((volatile uint32_t *)0x400FE314)) +#define SYSCTL_PPUART_R (*((volatile uint32_t *)0x400FE318)) +#define SYSCTL_PPSSI_R (*((volatile uint32_t *)0x400FE31C)) +#define SYSCTL_PPI2C_R (*((volatile uint32_t *)0x400FE320)) +#define SYSCTL_PPUSB_R (*((volatile uint32_t *)0x400FE328)) +#define SYSCTL_PPCAN_R (*((volatile uint32_t *)0x400FE334)) +#define SYSCTL_PPADC_R (*((volatile uint32_t *)0x400FE338)) +#define SYSCTL_PPACMP_R (*((volatile uint32_t *)0x400FE33C)) +#define SYSCTL_PPPWM_R (*((volatile uint32_t *)0x400FE340)) +#define SYSCTL_PPQEI_R (*((volatile uint32_t *)0x400FE344)) +#define SYSCTL_PPEEPROM_R (*((volatile uint32_t *)0x400FE358)) +#define SYSCTL_PPWTIMER_R (*((volatile uint32_t *)0x400FE35C)) +#define SYSCTL_SRWD_R (*((volatile uint32_t *)0x400FE500)) +#define SYSCTL_SRTIMER_R (*((volatile uint32_t *)0x400FE504)) +#define SYSCTL_SRGPIO_R (*((volatile uint32_t *)0x400FE508)) +#define SYSCTL_SRDMA_R (*((volatile uint32_t *)0x400FE50C)) +#define SYSCTL_SRHIB_R (*((volatile uint32_t *)0x400FE514)) +#define SYSCTL_SRUART_R (*((volatile uint32_t *)0x400FE518)) +#define SYSCTL_SRSSI_R (*((volatile uint32_t *)0x400FE51C)) +#define SYSCTL_SRI2C_R (*((volatile uint32_t *)0x400FE520)) +#define SYSCTL_SRUSB_R (*((volatile uint32_t *)0x400FE528)) +#define SYSCTL_SRCAN_R (*((volatile uint32_t *)0x400FE534)) +#define SYSCTL_SRADC_R (*((volatile uint32_t *)0x400FE538)) +#define SYSCTL_SRACMP_R (*((volatile uint32_t *)0x400FE53C)) +#define SYSCTL_SRPWM_R (*((volatile uint32_t *)0x400FE540)) +#define SYSCTL_SRQEI_R (*((volatile uint32_t *)0x400FE544)) +#define SYSCTL_SREEPROM_R (*((volatile uint32_t *)0x400FE558)) +#define SYSCTL_SRWTIMER_R (*((volatile uint32_t *)0x400FE55C)) +#define SYSCTL_RCGCWD_R (*((volatile uint32_t *)0x400FE600)) +#define SYSCTL_RCGCTIMER_R (*((volatile uint32_t *)0x400FE604)) +#define SYSCTL_RCGCGPIO_R (*((volatile uint32_t *)0x400FE608)) +#define SYSCTL_RCGCDMA_R (*((volatile uint32_t *)0x400FE60C)) +#define SYSCTL_RCGCHIB_R (*((volatile uint32_t *)0x400FE614)) +#define SYSCTL_RCGCUART_R (*((volatile uint32_t *)0x400FE618)) +#define SYSCTL_RCGCSSI_R (*((volatile uint32_t *)0x400FE61C)) +#define SYSCTL_RCGCI2C_R (*((volatile uint32_t *)0x400FE620)) +#define SYSCTL_RCGCUSB_R (*((volatile uint32_t *)0x400FE628)) +#define SYSCTL_RCGCCAN_R (*((volatile uint32_t *)0x400FE634)) +#define SYSCTL_RCGCADC_R (*((volatile uint32_t *)0x400FE638)) +#define SYSCTL_RCGCACMP_R (*((volatile uint32_t *)0x400FE63C)) +#define SYSCTL_RCGCPWM_R (*((volatile uint32_t *)0x400FE640)) +#define SYSCTL_RCGCQEI_R (*((volatile uint32_t *)0x400FE644)) +#define SYSCTL_RCGCEEPROM_R (*((volatile uint32_t *)0x400FE658)) +#define SYSCTL_RCGCWTIMER_R (*((volatile uint32_t *)0x400FE65C)) +#define SYSCTL_SCGCWD_R (*((volatile uint32_t *)0x400FE700)) +#define SYSCTL_SCGCTIMER_R (*((volatile uint32_t *)0x400FE704)) +#define SYSCTL_SCGCGPIO_R (*((volatile uint32_t *)0x400FE708)) +#define SYSCTL_SCGCDMA_R (*((volatile uint32_t *)0x400FE70C)) +#define SYSCTL_SCGCHIB_R (*((volatile uint32_t *)0x400FE714)) +#define SYSCTL_SCGCUART_R (*((volatile uint32_t *)0x400FE718)) +#define SYSCTL_SCGCSSI_R (*((volatile uint32_t *)0x400FE71C)) +#define SYSCTL_SCGCI2C_R (*((volatile uint32_t *)0x400FE720)) +#define SYSCTL_SCGCUSB_R (*((volatile uint32_t *)0x400FE728)) +#define SYSCTL_SCGCCAN_R (*((volatile uint32_t *)0x400FE734)) +#define SYSCTL_SCGCADC_R (*((volatile uint32_t *)0x400FE738)) +#define SYSCTL_SCGCACMP_R (*((volatile uint32_t *)0x400FE73C)) +#define SYSCTL_SCGCPWM_R (*((volatile uint32_t *)0x400FE740)) +#define SYSCTL_SCGCQEI_R (*((volatile uint32_t *)0x400FE744)) +#define SYSCTL_SCGCEEPROM_R (*((volatile uint32_t *)0x400FE758)) +#define SYSCTL_SCGCWTIMER_R (*((volatile uint32_t *)0x400FE75C)) +#define SYSCTL_DCGCWD_R (*((volatile uint32_t *)0x400FE800)) +#define SYSCTL_DCGCTIMER_R (*((volatile uint32_t *)0x400FE804)) +#define SYSCTL_DCGCGPIO_R (*((volatile uint32_t *)0x400FE808)) +#define SYSCTL_DCGCDMA_R (*((volatile uint32_t *)0x400FE80C)) +#define SYSCTL_DCGCHIB_R (*((volatile uint32_t *)0x400FE814)) +#define SYSCTL_DCGCUART_R (*((volatile uint32_t *)0x400FE818)) +#define SYSCTL_DCGCSSI_R (*((volatile uint32_t *)0x400FE81C)) +#define SYSCTL_DCGCI2C_R (*((volatile uint32_t *)0x400FE820)) +#define SYSCTL_DCGCUSB_R (*((volatile uint32_t *)0x400FE828)) +#define SYSCTL_DCGCCAN_R (*((volatile uint32_t *)0x400FE834)) +#define SYSCTL_DCGCADC_R (*((volatile uint32_t *)0x400FE838)) +#define SYSCTL_DCGCACMP_R (*((volatile uint32_t *)0x400FE83C)) +#define SYSCTL_DCGCPWM_R (*((volatile uint32_t *)0x400FE840)) +#define SYSCTL_DCGCQEI_R (*((volatile uint32_t *)0x400FE844)) +#define SYSCTL_DCGCEEPROM_R (*((volatile uint32_t *)0x400FE858)) +#define SYSCTL_DCGCWTIMER_R (*((volatile uint32_t *)0x400FE85C)) +#define SYSCTL_PRWD_R (*((volatile uint32_t *)0x400FEA00)) +#define SYSCTL_PRTIMER_R (*((volatile uint32_t *)0x400FEA04)) +#define SYSCTL_PRGPIO_R (*((volatile uint32_t *)0x400FEA08)) +#define SYSCTL_PRDMA_R (*((volatile uint32_t *)0x400FEA0C)) +#define SYSCTL_PRHIB_R (*((volatile uint32_t *)0x400FEA14)) +#define SYSCTL_PRUART_R (*((volatile uint32_t *)0x400FEA18)) +#define SYSCTL_PRSSI_R (*((volatile uint32_t *)0x400FEA1C)) +#define SYSCTL_PRI2C_R (*((volatile uint32_t *)0x400FEA20)) +#define SYSCTL_PRUSB_R (*((volatile uint32_t *)0x400FEA28)) +#define SYSCTL_PRCAN_R (*((volatile uint32_t *)0x400FEA34)) +#define SYSCTL_PRADC_R (*((volatile uint32_t *)0x400FEA38)) +#define SYSCTL_PRACMP_R (*((volatile uint32_t *)0x400FEA3C)) +#define SYSCTL_PRPWM_R (*((volatile uint32_t *)0x400FEA40)) +#define SYSCTL_PRQEI_R (*((volatile uint32_t *)0x400FEA44)) +#define SYSCTL_PREEPROM_R (*((volatile uint32_t *)0x400FEA58)) +#define SYSCTL_PRWTIMER_R (*((volatile uint32_t *)0x400FEA5C)) + +//***************************************************************************** +// +// Micro Direct Memory Access registers (UDMA) +// +//***************************************************************************** +#define UDMA_STAT_R (*((volatile uint32_t *)0x400FF000)) +#define UDMA_CFG_R (*((volatile uint32_t *)0x400FF004)) +#define UDMA_CTLBASE_R (*((volatile uint32_t *)0x400FF008)) +#define UDMA_ALTBASE_R (*((volatile uint32_t *)0x400FF00C)) +#define UDMA_WAITSTAT_R (*((volatile uint32_t *)0x400FF010)) +#define UDMA_SWREQ_R (*((volatile uint32_t *)0x400FF014)) +#define UDMA_USEBURSTSET_R (*((volatile uint32_t *)0x400FF018)) +#define UDMA_USEBURSTCLR_R (*((volatile uint32_t *)0x400FF01C)) +#define UDMA_REQMASKSET_R (*((volatile uint32_t *)0x400FF020)) +#define UDMA_REQMASKCLR_R (*((volatile uint32_t *)0x400FF024)) +#define UDMA_ENASET_R (*((volatile uint32_t *)0x400FF028)) +#define UDMA_ENACLR_R (*((volatile uint32_t *)0x400FF02C)) +#define UDMA_ALTSET_R (*((volatile uint32_t *)0x400FF030)) +#define UDMA_ALTCLR_R (*((volatile uint32_t *)0x400FF034)) +#define UDMA_PRIOSET_R (*((volatile uint32_t *)0x400FF038)) +#define UDMA_PRIOCLR_R (*((volatile uint32_t *)0x400FF03C)) +#define UDMA_ERRCLR_R (*((volatile uint32_t *)0x400FF04C)) +#define UDMA_CHASGN_R (*((volatile uint32_t *)0x400FF500)) +#define UDMA_CHIS_R (*((volatile uint32_t *)0x400FF504)) +#define UDMA_CHMAP0_R (*((volatile uint32_t *)0x400FF510)) +#define UDMA_CHMAP1_R (*((volatile uint32_t *)0x400FF514)) +#define UDMA_CHMAP2_R (*((volatile uint32_t *)0x400FF518)) +#define UDMA_CHMAP3_R (*((volatile uint32_t *)0x400FF51C)) + +//***************************************************************************** +// +// Micro Direct Memory Access (uDMA) offsets (UDMA) +// +//***************************************************************************** +#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End + // Pointer +#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address + // End Pointer +#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word + +//***************************************************************************** +// +// NVIC registers (NVIC) +// +//***************************************************************************** +#define NVIC_ACTLR_R (*((volatile uint32_t *)0xE000E008)) +#define NVIC_ST_CTRL_R (*((volatile uint32_t *)0xE000E010)) +#define NVIC_ST_RELOAD_R (*((volatile uint32_t *)0xE000E014)) +#define NVIC_ST_CURRENT_R (*((volatile uint32_t *)0xE000E018)) +#define NVIC_EN0_R (*((volatile uint32_t *)0xE000E100)) +#define NVIC_EN1_R (*((volatile uint32_t *)0xE000E104)) +#define NVIC_EN2_R (*((volatile uint32_t *)0xE000E108)) +#define NVIC_EN3_R (*((volatile uint32_t *)0xE000E10C)) +#define NVIC_EN4_R (*((volatile uint32_t *)0xE000E110)) +#define NVIC_DIS0_R (*((volatile uint32_t *)0xE000E180)) +#define NVIC_DIS1_R (*((volatile uint32_t *)0xE000E184)) +#define NVIC_DIS2_R (*((volatile uint32_t *)0xE000E188)) +#define NVIC_DIS3_R (*((volatile uint32_t *)0xE000E18C)) +#define NVIC_DIS4_R (*((volatile uint32_t *)0xE000E190)) +#define NVIC_PEND0_R (*((volatile uint32_t *)0xE000E200)) +#define NVIC_PEND1_R (*((volatile uint32_t *)0xE000E204)) +#define NVIC_PEND2_R (*((volatile uint32_t *)0xE000E208)) +#define NVIC_PEND3_R (*((volatile uint32_t *)0xE000E20C)) +#define NVIC_PEND4_R (*((volatile uint32_t *)0xE000E210)) +#define NVIC_UNPEND0_R (*((volatile uint32_t *)0xE000E280)) +#define NVIC_UNPEND1_R (*((volatile uint32_t *)0xE000E284)) +#define NVIC_UNPEND2_R (*((volatile uint32_t *)0xE000E288)) +#define NVIC_UNPEND3_R (*((volatile uint32_t *)0xE000E28C)) +#define NVIC_UNPEND4_R (*((volatile uint32_t *)0xE000E290)) +#define NVIC_ACTIVE0_R (*((volatile uint32_t *)0xE000E300)) +#define NVIC_ACTIVE1_R (*((volatile uint32_t *)0xE000E304)) +#define NVIC_ACTIVE2_R (*((volatile uint32_t *)0xE000E308)) +#define NVIC_ACTIVE3_R (*((volatile uint32_t *)0xE000E30C)) +#define NVIC_ACTIVE4_R (*((volatile uint32_t *)0xE000E310)) +#define NVIC_PRI0_R (*((volatile uint32_t *)0xE000E400)) +#define NVIC_PRI1_R (*((volatile uint32_t *)0xE000E404)) +#define NVIC_PRI2_R (*((volatile uint32_t *)0xE000E408)) +#define NVIC_PRI3_R (*((volatile uint32_t *)0xE000E40C)) +#define NVIC_PRI4_R (*((volatile uint32_t *)0xE000E410)) +#define NVIC_PRI5_R (*((volatile uint32_t *)0xE000E414)) +#define NVIC_PRI6_R (*((volatile uint32_t *)0xE000E418)) +#define NVIC_PRI7_R (*((volatile uint32_t *)0xE000E41C)) +#define NVIC_PRI8_R (*((volatile uint32_t *)0xE000E420)) +#define NVIC_PRI9_R (*((volatile uint32_t *)0xE000E424)) +#define NVIC_PRI10_R (*((volatile uint32_t *)0xE000E428)) +#define NVIC_PRI11_R (*((volatile uint32_t *)0xE000E42C)) +#define NVIC_PRI12_R (*((volatile uint32_t *)0xE000E430)) +#define NVIC_PRI13_R (*((volatile uint32_t *)0xE000E434)) +#define NVIC_PRI14_R (*((volatile uint32_t *)0xE000E438)) +#define NVIC_PRI15_R (*((volatile uint32_t *)0xE000E43C)) +#define NVIC_PRI16_R (*((volatile uint32_t *)0xE000E440)) +#define NVIC_PRI17_R (*((volatile uint32_t *)0xE000E444)) +#define NVIC_PRI18_R (*((volatile uint32_t *)0xE000E448)) +#define NVIC_PRI19_R (*((volatile uint32_t *)0xE000E44C)) +#define NVIC_PRI20_R (*((volatile uint32_t *)0xE000E450)) +#define NVIC_PRI21_R (*((volatile uint32_t *)0xE000E454)) +#define NVIC_PRI22_R (*((volatile uint32_t *)0xE000E458)) +#define NVIC_PRI23_R (*((volatile uint32_t *)0xE000E45C)) +#define NVIC_PRI24_R (*((volatile uint32_t *)0xE000E460)) +#define NVIC_PRI25_R (*((volatile uint32_t *)0xE000E464)) +#define NVIC_PRI26_R (*((volatile uint32_t *)0xE000E468)) +#define NVIC_PRI27_R (*((volatile uint32_t *)0xE000E46C)) +#define NVIC_PRI28_R (*((volatile uint32_t *)0xE000E470)) +#define NVIC_PRI29_R (*((volatile uint32_t *)0xE000E474)) +#define NVIC_PRI30_R (*((volatile uint32_t *)0xE000E478)) +#define NVIC_PRI31_R (*((volatile uint32_t *)0xE000E47C)) +#define NVIC_PRI32_R (*((volatile uint32_t *)0xE000E480)) +#define NVIC_PRI33_R (*((volatile uint32_t *)0xE000E484)) +#define NVIC_PRI34_R (*((volatile uint32_t *)0xE000E488)) +#define NVIC_CPUID_R (*((volatile uint32_t *)0xE000ED00)) +#define NVIC_INT_CTRL_R (*((volatile uint32_t *)0xE000ED04)) +#define NVIC_VTABLE_R (*((volatile uint32_t *)0xE000ED08)) +#define NVIC_APINT_R (*((volatile uint32_t *)0xE000ED0C)) +#define NVIC_SYS_CTRL_R (*((volatile uint32_t *)0xE000ED10)) +#define NVIC_CFG_CTRL_R (*((volatile uint32_t *)0xE000ED14)) +#define NVIC_SYS_PRI1_R (*((volatile uint32_t *)0xE000ED18)) +#define NVIC_SYS_PRI2_R (*((volatile uint32_t *)0xE000ED1C)) +#define NVIC_SYS_PRI3_R (*((volatile uint32_t *)0xE000ED20)) +#define NVIC_SYS_HND_CTRL_R (*((volatile uint32_t *)0xE000ED24)) +#define NVIC_FAULT_STAT_R (*((volatile uint32_t *)0xE000ED28)) +#define NVIC_HFAULT_STAT_R (*((volatile uint32_t *)0xE000ED2C)) +#define NVIC_DEBUG_STAT_R (*((volatile uint32_t *)0xE000ED30)) +#define NVIC_MM_ADDR_R (*((volatile uint32_t *)0xE000ED34)) +#define NVIC_FAULT_ADDR_R (*((volatile uint32_t *)0xE000ED38)) +#define NVIC_CPAC_R (*((volatile uint32_t *)0xE000ED88)) +#define NVIC_MPU_TYPE_R (*((volatile uint32_t *)0xE000ED90)) +#define NVIC_MPU_CTRL_R (*((volatile uint32_t *)0xE000ED94)) +#define NVIC_MPU_NUMBER_R (*((volatile uint32_t *)0xE000ED98)) +#define NVIC_MPU_BASE_R (*((volatile uint32_t *)0xE000ED9C)) +#define NVIC_MPU_ATTR_R (*((volatile uint32_t *)0xE000EDA0)) +#define NVIC_MPU_BASE1_R (*((volatile uint32_t *)0xE000EDA4)) +#define NVIC_MPU_ATTR1_R (*((volatile uint32_t *)0xE000EDA8)) +#define NVIC_MPU_BASE2_R (*((volatile uint32_t *)0xE000EDAC)) +#define NVIC_MPU_ATTR2_R (*((volatile uint32_t *)0xE000EDB0)) +#define NVIC_MPU_BASE3_R (*((volatile uint32_t *)0xE000EDB4)) +#define NVIC_MPU_ATTR3_R (*((volatile uint32_t *)0xE000EDB8)) +#define NVIC_DBG_CTRL_R (*((volatile uint32_t *)0xE000EDF0)) +#define NVIC_DBG_XFER_R (*((volatile uint32_t *)0xE000EDF4)) +#define NVIC_DBG_DATA_R (*((volatile uint32_t *)0xE000EDF8)) +#define NVIC_DBG_INT_R (*((volatile uint32_t *)0xE000EDFC)) +#define NVIC_SW_TRIG_R (*((volatile uint32_t *)0xE000EF00)) +#define NVIC_FPCC_R (*((volatile uint32_t *)0xE000EF34)) +#define NVIC_FPCA_R (*((volatile uint32_t *)0xE000EF38)) +#define NVIC_FPDSC_R (*((volatile uint32_t *)0xE000EF3C)) + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//***************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//***************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//***************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//***************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//***************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//***************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//***************************************************************************** +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//***************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_IM register. +// +//***************************************************************************** +#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable +#define GPIO_IM_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_RIS register. +// +//***************************************************************************** +#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status +#define GPIO_RIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_MIS register. +// +//***************************************************************************** +#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status +#define GPIO_MIS_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_ICR register. +// +//***************************************************************************** +#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear +#define GPIO_ICR_GPIO_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_LOCK register. +// +//***************************************************************************** +#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock +#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked + // and may be modified +#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked + // and may not be modified +#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port A. +// +//***************************************************************************** +#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 Mask +#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7 +#define GPIO_PCTL_PA7_M1PWM3 0x50000000 // M1PWM3 on PA7 +#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 Mask +#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6 +#define GPIO_PCTL_PA6_M1PWM2 0x05000000 // M1PWM2 on PA6 +#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 Mask +#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5 +#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 Mask +#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4 +#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 Mask +#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3 +#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 Mask +#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2 +#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 Mask +#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1 +#define GPIO_PCTL_PA1_CAN1TX 0x00000080 // CAN1TX on PA1 +#define GPIO_PCTL_PA0_M 0x0000000F // PA0 Mask +#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0 +#define GPIO_PCTL_PA0_CAN1RX 0x00000008 // CAN1RX on PA0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port B. +// +//***************************************************************************** +#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 Mask +#define GPIO_PCTL_PB7_SSI2TX 0x20000000 // SSI2TX on PB7 +#define GPIO_PCTL_PB7_M0PWM1 0x40000000 // M0PWM1 on PB7 +#define GPIO_PCTL_PB7_T0CCP1 0x70000000 // T0CCP1 on PB7 +#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 Mask +#define GPIO_PCTL_PB6_SSI2RX 0x02000000 // SSI2RX on PB6 +#define GPIO_PCTL_PB6_M0PWM0 0x04000000 // M0PWM0 on PB6 +#define GPIO_PCTL_PB6_T0CCP0 0x07000000 // T0CCP0 on PB6 +#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 Mask +#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5 +#define GPIO_PCTL_PB5_M0PWM3 0x00400000 // M0PWM3 on PB5 +#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5 +#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5 +#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 Mask +#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4 +#define GPIO_PCTL_PB4_M0PWM2 0x00040000 // M0PWM2 on PB4 +#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4 +#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4 +#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 Mask +#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3 +#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3 +#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 Mask +#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2 +#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2 +#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 Mask +#define GPIO_PCTL_PB1_USB0VBUS 0x00000000 // USB0VBUS on PB1 +#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1 +#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1 +#define GPIO_PCTL_PB0_M 0x0000000F // PB0 Mask +#define GPIO_PCTL_PB0_USB0ID 0x00000000 // USB0ID on PB0 +#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0 +#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port C. +// +//***************************************************************************** +#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 Mask +#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7 +#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7 +#define GPIO_PCTL_PC7_USB0PFLT 0x80000000 // USB0PFLT on PC7 +#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 Mask +#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6 +#define GPIO_PCTL_PC6_PHB1 0x06000000 // PHB1 on PC6 +#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6 +#define GPIO_PCTL_PC6_USB0EPEN 0x08000000 // USB0EPEN on PC6 +#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 Mask +#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5 +#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5 +#define GPIO_PCTL_PC5_M0PWM7 0x00400000 // M0PWM7 on PC5 +#define GPIO_PCTL_PC5_PHA1 0x00600000 // PHA1 on PC5 +#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5 +#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5 +#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 Mask +#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4 +#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4 +#define GPIO_PCTL_PC4_M0PWM6 0x00040000 // M0PWM6 on PC4 +#define GPIO_PCTL_PC4_IDX1 0x00060000 // IDX1 on PC4 +#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4 +#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4 +#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 Mask +#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3 +#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3 +#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 Mask +#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2 +#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2 +#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 Mask +#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1 +#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1 +#define GPIO_PCTL_PC0_M 0x0000000F // PC0 Mask +#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0 +#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port D. +// +//***************************************************************************** +#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 Mask +#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7 +#define GPIO_PCTL_PD7_PHB0 0x60000000 // PHB0 on PD7 +#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7 +#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7 +#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 Mask +#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6 +#define GPIO_PCTL_PD6_M0FAULT0 0x04000000 // M0FAULT0 on PD6 +#define GPIO_PCTL_PD6_PHA0 0x06000000 // PHA0 on PD6 +#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6 +#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 Mask +#define GPIO_PCTL_PD5_USB0DP 0x00000000 // USB0DP on PD5 +#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5 +#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5 +#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 Mask +#define GPIO_PCTL_PD4_USB0DM 0x00000000 // USB0DM on PD4 +#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4 +#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4 +#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 Mask +#define GPIO_PCTL_PD3_AIN4 0x00000000 // AIN4 on PD3 +#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3 +#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3 +#define GPIO_PCTL_PD3_IDX0 0x00006000 // IDX0 on PD3 +#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3 +#define GPIO_PCTL_PD3_USB0PFLT 0x00008000 // USB0PFLT on PD3 +#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 Mask +#define GPIO_PCTL_PD2_AIN5 0x00000000 // AIN5 on PD2 +#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2 +#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2 +#define GPIO_PCTL_PD2_M0FAULT0 0x00000400 // M0FAULT0 on PD2 +#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2 +#define GPIO_PCTL_PD2_USB0EPEN 0x00000800 // USB0EPEN on PD2 +#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 Mask +#define GPIO_PCTL_PD1_AIN6 0x00000000 // AIN6 on PD1 +#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1 +#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1 +#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1 +#define GPIO_PCTL_PD1_M0PWM7 0x00000040 // M0PWM7 on PD1 +#define GPIO_PCTL_PD1_M1PWM1 0x00000050 // M1PWM1 on PD1 +#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1 +#define GPIO_PCTL_PD0_M 0x0000000F // PD0 Mask +#define GPIO_PCTL_PD0_AIN7 0x00000000 // AIN7 on PD0 +#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0 +#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0 +#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0 +#define GPIO_PCTL_PD0_M0PWM6 0x00000004 // M0PWM6 on PD0 +#define GPIO_PCTL_PD0_M1PWM0 0x00000005 // M1PWM0 on PD0 +#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port E. +// +//***************************************************************************** +#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 Mask +#define GPIO_PCTL_PE5_AIN8 0x00000000 // AIN8 on PE5 +#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5 +#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5 +#define GPIO_PCTL_PE5_M0PWM5 0x00400000 // M0PWM5 on PE5 +#define GPIO_PCTL_PE5_M1PWM3 0x00500000 // M1PWM3 on PE5 +#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5 +#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 Mask +#define GPIO_PCTL_PE4_AIN9 0x00000000 // AIN9 on PE4 +#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4 +#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4 +#define GPIO_PCTL_PE4_M0PWM4 0x00040000 // M0PWM4 on PE4 +#define GPIO_PCTL_PE4_M1PWM2 0x00050000 // M1PWM2 on PE4 +#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4 +#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 Mask +#define GPIO_PCTL_PE3_AIN0 0x00000000 // AIN0 on PE3 +#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 Mask +#define GPIO_PCTL_PE2_AIN1 0x00000000 // AIN1 on PE2 +#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 Mask +#define GPIO_PCTL_PE1_AIN2 0x00000000 // AIN2 on PE1 +#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1 +#define GPIO_PCTL_PE0_M 0x0000000F // PE0 Mask +#define GPIO_PCTL_PE0_AIN3 0x00000000 // AIN3 on PE0 +#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the GPIO_PCTL register for +// port F. +// +//***************************************************************************** +#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 Mask +#define GPIO_PCTL_PF4_M1FAULT0 0x00050000 // M1FAULT0 on PF4 +#define GPIO_PCTL_PF4_IDX0 0x00060000 // IDX0 on PF4 +#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4 +#define GPIO_PCTL_PF4_USB0EPEN 0x00080000 // USB0EPEN on PF4 +#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 Mask +#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3 +#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3 +#define GPIO_PCTL_PF3_M1PWM7 0x00005000 // M1PWM7 on PF3 +#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3 +#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3 +#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 Mask +#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2 +#define GPIO_PCTL_PF2_M0FAULT0 0x00000400 // M0FAULT0 on PF2 +#define GPIO_PCTL_PF2_M1PWM6 0x00000500 // M1PWM6 on PF2 +#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2 +#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2 +#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 Mask +#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1 +#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1 +#define GPIO_PCTL_PF1_M1PWM5 0x00000050 // M1PWM5 on PF1 +#define GPIO_PCTL_PF1_PHB0 0x00000060 // PHB0 on PF1 +#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1 +#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1 +#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1 +#define GPIO_PCTL_PF0_M 0x0000000F // PF0 Mask +#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0 +#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0 +#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0 +#define GPIO_PCTL_PF0_M1PWM4 0x00000005 // M1PWM4 on PF0 +#define GPIO_PCTL_PF0_PHA0 0x00000006 // PHA0 on PF0 +#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0 +#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0 +#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR0 register. +// +//***************************************************************************** +#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate +#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase +#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity +#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select +#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format +#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format +#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format +#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select +#define SSI_CR0_DSS_4 0x00000003 // 4-bit data +#define SSI_CR0_DSS_5 0x00000004 // 5-bit data +#define SSI_CR0_DSS_6 0x00000005 // 6-bit data +#define SSI_CR0_DSS_7 0x00000006 // 7-bit data +#define SSI_CR0_DSS_8 0x00000007 // 8-bit data +#define SSI_CR0_DSS_9 0x00000008 // 9-bit data +#define SSI_CR0_DSS_10 0x00000009 // 10-bit data +#define SSI_CR0_DSS_11 0x0000000A // 11-bit data +#define SSI_CR0_DSS_12 0x0000000B // 12-bit data +#define SSI_CR0_DSS_13 0x0000000C // 13-bit data +#define SSI_CR0_DSS_14 0x0000000D // 14-bit data +#define SSI_CR0_DSS_15 0x0000000E // 15-bit data +#define SSI_CR0_DSS_16 0x0000000F // 16-bit data +#define SSI_CR0_SCR_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CR1 register. +// +//***************************************************************************** +#define SSI_CR1_EOT 0x00000010 // End of Transmission +#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select +#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port + // Enable +#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DR register. +// +//***************************************************************************** +#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data +#define SSI_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_SR register. +// +//***************************************************************************** +#define SSI_SR_BSY 0x00000010 // SSI Busy Bit +#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full +#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty +#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full +#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CPSR register. +// +//***************************************************************************** +#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor +#define SSI_CPSR_CPSDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_IM register. +// +//***************************************************************************** +#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask +#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask +#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt + // Mask +#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_RIS register. +// +//***************************************************************************** +#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt + // Status +#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt + // Status +#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw + // Interrupt Status +#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_MIS register. +// +//***************************************************************************** +#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked + // Interrupt Status +#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked + // Interrupt Status +#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked + // Interrupt Status +#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_ICR register. +// +//***************************************************************************** +#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt + // Clear +#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_DMACTL register. +// +//***************************************************************************** +#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the SSI_O_CC register. +// +//***************************************************************************** +#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source +#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock + // source and divisor factor) +#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//***************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//***************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//***************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//***************************************************************************** +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_CTS 0x00000001 // Clear To Send + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//***************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//***************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//***************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//***************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//***************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//***************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full +#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full +#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) +#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full +#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full +#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full +#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) +#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full +#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//***************************************************************************** +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//***************************************************************************** +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//***************************************************************************** +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//***************************************************************************** +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//***************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITADDR +// register. +// +//***************************************************************************** +#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode +#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode +#define UART_9BITADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_9BITAMASK +// register. +// +//***************************************************************************** +#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode +#define UART_9BITAMASK_MASK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//***************************************************************************** +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support + +//***************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//***************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source +#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock + // source and divisor factor) +#define UART_CC_CS_PIOSC 0x00000005 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//***************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_RS 0x00000001 // Receive not send +#define I2C_MSA_SA_S 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//***************************************************************************** +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_HS 0x00000010 // High-Speed Enable +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_STOP 0x00000004 // Generate STOP +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_START 0x00000002 // Generate START +#define I2C_MCS_RUN 0x00000001 // I2C Master Enable +#define I2C_MCS_BUSY 0x00000001 // I2C Busy + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//***************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data + // transferred during a transaction +#define I2C_MDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//***************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // Timer Period +#define I2C_MTPR_TPR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//***************************************************************************** +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//***************************************************************************** +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//***************************************************************************** +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//***************************************************************************** +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//***************************************************************************** +#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//***************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//***************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR2 register. +// +//***************************************************************************** +#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width +#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass +#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock +#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks +#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks +#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks +#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks +#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks +#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//***************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//***************************************************************************** +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +#define I2C_SCSR_RREQ 0x00000001 // Receive Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//***************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//***************************************************************************** +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//***************************************************************************** +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//***************************************************************************** +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//***************************************************************************** +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//***************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//***************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//***************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//***************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_CTL register. +// +//***************************************************************************** +#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3 +#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2 +#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1 +#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_SYNC register. +// +//***************************************************************************** +#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter +#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter +#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter +#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENABLE register. +// +//***************************************************************************** +#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable +#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable +#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable +#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable +#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable +#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable +#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable +#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INVERT register. +// +//***************************************************************************** +#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal +#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal +#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal +#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal +#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal +#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal +#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal +#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULT register. +// +//***************************************************************************** +#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault +#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault +#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault +#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault +#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault +#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault +#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault +#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_INTEN register. +// +//***************************************************************************** +#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1 +#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0 +#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable +#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable +#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable +#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_RIS register. +// +//***************************************************************************** +#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1 +#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0 +#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted +#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted +#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted +#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ISC register. +// +//***************************************************************************** +#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted +#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted +#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status +#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status +#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status +#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_STATUS register. +// +//***************************************************************************** +#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status +#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_FAULTVAL register. +// +//***************************************************************************** +#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value +#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value +#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value +#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value +#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value +#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value +#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value +#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_ENUPD register. +// +//***************************************************************************** +#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode +#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized +#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized +#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode +#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized +#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized +#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode +#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized +#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized +#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode +#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized +#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized +#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode +#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized +#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized +#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode +#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized +#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized +#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode +#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized +#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized +#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode +#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate +#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized +#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CTL register. +// +//***************************************************************************** +#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_0_CTL_MODE 0x00000002 // Counter Mode +#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_INTEN register. +// +//***************************************************************************** +#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_RIS register. +// +//***************************************************************************** +#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_ISC register. +// +//***************************************************************************** +#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_LOAD register. +// +//***************************************************************************** +#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_0_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_COUNT register. +// +//***************************************************************************** +#define PWM_0_COUNT_M 0x0000FFFF // Counter Value +#define PWM_0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPA register. +// +//***************************************************************************** +#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value +#define PWM_0_CMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_CMPB register. +// +//***************************************************************************** +#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value +#define PWM_0_CMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENA register. +// +//***************************************************************************** +#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_0_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_0_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_0_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_0_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_GENB register. +// +//***************************************************************************** +#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_0_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_0_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_0_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_0_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_0_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_0_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_0_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_0_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBCTL register. +// +//***************************************************************************** +#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBRISE register. +// +//***************************************************************************** +#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay +#define PWM_0_DBRISE_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_DBFALL register. +// +//***************************************************************************** +#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay +#define PWM_0_DBFALL_DELAY_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period +#define PWM_0_MINFLTPER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CTL register. +// +//***************************************************************************** +#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_1_CTL_MODE 0x00000002 // Counter Mode +#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_INTEN register. +// +//***************************************************************************** +#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_RIS register. +// +//***************************************************************************** +#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_ISC register. +// +//***************************************************************************** +#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_LOAD register. +// +//***************************************************************************** +#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_1_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_COUNT register. +// +//***************************************************************************** +#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_1_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPA register. +// +//***************************************************************************** +#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_1_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_CMPB register. +// +//***************************************************************************** +#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_1_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENA register. +// +//***************************************************************************** +#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_1_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_1_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_1_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_1_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_GENB register. +// +//***************************************************************************** +#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_1_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_1_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_1_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_1_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_1_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_1_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_1_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_1_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBCTL register. +// +//***************************************************************************** +#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBRISE register. +// +//***************************************************************************** +#define PWM_1_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_1_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_DBFALL register. +// +//***************************************************************************** +#define PWM_1_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_1_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_1_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CTL register. +// +//***************************************************************************** +#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_2_CTL_MODE 0x00000002 // Counter Mode +#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_INTEN register. +// +//***************************************************************************** +#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_RIS register. +// +//***************************************************************************** +#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_ISC register. +// +//***************************************************************************** +#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_LOAD register. +// +//***************************************************************************** +#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_2_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_COUNT register. +// +//***************************************************************************** +#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_2_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPA register. +// +//***************************************************************************** +#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_2_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_CMPB register. +// +//***************************************************************************** +#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_2_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENA register. +// +//***************************************************************************** +#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_2_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_2_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_2_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_2_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_GENB register. +// +//***************************************************************************** +#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_2_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_2_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_2_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_2_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_2_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_2_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_2_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_2_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBCTL register. +// +//***************************************************************************** +#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBRISE register. +// +//***************************************************************************** +#define PWM_2_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_2_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_DBFALL register. +// +//***************************************************************************** +#define PWM_2_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_2_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_2_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CTL register. +// +//***************************************************************************** +#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input +#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period +#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source +#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode +#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized +#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized +#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode +#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized +#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized +#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode +#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized +#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized +#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode +#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized +#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized +#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode +#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate +#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized +#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized +#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode +#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode +#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode +#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode +#define PWM_3_CTL_MODE 0x00000002 // Counter Mode +#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_INTEN register. +// +//***************************************************************************** +#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up +#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up +#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD +#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0 +#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB + // Down +#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB + // Up +#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA + // Down +#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA + // Up +#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD +#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_RIS register. +// +//***************************************************************************** +#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt + // Status +#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status +#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt + // Status +#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status +#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status +#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_ISC register. +// +//***************************************************************************** +#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt +#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt +#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt +#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt +#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt +#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_LOAD register. +// +//***************************************************************************** +#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value +#define PWM_3_LOAD_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_COUNT register. +// +//***************************************************************************** +#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value +#define PWM_3_COUNT_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPA register. +// +//***************************************************************************** +#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value +#define PWM_3_CMPA_COMPA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_CMPB register. +// +//***************************************************************************** +#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value +#define PWM_3_CMPB_COMPB_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENA register. +// +//***************************************************************************** +#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENA_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA +#define PWM_3_GENA_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High +#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENA_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA +#define PWM_3_GENA_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENA_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA +#define PWM_3_GENA_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High +#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENA_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA +#define PWM_3_GENA_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmA Low +#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High +#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA +#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low +#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High +#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA +#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low +#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_GENB register. +// +//***************************************************************************** +#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down +#define PWM_3_GENB_ACTCMPBD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB +#define PWM_3_GENB_ACTCMPBD_ZERO \ + 0x00000800 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High +#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up +#define PWM_3_GENB_ACTCMPBU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB +#define PWM_3_GENB_ACTCMPBU_ZERO \ + 0x00000200 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down +#define PWM_3_GENB_ACTCMPAD_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB +#define PWM_3_GENB_ACTCMPAD_ZERO \ + 0x00000080 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High +#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up +#define PWM_3_GENB_ACTCMPAU_NONE \ + 0x00000000 // Do nothing +#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB +#define PWM_3_GENB_ACTCMPAU_ZERO \ + 0x00000020 // Drive pwmB Low +#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High +#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD +#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB +#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low +#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High +#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0 +#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing +#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB +#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low +#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBCTL register. +// +//***************************************************************************** +#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBRISE register. +// +//***************************************************************************** +#define PWM_3_DBRISE_RISEDELAY_M \ + 0x00000FFF // Dead-Band Rise Delay +#define PWM_3_DBRISE_RISEDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_DBFALL register. +// +//***************************************************************************** +#define PWM_3_DBFALL_FALLDELAY_M \ + 0x00000FFF // Dead-Band Fall Delay +#define PWM_3_DBFALL_FALLDELAY_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input +#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSRC1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7 +#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6 +#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5 +#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4 +#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3 +#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2 +#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1 +#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_MINFLTPER +// register. +// +//***************************************************************************** +#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period +#define PWM_3_MINFLTPER_MFP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSEN register. +// +//***************************************************************************** +#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSEN register. +// +//***************************************************************************** +#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense +#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1 +#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1 +// register. +// +//***************************************************************************** +#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger +#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger +#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger +#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger +#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger +#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger +#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger +#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger + +//***************************************************************************** +// +// The following are defines for the bit fields in the PWM_O_PP register. +// +//***************************************************************************** +#define PWM_PP_ONE 0x00000400 // One-Shot Mode +#define PWM_PP_EFAULT 0x00000200 // Extended Fault +#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization +#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit) +#define PWM_PP_GCNT_M 0x0000000F // Generators +#define PWM_PP_FCNT_S 4 +#define PWM_PP_GCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_CTL register. +// +//***************************************************************************** +#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count +#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter +#define QEI_CTL_STALLEN 0x00001000 // Stall QEI +#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse +#define QEI_CTL_INVB 0x00000400 // Invert PhB +#define QEI_CTL_INVA 0x00000200 // Invert PhA +#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity +#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1 +#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2 +#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4 +#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8 +#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16 +#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32 +#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64 +#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128 +#define QEI_CTL_VELEN 0x00000020 // Capture Velocity +#define QEI_CTL_RESMODE 0x00000010 // Reset Mode +#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode +#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode +#define QEI_CTL_SWAP 0x00000002 // Swap Signals +#define QEI_CTL_ENABLE 0x00000001 // Enable QEI +#define QEI_CTL_FILTCNT_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_STAT register. +// +//***************************************************************************** +#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation +#define QEI_STAT_ERROR 0x00000001 // Error Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_POS register. +// +//***************************************************************************** +#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator + // Value +#define QEI_POS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_MAXPOS register. +// +//***************************************************************************** +#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator + // Value +#define QEI_MAXPOS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_LOAD register. +// +//***************************************************************************** +#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value +#define QEI_LOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_TIME register. +// +//***************************************************************************** +#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value +#define QEI_TIME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_COUNT register. +// +//***************************************************************************** +#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count +#define QEI_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_SPEED register. +// +//***************************************************************************** +#define QEI_SPEED_M 0xFFFFFFFF // Velocity +#define QEI_SPEED_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_INTEN register. +// +//***************************************************************************** +#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable +#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt + // Enable +#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable +#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_RIS register. +// +//***************************************************************************** +#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected +#define QEI_RIS_DIR 0x00000004 // Direction Change Detected +#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired +#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted + +//***************************************************************************** +// +// The following are defines for the bit fields in the QEI_O_ISC register. +// +//***************************************************************************** +#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt +#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt +#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt +#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this + // value selects the 32-bit timer + // configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this + // value selects the 32-bit + // real-time clock (RTC) counter + // configuration +#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this + // value selects the 16-bit timer + // configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer + // 5 +#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not + // affected +#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 5 is + // triggered +#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 5 is triggered +#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer + // 4 +#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not + // affected +#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 4 is + // triggered +#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 4 is triggered +#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer + // 3 +#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not + // affected +#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 3 is + // triggered +#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 3 is triggered +#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer + // 2 +#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not + // affected +#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 2 is + // triggered +#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 2 is triggered +#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer + // 1 +#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not + // affected +#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 1 is + // triggered +#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 1 is triggered +#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer + // 0 +#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not + // affected +#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of + // GPTM 32/64-Bit Timer 0 is + // triggered +#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM 32/64-Bit + // Timer 0 is triggered +#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected +#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected +#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected +#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected +#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected +#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected +#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Mask +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt + // Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt + // Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Raw Interrupt Status +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event + // Raw Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match + // Raw Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Masked Interrupt Status +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event + // Masked Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match + // Masked Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update + // Error Interrupt Clear +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt + // Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt + // Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event + // Interrupt Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match + // Interrupt Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +#define TIMER_TAILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +#define TIMER_TAMATCHR_TAMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +#define TIMER_TBMATCHR_TBMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +#define TIMER_TAPR_TAPSRH_S 8 +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +#define TIMER_TBPR_TBPSRH_S 8 +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +#define TIMER_TAPMR_TAPSMRH_S 8 +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +#define TIMER_TBPMR_TBPSMRH_S 8 +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +#define TIMER_TAR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +#define TIMER_TBR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +#define TIMER_TAV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are + // 32 bits each with a 16-bit + // prescale counter + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ACTSS register. +// +//***************************************************************************** +#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy +#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable +#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable +#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable +#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_RIS register. +// +//***************************************************************************** +#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt + // Status +#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status +#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status +#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status +#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_IM register. +// +//***************************************************************************** +#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on + // SS3 +#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on + // SS2 +#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on + // SS1 +#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on + // SS0 +#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask +#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask +#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask +#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ISC register. +// +//***************************************************************************** +#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt + // Status on SS3 +#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt + // Status on SS2 +#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt + // Status on SS1 +#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt + // Status on SS0 +#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear +#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear +#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear +#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_OSTAT register. +// +//***************************************************************************** +#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow +#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow +#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow +#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_EMUX register. +// +//***************************************************************************** +#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select +#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0 +#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1 +#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins) +#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer +#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0 +#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1 +#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2 +#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3 +#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample) +#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select +#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0 +#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1 +#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins) +#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer +#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0 +#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1 +#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2 +#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3 +#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample) +#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select +#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0 +#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1 +#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins) +#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer +#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0 +#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1 +#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2 +#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3 +#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample) +#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select +#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default) +#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0 +#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1 +#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins) +#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer +#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0 +#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1 +#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2 +#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3 +#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample) + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_USTAT register. +// +//***************************************************************************** +#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow +#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow +#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow +#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_TSSEL register. +// +//***************************************************************************** +#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger + // Select +#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger + // Select +#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger + // Select +#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its + // trigger) in PWM module 1 +#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger + // Select +#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its + // trigger) in PWM module 0 +#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its + // trigger) in PWM module 1 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSPRI register. +// +//***************************************************************************** +#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority +#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority +#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority +#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SPC register. +// +//***************************************************************************** +#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference +#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0 +#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5 +#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0 +#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5 +#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0 +#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5 +#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0 +#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5 +#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0 +#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5 +#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0 +#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5 +#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0 +#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5 +#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0 +#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PSSI register. +// +//***************************************************************************** +#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize +#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait +#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate +#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate +#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate +#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SAC register. +// +//***************************************************************************** +#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control +#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling +#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling +#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling +#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling +#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling +#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling +#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCISC register. +// +//***************************************************************************** +#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt + // Status and Clear +#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt + // Status and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CTL register. +// +//***************************************************************************** +#define ADC_CTL_DITHER 0x00000040 // Dither Mode Enable +#define ADC_CTL_VREF_M 0x00000001 // Voltage Reference Select +#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage + // references + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX0 register. +// +//***************************************************************************** +#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select +#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select +#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select +#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select +#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX0_MUX7_S 28 +#define ADC_SSMUX0_MUX6_S 24 +#define ADC_SSMUX0_MUX5_S 20 +#define ADC_SSMUX0_MUX4_S 16 +#define ADC_SSMUX0_MUX3_S 12 +#define ADC_SSMUX0_MUX2_S 8 +#define ADC_SSMUX0_MUX1_S 4 +#define ADC_SSMUX0_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL0 register. +// +//***************************************************************************** +#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select +#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable +#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence +#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input + // Select +#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select +#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable +#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence +#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input + // Select +#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select +#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable +#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence +#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input + // Select +#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select +#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable +#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence +#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input + // Select +#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. +// +//***************************************************************************** +#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. +// +//***************************************************************************** +#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT0_HPTR_S 4 +#define ADC_SSFSTAT0_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP0 register. +// +//***************************************************************************** +#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator + // Operation +#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator + // Operation +#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator + // Operation +#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator + // Operation +#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC0 register. +// +//***************************************************************************** +#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator + // Select +#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator + // Select +#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator + // Select +#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC0_S6DCSEL_S 24 +#define ADC_SSDC0_S5DCSEL_S 20 +#define ADC_SSDC0_S4DCSEL_S 16 +#define ADC_SSDC0_S3DCSEL_S 12 +#define ADC_SSDC0_S2DCSEL_S 8 +#define ADC_SSDC0_S1DCSEL_S 4 +#define ADC_SSDC0_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX1 register. +// +//***************************************************************************** +#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX1_MUX3_S 12 +#define ADC_SSMUX1_MUX2_S 8 +#define ADC_SSMUX1_MUX1_S 4 +#define ADC_SSMUX1_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL1 register. +// +//***************************************************************************** +#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. +// +//***************************************************************************** +#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. +// +//***************************************************************************** +#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT1_HPTR_S 4 +#define ADC_SSFSTAT1_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP1 register. +// +//***************************************************************************** +#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC1 register. +// +//***************************************************************************** +#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC1_S2DCSEL_S 8 +#define ADC_SSDC1_S1DCSEL_S 4 +#define ADC_SSDC1_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX2 register. +// +//***************************************************************************** +#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select +#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select +#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select +#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX2_MUX3_S 12 +#define ADC_SSMUX2_MUX2_S 8 +#define ADC_SSMUX2_MUX1_S 4 +#define ADC_SSMUX2_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL2 register. +// +//***************************************************************************** +#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select +#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable +#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence +#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input + // Select +#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select +#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable +#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence +#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input + // Select +#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select +#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable +#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence +#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input + // Select +#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable +#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence +#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. +// +//***************************************************************************** +#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. +// +//***************************************************************************** +#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT2_HPTR_S 4 +#define ADC_SSFSTAT2_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP2 register. +// +//***************************************************************************** +#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator + // Operation +#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator + // Operation +#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator + // Operation +#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC2 register. +// +//***************************************************************************** +#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator + // Select +#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator + // Select +#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select +#define ADC_SSDC2_S2DCSEL_S 8 +#define ADC_SSDC2_S1DCSEL_S 4 +#define ADC_SSDC2_S0DCSEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSMUX3 register. +// +//***************************************************************************** +#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select +#define ADC_SSMUX3_MUX0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSCTL3 register. +// +//***************************************************************************** +#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select +#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable +#define ADC_SSCTL3_END0 0x00000002 // End of Sequence +#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. +// +//***************************************************************************** +#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data +#define ADC_SSFIFO3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. +// +//***************************************************************************** +#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full +#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty +#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer +#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer +#define ADC_SSFSTAT3_HPTR_S 4 +#define ADC_SSFSTAT3_TPTR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSOP3 register. +// +//***************************************************************************** +#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator + // Operation + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_SSDC3 register. +// +//***************************************************************************** +#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator + // Select + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCRIC register. +// +//***************************************************************************** +#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7 +#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6 +#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5 +#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4 +#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3 +#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2 +#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1 +#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0 +#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7 +#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6 +#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5 +#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4 +#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3 +#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2 +#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1 +#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL0 register. +// +//***************************************************************************** +#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL1 register. +// +//***************************************************************************** +#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL2 register. +// +//***************************************************************************** +#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL3 register. +// +//***************************************************************************** +#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL4 register. +// +//***************************************************************************** +#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL5 register. +// +//***************************************************************************** +#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL6 register. +// +//***************************************************************************** +#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCTL7 register. +// +//***************************************************************************** +#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable +#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition +#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band +#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band +#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode +#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once +#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always +#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once +#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable +#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition +#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band +#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band +#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band +#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode +#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always +#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once +#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always +#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP0 register. +// +//***************************************************************************** +#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP0_COMP1_S 16 +#define ADC_DCCMP0_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP1 register. +// +//***************************************************************************** +#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP1_COMP1_S 16 +#define ADC_DCCMP1_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP2 register. +// +//***************************************************************************** +#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP2_COMP1_S 16 +#define ADC_DCCMP2_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP3 register. +// +//***************************************************************************** +#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP3_COMP1_S 16 +#define ADC_DCCMP3_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP4 register. +// +//***************************************************************************** +#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP4_COMP1_S 16 +#define ADC_DCCMP4_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP5 register. +// +//***************************************************************************** +#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP5_COMP1_S 16 +#define ADC_DCCMP5_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP6 register. +// +//***************************************************************************** +#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP6_COMP1_S 16 +#define ADC_DCCMP6_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_DCCMP7 register. +// +//***************************************************************************** +#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1 +#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0 +#define ADC_DCCMP7_COMP1_S 16 +#define ADC_DCCMP7_COMP0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PP register. +// +//***************************************************************************** +#define ADC_PP_TS 0x00800000 // Temperature Sensor +#define ADC_PP_RSL_M 0x007C0000 // Resolution +#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture +#define ADC_PP_TYPE_SAR 0x00000000 // SAR +#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count +#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count +#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate +#define ADC_PP_MSR_125K 0x00000001 // 125 ksps +#define ADC_PP_MSR_250K 0x00000003 // 250 ksps +#define ADC_PP_MSR_500K 0x00000005 // 500 ksps +#define ADC_PP_MSR_1M 0x00000007 // 1 Msps +#define ADC_PP_RSL_S 18 +#define ADC_PP_DC_S 10 +#define ADC_PP_CH_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_PC register. +// +//***************************************************************************** +#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate +#define ADC_PC_SR_125K 0x00000001 // 125 ksps +#define ADC_PC_SR_250K 0x00000003 // 250 ksps +#define ADC_PC_SR_500K 0x00000005 // 500 ksps +#define ADC_PC_SR_1M 0x00000007 // 1 Msps + +//***************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_CC register. +// +//***************************************************************************** +#define ADC_CC_CS_M 0x0000000F // ADC Clock Source +#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV +#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACMIS register. +// +//***************************************************************************** +#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt + // Status +#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACRIS register. +// +//***************************************************************************** +#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status +#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACINTEN register. +// +//***************************************************************************** +#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable +#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACREFCTL +// register. +// +//***************************************************************************** +#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable +#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range +#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref +#define COMP_ACREFCTL_VREF_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. +// +//***************************************************************************** +#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL0 register. +// +//***************************************************************************** +#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. +// +//***************************************************************************** +#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_ACCTL1 register. +// +//***************************************************************************** +#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable +#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive +#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+ +#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ +#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference +#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value +#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense +#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL +#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge +#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge +#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge +#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value +#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense +#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL +#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge +#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge +#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge +#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert + +//***************************************************************************** +// +// The following are defines for the bit fields in the COMP_O_PP register. +// +//***************************************************************************** +#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present +#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present +#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present +#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_CTL register. +// +//***************************************************************************** +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable +#define CAN_CTL_INIT 0x00000001 // Initialization + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_STS register. +// +//***************************************************************************** +#define CAN_STS_BOFF 0x00000080 // Bus-Off Status +#define CAN_STS_EWARN 0x00000040 // Warning Status +#define CAN_STS_EPASS 0x00000020 // Error Passive +#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully +#define CAN_STS_TXOK 0x00000008 // Transmitted a Message + // Successfully +#define CAN_STS_LEC_M 0x00000007 // Last Error Code +#define CAN_STS_LEC_NONE 0x00000000 // No Error +#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error +#define CAN_STS_LEC_FORM 0x00000002 // Format Error +#define CAN_STS_LEC_ACK 0x00000003 // ACK Error +#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error +#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error +#define CAN_STS_LEC_CRC 0x00000006 // CRC Error +#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_ERR register. +// +//***************************************************************************** +#define CAN_ERR_RP 0x00008000 // Received Error Passive +#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter +#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter +#define CAN_ERR_REC_S 8 +#define CAN_ERR_TEC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BIT register. +// +//***************************************************************************** +#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point +#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point +#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width +#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler +#define CAN_BIT_TSEG2_S 12 +#define CAN_BIT_TSEG1_S 8 +#define CAN_BIT_SJW_S 6 +#define CAN_BIT_BRP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_INT register. +// +//***************************************************************************** +#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier +#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending +#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TST register. +// +//***************************************************************************** +#define CAN_TST_RX 0x00000080 // Receive Observation +#define CAN_TST_TX_M 0x00000060 // Transmit Control +#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control +#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point +#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low +#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High +#define CAN_TST_LBACK 0x00000010 // Loopback Mode +#define CAN_TST_SILENT 0x00000008 // Silent Mode +#define CAN_TST_BASIC 0x00000004 // Basic Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_BRPE register. +// +//***************************************************************************** +#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension +#define CAN_BRPE_BRPE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CRQ register. +// +//***************************************************************************** +#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF1CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1CMSK register. +// +//***************************************************************************** +#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. +// +//***************************************************************************** +#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF1MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. +// +//***************************************************************************** +#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF1MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. +// +//***************************************************************************** +#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF1ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. +// +//***************************************************************************** +#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF1ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1MCTL register. +// +//***************************************************************************** +#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF1MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA1 register. +// +//***************************************************************************** +#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DA2 register. +// +//***************************************************************************** +#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB1 register. +// +//***************************************************************************** +#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF1DB2 register. +// +//***************************************************************************** +#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF1DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CRQ register. +// +//***************************************************************************** +#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag +#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number +#define CAN_IF2CRQ_MNUM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2CMSK register. +// +//***************************************************************************** +#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read +#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits +#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits +#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits +#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit +#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data +#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request +#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3 +#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. +// +//***************************************************************************** +#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask +#define CAN_IF2MSK1_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. +// +//***************************************************************************** +#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier +#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction +#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask +#define CAN_IF2MSK2_IDMSK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. +// +//***************************************************************************** +#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier +#define CAN_IF2ARB1_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. +// +//***************************************************************************** +#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid +#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier +#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction +#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier +#define CAN_IF2ARB2_ID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2MCTL register. +// +//***************************************************************************** +#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data +#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost +#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending +#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask +#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable +#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable +#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable +#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request +#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer +#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code +#define CAN_IF2MCTL_DLC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA1 register. +// +//***************************************************************************** +#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DA2 register. +// +//***************************************************************************** +#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DA2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB1 register. +// +//***************************************************************************** +#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_IF2DB2 register. +// +//***************************************************************************** +#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data +#define CAN_IF2DB2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ1 register. +// +//***************************************************************************** +#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ1_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_TXRQ2 register. +// +//***************************************************************************** +#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits +#define CAN_TXRQ2_TXRQST_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA1 register. +// +//***************************************************************************** +#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA1_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_NWDA2 register. +// +//***************************************************************************** +#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits +#define CAN_NWDA2_NEWDAT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1INT register. +// +//***************************************************************************** +#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG1INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2INT register. +// +//***************************************************************************** +#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits +#define CAN_MSG2INT_INTPND_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG1VAL register. +// +//***************************************************************************** +#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG1VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the CAN_O_MSG2VAL register. +// +//***************************************************************************** +#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits +#define CAN_MSG2VAL_MSGVAL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESIZE register. +// +//***************************************************************************** +#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks +#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words +#define EEPROM_EESIZE_BLKCNT_S 16 +#define EEPROM_EESIZE_WORDCNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEBLOCK register. +// +//***************************************************************************** +#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block +#define EEPROM_EEBLOCK_BLOCK_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEOFFSET +// register. +// +//***************************************************************************** +#define EEPROM_EEOFFSET_OFFSET_M \ + 0x0000000F // Current Address Offset +#define EEPROM_EEOFFSET_OFFSET_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWR register. +// +//***************************************************************************** +#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data +#define EEPROM_EERDWR_VALUE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EERDWRINC +// register. +// +//***************************************************************************** +#define EEPROM_EERDWRINC_VALUE_M \ + 0xFFFFFFFF // EEPROM Read or Write Data with + // Increment +#define EEPROM_EERDWRINC_VALUE_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDONE register. +// +//***************************************************************************** +#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy +#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission +#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy +#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase +#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EESUPP register. +// +//***************************************************************************** +#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried +#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEUNLOCK +// register. +// +//***************************************************************************** +#define EEPROM_EEUNLOCK_UNLOCK_M \ + 0xFFFFFFFF // EEPROM Unlock + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPROT register. +// +//***************************************************************************** +#define EEPROM_EEPROT_ACC 0x00000008 // Access Control +#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control +#define EEPROM_EEPROT_PROT_RWNPW \ + 0x00000000 // This setting is the default. If + // there is no password, the block + // is not protected and is readable + // and writable +#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the + // block is readable or writable + // only when unlocked +#define EEPROM_EEPROT_PROT_RONPW \ + 0x00000002 // If there is no password, the + // block is readable, not writable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS0 register. +// +//***************************************************************************** +#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS0_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS1 register. +// +//***************************************************************************** +#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS1_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEPASS2 register. +// +//***************************************************************************** +#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password +#define EEPROM_EEPASS2_PASS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEINT register. +// +//***************************************************************************** +#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEHIDE register. +// +//***************************************************************************** +#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_EEDBGME register. +// +//***************************************************************************** +#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key +#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase +#define EEPROM_EEDBGME_KEY_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the EEPROM_PP register. +// +//***************************************************************************** +#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size +#define EEPROM_PP_SIZE_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_RIS register. +// +//***************************************************************************** +#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception + // Raw Interrupt Status +#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation + // Raw Interrupt Status +#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0 + // Exception Raw Interrupt Status +#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal + // Exception Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IM register. +// +//***************************************************************************** +#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception + // Interrupt Mask +#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow + // Exception Interrupt Mask +#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation + // Interrupt Mask +#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Mask +#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_MIS register. +// +//***************************************************************************** +#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception + // Masked Interrupt Status +#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation + // Masked Interrupt Status +#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0 + // Exception Masked Interrupt + // Status +#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal + // Exception Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSEXC_IC register. +// +//***************************************************************************** +#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception + // Interrupt Clear +#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow + // Exception Interrupt Clear +#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation + // Interrupt Clear +#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0 + // Exception Interrupt Clear +#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal + // Exception Interrupt Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCC register. +// +//***************************************************************************** +#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter +#define HIB_RTCC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCM0 register. +// +//***************************************************************************** +#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0 +#define HIB_RTCM0_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCLD register. +// +//***************************************************************************** +#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load +#define HIB_RTCLD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_CTL register. +// +//***************************************************************************** +#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable +#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability +#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass +#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery + // Comparator +#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts +#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default) +#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts +#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts +#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status +#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery +#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered +#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable +#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable +#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable +#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable +#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request +#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IM register. +// +//***************************************************************************** +#define HIB_IM_WC 0x00000010 // External Write Complete/Capable + // Interrupt Mask +#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask +#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Mask +#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RIS register. +// +//***************************************************************************** +#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw + // Interrupt Status +#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt + // Status +#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw + // Interrupt Status +#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_MIS register. +// +//***************************************************************************** +#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked + // Interrupt Status +#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked + // Interrupt Status +#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked + // Interrupt Status +#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_IC register. +// +//***************************************************************************** +#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt + // Clear +#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear +#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt + // Clear +#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCT register. +// +//***************************************************************************** +#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value +#define HIB_RTCT_TRIM_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_RTCSS register. +// +//***************************************************************************** +#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match +#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count +#define HIB_RTCSS_RTCSSM_S 16 +#define HIB_RTCSS_RTCSSC_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the HIB_DATA register. +// +//***************************************************************************** +#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data +#define HIB_DATA_RTD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMA register. +// +//***************************************************************************** +#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset +#define FLASH_FMA_OFFSET_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMD register. +// +//***************************************************************************** +#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value +#define FLASH_FMD_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC register. +// +//***************************************************************************** +#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_FMC_COMT 0x00000008 // Commit Register Value +#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory +#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory +#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCRIS register. +// +//***************************************************************************** +#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw + // Interrupt Status +#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status +#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt + // Status +#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt + // Status +#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status +#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status +#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCIM register. +// +//***************************************************************************** +#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask +#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask +#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask +#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask +#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask +#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask +#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FCMISC register. +// +//***************************************************************************** +#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and + // Clear +#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear +#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear +#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FMC2 register. +// +//***************************************************************************** +#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBVAL register. +// +//***************************************************************************** +#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FWBN register. +// +//***************************************************************************** +#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_FSIZE register. +// +//***************************************************************************** +#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size +#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_SSIZE register. +// +//***************************************************************************** +#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size +#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_ROMSWMAP register. +// +//***************************************************************************** +#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_RMCTL register. +// +//***************************************************************************** +#define FLASH_RMCTL_BA 0x00000001 // Boot Alias + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_BOOTCFG register. +// +//***************************************************************************** +#define FLASH_BOOTCFG_NW 0x80000000 // Not Written +#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port +#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A +#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B +#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C +#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D +#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E +#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F +#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G +#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H +#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin +#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0 +#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1 +#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2 +#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3 +#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4 +#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5 +#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6 +#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7 +#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity +#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable +#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select +#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1 +#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG0 register. +// +//***************************************************************************** +#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG0_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG1 register. +// +//***************************************************************************** +#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG1_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG2 register. +// +//***************************************************************************** +#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG2_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the FLASH_USERREG3 register. +// +//***************************************************************************** +#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data +#define FLASH_USERREG3_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID0 register. +// +//***************************************************************************** +#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version +#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0 + // register format. +#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class +#define SYSCTL_DID0_CLASS_TM4C123 \ + 0x00050000 // Tiva TM4C123x and TM4E123x + // microcontrollers +#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision +#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) +#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer + // revision) +#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer + // revision) +#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision +#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major + // revision update +#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change +#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DID1 register. +// +//***************************************************************************** +#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version +#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib +#define SYSCTL_DID1_FAM_M 0x0F000000 // Family +#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers +#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number +#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \ + 0x00A10000 // TM4C123GH6PM +#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count +#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package +#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package +#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package +#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package +#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package +#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range +#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range +#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range +#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial + // temperature range (-40C to 85C) + // and extended temperature range + // (-40C to 105C) devices. See +#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type +#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package +#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package +#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance +#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status +#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified) +#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified) +#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC0 register. +// +//***************************************************************************** +#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size +#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM +#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM +#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size +#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash +#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash +#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash +#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash +#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash +#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash +#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash +#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC1 register. +// +//***************************************************************************** +#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present +#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present +#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present +#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present +#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present +#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present +#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present +#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider +#define SYSCTL_DC1_MINSYSDIV_80 0x00001000 // Specifies an 80-MHz CPU clock + // with a PLL divider of 2.5 +#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Specifies a 66-MHz CPU clock + // with a PLL divider of 3 +#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock + // with a PLL divider of 4 +#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock + // with a PLL divider of 5 +#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a + // PLL divider of 8 +#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a + // PLL divider of 10 +#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed +#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second +#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second +#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed +#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second +#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second +#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second +#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_DC1_MPU 0x00000080 // MPU Present +#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present +#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present +#define SYSCTL_DC1_PLL 0x00000010 // PLL Present +#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present +#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present +#define SYSCTL_DC1_SWD 0x00000002 // SWD Present +#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC2 register. +// +//***************************************************************************** +#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present +#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present +#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present +#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present +#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present +#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present +#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present +#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present +#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present +#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed +#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present +#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed +#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present +#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present +#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present +#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present +#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present +#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present +#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present +#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC3 register. +// +//***************************************************************************** +#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available +#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present +#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present +#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present +#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present +#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present +#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present +#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present +#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present +#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present +#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present +#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present +#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present +#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present +#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present +#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present +#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present +#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present +#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC4 register. +// +//***************************************************************************** +#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present +#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present +#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable +#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate +#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present +#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present +#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present +#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present +#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present +#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present +#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present +#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present +#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present +#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present +#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present +#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present +#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC5 register. +// +//***************************************************************************** +#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present +#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present +#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present +#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present +#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active +#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active +#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present +#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present +#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present +#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present +#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present +#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present +#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present +#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC6 register. +// +//***************************************************************************** +#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present +#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present +#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only +#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host +#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC7 register. +// +//***************************************************************************** +#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30 +#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29 +#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28 +#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27 +#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26 +#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25 +#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24 +#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23 +#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22 +#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21 +#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20 +#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19 +#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18 +#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17 +#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16 +#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15 +#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14 +#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13 +#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12 +#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11 +#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10 +#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9 +#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8 +#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7 +#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6 +#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5 +#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4 +#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3 +#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2 +#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1 +#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC8 register. +// +//***************************************************************************** +#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present +#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present +#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present +#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present +#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present +#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present +#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present +#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present +#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present +#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present +#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present +#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present +#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present +#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present +#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present +#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present +#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present +#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present +#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present +#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present +#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present +#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present +#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present +#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present +#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present +#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present +#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present +#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present +#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present +#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present +#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present +#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PBORCTL register. +// +//***************************************************************************** +#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action +#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR0 register. +// +//***************************************************************************** +#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control +#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control +#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control +#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control +#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control +#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control +#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control +#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR1 register. +// +//***************************************************************************** +#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control +#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control +#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control +#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control +#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control +#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control +#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control +#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control +#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control +#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control +#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control +#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control +#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control +#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control +#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCR2 register. +// +//***************************************************************************** +#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control +#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control +#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control +#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control +#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control +#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control +#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control +#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RIS register. +// +//***************************************************************************** +#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt + // Status +#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw + // Interrupt Status +#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt + // Status +#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt + // Status +#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status +#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw + // Interrupt Status +#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_IMC register. +// +//***************************************************************************** +#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask +#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask +#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask +#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask +#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask +#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure + // Interrupt Mask +#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MISC register. +// +//***************************************************************************** +#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt + // Status +#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt + // Status +#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt + // Status +#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt + // Status +#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status +#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked + // Interrupt Status +#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RESC register. +// +//***************************************************************************** +#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset +#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset +#define SYSCTL_RESC_SW 0x00000010 // Software Reset +#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset +#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset +#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset +#define SYSCTL_RESC_EXT 0x00000001 // External Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC register. +// +//***************************************************************************** +#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating +#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor +#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider +#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor +#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor +#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 +#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 +#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 +#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 +#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 +#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 +#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down +#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass +#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value +#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz +#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz +#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz +#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz +#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz +#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz +#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz +#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz +#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz +#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz +#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz +#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz +#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz +#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz +#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz +#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz +#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz +#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB) +#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB) +#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB) +#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB) +#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source +#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC +#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC +#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4 +#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC +#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable +#define SYSCTL_RCC_SYSDIV_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL +// register. +// +//***************************************************************************** +#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance + // Bus +#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance + // Bus + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCC2 register. +// +//***************************************************************************** +#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 +#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200 + // MHz +#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2 +#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2 +#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL +#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2 +#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2 +#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2 +#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC +#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC +#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4 +#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC +#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz +#define SYSCTL_RCC2_SYSDIV2_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. +// +//***************************************************************************** +#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected +#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action +#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC0 register. +// +//***************************************************************************** +#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed +#define SYSCTL_RCGC0_ADC1SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC1SPD_250K \ + 0x00000400 // 250K samples/second +#define SYSCTL_RCGC0_ADC1SPD_500K \ + 0x00000800 // 500K samples/second +#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second +#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed +#define SYSCTL_RCGC0_ADC0SPD_125K \ + 0x00000000 // 125K samples/second +#define SYSCTL_RCGC0_ADC0SPD_250K \ + 0x00000100 // 250K samples/second +#define SYSCTL_RCGC0_ADC0SPD_500K \ + 0x00000200 // 500K samples/second +#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second +#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC1 register. +// +//***************************************************************************** +#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGC2 register. +// +//***************************************************************************** +#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC0 register. +// +//***************************************************************************** +#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC1 register. +// +//***************************************************************************** +#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGC2 register. +// +//***************************************************************************** +#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC0 register. +// +//***************************************************************************** +#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control +#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control +#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control +#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control +#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control +#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control +#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control +#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC1 register. +// +//***************************************************************************** +#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating +#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating +#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control +#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control +#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control +#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control +#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control +#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control +#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control +#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control +#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control +#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control +#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control +#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control +#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGC2 register. +// +//***************************************************************************** +#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control +#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control +#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control +#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control +#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control +#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control +#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control +#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override +#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source +#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC +#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC +#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC +#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz +#define SYSCTL_DSLPCLKCFG_PIOSCPD \ + 0x00000002 // PIOSC Power Down Request +#define SYSCTL_DSLPCLKCFG_D_S 23 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SYSPROP register. +// +//***************************************************************************** +#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCCAL +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value +#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration +#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim +#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value +#define SYSCTL_PIOSCCAL_UT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT +// register. +// +//***************************************************************************** +#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value +#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result +#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been + // attempted +#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation + // completed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation + // failed to meet 1% accuracy +#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value +#define SYSCTL_PIOSCSTAT_DT_S 16 +#define SYSCTL_PIOSCSTAT_CT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ0 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value +#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value +#define SYSCTL_PLLFREQ0_MFRAC_S 10 +#define SYSCTL_PLLFREQ0_MINT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLFREQ1 +// register. +// +//***************************************************************************** +#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value +#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value +#define SYSCTL_PLLFREQ1_Q_S 8 +#define SYSCTL_PLLFREQ1_N_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PLLSTAT register. +// +//***************************************************************************** +#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_SLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_SLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG +// register. +// +//***************************************************************************** +#define SYSCTL_DSLPPWRCFG_FLASHPM_M \ + 0x00000030 // Flash Power Modes +#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \ + 0x00000020 // Low Power Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_M \ + 0x00000003 // SRAM Power Modes +#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \ + 0x00000000 // Active Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \ + 0x00000001 // Standby Mode +#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \ + 0x00000003 // Low Power Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DC9 register. +// +//***************************************************************************** +#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present +#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present +#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present +#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present +#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present +#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present +#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present +#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present +#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present +#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present +#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present +#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present +#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present +#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present +#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present +#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_NVMSTAT register. +// +//***************************************************************************** +#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer + // Available + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDOSPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDOSPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDOSPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDOSPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDOSPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDOSPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDOSPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDOSPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_LDODPCTL +// register. +// +//***************************************************************************** +#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable +#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage +#define SYSCTL_LDODPCTL_VLDO_0_90V \ + 0x00000012 // 0.90 V +#define SYSCTL_LDODPCTL_VLDO_0_95V \ + 0x00000013 // 0.95 V +#define SYSCTL_LDODPCTL_VLDO_1_00V \ + 0x00000014 // 1.00 V +#define SYSCTL_LDODPCTL_VLDO_1_05V \ + 0x00000015 // 1.05 V +#define SYSCTL_LDODPCTL_VLDO_1_10V \ + 0x00000016 // 1.10 V +#define SYSCTL_LDODPCTL_VLDO_1_15V \ + 0x00000017 // 1.15 V +#define SYSCTL_LDODPCTL_VLDO_1_20V \ + 0x00000018 // 1.20 V + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWD register. +// +//***************************************************************************** +#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present +#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPTIMER register. +// +//***************************************************************************** +#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Present +#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Present +#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Present +#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Present +#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Present +#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPGPIO register. +// +//***************************************************************************** +#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present +#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present +#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present +#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present +#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present +#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present +#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present +#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present +#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present +#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present +#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present +#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present +#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present +#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present +#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPDMA register. +// +//***************************************************************************** +#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPHIB register. +// +//***************************************************************************** +#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUART register. +// +//***************************************************************************** +#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present +#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present +#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present +#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present +#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present +#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present +#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present +#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPSSI register. +// +//***************************************************************************** +#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present +#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present +#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present +#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPI2C register. +// +//***************************************************************************** +#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present +#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present +#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present +#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present +#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present +#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPUSB register. +// +//***************************************************************************** +#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPCAN register. +// +//***************************************************************************** +#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present +#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPADC register. +// +//***************************************************************************** +#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present +#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPACMP register. +// +//***************************************************************************** +#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPPWM register. +// +//***************************************************************************** +#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present +#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPQEI register. +// +//***************************************************************************** +#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present +#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PPWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Present +#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Present +#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Present +#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Present +#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Present +#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Present + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWD register. +// +//***************************************************************************** +#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset +#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRTIMER register. +// +//***************************************************************************** +#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Software Reset +#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Software Reset +#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Software Reset +#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Software Reset +#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Software Reset +#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRGPIO register. +// +//***************************************************************************** +#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset +#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset +#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset +#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset +#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset +#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRDMA register. +// +//***************************************************************************** +#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRHIB register. +// +//***************************************************************************** +#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software + // Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUART register. +// +//***************************************************************************** +#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset +#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset +#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset +#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset +#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset +#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset +#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset +#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRSSI register. +// +//***************************************************************************** +#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset +#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset +#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset +#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRI2C register. +// +//***************************************************************************** +#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset +#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset +#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset +#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRUSB register. +// +//***************************************************************************** +#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRCAN register. +// +//***************************************************************************** +#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset +#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRADC register. +// +//***************************************************************************** +#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset +#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRACMP register. +// +//***************************************************************************** +#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRPWM register. +// +//***************************************************************************** +#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset +#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRQEI register. +// +//***************************************************************************** +#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset +#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Software Reset +#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Software Reset +#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Software Reset +#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Software Reset +#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Software Reset +#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Software Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWD register. +// +//***************************************************************************** +#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Run Mode Clock Gating Control +#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Run Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock + // Gating Control +#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCADC register. +// +//***************************************************************************** +#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock + // Gating Control +#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Run Mode Clock Gating + // Control +#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Run Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWD register. +// +//***************************************************************************** +#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode + // Clock Gating Control +#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCADC register. +// +//***************************************************************************** +#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock + // Gating Control +#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Sleep Mode Clock Gating + // Control +#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWD register. +// +//***************************************************************************** +#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Deep-Sleep Mode Clock Gating + // Control +#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCGPIO +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCDMA register. +// +//***************************************************************************** +#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCHIB register. +// +//***************************************************************************** +#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep + // Mode Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUART +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCSSI register. +// +//***************************************************************************** +#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCI2C register. +// +//***************************************************************************** +#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCUSB register. +// +//***************************************************************************** +#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCCAN register. +// +//***************************************************************************** +#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCADC register. +// +//***************************************************************************** +#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCACMP +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0 + // Deep-Sleep Mode Clock Gating + // Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCPWM register. +// +//***************************************************************************** +#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCQEI register. +// +//***************************************************************************** +#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode + // Clock Gating Control +#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode + // Clock Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Deep-Sleep Mode Clock + // Gating Control +#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Deep-Sleep Mode Clock + // Gating Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWD register. +// +//***************************************************************************** +#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral + // Ready +#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRTIMER register. +// +//***************************************************************************** +#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer + // 5 Peripheral Ready +#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer + // 4 Peripheral Ready +#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer + // 3 Peripheral Ready +#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer + // 2 Peripheral Ready +#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer + // 1 Peripheral Ready +#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer + // 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRGPIO register. +// +//***************************************************************************** +#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready +#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready +#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready +#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready +#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready +#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRDMA register. +// +//***************************************************************************** +#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRHIB register. +// +//***************************************************************************** +#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral + // Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUART register. +// +//***************************************************************************** +#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready +#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready +#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready +#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready +#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready +#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready +#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready +#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRSSI register. +// +//***************************************************************************** +#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready +#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready +#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready +#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRI2C register. +// +//***************************************************************************** +#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready +#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready +#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready +#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRUSB register. +// +//***************************************************************************** +#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRCAN register. +// +//***************************************************************************** +#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready +#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRADC register. +// +//***************************************************************************** +#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready +#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRACMP register. +// +//***************************************************************************** +#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0 + // Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRPWM register. +// +//***************************************************************************** +#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready +#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRQEI register. +// +//***************************************************************************** +#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready +#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PREEPROM +// register. +// +//***************************************************************************** +#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the SYSCTL_PRWTIMER +// register. +// +//***************************************************************************** +#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose + // Timer 5 Peripheral Ready +#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose + // Timer 4 Peripheral Ready +#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose + // Timer 3 Peripheral Ready +#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose + // Timer 2 Peripheral Ready +#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose + // Timer 1 Peripheral Ready +#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose + // Timer 0 Peripheral Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_STAT register. +// +//***************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status +#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle +#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data +#define UDMA_STAT_STATE_RD_SRCENDP \ + 0x00000020 // Reading source end pointer +#define UDMA_STAT_STATE_RD_DSTENDP \ + 0x00000030 // Reading destination end pointer +#define UDMA_STAT_STATE_RD_SRCDAT \ + 0x00000040 // Reading source data +#define UDMA_STAT_STATE_WR_DSTDAT \ + 0x00000050 // Writing destination data +#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to + // clear +#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data +#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled +#define UDMA_STAT_STATE_DONE 0x00000090 // Done +#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +#define UDMA_STAT_DMACHANS_S 16 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CFG register. +// +//***************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CTLBASE register. +// +//***************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTBASE register. +// +//***************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_WAITSTAT register. +// +//***************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_SWREQ register. +// +//***************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTSET +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_USEBURSTCLR +// register. +// +//***************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKSET +// register. +// +//***************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_REQMASKCLR +// register. +// +//***************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENASET register. +// +//***************************************************************************** +#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ENACLR register. +// +//***************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTSET register. +// +//***************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ALTCLR register. +// +//***************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOSET register. +// +//***************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_PRIOCLR register. +// +//***************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_ERRCLR register. +// +//***************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHASGN register. +// +//***************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel + // assignment +#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel + // assignment + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHIS register. +// +//***************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP0 register. +// +//***************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP1 register. +// +//***************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP2 register. +// +//***************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_CHMAP3 register. +// +//***************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SRCENDP register. +// +//***************************************************************************** +#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer +#define UDMA_SRCENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_DSTENDP register. +// +//***************************************************************************** +#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer +#define UDMA_DSTENDP_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHCTL register. +// +//***************************************************************************** +#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment +#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word +#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word +#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment +#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word +#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment +#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word +#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word +#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment +#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word +#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers +#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst +#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_CHCTL_XFERMODE_STOP \ + 0x00000000 // Stop +#define UDMA_CHCTL_XFERMODE_BASIC \ + 0x00000001 // Basic +#define UDMA_CHCTL_XFERMODE_AUTO \ + 0x00000002 // Auto-Request +#define UDMA_CHCTL_XFERMODE_PINGPONG \ + 0x00000003 // Ping-Pong +#define UDMA_CHCTL_XFERMODE_MEM_SG \ + 0x00000004 // Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_MEM_SGA \ + 0x00000005 // Alternate Memory Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SG \ + 0x00000006 // Peripheral Scatter-Gather +#define UDMA_CHCTL_XFERMODE_PER_SGA \ + 0x00000007 // Alternate Peripheral + // Scatter-Gather +#define UDMA_CHCTL_XFERSIZE_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating + // Point +#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI33 register. +// +//***************************************************************************** +#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI33_INTD_S 29 +#define NVIC_PRI33_INTC_S 21 +#define NVIC_PRI33_INTB_S 13 +#define NVIC_PRI33_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI34 register. +// +//***************************************************************************** +#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt + // [4n+3] +#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt + // [4n+2] +#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt + // [4n+1] +#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt + // [4n] +#define NVIC_PRI34_INTD_S 29 +#define NVIC_PRI34_INTC_S 21 +#define NVIC_PRI34_INTB_S 13 +#define NVIC_PRI34_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 10 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPAC register. +// +//***************************************************************************** +#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only +#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access +#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access + // Privilege +#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied +#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only +#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCC register. +// +//***************************************************************************** +#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation + // Enable +#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable +#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready +#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready +#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready +#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready +#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode +#define NVIC_FPCC_USER 0x00000002 // User Privilege Level +#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPCA register. +// +//***************************************************************************** +#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address +#define NVIC_FPCA_ADDRESS_S 3 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FPDSC register. +// +//***************************************************************************** +#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default +#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default +#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default +#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default +#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode +#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) + // mode +#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity + // (RM) mode +#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED +#define SYSCTL_DID0_CLASS_BLIZZARD \ + 0x00050000 // Tiva(TM) C Series TM4C123-class + // microcontrollers + +#endif + +#endif // __TM4C123GH6PM_H__ diff --git a/CCS/mm/lib/io.c b/CCS/mm/lib/io.c new file mode 100644 index 0000000..aa607c8 --- /dev/null +++ b/CCS/mm/lib/io.c @@ -0,0 +1,41 @@ +#include "tivaware/hw_memmap.h" +#include "tivaware/rom.h" +#include + +int _read(int file, char* ptr, int len) { + int recieved = 0; + char current = '\0'; + while (len--) { + switch (current = ROM_UARTCharGet(UART0_BASE)) { + case '\r': + putchar('\n'); + putchar('\r'); + if (recieved == 0) { + break; + } + *ptr++ = '\n'; + return recieved + 1; + case 127: + if (recieved > 0) { + putchar('\b'); + putchar(' '); + putchar('\b'); + --ptr; + --recieved; + } + break; + default: + putchar(current); + *ptr++ = current; + ++recieved; + } + } + return recieved; +} + +int _write(int file, char* ptr, int len) { + for (int i = 0; i < len; ++ptr, ++i) { + while (!ROM_UARTCharPutNonBlocking(UART0_BASE, *ptr)) {} + } + return len; +} diff --git a/CCS/mm/lib/launchpad.c b/CCS/mm/lib/launchpad.c new file mode 100644 index 0000000..1461c4b --- /dev/null +++ b/CCS/mm/lib/launchpad.c @@ -0,0 +1,68 @@ +#include "tivaware/gpio.h" +#include "tivaware/hw_memmap.h" +#include "tivaware/pin_map.h" +#include "tivaware/rom.h" +#include "tivaware/sysctl.h" +#include "tivaware/uart.h" +#include +#include "v_tm4c123gh6pm.h" +#include + +void launchpad_init(void) { + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); + + // Port A + ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7); + + // Port F + ROM_GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, 0xE); + ROM_GPIOPinTypeGPIOInput(GPIO_PORTF_BASE, 0x11); + ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, 0x11, GPIO_STRENGTH_2MA, + GPIO_PIN_TYPE_STD_WPU); + // Port D + ROM_GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE, GPIO_PIN_0); + //ADC init + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); // enable ADC0 + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); // enable for AIN6 on D1 + ROM_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_1); + ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_PROCESSOR, 1); + ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0, + ADC_CTL_CH6 | ADC_CTL_IE | ADC_CTL_END); + + ROM_ADCSequenceEnable(ADC0_BASE, 3); + + ROM_ADCIntClear(ADC0_BASE, 3); + + // UART + ROM_GPIOPinConfigure(GPIO_PA0_U0RX); + ROM_GPIOPinConfigure(GPIO_PA1_U0TX); + ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_1 | GPIO_PIN_0); + ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200, + UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | + UART_CONFIG_PAR_NONE); + ROM_UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8); + ROM_UARTFIFOEnable(UART0_BASE); + ROM_UARTEnable(UART0_BASE); + // Disable buffered output + setvbuf(stdout, NULL, _IONBF, 0); +} + +bool left_switch(void) { + return !ROM_GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_4); +} + +bool right_switch(void) { + return !ROM_GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_0); +} + +void led_toggle(uint8_t led) { + ROM_GPIOPinWrite(GPIO_PORTF_BASE, led, + ~ROM_GPIOPinRead(GPIO_PORTF_BASE, led)); +} + +void led_write(uint8_t led, bool value) { + ROM_GPIOPinWrite(GPIO_PORTF_BASE, led, value ? led : 0); +} diff --git a/CCS/mm/lib/main.c b/CCS/mm/lib/main.c new file mode 100644 index 0000000..a47f1ff --- /dev/null +++ b/CCS/mm/lib/main.c @@ -0,0 +1,140 @@ +#include "launchpad.h" +#include "tivaware/gpio.h" +#include "tivaware/hw_ints.h" +#include "tivaware/hw_memmap.h" +#include "tivaware/rom.h" +#include "tivaware/sysctl.h" +#include "tivaware/timer.h" +#include "driverlib/adc.h" +#include "driverlib/debug.h" +#include "driverlib/fpu.h" +#include "driverlib/gpio.h" +#include "driverlib/pin_map.h" +#include "driverlib/sysctl.h" +#include +#include +#include +/* XDCtools Header files */ +#include +#include + +/* BIOS Header files */ +#include +#include + +/* TI-RTOS Header files */ +#include +#include + +/* Example/Board Header files */ +#include "Board.h" +#include "v_tm4c123gh6pm.h" + +#define TASKSTACKSIZE 1024 + +extern void disable_interrupts(void); +extern void enable_interrupts(void); + +volatile uint32_t delay_timer; + +void systick_handler(void) { + --delay_timer; +} + +void wait_ms(uint32_t t) { + +} + +void blink_success(void) { + led_write(GREEN_LED, true); + Task_sleep(250); + led_write(GREEN_LED, false); +} + +void timer0_init() { + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); + ROM_TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC); + ROM_TimerLoadSet(TIMER0_BASE, TIMER_A, 800000); // 100Hz + ROM_IntEnable(INT_TIMER0A); + ROM_TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT); + ROM_TimerEnable(TIMER0_BASE, TIMER_BOTH); +} + +void timer0a_handler(void) { + ROM_TimerIntClear(TIMER0_BASE, TIMER_A); + ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_7, + ~ROM_GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_7)); +} + +void LEDtask(UArg arg0, UArg arg1) +{ + while (1) { + blink_success(); + printf("left: %d\t\tright:%d\n\r", left_switch(), right_switch()); + Task_sleep(1000); + } +} + +void Task_WallDetector(UArg arg0, UArg arg1) { + // cycle through all 4 sensors + + // init + SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0); + + /* + * Test circuit Pinout + * Emitter On/Off Gate: PD0 + * Receiver Voltage Level: PD1 + */ + while(1) + { + // 1. turn on emitter + GPIO_PORTD_DATA_R = GPIO_PORTD_DATA_R | 0x0001; + // 2. wait for emitter to fully turn on + Task_sleep(1); + // 3. read receiver voltage using ADC + + uint32_t result; + ADC0_PSSI_R = 0x0008; + while((ADC0_RIS_R&0x08)==0){}; + result = ADC0_SSFIFO3_R&0xFFF; + ADC0_ISC_R = 0x0008; + System_printf("%d\n",result); + System_flush(); + + // 4. turn off emitter + GPIO_PORTD_DATA_R = GPIO_PORTD_DATA_R & 0xFFFE; + + Task_sleep(1000); + } +} + +Task_Struct tsk0Struct; +Task_Struct tsk1Struct; +UInt8 tsk0Stack[TASKSTACKSIZE]; +UInt8 tsk1Stack[TASKSTACKSIZE]; + +int main(void) { + ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | + SYSCTL_OSC_MAIN); + ROM_SysTickEnable(); + launchpad_init(); + + Board_initGeneral(); + Board_initPWM(); + Board_initGPIO(); + + timer0_init(); + + // Task Initialization + Task_Params tskParams; + Task_Params_init(&tskParams); + tskParams.stackSize = TASKSTACKSIZE; + tskParams.stack = &tsk0Stack; + tskParams.arg0 = 0; + +// Task_construct(&tsk0Struct, (Task_FuncPtr)LEDtask, &tskParams, NULL); + Task_construct(&tsk1Struct, (Task_FuncPtr)Task_WallDetector, &tskParams, NULL); + + BIOS_start(); // This must be the very last line! +} diff --git a/CCS/mm/lib/motors.c b/CCS/mm/lib/motors.c new file mode 100644 index 0000000..80f34f5 --- /dev/null +++ b/CCS/mm/lib/motors.c @@ -0,0 +1,115 @@ +#include "motors.h" +#include "tivaware/gpio.h" +#include "tivaware/hw_memmap.h" +#include "tivaware/pin_map.h" +#include "tivaware/qei.h" +#include "tivaware/rom.h" +#include "tivaware/sysctl.h" +/* XDCtools Header files */ +#include +#include + +/* BIOS Header files */ +#include +#include + +/* TI-RTOS Header files */ +#include +#include + +/* Example/Board Header files */ +#include "Board.h" + +// TODO: init pwm for drivers +void init_motors() { + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_QEI0); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_QEI1); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC); + ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); + ROM_GPIOPinConfigure(GPIO_PD6_PHA0); + ROM_GPIOPinConfigure(GPIO_PD7_PHB0); + ROM_GPIOPinConfigure(GPIO_PC5_PHA1); + ROM_GPIOPinConfigure(GPIO_PC6_PHB1); + ROM_GPIOPinTypeQEI(GPIO_PORTD_BASE, GPIO_PIN_6 | GPIO_PIN_7); + ROM_GPIOPinTypeQEI(GPIO_PORTC_BASE, GPIO_PIN_5 | GPIO_PIN_6); + ROM_QEIConfigure(QEI0_BASE, QEI_CONFIG_CAPTURE_A_B | QEI_CONFIG_SWAP, + UINT32_MAX); + ROM_QEIConfigure(QEI1_BASE, QEI_CONFIG_CAPTURE_A_B | QEI_CONFIG_NO_SWAP, + UINT32_MAX); + ROM_QEIVelocityConfigure(QEI0_BASE, QEI_VELDIV_1, VELOCITY_PERIOD); + ROM_QEIVelocityConfigure(QEI1_BASE, QEI_VELDIV_1, VELOCITY_PERIOD); + ROM_QEIEnable(QEI0_BASE); + ROM_QEIEnable(QEI1_BASE); + ROM_QEIVelocityEnable(QEI0_BASE); + ROM_QEIVelocityEnable(QEI1_BASE); +} + +int32_t left_pos(void) { + return ROM_QEIPositionGet(QEI0_BASE); +} + +int32_t right_pos(void) { + return ROM_QEIPositionGet(QEI1_BASE); +} + +uint32_t left_speed(void) { + return ROM_QEIVelocityGet(QEI0_BASE); +} +uint32_t right_speed(void) { + return ROM_QEIVelocityGet(QEI1_BASE); +} + +void reset_enc(void) { + ROM_QEIPositionSet(QEI0_BASE, 0); + ROM_QEIPositionSet(QEI1_BASE, 0); +} + +Void pwmMotorFxn(UArg arg0, UArg arg1)//this is currently a copy pasted LED example renamed to Motor +{ + PWM_Handle pwm1; + PWM_Handle pwm2 = NULL; + PWM_Params params; + uint16_t pwmPeriod = 3000; // Period and duty in microseconds + uint16_t duty = 0; + uint16_t dutyInc = 100; + + PWM_Params_init(¶ms); + params.period = pwmPeriod; + pwm1 = PWM_open(Board_PWM0, ¶ms); + if (pwm1 == NULL) { + System_abort("Board_PWM0 did not open"); + } + + if (Board_PWM1 != Board_PWM0) { + params.polarity = PWM_POL_ACTIVE_LOW; + pwm2 = PWM_open(Board_PWM1, ¶ms); + if (pwm2 == NULL) { + System_abort("Board_PWM1 did not open"); + } + } + + /* Loop forever incrementing the PWM duty */ + while (1) { + PWM_setDuty(pwm1, duty); + + if (pwm2) { + PWM_setDuty(pwm2, duty); + } + + duty = (duty + dutyInc); + if (duty == pwmPeriod || (!duty)) { + dutyInc = - dutyInc; + } + + Task_sleep((UInt) arg0); + } +} + + +void set_left(float speed) { + // TODO +} + +void set_right(float speed) { + // TODO +} diff --git a/CCS/mm/makefile.defs b/CCS/mm/makefile.defs new file mode 100644 index 0000000..5a0353c --- /dev/null +++ b/CCS/mm/makefile.defs @@ -0,0 +1,24 @@ +#File used to help "Clean Project" in CCS completely clean the kernel files +CFG_SRCDIR = ../src + +ifneq (,$(findstring :,$(WINDIR)$(windir)$(COMSPEC)$(comspec))) + # if Windows, use copy to touch file dates + TOUCH = copy /b $(subst /,\,$@)+,, $(subst /,\,$@) +else + TOUCH = touch $@ +endif + +# include Config generated top-level makefile +-include $(CFG_SRCDIR)/makefile.libs + +ifneq (clean,$(MAKECMDGOALS)) +# ensure this file is reloaded when .cfg files change but after config runs +$(CFG_SRCDIR)/makefile.libs: $(GEN_OPTS) $(CFG_SRCS) + -@$(if $(wildcard $@),$(TOUCH),:) +endif + +#add generated makefile to list of files to delete during a clean +GEN_MISC_FILES__QUOTED += "$(CFG_SRCDIR)/makefile.libs" + +#add generated source dir to list of directories to delete during a clean +#GEN_MISC_DIRS__QTD += "$(CFG_SRCDIR)" diff --git a/CCS/mm/src/.exclude b/CCS/mm/src/.exclude new file mode 100644 index 0000000..8c86331 --- /dev/null +++ b/CCS/mm/src/.exclude @@ -0,0 +1 @@ +This file exists to prevent Eclipse/CDT from adding the C sources contained in this directory (or below) to any enclosing project. diff --git a/CCS/mm/src/inc/launchpad.h b/CCS/mm/src/inc/launchpad.h new file mode 100644 index 0000000..0b8ffb2 --- /dev/null +++ b/CCS/mm/src/inc/launchpad.h @@ -0,0 +1,26 @@ +#include +#include + +// PF0 - Left button +// PF1 - Red LED +// PF2 - Blue LED +// PF3 - Green LED +// PF4 - Right button +// PA0 - USB UART RX +// PA1 - USB UART TX + +// Initializes the LED and button pins on the launchpad, as well as +// UART <-> USB through the debugger. +void launchpad_init(void); + +#define RED_LED 2 +#define BLUE_LED 4 +#define GREEN_LED 8 + +bool left_switch(void); + +bool right_switch(void); + +void led_toggle(uint8_t led); + +void led_write(uint8_t led, bool value); diff --git a/CCS/mm/src/inc/motors.h b/CCS/mm/src/inc/motors.h new file mode 100644 index 0000000..aedee56 --- /dev/null +++ b/CCS/mm/src/inc/motors.h @@ -0,0 +1,16 @@ +#include + +const int VELOCITY_PERIOD = 4000; // TODO: investigate accuracy/latency tradeoff + +void init_motors(void); + +void reset_enc(void); + +int32_t left_pos(void); +int32_t right_pos(void); + +uint32_t left_speed(void); +uint32_t right_speed(void); + +void set_left(float speed); +void set_right(float speed); diff --git a/CCS/mm/src/inc/tivaware/adc.h b/CCS/mm/src/inc/tivaware/adc.h new file mode 100644 index 0000000..5fda3df --- /dev/null +++ b/CCS/mm/src/inc/tivaware/adc.h @@ -0,0 +1,329 @@ +#include +#include +//***************************************************************************** +// +// adc.h - ADC headers for using the ADC driver functions. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ADC_H__ +#define __DRIVERLIB_ADC_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceConfigure as the ui32Trigger +// parameter. +// +//***************************************************************************** +#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event +#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event +#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event +#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event +#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event +#define ADC_TRIGGER_TIMER 0x00000005 // Timer event +#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event +#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event +#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event +#define ADC_TRIGGER_PWM3 0x00000009 // PWM3 event +#define ADC_TRIGGER_NEVER 0x0000000E // Never Trigger +#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event +#define ADC_TRIGGER_PWM_MOD0 0x00000000 // PWM triggers from PWM0 +#define ADC_TRIGGER_PWM_MOD1 0x00000010 // PWM triggers from PWM1 + +//***************************************************************************** +// +// Values that can be passed to ADCSequenceStepConfigure as the ui32Config +// parameter. +// +//***************************************************************************** +#define ADC_CTL_TS 0x00000080 // Temperature sensor select +#define ADC_CTL_IE 0x00000040 // Interrupt enable +#define ADC_CTL_END 0x00000020 // Sequence end select +#define ADC_CTL_D 0x00000010 // Differential select +#define ADC_CTL_CH0 0x00000000 // Input channel 0 +#define ADC_CTL_CH1 0x00000001 // Input channel 1 +#define ADC_CTL_CH2 0x00000002 // Input channel 2 +#define ADC_CTL_CH3 0x00000003 // Input channel 3 +#define ADC_CTL_CH4 0x00000004 // Input channel 4 +#define ADC_CTL_CH5 0x00000005 // Input channel 5 +#define ADC_CTL_CH6 0x00000006 // Input channel 6 +#define ADC_CTL_CH7 0x00000007 // Input channel 7 +#define ADC_CTL_CH8 0x00000008 // Input channel 8 +#define ADC_CTL_CH9 0x00000009 // Input channel 9 +#define ADC_CTL_CH10 0x0000000A // Input channel 10 +#define ADC_CTL_CH11 0x0000000B // Input channel 11 +#define ADC_CTL_CH12 0x0000000C // Input channel 12 +#define ADC_CTL_CH13 0x0000000D // Input channel 13 +#define ADC_CTL_CH14 0x0000000E // Input channel 14 +#define ADC_CTL_CH15 0x0000000F // Input channel 15 +#define ADC_CTL_CH16 0x00000100 // Input channel 16 +#define ADC_CTL_CH17 0x00000101 // Input channel 17 +#define ADC_CTL_CH18 0x00000102 // Input channel 18 +#define ADC_CTL_CH19 0x00000103 // Input channel 19 +#define ADC_CTL_CH20 0x00000104 // Input channel 20 +#define ADC_CTL_CH21 0x00000105 // Input channel 21 +#define ADC_CTL_CH22 0x00000106 // Input channel 22 +#define ADC_CTL_CH23 0x00000107 // Input channel 23 +#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0 +#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1 +#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2 +#define ADC_CTL_CMP3 0x000B0000 // Select Comparator 3 +#define ADC_CTL_CMP4 0x000C0000 // Select Comparator 4 +#define ADC_CTL_CMP5 0x000D0000 // Select Comparator 5 +#define ADC_CTL_CMP6 0x000E0000 // Select Comparator 6 +#define ADC_CTL_CMP7 0x000F0000 // Select Comparator 7 +#define ADC_CTL_SHOLD_4 0x00000000 // Sample and hold 4 ADC clocks +#define ADC_CTL_SHOLD_8 0x00200000 // Sample and hold 8 ADC clocks +#define ADC_CTL_SHOLD_16 0x00400000 // Sample and hold 16 ADC clocks +#define ADC_CTL_SHOLD_32 0x00600000 // Sample and hold 32 ADC clocks +#define ADC_CTL_SHOLD_64 0x00800000 // Sample and hold 64 ADC clocks +#define ADC_CTL_SHOLD_128 0x00A00000 // Sample and hold 128 ADC clocks +#define ADC_CTL_SHOLD_256 0x00C00000 // Sample and hold 256 ADC clocks + +//***************************************************************************** +// +// Values that can be passed to ADCComparatorConfigure as part of the +// ui32Config parameter. +// +//***************************************************************************** +#define ADC_COMP_TRIG_NONE 0x00000000 // Trigger Disabled +#define ADC_COMP_TRIG_LOW_ALWAYS \ + 0x00001000 // Trigger Low Always +#define ADC_COMP_TRIG_LOW_ONCE 0x00001100 // Trigger Low Once +#define ADC_COMP_TRIG_LOW_HALWAYS \ + 0x00001200 // Trigger Low Always (Hysteresis) +#define ADC_COMP_TRIG_LOW_HONCE 0x00001300 // Trigger Low Once (Hysteresis) +#define ADC_COMP_TRIG_MID_ALWAYS \ + 0x00001400 // Trigger Mid Always +#define ADC_COMP_TRIG_MID_ONCE 0x00001500 // Trigger Mid Once +#define ADC_COMP_TRIG_HIGH_ALWAYS \ + 0x00001C00 // Trigger High Always +#define ADC_COMP_TRIG_HIGH_ONCE 0x00001D00 // Trigger High Once +#define ADC_COMP_TRIG_HIGH_HALWAYS \ + 0x00001E00 // Trigger High Always (Hysteresis) +#define ADC_COMP_TRIG_HIGH_HONCE \ + 0x00001F00 // Trigger High Once (Hysteresis) + +#define ADC_COMP_INT_NONE 0x00000000 // Interrupt Disabled +#define ADC_COMP_INT_LOW_ALWAYS \ + 0x00000010 // Interrupt Low Always +#define ADC_COMP_INT_LOW_ONCE 0x00000011 // Interrupt Low Once +#define ADC_COMP_INT_LOW_HALWAYS \ + 0x00000012 // Interrupt Low Always + // (Hysteresis) +#define ADC_COMP_INT_LOW_HONCE 0x00000013 // Interrupt Low Once (Hysteresis) +#define ADC_COMP_INT_MID_ALWAYS \ + 0x00000014 // Interrupt Mid Always +#define ADC_COMP_INT_MID_ONCE 0x00000015 // Interrupt Mid Once +#define ADC_COMP_INT_HIGH_ALWAYS \ + 0x0000001C // Interrupt High Always +#define ADC_COMP_INT_HIGH_ONCE 0x0000001D // Interrupt High Once +#define ADC_COMP_INT_HIGH_HALWAYS \ + 0x0000001E // Interrupt High Always + // (Hysteresis) +#define ADC_COMP_INT_HIGH_HONCE \ + 0x0000001F // Interrupt High Once (Hysteresis) + +//***************************************************************************** +// +// Values that can be used to modify the sequence number passed to +// ADCProcessorTrigger in order to get cross-module synchronous processor +// triggers. +// +//***************************************************************************** +#define ADC_TRIGGER_WAIT 0x08000000 // Wait for the synchronous trigger +#define ADC_TRIGGER_SIGNAL 0x80000000 // Signal the synchronous trigger + +//***************************************************************************** +// +// Values that can be passed to ADCPhaseDelaySet as the ui32Phase parameter and +// returned from ADCPhaseDelayGet. +// +//***************************************************************************** +#define ADC_PHASE_0 0x00000000 // 0 degrees +#define ADC_PHASE_22_5 0x00000001 // 22.5 degrees +#define ADC_PHASE_45 0x00000002 // 45 degrees +#define ADC_PHASE_67_5 0x00000003 // 67.5 degrees +#define ADC_PHASE_90 0x00000004 // 90 degrees +#define ADC_PHASE_112_5 0x00000005 // 112.5 degrees +#define ADC_PHASE_135 0x00000006 // 135 degrees +#define ADC_PHASE_157_5 0x00000007 // 157.5 degrees +#define ADC_PHASE_180 0x00000008 // 180 degrees +#define ADC_PHASE_202_5 0x00000009 // 202.5 degrees +#define ADC_PHASE_225 0x0000000A // 225 degrees +#define ADC_PHASE_247_5 0x0000000B // 247.5 degrees +#define ADC_PHASE_270 0x0000000C // 270 degrees +#define ADC_PHASE_292_5 0x0000000D // 292.5 degrees +#define ADC_PHASE_315 0x0000000E // 315 degrees +#define ADC_PHASE_337_5 0x0000000F // 337.5 degrees + +//***************************************************************************** +// +// Values that can be passed to ADCReferenceSet as the ui32Ref parameter. +// +//***************************************************************************** +#define ADC_REF_INT 0x00000000 // Internal reference +#define ADC_REF_EXT_3V 0x00000001 // External 3V reference + +//***************************************************************************** +// +// Values that can be passed to ADCIntDisableEx(), ADCIntEnableEx(), +// ADCIntClearEx() and ADCIntStatusEx(). +// +//***************************************************************************** +#define ADC_INT_SS0 0x00000001 +#define ADC_INT_SS1 0x00000002 +#define ADC_INT_SS2 0x00000004 +#define ADC_INT_SS3 0x00000008 +#define ADC_INT_DMA_SS0 0x00000100 +#define ADC_INT_DMA_SS1 0x00000200 +#define ADC_INT_DMA_SS2 0x00000400 +#define ADC_INT_DMA_SS3 0x00000800 +#define ADC_INT_DCON_SS0 0x00010000 +#define ADC_INT_DCON_SS1 0x00020000 +#define ADC_INT_DCON_SS2 0x00040000 +#define ADC_INT_DCON_SS3 0x00080000 + +//***************************************************************************** +// +// Values that can be passed to ADCClockConfigSet() and ADCClockConfigGet(). +// +//***************************************************************************** +#define ADC_CLOCK_RATE_FULL 0x00000070 +#define ADC_CLOCK_RATE_HALF 0x00000050 +#define ADC_CLOCK_RATE_FOURTH 0x00000030 +#define ADC_CLOCK_RATE_EIGHTH 0x00000010 +#define ADC_CLOCK_SRC_PLL 0x00000000 +#define ADC_CLOCK_SRC_PIOSC 0x00000001 +#define ADC_CLOCK_SRC_ALTCLK 0x00000001 +#define ADC_CLOCK_SRC_MOSC 0x00000002 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void ADCIntRegister(uint32_t ui32Base, uint32_t ui32SequenceNum, + void (*pfnHandler)(void)); +extern void ADCIntUnregister(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCIntDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCIntEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern uint32_t ADCIntStatus(uint32_t ui32Base, uint32_t ui32SequenceNum, + bool bMasked); +extern void ADCIntClear(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceDisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceConfigure(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t ui32Trigger, uint32_t ui32Priority); +extern void ADCSequenceStepConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Step, uint32_t ui32Config); +extern int32_t ADCSequenceOverflow(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCSequenceOverflowClear(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern int32_t ADCSequenceUnderflow(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCSequenceUnderflowClear(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern int32_t ADCSequenceDataGet(uint32_t ui32Base, uint32_t ui32SequenceNum, + uint32_t *pui32Buffer); +extern void ADCProcessorTrigger(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSoftwareOversampleConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Factor); +extern void ADCSoftwareOversampleStepConfigure(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t ui32Step, + uint32_t ui32Config); +extern void ADCSoftwareOversampleDataGet(uint32_t ui32Base, + uint32_t ui32SequenceNum, + uint32_t *pui32Buffer, + uint32_t ui32Count); +extern void ADCHardwareOversampleConfigure(uint32_t ui32Base, + uint32_t ui32Factor); +extern void ADCClockConfigSet(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32ClockDiv); +extern uint32_t ADCClockConfigGet(uint32_t ui32Base, uint32_t *pui32ClockDiv); + +extern void ADCComparatorConfigure(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32Config); +extern void ADCComparatorRegionSet(uint32_t ui32Base, uint32_t ui32Comp, + uint32_t ui32LowRef, uint32_t ui32HighRef); +extern void ADCComparatorReset(uint32_t ui32Base, uint32_t ui32Comp, + bool bTrigger, bool bInterrupt); +extern void ADCComparatorIntDisable(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern void ADCComparatorIntEnable(uint32_t ui32Base, + uint32_t ui32SequenceNum); +extern uint32_t ADCComparatorIntStatus(uint32_t ui32Base); +extern void ADCComparatorIntClear(uint32_t ui32Base, uint32_t ui32Status); +extern void ADCIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void ADCIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t ADCIntStatusEx(uint32_t ui32Base, bool bMasked); +extern void ADCIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void ADCSequenceDMAEnable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern void ADCSequenceDMADisable(uint32_t ui32Base, uint32_t ui32SequenceNum); +extern bool ADCBusy(uint32_t ui32Base); +extern void ADCReferenceSet(uint32_t ui32Base, uint32_t ui32Ref); +extern uint32_t ADCReferenceGet(uint32_t ui32Base); +extern void ADCPhaseDelaySet(uint32_t ui32Base, uint32_t ui32Phase); +extern uint32_t ADCPhaseDelayGet(uint32_t ui32Base); +extern void ADCSampleRateSet(uint32_t ui32Base, uint32_t ui32ADCClock, + uint32_t ui32Rate); +extern uint32_t ADCSampleRateGet(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_ADC_H__ diff --git a/CCS/mm/src/inc/tivaware/gpio.h b/CCS/mm/src/inc/tivaware/gpio.h new file mode 100644 index 0000000..1de14e8 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/gpio.h @@ -0,0 +1,206 @@ +#include +#include +//***************************************************************************** +// +// gpio.h - Defines and Macros for GPIO API. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_GPIO_H__ +#define __DRIVERLIB_GPIO_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following values define the bit field for the ui8Pins argument to +// several of the APIs. +// +//***************************************************************************** +#define GPIO_PIN_0 0x00000001 // GPIO pin 0 +#define GPIO_PIN_1 0x00000002 // GPIO pin 1 +#define GPIO_PIN_2 0x00000004 // GPIO pin 2 +#define GPIO_PIN_3 0x00000008 // GPIO pin 3 +#define GPIO_PIN_4 0x00000010 // GPIO pin 4 +#define GPIO_PIN_5 0x00000020 // GPIO pin 5 +#define GPIO_PIN_6 0x00000040 // GPIO pin 6 +#define GPIO_PIN_7 0x00000080 // GPIO pin 7 + +//***************************************************************************** +// +// Values that can be passed to GPIODirModeSet as the ui32PinIO parameter, and +// returned from GPIODirModeGet. +// +//***************************************************************************** +#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input +#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output +#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function + +//***************************************************************************** +// +// Values that can be passed to GPIOIntTypeSet as the ui32IntType parameter, +// and returned from GPIOIntTypeGet. +// +//***************************************************************************** +#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge +#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge +#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges +#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level +#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level +#define GPIO_DISCRETE_INT 0x00010000 // Interrupt for individual pins + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32Strength parameter, +// and returned by GPIOPadConfigGet in the *pui32Strength parameter. +// +//***************************************************************************** +#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength +#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength +#define GPIO_STRENGTH_6MA 0x00000065 // 6mA drive strength +#define GPIO_STRENGTH_8MA 0x00000066 // 8mA drive strength +#define GPIO_STRENGTH_8MA_SC 0x0000006E // 8mA drive with slew rate control +#define GPIO_STRENGTH_10MA 0x00000075 // 10mA drive strength +#define GPIO_STRENGTH_12MA 0x00000077 // 12mA drive strength + +//***************************************************************************** +// +// Values that can be passed to GPIOPadConfigSet as the ui32PadType parameter, +// and returned by GPIOPadConfigGet in the *pui32PadType parameter. +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull +#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up +#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down +#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain +#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator +#define GPIO_PIN_TYPE_WAKE_HIGH 0x00000208 // Hibernate wake, high +#define GPIO_PIN_TYPE_WAKE_LOW 0x00000108 // Hibernate wake, low + +//***************************************************************************** +// +// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions +// in the ui32IntFlags parameter. +// +//***************************************************************************** +#define GPIO_INT_PIN_0 0x00000001 +#define GPIO_INT_PIN_1 0x00000002 +#define GPIO_INT_PIN_2 0x00000004 +#define GPIO_INT_PIN_3 0x00000008 +#define GPIO_INT_PIN_4 0x00000010 +#define GPIO_INT_PIN_5 0x00000020 +#define GPIO_INT_PIN_6 0x00000040 +#define GPIO_INT_PIN_7 0x00000080 +#define GPIO_INT_DMA 0x00000100 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void GPIODirModeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32PinIO); +extern uint32_t GPIODirModeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOIntTypeSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32IntType); +extern uint32_t GPIOIntTypeGet(uint32_t ui32Port, uint8_t ui8Pin); +extern void GPIOPadConfigSet(uint32_t ui32Port, uint8_t ui8Pins, + uint32_t ui32Strength, uint32_t ui32PadType); +extern void GPIOPadConfigGet(uint32_t ui32Port, uint8_t ui8Pin, + uint32_t *pui32Strength, uint32_t *pui32PadType); +extern void GPIOIntEnable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntDisable(uint32_t ui32Port, uint32_t ui32IntFlags); +extern uint32_t GPIOIntStatus(uint32_t ui32Port, bool bMasked); +extern void GPIOIntClear(uint32_t ui32Port, uint32_t ui32IntFlags); +extern void GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void)); +extern void GPIOIntUnregister(uint32_t ui32Port); +extern void GPIOIntRegisterPin(uint32_t ui32Port, uint32_t ui32Pin, + void (*pfnIntHandler)(void)); +extern void GPIOIntUnregisterPin(uint32_t ui32Port, uint32_t ui32Pin); +extern int32_t GPIOPinRead(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinWrite(uint32_t ui32Port, uint8_t ui8Pins, uint8_t ui8Val); +extern void GPIOPinConfigure(uint32_t ui32PinConfig); +extern void GPIOPinTypeADC(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeCAN(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparator(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeComparatorOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeDIVSCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEPI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetLED(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeEthernetMII(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOInput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutput(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeGPIOOutputOD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeHibernateRTCCLK(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2C(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeI2CSCL(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeLCD(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeOneWire(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypePWM(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeQEI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeSSI(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTimer(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeTrace(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUART(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBAnalog(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeUSBDigital(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeHigh(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOPinTypeWakeLow(uint32_t ui32Port, uint8_t ui8Pins); +extern uint32_t GPIOPinWakeStatus(uint32_t ui32Port); +extern void GPIODMATriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIODMATriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerEnable(uint32_t ui32Port, uint8_t ui8Pins); +extern void GPIOADCTriggerDisable(uint32_t ui32Port, uint8_t ui8Pins); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_GPIO_H__ diff --git a/CCS/mm/src/inc/tivaware/hw_ints.h b/CCS/mm/src/inc/tivaware/hw_ints.h new file mode 100644 index 0000000..54c655d --- /dev/null +++ b/CCS/mm/src/inc/tivaware/hw_ints.h @@ -0,0 +1,493 @@ +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series +// MCUs. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +#define TARGET_IS_TM4C123_RB1 + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// TM4C123 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C123 16 // GPIO Port A +#define INT_GPIOB_TM4C123 17 // GPIO Port B +#define INT_GPIOC_TM4C123 18 // GPIO Port C +#define INT_GPIOD_TM4C123 19 // GPIO Port D +#define INT_GPIOE_TM4C123 20 // GPIO Port E +#define INT_UART0_TM4C123 21 // UART0 +#define INT_UART1_TM4C123 22 // UART1 +#define INT_SSI0_TM4C123 23 // SSI0 +#define INT_I2C0_TM4C123 24 // I2C0 +#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault +#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0 +#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1 +#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2 +#define INT_QEI0_TM4C123 29 // QEI0 +#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C123 41 // Analog Comparator 0 +#define INT_COMP1_TM4C123 42 // Analog Comparator 1 +#define INT_COMP2_TM4C123 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C123 44 // System Control +#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM + // Control +#define INT_GPIOF_TM4C123 46 // GPIO Port F +#define INT_GPIOG_TM4C123 47 // GPIO Port G +#define INT_GPIOH_TM4C123 48 // GPIO Port H +#define INT_UART2_TM4C123 49 // UART2 +#define INT_SSI1_TM4C123 50 // SSI1 +#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C123 52 // Timer 3B +#define INT_I2C1_TM4C123 53 // I2C1 +#define INT_QEI1_TM4C123 54 // QEI1 +#define INT_CAN0_TM4C123 55 // CAN0 +#define INT_CAN1_TM4C123 56 // CAN1 +#define INT_HIBERNATE_TM4C123 59 // Hibernation Module +#define INT_USB0_TM4C123 60 // USB +#define INT_PWM0_3_TM4C123 61 // PWM Generator 3 +#define INT_UDMA_TM4C123 62 // uDMA Software +#define INT_UDMAERR_TM4C123 63 // uDMA Error +#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3 +#define INT_GPIOJ_TM4C123 70 // GPIO Port J +#define INT_GPIOK_TM4C123 71 // GPIO Port K +#define INT_GPIOL_TM4C123 72 // GPIO Port L +#define INT_SSI2_TM4C123 73 // SSI2 +#define INT_SSI3_TM4C123 74 // SSI3 +#define INT_UART3_TM4C123 75 // UART3 +#define INT_UART4_TM4C123 76 // UART4 +#define INT_UART5_TM4C123 77 // UART5 +#define INT_UART6_TM4C123 78 // UART6 +#define INT_UART7_TM4C123 79 // UART7 +#define INT_I2C2_TM4C123 84 // I2C2 +#define INT_I2C3_TM4C123 85 // I2C3 +#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A +#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B +#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A +#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B +#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A +#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B +#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A +#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B +#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A +#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B +#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A +#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B +#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A +#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B +#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A +#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B +#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise) +#define INT_I2C4_TM4C123 125 // I2C4 +#define INT_I2C5_TM4C123 126 // I2C5 +#define INT_GPIOM_TM4C123 127 // GPIO Port M +#define INT_GPION_TM4C123 128 // GPIO Port N +#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C123 133 // GPIO Port P1 +#define INT_GPIOP2_TM4C123 134 // GPIO Port P2 +#define INT_GPIOP3_TM4C123 135 // GPIO Port P3 +#define INT_GPIOP4_TM4C123 136 // GPIO Port P4 +#define INT_GPIOP5_TM4C123 137 // GPIO Port P5 +#define INT_GPIOP6_TM4C123 138 // GPIO Port P6 +#define INT_GPIOP7_TM4C123 139 // GPIO Port P7 +#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7 +#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0 +#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1 +#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2 +#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3 +#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault +#define NUM_INTERRUPTS_TM4C123 155 + +//***************************************************************************** +// +// TM4C129 Class Interrupts +// +//***************************************************************************** +#define INT_GPIOA_TM4C129 16 // GPIO Port A +#define INT_GPIOB_TM4C129 17 // GPIO Port B +#define INT_GPIOC_TM4C129 18 // GPIO Port C +#define INT_GPIOD_TM4C129 19 // GPIO Port D +#define INT_GPIOE_TM4C129 20 // GPIO Port E +#define INT_UART0_TM4C129 21 // UART0 +#define INT_UART1_TM4C129 22 // UART1 +#define INT_SSI0_TM4C129 23 // SSI0 +#define INT_I2C0_TM4C129 24 // I2C0 +#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault +#define INT_PWM0_0_TM4C129 26 // PWM Generator 0 +#define INT_PWM0_1_TM4C129 27 // PWM Generator 1 +#define INT_PWM0_2_TM4C129 28 // PWM Generator 2 +#define INT_QEI0_TM4C129 29 // QEI0 +#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0 +#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1 +#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2 +#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3 +#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1 +#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A +#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B +#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A +#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B +#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A +#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B +#define INT_COMP0_TM4C129 41 // Analog Comparator 0 +#define INT_COMP1_TM4C129 42 // Analog Comparator 1 +#define INT_COMP2_TM4C129 43 // Analog Comparator 2 +#define INT_SYSCTL_TM4C129 44 // System Control +#define INT_FLASH_TM4C129 45 // Flash Memory Control +#define INT_GPIOF_TM4C129 46 // GPIO Port F +#define INT_GPIOG_TM4C129 47 // GPIO Port G +#define INT_GPIOH_TM4C129 48 // GPIO Port H +#define INT_UART2_TM4C129 49 // UART2 +#define INT_SSI1_TM4C129 50 // SSI1 +#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A +#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B +#define INT_I2C1_TM4C129 53 // I2C1 +#define INT_CAN0_TM4C129 54 // CAN 0 +#define INT_CAN1_TM4C129 55 // CAN1 +#define INT_EMAC0_TM4C129 56 // Ethernet MAC +#define INT_HIBERNATE_TM4C129 57 // HIB +#define INT_USB0_TM4C129 58 // USB MAC +#define INT_PWM0_3_TM4C129 59 // PWM Generator 3 +#define INT_UDMA_TM4C129 60 // uDMA 0 Software +#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error +#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0 +#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1 +#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2 +#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3 +#define INT_EPI0_TM4C129 66 // EPI 0 +#define INT_GPIOJ_TM4C129 67 // GPIO Port J +#define INT_GPIOK_TM4C129 68 // GPIO Port K +#define INT_GPIOL_TM4C129 69 // GPIO Port L +#define INT_SSI2_TM4C129 70 // SSI 2 +#define INT_SSI3_TM4C129 71 // SSI 3 +#define INT_UART3_TM4C129 72 // UART 3 +#define INT_UART4_TM4C129 73 // UART 4 +#define INT_UART5_TM4C129 74 // UART 5 +#define INT_UART6_TM4C129 75 // UART 6 +#define INT_UART7_TM4C129 76 // UART 7 +#define INT_I2C2_TM4C129 77 // I2C 2 +#define INT_I2C3_TM4C129 78 // I2C 3 +#define INT_TIMER4A_TM4C129 79 // Timer 4A +#define INT_TIMER4B_TM4C129 80 // Timer 4B +#define INT_TIMER5A_TM4C129 81 // Timer 5A +#define INT_TIMER5B_TM4C129 82 // Timer 5B +#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception + // (imprecise) +#define INT_I2C4_TM4C129 86 // I2C 4 +#define INT_I2C5_TM4C129 87 // I2C 5 +#define INT_GPIOM_TM4C129 88 // GPIO Port M +#define INT_GPION_TM4C129 89 // GPIO Port N +#define INT_TAMPER0_TM4C129 91 // Tamper +#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0) +#define INT_GPIOP1_TM4C129 93 // GPIO Port P1 +#define INT_GPIOP2_TM4C129 94 // GPIO Port P2 +#define INT_GPIOP3_TM4C129 95 // GPIO Port P3 +#define INT_GPIOP4_TM4C129 96 // GPIO Port P4 +#define INT_GPIOP5_TM4C129 97 // GPIO Port P5 +#define INT_GPIOP6_TM4C129 98 // GPIO Port P6 +#define INT_GPIOP7_TM4C129 99 // GPIO Port P7 +#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0) +#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1 +#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2 +#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3 +#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4 +#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5 +#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6 +#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7 +#define INT_GPIOR_TM4C129 108 // GPIO Port R +#define INT_GPIOS_TM4C129 109 // GPIO Port S +#define INT_SHA0_TM4C129 110 // SHA/MD5 +#define INT_AES0_TM4C129 111 // AES +#define INT_DES0_TM4C129 112 // DES +#define INT_LCD0_TM4C129 113 // LCD +#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A +#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B +#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A +#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B +#define INT_I2C6_TM4C129 118 // I2C 6 +#define INT_I2C7_TM4C129 119 // I2C 7 +#define INT_ONEWIRE0_TM4C129 121 // 1-Wire +#define INT_I2C8_TM4C129 125 // I2C 8 +#define INT_I2C9_TM4C129 126 // I2C 9 +#define INT_GPIOT_TM4C129 127 // GPIO T +#define NUM_INTERRUPTS_TM4C129 129 + +//***************************************************************************** +// +// TM4C123 Interrupt Class Definition +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \ + defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \ + defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \ + defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \ + defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \ + defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \ + defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \ + defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \ + defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \ + defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \ + defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \ + defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \ + defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \ + defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \ + defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \ + defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \ + defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \ + defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \ + defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \ + defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \ + defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \ + defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \ + defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \ + defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \ + defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \ + defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \ + defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \ + defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR) +#define INT_RESOLVE(intname, class) intname##TM4C123 + +//***************************************************************************** +// +// TM4C129 Interrupt Class Definition +// +//***************************************************************************** +#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \ + defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \ + defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \ + defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \ + defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \ + defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \ + defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \ + defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \ + defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \ + defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \ + defined(PART_TM4C129XNCZAD) +#define INT_RESOLVE(intname, class) intname##TM4C129 +#else +#define INT_DEVICE_CLASS "UNKNOWN" +#endif + +//***************************************************************************** +// +// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name. +// +//***************************************************************************** +#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class) + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS) +#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS) +#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS) +#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS) +#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS) +#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS) +#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS) +#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS) +#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS) +#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS) +#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS) +#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS) +#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS) +#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS) +#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS) +#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS) +#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS) +#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS) +#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS) +#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS) +#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS) +#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS) +#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS) +#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS) +#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS) +#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS) +#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS) +#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS) +#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS) +#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS) +#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS) +#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS) +#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS) +#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS) +#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS) +#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS) +#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS) +#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS) +#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS) +#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS) +#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS) +#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS) +#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS) +#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS) +#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS) +#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS) +#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS) +#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS) +#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS) +#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS) +#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS) +#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS) +#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS) +#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS) +#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS) +#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS) +#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS) +#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS) +#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS) +#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS) +#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS) +#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS) +#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS) +#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS) +#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS) +#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS) +#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS) +#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS) +#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS) +#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS) +#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS) +#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS) +#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS) +#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS) +#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS) +#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS) +#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS) +#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS) +#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS) +#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS) +#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS) +#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS) +#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS) +#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS) +#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS) +#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS) +#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS) +#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS) +#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS) +#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS) +#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS) +#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS) +#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS) +#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS) +#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS) +#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS) +#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS) +#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS) +#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS) +#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS) +#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS) +#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS) +#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS) +#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS) +#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS) +#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS) +#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS) +#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS) +#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS) +#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS) +#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS) +#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS) +#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS) +#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS) +#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS) +#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS) +#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS) +#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS) +#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS) +#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS) +#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS) +#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS) +#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS) + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + +#endif // __HW_INTS_H__ diff --git a/CCS/mm/src/inc/tivaware/hw_memmap.h b/CCS/mm/src/inc/tivaware/hw_memmap.h new file mode 100644 index 0000000..780789d --- /dev/null +++ b/CCS/mm/src/inc/tivaware/hw_memmap.h @@ -0,0 +1,153 @@ +#include +#include +//***************************************************************************** +// +// hw_memmap.h - Macros defining the memory map of the device. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define FLASH_BASE 0x00000000 // FLASH memory +#define SRAM_BASE 0x20000000 // SRAM memory +#define WATCHDOG0_BASE 0x40000000 // Watchdog0 +#define WATCHDOG1_BASE 0x40001000 // Watchdog1 +#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A +#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B +#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C +#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D +#define SSI0_BASE 0x40008000 // SSI0 +#define SSI1_BASE 0x40009000 // SSI1 +#define SSI2_BASE 0x4000A000 // SSI2 +#define SSI3_BASE 0x4000B000 // SSI3 +#define UART0_BASE 0x4000C000 // UART0 +#define UART1_BASE 0x4000D000 // UART1 +#define UART2_BASE 0x4000E000 // UART2 +#define UART3_BASE 0x4000F000 // UART3 +#define UART4_BASE 0x40010000 // UART4 +#define UART5_BASE 0x40011000 // UART5 +#define UART6_BASE 0x40012000 // UART6 +#define UART7_BASE 0x40013000 // UART7 +#define I2C0_BASE 0x40020000 // I2C0 +#define I2C1_BASE 0x40021000 // I2C1 +#define I2C2_BASE 0x40022000 // I2C2 +#define I2C3_BASE 0x40023000 // I2C3 +#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E +#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F +#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G +#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H +#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM) +#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM) +#define QEI0_BASE 0x4002C000 // QEI0 +#define QEI1_BASE 0x4002D000 // QEI1 +#define TIMER0_BASE 0x40030000 // Timer0 +#define TIMER1_BASE 0x40031000 // Timer1 +#define TIMER2_BASE 0x40032000 // Timer2 +#define TIMER3_BASE 0x40033000 // Timer3 +#define TIMER4_BASE 0x40034000 // Timer4 +#define TIMER5_BASE 0x40035000 // Timer5 +#define WTIMER0_BASE 0x40036000 // Wide Timer0 +#define WTIMER1_BASE 0x40037000 // Wide Timer1 +#define ADC0_BASE 0x40038000 // ADC0 +#define ADC1_BASE 0x40039000 // ADC1 +#define COMP_BASE 0x4003C000 // Analog comparators +#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J +#define CAN0_BASE 0x40040000 // CAN0 +#define CAN1_BASE 0x40041000 // CAN1 +#define WTIMER2_BASE 0x4004C000 // Wide Timer2 +#define WTIMER3_BASE 0x4004D000 // Wide Timer3 +#define WTIMER4_BASE 0x4004E000 // Wide Timer4 +#define WTIMER5_BASE 0x4004F000 // Wide Timer5 +#define USB0_BASE 0x40050000 // USB 0 Controller +#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) +#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) +#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) +#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) +#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) +#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) +#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) +#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) +#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed) +#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K +#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L +#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M +#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N +#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P +#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q +#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs + // (GPIOs) +#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs + // (GPIOs) +#define EEPROM_BASE 0x400AF000 // EEPROM memory +#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module +#define I2C8_BASE 0x400B8000 // I2C8 +#define I2C9_BASE 0x400B9000 // I2C9 +#define I2C4_BASE 0x400C0000 // I2C4 +#define I2C5_BASE 0x400C1000 // I2C5 +#define I2C6_BASE 0x400C2000 // I2C6 +#define I2C7_BASE 0x400C3000 // I2C7 +#define EPI0_BASE 0x400D0000 // EPI0 +#define TIMER6_BASE 0x400E0000 // General-Purpose Timers +#define TIMER7_BASE 0x400E1000 // General-Purpose Timers +#define EMAC0_BASE 0x400EC000 // Ethernet Controller +#define SYSEXC_BASE 0x400F9000 // System Exception Module +#define HIB_BASE 0x400FC000 // Hibernation Module +#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller +#define SYSCTL_BASE 0x400FE000 // System Control +#define UDMA_BASE 0x400FF000 // uDMA Controller +#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC) +#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator +#define AES_BASE 0x44036000 // Advance Encryption + // Hardware-Accelerated Module +#define DES_BASE 0x44038000 // Data Encryption Standard + // Accelerator (DES) +#define LCD0_BASE 0x44050000 // LCD Controller +#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell +#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace +#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint +#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl +#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit + +#endif // __HW_MEMMAP_H__ diff --git a/CCS/mm/src/inc/tivaware/i2c.h b/CCS/mm/src/inc/tivaware/i2c.h new file mode 100644 index 0000000..068c00c --- /dev/null +++ b/CCS/mm/src/inc/tivaware/i2c.h @@ -0,0 +1,364 @@ +#include +#include +//***************************************************************************** +// +// i2c.h - Prototypes for the I2C Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_I2C_H__ +#define __DRIVERLIB_I2C_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +// Interrupt defines. +// +//***************************************************************************** +#define I2C_INT_MASTER 0x00000001 +#define I2C_INT_SLAVE 0x00000002 + +//***************************************************************************** +// +// I2C Master commands. +// +//***************************************************************************** +#define I2C_MASTER_CMD_SINGLE_SEND \ + 0x00000007 +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ + 0x00000007 +#define I2C_MASTER_CMD_BURST_SEND_START \ + 0x00000003 +#define I2C_MASTER_CMD_BURST_SEND_CONT \ + 0x00000001 +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_SEND_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ + 0x0000000b +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ + 0x00000009 +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ + 0x00000005 +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_QUICK_COMMAND \ + 0x00000027 +#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ + 0x00000013 +#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ + 0x00000046 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ + 0x00000042 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ + 0x00000040 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ + 0x00000004 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ + 0x0000004a +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ + 0x00000048 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ + 0x00000044 +#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ + 0x00000004 + +//***************************************************************************** +// +// I2C Master glitch filter configuration. +// +//***************************************************************************** +#define I2C_MASTER_GLITCH_FILTER_DISABLED \ + 0 +#define I2C_MASTER_GLITCH_FILTER_1 \ + 0x00010000 +#define I2C_MASTER_GLITCH_FILTER_2 \ + 0x00020000 +#define I2C_MASTER_GLITCH_FILTER_3 \ + 0x00030000 +#define I2C_MASTER_GLITCH_FILTER_4 \ + 0x00040000 +#define I2C_MASTER_GLITCH_FILTER_8 \ + 0x00050000 +#define I2C_MASTER_GLITCH_FILTER_16 \ + 0x00060000 +#define I2C_MASTER_GLITCH_FILTER_32 \ + 0x00070000 + +//***************************************************************************** +// +// I2C Master error status. +// +//***************************************************************************** +#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 +#define I2C_MASTER_ERR_DATA_ACK 0x00000008 +#define I2C_MASTER_ERR_ARB_LOST 0x00000010 +#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 + +//***************************************************************************** +// +// I2C Slave action requests +// +//***************************************************************************** +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave +#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command +#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value + +//***************************************************************************** +// +// Miscellaneous I2C driver definitions. +// +//***************************************************************************** +#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries + +//***************************************************************************** +// +// I2C Master interrupts. +// +//***************************************************************************** +#define I2C_MASTER_INT_RX_FIFO_FULL \ + 0x00000800 // RX FIFO Full Interrupt +#define I2C_MASTER_INT_TX_FIFO_EMPTY \ + 0x00000400 // TX FIFO Empty Interrupt +#define I2C_MASTER_INT_RX_FIFO_REQ \ + 0x00000200 // RX FIFO Request Interrupt +#define I2C_MASTER_INT_TX_FIFO_REQ \ + 0x00000100 // TX FIFO Request Interrupt +#define I2C_MASTER_INT_ARB_LOST \ + 0x00000080 // Arb Lost Interrupt +#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt +#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt +#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt +#define I2C_MASTER_INT_TX_DMA_DONE \ + 0x00000008 // TX DMA Complete Interrupt +#define I2C_MASTER_INT_RX_DMA_DONE \ + 0x00000004 // RX DMA Complete Interrupt +#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt +#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave interrupts. +// +//***************************************************************************** +#define I2C_SLAVE_INT_RX_FIFO_FULL \ + 0x00000100 // RX FIFO Full Interrupt +#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ + 0x00000080 // TX FIFO Empty Interrupt +#define I2C_SLAVE_INT_RX_FIFO_REQ \ + 0x00000040 // RX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_FIFO_REQ \ + 0x00000020 // TX FIFO Request Interrupt +#define I2C_SLAVE_INT_TX_DMA_DONE \ + 0x00000010 // TX DMA Complete Interrupt +#define I2C_SLAVE_INT_RX_DMA_DONE \ + 0x00000008 // RX DMA Complete Interrupt +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt + +//***************************************************************************** +// +// I2C Slave FIFO configuration macros. +// +//***************************************************************************** +#define I2C_SLAVE_TX_FIFO_ENABLE \ + 0x00000002 +#define I2C_SLAVE_RX_FIFO_ENABLE \ + 0x00000004 + +//***************************************************************************** +// +// I2C FIFO configuration macros. +// +//***************************************************************************** +#define I2C_FIFO_CFG_TX_MASTER 0x00000000 +#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 +#define I2C_FIFO_CFG_RX_MASTER 0x00000000 +#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 +#define I2C_FIFO_CFG_TX_MASTER_DMA \ + 0x00002000 +#define I2C_FIFO_CFG_TX_SLAVE_DMA \ + 0x0000a000 +#define I2C_FIFO_CFG_RX_MASTER_DMA \ + 0x20000000 +#define I2C_FIFO_CFG_RX_SLAVE_DMA \ + 0xa0000000 +#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 +#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 +#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 +#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 +#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 +#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 +#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 +#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 +#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 +#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 +#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 +#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 +#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 +#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 +#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 +#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 +#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 + +//***************************************************************************** +// +// I2C FIFO status. +// +//***************************************************************************** +#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ + 0x00040000 +#define I2C_FIFO_RX_FULL 0x00020000 +#define I2C_FIFO_RX_EMPTY 0x00010000 +#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ + 0x00000004 +#define I2C_FIFO_TX_FULL 0x00000002 +#define I2C_FIFO_TX_EMPTY 0x00000001 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void I2CIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); +extern void I2CIntUnregister(uint32_t ui32Base); +extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CTxFIFOFlush(uint32_t ui32Base); +extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CRxFIFOFlush(uint32_t ui32Base); +extern uint32_t I2CFIFOStatus(uint32_t ui32Base); +extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); +extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, + uint8_t ui8Data); +extern uint32_t I2CFIFODataGet(uint32_t ui32Base); +extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, + uint8_t *pui8Data); +extern void I2CMasterBurstLengthSet(uint32_t ui32Base, + uint8_t ui8Length); +extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); +extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, + uint32_t ui32Config); +extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); +extern void I2CSlaveFIFODisable(uint32_t ui32Base); +extern bool I2CMasterBusBusy(uint32_t ui32Base); +extern bool I2CMasterBusy(uint32_t ui32Base); +extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); +extern uint32_t I2CMasterDataGet(uint32_t ui32Base); +extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CMasterDisable(uint32_t ui32Base); +extern void I2CMasterEnable(uint32_t ui32Base); +extern uint32_t I2CMasterErr(uint32_t ui32Base); +extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, + bool bFast); +extern void I2CMasterIntClear(uint32_t ui32Base); +extern void I2CMasterIntDisable(uint32_t ui32Base); +extern void I2CMasterIntEnable(uint32_t ui32Base); +extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); +extern void I2CMasterIntEnableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern void I2CMasterIntClearEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); +extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); +extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); +extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); +extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, + uint8_t ui8SlaveAddr, + bool bReceive); +extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); +extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); +extern void I2CSlaveDisable(uint32_t ui32Base); +extern void I2CSlaveEnable(uint32_t ui32Base); +extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); +extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, + uint8_t ui8SlaveAddr); +extern void I2CSlaveIntClear(uint32_t ui32Base); +extern void I2CSlaveIntDisable(uint32_t ui32Base); +extern void I2CSlaveIntEnable(uint32_t ui32Base); +extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void I2CSlaveIntDisableEx(uint32_t ui32Base, + uint32_t ui32IntFlags); +extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); +extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); +extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, + bool bMasked); +extern uint32_t I2CSlaveStatus(uint32_t ui32Base); +extern void I2CLoopbackEnable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_I2C_H__ diff --git a/CCS/mm/src/inc/tivaware/pin_map.h b/CCS/mm/src/inc/tivaware/pin_map.h new file mode 100644 index 0000000..dd0b7b1 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/pin_map.h @@ -0,0 +1,20956 @@ +#include +#include +#define PART_TM4C123GH6PM +//***************************************************************************** +// +// pin_map.h - Mapping of peripherals to pins for all parts. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_PIN_MAP_H__ +#define __DRIVERLIB_PIN_MAP_H__ + +//***************************************************************************** +// +// TM4C1230C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230C3PM + +//***************************************************************************** +// +// TM4C1230D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230D5PM + +//***************************************************************************** +// +// TM4C1230E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230E6PM + +//***************************************************************************** +// +// TM4C1230H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1230H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1230H6PM + +//***************************************************************************** +// +// TM4C1231C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231C3PM + +//***************************************************************************** +// +// TM4C1231D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231D5PM + +//***************************************************************************** +// +// TM4C1231D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231D5PZ + +//***************************************************************************** +// +// TM4C1231E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231E6PM + +//***************************************************************************** +// +// TM4C1231E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231E6PZ + +//***************************************************************************** +// +// TM4C1231H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1231H6PM + +//***************************************************************************** +// +// TM4C1231H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1231H6PZ + +//***************************************************************************** +// +// TM4C1232C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232C3PM + +//***************************************************************************** +// +// TM4C1232D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232D5PM + +//***************************************************************************** +// +// TM4C1232E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232E6PM + +//***************************************************************************** +// +// TM4C1232H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1232H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C1232H6PM + +//***************************************************************************** +// +// TM4C1233C3PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233C3PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233C3PM + +//***************************************************************************** +// +// TM4C1233D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233D5PM + +//***************************************************************************** +// +// TM4C1233D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233D5PZ + +//***************************************************************************** +// +// TM4C1233E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233E6PM + +//***************************************************************************** +// +// TM4C1233E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233E6PZ + +//***************************************************************************** +// +// TM4C1233H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C1233H6PM + +//***************************************************************************** +// +// TM4C1233H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1233H6PZ + +//***************************************************************************** +// +// TM4C1236D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236D5PM + +//***************************************************************************** +// +// TM4C1236E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236E6PM + +//***************************************************************************** +// +// TM4C1236H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1236H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C1236H6PM + +//***************************************************************************** +// +// TM4C1237D5PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237D5PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237D5PM + +//***************************************************************************** +// +// TM4C1237D5PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237D5PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237D5PZ + +//***************************************************************************** +// +// TM4C1237E6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237E6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237E6PM + +//***************************************************************************** +// +// TM4C1237E6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237E6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237E6PZ + +//***************************************************************************** +// +// TM4C1237H6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PM + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C1237H6PM + +//***************************************************************************** +// +// TM4C1237H6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PZ + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#endif // PART_TM4C1237H6PZ + +//***************************************************************************** +// +// TM4C123AE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123AE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C123AE6PM + +//***************************************************************************** +// +// TM4C123AH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123AH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#endif // PART_TM4C123AH6PM + +//***************************************************************************** +// +// TM4C123BE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C123BE6PM + +//***************************************************************************** +// +// TM4C123BE6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BE6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123BE6PZ + +//***************************************************************************** +// +// TM4C123BH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 + +#endif // PART_TM4C123BH6PM + +//***************************************************************************** +// +// TM4C123BH6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123BH6PZ + +//***************************************************************************** +// +// TM4C123FE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123FE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C123FE6PM + +//***************************************************************************** +// +// TM4C123FH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123FH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#endif // PART_TM4C123FH6PM + +//***************************************************************************** +// +// TM4C123GE6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GE6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C123GE6PM + +//***************************************************************************** +// +// TM4C123GE6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GE6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123GE6PZ + +//***************************************************************************** +// +// TM4C123GH6PM Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PM + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 + +#endif // PART_TM4C123GH6PM + +//***************************************************************************** +// +// TM4C123GH6PZ Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PZ + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#endif // PART_TM4C123GH6PZ + +//***************************************************************************** +// +// TM4C1231H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1231H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1231H6PGE + +//***************************************************************************** +// +// TM4C1233H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1233H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1233H6PGE + +//***************************************************************************** +// +// TM4C1237H6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1237H6PGE + +#define GPIO_PA0_U0RX 0x00000001 + +#define GPIO_PA1_U0TX 0x00000401 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 + +#define GPIO_PA7_I2C1SDA 0x00001C03 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE7_U1RI 0x00041C01 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 + +#define GPIO_PK1_SSI3FSS 0x00090402 + +#define GPIO_PK2_SSI3RX 0x00090802 + +#define GPIO_PK3_SSI3TX 0x00090C02 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C1237H6PGE + +//***************************************************************************** +// +// TM4C123BH6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6PGE + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C123BH6PGE + +//***************************************************************************** +// +// TM4C123BH6ZRB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123BH6ZRB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123BH6ZRB + +//***************************************************************************** +// +// TM4C123GH6PGE Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6PGE + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#endif // PART_TM4C123GH6PGE + +//***************************************************************************** +// +// TM4C123GH6ZRB Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZRB + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZRB + +//***************************************************************************** +// +// TM4C123GH6ZXR Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C123GH6ZXR + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_CAN1RX 0x00000008 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_CAN1TX 0x00000408 + +#define GPIO_PA2_SSI0CLK 0x00000802 + +#define GPIO_PA3_SSI0FSS 0x00000C02 + +#define GPIO_PA4_SSI0RX 0x00001002 + +#define GPIO_PA5_SSI0TX 0x00001402 + +#define GPIO_PA6_I2C1SCL 0x00001803 +#define GPIO_PA6_M1PWM2 0x00001805 + +#define GPIO_PA7_I2C1SDA 0x00001C03 +#define GPIO_PA7_M1PWM3 0x00001C05 + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_T2CCP0 0x00010007 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_T2CCP1 0x00010407 + +#define GPIO_PB2_I2C0SCL 0x00010803 +#define GPIO_PB2_T3CCP0 0x00010807 + +#define GPIO_PB3_I2C0SDA 0x00010C03 +#define GPIO_PB3_T3CCP1 0x00010C07 + +#define GPIO_PB4_SSI2CLK 0x00011002 +#define GPIO_PB4_M0PWM2 0x00011004 +#define GPIO_PB4_T1CCP0 0x00011007 +#define GPIO_PB4_CAN0RX 0x00011008 + +#define GPIO_PB5_SSI2FSS 0x00011402 +#define GPIO_PB5_M0PWM3 0x00011404 +#define GPIO_PB5_T1CCP1 0x00011407 +#define GPIO_PB5_CAN0TX 0x00011408 + +#define GPIO_PB6_SSI2RX 0x00011802 +#define GPIO_PB6_I2C5SCL 0x00011803 +#define GPIO_PB6_M0PWM0 0x00011804 +#define GPIO_PB6_T0CCP0 0x00011807 + +#define GPIO_PB7_SSI2TX 0x00011C02 +#define GPIO_PB7_I2C5SDA 0x00011C03 +#define GPIO_PB7_M0PWM1 0x00011C04 +#define GPIO_PB7_T0CCP1 0x00011C07 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 +#define GPIO_PC0_T4CCP0 0x00020007 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 +#define GPIO_PC1_T4CCP1 0x00020407 + +#define GPIO_PC2_TDI 0x00020801 +#define GPIO_PC2_T5CCP0 0x00020807 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 +#define GPIO_PC3_T5CCP1 0x00020C07 + +#define GPIO_PC4_U4RX 0x00021001 +#define GPIO_PC4_U1RX 0x00021002 +#define GPIO_PC4_M0PWM6 0x00021004 +#define GPIO_PC4_IDX1 0x00021006 +#define GPIO_PC4_WT0CCP0 0x00021007 +#define GPIO_PC4_U1RTS 0x00021008 + +#define GPIO_PC5_U4TX 0x00021401 +#define GPIO_PC5_U1TX 0x00021402 +#define GPIO_PC5_M0PWM7 0x00021404 +#define GPIO_PC5_PHA1 0x00021406 +#define GPIO_PC5_WT0CCP1 0x00021407 +#define GPIO_PC5_U1CTS 0x00021408 + +#define GPIO_PC6_U3RX 0x00021801 +#define GPIO_PC6_PHB1 0x00021806 +#define GPIO_PC6_WT1CCP0 0x00021807 +#define GPIO_PC6_USB0EPEN 0x00021808 + +#define GPIO_PC7_U3TX 0x00021C01 +#define GPIO_PC7_WT1CCP1 0x00021C07 +#define GPIO_PC7_USB0PFLT 0x00021C08 + +#define GPIO_PD0_SSI3CLK 0x00030001 +#define GPIO_PD0_SSI1CLK 0x00030002 +#define GPIO_PD0_I2C3SCL 0x00030003 +#define GPIO_PD0_M0PWM6 0x00030004 +#define GPIO_PD0_M1PWM0 0x00030005 +#define GPIO_PD0_WT2CCP0 0x00030007 + +#define GPIO_PD1_SSI3FSS 0x00030401 +#define GPIO_PD1_SSI1FSS 0x00030402 +#define GPIO_PD1_I2C3SDA 0x00030403 +#define GPIO_PD1_M0PWM7 0x00030404 +#define GPIO_PD1_M1PWM1 0x00030405 +#define GPIO_PD1_WT2CCP1 0x00030407 + +#define GPIO_PD2_SSI3RX 0x00030801 +#define GPIO_PD2_SSI1RX 0x00030802 +#define GPIO_PD2_M0FAULT0 0x00030804 +#define GPIO_PD2_WT3CCP0 0x00030807 +#define GPIO_PD2_USB0EPEN 0x00030808 + +#define GPIO_PD3_SSI3TX 0x00030C01 +#define GPIO_PD3_SSI1TX 0x00030C02 +#define GPIO_PD3_IDX0 0x00030C06 +#define GPIO_PD3_WT3CCP1 0x00030C07 +#define GPIO_PD3_USB0PFLT 0x00030C08 + +#define GPIO_PD4_U6RX 0x00031001 +#define GPIO_PD4_WT4CCP0 0x00031007 + +#define GPIO_PD5_U6TX 0x00031401 +#define GPIO_PD5_WT4CCP1 0x00031407 + +#define GPIO_PD6_U2RX 0x00031801 +#define GPIO_PD6_M0FAULT0 0x00031804 +#define GPIO_PD6_PHA0 0x00031806 +#define GPIO_PD6_WT5CCP0 0x00031807 + +#define GPIO_PD7_U2TX 0x00031C01 +#define GPIO_PD7_M0FAULT1 0x00031C04 +#define GPIO_PD7_PHB0 0x00031C06 +#define GPIO_PD7_WT5CCP1 0x00031C07 +#define GPIO_PD7_NMI 0x00031C08 + +#define GPIO_PE0_U7RX 0x00040001 + +#define GPIO_PE1_U7TX 0x00040401 + +#define GPIO_PE4_U5RX 0x00041001 +#define GPIO_PE4_I2C2SCL 0x00041003 +#define GPIO_PE4_M0PWM4 0x00041004 +#define GPIO_PE4_M1PWM2 0x00041005 +#define GPIO_PE4_CAN0RX 0x00041008 + +#define GPIO_PE5_U5TX 0x00041401 +#define GPIO_PE5_I2C2SDA 0x00041403 +#define GPIO_PE5_M0PWM5 0x00041404 +#define GPIO_PE5_M1PWM3 0x00041405 +#define GPIO_PE5_CAN0TX 0x00041408 + +#define GPIO_PE6_CAN1RX 0x00041808 + +#define GPIO_PE7_U1RI 0x00041C01 +#define GPIO_PE7_CAN1TX 0x00041C08 + +#define GPIO_PF0_U1RTS 0x00050001 +#define GPIO_PF0_SSI1RX 0x00050002 +#define GPIO_PF0_CAN0RX 0x00050003 +#define GPIO_PF0_M1PWM4 0x00050005 +#define GPIO_PF0_PHA0 0x00050006 +#define GPIO_PF0_T0CCP0 0x00050007 +#define GPIO_PF0_NMI 0x00050008 +#define GPIO_PF0_C0O 0x00050009 +#define GPIO_PF0_TRD2 0x0005000E + +#define GPIO_PF1_U1CTS 0x00050401 +#define GPIO_PF1_SSI1TX 0x00050402 +#define GPIO_PF1_M1PWM5 0x00050405 +#define GPIO_PF1_PHB0 0x00050406 +#define GPIO_PF1_T0CCP1 0x00050407 +#define GPIO_PF1_C1O 0x00050409 +#define GPIO_PF1_TRD1 0x0005040E + +#define GPIO_PF2_U1DCD 0x00050801 +#define GPIO_PF2_SSI1CLK 0x00050802 +#define GPIO_PF2_M0FAULT0 0x00050804 +#define GPIO_PF2_M1PWM6 0x00050805 +#define GPIO_PF2_T1CCP0 0x00050807 +#define GPIO_PF2_C2O 0x00050809 +#define GPIO_PF2_TRD0 0x0005080E + +#define GPIO_PF3_U1DSR 0x00050C01 +#define GPIO_PF3_SSI1FSS 0x00050C02 +#define GPIO_PF3_CAN0TX 0x00050C03 +#define GPIO_PF3_M0FAULT1 0x00050C04 +#define GPIO_PF3_M1PWM7 0x00050C05 +#define GPIO_PF3_T1CCP1 0x00050C07 +#define GPIO_PF3_TRCLK 0x00050C0E + +#define GPIO_PF4_U1DTR 0x00051001 +#define GPIO_PF4_M0FAULT2 0x00051004 +#define GPIO_PF4_M1FAULT0 0x00051005 +#define GPIO_PF4_IDX0 0x00051006 +#define GPIO_PF4_T2CCP0 0x00051007 +#define GPIO_PF4_USB0EPEN 0x00051008 +#define GPIO_PF4_TRD3 0x0005100E + +#define GPIO_PF5_M0FAULT3 0x00051404 +#define GPIO_PF5_T2CCP1 0x00051407 +#define GPIO_PF5_USB0PFLT 0x00051408 + +#define GPIO_PF6_I2C2SCL 0x00051803 +#define GPIO_PF6_T3CCP0 0x00051807 + +#define GPIO_PF7_I2C2SDA 0x00051C03 +#define GPIO_PF7_M1FAULT0 0x00051C05 +#define GPIO_PF7_T3CCP1 0x00051C07 + +#define GPIO_PG0_I2C3SCL 0x00060003 +#define GPIO_PG0_M1FAULT1 0x00060005 +#define GPIO_PG0_PHA1 0x00060006 +#define GPIO_PG0_T4CCP0 0x00060007 + +#define GPIO_PG1_I2C3SDA 0x00060403 +#define GPIO_PG1_M1FAULT2 0x00060405 +#define GPIO_PG1_PHB1 0x00060406 +#define GPIO_PG1_T4CCP1 0x00060407 + +#define GPIO_PG2_I2C4SCL 0x00060803 +#define GPIO_PG2_M0FAULT1 0x00060804 +#define GPIO_PG2_M1PWM0 0x00060805 +#define GPIO_PG2_T5CCP0 0x00060807 + +#define GPIO_PG3_I2C4SDA 0x00060C03 +#define GPIO_PG3_M0FAULT2 0x00060C04 +#define GPIO_PG3_M1PWM1 0x00060C05 +#define GPIO_PG3_PHA1 0x00060C06 +#define GPIO_PG3_T5CCP1 0x00060C07 + +#define GPIO_PG4_U2RX 0x00061001 +#define GPIO_PG4_I2C1SCL 0x00061003 +#define GPIO_PG4_M0PWM4 0x00061004 +#define GPIO_PG4_M1PWM2 0x00061005 +#define GPIO_PG4_PHB1 0x00061006 +#define GPIO_PG4_WT0CCP0 0x00061007 +#define GPIO_PG4_USB0EPEN 0x00061008 + +#define GPIO_PG5_U2TX 0x00061401 +#define GPIO_PG5_I2C1SDA 0x00061403 +#define GPIO_PG5_M0PWM5 0x00061404 +#define GPIO_PG5_M1PWM3 0x00061405 +#define GPIO_PG5_IDX1 0x00061406 +#define GPIO_PG5_WT0CCP1 0x00061407 +#define GPIO_PG5_USB0PFLT 0x00061408 + +#define GPIO_PG6_I2C5SCL 0x00061803 +#define GPIO_PG6_M0PWM6 0x00061804 +#define GPIO_PG6_WT1CCP0 0x00061807 + +#define GPIO_PG7_I2C5SDA 0x00061C03 +#define GPIO_PG7_M0PWM7 0x00061C04 +#define GPIO_PG7_IDX1 0x00061C05 +#define GPIO_PG7_WT1CCP1 0x00061C07 + +#define GPIO_PH0_SSI3CLK 0x00070002 +#define GPIO_PH0_M0PWM0 0x00070004 +#define GPIO_PH0_M0FAULT0 0x00070006 +#define GPIO_PH0_WT2CCP0 0x00070007 + +#define GPIO_PH1_SSI3FSS 0x00070402 +#define GPIO_PH1_M0PWM1 0x00070404 +#define GPIO_PH1_IDX0 0x00070405 +#define GPIO_PH1_M0FAULT1 0x00070406 +#define GPIO_PH1_WT2CCP1 0x00070407 + +#define GPIO_PH2_SSI3RX 0x00070802 +#define GPIO_PH2_M0PWM2 0x00070804 +#define GPIO_PH2_M0FAULT2 0x00070806 +#define GPIO_PH2_WT5CCP0 0x00070807 + +#define GPIO_PH3_SSI3TX 0x00070C02 +#define GPIO_PH3_M0PWM3 0x00070C04 +#define GPIO_PH3_M0FAULT3 0x00070C06 +#define GPIO_PH3_WT5CCP1 0x00070C07 + +#define GPIO_PH4_SSI2CLK 0x00071002 +#define GPIO_PH4_M0PWM4 0x00071004 +#define GPIO_PH4_PHA0 0x00071005 +#define GPIO_PH4_WT3CCP0 0x00071007 + +#define GPIO_PH5_SSI2FSS 0x00071402 +#define GPIO_PH5_M0PWM5 0x00071404 +#define GPIO_PH5_PHB0 0x00071405 +#define GPIO_PH5_WT3CCP1 0x00071407 + +#define GPIO_PH6_SSI2RX 0x00071802 +#define GPIO_PH6_M0PWM6 0x00071804 +#define GPIO_PH6_WT4CCP0 0x00071807 + +#define GPIO_PH7_SSI2TX 0x00071C02 +#define GPIO_PH7_M0PWM7 0x00071C04 +#define GPIO_PH7_WT4CCP1 0x00071C07 + +#define GPIO_PJ0_U4RX 0x00080001 +#define GPIO_PJ0_T1CCP0 0x00080007 + +#define GPIO_PJ1_U4TX 0x00080401 +#define GPIO_PJ1_T1CCP1 0x00080407 + +#define GPIO_PJ2_U5RX 0x00080801 +#define GPIO_PJ2_IDX0 0x00080805 +#define GPIO_PJ2_T2CCP0 0x00080807 + +#define GPIO_PJ3_U5TX 0x00080C01 +#define GPIO_PJ3_T2CCP1 0x00080C07 + +#define GPIO_PJ4_U6RX 0x00081001 +#define GPIO_PJ4_T3CCP0 0x00081007 + +#define GPIO_PJ5_U6TX 0x00081401 +#define GPIO_PJ5_T3CCP1 0x00081407 + +#define GPIO_PK0_SSI3CLK 0x00090002 +#define GPIO_PK0_M1FAULT0 0x00090006 + +#define GPIO_PK1_SSI3FSS 0x00090402 +#define GPIO_PK1_M1FAULT1 0x00090406 + +#define GPIO_PK2_SSI3RX 0x00090802 +#define GPIO_PK2_M1FAULT2 0x00090806 + +#define GPIO_PK3_SSI3TX 0x00090C02 +#define GPIO_PK3_M1FAULT3 0x00090C06 + +#define GPIO_PK4_U7RX 0x00091001 +#define GPIO_PK4_M0FAULT0 0x00091006 +#define GPIO_PK4_RTCCLK 0x00091007 +#define GPIO_PK4_C0O 0x00091008 + +#define GPIO_PK5_U7TX 0x00091401 +#define GPIO_PK5_M0FAULT1 0x00091406 +#define GPIO_PK5_C1O 0x00091408 + +#define GPIO_PK6_M0FAULT2 0x00091806 +#define GPIO_PK6_WT1CCP0 0x00091807 +#define GPIO_PK6_C2O 0x00091808 + +#define GPIO_PK7_M0FAULT3 0x00091C06 +#define GPIO_PK7_WT1CCP1 0x00091C07 + +#define GPIO_PL0_T0CCP0 0x000A0007 +#define GPIO_PL0_WT0CCP0 0x000A0008 + +#define GPIO_PL1_T0CCP1 0x000A0407 +#define GPIO_PL1_WT0CCP1 0x000A0408 + +#define GPIO_PL2_T1CCP0 0x000A0807 +#define GPIO_PL2_WT1CCP0 0x000A0808 + +#define GPIO_PL3_T1CCP1 0x000A0C07 +#define GPIO_PL3_WT1CCP1 0x000A0C08 + +#define GPIO_PL4_T2CCP0 0x000A1007 +#define GPIO_PL4_WT2CCP0 0x000A1008 + +#define GPIO_PL5_T2CCP1 0x000A1407 +#define GPIO_PL5_WT2CCP1 0x000A1408 + +#define GPIO_PL6_T3CCP0 0x000A1807 +#define GPIO_PL6_WT3CCP0 0x000A1808 + +#define GPIO_PL7_T3CCP1 0x000A1C07 +#define GPIO_PL7_WT3CCP1 0x000A1C08 + +#define GPIO_PM0_T4CCP0 0x000B0007 +#define GPIO_PM0_WT4CCP0 0x000B0008 + +#define GPIO_PM1_T4CCP1 0x000B0407 +#define GPIO_PM1_WT4CCP1 0x000B0408 + +#define GPIO_PM2_T5CCP0 0x000B0807 +#define GPIO_PM2_WT5CCP0 0x000B0808 + +#define GPIO_PM3_T5CCP1 0x000B0C07 +#define GPIO_PM3_WT5CCP1 0x000B0C08 + +#define GPIO_PM6_M0PWM4 0x000B1802 +#define GPIO_PM6_WT0CCP0 0x000B1807 + +#define GPIO_PM7_M0PWM5 0x000B1C02 +#define GPIO_PM7_WT0CCP1 0x000B1C07 + +#define GPIO_PN0_CAN0RX 0x000C0001 + +#define GPIO_PN1_CAN0TX 0x000C0401 + +#define GPIO_PN2_M0PWM6 0x000C0802 +#define GPIO_PN2_WT2CCP0 0x000C0807 + +#define GPIO_PN3_M0PWM7 0x000C0C02 +#define GPIO_PN3_WT2CCP1 0x000C0C07 + +#define GPIO_PN4_M1PWM4 0x000C1002 +#define GPIO_PN4_WT3CCP0 0x000C1007 + +#define GPIO_PN5_M1PWM5 0x000C1402 +#define GPIO_PN5_WT3CCP1 0x000C1407 + +#define GPIO_PN6_M1PWM6 0x000C1802 +#define GPIO_PN6_WT4CCP0 0x000C1807 + +#define GPIO_PN7_M1PWM7 0x000C1C02 +#define GPIO_PN7_WT4CCP1 0x000C1C07 + +#define GPIO_PP0_M0PWM0 0x000D0001 +#define GPIO_PP0_T4CCP0 0x000D0007 + +#define GPIO_PP1_M0PWM1 0x000D0401 +#define GPIO_PP1_T4CCP1 0x000D0407 + +#define GPIO_PP2_M0PWM2 0x000D0801 +#define GPIO_PP2_T5CCP0 0x000D0807 + +#define GPIO_PP3_M0PWM3 0x000D0C01 +#define GPIO_PP3_T5CCP1 0x000D0C07 + +#define GPIO_PP4_M0PWM4 0x000D1001 +#define GPIO_PP4_WT0CCP0 0x000D1007 + +#define GPIO_PP5_M0PWM5 0x000D1401 +#define GPIO_PP5_WT0CCP1 0x000D1407 + +#define GPIO_PP6_M0PWM6 0x000D1801 +#define GPIO_PP6_WT1CCP0 0x000D1807 + +#define GPIO_PP7_M0PWM7 0x000D1C01 +#define GPIO_PP7_WT1CCP1 0x000D1C07 + +#define GPIO_PQ0_M1PWM0 0x000E0001 +#define GPIO_PQ0_WT2CCP0 0x000E0007 + +#define GPIO_PQ1_M1PWM1 0x000E0401 +#define GPIO_PQ1_WT2CCP1 0x000E0407 + +#define GPIO_PQ2_M1PWM2 0x000E0801 +#define GPIO_PQ2_WT3CCP0 0x000E0807 + +#define GPIO_PQ3_M1PWM3 0x000E0C01 +#define GPIO_PQ3_WT3CCP1 0x000E0C07 + +#define GPIO_PQ4_M1PWM4 0x000E1001 +#define GPIO_PQ4_WT4CCP0 0x000E1007 + +#define GPIO_PQ5_M1PWM5 0x000E1401 +#define GPIO_PQ5_WT4CCP1 0x000E1407 + +#define GPIO_PQ6_M1PWM6 0x000E1801 +#define GPIO_PQ6_WT5CCP0 0x000E1807 + +#define GPIO_PQ7_M1PWM7 0x000E1C01 +#define GPIO_PQ7_WT5CCP1 0x000E1C07 + +#endif // PART_TM4C123GH6ZXR + +//***************************************************************************** +// +// TM4C1290NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1290NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#endif // PART_TM4C1290NCPDT + +//***************************************************************************** +// +// TM4C1290NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1290NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1290NCZAD + +//***************************************************************************** +// +// TM4C1292NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1292NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#endif // PART_TM4C1292NCPDT + +//***************************************************************************** +// +// TM4C1292NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1292NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1292NCZAD + +//***************************************************************************** +// +// TM4C1294KCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294KCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C1294KCPDT + +//***************************************************************************** +// +// TM4C1294NCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294NCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C1294NCPDT + +//***************************************************************************** +// +// TM4C1294NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1294NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C1294NCZAD + +//***************************************************************************** +// +// TM4C1297NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1297NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1297NCZAD + +//***************************************************************************** +// +// TM4C1299KCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1299KCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1299KCZAD + +//***************************************************************************** +// +// TM4C1299NCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C1299NCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C1299NCZAD + +//***************************************************************************** +// +// TM4C129CNCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129CNCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#endif // PART_TM4C129CNCPDT + +//***************************************************************************** +// +// TM4C129CNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129CNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129CNCZAD + +//***************************************************************************** +// +// TM4C129DNCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129DNCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#endif // PART_TM4C129DNCPDT + +//***************************************************************************** +// +// TM4C129DNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129DNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129DNCZAD + +//***************************************************************************** +// +// TM4C129EKCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129EKCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C129EKCPDT + +//***************************************************************************** +// +// TM4C129ENCPDT Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129ENCPDT + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#endif // PART_TM4C129ENCPDT + +//***************************************************************************** +// +// TM4C129ENCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129ENCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 + +#define GPIO_PJ3_U2CTS 0x00080C01 + +#define GPIO_PJ4_U3RTS 0x00081001 + +#define GPIO_PJ5_U3CTS 0x00081401 + +#define GPIO_PJ6_U4RTS 0x00081801 + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 + +#define GPIO_PS7_T5CCP1 0x00101C03 + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 + +#endif // PART_TM4C129ENCZAD + +//***************************************************************************** +// +// TM4C129LNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129LNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 + +#define GPIO_PQ6_U1DTR 0x000E1801 + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129LNCZAD + +//***************************************************************************** +// +// TM4C129XKCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129XKCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 +#define GPIO_PE3_OWIRE 0x00040C05 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_OWIRE 0x00061005 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_OWALT 0x00061405 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_OWIRE 0x00061805 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_OWIRE 0x00061C05 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_OWIRE 0x000D1004 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_OWALT 0x000D1404 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PP7_OWIRE 0x000D1C05 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129XKCZAD + +//***************************************************************************** +// +// TM4C129XNCZAD Port/Pin Mapping Definitions +// +//***************************************************************************** +#ifdef PART_TM4C129XNCZAD + +#define GPIO_PA0_U0RX 0x00000001 +#define GPIO_PA0_I2C9SCL 0x00000002 +#define GPIO_PA0_T0CCP0 0x00000003 +#define GPIO_PA0_CAN0RX 0x00000007 + +#define GPIO_PA1_U0TX 0x00000401 +#define GPIO_PA1_I2C9SDA 0x00000402 +#define GPIO_PA1_T0CCP1 0x00000403 +#define GPIO_PA1_CAN0TX 0x00000407 + +#define GPIO_PA2_U4RX 0x00000801 +#define GPIO_PA2_I2C8SCL 0x00000802 +#define GPIO_PA2_T1CCP0 0x00000803 +#define GPIO_PA2_SSI0CLK 0x0000080F + +#define GPIO_PA3_U4TX 0x00000C01 +#define GPIO_PA3_I2C8SDA 0x00000C02 +#define GPIO_PA3_T1CCP1 0x00000C03 +#define GPIO_PA3_SSI0FSS 0x00000C0F + +#define GPIO_PA4_U3RX 0x00001001 +#define GPIO_PA4_T2CCP0 0x00001003 +#define GPIO_PA4_I2C7SCL 0x00001002 +#define GPIO_PA4_SSI0XDAT0 0x0000100F + +#define GPIO_PA5_U3TX 0x00001401 +#define GPIO_PA5_T2CCP1 0x00001403 +#define GPIO_PA5_I2C7SDA 0x00001402 +#define GPIO_PA5_SSI0XDAT1 0x0000140F + +#define GPIO_PA6_U2RX 0x00001801 +#define GPIO_PA6_I2C6SCL 0x00001802 +#define GPIO_PA6_T3CCP0 0x00001803 +#define GPIO_PA6_USB0EPEN 0x00001805 +#define GPIO_PA6_SSI0XDAT2 0x0000180D +#define GPIO_PA6_EN0RXCK 0x0000180E +#define GPIO_PA6_EPI0S8 0x0000180F + +#define GPIO_PA7_U2TX 0x00001C01 +#define GPIO_PA7_I2C6SDA 0x00001C02 +#define GPIO_PA7_T3CCP1 0x00001C03 +#define GPIO_PA7_USB0PFLT 0x00001C05 +#define GPIO_PA7_USB0EPEN 0x00001C0B +#define GPIO_PA7_SSI0XDAT3 0x00001C0D +#define GPIO_PA7_EPI0S9 0x00001C0F + +#define GPIO_PB0_U1RX 0x00010001 +#define GPIO_PB0_I2C5SCL 0x00010002 +#define GPIO_PB0_CAN1RX 0x00010007 +#define GPIO_PB0_T4CCP0 0x00010003 + +#define GPIO_PB1_U1TX 0x00010401 +#define GPIO_PB1_I2C5SDA 0x00010402 +#define GPIO_PB1_CAN1TX 0x00010407 +#define GPIO_PB1_T4CCP1 0x00010403 + +#define GPIO_PB2_T5CCP0 0x00010803 +#define GPIO_PB2_I2C0SCL 0x00010802 +#define GPIO_PB2_EN0MDC 0x00010805 +#define GPIO_PB2_USB0STP 0x0001080E +#define GPIO_PB2_EPI0S27 0x0001080F + +#define GPIO_PB3_I2C0SDA 0x00010C02 +#define GPIO_PB3_T5CCP1 0x00010C03 +#define GPIO_PB3_EN0MDIO 0x00010C05 +#define GPIO_PB3_USB0CLK 0x00010C0E +#define GPIO_PB3_EPI0S28 0x00010C0F + +#define GPIO_PB4_U0CTS 0x00011001 +#define GPIO_PB4_I2C5SCL 0x00011002 +#define GPIO_PB4_SSI1FSS 0x0001100F + +#define GPIO_PB5_U0RTS 0x00011401 +#define GPIO_PB5_I2C5SDA 0x00011402 +#define GPIO_PB5_SSI1CLK 0x0001140F + +#define GPIO_PB6_I2C6SCL 0x00011802 +#define GPIO_PB6_T6CCP0 0x00011803 + +#define GPIO_PB7_I2C6SDA 0x00011C02 +#define GPIO_PB7_T6CCP1 0x00011C03 + +#define GPIO_PC0_TCK 0x00020001 +#define GPIO_PC0_SWCLK 0x00020001 + +#define GPIO_PC1_TMS 0x00020401 +#define GPIO_PC1_SWDIO 0x00020401 + +#define GPIO_PC2_TDI 0x00020801 + +#define GPIO_PC3_SWO 0x00020C01 +#define GPIO_PC3_TDO 0x00020C01 + +#define GPIO_PC4_U7RX 0x00021001 +#define GPIO_PC4_T7CCP0 0x00021003 +#define GPIO_PC4_EPI0S7 0x0002100F + +#define GPIO_PC5_U7TX 0x00021401 +#define GPIO_PC5_T7CCP1 0x00021403 +#define GPIO_PC5_RTCCLK 0x00021407 +#define GPIO_PC5_EPI0S6 0x0002140F + +#define GPIO_PC6_U5RX 0x00021801 +#define GPIO_PC6_EPI0S5 0x0002180F + +#define GPIO_PC7_U5TX 0x00021C01 +#define GPIO_PC7_EPI0S4 0x00021C0F + +#define GPIO_PD0_I2C7SCL 0x00030002 +#define GPIO_PD0_T0CCP0 0x00030003 +#define GPIO_PD0_C0O 0x00030005 +#define GPIO_PD0_SSI2XDAT1 0x0003000F + +#define GPIO_PD1_I2C7SDA 0x00030402 +#define GPIO_PD1_T0CCP1 0x00030403 +#define GPIO_PD1_C1O 0x00030405 +#define GPIO_PD1_SSI2XDAT0 0x0003040F + +#define GPIO_PD2_I2C8SCL 0x00030802 +#define GPIO_PD2_T1CCP0 0x00030803 +#define GPIO_PD2_C2O 0x00030805 +#define GPIO_PD2_SSI2FSS 0x0003080F + +#define GPIO_PD3_I2C8SDA 0x00030C02 +#define GPIO_PD3_T1CCP1 0x00030C03 +#define GPIO_PD3_SSI2CLK 0x00030C0F + +#define GPIO_PD4_U2RX 0x00031001 +#define GPIO_PD4_T3CCP0 0x00031003 +#define GPIO_PD4_SSI1XDAT2 0x0003100F + +#define GPIO_PD5_U2TX 0x00031401 +#define GPIO_PD5_T3CCP1 0x00031403 +#define GPIO_PD5_SSI1XDAT3 0x0003140F + +#define GPIO_PD6_U2RTS 0x00031801 +#define GPIO_PD6_T4CCP0 0x00031803 +#define GPIO_PD6_USB0EPEN 0x00031805 +#define GPIO_PD6_SSI2XDAT3 0x0003180F + +#define GPIO_PD7_U2CTS 0x00031C01 +#define GPIO_PD7_T4CCP1 0x00031C03 +#define GPIO_PD7_USB0PFLT 0x00031C05 +#define GPIO_PD7_NMI 0x00031C08 +#define GPIO_PD7_SSI2XDAT2 0x00031C0F + +#define GPIO_PE0_U1RTS 0x00040001 + +#define GPIO_PE1_U1DSR 0x00040401 + +#define GPIO_PE2_U1DCD 0x00040801 + +#define GPIO_PE3_U1DTR 0x00040C01 +#define GPIO_PE3_OWIRE 0x00040C05 + +#define GPIO_PE4_U1RI 0x00041001 +#define GPIO_PE4_SSI1XDAT0 0x0004100F + +#define GPIO_PE5_SSI1XDAT1 0x0004140F + +#define GPIO_PE6_U0CTS 0x00041801 +#define GPIO_PE6_I2C9SCL 0x00041802 + +#define GPIO_PE7_U0RTS 0x00041C01 +#define GPIO_PE7_I2C9SDA 0x00041C02 +#define GPIO_PE7_NMI 0x00041C08 + +#define GPIO_PF0_EN0LED0 0x00050005 +#define GPIO_PF0_M0PWM0 0x00050006 +#define GPIO_PF0_SSI3XDAT1 0x0005000E +#define GPIO_PF0_TRD2 0x0005000F + +#define GPIO_PF1_EN0LED2 0x00050405 +#define GPIO_PF1_M0PWM1 0x00050406 +#define GPIO_PF1_SSI3XDAT0 0x0005040E +#define GPIO_PF1_TRD1 0x0005040F + +#define GPIO_PF2_EN0MDC 0x00050805 +#define GPIO_PF2_M0PWM2 0x00050806 +#define GPIO_PF2_SSI3FSS 0x0005080E +#define GPIO_PF2_TRD0 0x0005080F + +#define GPIO_PF3_EN0MDIO 0x00050C05 +#define GPIO_PF3_M0PWM3 0x00050C06 +#define GPIO_PF3_SSI3CLK 0x00050C0E +#define GPIO_PF3_TRCLK 0x00050C0F + +#define GPIO_PF4_EN0LED1 0x00051005 +#define GPIO_PF4_M0FAULT0 0x00051006 +#define GPIO_PF4_SSI3XDAT2 0x0005100E +#define GPIO_PF4_TRD3 0x0005100F + +#define GPIO_PF5_SSI3XDAT3 0x0005140E + +#define GPIO_PF6_LCDMCLK 0x0005180F + +#define GPIO_PF7_LCDDATA02 0x00051C0F + +#define GPIO_PG0_I2C1SCL 0x00060002 +#define GPIO_PG0_EN0PPS 0x00060005 +#define GPIO_PG0_M0PWM4 0x00060006 +#define GPIO_PG0_EPI0S11 0x0006000F + +#define GPIO_PG1_I2C1SDA 0x00060402 +#define GPIO_PG1_M0PWM5 0x00060406 +#define GPIO_PG1_EPI0S10 0x0006040F + +#define GPIO_PG2_I2C2SCL 0x00060802 +#define GPIO_PG2_EN0TXCK 0x0006080E +#define GPIO_PG2_SSI2XDAT3 0x0006080F + +#define GPIO_PG3_I2C2SDA 0x00060C02 +#define GPIO_PG3_EN0TXEN 0x00060C0E +#define GPIO_PG3_SSI2XDAT2 0x00060C0F + +#define GPIO_PG4_U0CTS 0x00061001 +#define GPIO_PG4_I2C3SCL 0x00061002 +#define GPIO_PG4_OWIRE 0x00061005 +#define GPIO_PG4_EN0TXD0 0x0006100E +#define GPIO_PG4_SSI2XDAT1 0x0006100F + +#define GPIO_PG5_U0RTS 0x00061401 +#define GPIO_PG5_I2C3SDA 0x00061402 +#define GPIO_PG5_OWALT 0x00061405 +#define GPIO_PG5_EN0TXD1 0x0006140E +#define GPIO_PG5_SSI2XDAT0 0x0006140F + +#define GPIO_PG6_I2C4SCL 0x00061802 +#define GPIO_PG6_OWIRE 0x00061805 +#define GPIO_PG6_EN0RXER 0x0006180E +#define GPIO_PG6_SSI2FSS 0x0006180F + +#define GPIO_PG7_I2C4SDA 0x00061C02 +#define GPIO_PG7_OWIRE 0x00061C05 +#define GPIO_PG7_EN0RXDV 0x00061C0E +#define GPIO_PG7_SSI2CLK 0x00061C0F + +#define GPIO_PH0_U0RTS 0x00070001 +#define GPIO_PH0_EPI0S0 0x0007000F + +#define GPIO_PH1_U0CTS 0x00070401 +#define GPIO_PH1_EPI0S1 0x0007040F + +#define GPIO_PH2_U0DCD 0x00070801 +#define GPIO_PH2_EPI0S2 0x0007080F + +#define GPIO_PH3_U0DSR 0x00070C01 +#define GPIO_PH3_EPI0S3 0x00070C0F + +#define GPIO_PH4_U0DTR 0x00071001 + +#define GPIO_PH5_U0RI 0x00071401 +#define GPIO_PH5_EN0PPS 0x00071405 + +#define GPIO_PH6_U5RX 0x00071801 +#define GPIO_PH6_U7RX 0x00071802 + +#define GPIO_PH7_U5TX 0x00071C01 +#define GPIO_PH7_U7TX 0x00071C02 + +#define GPIO_PJ0_U3RX 0x00080001 +#define GPIO_PJ0_EN0PPS 0x00080005 + +#define GPIO_PJ1_U3TX 0x00080401 + +#define GPIO_PJ2_U2RTS 0x00080801 +#define GPIO_PJ2_LCDDATA14 0x0008080F + +#define GPIO_PJ3_U2CTS 0x00080C01 +#define GPIO_PJ3_LCDDATA15 0x00080C0F + +#define GPIO_PJ4_U3RTS 0x00081001 +#define GPIO_PJ4_LCDDATA16 0x0008100F + +#define GPIO_PJ5_U3CTS 0x00081401 +#define GPIO_PJ5_LCDDATA17 0x0008140F + +#define GPIO_PJ6_U4RTS 0x00081801 +#define GPIO_PJ6_LCDAC 0x0008180F + +#define GPIO_PJ7_U4CTS 0x00081C01 + +#define GPIO_PK0_U4RX 0x00090001 +#define GPIO_PK0_EPI0S0 0x0009000F + +#define GPIO_PK1_U4TX 0x00090401 +#define GPIO_PK1_EPI0S1 0x0009040F + +#define GPIO_PK2_U4RTS 0x00090801 +#define GPIO_PK2_EPI0S2 0x0009080F + +#define GPIO_PK3_U4CTS 0x00090C01 +#define GPIO_PK3_EPI0S3 0x00090C0F + +#define GPIO_PK4_I2C3SCL 0x00091002 +#define GPIO_PK4_EN0LED0 0x00091005 +#define GPIO_PK4_M0PWM6 0x00091006 +#define GPIO_PK4_EN0INTRN 0x00091007 +#define GPIO_PK4_EN0RXD3 0x0009100E +#define GPIO_PK4_EPI0S32 0x0009100F + +#define GPIO_PK5_I2C3SDA 0x00091402 +#define GPIO_PK5_EN0LED2 0x00091405 +#define GPIO_PK5_M0PWM7 0x00091406 +#define GPIO_PK5_EN0RXD2 0x0009140E +#define GPIO_PK5_EPI0S31 0x0009140F + +#define GPIO_PK6_I2C4SCL 0x00091802 +#define GPIO_PK6_EN0LED1 0x00091805 +#define GPIO_PK6_M0FAULT1 0x00091806 +#define GPIO_PK6_EN0TXD2 0x0009180E +#define GPIO_PK6_EPI0S25 0x0009180F + +#define GPIO_PK7_U0RI 0x00091C01 +#define GPIO_PK7_I2C4SDA 0x00091C02 +#define GPIO_PK7_RTCCLK 0x00091C05 +#define GPIO_PK7_M0FAULT2 0x00091C06 +#define GPIO_PK7_EN0TXD3 0x00091C0E +#define GPIO_PK7_EPI0S24 0x00091C0F + +#define GPIO_PL0_I2C2SDA 0x000A0002 +#define GPIO_PL0_M0FAULT3 0x000A0006 +#define GPIO_PL0_USB0D0 0x000A000E +#define GPIO_PL0_EPI0S16 0x000A000F + +#define GPIO_PL1_I2C2SCL 0x000A0402 +#define GPIO_PL1_PHA0 0x000A0406 +#define GPIO_PL1_USB0D1 0x000A040E +#define GPIO_PL1_EPI0S17 0x000A040F + +#define GPIO_PL2_C0O 0x000A0805 +#define GPIO_PL2_PHB0 0x000A0806 +#define GPIO_PL2_USB0D2 0x000A080E +#define GPIO_PL2_EPI0S18 0x000A080F + +#define GPIO_PL3_C1O 0x000A0C05 +#define GPIO_PL3_IDX0 0x000A0C06 +#define GPIO_PL3_USB0D3 0x000A0C0E +#define GPIO_PL3_EPI0S19 0x000A0C0F + +#define GPIO_PL4_T0CCP0 0x000A1003 +#define GPIO_PL4_USB0D4 0x000A100E +#define GPIO_PL4_EPI0S26 0x000A100F + +#define GPIO_PL5_T0CCP1 0x000A1403 +#define GPIO_PL5_EPI0S33 0x000A140F +#define GPIO_PL5_USB0D5 0x000A140E + +#define GPIO_PL6_T1CCP0 0x000A1803 + +#define GPIO_PL7_T1CCP1 0x000A1C03 + +#define GPIO_PM0_T2CCP0 0x000B0003 +#define GPIO_PM0_EPI0S15 0x000B000F + +#define GPIO_PM1_T2CCP1 0x000B0403 +#define GPIO_PM1_EPI0S14 0x000B040F + +#define GPIO_PM2_T3CCP0 0x000B0803 +#define GPIO_PM2_EPI0S13 0x000B080F + +#define GPIO_PM3_T3CCP1 0x000B0C03 +#define GPIO_PM3_EPI0S12 0x000B0C0F + +#define GPIO_PM4_U0CTS 0x000B1001 +#define GPIO_PM4_T4CCP0 0x000B1003 +#define GPIO_PM4_EN0RREF_CLK 0x000B100E + +#define GPIO_PM5_U0DCD 0x000B1401 +#define GPIO_PM5_T4CCP1 0x000B1403 + +#define GPIO_PM6_U0DSR 0x000B1801 +#define GPIO_PM6_T5CCP0 0x000B1803 +#define GPIO_PM6_EN0CRS 0x000B180E + +#define GPIO_PM7_U0RI 0x000B1C01 +#define GPIO_PM7_T5CCP1 0x000B1C03 +#define GPIO_PM7_EN0COL 0x000B1C0E + +#define GPIO_PN0_U1RTS 0x000C0001 + +#define GPIO_PN1_U1CTS 0x000C0401 + +#define GPIO_PN2_U1DCD 0x000C0801 +#define GPIO_PN2_U2RTS 0x000C0802 +#define GPIO_PN2_EPI0S29 0x000C080F + +#define GPIO_PN3_U1DSR 0x000C0C01 +#define GPIO_PN3_U2CTS 0x000C0C02 +#define GPIO_PN3_EPI0S30 0x000C0C0F + +#define GPIO_PN4_U1DTR 0x000C1001 +#define GPIO_PN4_U3RTS 0x000C1002 +#define GPIO_PN4_I2C2SDA 0x000C1003 +#define GPIO_PN4_EPI0S34 0x000C100F + +#define GPIO_PN5_U1RI 0x000C1401 +#define GPIO_PN5_U3CTS 0x000C1402 +#define GPIO_PN5_I2C2SCL 0x000C1403 +#define GPIO_PN5_EPI0S35 0x000C140F + +#define GPIO_PN6_U4RTS 0x000C1802 +#define GPIO_PN6_EN0TXER 0x000C180E +#define GPIO_PN6_LCDDATA13 0x000C180F + +#define GPIO_PN7_U1RTS 0x000C1C01 +#define GPIO_PN7_U4CTS 0x000C1C02 +#define GPIO_PN7_LCDDATA12 0x000C1C0F + +#define GPIO_PP0_U6RX 0x000D0001 +#define GPIO_PP0_T6CCP0 0x000D0005 +#define GPIO_PP0_EN0INTRN 0x000D0007 +#define GPIO_PP0_SSI3XDAT2 0x000D000F + +#define GPIO_PP1_U6TX 0x000D0401 +#define GPIO_PP1_T6CCP1 0x000D0405 +#define GPIO_PP1_SSI3XDAT3 0x000D040F + +#define GPIO_PP2_U0DTR 0x000D0801 +#define GPIO_PP2_USB0NXT 0x000D080E +#define GPIO_PP2_EPI0S29 0x000D080F + +#define GPIO_PP3_U1CTS 0x000D0C01 +#define GPIO_PP3_U0DCD 0x000D0C02 +#define GPIO_PP3_RTCCLK 0x000D0C07 +#define GPIO_PP3_USB0DIR 0x000D0C0E +#define GPIO_PP3_EPI0S30 0x000D0C0F + +#define GPIO_PP4_U3RTS 0x000D1001 +#define GPIO_PP4_U0DSR 0x000D1002 +#define GPIO_PP4_OWIRE 0x000D1004 +#define GPIO_PP4_USB0D7 0x000D100E + +#define GPIO_PP5_U3CTS 0x000D1401 +#define GPIO_PP5_I2C2SCL 0x000D1402 +#define GPIO_PP5_OWALT 0x000D1404 +#define GPIO_PP5_USB0D6 0x000D140E + +#define GPIO_PP6_U1DCD 0x000D1801 +#define GPIO_PP6_I2C2SDA 0x000D1802 + +#define GPIO_PP7_OWIRE 0x000D1C05 + +#define GPIO_PQ0_T6CCP0 0x000E0003 +#define GPIO_PQ0_SSI3CLK 0x000E000E +#define GPIO_PQ0_EPI0S20 0x000E000F + +#define GPIO_PQ1_T6CCP1 0x000E0403 +#define GPIO_PQ1_SSI3FSS 0x000E040E +#define GPIO_PQ1_EPI0S21 0x000E040F + +#define GPIO_PQ2_T7CCP0 0x000E0803 +#define GPIO_PQ2_SSI3XDAT0 0x000E080E +#define GPIO_PQ2_EPI0S22 0x000E080F + +#define GPIO_PQ3_T7CCP1 0x000E0C03 +#define GPIO_PQ3_SSI3XDAT1 0x000E0C0E +#define GPIO_PQ3_EPI0S23 0x000E0C0F + +#define GPIO_PQ4_U1RX 0x000E1001 +#define GPIO_PQ4_DIVSCLK 0x000E1007 + +#define GPIO_PQ5_U1TX 0x000E1401 +#define GPIO_PQ5_EN0RXD0 0x000E140E + +#define GPIO_PQ6_U1DTR 0x000E1801 +#define GPIO_PQ6_EN0RXD1 0x000E180E + +#define GPIO_PQ7_U1RI 0x000E1C01 + +#define GPIO_PR0_U4TX 0x000F0001 +#define GPIO_PR0_I2C1SCL 0x000F0002 +#define GPIO_PR0_M0PWM0 0x000F0006 +#define GPIO_PR0_LCDCP 0x000F000F + +#define GPIO_PR1_U4RX 0x000F0401 +#define GPIO_PR1_I2C1SDA 0x000F0402 +#define GPIO_PR1_M0PWM1 0x000F0406 +#define GPIO_PR1_LCDFP 0x000F040F + +#define GPIO_PR2_I2C2SCL 0x000F0802 +#define GPIO_PR2_M0PWM2 0x000F0806 +#define GPIO_PR2_LCDLP 0x000F080F + +#define GPIO_PR3_I2C2SDA 0x000F0C02 +#define GPIO_PR3_M0PWM3 0x000F0C06 +#define GPIO_PR3_LCDDATA03 0x000F0C0F + +#define GPIO_PR4_I2C3SCL 0x000F1002 +#define GPIO_PR4_T0CCP0 0x000F1003 +#define GPIO_PR4_M0PWM4 0x000F1006 +#define GPIO_PR4_LCDDATA00 0x000F100F + +#define GPIO_PR5_U1RX 0x000F1401 +#define GPIO_PR5_I2C3SDA 0x000F1402 +#define GPIO_PR5_T0CCP1 0x000F1403 +#define GPIO_PR5_M0PWM5 0x000F1406 +#define GPIO_PR5_LCDDATA01 0x000F140F + +#define GPIO_PR6_U1TX 0x000F1801 +#define GPIO_PR6_I2C4SCL 0x000F1802 +#define GPIO_PR6_T1CCP0 0x000F1803 +#define GPIO_PR6_M0PWM6 0x000F1806 +#define GPIO_PR6_LCDDATA04 0x000F180F + +#define GPIO_PR7_I2C4SDA 0x000F1C02 +#define GPIO_PR7_T1CCP1 0x000F1C03 +#define GPIO_PR7_M0PWM7 0x000F1C06 +#define GPIO_PR7_EN0TXEN 0x000F1C0E +#define GPIO_PR7_LCDDATA05 0x000F1C0F + +#define GPIO_PS0_T2CCP0 0x00100003 +#define GPIO_PS0_M0FAULT0 0x00100006 +#define GPIO_PS0_LCDDATA20 0x0010000F + +#define GPIO_PS1_T2CCP1 0x00100403 +#define GPIO_PS1_M0FAULT1 0x00100406 +#define GPIO_PS1_LCDDATA21 0x0010040F + +#define GPIO_PS2_U1DSR 0x00100801 +#define GPIO_PS2_T3CCP0 0x00100803 +#define GPIO_PS2_M0FAULT2 0x00100806 +#define GPIO_PS2_LCDDATA22 0x0010080F + +#define GPIO_PS3_T3CCP1 0x00100C03 +#define GPIO_PS3_M0FAULT3 0x00100C06 +#define GPIO_PS3_LCDDATA23 0x00100C0F + +#define GPIO_PS4_T4CCP0 0x00101003 +#define GPIO_PS4_PHA0 0x00101006 +#define GPIO_PS4_EN0TXD0 0x0010100E +#define GPIO_PS4_LCDDATA06 0x0010100F + +#define GPIO_PS5_T4CCP1 0x00101403 +#define GPIO_PS5_PHB0 0x00101406 +#define GPIO_PS5_EN0TXD1 0x0010140E +#define GPIO_PS5_LCDDATA07 0x0010140F + +#define GPIO_PS6_T5CCP0 0x00101803 +#define GPIO_PS6_IDX0 0x00101806 +#define GPIO_PS6_EN0RXER 0x0010180E +#define GPIO_PS6_LCDDATA08 0x0010180F + +#define GPIO_PS7_T5CCP1 0x00101C03 +#define GPIO_PS7_EN0RXDV 0x00101C0E +#define GPIO_PS7_LCDDATA09 0x00101C0F + +#define GPIO_PT0_T6CCP0 0x00110003 +#define GPIO_PT0_CAN0RX 0x00110007 +#define GPIO_PT0_EN0RXD0 0x0011000E +#define GPIO_PT0_LCDDATA10 0x0011000F + +#define GPIO_PT1_T6CCP1 0x00110403 +#define GPIO_PT1_CAN0TX 0x00110407 +#define GPIO_PT1_EN0RXD1 0x0011040E +#define GPIO_PT1_LCDDATA11 0x0011040F + +#define GPIO_PT2_T7CCP0 0x00110803 +#define GPIO_PT2_CAN1RX 0x00110807 +#define GPIO_PT2_LCDDATA18 0x0011080F + +#define GPIO_PT3_T7CCP1 0x00110C03 +#define GPIO_PT3_CAN1TX 0x00110C07 +#define GPIO_PT3_LCDDATA19 0x00110C0F + +#endif // PART_TM4C129XNCZAD + +#endif // __DRIVERLIB_PIN_MAP_H__ diff --git a/CCS/mm/src/inc/tivaware/pwm.h b/CCS/mm/src/inc/tivaware/pwm.h new file mode 100644 index 0000000..d473161 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/pwm.h @@ -0,0 +1,328 @@ +#include +#include +//***************************************************************************** +// +// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_PWM_H__ +#define __DRIVERLIB_PWM_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following defines are passed to PWMGenConfigure() as the ui32Config +// parameter and specify the configuration of the PWM generator. +// +//***************************************************************************** +#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode +#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode +#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates +#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates +#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode +#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode +#define PWM_GEN_MODE_FAULT_LATCHED \ + 0x00040000 // Fault is latched +#define PWM_GEN_MODE_FAULT_UNLATCHED \ + 0x00000000 // Fault is not latched +#define PWM_GEN_MODE_FAULT_MINPER \ + 0x00020000 // Enable min fault period +#define PWM_GEN_MODE_FAULT_NO_MINPER \ + 0x00000000 // Disable min fault period +#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support +#define PWM_GEN_MODE_FAULT_LEGACY \ + 0x00000000 // Disable extended fault support +#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur + // immediately +#define PWM_GEN_MODE_DB_SYNC_LOCAL \ + 0x0000A800 // Deadband updates locally + // synchronized +#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ + 0x0000FC00 // Deadband updates globally + // synchronized +#define PWM_GEN_MODE_GEN_NO_SYNC \ + 0x00000000 // Generator mode updates occur + // immediately +#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ + 0x00000280 // Generator mode updates locally + // synchronized +#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ + 0x000003C0 // Generator mode updates globally + // synchronized + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM generator interrupts and +// triggers. +// +//***************************************************************************** +#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 +#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD +#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U +#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D +#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U +#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D +#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 +#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD +#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D +#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U +#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D + +//***************************************************************************** +// +// Defines for enabling, disabling, and clearing PWM interrupts. +// +//***************************************************************************** +#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt +#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt +#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt +#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt +#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt +#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt +#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt +#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt +#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask + +//***************************************************************************** +// +// Defines to identify the generators within a module. +// +//***************************************************************************** +#define PWM_GEN_0 0x00000040 // Offset address of Gen0 +#define PWM_GEN_1 0x00000080 // Offset address of Gen1 +#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 +#define PWM_GEN_3 0x00000100 // Offset address of Gen3 + +#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 +#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 +#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 +#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 + +#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range +#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range +#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range +#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range + +//***************************************************************************** +// +// Defines to identify the outputs within a module. +// +//***************************************************************************** +#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 +#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 +#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 +#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 +#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 +#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 +#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 +#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 + +#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 +#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 +#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 +#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 +#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 +#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 +#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 +#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_0. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_0 0 + +#define PWM_FAULT_FAULT0 0x00000001 +#define PWM_FAULT_FAULT1 0x00000002 +#define PWM_FAULT_FAULT2 0x00000004 +#define PWM_FAULT_FAULT3 0x00000008 +#define PWM_FAULT_ACMP0 0x00010000 +#define PWM_FAULT_ACMP1 0x00020000 +#define PWM_FAULT_ACMP2 0x00040000 + +//***************************************************************************** +// +// Defines to identify each of the possible fault trigger conditions in +// PWM_FAULT_GROUP_1. +// +//***************************************************************************** +#define PWM_FAULT_GROUP_1 1 + +#define PWM_FAULT_DCMP0 0x00000001 +#define PWM_FAULT_DCMP1 0x00000002 +#define PWM_FAULT_DCMP2 0x00000004 +#define PWM_FAULT_DCMP3 0x00000008 +#define PWM_FAULT_DCMP4 0x00000010 +#define PWM_FAULT_DCMP5 0x00000020 +#define PWM_FAULT_DCMP6 0x00000040 +#define PWM_FAULT_DCMP7 0x00000080 + +//***************************************************************************** +// +// Defines to identify the sense of each of the external FAULTn signals +// +//***************************************************************************** +#define PWM_FAULT0_SENSE_HIGH 0x00000000 +#define PWM_FAULT0_SENSE_LOW 0x00000001 +#define PWM_FAULT1_SENSE_HIGH 0x00000000 +#define PWM_FAULT1_SENSE_LOW 0x00000002 +#define PWM_FAULT2_SENSE_HIGH 0x00000000 +#define PWM_FAULT2_SENSE_LOW 0x00000004 +#define PWM_FAULT3_SENSE_HIGH 0x00000000 +#define PWM_FAULT3_SENSE_LOW 0x00000008 + +//***************************************************************************** +// +// Defines that can be passed to the PWMClockSet() API as the ui32Config +// parameter, and can be returned by the PWMClockGet() API. +// +//***************************************************************************** +#define PWM_SYSCLK_DIV_1 0x00000000 // PWM clock is system clock +#define PWM_SYSCLK_DIV_2 0x00000100 // PWM clock is system clock /2 +#define PWM_SYSCLK_DIV_4 0x00000101 // PWM clock is system clock /4 +#define PWM_SYSCLK_DIV_8 0x00000102 // PWM clock is system clock /8 +#define PWM_SYSCLK_DIV_16 0x00000103 // PWM clock is system clock /16 +#define PWM_SYSCLK_DIV_32 0x00000104 // PWM clock is system clock /32 +#define PWM_SYSCLK_DIV_64 0x00000105 // PWM clock is system clock /64 + +//***************************************************************************** +// +// Defines passed to PWMOutputUpdateMode() to identify the synchronization mode +// to use when enabling or disabling outputs using PWMOutputState(). +// +//***************************************************************************** +#define PWM_OUTPUT_MODE_NO_SYNC 0x00000000 // Updates to occur immediately +#define PWM_OUTPUT_MODE_SYNC_LOCAL \ + 0x00000002 // Updates are locally synchronized +#define PWM_OUTPUT_MODE_SYNC_GLOBAL \ + 0x00000003 // Updates are globally synchronized + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void PWMGenConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Config); +extern void PWMGenPeriodSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Period); +extern uint32_t PWMGenPeriodGet(uint32_t ui32Base, + uint32_t ui32Gen); +extern void PWMGenEnable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMGenDisable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMPulseWidthSet(uint32_t ui32Base, uint32_t ui32PWMOut, + uint32_t ui32Width); +extern uint32_t PWMPulseWidthGet(uint32_t ui32Base, + uint32_t ui32PWMOut); +extern void PWMDeadBandEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint16_t ui16Rise, uint16_t ui16Fall); +extern void PWMDeadBandDisable(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMSyncUpdate(uint32_t ui32Base, uint32_t ui32GenBits); +extern void PWMSyncTimeBase(uint32_t ui32Base, uint32_t ui32GenBits); +extern void PWMOutputState(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bEnable); +extern void PWMOutputInvert(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bInvert); +extern void PWMOutputFaultLevel(uint32_t ui32Base, + uint32_t ui32PWMOutBits, + bool bDriveHigh); +extern void PWMOutputFault(uint32_t ui32Base, uint32_t ui32PWMOutBits, + bool bFaultSuppress); +extern void PWMGenIntRegister(uint32_t ui32Base, uint32_t ui32Gen, + void (*pfnIntHandler)(void)); +extern void PWMGenIntUnregister(uint32_t ui32Base, uint32_t ui32Gen); +extern void PWMFaultIntRegister(uint32_t ui32Base, + void (*pfnIntHandler)(void)); +extern void PWMFaultIntUnregister(uint32_t ui32Base); +extern void PWMGenIntTrigEnable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig); +extern void PWMGenIntTrigDisable(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32IntTrig); +extern uint32_t PWMGenIntStatus(uint32_t ui32Base, uint32_t ui32Gen, + bool bMasked); +extern void PWMGenIntClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Ints); +extern void PWMIntEnable(uint32_t ui32Base, uint32_t ui32GenFault); +extern void PWMIntDisable(uint32_t ui32Base, uint32_t ui32GenFault); +extern void PWMFaultIntClear(uint32_t ui32Base); +extern uint32_t PWMIntStatus(uint32_t ui32Base, bool bMasked); +extern void PWMFaultIntClearExt(uint32_t ui32Base, + uint32_t ui32FaultInts); +extern void PWMGenFaultConfigure(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32MinFaultPeriod, + uint32_t ui32FaultSenses); +extern void PWMGenFaultTriggerSet(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, + uint32_t ui32FaultTriggers); +extern uint32_t PWMGenFaultTriggerGet(uint32_t ui32Base, + uint32_t ui32Gen, + uint32_t ui32Group); +extern uint32_t PWMGenFaultStatus(uint32_t ui32Base, + uint32_t ui32Gen, + uint32_t ui32Group); +extern void PWMGenFaultClear(uint32_t ui32Base, uint32_t ui32Gen, + uint32_t ui32Group, + uint32_t ui32FaultTriggers); +extern void PWMClockSet(uint32_t ui32Base, uint32_t ui32Config); +extern uint32_t PWMClockGet(uint32_t ui32Base); +extern void PWMOutputUpdateMode(uint32_t ui32Base, + uint32_t ui32PWMOutBits, + uint32_t ui32Mode); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_PWM_H__ diff --git a/CCS/mm/src/inc/tivaware/qei.h b/CCS/mm/src/inc/tivaware/qei.h new file mode 100644 index 0000000..3f9b020 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/qei.h @@ -0,0 +1,156 @@ +#include +#include +//***************************************************************************** +// +// qei.h - Prototypes for the Quadrature Encoder Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_QEI_H__ +#define __DRIVERLIB_QEI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to QEIConfigure as the ui32Config paramater. +// +//***************************************************************************** +#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only +#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges +#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse +#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse +#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature +#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir +#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB +#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB + +//***************************************************************************** +// +// Values that can be passed to QEIFilterConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_FILTCNT_2 0x00000000 // Filter Count of 2 System Clocks +#define QEI_FILTCNT_3 0x00010000 // Filter Count of 3 System Clocks +#define QEI_FILTCNT_4 0x00020000 // Filter Count of 4 System Clocks +#define QEI_FILTCNT_5 0x00030000 // Filter Count of 5 System Clocks +#define QEI_FILTCNT_6 0x00040000 // Filter Count of 6 System Clocks +#define QEI_FILTCNT_7 0x00050000 // Filter Count of 7 System Clocks +#define QEI_FILTCNT_8 0x00060000 // Filter Count of 8 System Clocks +#define QEI_FILTCNT_9 0x00070000 // Filter Count of 9 System Clocks +#define QEI_FILTCNT_10 0x00080000 // Filter Count of 10 System Clocks +#define QEI_FILTCNT_11 0x00090000 // Filter Count of 11 System Clocks +#define QEI_FILTCNT_12 0x000A0000 // Filter Count of 12 System Clocks +#define QEI_FILTCNT_13 0x000B0000 // Filter Count of 13 System Clocks +#define QEI_FILTCNT_14 0x000C0000 // Filter Count of 14 System Clocks +#define QEI_FILTCNT_15 0x000D0000 // Filter Count of 15 System Clocks +#define QEI_FILTCNT_16 0x000E0000 // Filter Count of 16 System Clocks +#define QEI_FILTCNT_17 0x000F0000 // Filter Count of 17 System Clocks + +//***************************************************************************** +// +// Values that can be passed to QEIVelocityConfigure as the ui32PreDiv +// parameter. +// +//***************************************************************************** +#define QEI_VELDIV_1 0x00000000 // Predivide by 1 +#define QEI_VELDIV_2 0x00000040 // Predivide by 2 +#define QEI_VELDIV_4 0x00000080 // Predivide by 4 +#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 +#define QEI_VELDIV_16 0x00000100 // Predivide by 16 +#define QEI_VELDIV_32 0x00000140 // Predivide by 32 +#define QEI_VELDIV_64 0x00000180 // Predivide by 64 +#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 + +//***************************************************************************** +// +// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts +// as the ui32IntFlags parameter, and returned by QEIGetIntStatus. +// +//***************************************************************************** +#define QEI_INTERROR 0x00000008 // Phase error detected +#define QEI_INTDIR 0x00000004 // Direction change +#define QEI_INTTIMER 0x00000002 // Velocity timer expired +#define QEI_INTINDEX 0x00000001 // Index pulse detected + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void QEIEnable(uint32_t ui32Base); +extern void QEIDisable(uint32_t ui32Base); +extern void QEIConfigure(uint32_t ui32Base, uint32_t ui32Config, + uint32_t ui32MaxPosition); +extern uint32_t QEIPositionGet(uint32_t ui32Base); +extern void QEIPositionSet(uint32_t ui32Base, uint32_t ui32Position); +extern int32_t QEIDirectionGet(uint32_t ui32Base); +extern bool QEIErrorGet(uint32_t ui32Base); +extern void QEIFilterEnable(uint32_t ui32Base); +extern void QEIFilterDisable(uint32_t ui32Base); +extern void QEIFilterConfigure(uint32_t ui32Base, uint32_t ui32FiltCnt); +extern void QEIVelocityEnable(uint32_t ui32Base); +extern void QEIVelocityDisable(uint32_t ui32Base); +extern void QEIVelocityConfigure(uint32_t ui32Base, uint32_t ui32PreDiv, + uint32_t ui32Period); +extern uint32_t QEIVelocityGet(uint32_t ui32Base); +extern void QEIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void QEIIntUnregister(uint32_t ui32Base); +extern void QEIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void QEIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t QEIIntStatus(uint32_t ui32Base, bool bMasked); +extern void QEIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_QEI_H__ diff --git a/CCS/mm/src/inc/tivaware/rom.h b/CCS/mm/src/inc/tivaware/rom.h new file mode 100644 index 0000000..df53398 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/rom.h @@ -0,0 +1,8350 @@ +#include +#include +//***************************************************************************** +// +// rom.h - Macros to facilitate calling functions in the ROM. +// +// Copyright (c) 2007-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_ROM_H__ +#define __DRIVERLIB_ROM_H__ + +#define TARGET_IS_TM4C123_RB1 + +#ifndef DEPRECATED +//***************************************************************************** +// +// ROM selection labels changed between TivaWare 2.0.1 and 2.1. The following +// labels are intended to ensure backwards compatibility for applications +// which have not yet been updated to use the replacement labels. +// +//***************************************************************************** +#ifdef TARGET_IS_SNOWFLAKE_RA0 +#define TARGET_IS_TM4C129_RA0 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA1 +#define TARGET_IS_TM4C129_RA1 +#endif +#ifdef TARGET_IS_SNOWFLAKE_RA2 +#define TARGET_IS_TM4C129_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA1 +#define TARGET_IS_TM4C123_RA1 +#endif +#ifdef TARGET_IS_BLIZZARD_RA2 +#define TARGET_IS_TM4C123_RA2 +#endif +#ifdef TARGET_IS_BLIZZARD_RA3 +#define TARGET_IS_TM4C123_RA3 +#endif +#ifdef TARGET_IS_BLIZZARD_RB0 +#define TARGET_IS_TM4C123_RB0 +#endif +#ifdef TARGET_IS_BLIZZARD_RB1 +#define TARGET_IS_TM4C123_RB1 +#endif +#endif + +//***************************************************************************** +// +// Pointers to the main API tables. +// +//***************************************************************************** +#define ROM_APITABLE ((uint32_t *)0x01000010) +#define ROM_VERSION (ROM_APITABLE[0]) +#define ROM_UARTTABLE ((uint32_t *)(ROM_APITABLE[1])) +#define ROM_SSITABLE ((uint32_t *)(ROM_APITABLE[2])) +#define ROM_I2CTABLE ((uint32_t *)(ROM_APITABLE[3])) +#define ROM_GPIOTABLE ((uint32_t *)(ROM_APITABLE[4])) +#define ROM_ADCTABLE ((uint32_t *)(ROM_APITABLE[5])) +#define ROM_COMPARATORTABLE ((uint32_t *)(ROM_APITABLE[6])) +#define ROM_FLASHTABLE ((uint32_t *)(ROM_APITABLE[7])) +#define ROM_PWMTABLE ((uint32_t *)(ROM_APITABLE[8])) +#define ROM_QEITABLE ((uint32_t *)(ROM_APITABLE[9])) +#define ROM_SYSTICKTABLE ((uint32_t *)(ROM_APITABLE[10])) +#define ROM_TIMERTABLE ((uint32_t *)(ROM_APITABLE[11])) +#define ROM_WATCHDOGTABLE ((uint32_t *)(ROM_APITABLE[12])) +#define ROM_SYSCTLTABLE ((uint32_t *)(ROM_APITABLE[13])) +#define ROM_INTERRUPTTABLE ((uint32_t *)(ROM_APITABLE[14])) +#define ROM_USBTABLE ((uint32_t *)(ROM_APITABLE[16])) +#define ROM_UDMATABLE ((uint32_t *)(ROM_APITABLE[17])) +#define ROM_CANTABLE ((uint32_t *)(ROM_APITABLE[18])) +#define ROM_HIBERNATETABLE ((uint32_t *)(ROM_APITABLE[19])) +#define ROM_MPUTABLE ((uint32_t *)(ROM_APITABLE[20])) +#define ROM_SOFTWARETABLE ((uint32_t *)(ROM_APITABLE[21])) +#define ROM_EPITABLE ((uint32_t *)(ROM_APITABLE[23])) +#define ROM_EEPROMTABLE ((uint32_t *)(ROM_APITABLE[24])) +#define ROM_FPUTABLE ((uint32_t *)(ROM_APITABLE[26])) +#define ROM_SMBUSTABLE ((uint32_t *)(ROM_APITABLE[29])) +#define ROM_SYSEXCTABLE ((uint32_t *)(ROM_APITABLE[30])) +#define ROM_ONEWIRETABLE ((uint32_t *)(ROM_APITABLE[34])) +#define ROM_SPIFLASHTABLE ((uint32_t *)(ROM_APITABLE[38])) +#define ROM_LCDTABLE ((uint32_t *)(ROM_APITABLE[41])) +#define ROM_EMACTABLE ((uint32_t *)(ROM_APITABLE[42])) +#define ROM_AESTABLE ((uint32_t *)(ROM_APITABLE[43])) +#define ROM_CRCTABLE ((uint32_t *)(ROM_APITABLE[44])) +#define ROM_DESTABLE ((uint32_t *)(ROM_APITABLE[45])) +#define ROM_SHAMD5TABLE ((uint32_t *)(ROM_APITABLE[46])) + +//***************************************************************************** +// +// Macros for calling ROM functions in the ADC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t *pui32Buffer))ROM_ADCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + bool bMasked))ROM_ADCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Trigger, \ + uint32_t ui32Priority))ROM_ADCTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceStepConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum, \ + uint32_t ui32Step, \ + uint32_t ui32Config))ROM_ADCTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceOverflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflow \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceUnderflowClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCProcessorTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCHardwareOversampleConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Factor))ROM_ADCTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_ADCTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorRegionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32LowRef, \ + uint32_t ui32HighRef))ROM_ADCTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bTrigger, \ + bool bInterrupt))ROM_ADCTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Status))ROM_ADCTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_ADCTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCReferenceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelaySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Phase))ROM_ADCTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCPhaseDelayGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ADCTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ADCTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ADCTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCSequenceDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SequenceNum))ROM_ADCTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ADCBusy \ + ((bool (*)(uint32_t ui32Base))ROM_ADCTABLE[34]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the AES API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_AESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESAuthLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_AESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_AESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t ui32Length, \ + uint32_t *pui32Tag))ROM_AESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_AESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataProcessAuth \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length, \ + uint32_t *pui32AuthSrc, \ + uint32_t ui32AuthLength, \ + uint32_t *pui32Tag))ROM_AESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_AESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_AESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_AESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_AESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey1Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey2Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t ui32Keysize))ROM_AESTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESKey3Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_AESTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Length))ROM_AESTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESReset \ + ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESTagRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TagData))ROM_AESTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_AESIVRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_AESTABLE[22]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CAN API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntClr))ROM_CANTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANInit \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANEnable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANDisable \ + ((void (*)(uint32_t ui32Base))ROM_CANTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingSet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitTimingGet \ + ((void (*)(uint32_t ui32Base, \ + tCANBitClkParms *psClkParms))ROM_CANTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + tMsgObjType eMsgType))ROM_CANTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID, \ + tCANMsgObject *psMsgObject, \ + bool bClrPendingInt))ROM_CANTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANStatusGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANStsReg eStatusReg))ROM_CANTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANMessageClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ObjID))ROM_CANTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_CANTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + tCANIntStsReg eIntStsReg))ROM_CANTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetryGet \ + ((bool (*)(uint32_t ui32Base))ROM_CANTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANRetrySet \ + ((void (*)(uint32_t ui32Base, \ + bool bAutoRetry))ROM_CANTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANErrCntrGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32RxCount, \ + uint32_t *pui32TxCount))ROM_CANTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CANBitRateSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32SourceClock, \ + uint32_t ui32BitRate))ROM_CANTABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Comparator API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + uint32_t ui32Config))ROM_COMPARATORTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorRefSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ref))ROM_COMPARATORTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorValueGet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Comp))ROM_COMPARATORTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_ComparatorIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32Comp, \ + bool bMasked))ROM_COMPARATORTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the CRC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataProcess \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32DataIn, \ + uint32_t ui32DataLength, \ + bool bPPResult))ROM_CRCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_CRCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCResultRead \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bPPResult))ROM_CRCTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_CRCSeedSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seed))ROM_CRCTABLE[4]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the DES API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_DESTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_DESTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataReadNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_DESTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataProcess \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src, \ + uint32_t *pui32Dest, \ + uint32_t ui32Length))ROM_DESTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_DESTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_DESTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_DESTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESIVSet \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32IVdata))ROM_DESTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key))ROM_DESTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_DESTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_DESReset \ + ((void (*)(uint32_t ui32Base))ROM_DESTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EEPROM API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMRead \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockCountGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockHide \ + ((void (*)(uint32_t ui32Block))ROM_EEPROMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockLock \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockPasswordSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectGet \ + ((uint32_t (*)(uint32_t ui32Block))ROM_EEPROMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockProtectSet \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t ui32Protect))ROM_EEPROMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMBlockUnlock \ + ((uint32_t (*)(uint32_t ui32Block, \ + uint32_t *pui32Password, \ + uint32_t ui32Count))ROM_EEPROMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_EEPROMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_EEPROMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) +#define ROM_EEPROMMassErase \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgram \ + ((uint32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_EEPROMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMProgramNonBlocking \ + ((uint32_t (*)(uint32_t ui32Data, \ + uint32_t ui32Address))ROM_EEPROMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMSizeGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMStatusGet \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EEPROMInit \ + ((uint32_t (*)(void))ROM_EEPROMTABLE[17]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EPI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EPITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_EPITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Divider))ROM_EPITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigSDRAMSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32Refresh))ROM_EPITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigGPModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32FrameCount, \ + uint32_t ui32MaxWait))ROM_EPITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16Set \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxWait))ROM_EPITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIAddressMapSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Map))ROM_EPITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32DataSize, \ + uint32_t ui32Address))ROM_EPITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStart \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Count))ROM_EPITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadStop \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadCount \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_EPITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadAvail \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet32 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t *pui32Buf))ROM_EPITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet16 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint16_t *pui16Buf))ROM_EPITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPINonBlockingReadGet8 \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint8_t *pui8Buf))ROM_EPITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIFIFOConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EPITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIWriteFIFOCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EPITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EPITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIIntErrorClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ErrFlags))ROM_EPITABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDividerCSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Divider))ROM_EPITABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIDMATxCount \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count))ROM_EPITABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16CSSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB8TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIConfigHB16TimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32Config))ROM_EPITABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t ui32CR))ROM_EPITABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint32_t *pui32CR))ROM_EPITABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EPIPSRAMConfigRegGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_EPITABLE[31]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the EMAC API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_EMACTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint8_t *pui8MACAddr))ROM_EMACTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + const uint8_t *pui8MACAddr))ROM_EMACTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Config, \ + uint32_t *pui32Mode, \ + uint32_t *pui32RxMaxFrameSize))ROM_EMACTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32ModeFlags, \ + uint32_t ui32RxMaxFrameSize))ROM_EMACTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACDMAStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FilterOpts))ROM_EMACTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SysClk, \ + uint32_t ui32BusConfig, \ + uint32_t ui32RxBurst, \ + uint32_t ui32TxBurst, \ + uint32_t ui32DescSkipSize))ROM_EMACTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_EMACTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOff \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYPowerOn \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr))ROM_EMACTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr))ROM_EMACTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint8_t ui8RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACReset \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRxWatchdogTimerSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Timeout))ROM_EMACTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentBufferGet \ + ((uint8_t * (*)(uint32_t ui32Base))ROM_EMACTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMACurrentDescriptorGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListGet \ + ((tEMACDMADescriptor * (*)(uint32_t ui32Base))ROM_EMACTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMADescriptorListSet \ + ((void (*)(uint32_t ui32Base, \ + tEMACDMADescriptor *pDescriptor))ROM_EMACTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxDMAPollDemand \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTxFlush \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Index))ROM_EMACTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACAddrFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Index, \ + uint32_t ui32Config))ROM_EMACTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterBitCalculate \ + ((uint32_t (*)(uint8_t *pui8MACAddr))ROM_EMACTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32HashHi, \ + uint32_t *pui32HashLo))ROM_EMACTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32HashHi, \ + uint32_t ui32HashLo))ROM_EMACTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACNumAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr))ROM_EMACTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPHYExtendedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8PhyAddr, \ + uint16_t ui16RegAddr, \ + uint16_t ui16Data))ROM_EMACTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_EMACTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACPowerManagementStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterGet \ + ((void (*)(uint32_t ui32Base, \ + tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACRemoteWakeUpFrameFilterSet \ + ((void (*)(uint32_t ui32Base, \ + const tEMACWakeUpFrameFilter *pFilter))ROM_EMACTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampAddendSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds))ROM_EMACTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32SubSecondInc))ROM_EMACTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32SubSecondInc))ROM_EMACTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommand \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Cmd))ROM_EMACTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSCommandModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_EMACTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Period, \ + uint32_t ui32Width))ROM_EMACTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampPPSSimpleModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FreqConfig))ROM_EMACTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Seconds, \ + uint32_t *pui32SubSeconds))ROM_EMACTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds))ROM_EMACTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampSysTimeUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32SubSeconds, \ + bool bInc))ROM_EMACTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_EMACTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACTimestampTargetSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Seconds, \ + uint32_t ui32Nanoseconds))ROM_EMACTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterBitCalculate \ + ((uint32_t (*)(uint16_t ui16Tag))ROM_EMACTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_EMACTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANHashFilterSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Hash))ROM_EMACTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANRxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint16_t *pui16Tag))ROM_EMACTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_EMACVLANTxConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint16_t ui16Tag, \ + uint32_t ui32Config))ROM_EMACTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateEMAC \ + ((void (*)(uint32_t ui32Clock))ROM_EMACTABLE[71]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Flash API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProgram \ + ((int32_t (*)(uint32_t *pui32Data, \ + uint32_t ui32Address, \ + uint32_t ui32Count))ROM_FLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashErase \ + ((int32_t (*)(uint32_t ui32Address))ROM_FLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectGet \ + ((tFlashProtection (*)(uint32_t ui32Address))ROM_FLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSet \ + ((int32_t (*)(uint32_t ui32Address, \ + tFlashProtection eProtect))ROM_FLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashProtectSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserGet \ + ((int32_t (*)(uint32_t *pui32User0, \ + uint32_t *pui32User1))ROM_FLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSet \ + ((int32_t (*)(uint32_t ui32User0, \ + uint32_t ui32User1))ROM_FLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashUserSave \ + ((int32_t (*)(void))ROM_FLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_FLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FlashIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_FLASHTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the FPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUEnable \ + ((void (*)(void))ROM_FPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUDisable \ + ((void (*)(void))ROM_FPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUFlushToZeroModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUHalfPrecisionModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPULazyStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUNaNModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPURoundingModeSet \ + ((void (*)(uint32_t ui32Mode))ROM_FPUTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingDisable \ + ((void (*)(void))ROM_FPUTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_FPUStackingEnable \ + ((void (*)(void))ROM_FPUTABLE[8]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the GPIO API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinWrite \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint8_t ui8Val))ROM_GPIOTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32PinIO))ROM_GPIOTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODirModeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32IntType))ROM_GPIOTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntTypeGet \ + ((uint32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pin))ROM_GPIOTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPadConfigSet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins, \ + uint32_t ui32Strength, \ + uint32_t ui32PadType))ROM_GPIOTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPadConfigGet \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pin, \ + uint32_t *pui32Strength, \ + uint32_t *pui32PadType))ROM_GPIOTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinRead \ + ((int32_t (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_GPIOPinTypeCAN \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeComparator \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOInput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutput \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2C \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypePWM \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeQEI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeSSI \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeTimer \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUART \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeGPIOOutputOD \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeADC \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBDigital \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinConfigure \ + ((void (*)(uint32_t ui32PinConfig))ROM_GPIOTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeUSBAnalog \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIODMATriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerEnable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOADCTriggerDisable \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeI2CSCL \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeOneWire \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeHigh \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOPinTypeWakeLow \ + ((void (*)(uint32_t ui32Port, \ + uint8_t ui8Pins))ROM_GPIOTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntClear \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntDisable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntEnable \ + ((void (*)(uint32_t ui32Port, \ + uint32_t ui32IntFlags))ROM_GPIOTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_GPIOIntStatus \ + ((uint32_t (*)(uint32_t ui32Port, \ + bool bMasked))ROM_GPIOTABLE[54]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Hibernate API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateEnableExpClk \ + ((void (*)(uint32_t ui32HibClk))ROM_HIBERNATETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeSet \ + ((void (*)(uint32_t ui32WakeFlags))ROM_HIBERNATETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateWakeGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatSet \ + ((void (*)(uint32_t ui32LowBatFlags))ROM_HIBERNATETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateLowBatGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSet \ + ((void (*)(uint32_t ui32RTCValue))ROM_HIBERNATETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimSet \ + ((void (*)(uint32_t ui32Trim))ROM_HIBERNATETABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCTrimGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataSet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateDataGet \ + ((void (*)(uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_HIBERNATETABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRequest \ + ((void (*)(void))ROM_HIBERNATETABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_HIBERNATETABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_HIBERNATETABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateIsActive \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateClockConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckStart \ + ((void (*)(void))ROM_HIBERNATETABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateBatCheckDone \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateGPIORetentionGet \ + ((bool (*)(void))ROM_HIBERNATETABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCounterMode \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarSet \ + ((void (*)(struct tm *psTime))ROM_HIBERNATETABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarGet \ + ((int (*)(struct tm *psTime))ROM_HIBERNATETABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchSet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateCalendarMatchGet \ + ((void (*)(uint32_t ui32Index, \ + struct tm *psTime))ROM_HIBERNATETABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperDisable \ + ((void (*)(void))ROM_HIBERNATETABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEnable \ + ((void (*)(void))ROM_HIBERNATETABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsClear \ + ((void (*)(void))ROM_HIBERNATETABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsConfig \ + ((void (*)(uint32_t ui32Config))ROM_HIBERNATETABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperEventsGet \ + ((bool (*)(uint32_t ui32Index, \ + uint32_t *pui32RTC, \ + uint32_t *pui32Event))ROM_HIBERNATETABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscValid \ + ((bool (*)(void))ROM_HIBERNATETABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperExtOscRecover \ + ((void (*)(void))ROM_HIBERNATETABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIODisable \ + ((void (*)(uint32_t ui32Input))ROM_HIBERNATETABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperIOEnable \ + ((void (*)(uint32_t ui32Input, \ + uint32_t ui32Config))ROM_HIBERNATETABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateTamperStatusGet \ + ((uint32_t (*)(void))ROM_HIBERNATETABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchGet \ + ((uint32_t (*)(uint32_t ui32Match))ROM_HIBERNATETABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_HibernateRTCSSMatchSet \ + ((void (*)(uint32_t ui32Match, \ + uint32_t ui32Value))ROM_HIBERNATETABLE[52]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the I2C API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterInitExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32I2CClk, \ + bool bFast))ROM_I2CTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveInit \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatus \ + ((bool (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClear \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterSlaveAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8SlaveAddr, \ + bool bReceive))ROM_I2CTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBusBusy \ + ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Cmd))ROM_I2CTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterErr \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveDataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateI2C \ + ((void (*)(void))ROM_I2CTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntEnableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntDisableEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntStatusEx \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_I2CTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterIntClearEx \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_I2CTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterTimeoutSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Value))ROM_I2CTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKOverride \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_I2CTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveACKValueSet \ + ((void (*)(uint32_t ui32Base, \ + bool bACK))ROM_I2CTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8AddrNum, \ + uint8_t ui8SlaveAddr))ROM_I2CTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterLineStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CTxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CRxFIFOFlush \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFOStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPut \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataPutNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Data))ROM_I2CTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CFIFODataGetNonBlocking \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t *pui8Data))ROM_I2CTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Length))ROM_I2CTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterBurstCountGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CSlaveFIFOEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_I2CMasterGlitchFilterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_I2CTABLE[54]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Interrupt API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntEnable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterEnable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntMasterDisable \ + ((bool (*)(void))ROM_INTERRUPTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntDisable \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingSet \ + ((void (*)(uint32_t ui32Bits))ROM_INTERRUPTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGroupingGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPrioritySet \ + ((void (*)(uint32_t ui32Interrupt, \ + uint8_t ui8Priority))ROM_INTERRUPTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityGet \ + ((int32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendSet \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPendClear \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskSet \ + ((void (*)(uint32_t ui32PriorityMask))ROM_INTERRUPTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntPriorityMaskGet \ + ((uint32_t (*)(void))ROM_INTERRUPTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntIsEnabled \ + ((uint32_t (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_IntTrigger \ + ((void (*)(uint32_t ui32Interrupt))ROM_INTERRUPTTABLE[13]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the LCD API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_LCDTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDClockReset \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clocks))ROM_LCDTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDCommandWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Cmd))ROM_LCDTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_LCDTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Data))ROM_LCDTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMADisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDDMAWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const uint32_t *pui32Data, \ + uint32_t ui32Count))ROM_LCDTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr))ROM_LCDTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDIndexedWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + uint16_t ui16Addr, \ + uint16_t ui16Data))ROM_LCDTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDStatusRead \ + ((uint16_t (*)(uint32_t ui32Base, \ + uint32_t ui32CS))ROM_LCDTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIDDTimingSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32CS, \ + const tLCDIDDTiming *pTiming))ROM_LCDTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_LCDTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDModeSet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint8_t ui8Mode, \ + uint32_t ui32PixClk, \ + uint32_t ui32SysClk))ROM_LCDTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterACBiasIntCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Count))ROM_LCDTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint8_t ui8PalLoadDelay))ROM_LCDTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterFrameBufferSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Buffer, \ + uint32_t *pui32Addr, \ + uint32_t ui32NumBytes))ROM_LCDTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterPaletteSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type, \ + uint32_t *pui32PalAddr, \ + const uint32_t *pui32SrcColors, \ + uint32_t ui32Start, \ + uint32_t ui32Count))ROM_LCDTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags, \ + uint32_t ui32BottomLines, \ + uint32_t ui32DefaultPixel))ROM_LCDTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelDisable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterSubPanelEnable \ + ((void (*)(uint32_t ui32Base))ROM_LCDTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterTimingSet \ + ((void (*)(uint32_t ui32Base, \ + const tLCDRasterTiming *pTiming))ROM_LCDTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_LCDRasterEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_LCDTABLE[27]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the MPU API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUEnable \ + ((void (*)(uint32_t ui32MPUConfig))ROM_MPUTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPUDisable \ + ((void (*)(void))ROM_MPUTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionCountGet \ + ((uint32_t (*)(void))ROM_MPUTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionEnable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionDisable \ + ((void (*)(uint32_t ui32Region))ROM_MPUTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionSet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_MPUTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_MPURegionGet \ + ((void (*)(uint32_t ui32Region, \ + uint32_t *pui32Addr, \ + uint32_t *pui32Flags))ROM_MPUTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the OneWire API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_ONEWIRETABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusReset \ + ((void (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireBusStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_ONEWIRETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGet \ + ((void (*)(uint32_t u3i2Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDataGetNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_ONEWIRETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32InitFlags))ROM_ONEWIRETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_ONEWIRETABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireTransaction \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32OpFlags, \ + uint32_t ui32Data, \ + uint32_t ui32BitCnt))ROM_ONEWIRETABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_OneWireDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_ONEWIRETABLE[11]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the PWM API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut, \ + uint32_t ui32Width))ROM_PWMTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Config))ROM_PWMTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Period))ROM_PWMTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenPeriodGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMPulseWidthGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOut))ROM_PWMTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint16_t ui16Rise, \ + uint16_t ui16Fall))ROM_PWMTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMDeadBandDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen))ROM_PWMTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncUpdate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMSyncTimeBase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenBits))ROM_PWMTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputState \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bEnable))ROM_PWMTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputInvert \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bInvert))ROM_PWMTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFault \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bFaultSuppress))ROM_PWMTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntTrigDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32IntTrig))ROM_PWMTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + bool bMasked))ROM_PWMTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Ints))ROM_PWMTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32GenFault))ROM_PWMTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClear \ + ((void (*)(uint32_t ui32Base))ROM_PWMTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_PWMTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputFaultLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + bool bDriveHigh))ROM_PWMTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMFaultIntClearExt \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32FaultInts))ROM_PWMTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32MinFaultPeriod, \ + uint32_t ui32FaultSenses))ROM_PWMTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultTriggerGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group))ROM_PWMTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMGenFaultClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Gen, \ + uint32_t ui32Group, \ + uint32_t ui32FaultTriggers))ROM_PWMTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_PWMTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMClockGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_PWMTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_PWMOutputUpdateMode \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PWMOutBits, \ + uint32_t ui32Mode))ROM_PWMTABLE[31]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the QEI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config, \ + uint32_t ui32MaxPosition))ROM_QEITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIPositionSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Position))ROM_QEITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIDirectionGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_QEITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIErrorGet \ + ((bool (*)(uint32_t ui32Base))ROM_QEITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityEnable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityDisable \ + ((void (*)(uint32_t ui32Base))ROM_QEITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32PreDiv, \ + uint32_t ui32Period))ROM_QEITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIVelocityGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_QEITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_QEITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_QEIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_QEITABLE[14]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SHAMD5 API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SHAMD5TABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SHAMD5TABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWrite \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DataWriteNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMADisable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5DMAEnable \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HashLengthSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Length))ROM_SHAMD5TABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeyGenerate \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Key, \ + uint32_t *pui32PPKey))ROM_SHAMD5TABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACPPKeySet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Src))ROM_SHAMD5TABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5HMACProcess \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32DataSrc, \ + uint32_t ui32DataLength, \ + uint32_t *pui32HashResult))ROM_SHAMD5TABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5IntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SHAMD5TABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5Reset \ + ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SHAMD5ResultRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Dest))ROM_SHAMD5TABLE[16]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SMBus API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketDecode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t *pui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusARPUDIDPacketEncode \ + ((void (*)(tSMBusUDID *pUDID, \ + uint8_t ui8Address, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPAssignAddress \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPGetUDIDGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPNotifyMaster \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPPrepareToARP \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceDir \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress))ROM_SMBUSTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterARPResetDeviceGen \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterBlockWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteReceive \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Data))ROM_SMBUSTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterByteWordWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterHostNotify \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8OwnSlaveAddress, \ + uint8_t *pui8Data))ROM_SMBUSTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWrite \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterI2CWriteRead \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t *pui8TxData, \ + uint8_t ui8TxSize, \ + uint8_t *pui8RxData, \ + uint8_t ui8RxSize))ROM_SMBUSTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase, \ + uint32_t ui32SMBusClock))ROM_SMBUSTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterProcessCall \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + uint8_t ui8Command, \ + uint8_t *pui8TxData, \ + uint8_t *pui8RxData))ROM_SMBUSTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusMasterQuickCommand \ + ((tSMBusStatus (*)(tSMBus *psSMBus, \ + uint8_t ui8TargetAddress, \ + bool bData))ROM_SMBUSTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusPECEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusRxPacketSizeGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveACKSend \ + ((void (*)(tSMBus *psSMBus, \ + bool bACK))ROM_SMBUSTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveAddressSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8AddressNum, \ + uint8_t ui8SlaveAddress))ROM_SMBUSTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagARSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveARPFlagAVSet \ + ((void (*)(tSMBus *psSMBus, \ + bool bValue))ROM_SMBUSTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveBlockTransferEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveCommandGet \ + ((uint8_t (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveI2CEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveInit \ + ((void (*)(tSMBus *psSMBus, \ + uint32_t ui32I2CBase))ROM_SMBUSTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntAddressGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveIntProcess \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveManualACKStatusGet \ + ((bool (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallDisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveProcessCallEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveRxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTransferInit \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveTxBufferSet \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t *pui8Data, \ + uint8_t ui8Size))ROM_SMBUSTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveUDIDSet \ + ((void (*)(tSMBus *psSMBus, \ + tSMBusUDID *pUDID))ROM_SMBUSTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusStatusGet \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusSlaveDataSend \ + ((tSMBusStatus (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFOEnable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusFIFODisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMAEnable \ + ((void (*)(tSMBus *psSMBus, \ + uint8_t ui8TxChannel, \ + uint8_t ui8RxChannel))ROM_SMBUSTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SMBusDMADisable \ + ((void (*)(tSMBus *psSMBus))ROM_SMBUSTABLE[59]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SPIFlash API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashIntHandler \ + ((uint32_t (*)(tSPIFlashState *pState))ROM_SPIFLASHTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashInit \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Clock, \ + uint32_t ui32BitRate))ROM_SPIFLASHTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteStatus \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Status))ROM_SPIFLASHTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgram \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashPageProgramNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel))ROM_SPIFLASHTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteDisable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadStatus \ + ((uint8_t (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashWriteEnable \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashFastReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashSectorErase \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashDualReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase32 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadRead \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SPIFLASHTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashQuadReadNonBlocking \ + ((void (*)(tSPIFlashState *pState, \ + uint32_t ui32Base, \ + uint32_t ui32Addr, \ + uint8_t *pui8Data, \ + uint32_t ui32Count, \ + bool bUseDMA, \ + uint32_t ui32TxChannel, \ + uint32_t ui32RxChannel))ROM_SPIFLASHTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashReadID \ + ((void (*)(uint32_t ui32Base, \ + uint8_t *pui8ManufacturerID, \ + uint16_t *pui16DeviceID))ROM_SPIFLASHTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashChipErase \ + ((void (*)(uint32_t ui32Base))ROM_SPIFLASHTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SPIFlashBlockErase64 \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Addr))ROM_SPIFLASHTABLE[20]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SSI API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPut \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32SSIClk, \ + uint32_t ui32Protocol, \ + uint32_t ui32Mode, \ + uint32_t ui32BitRate, \ + uint32_t ui32DataWidth))ROM_SSITABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_SSITABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_SSITABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t *pui32Data))ROM_SSITABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateSSI \ + ((void (*)(void))ROM_SSITABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_SSITABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIBusy \ + ((bool (*)(uint32_t ui32Base))ROM_SSITABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_SSITABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_SSITABLE[16]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_SSITABLE[17]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEnd \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[18]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvDataPutFrameEndNonBlocking \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Data))ROM_SSITABLE[19]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldEnable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[20]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SSIAdvFrameHoldDisable \ + ((void (*)(uint32_t ui32Base))ROM_SSITABLE[21]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysCtl API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlSRAMSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPresent \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReset \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepEnable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralDeepSleepDisable \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralClockGating \ + ((void (*)(bool bEnable))ROM_SYSCTLTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntEnable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntDisable \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntClear \ + ((void (*)(uint32_t ui32Ints))ROM_SYSCTLTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSCTLTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlReset \ + ((void (*)(void))ROM_SYSCTLTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleep \ + ((void (*)(void))ROM_SYSCTLTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetCauseClear \ + ((void (*)(uint32_t ui32Causes))ROM_SYSCTLTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlPWMClockGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLEnable \ + ((void (*)(void))ROM_SYSCTLTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlUSBPLLDisable \ + ((void (*)(void))ROM_SYSCTLTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDelay \ + ((void (*)(uint32_t ui32Count))ROM_SYSCTLTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralReady \ + ((bool (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOn \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPeripheralPowerOff \ + ((void (*)(uint32_t ui32Peripheral))ROM_SYSCTLTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlMOSCConfigSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlPIOSCCalibrate \ + ((uint32_t (*)(uint32_t ui32Type))ROM_SYSCTLTABLE[45]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_SysCtlDeepSleepClockSet \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlDeepSleepClockConfigSet \ + ((void (*)(uint32_t ui32Div, \ + uint32_t ui32Config))ROM_SYSCTLTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorSet \ + ((void (*)(uint32_t ui32Behavior))ROM_SYSCTLTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlResetBehaviorGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlFlashSectorSizeGet \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlVoltageEventClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIStatus \ + ((uint32_t (*)(void))ROM_SYSCTLTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlNMIClear \ + ((void (*)(uint32_t ui32Status))ROM_SYSCTLTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlClockOutConfig \ + ((void (*)(uint32_t ui32Config, \ + uint32_t ui32Div))ROM_SYSCTLTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysCtlAltClkConfig \ + ((void (*)(uint32_t ui32Config))ROM_SYSCTLTABLE[61]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysExc API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntStatus \ + ((uint32_t (*)(bool bMasked))ROM_SYSEXCTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntClear \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntDisable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysExcIntEnable \ + ((void (*)(uint32_t ui32IntFlags))ROM_SYSEXCTABLE[3]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the SysTick API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickValueGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntEnable \ + ((void (*)(void))ROM_SYSTICKTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickIntDisable \ + ((void (*)(void))ROM_SYSTICKTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodSet \ + ((void (*)(uint32_t ui32Period))ROM_SYSTICKTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_SysTickPeriodGet \ + ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Timer API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerConfigure \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_TIMERTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlLevel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bInvert))ROM_TIMERTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA1) +#define ROM_TimerControlTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bEnable))ROM_TIMERTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlEvent \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Event))ROM_TIMERTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bStall))ROM_TIMERTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCEnable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerRTCDisable \ + ((void (*)(uint32_t ui32Base))ROM_TIMERTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerPrescaleMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerLoadGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerValueGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + uint32_t ui32Value))ROM_TIMERTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerMatchGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Timer))ROM_TIMERTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_TIMERTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_TIMERTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerControlWaitOnTrigger \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timer, \ + bool bWait))ROM_TIMERTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerLoadGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerValueGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchSet64 \ + ((void (*)(uint32_t ui32Base, \ + uint64_t ui64Value))ROM_TIMERTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) +#define ROM_TimerMatchGet64 \ + ((uint64_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_TIMERTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerADCEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ADCEvent))ROM_TIMERTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_TIMERTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerDMAEventSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAEvent))ROM_TIMERTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_TimerSynchronize \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Timers))ROM_TIMERTABLE[34]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the UART API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPut \ + ((void (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Parity))ROM_UARTTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTParityModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32TxLevel, \ + uint32_t ui32RxLevel))ROM_UARTTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t *pui32TxLevel, \ + uint32_t *pui32RxLevel))ROM_UARTTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigSetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t ui32Baud, \ + uint32_t ui32Config))ROM_UARTTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32UARTClk, \ + uint32_t *pui32Baud, \ + uint32_t *pui32Config))ROM_UARTTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTEnableSIR \ + ((void (*)(uint32_t ui32Base, \ + bool bLowPower))ROM_UARTTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDisableSIR \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharsAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSpaceAvail \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharGet \ + ((int32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTCharPutNonBlocking \ + ((bool (*)(uint32_t ui32Base, \ + unsigned char ucData))ROM_UARTTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBreakCtl \ + ((void (*)(uint32_t ui32Base, \ + bool bBreakState))ROM_UARTTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_UARTTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTIntClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_UARTTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUART \ + ((void (*)(void))ROM_UARTTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32DMAFlags))ROM_UARTTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFOEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFIFODisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTBusy \ + ((bool (*)(uint32_t ui32Base))ROM_UARTTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTTxIntModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTRxErrorClear \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Source))ROM_UARTTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTClockSourceGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr, \ + uint8_t ui8Mask))ROM_UARTTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UART9BitAddrSend \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Addr))ROM_UARTTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardDisable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTSmartCardEnable \ + ((void (*)(uint32_t ui32Base))ROM_UARTTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[39]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[40]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Control))ROM_UARTTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTModemStatusGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_UARTTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UARTFlowControlSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_UARTTABLE[44]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the uDMA API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelTransferSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Mode, \ + void *pvSrcAddr, \ + void *pvDstAddr, \ + uint32_t ui32TransferSize))ROM_UDMATABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAEnable \ + ((void (*)(void))ROM_UDMATABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMADisable \ + ((void (*)(void))ROM_UDMATABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusGet \ + ((uint32_t (*)(void))ROM_UDMATABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAErrorStatusClear \ + ((void (*)(void))ROM_UDMATABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelEnable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelDisable \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelIsEnabled \ + ((bool (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseSet \ + ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelRequest \ + ((void (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeEnable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeDisable \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32Attr))ROM_UDMATABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t (*)(uint32_t ui32ChannelNum))ROM_UDMATABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelControlSet \ + ((void (*)(uint32_t ui32ChannelStructIndex, \ + uint32_t ui32Control))ROM_UDMATABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelModeGet \ + ((uint32_t (*)(uint32_t ui32ChannelStructIndex))ROM_UDMATABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectSecondary \ + ((void (*)(uint32_t ui32SecPeriphs))ROM_UDMATABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelSelectDefault \ + ((void (*)(uint32_t ui32DefPeriphs))ROM_UDMATABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntStatus \ + ((uint32_t (*)(void))ROM_UDMATABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAIntClear \ + ((void (*)(uint32_t ui32ChanMask))ROM_UDMATABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAControlAlternateBaseGet \ + ((void * (*)(void))ROM_UDMATABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32ChannelNum, \ + uint32_t ui32TaskCount, \ + void *pvTaskList, \ + uint32_t ui32IsPeriphSG))ROM_UDMATABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_uDMAChannelAssign \ + ((void (*)(uint32_t ui32Mapping))ROM_UDMATABLE[23]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the USB API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address))ROM_USBTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevConnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevDisconnect \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32Flags))ROM_USBTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bIsLastPacket))ROM_USBTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStall \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStallClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataGet \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t *pui32Size))ROM_USBTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataPut \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint8_t *pui8Data, \ + uint32_t ui32Size))ROM_USBTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataSend \ + ((int32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32TransType))ROM_USBTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataToggleClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[15]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32FIFOAddress, \ + uint32_t *pui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[16]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32FIFOAddress, \ + uint32_t ui32FIFOSize, \ + uint32_t ui32Flags))ROM_USBTABLE[17]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFIFOFlush \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[18]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBFrameNumberGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[19]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[20]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[21]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32MaxPacketSize, \ + uint32_t ui32NAKPollInterval, \ + uint32_t ui32TargetEndpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[22]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataAck \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[23]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointDataToggle \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bDataToggle, \ + uint32_t ui32Flags))ROM_USBTABLE[24]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[25]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[26]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostHubAddrSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Addr, \ + uint32_t ui32Flags))ROM_USBTABLE[27]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[28]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[29]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Flags))ROM_USBTABLE[30]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[31]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostPwrFaultEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[32]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestIN \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[33]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestStatus \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[34]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostReset \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[35]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostResume \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[36]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[37]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostSuspend \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[38]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevEndpointConfigGet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t *pui32MaxPacketSize, \ + uint32_t *pui32Flags))ROM_USBTABLE[41]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[42]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMADisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[43]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDataAvail \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[44]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[46]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAChannel \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Channel))ROM_USBTABLE[47]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[48]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableControl \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[49]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusControl \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[50]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntDisableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[51]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntEnableEndpoint \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32IntFlags))ROM_USBTABLE[52]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBIntStatusEndpoint \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[53]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[54]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[55]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOff \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[56]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBPHYPowerOn \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[57]) +#endif +#if defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_UpdateUSB \ + ((void (*)(uint8_t *pui8DescriptorInfo))ROM_USBTABLE[58]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGMode \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[59]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostRequestINClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint))ROM_USBTABLE[60]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBNumEndpointsGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[61]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[62]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBClockEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Div, \ + uint32_t ui32Flags))ROM_USBTABLE[63]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBControllerVersion \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[64]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[65]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[66]) +#endif +#if defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[67]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevLPMRemoteWake \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[68]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDevSpeedGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[69]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressGet \ + ((void * (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[70]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelAddressSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + void *pvAddress))ROM_USBTABLE[71]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[72]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[73]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[74]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[75]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[76]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountGet \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[77]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Count, \ + uint32_t ui32Channel))ROM_USBTABLE[78]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[79]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + uint32_t ui32Channel))ROM_USBTABLE[80]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMAChannelStatusClear \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Channel, \ + uint32_t ui32Status))ROM_USBTABLE[81]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHighSpeed \ + ((void (*)(uint32_t ui32Base, \ + bool bEnable))ROM_USBTABLE[82]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointPing \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + bool bEnable))ROM_USBTABLE[83]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostEndpointSpeed \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Flags))ROM_USBTABLE[84]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32ResumeTime, \ + uint32_t ui32Config))ROM_USBTABLE[85]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMResume \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[86]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBHostLPMSend \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Address, \ + uint32_t uiEndpoint))ROM_USBTABLE[87]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntDisable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[88]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntEnable \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Ints))ROM_USBTABLE[89]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMIntStatus \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[90]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMLinkStateGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[91]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointPacketCountSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Count))ROM_USBTABLE[92]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Config))ROM_USBTABLE[93]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIDisable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[94]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIEnable \ + ((void (*)(uint32_t ui32Base))ROM_USBTABLE[95]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegRead \ + ((uint8_t (*)(uint32_t ui32Base, \ + uint8_t ui8Reg))ROM_USBTABLE[96]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBULPIRegWrite \ + ((void (*)(uint32_t ui32Base, \ + uint8_t ui8Reg, \ + uint8_t ui8Data))ROM_USBTABLE[97]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBOTGSessionRequest \ + ((void (*)(uint32_t ui32Base, \ + bool bStart))ROM_USBTABLE[98]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBDMANumChannels \ + ((uint32_t (*)(uint32_t ui32Base))ROM_USBTABLE[99]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBEndpointDMAConfigSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Endpoint, \ + uint32_t ui32Config))ROM_USBTABLE[100]) +#endif +#if defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBLPMRemoteWakeEnabled \ + ((bool (*)(uint32_t ui32Base))ROM_USBTABLE[102]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_USBModeConfig \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Mode))ROM_USBTABLE[103]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Watchdog API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntClear \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[0]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogRunning \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogResetDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[4]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogUnlock \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[6]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogLockState \ + ((bool (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[7]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32LoadVal))ROM_WATCHDOGTABLE[8]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogReloadGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[9]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogValueGet \ + ((uint32_t (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[10]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[11]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntStatus \ + ((uint32_t (*)(uint32_t ui32Base, \ + bool bMasked))ROM_WATCHDOGTABLE[12]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallEnable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[13]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogStallDisable \ + ((void (*)(uint32_t ui32Base))ROM_WATCHDOGTABLE[14]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_WatchdogIntTypeSet \ + ((void (*)(uint32_t ui32Base, \ + uint32_t ui32Type))ROM_WATCHDOGTABLE[15]) +#endif + +//***************************************************************************** +// +// Macros for calling ROM functions in the Software API. +// +//***************************************************************************** +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array \ + ((uint16_t (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data))ROM_SOFTWARETABLE[1]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16Array3 \ + ((void (*)(uint32_t ui32WordLen, \ + const uint32_t *pui32Data, \ + uint16_t *pui16Crc3))ROM_SOFTWARETABLE[2]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc16 \ + ((uint16_t (*)(uint16_t ui16Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[3]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc8CCITT \ + ((uint8_t (*)(uint8_t ui8Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[4]) +#endif +#if defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_Crc32 \ + ((uint32_t (*)(uint32_t ui32Crc, \ + const uint8_t *pui8Data, \ + uint32_t ui32Count))ROM_SOFTWARETABLE[5]) +#endif +#if defined(TARGET_IS_TM4C123_RA1) || \ + defined(TARGET_IS_TM4C123_RA3) || \ + defined(TARGET_IS_TM4C123_RB1) || \ + defined(TARGET_IS_TM4C123_RB2) || \ + defined(TARGET_IS_TM4C129_RA0) || \ + defined(TARGET_IS_TM4C129_RA1) || \ + defined(TARGET_IS_TM4C129_RA2) +#define ROM_pvAESTable \ + ((void *)&(ROM_SOFTWARETABLE[7])) +#endif + +#endif // __DRIVERLIB_ROM_H__ diff --git a/CCS/mm/src/inc/tivaware/ssi.h b/CCS/mm/src/inc/tivaware/ssi.h new file mode 100644 index 0000000..322e278 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/ssi.h @@ -0,0 +1,159 @@ +#include +#include +//***************************************************************************** +// +// ssi.h - Prototypes for the Synchronous Serial Interface Driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SSI_H__ +#define __DRIVERLIB_SSI_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear +// as the ui32IntFlags parameter, and returned by SSIIntStatus. +// +//***************************************************************************** +#define SSI_TXEOT 0x00000040 // Transmit FIFO is empty +#define SSI_DMATX 0x00000020 // DMA Transmit complete +#define SSI_DMARX 0x00000010 // DMA Receive complete +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun + +//***************************************************************************** +// +// Values that can be passed to SSIConfigSetExpClk. +// +//***************************************************************************** +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format + +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled + +//***************************************************************************** +// +// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). +// +//***************************************************************************** +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values that can be passed to SSIClockSourceSet() or returned from +// SSIClockSourceGet(). +// +//***************************************************************************** +#define SSI_CLOCK_SYSTEM 0x00000000 +#define SSI_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// Values that can be passed to SSIAdvModeSet(). +// +//***************************************************************************** +#define SSI_ADV_MODE_LEGACY 0x00000000 +#define SSI_ADV_MODE_READ_WRITE 0x000001c0 +#define SSI_ADV_MODE_WRITE 0x000000c0 +#define SSI_ADV_MODE_BI_READ 0x00000140 +#define SSI_ADV_MODE_BI_WRITE 0x00000040 +#define SSI_ADV_MODE_QUAD_READ 0x00000180 +#define SSI_ADV_MODE_QUAD_WRITE 0x00000080 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, + uint32_t ui32Protocol, uint32_t ui32Mode, + uint32_t ui32BitRate, + uint32_t ui32DataWidth); +extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); +extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, + uint32_t *pui32Data); +extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); +extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); +extern void SSIDisable(uint32_t ui32Base); +extern void SSIEnable(uint32_t ui32Base); +extern void SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern uint32_t SSIIntStatus(uint32_t ui32Base, bool bMasked); +extern void SSIIntUnregister(uint32_t ui32Base); +extern void SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern bool SSIBusy(uint32_t ui32Base); +extern void SSIClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t SSIClockSourceGet(uint32_t ui32Base); +extern void SSIAdvModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern void SSIAdvDataPutFrameEnd(uint32_t ui32Base, uint32_t ui32Data); +extern int32_t SSIAdvDataPutFrameEndNonBlocking(uint32_t ui32Base, + uint32_t ui32Data); +extern void SSIAdvFrameHoldEnable(uint32_t ui32Base); +extern void SSIAdvFrameHoldDisable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SSI_H__ diff --git a/CCS/mm/src/inc/tivaware/sysctl.h b/CCS/mm/src/inc/tivaware/sysctl.h new file mode 100644 index 0000000..33b1072 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/sysctl.h @@ -0,0 +1,661 @@ +#include +#include +//***************************************************************************** +// +// sysctl.h - Prototypes for the system control driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSCTL_H__ +#define __DRIVERLIB_SYSCTL_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +#include + +//***************************************************************************** +// +// The following are values that can be passed to the +// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), +// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the +// ui32Peripheral parameter. The peripherals in the fourth group (upper nibble +// is 3) can only be used with the SysCtlPeripheralPresent() API. +// +//***************************************************************************** +#define SYSCTL_PERIPH_ADC0 0xf0003800 // ADC 0 +#define SYSCTL_PERIPH_ADC1 0xf0003801 // ADC 1 +#define SYSCTL_PERIPH_CAN0 0xf0003400 // CAN 0 +#define SYSCTL_PERIPH_CAN1 0xf0003401 // CAN 1 +#define SYSCTL_PERIPH_COMP0 0xf0003c00 // Analog Comparator Module 0 +#define SYSCTL_PERIPH_EMAC0 0xf0009c00 // Ethernet MAC0 +#define SYSCTL_PERIPH_EPHY0 0xf0003000 // Ethernet PHY0 +#define SYSCTL_PERIPH_EPI0 0xf0001000 // EPI0 +#define SYSCTL_PERIPH_GPIOA 0xf0000800 // GPIO A +#define SYSCTL_PERIPH_GPIOB 0xf0000801 // GPIO B +#define SYSCTL_PERIPH_GPIOC 0xf0000802 // GPIO C +#define SYSCTL_PERIPH_GPIOD 0xf0000803 // GPIO D +#define SYSCTL_PERIPH_GPIOE 0xf0000804 // GPIO E +#define SYSCTL_PERIPH_GPIOF 0xf0000805 // GPIO F +#define SYSCTL_PERIPH_GPIOG 0xf0000806 // GPIO G +#define SYSCTL_PERIPH_GPIOH 0xf0000807 // GPIO H +#define SYSCTL_PERIPH_GPIOJ 0xf0000808 // GPIO J +#define SYSCTL_PERIPH_HIBERNATE 0xf0001400 // Hibernation module +#define SYSCTL_PERIPH_CCM0 0xf0007400 // CCM 0 +#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0 +#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0 +#define SYSCTL_PERIPH_FAN1 0xf0005401 // FAN 1 +#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K +#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L +#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M +#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N +#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P +#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q +#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R +#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S +#define SYSCTL_PERIPH_GPIOT 0xf0000811 // GPIO T +#define SYSCTL_PERIPH_I2C0 0xf0002000 // I2C 0 +#define SYSCTL_PERIPH_I2C1 0xf0002001 // I2C 1 +#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2 +#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3 +#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4 +#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5 +#define SYSCTL_PERIPH_I2C6 0xf0002006 // I2C 6 +#define SYSCTL_PERIPH_I2C7 0xf0002007 // I2C 7 +#define SYSCTL_PERIPH_I2C8 0xf0002008 // I2C 8 +#define SYSCTL_PERIPH_I2C9 0xf0002009 // I2C 9 +#define SYSCTL_PERIPH_LCD0 0xf0009000 // LCD 0 +#define SYSCTL_PERIPH_ONEWIRE0 0xf0009800 // One Wire 0 +#define SYSCTL_PERIPH_PWM0 0xf0004000 // PWM 0 +#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1 +#define SYSCTL_PERIPH_QEI0 0xf0004400 // QEI 0 +#define SYSCTL_PERIPH_QEI1 0xf0004401 // QEI 1 +#define SYSCTL_PERIPH_SSI0 0xf0001c00 // SSI 0 +#define SYSCTL_PERIPH_SSI1 0xf0001c01 // SSI 1 +#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2 +#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3 +#define SYSCTL_PERIPH_TIMER0 0xf0000400 // Timer 0 +#define SYSCTL_PERIPH_TIMER1 0xf0000401 // Timer 1 +#define SYSCTL_PERIPH_TIMER2 0xf0000402 // Timer 2 +#define SYSCTL_PERIPH_TIMER3 0xf0000403 // Timer 3 +#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4 +#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5 +#define SYSCTL_PERIPH_TIMER6 0xf0000406 // Timer 6 +#define SYSCTL_PERIPH_TIMER7 0xf0000407 // Timer 7 +#define SYSCTL_PERIPH_UART0 0xf0001800 // UART 0 +#define SYSCTL_PERIPH_UART1 0xf0001801 // UART 1 +#define SYSCTL_PERIPH_UART2 0xf0001802 // UART 2 +#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3 +#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4 +#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5 +#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6 +#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7 +#define SYSCTL_PERIPH_UDMA 0xf0000c00 // uDMA +#define SYSCTL_PERIPH_USB0 0xf0002800 // USB 0 +#define SYSCTL_PERIPH_WDOG0 0xf0000000 // Watchdog 0 +#define SYSCTL_PERIPH_WDOG1 0xf0000001 // Watchdog 1 +#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0 +#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1 +#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2 +#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3 +#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4 +#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlLDOSleepSet() and +// SysCtlLDODeepSleepSet() APIs as the ui32Voltage value, or returned by the +// SysCtlLDOSleepGet() and SysCtlLDODeepSleepGet() APIs. +// +//***************************************************************************** +#define SYSCTL_LDO_0_90V 0x80000012 // LDO output of 0.90V +#define SYSCTL_LDO_0_95V 0x80000013 // LDO output of 0.95V +#define SYSCTL_LDO_1_00V 0x80000014 // LDO output of 1.00V +#define SYSCTL_LDO_1_05V 0x80000015 // LDO output of 1.05V +#define SYSCTL_LDO_1_10V 0x80000016 // LDO output of 1.10V +#define SYSCTL_LDO_1_15V 0x80000017 // LDO output of 1.15V +#define SYSCTL_LDO_1_20V 0x80000018 // LDO output of 1.20V + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlIntEnable(), +// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask +// by the SysCtlIntStatus() API. +// +//***************************************************************************** +#define SYSCTL_INT_BOR0 0x00000800 // VDD under BOR0 +#define SYSCTL_INT_VDDA_OK 0x00000400 // VDDA Power OK +#define SYSCTL_INT_MOSC_PUP 0x00000100 // MOSC power-up interrupt +#define SYSCTL_INT_USBPLL_LOCK 0x00000080 // USB PLL lock interrupt +#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt +#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int +#define SYSCTL_INT_BOR1 0x00000002 // VDD under BOR1 +#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlResetCauseClear() +// API or returned by the SysCtlResetCauseGet() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_HSRVREQ 0x00001000 // Hardware System Service Request +#define SYSCTL_CAUSE_HIB 0x00000040 // Hibernate reset +#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog 1 reset +#define SYSCTL_CAUSE_SW 0x00000010 // Software reset +#define SYSCTL_CAUSE_WDOG0 0x00000008 // Watchdog 0 reset +#ifndef DEPRECATED +#define SYSCTL_CAUSE_WDOG SYSCTL_CAUSE_WDOG0 + // Watchdog reset(Deprecated) +#endif +#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset +#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset +#define SYSCTL_CAUSE_EXT 0x00000001 // External reset + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlBrownOutConfigSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting +#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPWMClockSet() API +// as the ui32Config parameter, and can be returned by the SysCtlPWMClockGet() +// API. +// +//***************************************************************************** +#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 +#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 +#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 +#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 +#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 +#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 +#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlClockSet() API as +// the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 +#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 +#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 +#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 +#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 +#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 +#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 +#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 +#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 +#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 +#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 +#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 +#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 +#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 +#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 +#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 +#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 +#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 +#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 +#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 +#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 +#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 +#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 +#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 +#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 +#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 +#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 +#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 +#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 +#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 +#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 +#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 +#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 +#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 +#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 +#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 +#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 +#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 +#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 +#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 +#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 +#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 +#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 +#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 +#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 +#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 +#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 +#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 +#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 +#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 +#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 +#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 +#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 +#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 +#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 +#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 +#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 +#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 +#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 +#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 +#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 +#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 +#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 +#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 +#define SYSCTL_SYSDIV_2_5 0xC1000000 // Processor clock is pll / 2.5 +#define SYSCTL_SYSDIV_3_5 0xC1800000 // Processor clock is pll / 3.5 +#define SYSCTL_SYSDIV_4_5 0xC2000000 // Processor clock is pll / 4.5 +#define SYSCTL_SYSDIV_5_5 0xC2800000 // Processor clock is pll / 5.5 +#define SYSCTL_SYSDIV_6_5 0xC3000000 // Processor clock is pll / 6.5 +#define SYSCTL_SYSDIV_7_5 0xC3800000 // Processor clock is pll / 7.5 +#define SYSCTL_SYSDIV_8_5 0xC4000000 // Processor clock is pll / 8.5 +#define SYSCTL_SYSDIV_9_5 0xC4800000 // Processor clock is pll / 9.5 +#define SYSCTL_SYSDIV_10_5 0xC5000000 // Processor clock is pll / 10.5 +#define SYSCTL_SYSDIV_11_5 0xC5800000 // Processor clock is pll / 11.5 +#define SYSCTL_SYSDIV_12_5 0xC6000000 // Processor clock is pll / 12.5 +#define SYSCTL_SYSDIV_13_5 0xC6800000 // Processor clock is pll / 13.5 +#define SYSCTL_SYSDIV_14_5 0xC7000000 // Processor clock is pll / 14.5 +#define SYSCTL_SYSDIV_15_5 0xC7800000 // Processor clock is pll / 15.5 +#define SYSCTL_SYSDIV_16_5 0xC8000000 // Processor clock is pll / 16.5 +#define SYSCTL_SYSDIV_17_5 0xC8800000 // Processor clock is pll / 17.5 +#define SYSCTL_SYSDIV_18_5 0xC9000000 // Processor clock is pll / 18.5 +#define SYSCTL_SYSDIV_19_5 0xC9800000 // Processor clock is pll / 19.5 +#define SYSCTL_SYSDIV_20_5 0xCA000000 // Processor clock is pll / 20.5 +#define SYSCTL_SYSDIV_21_5 0xCA800000 // Processor clock is pll / 21.5 +#define SYSCTL_SYSDIV_22_5 0xCB000000 // Processor clock is pll / 22.5 +#define SYSCTL_SYSDIV_23_5 0xCB800000 // Processor clock is pll / 23.5 +#define SYSCTL_SYSDIV_24_5 0xCC000000 // Processor clock is pll / 24.5 +#define SYSCTL_SYSDIV_25_5 0xCC800000 // Processor clock is pll / 25.5 +#define SYSCTL_SYSDIV_26_5 0xCD000000 // Processor clock is pll / 26.5 +#define SYSCTL_SYSDIV_27_5 0xCD800000 // Processor clock is pll / 27.5 +#define SYSCTL_SYSDIV_28_5 0xCE000000 // Processor clock is pll / 28.5 +#define SYSCTL_SYSDIV_29_5 0xCE800000 // Processor clock is pll / 29.5 +#define SYSCTL_SYSDIV_30_5 0xCF000000 // Processor clock is pll / 30.5 +#define SYSCTL_SYSDIV_31_5 0xCF800000 // Processor clock is pll / 31.5 +#define SYSCTL_SYSDIV_32_5 0xD0000000 // Processor clock is pll / 32.5 +#define SYSCTL_SYSDIV_33_5 0xD0800000 // Processor clock is pll / 33.5 +#define SYSCTL_SYSDIV_34_5 0xD1000000 // Processor clock is pll / 34.5 +#define SYSCTL_SYSDIV_35_5 0xD1800000 // Processor clock is pll / 35.5 +#define SYSCTL_SYSDIV_36_5 0xD2000000 // Processor clock is pll / 36.5 +#define SYSCTL_SYSDIV_37_5 0xD2800000 // Processor clock is pll / 37.5 +#define SYSCTL_SYSDIV_38_5 0xD3000000 // Processor clock is pll / 38.5 +#define SYSCTL_SYSDIV_39_5 0xD3800000 // Processor clock is pll / 39.5 +#define SYSCTL_SYSDIV_40_5 0xD4000000 // Processor clock is pll / 40.5 +#define SYSCTL_SYSDIV_41_5 0xD4800000 // Processor clock is pll / 41.5 +#define SYSCTL_SYSDIV_42_5 0xD5000000 // Processor clock is pll / 42.5 +#define SYSCTL_SYSDIV_43_5 0xD5800000 // Processor clock is pll / 43.5 +#define SYSCTL_SYSDIV_44_5 0xD6000000 // Processor clock is pll / 44.5 +#define SYSCTL_SYSDIV_45_5 0xD6800000 // Processor clock is pll / 45.5 +#define SYSCTL_SYSDIV_46_5 0xD7000000 // Processor clock is pll / 46.5 +#define SYSCTL_SYSDIV_47_5 0xD7800000 // Processor clock is pll / 47.5 +#define SYSCTL_SYSDIV_48_5 0xD8000000 // Processor clock is pll / 48.5 +#define SYSCTL_SYSDIV_49_5 0xD8800000 // Processor clock is pll / 49.5 +#define SYSCTL_SYSDIV_50_5 0xD9000000 // Processor clock is pll / 50.5 +#define SYSCTL_SYSDIV_51_5 0xD9800000 // Processor clock is pll / 51.5 +#define SYSCTL_SYSDIV_52_5 0xDA000000 // Processor clock is pll / 52.5 +#define SYSCTL_SYSDIV_53_5 0xDA800000 // Processor clock is pll / 53.5 +#define SYSCTL_SYSDIV_54_5 0xDB000000 // Processor clock is pll / 54.5 +#define SYSCTL_SYSDIV_55_5 0xDB800000 // Processor clock is pll / 55.5 +#define SYSCTL_SYSDIV_56_5 0xDC000000 // Processor clock is pll / 56.5 +#define SYSCTL_SYSDIV_57_5 0xDC800000 // Processor clock is pll / 57.5 +#define SYSCTL_SYSDIV_58_5 0xDD000000 // Processor clock is pll / 58.5 +#define SYSCTL_SYSDIV_59_5 0xDD800000 // Processor clock is pll / 59.5 +#define SYSCTL_SYSDIV_60_5 0xDE000000 // Processor clock is pll / 60.5 +#define SYSCTL_SYSDIV_61_5 0xDE800000 // Processor clock is pll / 61.5 +#define SYSCTL_SYSDIV_62_5 0xDF000000 // Processor clock is pll / 62.5 +#define SYSCTL_SYSDIV_63_5 0xDF800000 // Processor clock is pll / 63.5 +#define SYSCTL_CFG_VCO_480 0xF1000000 // VCO is 480 MHz +#define SYSCTL_CFG_VCO_320 0xF0000000 // VCO is 320 MHz +#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock +#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock +#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz +#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz +#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz +#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz +#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz +#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz +#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz +#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz +#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz +#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz +#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz +#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz +#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz +#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz +#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz +#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz +#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz +#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz +#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz +#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz +#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz +#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz +#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz +#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz +#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz +#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz +#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz +#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4 +#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz +#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator +#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlDeepSleepClockSet() +// API as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1 +#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2 +#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3 +#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4 +#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5 +#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6 +#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7 +#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8 +#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9 +#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10 +#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11 +#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12 +#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13 +#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14 +#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15 +#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16 +#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17 +#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18 +#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19 +#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20 +#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21 +#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22 +#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23 +#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24 +#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25 +#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26 +#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27 +#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28 +#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29 +#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30 +#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31 +#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32 +#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33 +#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34 +#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35 +#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36 +#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37 +#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38 +#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39 +#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40 +#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41 +#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42 +#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43 +#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44 +#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45 +#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46 +#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47 +#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48 +#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49 +#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50 +#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51 +#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52 +#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53 +#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54 +#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55 +#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56 +#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57 +#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58 +#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59 +#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60 +#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61 +#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62 +#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63 +#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64 +#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc +#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc +#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz +#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz +#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep +#define SYSCTL_DSLP_MOSC_PD 0x40000000 // Power down MOSC in deep-sleep + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlPIOSCCalibrate() +// API as the ui32Type parameter. +// +//***************************************************************************** +#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration +#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration +#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlMOSCConfigSet() API +// as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation +#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail +#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC +#define SYSCTL_MOSC_PWR_DIS 0x00000008 // Power down the MOSC. +#define SYSCTL_MOSC_LOWFREQ 0x00000000 // MOSC is less than 10MHz +#define SYSCTL_MOSC_HIGHFREQ 0x00000010 // MOSC is greater than 10MHz +#define SYSCTL_MOSC_SESRC 0x00000020 // Singled ended oscillator source. + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtlSleepPowerSet() and +// SysCtlDeepSleepPowerSet() APIs as the ui32Config parameter. +// +//***************************************************************************** +#define SYSCTL_LDO_SLEEP 0x00000200 // LDO in sleep mode + // (Deep Sleep Only) +#define SYSCTL_TEMP_LOW_POWER 0x00000100 // Temp sensor in low power mode + // (Deep Sleep Only) +#define SYSCTL_FLASH_NORMAL 0x00000000 // Flash in normal mode +#define SYSCTL_FLASH_LOW_POWER 0x00000020 // Flash in low power mode +#define SYSCTL_SRAM_NORMAL 0x00000000 // SRAM in normal mode +#define SYSCTL_SRAM_STANDBY 0x00000001 // SRAM in standby mode +#define SYSCTL_SRAM_LOW_POWER 0x00000003 // SRAM in low power mode + +//***************************************************************************** +// +// Defines for the SysCtlResetBehaviorSet() and SysCtlResetBehaviorGet() APIs. +// +//***************************************************************************** +#define SYSCTL_ONRST_WDOG0_POR 0x00000030 +#define SYSCTL_ONRST_WDOG0_SYS 0x00000020 +#define SYSCTL_ONRST_WDOG1_POR 0x000000C0 +#define SYSCTL_ONRST_WDOG1_SYS 0x00000080 +#define SYSCTL_ONRST_BOR_POR 0x0000000C +#define SYSCTL_ONRST_BOR_SYS 0x00000008 +#define SYSCTL_ONRST_EXT_POR 0x00000003 +#define SYSCTL_ONRST_EXT_SYS 0x00000002 + +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventConfig() API. +// +//***************************************************************************** +#define SYSCTL_VEVENT_VDDABO_NONE \ + 0x00000000 +#define SYSCTL_VEVENT_VDDABO_INT \ + 0x00000100 +#define SYSCTL_VEVENT_VDDABO_NMI \ + 0x00000200 +#define SYSCTL_VEVENT_VDDABO_RST \ + 0x00000300 +#define SYSCTL_VEVENT_VDDBO_NONE \ + 0x00000000 +#define SYSCTL_VEVENT_VDDBO_INT 0x00000001 +#define SYSCTL_VEVENT_VDDBO_NMI 0x00000002 +#define SYSCTL_VEVENT_VDDBO_RST 0x00000003 + +//***************************************************************************** +// +// Values used with the SysCtlVoltageEventStatus() and +// SysCtlVoltageEventClear() APIs. +// +//***************************************************************************** +#define SYSCTL_VESTAT_VDDBOR 0x00000040 +#define SYSCTL_VESTAT_VDDABOR 0x00000010 + +//***************************************************************************** +// +// Values used with the SysCtlNMIStatus() API. +// +//***************************************************************************** +#define SYSCTL_NMI_MOSCFAIL 0x00010000 +#define SYSCTL_NMI_TAMPER 0x00000200 +#define SYSCTL_NMI_WDT1 0x00000020 +#define SYSCTL_NMI_WDT0 0x00000008 +#define SYSCTL_NMI_POWER 0x00000004 +#define SYSCTL_NMI_EXTERNAL 0x00000001 + +//***************************************************************************** +// +// The defines for the SysCtlClockOutConfig() API. +// +//***************************************************************************** +#define SYSCTL_CLKOUT_EN 0x80000000 +#define SYSCTL_CLKOUT_DIS 0x00000000 +#define SYSCTL_CLKOUT_SYSCLK 0x00000000 +#define SYSCTL_CLKOUT_PIOSC 0x00010000 +#define SYSCTL_CLKOUT_MOSC 0x00020000 + +//***************************************************************************** +// +// The following defines are used with the SysCtlAltClkConfig() function. +// +//***************************************************************************** +#define SYSCTL_ALTCLK_PIOSC 0x00000000 +#define SYSCTL_ALTCLK_RTCOSC 0x00000003 +#define SYSCTL_ALTCLK_LFIOSC 0x00000004 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t SysCtlSRAMSizeGet(void); +extern uint32_t SysCtlFlashSizeGet(void); +extern uint32_t SysCtlFlashSectorSizeGet(void); +extern bool SysCtlPeripheralPresent(uint32_t ui32Peripheral); +extern bool SysCtlPeripheralReady(uint32_t ui32Peripheral); +extern void SysCtlPeripheralPowerOn(uint32_t ui32Peripheral); +extern void SysCtlPeripheralPowerOff(uint32_t ui32Peripheral); +extern void SysCtlPeripheralReset(uint32_t ui32Peripheral); +extern void SysCtlPeripheralEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralSleepEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralSleepDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDeepSleepEnable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralDeepSleepDisable(uint32_t ui32Peripheral); +extern void SysCtlPeripheralClockGating(bool bEnable); +extern void SysCtlIntRegister(void (*pfnHandler)(void)); +extern void SysCtlIntUnregister(void); +extern void SysCtlIntEnable(uint32_t ui32Ints); +extern void SysCtlIntDisable(uint32_t ui32Ints); +extern void SysCtlIntClear(uint32_t ui32Ints); +extern uint32_t SysCtlIntStatus(bool bMasked); +extern void SysCtlLDOSleepSet(uint32_t ui32Voltage); +extern uint32_t SysCtlLDOSleepGet(void); +extern void SysCtlLDODeepSleepSet(uint32_t ui32Voltage); +extern uint32_t SysCtlLDODeepSleepGet(void); +extern void SysCtlSleepPowerSet(uint32_t ui32Config); +extern void SysCtlDeepSleepPowerSet(uint32_t ui32Config); +extern void SysCtlReset(void); +extern void SysCtlSleep(void); +extern void SysCtlDeepSleep(void); +extern uint32_t SysCtlResetCauseGet(void); +extern void SysCtlResetCauseClear(uint32_t ui32Causes); +extern void SysCtlBrownOutConfigSet(uint32_t ui32Config, + uint32_t ui32Delay); +extern void SysCtlDelay(uint32_t ui32Count); +extern void SysCtlMOSCConfigSet(uint32_t ui32Config); +extern uint32_t SysCtlPIOSCCalibrate(uint32_t ui32Type); +extern void SysCtlClockSet(uint32_t ui32Config); +extern uint32_t SysCtlClockGet(void); +extern void SysCtlDeepSleepClockSet(uint32_t ui32Config); +extern void SysCtlDeepSleepClockConfigSet(uint32_t ui32Div, + uint32_t ui32Config); +extern void SysCtlPWMClockSet(uint32_t ui32Config); +extern uint32_t SysCtlPWMClockGet(void); +extern void SysCtlIOSCVerificationSet(bool bEnable); +extern void SysCtlMOSCVerificationSet(bool bEnable); +extern void SysCtlPLLVerificationSet(bool bEnable); +extern void SysCtlClkVerificationClear(void); +extern void SysCtlGPIOAHBEnable(uint32_t ui32GPIOPeripheral); +extern void SysCtlGPIOAHBDisable(uint32_t ui32GPIOPeripheral); +extern void SysCtlUSBPLLEnable(void); +extern void SysCtlUSBPLLDisable(void); +extern uint32_t SysCtlClockFreqSet(uint32_t ui32Config, + uint32_t ui32SysClock); +extern void SysCtlResetBehaviorSet(uint32_t ui32Behavior); +extern uint32_t SysCtlResetBehaviorGet(void); +extern void SysCtlClockOutConfig(uint32_t ui32Config, uint32_t ui32Div); +extern void SysCtlAltClkConfig(uint32_t ui32Config); +extern uint32_t SysCtlNMIStatus(void); +extern void SysCtlNMIClear(uint32_t ui32Status); +extern void SysCtlVoltageEventConfig(uint32_t ui32Config); +extern uint32_t SysCtlVoltageEventStatus(void); +extern void SysCtlVoltageEventClear(uint32_t ui32Status); +extern bool SysCtlVCOGet(uint32_t ui32Crystal, uint32_t *pui32VCOFrequency); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSCTL_H__ diff --git a/CCS/mm/src/inc/tivaware/systick.h b/CCS/mm/src/inc/tivaware/systick.h new file mode 100644 index 0000000..c261b80 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/systick.h @@ -0,0 +1,82 @@ +#include +#include +//***************************************************************************** +// +// systick.h - Prototypes for the SysTick driver. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_SYSTICK_H__ +#define __DRIVERLIB_SYSTICK_H__ + +#include + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(uint32_t ui32Period); +extern uint32_t SysTickPeriodGet(void); +extern uint32_t SysTickValueGet(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_SYSTICK_H__ diff --git a/CCS/mm/src/inc/tivaware/timer.h b/CCS/mm/src/inc/tivaware/timer.h new file mode 100644 index 0000000..b8f9d2e --- /dev/null +++ b/CCS/mm/src/inc/tivaware/timer.h @@ -0,0 +1,303 @@ +#include +#include +//***************************************************************************** +// +// timer.h - Prototypes for the timer module +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_TIMER_H__ +#define __DRIVERLIB_TIMER_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to TimerConfigure as the ui32Config parameter. +// +//***************************************************************************** +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count + // timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count + // timer +#define TIMER_CFG_RTC 0x01000000 // Full-width RTC timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_A_ACT_TOINTD 0x00010000 // Timer A compare action disable + // time-out interrupt. +#define TIMER_CFG_A_ACT_NONE 0x00000000 // Timer A compare action none. +#define TIMER_CFG_A_ACT_TOGGLE 0x00020000 // Timer A compare action toggle. +#define TIMER_CFG_A_ACT_CLRTO 0x00040000 // Timer A compare action CCP + // clear on time-out. +#define TIMER_CFG_A_ACT_SETTO 0x00060000 // Timer A compare action CCP set + // on time-out. +#define TIMER_CFG_A_ACT_SETTOGTO 0x00080000 // Timer A compare action set CCP + // toggle on time-out. +#define TIMER_CFG_A_ACT_CLRTOGTO 0x000A0000 // Timer A compare action clear + // CCP toggle on time-out. +#define TIMER_CFG_A_ACT_SETCLRTO 0x000C0000 // Timer A compare action set CCP + // clear on time-out. +#define TIMER_CFG_A_ACT_CLRSETTO 0x000E0000 // Timer A compare action clear + // CCP set on time-out. +#define TIMER_CFG_B_ACT_TOINTD 0x00100000 // Timer B compare action disable + // time-out interrupt. +#define TIMER_CFG_B_ACT_NONE 0x00000000 // Timer A compare action none. +#define TIMER_CFG_B_ACT_TOGGLE 0x00200000 // Timer A compare action toggle. +#define TIMER_CFG_B_ACT_CLRTO 0x00400000 // Timer A compare action CCP + // clear on time-out. +#define TIMER_CFG_B_ACT_SETTO 0x00600000 // Timer A compare action CCP set + // on time-out. +#define TIMER_CFG_B_ACT_SETTOGTO 0x00800000 // Timer A compare action set CCP + // toggle on time-out. +#define TIMER_CFG_B_ACT_CLRTOGTO 0x00A00000 // Timer A compare action clear + // CCP toggle on time-out. +#define TIMER_CFG_B_ACT_SETCLRTO 0x00C00000 // Timer A compare action set CCP + // clear on time-out. +#define TIMER_CFG_B_ACT_CLRSETTO 0x0000E000 // Timer A compare action clear + // CCP set on time-out. + +//***************************************************************************** +// +// Values that can be passed to TimerIntEnable, TimerIntDisable, and +// TimerIntClear as the ui32IntFlags parameter, and returned from +// TimerIntStatus. +// +//***************************************************************************** +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Complete Interrupt. +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Complete Interrupt. +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt + +//***************************************************************************** +// +// Values that can be passed to TimerControlEvent as the ui32Event parameter. +// +//***************************************************************************** +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges + +//***************************************************************************** +// +// Values that can be passed to most of the timer APIs as the ui32Timer +// parameter. +// +//***************************************************************************** +#define TIMER_A 0x000000ff // Timer A +#define TIMER_B 0x0000ff00 // Timer B +#define TIMER_BOTH 0x0000ffff // Timer Both + +//***************************************************************************** +// +// Values that can be passed to TimerSynchronize as the ui32Timers parameter. +// +//***************************************************************************** +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_4A_SYNC 0x00000100 // Synchronize Timer 4A +#define TIMER_4B_SYNC 0x00000200 // Synchronize Timer 4B +#define TIMER_5A_SYNC 0x00000400 // Synchronize Timer 5A +#define TIMER_5B_SYNC 0x00000800 // Synchronize Timer 5B +#define WTIMER_0A_SYNC 0x00001000 // Synchronize Wide Timer 0A +#define WTIMER_0B_SYNC 0x00002000 // Synchronize Wide Timer 0B +#define WTIMER_1A_SYNC 0x00004000 // Synchronize Wide Timer 1A +#define WTIMER_1B_SYNC 0x00008000 // Synchronize Wide Timer 1B +#define WTIMER_2A_SYNC 0x00010000 // Synchronize Wide Timer 2A +#define WTIMER_2B_SYNC 0x00020000 // Synchronize Wide Timer 2B +#define WTIMER_3A_SYNC 0x00040000 // Synchronize Wide Timer 3A +#define WTIMER_3B_SYNC 0x00080000 // Synchronize Wide Timer 3B +#define WTIMER_4A_SYNC 0x00100000 // Synchronize Wide Timer 4A +#define WTIMER_4B_SYNC 0x00200000 // Synchronize Wide Timer 4B +#define WTIMER_5A_SYNC 0x00400000 // Synchronize Wide Timer 5A +#define WTIMER_5B_SYNC 0x00800000 // Synchronize Wide Timer 5B + +//***************************************************************************** +// +// Values that can be passed to TimerClockSourceSet() or returned from +// TimerClockSourceGet(). +// +//***************************************************************************** +#define TIMER_CLOCK_SYSTEM 0x00000000 +#define TIMER_CLOCK_PIOSC 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerDMAEventSet() or returned from +// TimerDMAEventGet(). +// +//***************************************************************************** +#define TIMER_DMA_MODEMATCH_B 0x00000800 +#define TIMER_DMA_CAPEVENT_B 0x00000400 +#define TIMER_DMA_CAPMATCH_B 0x00000200 +#define TIMER_DMA_TIMEOUT_B 0x00000100 +#define TIMER_DMA_MODEMATCH_A 0x00000010 +#define TIMER_DMA_RTC_A 0x00000008 +#define TIMER_DMA_CAPEVENT_A 0x00000004 +#define TIMER_DMA_CAPMATCH_A 0x00000002 +#define TIMER_DMA_TIMEOUT_A 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerADCEventSet() or returned from +// TimerADCEventGet(). +// +//***************************************************************************** +#define TIMER_ADC_MODEMATCH_B 0x00000800 +#define TIMER_ADC_CAPEVENT_B 0x00000400 +#define TIMER_ADC_CAPMATCH_B 0x00000200 +#define TIMER_ADC_TIMEOUT_B 0x00000100 +#define TIMER_ADC_MODEMATCH_A 0x00000010 +#define TIMER_ADC_RTC_A 0x00000008 +#define TIMER_ADC_CAPEVENT_A 0x00000004 +#define TIMER_ADC_CAPMATCH_A 0x00000002 +#define TIMER_ADC_TIMEOUT_A 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to TimerUpdateMode(). +// +//***************************************************************************** +#define TIMER_UP_LOAD_IMMEDIATE 0x00000000 +#define TIMER_UP_LOAD_TIMEOUT 0x00000100 +#define TIMER_UP_MATCH_IMMEDIATE \ + 0x00000000 +#define TIMER_UP_MATCH_TIMEOUT 0x00000400 + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern void TimerEnable(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerDisable(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); +extern void TimerControlLevel(uint32_t ui32Base, uint32_t ui32Timer, + bool bInvert); +extern void TimerControlTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bEnable); +extern void TimerControlEvent(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Event); +extern void TimerControlStall(uint32_t ui32Base, uint32_t ui32Timer, + bool bStall); +extern void TimerControlWaitOnTrigger(uint32_t ui32Base, uint32_t ui32Timer, + bool bWait); +extern void TimerRTCEnable(uint32_t ui32Base); +extern void TimerRTCDisable(uint32_t ui32Base); +extern void TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerLoadSet64(uint32_t ui32Base, uint64_t ui64Value); +extern uint64_t TimerLoadGet64(uint32_t ui32Base); +extern uint32_t TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer); +extern uint64_t TimerValueGet64(uint32_t ui32Base); +extern void TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Value); +extern uint32_t TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerMatchSet64(uint32_t ui32Base, uint64_t ui64Value); +extern uint64_t TimerMatchGet64(uint32_t ui32Base); +extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, + void (*pfnHandler)(void)); +extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); +extern void TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t TimerIntStatus(uint32_t ui32Base, bool bMasked); +extern void TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers); +extern uint32_t TimerClockSourceGet(uint32_t ui32Base); +extern void TimerClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t TimerADCEventGet(uint32_t ui32Base); +extern void TimerADCEventSet(uint32_t ui32Base, uint32_t ui32ADCEvent); +extern uint32_t TimerDMAEventGet(uint32_t ui32Base); +extern void TimerDMAEventSet(uint32_t ui32Base, uint32_t ui32DMAEvent); +extern void TimerUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, + uint32_t ui32Config); +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_TIMER_H__ diff --git a/CCS/mm/src/inc/tivaware/uart.h b/CCS/mm/src/inc/tivaware/uart.h new file mode 100644 index 0000000..ea3fb44 --- /dev/null +++ b/CCS/mm/src/inc/tivaware/uart.h @@ -0,0 +1,258 @@ +#include +#include +//***************************************************************************** +// +// uart.h - Defines and Macros for the UART. +// +// Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved. +// Software License Agreement +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// This is part of revision 2.1.4.178 of the Tiva Peripheral Driver Library. +// +//***************************************************************************** + +#ifndef __DRIVERLIB_UART_H__ +#define __DRIVERLIB_UART_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear +// as the ui32IntFlags parameter, and returned from UARTIntStatus. +// +//***************************************************************************** +#define UART_INT_DMATX 0x20000 // DMA TX interrupt +#define UART_INT_DMARX 0x10000 // DMA RX interrupt +#define UART_INT_9BIT 0x1000 // 9-bit address match interrupt +#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask +#define UART_INT_BE 0x200 // Break Error Interrupt Mask +#define UART_INT_PE 0x100 // Parity Error Interrupt Mask +#define UART_INT_FE 0x080 // Framing Error Interrupt Mask +#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask +#define UART_INT_TX 0x020 // Transmit Interrupt Mask +#define UART_INT_RX 0x010 // Receive Interrupt Mask +#define UART_INT_DSR 0x008 // DSR Modem Interrupt Mask +#define UART_INT_DCD 0x004 // DCD Modem Interrupt Mask +#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask +#define UART_INT_RI 0x001 // RI Modem Interrupt Mask + +//***************************************************************************** +// +// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter +// and returned by UARTConfigGetExpClk in the pui32Config parameter. +// Additionally, the UART_CONFIG_PAR_* subset can be passed to +// UARTParityModeSet as the ui32Parity parameter, and are returned by +// UARTParityModeGet. +// +//***************************************************************************** +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32TxLevel. +// +//***************************************************************************** +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter +// and returned by UARTFIFOLevelGet in the pui32RxLevel. +// +//***************************************************************************** +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full + +//***************************************************************************** +// +// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). +// +//***************************************************************************** +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive + +//***************************************************************************** +// +// Values returned from UARTRxErrorGet(). +// +//***************************************************************************** +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTHandshakeOutputsSet() or returned from +// UARTHandshakeOutputGet(). +// +//***************************************************************************** +#define UART_OUTPUT_RTS 0x00000800 +#define UART_OUTPUT_DTR 0x00000400 + +//***************************************************************************** +// +// Values that can be returned from UARTHandshakeInputsGet(). +// +//***************************************************************************** +#define UART_INPUT_RI 0x00000100 +#define UART_INPUT_DCD 0x00000004 +#define UART_INPUT_DSR 0x00000002 +#define UART_INPUT_CTS 0x00000001 + +//***************************************************************************** +// +// Values that can be passed to UARTFlowControl() or returned from +// UARTFlowControlGet(). +// +//***************************************************************************** +#define UART_FLOWCONTROL_TX 0x00008000 +#define UART_FLOWCONTROL_RX 0x00004000 +#define UART_FLOWCONTROL_NONE 0x00000000 + +//***************************************************************************** +// +// Values that can be passed to UARTTxIntModeSet() or returned from +// UARTTxIntModeGet(). +// +//***************************************************************************** +#define UART_TXINT_MODE_FIFO 0x00000000 +#define UART_TXINT_MODE_EOT 0x00000010 + +//***************************************************************************** +// +// Values that can be passed to UARTClockSourceSet() or returned from +// UARTClockSourceGet(). +// +//***************************************************************************** +#define UART_CLOCK_SYSTEM 0x00000000 +#define UART_CLOCK_PIOSC 0x00000005 + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +extern void UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity); +extern uint32_t UARTParityModeGet(uint32_t ui32Base); +extern void UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, + uint32_t ui32RxLevel); +extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, + uint32_t *pui32RxLevel); +extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t ui32Baud, uint32_t ui32Config); +extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, + uint32_t *pui32Baud, uint32_t *pui32Config); +extern void UARTEnable(uint32_t ui32Base); +extern void UARTDisable(uint32_t ui32Base); +extern void UARTFIFOEnable(uint32_t ui32Base); +extern void UARTFIFODisable(uint32_t ui32Base); +extern void UARTEnableSIR(uint32_t ui32Base, bool bLowPower); +extern void UARTDisableSIR(uint32_t ui32Base); +extern bool UARTCharsAvail(uint32_t ui32Base); +extern bool UARTSpaceAvail(uint32_t ui32Base); +extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); +extern int32_t UARTCharGet(uint32_t ui32Base); +extern bool UARTCharPutNonBlocking(uint32_t ui32Base, unsigned char ucData); +extern void UARTCharPut(uint32_t ui32Base, unsigned char ucData); +extern void UARTBreakCtl(uint32_t ui32Base, bool bBreakState); +extern bool UARTBusy(uint32_t ui32Base); +extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void UARTIntUnregister(uint32_t ui32Base); +extern void UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t UARTIntStatus(uint32_t ui32Base, bool bMasked); +extern void UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern void UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags); +extern uint32_t UARTRxErrorGet(uint32_t ui32Base); +extern void UARTRxErrorClear(uint32_t ui32Base); +extern void UARTSmartCardEnable(uint32_t ui32Base); +extern void UARTSmartCardDisable(uint32_t ui32Base); +extern void UARTModemControlSet(uint32_t ui32Base, uint32_t ui32Control); +extern void UARTModemControlClear(uint32_t ui32Base, uint32_t ui32Control); +extern uint32_t UARTModemControlGet(uint32_t ui32Base); +extern uint32_t UARTModemStatusGet(uint32_t ui32Base); +extern void UARTFlowControlSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTFlowControlGet(uint32_t ui32Base); +extern void UARTTxIntModeSet(uint32_t ui32Base, uint32_t ui32Mode); +extern uint32_t UARTTxIntModeGet(uint32_t ui32Base); +extern void UARTClockSourceSet(uint32_t ui32Base, uint32_t ui32Source); +extern uint32_t UARTClockSourceGet(uint32_t ui32Base); +extern void UART9BitEnable(uint32_t ui32Base); +extern void UART9BitDisable(uint32_t ui32Base); +extern void UART9BitAddrSet(uint32_t ui32Base, uint8_t ui8Addr, + uint8_t ui8Mask); +extern void UART9BitAddrSend(uint32_t ui32Base, uint8_t ui8Addr); +extern void UARTLoopbackEnable(uint32_t ui32Base); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_UART_H__ diff --git a/CCS/mm/src/makefile.libs b/CCS/mm/src/makefile.libs new file mode 100644 index 0000000..648e1fe --- /dev/null +++ b/CCS/mm/src/makefile.libs @@ -0,0 +1,62 @@ +# +# This file was generated based on the configuration script: +# C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\gpiointerrupt.cfg +# +# This makefile may be included in other makefiles that need to build +# the libraries containing the compiled source files generated as +# part of the configuration step. + +# +# ======== GEN_SRC_DIR ========= +# The path to the sources generated during configuration +# +# This path must be either absolute or relative to the build directory. +# +# The absolute path to the generated source directory (at the time the +# sources were generated) is: +# C:\Users\Allen\Documents\GitHub\mm20\CCS\mm\src +# +GEN_SRC_DIR ?= ../src + +ifeq (,$(wildcard $(GEN_SRC_DIR))) +$(error "ERROR: GEN_SRC_DIR must be set to the directory containing the generated sources") +endif + +# +# ======== .force ======== +# The .force goal is used to force the build of any goal that names it as +# a prerequisite +# +.PHONY: .force + +# +# ======== library macros ======== +# +sysbios_SRC = $(GEN_SRC_DIR)/sysbios +sysbios_LIB = $(GEN_SRC_DIR)/sysbios/sysbios.aem4f + +# +# ======== dependencies ======== +# +all: $(sysbios_LIB) +clean: .sysbios_clean + + +# ======== convenient build goals ======== +.PHONY: sysbios +sysbios: $(GEN_SRC_DIR)/sysbios/sysbios.aem4f + +# CDT managed make executables depend on $(OBJS) +OBJS += $(sysbios_LIB) + +# +# ======== rules ======== +# +$(sysbios_LIB): .force + @echo making $@ ... + @$(MAKE) -C $(sysbios_SRC) + +.sysbios_clean: + @echo cleaning $(sysbios_SRC) ... + -@$(MAKE) --no-print-directory -C $(sysbios_SRC) clean + diff --git a/CCS/mm/src/sysbios/BIOS.obj b/CCS/mm/src/sysbios/BIOS.obj new file mode 100644 index 0000000..02f2cf0 Binary files /dev/null and b/CCS/mm/src/sysbios/BIOS.obj differ diff --git a/CCS/mm/src/sysbios/m3_Hwi_asm.obj b/CCS/mm/src/sysbios/m3_Hwi_asm.obj new file mode 100644 index 0000000..546a361 Binary files /dev/null and b/CCS/mm/src/sysbios/m3_Hwi_asm.obj differ diff --git a/CCS/mm/src/sysbios/m3_Hwi_asm_switch.obj b/CCS/mm/src/sysbios/m3_Hwi_asm_switch.obj new file mode 100644 index 0000000..287481b Binary files /dev/null and b/CCS/mm/src/sysbios/m3_Hwi_asm_switch.obj differ diff --git a/CCS/mm/src/sysbios/m3_IntrinsicsSupport_asm.obj b/CCS/mm/src/sysbios/m3_IntrinsicsSupport_asm.obj new file mode 100644 index 0000000..21dd82a Binary files /dev/null and b/CCS/mm/src/sysbios/m3_IntrinsicsSupport_asm.obj differ diff --git a/CCS/mm/src/sysbios/m3_TaskSupport_asm.obj b/CCS/mm/src/sysbios/m3_TaskSupport_asm.obj new file mode 100644 index 0000000..fc14b82 Binary files /dev/null and b/CCS/mm/src/sysbios/m3_TaskSupport_asm.obj differ diff --git a/CCS/mm/src/sysbios/makefile b/CCS/mm/src/sysbios/makefile new file mode 100644 index 0000000..6db813a --- /dev/null +++ b/CCS/mm/src/sysbios/makefile @@ -0,0 +1,87 @@ + +XOPTS = -I"C:/ti/ccs930/xdctools_3_60_02_34_core/packages/" -Dxdc_target_types__=C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/targets/arm/elf/std.h -Dxdc_target_name__=M4F + +vpath % C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/ +vpath %.c C:/ti/ccs930/xdctools_3_60_02_34_core/packages/ + +CCOPTS = --endian=little -mv7M4 --abi=eabi --float_support=fpv4spd16 -q -ms --opt_for_speed=2 --program_level_compile -o3 -g --optimize_with_debug -Dti_sysbios_knl_Task_minimizeLatency__D=FALSE -Dti_sysbios_knl_Clock_stopCheckNext__D=FALSE -Dti_sysbios_family_arm_m3_Hwi_enableException__D=TRUE -Dti_sysbios_family_arm_m3_Hwi_disablePriority__D=32U -Dti_sysbios_family_arm_m3_Hwi_numSparseInterrupts__D=0U + +XDC_ROOT = C:/ti/ccs930/xdctools_3_60_02_34_core/packages/ + +BIOS_ROOT = C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/ + +BIOS_DEFS = -Dti_sysbios_BIOS_swiEnabled__D=TRUE -Dti_sysbios_BIOS_taskEnabled__D=TRUE -Dti_sysbios_BIOS_clockEnabled__D=TRUE -Dti_sysbios_BIOS_runtimeCreatesEnabled__D=TRUE -Dti_sysbios_hal_Hwi_DISABLE_ALL_HOOKS -Dti_sysbios_knl_Swi_DISABLE_ALL_HOOKS -Dti_sysbios_BIOS_smpEnabled__D=FALSE -Dti_sysbios_Build_useHwiMacros -Dti_sysbios_knl_Swi_numPriorities__D=16 -Dti_sysbios_knl_Task_deleteTerminatedTasks__D=FALSE -Dti_sysbios_knl_Task_numPriorities__D=16 -Dti_sysbios_knl_Task_checkStackFlag__D=TRUE -Dti_sysbios_knl_Task_initStackFlag__D=TRUE -Dti_sysbios_knl_Task_DISABLE_ALL_HOOKS -Dti_sysbios_knl_Clock_TICK_SOURCE=ti_sysbios_knl_Clock_TickSource_TIMER -Dti_sysbios_knl_Clock_TICK_MODE=ti_sysbios_knl_Clock_TickMode_PERIODIC -Dti_sysbios_hal_Core_delegate_getId=ti_sysbios_hal_CoreNull_getId__E -Dti_sysbios_hal_Core_delegate_interruptCore=ti_sysbios_hal_CoreNull_interruptCore__E -Dti_sysbios_hal_Core_delegate_lock=ti_sysbios_hal_CoreNull_lock__E -Dti_sysbios_hal_Core_delegate_unlock=ti_sysbios_hal_CoreNull_unlock__E -Dti_sysbios_hal_Core_numCores__D=1 -Dti_sysbios_hal_CoreNull_numCores__D=1 -Dti_sysbios_utils_Load_taskEnabled__D=TRUE -Dti_sysbios_utils_Load_swiEnabled__D=FALSE -Dti_sysbios_utils_Load_hwiEnabled__D=FALSE -Dti_sysbios_family_arm_m3_Hwi_dispatcherSwiSupport__D=TRUE -Dti_sysbios_family_arm_m3_Hwi_dispatcherTaskSupport__D=TRUE -Dti_sysbios_family_arm_m3_Hwi_dispatcherAutoNestingSupport__D=TRUE -Dti_sysbios_family_arm_m3_Hwi_dispatcherIrpTrackingSupport__D=TRUE -Dti_sysbios_knl_Semaphore_supportsEvents__D=FALSE -Dti_sysbios_knl_Semaphore_supportsPriority__D=FALSE -Dxdc_runtime_Assert_DISABLE_ALL -Dxdc_runtime_Log_DISABLE_ALL + +BIOS_INC = -I"C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/" + +TARGET_INC = -I"C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/" + +INCS = $(BIOS_INC) $(TARGET_INC) --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm/inc" --include_path="C:/Users/Allen/Documents/GitHub/mm20/CCS/mm" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/TivaWare_C_Series-2.1.1.71b" --include_path="C:/ti/tirtos_tivac_2_16_00_08/products/bios_6_45_01_29/packages/ti/sysbios/posix" --include_path="C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include" + +CC = C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include +ASM = C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/bin/armcl -c $(CCOPTS) -I C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/include +AR = C:/ti/ccs930/ccs/tools/compiler/ti-cgt-arm_18.12.4.LTS/bin/armar rq + +DEL = C:/ti/ccs930/xdctools_3_60_02_34_core/packages/../bin/rm -f +CP = C:/ti/ccs930/xdctools_3_60_02_34_core/packages/../bin/cp -f + +define RM + $(if $(wildcard $1),$(DEL) $1,:) +endef + +define ASSEMBLE + @echo asmem4f $< ... + @$(ASM) $(BIOS_DEFS) $(XOPTS) $(INCS) $< +endef + +all: sysbios.aem4f + +m3_Hwi_asm.obj: family/arm/m3/Hwi_asm.sv7M makefile + @-$(call RM, $@) + $(ASSEMBLE) --output_file=m3_Hwi_asm.obj + +m3_Hwi_asm_switch.obj: family/arm/m3/Hwi_asm_switch.sv7M makefile + @-$(call RM, $@) + $(ASSEMBLE) --output_file=m3_Hwi_asm_switch.obj + +m3_IntrinsicsSupport_asm.obj: family/arm/m3/IntrinsicsSupport_asm.sv7M makefile + @-$(call RM, $@) + $(ASSEMBLE) --output_file=m3_IntrinsicsSupport_asm.obj + +m3_TaskSupport_asm.obj: family/arm/m3/TaskSupport_asm.sv7M makefile + @-$(call RM, $@) + $(ASSEMBLE) --output_file=m3_TaskSupport_asm.obj + + +BIOS.obj: BIOS.c knl/Clock.c knl/Idle.c knl/Intrinsics.c knl/Queue.c knl/Semaphore.c knl/Swi.c knl/Swi_andn.c knl/Task.c hal/Hwi.c hal/Hwi_stack.c hal/Hwi_startup.c family/arm/m3/Hwi.c family/arm/m3/TaskSupport.c gates/GateHwi.c gates/GateMutex.c heaps/HeapMem.c family/arm/lm4/Timer.c makefile + @-$(call RM, $@) + @echo clem4f $< ... + @$(CC) $(BIOS_DEFS) $(XOPTS) $(INCS) \ + $(BIOS_ROOT)BIOS.c \ + $(BIOS_ROOT)knl/Clock.c \ + $(BIOS_ROOT)knl/Idle.c \ + $(BIOS_ROOT)knl/Intrinsics.c \ + $(BIOS_ROOT)knl/Queue.c \ + $(BIOS_ROOT)knl/Semaphore.c \ + $(BIOS_ROOT)knl/Swi.c \ + $(BIOS_ROOT)knl/Swi_andn.c \ + $(BIOS_ROOT)knl/Task.c \ + $(BIOS_ROOT)hal/Hwi.c \ + $(BIOS_ROOT)hal/Hwi_stack.c \ + $(BIOS_ROOT)hal/Hwi_startup.c \ + $(BIOS_ROOT)family/arm/m3/Hwi.c \ + $(BIOS_ROOT)family/arm/m3/TaskSupport.c \ + $(BIOS_ROOT)gates/GateHwi.c \ + $(BIOS_ROOT)gates/GateMutex.c \ + $(BIOS_ROOT)heaps/HeapMem.c \ + $(BIOS_ROOT)family/arm/lm4/Timer.c \ + +sysbios.aem4f: BIOS.obj m3_Hwi_asm.obj m3_Hwi_asm_switch.obj m3_IntrinsicsSupport_asm.obj m3_TaskSupport_asm.obj + @-$(call RM, $@) + @echo arem4f $^ ... + @$(AR) $@ $^ + + +clean: + @$(DEL) ..\makefile.libs + @-$(call RM, *) diff --git a/CCS/mm/src/sysbios/sysbios.aem4f b/CCS/mm/src/sysbios/sysbios.aem4f new file mode 100644 index 0000000..671091d Binary files /dev/null and b/CCS/mm/src/sysbios/sysbios.aem4f differ diff --git a/CCS/mm/test.ccxml b/CCS/mm/test.ccxml new file mode 100644 index 0000000..d34bca5 --- /dev/null +++ b/CCS/mm/test.ccxml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/mm.uvprojx b/mm.uvprojx index cacd6db..032c871 100644 --- a/mm.uvprojx +++ b/mm.uvprojx @@ -300,6 +300,11 @@ 1 .\lib\startup.c + + motors.c + 1 + .\lib\motors.c + @@ -380,6 +385,11 @@ 5 .\inc\launchpad.h + + motors.h + 5 + .\inc\motors.h +