From 41925e3e67c2f073cad31b1bf364ec78423899f3 Mon Sep 17 00:00:00 2001 From: ulysse31 Date: Sat, 15 Jun 2019 19:16:59 +0200 Subject: [PATCH] Updated schema : longer but smaller ^^' (possibility to solder arduino and mcp module directly without header connectors) --- Hardware/USB_Powered/CID_Faker.bin | Bin 0 -> 24965 bytes Hardware/USB_Powered/CID_Faker.dsn | 57 ++++++------ Hardware/USB_Powered/CID_Faker.kicad_pcb | 70 +++++++------- Hardware/USB_Powered/CID_Faker.net | 35 +++---- Hardware/USB_Powered/CID_Faker.rules | 2 +- Hardware/USB_Powered/CID_Faker.sch | 4 +- Hardware/USB_Powered/CID_Faker.ses | 114 +++++++++++------------ 7 files changed, 137 insertions(+), 145 deletions(-) create mode 100644 Hardware/USB_Powered/CID_Faker.bin diff --git a/Hardware/USB_Powered/CID_Faker.bin b/Hardware/USB_Powered/CID_Faker.bin new file mode 100644 index 0000000000000000000000000000000000000000..63a4d0fcdc9e7314d62baccda8eab49578112c7b GIT binary patch literal 24965 zcmeHvdw5*cb?=@TTe2+4Pswlm0D&>Vl4Z=xCio%QjzE5Zz;>m=a5Qry4Ia%5XU^CX zH$Xl}DR8-k-lQbq;}S>$1WL=}5^iV+#I7MG0YV;y57MM@pn=eu2tpf5kk9?Cwf8=+ zIWvgwYrpUQanJY3p0oElzrEJlYp=E64;~ehixKD}oyiSuqL-m;_i-x+ zuRR2h^p>|V7kNy^BD(&8oS3URflN3AUl z172tjma>L*Q6_8l3>gJeK_8TrJU>hxrh8h_9T%qCna_@9Gr0if_lULtspf^LArJqUL{EdR=<}kUR_DKd6vlrdu9BtfGBsph@<`3?5-rI6JikdC0G+-X8lo#S+ za+jEj>dt3j&u`WF_@qfgCJTmDgq>wjm@Q8B4A(RImL667 zPA2UFB@iZ|QNWTL)E5`yjZH~Rg%(Z;@ZYKnYmMMvD(AZCagpd0HT_1>OpfRuqn)Cm zm@=|va==JIFf!HPv!O-4qs+Nd^Id3V0cpQ_}@f-&sV$B(aRP?;=*NWf>zdpBDnR%Jzt$s zT#=PtM{w(!?wYBTODSR*2f}zR-z%o%VUrf(Rj-&<$QLtYY0$@rneG&`SUr@0(3my{ zEz|54GY~i63Q~KGK{MHp|7|hTjU_u}I@C1NPsRn1x=x1;XY)Ej&Mk`!IxI9~^MeSa zS@Jn>9nEe5-7+2ig`&r#oG~nIn%jF!hz+|w$0mU~nXUp{t77WK$A5axHDAq)L3W6p zDN3=s1k?ci?={T=Iux?v7xcLWs*hXFm-&H0`$R21p;&^BL0_3L9JKI3gVvUe=(EDu z#dQEGK*elybIQx!naP1F51TZBEIWxCL7KKCFqsN>DH z*T$}mA^?568gEnS$GMz&Hnn$|1Jw&O<(UO5Kb%Qf`L#Q({5JZ*-)%zX3~kH5e^VqL zeFC!fJIC&R5k_&Y5GpNp>1r+aN87d%8EpEXCUcy`kA(QB-8pvO13ogxX_&9cV8eGh z$3C5O#uvpM0UCx z0m6%JZZM+gw(vl5*}czq{z8X`c?b`)LoKNVgm=HyIlk>@&$q_Kq%MKRq*_icU!k+& zbr8@au}lPo%sw;e^+3vp^Qxc6{R#A2<%3>nJ2)yEaw1?!dKIsJ92^~%4Uq%HKVo5> z@n3d3$6nsU4Uz^e)QtH-p{qI7c8+cQd_|hmG|e}jtVpv)(Kxm5SEM;z)9gL9BF!0^ z2Jxa2&u2;+cJq~J&eAkr{8>euvo*~J4V7r(?W+_~tgo{&QM)F3>a&%Jl&VF1*<+Q7 zl&*FR+-3EI09-##+AmY zH&BsiwbHob>^-$Ik<&hoj}_i9%d2gmh3c!_%5Z1CEPnZhDExPv((8ypP9Y%ys| zYe$JK^ci~Fq~CNWVzSqXKncEXi|4%$~G0m{iLm5gM*=&BlndUK5ub9pQl62DO z=V>a84gKym*sme=?dlUXMViRN?Be3`;SvTO`^*tJTwwPLSBRl7rg?MezKxflvXbp* ztXh>U4HMYY(3}rMk2d@uKV6)9=C0qreuH0=WiGiRW2LfcYVo>h?7wR)Bb_M~yG2b3 zLv>S4P@ zkEh^*Cxr|C7};G|DY-6q*&33Y-#(s#3!Y47vnyltty!PT} zgy6S`boL-4+-hC~OI?^!B*|$d0 z=s-g>{z&UDOUD_eDK3q~al;JZOn)nq#*H$d8GrC$&#`*H$c*GrWQLf1*_iWQ!%~`& zJ5QC4XV{(KG3;kEm{_2S_AM{8*PL;0y6phws%8Z8rZ zbC|{|X0Sqn9-!zDj2z8 zOX+WGW^TDJA!2G}$xsvf!Aay{Or+6-KNv3%Z)c&H_Uf8#32J(KKCRtk3wOUKXQf(e zq~>g~BD|Ck1Sq!jfB{;%!kkz=*OdP9w2%8Th(xRqMu}!(B?e@QEtOG&#bYUB(@FKQ z#i%JkKc+*)Bb+pgC&vP{=NnX4s<4;~M^oNv{YEb*VVNbRm#BV;kdKu#ni)i_D_;Q9 z->kzDl8WuV&##-wVQ8vjv#0u4VT;;}w{Pj%v$+#-8yMUE?y{5iz5VDtIyO^%)Cyi* z6r|j;bvUguCG=!pr)q9_Ujl0ortDq$GIbw;GoOF!wY&c~<=NGm0a{pY3QtH9rE)L_ zxNjIUNE%Fo#rpY&nwXIe@10vtX3L?s-#PExvVzTJEm__N8UC!?w`wK5)y)R?z zm+XmS{KZC<(frs3@}%Au9d5=(WGsP2d)|_YTF705*a|3Ajb9VTvGuo;dy1Wg^q{gS z^>ofV3we`eNvaU?<5k4!R%B&j?eJv;#JWIbl!?{jX0TZF#tk=4KeiUigo?c%yPC3A zVg0D*Gdp%|PD<;dG%X_nGc8xcpeWUok==G|ttzo;`DI$eSf6cLZs<2z5tjzYmN1n5 z6xhzYucQ?P3es=PdW=fl9l`p0oD-~%O1w@A6iD^)?&gP8f%5GUNkN6})fs>FpeB<- zW@aO8?8w)A6k|v3rZ=U=|Z-7@z)X4!l z1|2F~9O2=4Xxxm&Pd#Nxp;k>pwCQOG>J6v`+fFN!&3ZBZ+MjceYkqKXi&w4XJVjS{ z;fpsfaG#-5%ng1<`ALxya~{EGZW$4gDUNj=e!^w^@>OOfO&L0bNs} z3WJ@MrlT+EN<$Sk9sRL>ld}Cvses7F{^3SX=-0Jw?z_MlTQtSX_-CB~?;pr`GmybE z0iM2o9wF4h2%&Uc$GAYRcM_^=iac(|lH<@V%O#6GCj1nLO}gu;DNqCNe3>OC+xDzS zD&`L^*%a51+~)f)5z^dSMH==9zBn3cWg%%cYT1~RxOOKj=BLJ_m@vsWqY&>Dc~yqX z;vXYe{8MHz7%s4qAK6U_vPcsVUbtww=_~q8ve=-MCCNUiBZ${V@Y)-p&Pu!nje|N- zW54DhEtDhQxF6+);V5Z>9szCE=MnsUSn3|cr_(1|v|;ia{!5l@R|bp)VVy(zz$(& zDsMc)yo6foqYV!1r2aR&3C+EbS7{4#fHZpC-V?1X%q2$l1YOh~B@VVcxnQjm0h>c$ zeL=9k2(XnC0c$2Oo*Ln>z|Qkh9~gD;Nz7A2U?e`~`S@`~WsfZ57dkS?Ya(MMt$honp#5WlIu{DY#^|!f{M5*0_=o|fYlS& z=Yn9LivT-*B4D%^Fn(PS?79fBWfK9bBe3g(VAn^0Eu9G16ate2F1G@1^nq#9ToMAK ziowv2pK$fk5CLN{7&!>6DbF&X!SMTBwx&ro$o;+?1f!!LETTMsB{T}zYiGWQe zurCC`zTo3b%e^QBra2}KqvXa+ByuJZ`fWk<+ak~xMxav(^hBbw3r-OF?LqY0BhVLo zQuI&J%n{A%$L|cH-|0iw8kiqKXQuspQ=Jh_oaZ7v1Nd45*u05=aU{DZ$k{y#>;zRj zaW}UN%s*Z$`k)sS4La5cI$<=Bg+cMxZlpjQ()K^9MOa#gc5hzouqHK*oc_{*=t}4ow z2$Y{H6p9h#*2zUo387G0rM@qPGdK!Ra0Gfe*w$Z;K(CEJrxNIK-8wjp9Y6v{qSu0; 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cr-isJIFouT5>=}>}5-xVyrj30%8l?3mkeRrO&kG=YXnU~$M>OcN9L1(I` z3>n3t6b_qXNXe7l)+p5)E>)che=KdE_@$I7bQNa_cVepd8nl~CfhHFyw|1XlWpKGG zzm62>coXh5#arT8)RIYewI-hBfB1rl#6zeL>eb9tHszYfy0cDv?Wq@^Nd1GhC_b*D zRD+L#g8#-Lz4}y&azhEMc^^gkHn%E>AHRJFhu|so86MlY&4`!H9zS%GwdU%>Cvg)} z7bK(Q#J+|J0X{#F_%ZmS-F|an^@p;VMSiB|dX$gR1Fm)*?xJP2&b%-9%z;$?~_klC*?4~8;hfQ;=_nU_LA$CFS} z3hEZp_#`aNzg_!htuJl4;Tup`K$r_NMs9HQB%ES0% zLX^A>U}BWFP8jq32~%E5lwrmE5Lz2U22BF;CQ4s3hGQ17FCv4gGAc7c%chihI0P$h zN8yS!2iW?FDgH)CsYP*#++D9#rF_psKD4l6v#8X I$UOXi0eL@uuK)l5 literal 0 HcmV?d00001 diff --git a/Hardware/USB_Powered/CID_Faker.dsn b/Hardware/USB_Powered/CID_Faker.dsn index 22cb40e..fa99b11 100644 --- a/Hardware/USB_Powered/CID_Faker.dsn +++ b/Hardware/USB_Powered/CID_Faker.dsn @@ -3,7 +3,7 @@ (string_quote ") (space_in_quoted_tokens on) (host_cad "KiCad's Pcbnew") - (host_version "4.0.7") + (host_version "(5.1.2-1)-1") ) (resolution um 10) (unit um) @@ -21,8 +21,8 @@ ) ) (boundary - (path pcb 0 143891 -90043 125349 -90043 125349 -124079 143891 -124079 - 143891 -90043 143891 -90043) + (path pcb 0 143891 -124079 125349 -124079 125349 -90043 143891 -90043 + 143891 -124079) ) (via "Via[0-1]_600:400_um") (rule @@ -33,29 +33,30 @@ ) ) (placement - (component Socket_Strips:Socket_Strip_Straight_1x07_Pitch2.54mm - (place J2 127000 -122301 back 90 (PN CAN)) + (component Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical + (place J1 127000 -91440 back 90 (PN CAN1)) ) (component promicro:ProMicro - (place U1 134620 -105283 front 90 (PN ProMicro)) + (place U1 134620 -107950 front 90 (PN ProMicro)) ) ) (library - (image Socket_Strips:Socket_Strip_Straight_1x07_Pitch2.54mm - (outline (path signal 100 -1270 1270 -1270 -16510)) - (outline (path signal 100 -1270 -16510 1270 -16510)) - (outline (path signal 100 1270 -16510 1270 1270)) - (outline (path signal 100 1270 1270 -1270 1270)) + (image Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical + (outline (path signal 100 -1270 1270 635 1270)) + (outline (path signal 100 635 1270 1270 635)) + (outline (path signal 100 1270 635 1270 -16510)) + (outline (path signal 100 1270 -16510 -1270 -16510)) + (outline (path signal 100 -1270 -16510 -1270 1270)) + (outline (path signal 120 -1330 -1270 1330 -1270)) (outline (path signal 120 -1330 -1270 -1330 -16570)) (outline (path signal 120 -1330 -16570 1330 -16570)) - (outline (path signal 120 1330 -16570 1330 -1270)) - (outline (path signal 120 1330 -1270 -1330 -1270)) - (outline (path signal 120 -1330 0 -1330 1330)) - (outline (path signal 120 -1330 1330 0 1330)) - (outline (path signal 50 -1800 1800 -1800 -17050)) - (outline (path signal 50 -1800 -17050 1800 -17050)) - (outline (path signal 50 1800 -17050 1800 1800)) - (outline (path signal 50 1800 1800 -1800 1800)) + (outline (path signal 120 1330 -1270 1330 -16570)) + (outline (path signal 120 1330 1330 1330 0)) + (outline (path signal 120 0 1330 1330 1330)) + (outline (path signal 50 -1800 1800 1750 1800)) + (outline (path signal 50 1750 1800 1750 -17000)) + (outline (path signal 50 1750 -17000 -1800 -17000)) + (outline (path signal 50 -1800 -17000 -1800 1800)) (pin Rect[A]Pad_1700x1700_um 1 0 0) (pin Oval[A]Pad_1700x1700_um 2 0 -2540) (pin Oval[A]Pad_1700x1700_um 3 0 -5080) @@ -134,31 +135,31 @@ ) (network (net GND - (pins J2-6 U1-3 U1-4 U1-23) + (pins J1-6 U1-3 U1-4) ) (net INT - (pins J2-1 U1-5) + (pins J1-1 U1-5) ) (net SCK - (pins J2-2 U1-16) + (pins J1-2 U1-16) ) (net MOSI - (pins J2-3 U1-14) + (pins J1-3 U1-14) ) (net MISO - (pins J2-4 U1-15) + (pins J1-4 U1-15) ) (net CS - (pins J2-5 U1-8) + (pins J1-5 U1-8) ) (net VCC - (pins J2-7 U1-21) + (pins J1-7 U1-21) ) (class kicad_default "" CS GND INT MISO MOSI "Net-(U1-Pad1)" "Net-(U1-Pad10)" "Net-(U1-Pad11)" "Net-(U1-Pad12)" "Net-(U1-Pad13)" "Net-(U1-Pad17)" "Net-(U1-Pad18)" "Net-(U1-Pad19)" "Net-(U1-Pad2)" "Net-(U1-Pad20)" "Net-(U1-Pad22)" - "Net-(U1-Pad24)" "Net-(U1-Pad6)" "Net-(U1-Pad7)" "Net-(U1-Pad9)" RAW - SCK VCC VIN + "Net-(U1-Pad23)" "Net-(U1-Pad24)" "Net-(U1-Pad6)" "Net-(U1-Pad7)" "Net-(U1-Pad9)" + SCK VCC (circuit (use_via Via[0-1]_600:400_um) ) diff --git a/Hardware/USB_Powered/CID_Faker.kicad_pcb b/Hardware/USB_Powered/CID_Faker.kicad_pcb index b835fda..9ecfd0a 100644 --- a/Hardware/USB_Powered/CID_Faker.kicad_pcb +++ b/Hardware/USB_Powered/CID_Faker.kicad_pcb @@ -3,7 +3,7 @@ (general (thickness 1.6) (drawings 5) - (tracks 30) + (tracks 29) (zones 0) (modules 2) (nets 8) @@ -115,7 +115,7 @@ ) (module Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical (layer B.Cu) (tedit 5A19A433) (tstamp 5CFFE7A6) - (at 127 121.92 270) + (at 127 91.44 270) (descr "Through hole straight socket strip, 1x07, 2.54mm pitch, single row (from Kicad 4.0.7), script generated") (tags "Through hole socket strip THT 1x07 2.54mm single row") (path /5CFEC3BA) @@ -165,7 +165,7 @@ ) (module promicro:ProMicro (layer F.Cu) (tedit 5A06A962) (tstamp 5CFFE7D2) - (at 134.62 105.41 90) + (at 134.62 107.95 90) (descr "Pro Micro footprint") (tags "promicro ProMicro") (path /5CFEB39A) @@ -221,12 +221,11 @@ (pad 21 thru_hole circle (at -6.35 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS) (net 7 VCC)) (pad 22 thru_hole circle (at -8.89 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS)) - (pad 23 thru_hole circle (at -11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS) - (net 1 GND)) + (pad 23 thru_hole circle (at -11.43 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS)) (pad 24 thru_hole circle (at -13.97 -7.62 90) (size 1.6 1.6) (drill 1.1) (layers *.Cu *.Mask F.SilkS)) ) - (gr_text "Designed by\nUlysse31 a.k.a Nix\nUlysse31@gmail.com\n" (at 135.89 102.87 90) (layer B.Cu) + (gr_text "Designed by\nUlysse31 a.k.a Nix\nUlysse31@gmail.com\n" (at 133.35 111.76 90) (layer B.Cu) (tstamp 5D0524F1) (effects (font (size 1.5 1.5) (thickness 0.3)) (justify mirror)) ) (gr_line (start 143.891 90.043) (end 143.891 124.079) (angle 90) (layer Edge.Cuts) (width 0.15)) @@ -234,35 +233,34 @@ (gr_line (start 125.349 124.079) (end 125.349 90.043) (angle 90) (layer Edge.Cuts) (width 0.15)) (gr_line (start 143.891 124.079) (end 125.349 124.079) (angle 90) (layer Edge.Cuts) (width 0.15)) - (segment (start 139.7 120.57) (end 139.7 120.3918) (width 0.5) (layer B.Cu) (net 1)) - (segment (start 139.7 120.3918) (end 136.1482 116.84) (width 0.5) (layer B.Cu) (net 1)) - (segment (start 136.1482 116.84) (end 127 116.84) (width 0.5) (layer B.Cu) (net 1)) - (segment (start 142.24 114.3) (end 139.7 116.84) (width 0.5) (layer F.Cu) (net 1)) - (segment (start 139.7 116.84) (end 139.7 121.92) (width 0.5) (layer F.Cu) (net 1)) - (segment (start 142.24 111.76) (end 142.24 114.3) (width 0.5) (layer F.Cu) (net 1)) - (segment (start 139.7 121.92) (end 139.7 120.57) (width 0.5) (layer B.Cu) (net 1)) - (segment (start 137.8372 119.5902) (end 129.3298 119.5902) (width 0.5) (layer B.Cu) (net 2)) - (segment (start 129.3298 119.5902) (end 127 121.92) (width 0.5) (layer B.Cu) (net 2)) - (segment (start 142.24 109.22) (end 137.8372 113.6228) (width 0.5) (layer F.Cu) (net 2)) - (segment (start 137.8372 113.6228) (end 137.8372 119.5902) (width 0.5) (layer F.Cu) (net 2)) - (via (at 137.8372 119.5902) (size 0.6) (layers F.Cu B.Cu) (net 2)) - (segment (start 127 99.06) (end 129.4467 101.5067) (width 0.5) (layer F.Cu) (net 3)) - (segment (start 129.4467 101.5067) (end 129.4467 120.4767) (width 0.5) (layer F.Cu) (net 3)) - (segment (start 129.4467 120.4767) (end 129.54 120.57) (width 0.5) (layer F.Cu) (net 3)) - (segment (start 129.54 121.92) (end 129.54 120.57) (width 0.5) (layer F.Cu) (net 3)) - (segment (start 132.08 120.57) (end 130.1504 118.6404) (width 0.5) (layer F.Cu) (net 4)) - (segment (start 130.1504 118.6404) (end 130.1504 100.9245) (width 0.5) (layer F.Cu) (net 4)) - (segment (start 127 93.98) (end 130.1504 97.1304) (width 0.5) (layer B.Cu) (net 4)) - (segment (start 130.1504 97.1304) (end 130.1504 100.9245) (width 0.5) (layer B.Cu) (net 4)) - (segment (start 132.08 121.92) (end 132.08 120.57) (width 0.5) (layer F.Cu) (net 4)) - (via (at 130.1504 100.9245) (size 0.6) (layers F.Cu B.Cu) (net 4)) - (segment (start 127 96.52) (end 134.62 104.14) (width 0.5) (layer F.Cu) (net 5)) - (segment (start 134.62 104.14) (end 134.62 121.92) (width 0.5) (layer F.Cu) (net 5)) - (segment (start 142.24 101.6) (end 137.0869 106.7531) (width 0.5) (layer F.Cu) (net 6)) - (segment (start 137.0869 106.7531) (end 137.0869 120.4969) (width 0.5) (layer F.Cu) (net 6)) - (segment (start 137.0869 120.4969) (end 137.16 120.57) (width 0.5) (layer F.Cu) (net 6)) - (segment (start 137.16 121.92) (end 137.16 120.57) (width 0.5) (layer F.Cu) (net 6)) - (segment (start 127 111.76) (end 132.08 111.76) (width 0.5) (layer B.Cu) (net 7)) - (segment (start 132.08 111.76) (end 142.24 121.92) (width 0.5) (layer B.Cu) (net 7)) + (segment (start 139.7 91.44) (end 139.7 92.79) (width 0.5) (layer F.Cu) (net 1)) + (segment (start 140.7495 101.9195) (end 140.7495 93.8395) (width 0.5) (layer F.Cu) (net 1)) + (segment (start 140.7495 93.8395) (end 139.7 92.79) (width 0.5) (layer F.Cu) (net 1)) + (segment (start 142.24 114.3) (end 140.7495 112.8095) (width 0.5) (layer B.Cu) (net 1)) + (segment (start 140.7495 112.8095) (end 140.7495 101.9195) (width 0.5) (layer B.Cu) (net 1)) + (segment (start 142.24 114.3) (end 142.24 116.84) (width 0.5) (layer F.Cu) (net 1)) + (via (at 140.7495 101.9195) (size 0.6) (layers F.Cu B.Cu) (net 1)) + (segment (start 127 91.44) (end 127.2429 91.44) (width 0.5) (layer B.Cu) (net 2)) + (segment (start 127.2429 91.44) (end 129.5683 93.7654) (width 0.5) (layer B.Cu) (net 2)) + (segment (start 142.24 111.76) (end 129.5683 99.0883) (width 0.5) (layer F.Cu) (net 2)) + (segment (start 129.5683 99.0883) (end 129.5683 93.7654) (width 0.5) (layer F.Cu) (net 2)) + (via (at 129.5683 93.7654) (size 0.6) (layers F.Cu B.Cu) (net 2)) + (segment (start 129.54 92.79) (end 129.4826 92.79) (width 0.5) (layer F.Cu) (net 3)) + (segment (start 129.4826 92.79) (end 128.818 93.4546) (width 0.5) (layer F.Cu) (net 3)) + (segment (start 128.818 93.4546) (end 128.818 99.782) (width 0.5) (layer F.Cu) (net 3)) + (segment (start 128.818 99.782) (end 127 101.6) (width 0.5) (layer F.Cu) (net 3)) + (segment (start 129.54 91.44) (end 129.54 92.79) (width 0.5) (layer F.Cu) (net 3)) + (segment (start 132.08 91.44) (end 132.08 92.79) (width 0.5) (layer B.Cu) (net 4)) + (segment (start 127 96.52) (end 128.35 96.52) (width 0.5) (layer B.Cu) (net 4)) + (segment (start 128.35 96.52) (end 132.08 92.79) (width 0.5) (layer B.Cu) (net 4)) + (segment (start 134.62 91.44) (end 134.62 92.79) (width 0.5) (layer B.Cu) (net 5)) + (segment (start 127 99.06) (end 133.27 92.79) (width 0.5) (layer B.Cu) (net 5)) + (segment (start 133.27 92.79) (end 134.62 92.79) (width 0.5) (layer B.Cu) (net 5)) + (segment (start 137.16 91.44) (end 137.16 99.3911) (width 0.5) (layer F.Cu) (net 6)) + (segment (start 137.16 99.3911) (end 141.9089 104.14) (width 0.5) (layer F.Cu) (net 6)) + (segment (start 141.9089 104.14) (end 142.24 104.14) (width 0.5) (layer F.Cu) (net 6)) + (segment (start 127 114.3) (end 134.511 106.789) (width 0.5) (layer B.Cu) (net 7)) + (segment (start 134.511 106.789) (end 134.511 99.169) (width 0.5) (layer B.Cu) (net 7)) + (segment (start 134.511 99.169) (end 142.24 91.44) (width 0.5) (layer B.Cu) (net 7)) ) diff --git a/Hardware/USB_Powered/CID_Faker.net b/Hardware/USB_Powered/CID_Faker.net index b10c69e..8b786eb 100644 --- a/Hardware/USB_Powered/CID_Faker.net +++ b/Hardware/USB_Powered/CID_Faker.net @@ -1,7 +1,7 @@ (export (version D) (design (source /Users/nix/Documents/PlatformIO/Projects/CID_Faker/Hardware/USB_Powered/CID_Faker.sch) - (date "2019 June 12, Wednesday 19:22:30") + (date "2019 June 15, Saturday 19:09:22") (tool "Eeschema (5.1.2-1)-1") (sheet (number 1) (name /) (tstamps /) (title_block @@ -110,26 +110,27 @@ (node (ref U1) (pin 13))) (net (code 15) (name "Net-(U1-Pad24)") (node (ref U1) (pin 24))) - (net (code 16) (name INT) - (node (ref J1) (pin 1)) - (node (ref U1) (pin 5))) - (net (code 17) (name SCK) + (net (code 16) (name "Net-(U1-Pad23)") + (node (ref U1) (pin 23))) + (net (code 17) (name INT) + (node (ref U1) (pin 5)) + (node (ref J1) (pin 1))) + (net (code 18) (name SCK) (node (ref U1) (pin 16)) (node (ref J1) (pin 2))) - (net (code 18) (name MOSI) - (node (ref J1) (pin 3)) - (node (ref U1) (pin 14))) - (net (code 19) (name MISO) - (node (ref J1) (pin 4)) - (node (ref U1) (pin 15))) - (net (code 20) (name CS) + (net (code 19) (name MOSI) + (node (ref U1) (pin 14)) + (node (ref J1) (pin 3))) + (net (code 20) (name MISO) + (node (ref U1) (pin 15)) + (node (ref J1) (pin 4))) + (net (code 21) (name CS) (node (ref U1) (pin 8)) (node (ref J1) (pin 5))) - (net (code 21) (name GND) - (node (ref U1) (pin 23)) - (node (ref U1) (pin 4)) + (net (code 22) (name GND) (node (ref U1) (pin 3)) - (node (ref J1) (pin 6))) - (net (code 22) (name VCC) + (node (ref J1) (pin 6)) + (node (ref U1) (pin 4))) + (net (code 23) (name VCC) (node (ref U1) (pin 21)) (node (ref J1) (pin 7))))) \ No newline at end of file diff --git a/Hardware/USB_Powered/CID_Faker.rules b/Hardware/USB_Powered/CID_Faker.rules index 67bce76..83ded91 100644 --- a/Hardware/USB_Powered/CID_Faker.rules +++ b/Hardware/USB_Powered/CID_Faker.rules @@ -11,7 +11,7 @@ (via_costs 50) (plane_via_costs 5) (start_ripup_costs 100) - (start_pass_no 106) + (start_pass_no 124) (layer_rule F.Cu (active on) (preferred_direction vertical) diff --git a/Hardware/USB_Powered/CID_Faker.sch b/Hardware/USB_Powered/CID_Faker.sch index 00644bc..0bacd1a 100644 --- a/Hardware/USB_Powered/CID_Faker.sch +++ b/Hardware/USB_Powered/CID_Faker.sch @@ -1,5 +1,4 @@ EESchema Schematic File Version 4 -LIBS:CID_Faker-cache EELAYER 29 0 EELAYER END $Descr A4 11693 8268 @@ -26,8 +25,6 @@ Text GLabel 3300 1300 1 60 Input ~ 0 VCC Text GLabel 4300 2400 2 60 Input ~ 0 VCC -Text GLabel 4300 2200 2 60 Input ~ 0 -GND Text GLabel 3900 1300 1 60 Input ~ 0 INT Text GLabel 3800 1300 1 60 Input ~ 0 @@ -83,4 +80,5 @@ Text GLabel 2900 2400 0 50 Input ~ 0 GND Text GLabel 2900 2300 0 50 Input ~ 0 GND +NoConn ~ 4300 2200 $EndSCHEMATC diff --git a/Hardware/USB_Powered/CID_Faker.ses b/Hardware/USB_Powered/CID_Faker.ses index 75ede73..468cc3f 100644 --- a/Hardware/USB_Powered/CID_Faker.ses +++ b/Hardware/USB_Powered/CID_Faker.ses @@ -4,10 +4,10 @@ (placement (resolution um 10) (component Connector_PinSocket_2.54mm:PinSocket_1x07_P2.54mm_Vertical - (place J1 1270000 -1219200 back 90) + (place J1 1270000 -914400 back 90) ) (component promicro:ProMicro - (place U1 1346200 -1054100 front 90) + (place U1 1346200 -1079500 front 90) ) ) (was_is @@ -32,122 +32,116 @@ (network_out (net GND (wire - (path B.Cu 5000 - 1397000 -1205700 - 1397000 -1203918 - 1361482 -1168400 - 1270000 -1168400 + (path F.Cu 5000 + 1397000 -914400 + 1397000 -927900 ) ) (wire (path F.Cu 5000 - 1422400 -1143000 - 1397000 -1168400 - 1397000 -1219200 + 1407495 -1019195 + 1407495 -938395 + 1397000 -927900 ) ) + (via "Via[0-1]_600:400_um" 1407495 -1019195 + ) (wire - (path F.Cu 5000 - 1422400 -1117600 + (path B.Cu 5000 1422400 -1143000 + 1407495 -1128095 + 1407495 -1019195 ) ) (wire - (path B.Cu 5000 - 1397000 -1219200 - 1397000 -1205700 + (path F.Cu 5000 + 1422400 -1143000 + 1422400 -1168400 ) ) ) (net INT (wire (path B.Cu 5000 - 1378372 -1195902 - 1293298 -1195902 - 1270000 -1219200 + 1270000 -914400 + 1272429 -914400 + 1295683 -937654 ) ) - (via "Via[0-1]_600:400_um" 1378372 -1195902 - ) (wire (path F.Cu 5000 - 1422400 -1092200 - 1378372 -1136228 - 1378372 -1195902 + 1422400 -1117600 + 1295683 -990883 + 1295683 -937654 ) ) + (via "Via[0-1]_600:400_um" 1295683 -937654 + ) ) (net SCK (wire (path F.Cu 5000 - 1270000 -990600 - 1294467 -1015067 - 1294467 -1204767 - 1295400 -1205700 + 1295400 -927900 + 1294826 -927900 + 1288180 -934546 + 1288180 -997820 + 1270000 -1016000 ) ) (wire (path F.Cu 5000 - 1295400 -1219200 - 1295400 -1205700 + 1295400 -914400 + 1295400 -927900 ) ) ) (net MOSI - (wire - (path F.Cu 5000 - 1320800 -1205700 - 1301504 -1186404 - 1301504 -1009245 - ) - ) (wire (path B.Cu 5000 - 1270000 -939800 - 1301504 -971304 - 1301504 -1009245 + 1320800 -914400 + 1320800 -927900 ) ) (wire - (path F.Cu 5000 - 1320800 -1219200 - 1320800 -1205700 + (path B.Cu 5000 + 1270000 -965200 + 1283500 -965200 + 1320800 -927900 ) ) - (via "Via[0-1]_600:400_um" 1301504 -1009245 - ) ) (net MISO (wire - (path F.Cu 5000 - 1270000 -965200 - 1346200 -1041400 - 1346200 -1219200 + (path B.Cu 5000 + 1346200 -914400 + 1346200 -927900 ) ) - ) - (net CS (wire - (path F.Cu 5000 - 1422400 -1016000 - 1370869 -1067531 - 1370869 -1204969 - 1371600 -1205700 + (path B.Cu 5000 + 1270000 -990600 + 1332700 -927900 + 1346200 -927900 ) ) + ) + (net CS (wire (path F.Cu 5000 - 1371600 -1219200 - 1371600 -1205700 + 1371600 -914400 + 1371600 -993911 + 1419089 -1041400 + 1422400 -1041400 ) ) ) (net VCC (wire (path B.Cu 5000 - 1270000 -1117600 - 1320800 -1117600 - 1422400 -1219200 + 1270000 -1143000 + 1345110 -1067890 + 1345110 -991690 + 1422400 -914400 ) ) )