-
Notifications
You must be signed in to change notification settings - Fork 7
/
Copy pathturbo9_fetch_queue.v
333 lines (290 loc) · 13.4 KB
/
turbo9_fetch_queue.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
// [TURBO9_HEADER_START]
//////////////////////////////////////////////////////////////////////////////
// Turbo9 Microprocessor IP
//////////////////////////////////////////////////////////////////////////////
// Website: www.turbo9.org
// Contact: team[at]turbo9[dot]org
//////////////////////////////////////////////////////////////////////////////
// [TURBO9_LICENSE_START]
// BSD-1-Clause
//
// Copyright (c) 2020-2023
// Kevin Phillipson
// Michael Rywalt
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS AND CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
// [TURBO9_LICENSE_END]
//////////////////////////////////////////////////////////////////////////////
// Engineer: Kevin Phillipson
// Description: Fetch Queue (8-bit by 4to7 shifting FIFO)
//
//////////////////////////////////////////////////////////////////////////////
// History:
// 07.14.2023 - Kevin Phillipson
// File header added
//
//////////////////////////////////////////////////////////////////////////////
// [TURBO9_HEADER_END]
/////////////////////////////////////////////////////////////////////////////
// MODULE
/////////////////////////////////////////////////////////////////////////////
module turbo9_fetch_queue
#(
parameter TURBO9_TYPE = 0, // Turbo9 Type: 0=Turbo9, 1=Turbo9S, 2=Turbo9R
parameter QUEUE_SIZE = 6 // Fetch Queue Size: 6=Default, 4=Min, 7=Max
)
(
// Inputs: Clock & Reset
input RST_I,
input CLK_I,
input [2:0] QUEUE_RD_LEN_I,
input QUEUE_FLUSH_I,
input QUEUE_WR_EN_I,
input QUEUE_WIDTH_I,
input [15:0] QUEUE_DAT_I,
output [2:0] QUEUE_LEVEL_O,
output [2:0] QUEUE_REJECT_LEN_O,
//
output [7:0] QUEUE_DATA_3_O,
output [7:0] QUEUE_DATA_2_O,
output [7:0] QUEUE_DATA_1_O,
output [7:0] QUEUE_DATA_0_O,
output PREBYTE_EN_O
//
);
/////////////////////////////////////////////////////////////////////////////
// INTERNAL SIGNALS
/////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////// WIDTH_I defines
//
localparam CLOG2_SIZE = 3; // Solve: 2^CLOG2_SIZE >= QUEUE_SIZE (keep it Verilog2001!)
// This must match the MSB of the *_REG_SEL control vectors
localparam WIDTH_16 = 1'b0;
localparam WIDTH_8 = 1'b1;
wire [(CLOG2_SIZE-1):0] size_const = QUEUE_SIZE;
wire [(CLOG2_SIZE-1):0] size_m1_const = QUEUE_SIZE-1;
wire [(QUEUE_SIZE-1):0] queue_wr_en;
wire [(CLOG2_SIZE-1):0] queue_wr_ptr;
reg [(CLOG2_SIZE-1):0] queue_reject_len;
wire [(CLOG2_SIZE-1):0] queue_level_term;
wire [(CLOG2_SIZE-1):0] queue_level_inc;
reg [(CLOG2_SIZE-1):0] queue_level_reg;
wire [(CLOG2_SIZE-1):0] queue_level_nxt;
localparam queue_level_rst = 'd0;
reg prebyte_en_reg;
localparam prebyte_en_rst = 1'b0;
reg [7:0] queue_data_reg [(QUEUE_SIZE-1):0];
wire [7:0] queue_data_nxt [(QUEUE_SIZE-1):0];
localparam queue_data_rst = 'd0;
wire [7:0] queue_data_shift4 [(QUEUE_SIZE-1):0];
wire [7:0] queue_data_shift2 [(QUEUE_SIZE-1):0];
wire [7:0] queue_data_shift1 [(QUEUE_SIZE-1):0];
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// QUEUE LOGIC
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////// Pointer & Level Calculation
//
assign queue_level_term = (QUEUE_WIDTH_I == WIDTH_16) ? 'd2 : 'd1;
//
assign queue_level_inc = (QUEUE_WR_EN_I) ? queue_level_term : 'd0;
assign queue_wr_ptr = QUEUE_FLUSH_I ? 'd0 : queue_level_reg - QUEUE_RD_LEN_I;
assign queue_level_nxt = queue_wr_ptr + queue_level_inc - queue_reject_len;
/////////////////////////////////// Reject Calculation
//
always @* begin
if ((QUEUE_WIDTH_I==WIDTH_16) && (queue_wr_ptr==size_const ) && QUEUE_WR_EN_I)
queue_reject_len = 'd2;
else if ((QUEUE_WIDTH_I==WIDTH_16) && (queue_wr_ptr==size_m1_const) && QUEUE_WR_EN_I)
queue_reject_len = 'd1;
else if ((QUEUE_WIDTH_I==WIDTH_8 ) && (queue_wr_ptr==size_const ) && QUEUE_WR_EN_I)
queue_reject_len = 'd1;
else
queue_reject_len = 'd0;
end
/////////////////////////////////// Write Enables
//
genvar i;
generate
// QUEUE_SIZE = 7 example:
// assign queue_wr_en[0] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd0));
// assign queue_wr_en[1] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd1));
// assign queue_wr_en[2] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd2));
// assign queue_wr_en[3] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd3));
// assign queue_wr_en[4] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd4));
// assign queue_wr_en[5] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd5));
// assign queue_wr_en[6] = (QUEUE_WR_EN_I & (queue_wr_ptr == 'd6));
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_wr_en
assign queue_wr_en[i] = (QUEUE_WR_EN_I & (queue_wr_ptr == i));
end
endgenerate
/////////////////////////////////// Data Barrell Shifter
//
// Shift by 4
generate
// QUEUE_SIZE = 7 example:
// assign queue_data_shift4[0] = QUEUE_RD_LEN_I[2] ? queue_data_reg[4] : queue_data_reg[0];
// assign queue_data_shift4[1] = QUEUE_RD_LEN_I[2] ? queue_data_reg[5] : queue_data_reg[1];
// assign queue_data_shift4[2] = QUEUE_RD_LEN_I[2] ? queue_data_reg[6] : queue_data_reg[2];
// assign queue_data_shift4[3] = queue_data_reg[3];
// assign queue_data_shift4[4] = queue_data_reg[4];
// assign queue_data_shift4[5] = queue_data_reg[5];
// assign queue_data_shift4[6] = queue_data_reg[6];
if (QUEUE_SIZE > 4) begin
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_data_shift_quadplus
if (i<(QUEUE_SIZE-4)) begin
assign queue_data_shift4[i] = QUEUE_RD_LEN_I[CLOG2_SIZE-1] ? queue_data_reg[i+4] : queue_data_reg[i];
end else begin
assign queue_data_shift4[i] = queue_data_reg[i];
end
end
end else begin
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_data_shift_quad
assign queue_data_shift4[i] = queue_data_reg[i];
end
end
endgenerate
//
// Shift by 2
generate
// QUEUE_SIZE = 7 example:
// assign queue_data_shift2[0] = QUEUE_RD_LEN_I[1] ? queue_data_shift4[2] : queue_data_shift4[0];
// assign queue_data_shift2[1] = QUEUE_RD_LEN_I[1] ? queue_data_shift4[3] : queue_data_shift4[1];
// assign queue_data_shift2[2] = QUEUE_RD_LEN_I[1] ? queue_data_shift4[4] : queue_data_shift4[2];
// assign queue_data_shift2[3] = QUEUE_RD_LEN_I[1] ? queue_data_shift4[5] : queue_data_shift4[3];
// assign queue_data_shift2[4] = QUEUE_RD_LEN_I[1] ? queue_data_shift4[6] : queue_data_shift4[4];
// assign queue_data_shift2[5] = queue_data_shift4[5];
// assign queue_data_shift2[6] = queue_data_shift4[6];
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_data_shift_double
if (i<(QUEUE_SIZE-2)) begin
assign queue_data_shift2[i] = QUEUE_RD_LEN_I[CLOG2_SIZE-2] ? queue_data_shift4[i+2] : queue_data_shift4[i];
end else begin
assign queue_data_shift2[i] = queue_data_shift4[i];
end
end
endgenerate
//
// Shift by 1
generate
// QUEUE_SIZE = 7 example:
// assign queue_data_shift1[0] = QUEUE_RD_LEN_I[0] ? queue_data_shift2[1] : queue_data_shift2[0];
// assign queue_data_shift1[1] = QUEUE_RD_LEN_I[0] ? queue_data_shift2[2] : queue_data_shift2[1];
// assign queue_data_shift1[2] = QUEUE_RD_LEN_I[0] ? queue_data_shift2[3] : queue_data_shift2[2];
// assign queue_data_shift1[3] = QUEUE_RD_LEN_I[0] ? queue_data_shift2[4] : queue_data_shift2[3];
// assign queue_data_shift1[4] = QUEUE_RD_LEN_I[0] ? queue_data_shift2[5] : queue_data_shift2[4];
// assign queue_data_shift1[5] = QUEUE_RD_LEN_I[0] ? queue_data_shift2[6] : queue_data_shift2[5];
// assign queue_data_shift1[6] = queue_data_shift2[6];
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_data_shift_single
if (i<(QUEUE_SIZE-1)) begin
assign queue_data_shift1[i] = QUEUE_RD_LEN_I[CLOG2_SIZE-3] ? queue_data_shift2[i+1] : queue_data_shift2[i];
end else begin
assign queue_data_shift1[i] = queue_data_shift2[i];
end
end
endgenerate
/////////////////////////////////// Write Logic
//
generate
if (TURBO9_TYPE == 0) begin // 0:Turbo9, 1:Turbo9S, 2:Turbo9R
//
// Write Enable Logic (8bit)
// assign queue_data_nxt[0] = (queue_wr_en[0]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[0];
// assign queue_data_nxt[1] = (queue_wr_en[1]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[1];
// assign queue_data_nxt[2] = (queue_wr_en[2]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[2];
// assign queue_data_nxt[3] = (queue_wr_en[3]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[3];
// assign queue_data_nxt[4] = (queue_wr_en[4]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[4];
// assign queue_data_nxt[5] = (queue_wr_en[5]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[5];
// assign queue_data_nxt[6] = (queue_wr_en[6]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[6];
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_write_enable
assign queue_data_nxt[i] = (queue_wr_en[i]) ? QUEUE_DAT_I[ 7:0] : queue_data_shift1[i];
end
end else begin
wire [7:0] queue_data_nxt_lo [(QUEUE_SIZE-1):0];
//
// Write Enable Logic (Low Byte)
// assign queue_data_nxt_lo[0] = (queue_wr_en[0]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[0];
// assign queue_data_nxt_lo[1] = (queue_wr_en[1]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[1];
// assign queue_data_nxt_lo[2] = (queue_wr_en[2]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[2];
// assign queue_data_nxt_lo[3] = (queue_wr_en[3]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[3];
// assign queue_data_nxt_lo[4] = (queue_wr_en[4]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[4];
// assign queue_data_nxt_lo[5] = (queue_wr_en[5]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[5];
// assign queue_data_nxt_lo[6] = (queue_wr_en[6]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[6];
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_write_enable_lo
assign queue_data_nxt_lo[i] = (queue_wr_en[i]) ? QUEUE_DAT_I[15:8] : queue_data_shift1[i];
end
//
// Write Enable Logic (High Byte)
// assign queue_data_nxt[0] = queue_data_nxt_lo[0];
// assign queue_data_nxt[1] = (queue_wr_en[0]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[1];
// assign queue_data_nxt[2] = (queue_wr_en[1]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[2];
// assign queue_data_nxt[3] = (queue_wr_en[2]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[3];
// assign queue_data_nxt[4] = (queue_wr_en[3]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[4];
// assign queue_data_nxt[5] = (queue_wr_en[4]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[5];
// assign queue_data_nxt[6] = (queue_wr_en[5]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[6];
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_write_enable_hi
if (i==0) begin
assign queue_data_nxt[i] = queue_data_nxt_lo[i];
end else begin
assign queue_data_nxt[i] = (queue_wr_en[i-1]) ? QUEUE_DAT_I[ 7:0] : queue_data_nxt_lo[i];
end
end
end
endgenerate
//////////////////////////////////a Queue Data Registers
//
generate
for (i=0; i<QUEUE_SIZE; i=i+1) begin: q_data_reg
always @(posedge CLK_I, posedge RST_I) begin
if (RST_I) begin
queue_data_reg[i] <= queue_data_rst;
end else begin
queue_data_reg[i] <= queue_data_nxt[i];
end
end
end
endgenerate
/////////////////////////////////// Level and Prebyte Registers
//
always @(posedge CLK_I, posedge RST_I) begin
if (RST_I) begin
queue_level_reg <= queue_level_rst;
prebyte_en_reg <= prebyte_en_rst;
end else begin
queue_level_reg <= queue_level_nxt;
prebyte_en_reg <= (queue_data_nxt[0][7:1] == 7'b0001_000);
end
end
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// ASSIGN OUTPUTS
/////////////////////////////////////////////////////////////////////////////
//
assign QUEUE_REJECT_LEN_O = queue_reject_len;
assign QUEUE_LEVEL_O = queue_level_reg;
//
assign QUEUE_DATA_3_O = queue_data_reg[3];
assign QUEUE_DATA_2_O = queue_data_reg[2];
assign QUEUE_DATA_1_O = queue_data_reg[1];
assign QUEUE_DATA_0_O = queue_data_reg[0];
assign PREBYTE_EN_O = prebyte_en_reg;
//
/////////////////////////////////////////////////////////////////////////////
endmodule