From dc9e029648dbd6f6e3626d083c2d5dfb294e94ae Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:24:02 +0100 Subject: [PATCH 01/80] settings: expose debug_build config and use_ninja to user --- examples/cfg/llvm.yml | 3 +++ examples/demo.py | 15 ++++++++++----- seal5/flow.py | 18 ++++++++++++------ seal5/pass_list.py | 2 +- seal5/settings.py | 6 +++++- seal5/tools/llvm.py | 4 +++- 6 files changed, 34 insertions(+), 14 deletions(-) diff --git a/examples/cfg/llvm.yml b/examples/cfg/llvm.yml index e250ab4c..690a2615 100644 --- a/examples/cfg/llvm.yml +++ b/examples/cfg/llvm.yml @@ -1,4 +1,7 @@ llvm: + ninja: true # TODO: move to configs + num_threads: -1 # TODO: move to configs + default_config: release configs: release: options: diff --git a/examples/demo.py b/examples/demo.py index a5f886d8..97a89084 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -37,6 +37,8 @@ SKIP_PATTERNS = False # SKIP_PATTERNS = True INTERACTIVE = False +BUILD_CONFIG = "release" +# BUILD_CONFIG = "debug" seal5_flow = Seal5Flow("/tmp/seal5_llvm_demo", "demo") @@ -111,6 +113,9 @@ ] seal5_flow.load(cfg_files, verbose=VERBOSE, overwrite=False) +# Override settings from Python +seal5_flow.settings.llvm.default_config = BUILD_CONFIG + # Clone & install Seal5 dependencies # 1. CDSL2LLVM (add PHASE_0 patches) seal5_flow.setup(force=True, verbose=VERBOSE) @@ -120,7 +125,7 @@ if not FAST: # Build initial LLVM - seal5_flow.build(verbose=VERBOSE, config="release") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) # Transform inputs # 1. Create M2-ISA-R metamodel @@ -136,11 +141,11 @@ if not FAST: # Build patched LLVM - seal5_flow.build(verbose=VERBOSE, config="release") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) if not SKIP_PATTERNS: # Build PatternGen & llc - seal5_flow.build(verbose=VERBOSE, config="release", target="pattern-gen") - seal5_flow.build(verbose=VERBOSE, config="release", target="llc") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="pattern-gen") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="llc") # Generate remaining patches seal5_flow.generate(verbose=VERBOSE, only=["pattern_gen"]) @@ -149,7 +154,7 @@ seal5_flow.patch(verbose=VERBOSE) # Build patched LLVM -seal5_flow.build(verbose=VERBOSE, config="release") +seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) # Test patched LLVM seal5_flow.test(verbose=VERBOSE, ignore_error=True) diff --git a/seal5/flow.py b/seal5/flow.py index 8c8ab106..f933c6df 100644 --- a/seal5/flow.py +++ b/seal5/flow.py @@ -287,7 +287,7 @@ def setup( self.settings.deps_dir / "cdsl2llvm", self.settings.deps_dir / "cdsl2llvm" / "llvm" / "build", cmake_options=cmake_options, - use_ninja=True, + use_ninja=self.settings.llvm.ninja, ) logger.info("Completed build of PatternGen") logger.info("Building llc") @@ -295,7 +295,7 @@ def setup( self.settings.deps_dir / "cdsl2llvm", self.settings.deps_dir / "cdsl2llvm" / "llvm" / "build", cmake_options=cmake_options, - use_ninja=True, + use_ninja=self.settings.llvm.ninja, ) logger.info("Completed build of llc") # input("qqqqqq") @@ -324,7 +324,7 @@ def prepare_environment(self): cdsl2llvm_build_dir = None integrated_pattern_gen = self.settings.tools.pattern_gen.integrated if integrated_pattern_gen: - config = "release" # TODO: fetch default config + config = self.settings.llvm.default_config cdsl2llvm_build_dir = str(self.settings.build_dir / config) else: cdsl2llvm_build_dir = str(self.settings.deps_dir / "cdsl2llvm" / "llvm" / "build") @@ -376,13 +376,19 @@ def load(self, files: List[Path], verbose: bool = False, overwrite: bool = False # TODO: only allow single instr set for now and track inputs in settings logger.info("Completed load of Seal5 inputs") - def build(self, config="release", target="all", verbose: bool = False): + def build(self, config=None, target="all", verbose: bool = False): logger.info("Building Seal5 LLVM (%s)", target) + if config is None: + config = self.settings.llvm.default_config llvm_config = self.settings.llvm.configs.get(config, None) assert llvm_config is not None, f"Invalid llvm config: {config}" cmake_options = llvm_config.options llvm.build_llvm( - Path(self.settings.directory), self.settings.build_dir / config, cmake_options=cmake_options, target=target + Path(self.settings.directory), + self.settings.build_dir / config, + cmake_options=cmake_options, + target=target, + use_ninja=self.settings.llvm.ninja, ) logger.info("Completed build of Seal5 LLVM (%s)", target) @@ -585,7 +591,7 @@ def test( ): logger.info("Testing Seal5 LLVM") if config is None: - config = "debug" if debug else "release" + config = self.settings.llvm.default_config test_paths = self.settings.test.paths failing_tests = llvm.test_llvm( self.directory / "llvm" / "test", self.settings.build_dir / config, test_paths, verbose=verbose diff --git a/seal5/pass_list.py b/seal5/pass_list.py index 21f3ec55..22b99088 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -1171,7 +1171,7 @@ def convert_llvmir_to_gmir( cdsl2llvm_build_dir = None integrated_pattern_gen = settings.tools.pattern_gen.integrated if integrated_pattern_gen: - config = "release" # TODO: fetch default config + config = settings.llvm.default_config cdsl2llvm_build_dir = str(settings.build_dir / config) else: cdsl2llvm_build_dir = str(settings.deps_dir / "cdsl2llvm" / "llvm" / "build") diff --git a/seal5/settings.py b/seal5/settings.py index 2e001942..9e9a0e75 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -89,6 +89,8 @@ }, "llvm": { "state": {"version": "auto", "base_commit": "unknown"}, + "ninja": False, + "default_config": "release", "configs": { "release": { "options": { @@ -469,8 +471,10 @@ class LLVMConfig(YAMLSettings): @dataclass class LLVMSettings(YAMLSettings): - state: Optional[LLVMState] = None + ninja: Optional[bool] = None + default_config: Optional[str] = None configs: Optional[Dict[str, LLVMConfig]] = None + state: Optional[LLVMState] = None @dataclass diff --git a/seal5/tools/llvm.py b/seal5/tools/llvm.py index 0869d808..14cd2f44 100644 --- a/seal5/tools/llvm.py +++ b/seal5/tools/llvm.py @@ -112,7 +112,9 @@ def build_llvm( print_func=logger.info if verbose else logger.debug, live=True, ) - utils.make(target=target, cwd=dest, print_func=logger.info if verbose else logger.debug, live=True) + utils.make( + target=target, cwd=dest, print_func=logger.info if verbose else logger.debug, live=True, use_ninja=use_ninja + ) def test_llvm(base: Path, build_dir: Path, test_paths: List[str] = [], verbose: bool = False): From 62fff51f2a6dd1927716fbfdc9d3fb23ee26636a Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:24:35 +0100 Subject: [PATCH 02/80] examples/cfg/llvm.yml: no not build x86 target --- examples/cfg/llvm.yml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/examples/cfg/llvm.yml b/examples/cfg/llvm.yml index 690a2615..50fd93df 100644 --- a/examples/cfg/llvm.yml +++ b/examples/cfg/llvm.yml @@ -10,7 +10,8 @@ llvm: LLVM_ENABLE_ASSERTIONS: false LLVM_OPTIMIZED_TABLEGEN: true LLVM_ENABLE_PROJECTS: [clang, lld] - LLVM_TARGETS_TO_BUILD: [X86, RISCV] + # LLVM_TARGETS_TO_BUILD: [X86, RISCV] + LLVM_TARGETS_TO_BUILD: [RISCV] release_assertions: options: CMAKE_BUILD_TYPE: Release @@ -18,7 +19,8 @@ llvm: LLVM_ENABLE_ASSERTIONS: true LLVM_OPTIMIZED_TABLEGEN: true LLVM_ENABLE_PROJECTS: [clang, lld] - LLVM_TARGETS_TO_BUILD: [X86, RISCV] + # LLVM_TARGETS_TO_BUILD: [X86, RISCV] + LLVM_TARGETS_TO_BUILD: [RISCV] debug: options: CMAKE_BUILD_TYPE: Debug @@ -26,4 +28,7 @@ llvm: LLVM_ENABLE_ASSERTIONS: true LLVM_OPTIMIZED_TABLEGEN: true LLVM_ENABLE_PROJECTS: [clang, lld] - LLVM_TARGETS_TO_BUILD: [X86, RISCV] + # LLVM_TARGETS_TO_BUILD: [X86, RISCV] + LLVM_TARGETS_TO_BUILD: [RISCV] + LLVM_PARALLEL_LINK_JOBS: 8 + # LLVM_USE_LINKER: lld From 8ee4e929f1fd1178c8f17975f5f14bdca188f253 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:26:05 +0100 Subject: [PATCH 03/80] demo: add prepatched setting --- examples/demo.py | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/examples/demo.py b/examples/demo.py index 97a89084..dcf455cb 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -39,6 +39,8 @@ INTERACTIVE = False BUILD_CONFIG = "release" # BUILD_CONFIG = "debug" +# PREPATCHED = False +PREPATCHED = True seal5_flow = Seal5Flow("/tmp/seal5_llvm_demo", "demo") @@ -50,9 +52,11 @@ # Clone LLVM and init seal5 metadata directory seal5_flow.initialize( clone=True, - clone_url="https://github.com/llvm/llvm-project.git", + clone_url="git@gitlab.lrz.de:de-tum-ei-eda-esl/llvm/core-v-llvm-project.git" + if PREPATCHED + else "https://github.com/llvm/llvm-project.git", # clone_ref="llvmorg-17.0.6", - clone_ref="llvmorg-18.1.0-rc3", + clone_ref="seal5-demo-prepatched" if PREPATCHED else "llvmorg-18.1.0-rc3", force=True, verbose=VERBOSE, ) @@ -121,7 +125,8 @@ seal5_flow.setup(force=True, verbose=VERBOSE) # Apply initial patches -seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_0]) +if not PREPATCHED: + seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_0]) if not FAST: # Build initial LLVM @@ -151,7 +156,7 @@ seal5_flow.generate(verbose=VERBOSE, only=["pattern_gen"]) # Apply patches - seal5_flow.patch(verbose=VERBOSE) + seal5_flow.patch(verbose=VERBOSE, stages=list(range(PatchStage.PHASE_3, PatchStage.PHASE_5 + 1))) # Build patched LLVM seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) From 75c6769f7aa76b18a9107804c67d015aa30c8e15 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:27:24 +0100 Subject: [PATCH 04/80] cdsl writer: fixes --- seal5/backends/coredsl2/writer.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/seal5/backends/coredsl2/writer.py b/seal5/backends/coredsl2/writer.py index ea0cc5db..85f6181e 100644 --- a/seal5/backends/coredsl2/writer.py +++ b/seal5/backends/coredsl2/writer.py @@ -100,18 +100,21 @@ def write_type(self, data_type, size): def write_attribute(self, attr, val=None): if self.needsspace: self.write(" ") + if val is not None: + if isinstance(val, list) and len(val) == 0: + val = None + if self.compat and val is not None: + return self.write("[[") self.write(attr.name.lower()) - if val: + if val is not None: self.write("=") - self.write(val) # TODO: operation + self.write(str(val)) # TODO: operation self.write("]]") # print("key", key) # print("value", value) def write_attributes(self, attributes): - if self.compat: - return for attr, val in attributes.items(): self.write_attribute(attr, val) # input("inp") @@ -199,8 +202,6 @@ def write_instruction_constraints(self, constraints, operands): self.leave_block() def write_operands(self, operands): - if self.compat: - return self.write("operands: ") if len(operands) == 0: self.write_line("{};") From 53a54df8dccfe88b8f047ccad63c0ceff04c9acb Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:30:58 +0100 Subject: [PATCH 05/80] mattr: use +gpr32v by default --- examples/cfg/riscv.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/cfg/riscv.yml b/examples/cfg/riscv.yml index 70f7e95c..7892d612 100644 --- a/examples/cfg/riscv.yml +++ b/examples/cfg/riscv.yml @@ -4,6 +4,7 @@ riscv: features: - m - fast-unaligned-access + - gpr32v legalization: gisel: ops: From e8c8ca1fc43a6ef23a3400d9edbe53a2a3d8f8de Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:32:00 +0100 Subject: [PATCH 06/80] add __repr__ for Seal5Operand --- seal5/model.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/seal5/model.py b/seal5/model.py index 0289c865..39f48539 100644 --- a/seal5/model.py +++ b/seal5/model.py @@ -178,6 +178,9 @@ class Seal5Operand: # TODO: track imm, const? # TODO: helpers (is_float, is_int,...) + def __repr__(self): + return f"{type(self)}({self.name}, ty={self.ty}, attrs={self.attributes})" + @property def attributes(self): ret = self._attributes From a6ab658c484ced4cd6a6fc87db2e632b434e80fc Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:32:41 +0100 Subject: [PATCH 07/80] small fix for gen_set_td --- seal5/pass_list.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/seal5/pass_list.py b/seal5/pass_list.py index 22b99088..bf15da5a 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -1295,7 +1295,6 @@ def gen_set_td( set_name_lower = set_name.lower() patch_name = f"set_td_{set_name}" dest = f"llvm/lib/Target/RISCV/seal5/{set_name}.td" - dest2 = "llvm/lib/Target/RISCV/seal5.td" content = f""" // Includes // {set_name}.td - {set_name_lower}_set_td_includes - INSERTION_START @@ -1308,6 +1307,7 @@ def gen_set_td( ) artifacts.append(file_artifact) content2 = f"// {input_model}\n" + "\n".join([f'include "{inc}"' for inc in includes]) + "\n" + dest2 = "llvm/lib/Target/RISCV/seal5.td" patch_artifact = NamedPatch( dest2, key="seal5_td_includes", @@ -1317,6 +1317,7 @@ def gen_set_td( index_file = settings.temp_dir / f"{input_model}_set_td_index.yml" write_index_yaml(index_file, artifacts, {}, content=True) + patch_name = f"set_td_{input_model}" patch_settings = PatchSettings( name=patch_name, stage=int(PatchStage.PHASE_1), From ec67145aaa489625c597aebafa114e209e58ee91 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:33:23 +0100 Subject: [PATCH 08/80] examples/cfg/llvm.yml: no not build x86 target --- seal5/settings.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/seal5/settings.py b/seal5/settings.py index 9e9a0e75..f8c9c1bc 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -99,7 +99,7 @@ "LLVM_ENABLE_ASSERTIONS": False, "LLVM_OPTIMIZED_TABLEGEN": True, "LLVM_ENABLE_PROJECTS": ["clang", "lld"], - "LLVM_TARGETS_TO_BUILD": ["X86", "RISCV"], + "LLVM_TARGETS_TO_BUILD": ["RISCV"], }, }, "release_assertions": { @@ -109,7 +109,7 @@ "LLVM_ENABLE_ASSERTIONS": True, "LLVM_OPTIMIZED_TABLEGEN": True, "LLVM_ENABLE_PROJECTS": ["clang", "lld"], - "LLVM_TARGETS_TO_BUILD": ["X86", "RISCV"], + "LLVM_TARGETS_TO_BUILD": ["RISCV"], }, }, "debug": { @@ -119,7 +119,7 @@ "LLVM_ENABLE_ASSERTIONS": True, "LLVM_OPTIMIZED_TABLEGEN": True, "LLVM_ENABLE_PROJECTS": ["clang", "lld"], - "LLVM_TARGETS_TO_BUILD": ["X86", "RISCV"], + "LLVM_TARGETS_TO_BUILD": ["RISCV"], }, }, }, From de321291b0b2ea575ab964b792854b10d57757f2 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:35:18 +0100 Subject: [PATCH 09/80] update llvm18 patch --- .../patches/llvm/insert_markers_llvm18.patch | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/seal5/resources/patches/llvm/insert_markers_llvm18.patch b/seal5/resources/patches/llvm/insert_markers_llvm18.patch index 87e224ef..8e4c8f45 100644 --- a/seal5/resources/patches/llvm/insert_markers_llvm18.patch +++ b/seal5/resources/patches/llvm/insert_markers_llvm18.patch @@ -92,6 +92,21 @@ diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.c {"zacas", {1, 0}}, {"zcmop", {0, 2}}, +@@ -213,10 +218,10 @@ static void verifyTables() { + #ifndef NDEBUG + static std::atomic TableChecked(false); + if (!TableChecked.load(std::memory_order_relaxed)) { +- assert(llvm::is_sorted(SupportedExtensions) && +- "Extensions are not sorted by name"); +- assert(llvm::is_sorted(SupportedExperimentalExtensions) && +- "Experimental extensions are not sorted by name"); ++ // assert(llvm::is_sorted(SupportedExtensions) && ++ // "Extensions are not sorted by name"); ++ // assert(llvm::is_sorted(SupportedExperimentalExtensions) && ++ // "Experimental extensions are not sorted by name"); + TableChecked.store(true, std::memory_order_relaxed); + } + #endif diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp From 9a6f11ca600c4e71e4a2974a5216b96c2e61979d Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:36:33 +0100 Subject: [PATCH 10/80] move pattern gen support patch to PASE_0 --- seal5/tools/cdsl2llvm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/tools/cdsl2llvm.py b/seal5/tools/cdsl2llvm.py index 4051afe0..d6d520e6 100644 --- a/seal5/tools/cdsl2llvm.py +++ b/seal5/tools/cdsl2llvm.py @@ -91,7 +91,7 @@ def get_pattern_gen_patches( write_index_yaml(index_file, artifacts, {}, content=True) patch_settings = PatchSettings( name="pattern_gen_support", - stage=int(PatchStage.PHASE_2), + stage=int(PatchStage.PHASE_0), comment="Integrate PatternGen in Seal5 LLVM", index=str(index_file), generated=True, From 4fe35da59051cd724f185ebaac4bce981ca6fa3c Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:37:49 +0100 Subject: [PATCH 11/80] try passing legalizer settings via cmdline --- seal5/tools/cdsl2llvm.py | 1 + 1 file changed, 1 insertion(+) diff --git a/seal5/tools/cdsl2llvm.py b/seal5/tools/cdsl2llvm.py index d6d520e6..7a71e849 100644 --- a/seal5/tools/cdsl2llvm.py +++ b/seal5/tools/cdsl2llvm.py @@ -132,6 +132,7 @@ def run_pattern_gen( if not isinstance(build_dir, Path): build_dir = Path(build_dir) pattern_gen_args = [src] + pattern_gen_args.append("--custom-legalizer-settings=foo") if dest: pattern_gen_args.extend(["-o", str(dest)]) From 2a6dd85a6e44ecaeb0905c27fcabf8b8732a92ef Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 08:39:15 +0100 Subject: [PATCH 12/80] WIP: add seal5 prefix to all instrs (workaround) --- seal5/transform/converter.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/seal5/transform/converter.py b/seal5/transform/converter.py index fe13816b..01bb2aad 100644 --- a/seal5/transform/converter.py +++ b/seal5/transform/converter.py @@ -65,6 +65,10 @@ def main(): for set_name, set_def in sets.items(): logger.info("replacing set %s", set_name) for enc, instr_def in set_def.instructions.items(): + PREFIX = True + if PREFIX: + instr_def.name = f"SEAL5_{instr_def.name}" + instr_def.mnemonic = f"seal5.{instr_def.mnemonic}" set_def.instructions[enc] = seal5_model.Seal5Instruction( instr_def.name, instr_def.attributes, From a059aa2b16e98f788e259e53fe06796a82f221dd Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 19:56:23 +0100 Subject: [PATCH 13/80] demo: expose some options as environment vars --- examples/demo.py | 18 +++++++----------- 1 file changed, 7 insertions(+), 11 deletions(-) diff --git a/examples/demo.py b/examples/demo.py index dcf455cb..5316c237 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -30,17 +30,13 @@ set_log_level(console_level="DEBUG", file_level="DEBUG") EXAMPLES_DIR = Path(os.path.dirname(os.path.realpath(__file__))) -VERBOSE = False -# VERBOSE = True -# FAST = False -FAST = True -SKIP_PATTERNS = False -# SKIP_PATTERNS = True -INTERACTIVE = False -BUILD_CONFIG = "release" -# BUILD_CONFIG = "debug" -# PREPATCHED = False -PREPATCHED = True +# VERBOSE = False +VERBOSE = bool(int(os.environ.get("VERBOSE", 0))) +FAST = bool(int(os.environ.get("FAST", 1))) +SKIP_PATTERNS = bool(int(os.environ.get("SKIP_PATTERNS", 0))) +INTERACTIVE = bool(int(os.environ.get("INTERACTIVE", 0))) +PREPATCHED = bool(int(os.environ.get("PREPATCHED", 1))) +BUILD_CONFIG = os.environ.get("BUILD_CONFIG", "release") seal5_flow = Seal5Flow("/tmp/seal5_llvm_demo", "demo") From a3e06cc1d4ad9e6a7a2cbeaf3ca163252da546ee Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 19:57:36 +0100 Subject: [PATCH 14/80] fix gen_riscv_instr_info_str --- seal5/backends/riscv_instr_info/writer.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/seal5/backends/riscv_instr_info/writer.py b/seal5/backends/riscv_instr_info/writer.py index 7f7df48c..a065d10a 100644 --- a/seal5/backends/riscv_instr_info/writer.py +++ b/seal5/backends/riscv_instr_info/writer.py @@ -182,11 +182,11 @@ def gen_riscv_instr_info_str(instr): assert cls in ["GPR"] pre = cls elif Seal5OperandAttribute.IS_IMM in op.attributes: - assert Seal5OperandAttribute.TY in op.attributes - ty = op.attributes[Seal5OperandAttribute.TY] + assert Seal5OperandAttribute.TYPE in op.attributes + ty = op.attributes[Seal5OperandAttribute.TYPE] assert ty[0] in ["u", "s"] sz = int(ty[1:]) - pre = f"{ty}imm{sz}" + pre = f"{ty[0]}imm{sz}" if Seal5OperandAttribute.INOUT in op.attributes or ( Seal5OperandAttribute.OUT in op.attributes and Seal5OperandAttribute.IN in op.attributes From 9de8792cfad50371516e7316d63522597a9b154b Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 19:58:20 +0100 Subject: [PATCH 15/80] clear filters in flow.settings.reset() --- seal5/settings.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/seal5/settings.py b/seal5/settings.py index f8c9c1bc..01f7617b 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -537,6 +537,14 @@ def reset(self): self.inputs = [] self.metrics = [] # TODO: clear user provided tests! + self.filter = FilterSettings( + sets=FilterSetting(keep=[], drop=[]), + instructions=FilterSetting(keep=[], drop=[]), + aliases=FilterSetting(keep=[], drop=[]), + intrinsics=FilterSetting(keep=[], drop=[]), + opcodes=FilterSetting(keep=[], drop=[]), + encoding_sizes=FilterSetting(keep=[], drop=[]), + ) def save(self, dest: Optional[Path] = None): if dest is None: From 5fb43cd12fa1fb56599cdd7f7146687fe151093a Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 20:04:01 +0100 Subject: [PATCH 16/80] pattern-gen: disable-gisel-legality-check --- seal5/tools/cdsl2llvm.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/tools/cdsl2llvm.py b/seal5/tools/cdsl2llvm.py index 7a71e849..36ca6fd1 100644 --- a/seal5/tools/cdsl2llvm.py +++ b/seal5/tools/cdsl2llvm.py @@ -132,7 +132,7 @@ def run_pattern_gen( if not isinstance(build_dir, Path): build_dir = Path(build_dir) pattern_gen_args = [src] - pattern_gen_args.append("--custom-legalizer-settings=foo") + pattern_gen_args.extend(["-custom-legalizer-settings=foo", "-disable-gisel-legality-check"]) if dest: pattern_gen_args.extend(["-o", str(dest)]) From c06252eb607977443425bf8e0cf9b18082632b37 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Sun, 10 Mar 2024 20:05:06 +0100 Subject: [PATCH 17/80] filter_model: allow regex filters --- seal5/transform/filter_model/filter.py | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/seal5/transform/filter_model/filter.py b/seal5/transform/filter_model/filter.py index e1acbea8..3167e512 100644 --- a/seal5/transform/filter_model/filter.py +++ b/seal5/transform/filter_model/filter.py @@ -8,6 +8,7 @@ """Filter M2-ISA-R/Seal5 metamodel.""" +import re import argparse import logging import pathlib @@ -180,16 +181,25 @@ def opcodes_helper(x): # print("keep", keep_instructions) # print("drop", drop_instructions) # input("456") + # def check_filter(name, keep, drop): + # if drop and keep: + # return name not in drop and name in keep + # elif keep: + # return name in keep + # elif drop: + # return name not in drop + # return True - def check_filter(name, keep, drop): + def check_filter_regex(name, keep, drop): if drop and keep: - return name not in drop and name in keep + return not any(re.compile(expr).match(name) for expr in drop) and any(re.compile(expr).match(name) for expr in keep) elif keep: - return name in keep + return any(re.compile(expr).match(name) for expr in keep) elif drop: - return name not in drop + return not any(re.compile(expr).match(name) for expr in drop) return True + def check_encoding_filter(enc, keep, drop, keep2, drop2): opcode = None size = 0 From 4b93be2fb9b5a4229fd14ddaa9d9e57293ccfac6 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 12:54:42 +0100 Subject: [PATCH 18/80] run pattern_gen using threadpoolexecutor --- seal5/backends/patterngen/writer.py | 18 +++++++++++++++--- seal5/pass_list.py | 5 +++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/seal5/backends/patterngen/writer.py b/seal5/backends/patterngen/writer.py index f34eb30b..25a09200 100644 --- a/seal5/backends/patterngen/writer.py +++ b/seal5/backends/patterngen/writer.py @@ -13,6 +13,7 @@ import logging import pathlib import pickle +from concurrent.futures import ThreadPoolExecutor, as_completed from typing import Union from m2isar.metamodel import arch @@ -38,6 +39,7 @@ def main(): parser.add_argument("--metrics", default=None, help="Output metrics to file") parser.add_argument("--index", default=None, help="Output index to file") parser.add_argument("--ext", type=str, default="td", help="Default file extension (if using --splitted)") + parser.add_argument("--parallel", type=int, default=1, help="How many instructions should be processed in parallel") args = parser.parse_args() # initialize logging @@ -112,7 +114,7 @@ def main(): ext_settings = set_def.settings set_dir = out_path / set_name includes = [] - for instr_def in set_def.instructions.values(): + def process_instrunction(instr_def): metrics["n_instructions"] += 1 input_file = out_path / set_name / f"{instr_def.name}.core_desc" attrs = instr_def.attributes @@ -128,10 +130,10 @@ def main(): skip = True if skip: metrics["n_skipped"] += 1 - continue + return False if not input_file.is_file(): metrics["n_skipped"] += 1 - continue + return False # if args.patterns: out_name = f"{instr_def.name}.{args.ext}" output_file = set_dir / out_name @@ -178,6 +180,16 @@ def main(): except AssertionError: metrics["n_failed"] += 1 # errs.append((insn_name, str(ex))) + return True + with ThreadPoolExecutor(args.parallel) as executor: + futures = [] + for instr_def in set_def.instructions.values(): + future = executor.submit(process_instrunction, instr_def) + futures.append(future) + results = [] + for future in as_completed(futures): + result = future.result + results.append(result) if len(includes) > 0: set_includes_str = "\n".join([f'include "seal5/{inc}"' for inc in includes]) set_includes_artifact_dest = f"llvm/lib/Target/RISCV/seal5/{set_name}.td" diff --git a/seal5/pass_list.py b/seal5/pass_list.py index bf15da5a..38a7b024 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -768,6 +768,7 @@ def convert_behav_to_tablegen( split: bool = True, formats: bool = True, patterns: bool = True, + parallel: bool = False, **kwargs, ): assert split, "TODO" @@ -803,6 +804,10 @@ def convert_behav_to_tablegen( if gen_index_file: index_file = settings.temp_dir / (new_name + "_tblgen_patterns_index.yml") args.extend(["--index", index_file]) + if parallel: + import multiprocessing + num_threads = multiprocessing.cpu_count() + args.extend(["--parallel", num_threads]) utils.python( "-m", "seal5.backends.patterngen.writer", From 2543668ec4b1b771ef2896b4797cd143b16d66db Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 12:55:27 +0100 Subject: [PATCH 19/80] allow gloab file patterns in flow.load() --- seal5/flow.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/seal5/flow.py b/seal5/flow.py index f933c6df..521bbb93 100644 --- a/seal5/flow.py +++ b/seal5/flow.py @@ -19,6 +19,7 @@ """Seal5 Flow API.""" import os import sys +import glob import tarfile from pathlib import Path from typing import Optional, List, Dict, Tuple @@ -362,6 +363,8 @@ def load_cdsl(self, file: Path, verbose: bool = False, overwrite: bool = False): def load(self, files: List[Path], verbose: bool = False, overwrite: bool = False): logger.info("Loading Seal5 inputs") + # Expand glob patterns + files = sum([list(map(Path, glob.glob(str(file)))) for file in files], []) for file in files: logger.info("Processing file: %s", file) ext = file.suffix From ac6cc627c775be68c607856d963ae18536f076cd Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 12:56:35 +0100 Subject: [PATCH 20/80] add stage runtimes to metrics --- seal5/flow.py | 96 +++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 86 insertions(+), 10 deletions(-) diff --git a/seal5/flow.py b/seal5/flow.py index 521bbb93..2cb550da 100644 --- a/seal5/flow.py +++ b/seal5/flow.py @@ -19,6 +19,7 @@ """Seal5 Flow API.""" import os import sys +import time import glob import tarfile from pathlib import Path @@ -220,6 +221,8 @@ def initialize( verbose: bool = False, ): logger.info("Initializing Seal5") + start = time.time() + metrics = {} sha = None if not self.directory.is_dir(): if clone is False and not utils.ask_user("Clone LLVM repository?", default=False, interactive=interactive): @@ -251,6 +254,11 @@ def initialize( self.settings.save() set_log_file(self.settings.log_file_path) set_log_level(console_level=self.settings.logging.console.level, file_level=self.settings.logging.file.level) + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"initialize": metrics}) + self.settings.save() logger.info("Completed initialization of Seal5") def setup( @@ -260,6 +268,8 @@ def setup( verbose: bool = False, ): logger.info("Installing Seal5 dependencies") + start = time.time() + metrics = {} logger.info("Cloning CDSL2LLVM") # cdsl2llvm_dependency.clone(self.settings.deps_dir / "cdsl2llvm", overwrite=force, depth=1) cdsl2llvm_dependency.clone(self.settings.deps_dir / "cdsl2llvm", overwrite=force) @@ -300,6 +310,11 @@ def setup( ) logger.info("Completed build of llc") # input("qqqqqq") + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"setup": metrics}) + self.settings.save() logger.info("Completed installation of Seal5 dependencies") def load_cfg(self, file: Path, overwrite: bool = False): @@ -381,6 +396,8 @@ def load(self, files: List[Path], verbose: bool = False, overwrite: bool = False def build(self, config=None, target="all", verbose: bool = False): logger.info("Building Seal5 LLVM (%s)", target) + start = time.time() + metrics = {} if config is None: config = self.settings.llvm.default_config llvm_config = self.settings.llvm.configs.get(config, None) @@ -393,10 +410,17 @@ def build(self, config=None, target="all", verbose: bool = False): target=target, use_ninja=self.settings.llvm.ninja, ) + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"build": metrics}) + self.settings.save() logger.info("Completed build of Seal5 LLVM (%s)", target) def transform(self, verbose: bool = False, skip: Optional[List[str]] = None, only: Optional[List[str]] = None): logger.info("Tranforming Seal5 models") + start = time.time() + metrics = {"passes": []} passes_settings = self.settings.passes assert passes_settings is not None assert passes_settings.defaults is not None @@ -415,26 +439,36 @@ def transform(self, verbose: bool = False, skip: Optional[List[str]] = None, onl with PassManager("transform_passes", transform_passes, skip=skip, only=only) as pm: result = pm.run(input_models, settings=self.settings, env=self.prepare_environment(), verbose=verbose) if result: - metrics = result.metrics - if metrics: - self.settings.metrics.append({pm.name: metrics}) - self.settings.save() - + metrics_ = result.metrics + if metrics_: + metrics["passes"].append({pm.name: metrics_}) + + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"transform": metrics}) + self.settings.save() logger.info("Completed tranformation of Seal5 models") def generate(self, verbose: bool = False, skip: Optional[List[str]] = None, only: Optional[List[str]] = None): logger.info("Generating Seal5 patches") + start = time.time() + metrics = {"passes": []} generate_passes = filter_passes(self.passes, pass_type=PassType.GENERATE) # TODO: User, Global, PerInstr input_models = self.settings.model_names with PassManager("generate_passes", generate_passes, skip=skip, only=only) as pm: result = pm.run(input_models, settings=self.settings, env=self.prepare_environment(), verbose=verbose) if result: - metrics = result.metrics - if metrics: - self.settings.metrics.append({pm.name: metrics}) - self.settings.save() - + metrics_ = result.metrics + if metrics_: + metrics["passes"].append({pm.name: metrics_}) + + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"generate": metrics}) + self.settings.save() logger.info("Completed generation of Seal5 patches") # def collect_patches(self, stage: Optional[PatchStage]): @@ -574,6 +608,8 @@ def apply_patch(self, patch: PatchSettings, force: bool = False): def patch(self, verbose: bool = False, stages: List[PatchStage] = None, force: bool = False): logger.info("Applying Seal5 patches") + start = time.time() + metrics = {} if stages is None: stages = list(map(PatchStage, range(PatchStage.PHASE_5 + 1))) assert len(stages) > 0 @@ -587,12 +623,19 @@ def patch(self, verbose: bool = False, stages: List[PatchStage] = None, force: b # skipping continue self.apply_patch(patch, force=force) + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"patch": metrics}) + self.settings.save() logger.info("Completed application of Seal5 patches") def test( self, debug: bool = False, verbose: bool = False, ignore_error: bool = False, config: Optional[str] = None ): logger.info("Testing Seal5 LLVM") + start = time.time() + metrics = {} if config is None: config = self.settings.llvm.default_config test_paths = self.settings.test.paths @@ -603,14 +646,28 @@ def test( logger.error("%d tests failed: %s", len(failing_tests), ", ".join(failing_tests)) if not ignore_error: raise RuntimeError("Tests failed!") + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"test": metrics}) + self.settings.save() logger.info("Completed test of Seal5 LLVM") def deploy(self, verbose: bool = False): logger.info("Deploying Seal5 LLVM") + start = time.time() + metrics = {} + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"deploy": metrics}) + self.settings.save() logger.info("Completed deployment of Seal5 LLVM") def export(self, dest: Path, verbose: bool = False): logger.info("Exporting Seal5 artifacts") + start = time.time() + metrics = {} if isinstance(dest, str): dest = Path(dest) suffix = dest.suffix @@ -636,14 +693,26 @@ def export(self, dest: Path, verbose: bool = False): elif artifact.is_dir(): archive.add(artifact, arcname=name, recursive=True) + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"export": metrics}) + self.settings.save() logger.info("Completed export of Seal5 artifacts") def reset(self, settings: bool = True, verbose: bool = False, interactive: bool = False): logger.info("Cleaning Seal5 state") + start = time.time() + metrics = {} if interactive: raise NotImplementedError if settings: self.settings.reset() + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"reset": metrics}) + self.settings.save() logger.info("Completed clean of Seal5 settings") def clean( @@ -660,6 +729,8 @@ def clean( interactive: bool = False, ): logger.info("Cleaning Seal5 directories") + start = time.time() + metrics = {} to_clean = [] if temp: to_clean.append(self.settings.temp_dir) @@ -682,4 +753,9 @@ def clean( for path in to_clean: utils.clean_path(path, interactive=interactive) # self.reset(verbose=verbose, interactive=interactive) + end = time.time() + diff = end - start + metrics["time_s"] = diff + self.settings.metrics.append({"clean": metrics}) + self.settings.save() logger.info("Completed clean of Seal5 directories") From 74897d44382529c7a97d073d488c30365e1b1085 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 12:58:13 +0100 Subject: [PATCH 21/80] rename test files --- examples/tests/xcorev/cv_abs.inline_asm.c | 9 +++++++++ examples/tests/xcorev/cv_abs.test.c | 9 --------- examples/tests/xcorev/cv_mac.inline_asm.c | 9 +++++++++ examples/tests/xcorev/cv_mac.test.c | 9 --------- 4 files changed, 18 insertions(+), 18 deletions(-) create mode 100644 examples/tests/xcorev/cv_abs.inline_asm.c delete mode 100644 examples/tests/xcorev/cv_abs.test.c create mode 100644 examples/tests/xcorev/cv_mac.inline_asm.c delete mode 100644 examples/tests/xcorev/cv_mac.test.c diff --git a/examples/tests/xcorev/cv_abs.inline_asm.c b/examples/tests/xcorev/cv_abs.inline_asm.c new file mode 100644 index 00000000..4713e421 --- /dev/null +++ b/examples/tests/xcorev/cv_abs.inline_asm.c @@ -0,0 +1,9 @@ +// RUN: %clang --target=riscv32 -march=rv32ixcorevalu -c -o %t.o %s +// RUN: llvm-objdump --disassembler-options=numeric -d %t.o | FileCheck %s + +int main() { + // CHECK: 0b 90 1a 01 seal5.cv.abs x1, x2 + asm("seal5.cv.abs x1, x2"); + + return 0; +} diff --git a/examples/tests/xcorev/cv_abs.test.c b/examples/tests/xcorev/cv_abs.test.c deleted file mode 100644 index 0a48c221..00000000 --- a/examples/tests/xcorev/cv_abs.test.c +++ /dev/null @@ -1,9 +0,0 @@ -// RUN: %clang --target=riscv32 -march=rv32ixs4emac -c -o %t.o %s -// RUN: llvm-objdump --disassembler-options=numeric -d %t.o | FileCheck %s - -int main() { - // CHECK: 0b 90 1a 01 cv.abs x1, x2 - asm("cv.abs x1, x2"); - - return 0; -} diff --git a/examples/tests/xcorev/cv_mac.inline_asm.c b/examples/tests/xcorev/cv_mac.inline_asm.c new file mode 100644 index 00000000..72e85601 --- /dev/null +++ b/examples/tests/xcorev/cv_mac.inline_asm.c @@ -0,0 +1,9 @@ +// RUN: %clang --target=riscv32 -march=rv32xcorevmac -c -o %t.o %s +// RUN: llvm-objdump --disassembler-options=numeric -d %t.o | FileCheck %s + +int main() { + // CHECK: 0b 90 1a 01 seal5.cv.mac x1, x2, x3 + asm("seal5.cv.mac x1, x2, x3"); + + return 0; +} diff --git a/examples/tests/xcorev/cv_mac.test.c b/examples/tests/xcorev/cv_mac.test.c deleted file mode 100644 index 0505648e..00000000 --- a/examples/tests/xcorev/cv_mac.test.c +++ /dev/null @@ -1,9 +0,0 @@ -// RUN: %clang --target=riscv32 -march=rv32ixs4emac -c -o %t.o %s -// RUN: llvm-objdump --disassembler-options=numeric -d %t.o | FileCheck %s - -int main() { - // CHECK: 0b 90 1a 01 cv.mac x1, x2, x3 - asm("cv.mac x1, x2, x3"); - - return 0; -} From 06024019d7a8ad580110dfdf0d988dbe51223fb4 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 12:59:29 +0100 Subject: [PATCH 22/80] filter_model: allow regex filters 2 --- examples/cfg/filter.yml | 2 +- seal5/transform/filter_model/filter.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/cfg/filter.yml b/examples/cfg/filter.yml index 653009a0..b49612cb 100644 --- a/examples/cfg/filter.yml +++ b/examples/cfg/filter.yml @@ -7,7 +7,7 @@ filter: # drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode, RV32Zpsfoperand] instructions: # keep: [CV_ABS, CV_ADD_B] - drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU] + drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU, SEAL5_CV_SHUFFLE2_B, SEAL5_CV_SHUFFLE2_H, ".*_(SC|SCI)_.*"] opcodes: keep: [custom-0, custom-1, custom-2 ,custom-3, 0b00000, OP-P, OP] encoding_sizes: diff --git a/seal5/transform/filter_model/filter.py b/seal5/transform/filter_model/filter.py index 3167e512..3e223b2f 100644 --- a/seal5/transform/filter_model/filter.py +++ b/seal5/transform/filter_model/filter.py @@ -236,13 +236,13 @@ def check_encoding_filter(enc, keep, drop, keep2, drop2): return True model["sets"] = { - set_name: set_def for set_name, set_def in model["sets"].items() if check_filter(set_name, keep_sets, drop_sets) + set_name: set_def for set_name, set_def in model["sets"].items() if check_filter_regex(set_name, keep_sets, drop_sets) } for set_name, set_def in model["sets"].items(): set_def.instructions = { key: instr_def for key, instr_def in set_def.instructions.items() - if check_filter(instr_def.name, keep_instructions, drop_instructions) + if check_filter_regex(instr_def.name, keep_instructions, drop_instructions) and check_encoding_filter( instr_def.encoding, keep_opcodes, drop_opcodes, keep_encoding_sizes, drop_encoding_sizes ) From 378e7db069fdf87515f75f68efbee2bf83d06522 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 13:00:04 +0100 Subject: [PATCH 23/80] add sha256 examples --- examples/cdsl/rv_tumeda/OpenASIP.core_desc | 216 ++++++++++++++++++ .../cdsl/rv_tumeda/OpenASIP.core_desc.old | 208 +++++++++++++++++ examples/cfg/riscv.yml | 3 + examples/demo.py | 3 +- 4 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 examples/cdsl/rv_tumeda/OpenASIP.core_desc create mode 100644 examples/cdsl/rv_tumeda/OpenASIP.core_desc.old diff --git a/examples/cdsl/rv_tumeda/OpenASIP.core_desc b/examples/cdsl/rv_tumeda/OpenASIP.core_desc new file mode 100644 index 00000000..cc848ac4 --- /dev/null +++ b/examples/cdsl/rv_tumeda/OpenASIP.core_desc @@ -0,0 +1,216 @@ +import "../rv_base/RV32I.core_desc" + +InstructionSet XISE extends RV32I { + // functions { + // unsigned<32> rotl32(unsigned<32> x, unsigned<32> n) { + // return (x << n) | (x >> (32 - n)) + // // return (x << n) | (x >> (-(n)&31)) + // } + // unsigned<32> rotr32(unsigned<32> x, unsigned<32> n) { + // return (x >> n) | (x << (32 - n)) + // // return (x >> n) | (x << (-(n)&31)) + // } + // } + instructions { + AES283XOR { + // opcode: custom-0 + encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.aes283xor", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + unsigned<32> input = X[rs1]; + unsigned<32> temp = input << 1; + X[rd] = ((input >> 7) == 1) ? (temp ^ 283) : temp; + } + } + } + AES283XORB { + // opcode: custom-0 + encoding: 7'b0000001 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.aes283xorb", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + unsigned<32> input = X[rs1]; + unsigned<32> temp = input << 1; + X[rd] = ((input >> 8) == 1) ? (temp ^ 283) : temp; + } + } + } + // REFLECT8 { + // // opcode: custom-0 + // encoding: 7'b0000010 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + // assembly: {"oa.reflect8", "{name(rd)}, {name(rs1)}"}; + // behavior: { + // if (rd != 0) { + // // unsigned<8> input = X[rs1][7:0]; + // // TODO: try loop variant (evantually with automatic unrolling) + // // TODO: try concat (::) version + // // TODO: try 8 bit slice + // X[rd][0] = X[rs1][7]; + // X[rd][1] = X[rs1][6]; + // X[rd][2] = X[rs1][5]; + // X[rd][3] = X[rs1][4]; + // X[rd][4] = X[rs1][3]; + // X[rd][5] = X[rs1][2]; + // X[rd][6] = X[rs1][1]; + // X[rd][7] = X[rs1][0]; + // } + // } + // } + // REFLECT32 { + // // opcode: custom-0 + // encoding: 7'b0000011 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + // assembly: {"oa.reflect32", "{name(rd)}, {name(rs1)}"}; + // behavior: { + // if (rd != 0) { + // // TODO: try loop variant (evantually with automatic unrolling) + // // TODO: try concat (::) version + // X[rd][0] = X[rs1][31]; + // X[rd][1] = X[rs1][30]; + // X[rd][2] = X[rs1][29]; + // X[rd][3] = X[rs1][28]; + // X[rd][4] = X[rs1][27]; + // X[rd][5] = X[rs1][26]; + // X[rd][6] = X[rs1][25]; + // X[rd][7] = X[rs1][24]; + // X[rd][8] = X[rs1][23]; + // X[rd][9] = X[rs1][22]; + // X[rd][10] = X[rs1][21]; + // X[rd][11] = X[rs1][20]; + // X[rd][12] = X[rs1][19]; + // X[rd][13] = X[rs1][18]; + // X[rd][14] = X[rs1][17]; + // X[rd][15] = X[rs1][16]; + // X[rd][16] = X[rs1][15]; + // X[rd][17] = X[rs1][14]; + // X[rd][18] = X[rs1][13]; + // X[rd][19] = X[rs1][12]; + // X[rd][20] = X[rs1][11]; + // X[rd][21] = X[rs1][10]; + // X[rd][22] = X[rs1][9]; + // X[rd][23] = X[rs1][8]; + // X[rd][24] = X[rs1][7]; + // X[rd][25] = X[rs1][6]; + // X[rd][26] = X[rs1][5]; + // X[rd][27] = X[rs1][4]; + // X[rd][28] = X[rs1][3]; + // X[rd][29] = X[rs1][2]; + // X[rd][30] = X[rs1][1]; + // X[rd][31] = X[rs1][0]; + // } + // } + // } + SHA256SIG0 { + // opcode: custom-0 + encoding: 7'b0000100 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig0", "{name(rd)}, {name(rs1)}"}; + behavior: { + // TODO: try with inlining or intrinsic detection + if (rd != 0) { + // X[rd] = rotr32(X[rs1], 7) ^ rotr32(X[rs1], 18) ^ (X[rs1] >> 3); + X[rd] = ((X[rs1] >> 7) | (X[rs1] << 25)) ^ ((X[rs1] >> 18) | (X[rs1] << 14)) ^ (X[rs1] >> 3); + } + } + } + SHA256SIG1 { + // opcode: custom-0 + encoding: 7'b0000101 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig1", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // X[rd] = rotr32(X[rs1], 17) ^ rotr32(X[rs1], 19) ^ (X[rs1] >> 10); + X[rd] = ((X[rs1] >> 17) | (X[rs1] << 15)) ^ ((X[rs1] >> 19) | (X[rs1] << 13)) ^ (X[rs1] >> 10); + } + } + } + SHA256SUM0 { + // opcode: custom-0 + encoding: 7'b0000110 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum0", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // X[rd] = rotr32(X[rs1], 2) ^ rotr32(X[rs1], 13) ^ rotr32(X[rs1], 22); + X[rd] = ((X[rs1] >> 2) | (X[rs1] << 30)) ^ ((X[rs1] >> 13) | (X[rs1] << 19)) ^ ((X[rs1] >> 22) | (X[rs1] << 10)); + } + } + } + SHA256SUM1 { + // opcode: custom-0 + encoding: 7'b0000111 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum1", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // X[rd] = rotr32(X[rs1], 6) ^ rotr32(X[rs1], 11) ^ rotr32(X[rs1], 25); + X[rd] = ((X[rs1] >> 6) | (X[rs1] << 26)) ^ ((X[rs1] >> 11) | (X[rs1] << 21)) ^ ((X[rs1] >> 25) | (X[rs1] << 7)); + } + } + } + SHA256SIG0B { + // opcode: custom-0 + encoding: 7'b0001000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig0b", "{name(rd)}, {name(rs1)}"}; + behavior: { + // TODO: try with inlining or intrinsic detection + if (rd != 0) { + // X[rd] = rotl32(X[rs1], 25) ^ rotl32(X[rs1], 14) ^ (X[rs1] >> 3); + X[rd] = ((X[rs1] << 25) | (X[rs1] >> 7)) ^ ((X[rs1] << 14) | (X[rs1] >> 18)) ^ (X[rs1] >> 3); + } + } + } + SHA256SIG1B { + // opcode: custom-0 + encoding: 7'b0001001 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig1b", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // X[rd] = rotl32(X[rs1], 15) ^ rotl32(X[rs1], 13) ^ (X[rs1] >> 10); + X[rd] = ((X[rs1] << 15) | (X[rs1] >> 17)) ^ ((X[rs1] << 13) | (X[rs1] >> 19)) ^ (X[rs1] >> 10); + } + } + } + SHA256SUM0B { + // opcode: custom-0 + encoding: 7'b0001010 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum0b", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // X[rd] = rotl32(X[rs1], 30) ^ rotl32(X[rs1], 19) ^ rotl32(X[rs1], 10); + X[rd] = ((X[rs1] << 30) | (X[rs1] >> 2)) ^ ((X[rs1] << 19) | (X[rs1] >> 13)) ^ ((X[rs1] << 10) | (X[rs1] >> 12)); + } + } + } + SHA256SUM1B { + // opcode: custom-0 + encoding: 7'b0001011 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum1b", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // X[rd] = rotl32(X[rs1], 26) ^ rotl32(X[rs1], 21) ^ rotl32(X[rs1], 7); + X[rd] = ((X[rs1] << 26) | (X[rs1] >> 6)) ^ ((X[rs1] << 21) | (X[rs1] >> 11)) ^ ((X[rs1] << 7) | (X[rs1] >> 25)); + } + } + } + ROTL32 { + // opcode: custom-0 + encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.rotl32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: { + if (rd != 0) { + // X[rd] = (X[rs1] << X[rs2]) | (X[rs1] >> (32 - X[rs2])); + X[rd] = (X[rs1] << X[rs2][4:0]) | (X[rs1] >> (32 - X[rs2][4:0])); + } + } + } + ROTR32 { + // opcode: custom-0 + encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.rotr32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: { + if (rd != 0) { + // X[rd] = (X[rs1] >> X[rs2]) | (X[rs1] << (32 - X[rs2])); + X[rd] = (X[rs1] >> X[rs2][4:0]) | (X[rs1] << (32 - X[rs2][4:0])); + } + } + } + } +} diff --git a/examples/cdsl/rv_tumeda/OpenASIP.core_desc.old b/examples/cdsl/rv_tumeda/OpenASIP.core_desc.old new file mode 100644 index 00000000..267d91fa --- /dev/null +++ b/examples/cdsl/rv_tumeda/OpenASIP.core_desc.old @@ -0,0 +1,208 @@ +import "../rv_base/RV32I.core_desc" + +InstructionSet XISE extends RV32I { + // functions { + // unsigned<32> rotl32(unsigned<32> x, unsigned<32> n) { + // return (x << n) | (x >> (32 - n)); + // // return (x << n) | (x >> (-(n)&31)); + // } + // unsigned<32> rotr32(unsigned<32> x, unsigned<32> n) { + // return (x >> n) | (x << (32 - n)); + // // return (x >> n) | (x << (-(n)&31)); + // } + // } + instructions { + AES283XOR { + // opcode: custom-0 + encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.aes283xor", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + unsigned<32> input = X[rs1]; + unsigned<32> temp = input << 1; + X[rd] = ((input >> 7) == 1) ? (temp ^ 283) : temp; + } + } + } + AES283XORB { + // opcode: custom-0 + encoding: 7'b0000001 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.aes283xorb", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + unsigned<32> input = X[rs1]; + unsigned<32> temp = input << 1; + X[rd] = ((input >> 8) == 1) ? (temp ^ 283) : temp; + } + } + } + REFLECT8 { + // opcode: custom-0 + encoding: 7'b0000010 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.reflect8", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // unsigned<8> input = X[rs1][7:0]; + // TODO: try loop variant (evantually with automatic unrolling) + // TODO: try concat (::) version + // TODO: try 8 bit slice + X[rd][0] = X[rs1][7]; + X[rd][1] = X[rs1][6]; + X[rd][2] = X[rs1][5]; + X[rd][3] = X[rs1][4]; + X[rd][4] = X[rs1][3]; + X[rd][5] = X[rs1][2]; + X[rd][6] = X[rs1][1]; + X[rd][7] = X[rs1][0]; + } + } + } + REFLECT32 { + // opcode: custom-0 + encoding: 7'b0000011 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.reflect32", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + // TODO: try loop variant (evantually with automatic unrolling) + // TODO: try concat (::) version + X[rd][0] = X[rs1][31]; + X[rd][1] = X[rs1][30]; + X[rd][2] = X[rs1][29]; + X[rd][3] = X[rs1][28]; + X[rd][4] = X[rs1][27]; + X[rd][5] = X[rs1][26]; + X[rd][6] = X[rs1][25]; + X[rd][7] = X[rs1][24]; + X[rd][8] = X[rs1][23]; + X[rd][9] = X[rs1][22]; + X[rd][10] = X[rs1][21]; + X[rd][11] = X[rs1][20]; + X[rd][12] = X[rs1][19]; + X[rd][13] = X[rs1][18]; + X[rd][14] = X[rs1][17]; + X[rd][15] = X[rs1][16]; + X[rd][16] = X[rs1][15]; + X[rd][17] = X[rs1][14]; + X[rd][18] = X[rs1][13]; + X[rd][19] = X[rs1][12]; + X[rd][20] = X[rs1][11]; + X[rd][21] = X[rs1][10]; + X[rd][22] = X[rs1][9]; + X[rd][23] = X[rs1][8]; + X[rd][24] = X[rs1][7]; + X[rd][25] = X[rs1][6]; + X[rd][26] = X[rs1][5]; + X[rd][27] = X[rs1][4]; + X[rd][28] = X[rs1][3]; + X[rd][29] = X[rs1][2]; + X[rd][30] = X[rs1][1]; + X[rd][31] = X[rs1][0]; + } + } + } + SHA256SIG0 { + // opcode: custom-0 + encoding: 7'b0000100 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig0", "{name(rd)}, {name(rs1)}"}; + behavior: { + // TODO: try with inlining or intrinsic detection + if (rd != 0) { + X[rd] = rotr32(X[rs1], 7) ^ rotr32(X[rs1], 18) ^ (X[rs1] >> 3); + } + } + } + SHA256SIG1 { + // opcode: custom-0 + encoding: 7'b0000101 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig1", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + X[rd] = rotr32(X[rs1], 17) ^ rotr32(X[rs1], 19) ^ (X[rs1] >> 10); + } + } + } + SHA256SUM0 { + // opcode: custom-0 + encoding: 7'b0000110 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum0", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + X[rd] = rotr32(X[rs1], 2) ^ rotr32(X[rs1], 13) ^ rotr32(X[rs1], 22); + } + } + } + SHA256SUM1 { + // opcode: custom-0 + encoding: 7'b0000111 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum1", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + X[rd] = rotr32(X[rs1], 6) ^ rotr32(X[rs1], 11) ^ rotr32(X[rs1], 25); + } + } + } + SHA256SIG0B { + // opcode: custom-0 + encoding: 7'b0001000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig0b", "{name(rd)}, {name(rs1)}"}; + behavior: { + // TODO: try with inlining or intrinsic detection + if (rd != 0) { + X[rd] = rotl32(X[rs1], 25) ^ rotl32(X[rs1], 14) ^ (X[rs1] >> 3); + } + } + } + SHA256SIG1B { + // opcode: custom-0 + encoding: 7'b0001001 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sig1b", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + X[rd] = rotl32(X[rs1], 15) ^ rotl32(X[rs1], 13) ^ (X[rs1] >> 10); + } + } + } + SHA256SUM0B { + // opcode: custom-0 + encoding: 7'b0001010 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum0b", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + X[rd] = rotl32(X[rs1], 30) ^ rotl32(X[rs1], 19) ^ rotl32(X[rs1], 10); + } + } + } + SHA256SUM1B { + // opcode: custom-0 + encoding: 7'b0001011 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.sha256sum1b", "{name(rd)}, {name(rs1)}"}; + behavior: { + if (rd != 0) { + X[rd] = rotl32(X[rs1], 26) ^ rotl32(X[rs1], 21) ^ rotl32(X[rs1], 7); + } + } + } + ROTL32 { + // opcode: custom-0 + encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.rotl32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: { + if (rd != 0) { + // X[rd] = (X[rs1] << X[rs2]) | (X[rs1] >> (32 - X[rs2])); + X[rd] = (X[rs1] << X[rs2][4:0]) | (X[rs1] >> (32 - X[rs2][4:0])); + } + } + } + ROTR32 { + // opcode: custom-0 + encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0001011; + assembly: {"oa.rotr32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: { + if (rd != 0) { + // X[rd] = (X[rs1] >> X[rs2]) | (X[rs1] << (32 - X[rs2])); + X[rd] = (X[rs1] >> X[rs2][4:0]) | (X[rs1] << (32 - X[rs2][4:0])); + } + } + } + } +} diff --git a/examples/cfg/riscv.yml b/examples/cfg/riscv.yml index 7892d612..d604f3f7 100644 --- a/examples/cfg/riscv.yml +++ b/examples/cfg/riscv.yml @@ -36,6 +36,9 @@ riscv: # onlyif: [HasExtRV32Zbpo] # # TODO: RV32Zpsfoperand (register pairs) # TODO: G_BITCAST + # - name: [G_ROTL, G_ROTR] + # types: [s32] + # onlyif: [HasExtXISE] transform_info: shouldFoldTerminatingConditionAfterLSR: true prefersVectorizedAddressing: false diff --git a/examples/demo.py b/examples/demo.py index 5316c237..45614ac3 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -63,7 +63,7 @@ EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMac.core_desc", EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVAlu.core_desc", # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBitmanip.core_desc", - # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVSimd.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVSimd.core_desc", # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMem.core_desc", # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBranchImmediate.core_desc", # RVP (will not work) @@ -73,6 +73,7 @@ # EXAMPLES_DIR / "cdsl" / "rv_s4e" / "s4e-mac.core_desc", # TUMEDA (untested) EXAMPLES_DIR / "cdsl" / "rv_tumeda" / "XCoreVNand.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_tumeda" / "OpenASIP.core_desc", # GENERATED (untested) EXAMPLES_DIR / "cdsl" / "rv_gen" / "test.core_desc", # OTHERS (untested) From b5cf73da5c77a02214b5808df401330a658b1a76 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 11 Mar 2024 13:00:37 +0100 Subject: [PATCH 24/80] clear pass settings in flow.reset() --- seal5/settings.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/seal5/settings.py b/seal5/settings.py index 01f7617b..15389f20 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -545,6 +545,14 @@ def reset(self): opcodes=FilterSetting(keep=[], drop=[]), encoding_sizes=FilterSetting(keep=[], drop=[]), ) + self.passes = PassesSettings( + defaults=PassesSetting( + skip=[], + only=[], + overrides={}, + ), + per_model={}, + ) def save(self, dest: Optional[Path] = None): if dest is None: From 390ffbd6ffb4216be8702563d36816955d4d7c74 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:51:52 +0100 Subject: [PATCH 25/80] detect_inouts: fix bug in ternary visitor --- seal5/transform/detect_inouts/visitor.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/transform/detect_inouts/visitor.py b/seal5/transform/detect_inouts/visitor.py index 82438c60..af504e92 100644 --- a/seal5/transform/detect_inouts/visitor.py +++ b/seal5/transform/detect_inouts/visitor.py @@ -134,9 +134,9 @@ def loop(self: behav.Loop, context): def ternary(self: behav.Ternary, context): context.is_read = True self.cond = self.cond.generate(context) - context.is_read = False self.then_expr = self.then_expr.generate(context) self.else_expr = self.else_expr.generate(context) + context.is_read = False return self From 458f7d56a09227fe2a7c6fa600a6a56d3ad13af5 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:52:21 +0100 Subject: [PATCH 26/80] convert_behav_to_tablegen: fix --- seal5/pass_list.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/pass_list.py b/seal5/pass_list.py index 38a7b024..15a1dd90 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -807,7 +807,7 @@ def convert_behav_to_tablegen( if parallel: import multiprocessing num_threads = multiprocessing.cpu_count() - args.extend(["--parallel", num_threads]) + args.extend(["--parallel", str(num_threads)]) utils.python( "-m", "seal5.backends.patterngen.writer", From 2391f5e7ee4f9ec7e9e9dd57d2290061f184cc2d Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:52:57 +0100 Subject: [PATCH 27/80] Seal5Pass: actually use user-provided overrides --- seal5/passes.py | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/seal5/passes.py b/seal5/passes.py index 54d5db98..a254b52a 100644 --- a/seal5/passes.py +++ b/seal5/passes.py @@ -88,11 +88,19 @@ def skip(self): def run(self, inputs: List[str], *args, settings: Optional[Seal5Settings] = None, **kwargs): logger.debug("Running pass: %s", self) self.status = PassStatus.RUNNING + assert settings is not None + passes_settings = settings.passes + assert passes_settings is not None + assert passes_settings.defaults is not None + assert passes_settings.defaults.overrides is not None + default_overrides = passes_settings.defaults.overrides.get(self.name, None) self.metrics["models"] = [] try: kwargs_ = {**kwargs} if self.options: kwargs_.update(self.options) + if default_overrides: + kwargs_.update(default_overrides) start = time.time() parent = kwargs.get("parent", None) if parent: @@ -100,9 +108,6 @@ def run(self, inputs: List[str], *args, settings: Optional[Seal5Settings] = None else: parallel = 1 if self.pass_scope == PassScope.MODEL: - assert settings is not None - passes_settings = settings.passes - assert passes_settings is not None assert passes_settings.per_model is not None with ThreadPoolExecutor(max_workers=parallel) as executor: From 0df14503cc90280609d177ef2b9b5b8db217ca7e Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:54:58 +0100 Subject: [PATCH 28/80] Seal5Settings.reset(): clear user provided tests --- seal5/settings.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/settings.py b/seal5/settings.py index 15389f20..3b4a1e5c 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -536,7 +536,7 @@ def reset(self): self.patches = [] self.inputs = [] self.metrics = [] - # TODO: clear user provided tests! + self.test = TestSettings(paths=[]) self.filter = FilterSettings( sets=FilterSetting(keep=[], drop=[]), instructions=FilterSetting(keep=[], drop=[]), From 0c0dc2dfd417e527f4b5a24d1cc231b4c4c9ec6f Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:57:07 +0100 Subject: [PATCH 29/80] seal5.backends.llvmir.writer: use mattr from riscv.yml --- seal5/backends/llvmir/writer.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/seal5/backends/llvmir/writer.py b/seal5/backends/llvmir/writer.py index 576d138d..9f31809b 100644 --- a/seal5/backends/llvmir/writer.py +++ b/seal5/backends/llvmir/writer.py @@ -85,8 +85,20 @@ def main(): "n_failed": 0, "n_success": 0, } + settings = model.get("settings", None) if args.splitted: # errs = [] + # model_includes = [] + default_mattr = "+m,+fast-unaligned-access" + if settings: + riscv_settings = settings.riscv + if riscv_settings: + features = riscv_settings.features + if features is None: + pass + else: + default_mattr = ",".join([f"+{f}" for f in features]) + # errs = [] assert out_path.is_dir(), "Expecting output directory when using --splitted" for set_name, set_def in model["sets"].items(): metrics["n_sets"] += 1 @@ -122,6 +134,7 @@ def main(): output_file, skip_patterns=True, skip_formats=True, + mattr=default_mattr, ) metrics["n_success"] += 1 except AssertionError: From 2d79837889126a8e343826a17833c552a24d7243 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:57:25 +0100 Subject: [PATCH 30/80] update demo files --- examples/cfg/filter.yml | 6 ++++-- examples/cfg/riscv.yml | 6 +++--- examples/demo.py | 9 ++++++--- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/examples/cfg/filter.yml b/examples/cfg/filter.yml index b49612cb..03a5ae75 100644 --- a/examples/cfg/filter.yml +++ b/examples/cfg/filter.yml @@ -1,13 +1,15 @@ --- filter: sets: - # keep: [XCoreVAlu] + # keep: [XCoreVSimd] # drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode, XCoreVSimd] drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode] # drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode, RV32Zpsfoperand] instructions: # keep: [CV_ABS, CV_ADD_B] - drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU, SEAL5_CV_SHUFFLE2_B, SEAL5_CV_SHUFFLE2_H, ".*_(SC|SCI)_.*"] + # keep: [SEAL5_simd_add16] + # drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU, SEAL5_CV_SHUFFLE2_B, SEAL5_CV_SHUFFLE2_H, ".*_(SC|SCI)_.*"] + drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU] opcodes: keep: [custom-0, custom-1, custom-2 ,custom-3, 0b00000, OP-P, OP] encoding_sizes: diff --git a/examples/cfg/riscv.yml b/examples/cfg/riscv.yml index d604f3f7..415a2c79 100644 --- a/examples/cfg/riscv.yml +++ b/examples/cfg/riscv.yml @@ -22,9 +22,9 @@ riscv: # - name: [G_ADD] # types: [v4i8, v2i16] # onlyif: [HasExtmyextsimd] - - name: [G_ADD] - types: [s16, s32] - onlyif: [HasExtmyextalu] + # - name: [G_ADD] + # types: [s16, s32] + # onlyif: [HasExtmyextalu] # - name: [G_ADD, G_SMAX] # types: [v4i8, v2i16] # onlyif: [HasExtRV32Zpn] diff --git a/examples/demo.py b/examples/demo.py index 45614ac3..64de7470 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -88,15 +88,17 @@ EXAMPLES_DIR / "tests" / "cv_nand" / "cv_nand.s", EXAMPLES_DIR / "tests" / "cv_nand" / "cv_nand_invalid.s", # TODO: support subdirectories to avoid duplicate test names (WARN!) - # EXAMPLES_DIR / "tests" / "cv_nand" / "*.c", # TODO: support glob patterns + # EXAMPLES_DIR / "tests" / "corev" / "*.asm.s", + # EXAMPLES_DIR / "tests" / "corev" / "*.invalid-asm.s", + EXAMPLES_DIR / "tests" / "corev" / "*.inline-asm.c", ] seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) # Load YAML inputs cfg_files = [ # XCOREV - EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMac.yml", - EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVAlu.yml", + # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMac.yml", + # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVAlu.yml", # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBitmanip.yml", # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVSimd.yml", # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMem.yml", @@ -110,6 +112,7 @@ EXAMPLES_DIR / "cfg" / "patches.yml", EXAMPLES_DIR / "cfg" / "riscv.yml", EXAMPLES_DIR / "cfg" / "tests.yml", + EXAMPLES_DIR / "cfg" / "passes.yml", EXAMPLES_DIR / "cfg" / "git.yml", ] seal5_flow.load(cfg_files, verbose=VERBOSE, overwrite=False) From c8a5efee4711253476f7fbf496b0456922a38a05 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 13 Mar 2024 14:58:39 +0100 Subject: [PATCH 31/80] add some prints for debugging --- seal5/transform/detect_inouts/visitor.py | 29 +++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/seal5/transform/detect_inouts/visitor.py b/seal5/transform/detect_inouts/visitor.py index af504e92..2ebc13ce 100644 --- a/seal5/transform/detect_inouts/visitor.py +++ b/seal5/transform/detect_inouts/visitor.py @@ -59,6 +59,7 @@ def block(self: behav.Block, context): def binary_operation(self: behav.BinaryOperation, context): + # print("binary_operation") self.left = self.left.generate(context) self.right = self.right.generate(context) @@ -66,6 +67,7 @@ def binary_operation(self: behav.BinaryOperation, context): def slice_operation(self: behav.SliceOperation, context): + # print("slice_operation") self.expr = self.expr.generate(context) self.left = self.left.generate(context) self.right = self.right.generate(context) @@ -74,6 +76,7 @@ def slice_operation(self: behav.SliceOperation, context): def concat_operation(self: behav.ConcatOperation, context): + # print("concat_operation") self.left = self.left.generate(context) self.right = self.right.generate(context) @@ -81,28 +84,36 @@ def concat_operation(self: behav.ConcatOperation, context): def number_literal(self: behav.IntLiteral, context): + # print("number_literal") return self def int_literal(self: behav.IntLiteral, context): + # print("int_literal") return self def scalar_definition(self: behav.ScalarDefinition, context): + # print("scalar_definition") return self def break_(self: behav.Break, context): + # print("break_") return self def assignment(self: behav.Assignment, context): # print("assignment") context.is_write = True + # print("> START WRITE") self.target = self.target.generate(context) + # print("< STOP WRITE") context.is_write = False context.is_read = True + # print("> START READ") self.expr = self.expr.generate(context) + # print("> STOP READ") context.is_read = False return self @@ -112,7 +123,9 @@ def conditional(self: behav.Conditional, context): # print("conditional") for i, cond in enumerate(self.conds): context.is_read = True + # print("> START READ") self.conds[i] = cond.generate(context) + # print("> STOP READ") context.is_read = False for op in self.stmts: # for stmt in flatten(op): @@ -123,8 +136,11 @@ def conditional(self: behav.Conditional, context): def loop(self: behav.Loop, context): + # print("loop") context.is_read = True + # print("> START READ") self.cond = self.cond.generate(context) + # print("> STOP READ") context.is_read = False self.stmts = [x.generate(context) for x in self.stmts] @@ -132,16 +148,20 @@ def loop(self: behav.Loop, context): def ternary(self: behav.Ternary, context): + # print("ternary") context.is_read = True + # print("> START READ") self.cond = self.cond.generate(context) self.then_expr = self.then_expr.generate(context) self.else_expr = self.else_expr.generate(context) + # print("> STOP READ") context.is_read = False return self def return_(self: behav.Return, context): + # print("return_") if self.expr is not None: self.expr = self.expr.generate(context) @@ -149,12 +169,16 @@ def return_(self: behav.Return, context): def unary_operation(self: behav.UnaryOperation, context): + # print("unary_operation") self.right = self.right.generate(context) return self def named_reference(self: behav.NamedReference, context): + # print("named_reference", self.reference.name) + # print("is_read", context.is_read) + # print("is_write", context.is_write) if context.is_read: context.reads.add(self.reference.name) elif context.is_write: @@ -163,24 +187,27 @@ def named_reference(self: behav.NamedReference, context): def indexed_reference(self: behav.IndexedReference, context): + # print("indexed_reference") self.index = self.index.generate(context) return self def type_conv(self: behav.TypeConv, context): + # print("type_conv") self.expr = self.expr.generate(context) return self def callable_(self: behav.Callable, context): + # print("callable_") self.args = [stmt.generate(context) for stmt in self.args] return self def group(self: behav.Group, context): - # print("group", group) + # print("group") self.expr = self.expr.generate(context) return self From 45125b4e33d9439a20832a8691517c4d25906887 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 14 Mar 2024 10:48:54 +0100 Subject: [PATCH 32/80] seal5.transform.converter: add --prefix option --- examples/cfg/xcorev/XCoreVMac.yml | 12 +++++++----- seal5/transform/converter.py | 8 ++++---- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/examples/cfg/xcorev/XCoreVMac.yml b/examples/cfg/xcorev/XCoreVMac.yml index ecf0ce37..03aa6eb5 100644 --- a/examples/cfg/xcorev/XCoreVMac.yml +++ b/examples/cfg/xcorev/XCoreVMac.yml @@ -1,8 +1,8 @@ --- extensions: XCoreVMac: - feature: XCVmac - arch: xcvmac + # feature: XCVmac + # arch: xcvmac version: "1.0" experimental: false vendor: true @@ -10,7 +10,9 @@ extensions: passes: per_model: XCoreVMac: - skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] + # skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] override: - behav_to_pat: - patterns: false + # behav_to_pat: + # patterns: false + convert_models: + prefix: "SEAL5" diff --git a/seal5/transform/converter.py b/seal5/transform/converter.py index 01bb2aad..861f3568 100644 --- a/seal5/transform/converter.py +++ b/seal5/transform/converter.py @@ -27,6 +27,7 @@ def main(): parser = argparse.ArgumentParser() parser.add_argument("top_level", help="A .m2isarmodel file containing the models to generate.") parser.add_argument("--log", default="info", choices=["critical", "error", "warning", "info", "debug"]) + parser.add_argument("--prefix", default="", type=str) parser.add_argument("--output", "-o", type=str, default=None) args = parser.parse_args() @@ -65,10 +66,9 @@ def main(): for set_name, set_def in sets.items(): logger.info("replacing set %s", set_name) for enc, instr_def in set_def.instructions.items(): - PREFIX = True - if PREFIX: - instr_def.name = f"SEAL5_{instr_def.name}" - instr_def.mnemonic = f"seal5.{instr_def.mnemonic}" + if args.prefix: + instr_def.name = f"{args.prefix.upper()}_{instr_def.name}" + instr_def.mnemonic = f"{args.prefix.lower()}.{instr_def.mnemonic}" set_def.instructions[enc] = seal5_model.Seal5Instruction( instr_def.name, instr_def.attributes, From 3182d58a60e6f6ee03b0d565de3797ef1f622fbb Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 14 Mar 2024 10:51:34 +0100 Subject: [PATCH 33/80] lint code --- seal5/transform/filter_model/filter.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/seal5/transform/filter_model/filter.py b/seal5/transform/filter_model/filter.py index 3e223b2f..5284c587 100644 --- a/seal5/transform/filter_model/filter.py +++ b/seal5/transform/filter_model/filter.py @@ -192,14 +192,15 @@ def opcodes_helper(x): def check_filter_regex(name, keep, drop): if drop and keep: - return not any(re.compile(expr).match(name) for expr in drop) and any(re.compile(expr).match(name) for expr in keep) + return not any(re.compile(expr).match(name) for expr in drop) and any( + re.compile(expr).match(name) for expr in keep + ) elif keep: return any(re.compile(expr).match(name) for expr in keep) elif drop: return not any(re.compile(expr).match(name) for expr in drop) return True - def check_encoding_filter(enc, keep, drop, keep2, drop2): opcode = None size = 0 @@ -236,7 +237,9 @@ def check_encoding_filter(enc, keep, drop, keep2, drop2): return True model["sets"] = { - set_name: set_def for set_name, set_def in model["sets"].items() if check_filter_regex(set_name, keep_sets, drop_sets) + set_name: set_def + for set_name, set_def in model["sets"].items() + if check_filter_regex(set_name, keep_sets, drop_sets) } for set_name, set_def in model["sets"].items(): set_def.instructions = { From 46eba69ba246c27fd1117b503306d962aee39cec Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 08:44:34 +0100 Subject: [PATCH 34/80] update xcv settings --- examples/cfg/xcorev/XCoreVAlu.yml | 12 +++++------- examples/cfg/xcorev/XCoreVBitmanip.yml | 12 +++++------- examples/cfg/xcorev/XCoreVBranchImmediate.yml | 12 +++++------- examples/cfg/xcorev/XCoreVMac.yml | 4 ---- examples/cfg/xcorev/XCoreVMem.yml | 12 +++++------- examples/cfg/xcorev/XCoreVSimd.yml | 12 +++++------- examples/demo.py | 14 +++++++------- 7 files changed, 32 insertions(+), 46 deletions(-) diff --git a/examples/cfg/xcorev/XCoreVAlu.yml b/examples/cfg/xcorev/XCoreVAlu.yml index 3c43f88b..ad8fabdf 100644 --- a/examples/cfg/xcorev/XCoreVAlu.yml +++ b/examples/cfg/xcorev/XCoreVAlu.yml @@ -1,16 +1,14 @@ --- extensions: XCoreVAlu: - feature: XCValu - arch: xcvalu + # feature: XCValu + # arch: xcvalu version: "1.0" experimental: false vendor: true - # patches: [] passes: per_model: - XCoreVAlu: - skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] + XCoreVMac: override: - behav_to_pat: - patterns: false + convert_models: + prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVBitmanip.yml b/examples/cfg/xcorev/XCoreVBitmanip.yml index 5966e448..af5fd982 100644 --- a/examples/cfg/xcorev/XCoreVBitmanip.yml +++ b/examples/cfg/xcorev/XCoreVBitmanip.yml @@ -1,16 +1,14 @@ --- extensions: XCoreVBitmanip: - feature: XCVbitmanip - arch: xcvbitmanip + # feature: XCVbitmanip + # arch: xcvbitmanip version: "1.0" experimental: false vendor: true - # patches: [] passes: per_model: - XCoreVBitmanip: - skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] + XCoreVMac: override: - behav_to_pat: - patterns: false + convert_models: + prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVBranchImmediate.yml b/examples/cfg/xcorev/XCoreVBranchImmediate.yml index 470327d0..bc1fa693 100644 --- a/examples/cfg/xcorev/XCoreVBranchImmediate.yml +++ b/examples/cfg/xcorev/XCoreVBranchImmediate.yml @@ -1,16 +1,14 @@ --- extensions: XCoreVBranchImmediate: - feature: XCVbi - arch: xcvbi + # feature: XCVbi + # arch: xcvbi version: "1.0" experimental: false vendor: true - # patches: [] passes: per_model: - XCoreVBranchImmediate: - skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] + XCoreVMac: override: - behav_to_pat: - patterns: false + convert_models: + prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVMac.yml b/examples/cfg/xcorev/XCoreVMac.yml index 03aa6eb5..ab135952 100644 --- a/examples/cfg/xcorev/XCoreVMac.yml +++ b/examples/cfg/xcorev/XCoreVMac.yml @@ -6,13 +6,9 @@ extensions: version: "1.0" experimental: false vendor: true - # patches: [] passes: per_model: XCoreVMac: - # skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] override: - # behav_to_pat: - # patterns: false convert_models: prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVMem.yml b/examples/cfg/xcorev/XCoreVMem.yml index b69ac115..1091b8e7 100644 --- a/examples/cfg/xcorev/XCoreVMem.yml +++ b/examples/cfg/xcorev/XCoreVMem.yml @@ -1,16 +1,14 @@ --- extensions: XCoreVMem: - feature: XCVmem - arch: xcvmem + # feature: XCVmem + # arch: xcvmem version: "1.0" experimental: false vendor: true - # patches: [] passes: per_model: - XCoreVMem: - skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] + XCoreVMac: override: - behav_to_pat: - patterns: false + convert_models: + prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVSimd.yml b/examples/cfg/xcorev/XCoreVSimd.yml index ea5d0cca..36b218a6 100644 --- a/examples/cfg/xcorev/XCoreVSimd.yml +++ b/examples/cfg/xcorev/XCoreVSimd.yml @@ -1,16 +1,14 @@ --- extensions: XCoreVSimd: - feature: XCVsimd - arch: xcvsimd + # feature: XCVsimd + # arch: xcvsimd version: "1.0" experimental: false vendor: true - # patches: [] passes: per_model: - XCoreVSimd: - skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat] + XCoreVMac: override: - behav_to_pat: - patterns: false + convert_models: + prefix: "SEAL5" diff --git a/examples/demo.py b/examples/demo.py index 64de7470..6134fa7a 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -62,9 +62,9 @@ # XCOREV EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMac.core_desc", EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVAlu.core_desc", - # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBitmanip.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBitmanip.core_desc", EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVSimd.core_desc", - # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMem.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMem.core_desc", # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBranchImmediate.core_desc", # RVP (will not work) # EXAMPLES_DIR / "cdsl" / "RV32P.core_desc", @@ -97,11 +97,11 @@ # Load YAML inputs cfg_files = [ # XCOREV - # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMac.yml", - # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVAlu.yml", - # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBitmanip.yml", - # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVSimd.yml", - # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMem.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMac.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVAlu.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBitmanip.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVSimd.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMem.yml", # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBranchImmediate.yml", # S4E # TUMEDA From 60047a0947d51ca61ee4a1f69ddbd1755e968798 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 10:37:32 +0100 Subject: [PATCH 35/80] expose llvm repo to seal5 flow class --- examples/demo.py | 10 ++++++---- seal5/flow.py | 11 +++++++++-- seal5/tools/llvm.py | 4 ++-- 3 files changed, 17 insertions(+), 8 deletions(-) diff --git a/examples/demo.py b/examples/demo.py index 6134fa7a..e0478ddd 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -45,14 +45,16 @@ seal5_flow.reset(settings=True, interactive=False) seal5_flow.clean(temp=True, patches=True, models=True, inputs=True, interactive=INTERACTIVE) +if PREPATCHED: + if seal5_flow.repo is None or "seal5-demo-stage0" not in seal5_flow.repo.tags: + raise RuntimeError("PREPATCHED can only be used after LLVM was patched at least once.") + # Clone LLVM and init seal5 metadata directory seal5_flow.initialize( clone=True, - clone_url="git@gitlab.lrz.de:de-tum-ei-eda-esl/llvm/core-v-llvm-project.git" - if PREPATCHED - else "https://github.com/llvm/llvm-project.git", + clone_url="https://github.com/llvm/llvm-project.git", # clone_ref="llvmorg-17.0.6", - clone_ref="seal5-demo-prepatched" if PREPATCHED else "llvmorg-18.1.0-rc3", + clone_ref="seal5-demo-stage0" if PREPATCHED else "llvmorg-18.1.0-rc3", force=True, verbose=VERBOSE, ) diff --git a/seal5/flow.py b/seal5/flow.py index 2cb550da..30cc34a3 100644 --- a/seal5/flow.py +++ b/seal5/flow.py @@ -90,6 +90,7 @@ def __init__(self, directory: Optional[Path] = None, name: str = "default"): self.name: str = name self.state: Seal5State = Seal5State.UNKNOWN self.passes: List[Seal5Pass] = [] # TODO: implement PassManager + self.repo: Optional[git.Repo] = git.Repo(self.directory) self.check() self.settings = Seal5Settings.from_dict(DEFAULT_SETTINGS) # self.settings: Seal5Settings = Seal5Settings(directory=self.directory) @@ -228,10 +229,12 @@ def initialize( if clone is False and not utils.ask_user("Clone LLVM repository?", default=False, interactive=interactive): logger.error("Target directory does not exist! Aborting...") sys.exit(1) - sha, version_info = llvm.clone_llvm_repo(self.directory, clone_url, ref=clone_ref, label=self.name) + self.repo, sha, version_info = llvm.clone_llvm_repo( + self.directory, clone_url, ref=clone_ref, label=self.name + ) else: if force: - sha, version_info = llvm.clone_llvm_repo( + self.repo, sha, version_info = llvm.clone_llvm_repo( self.directory, clone_url, ref=clone_ref, refresh=True, label=self.name ) if self.settings.meta_dir.is_dir(): @@ -623,6 +626,10 @@ def patch(self, verbose: bool = False, stages: List[PatchStage] = None, force: b # skipping continue self.apply_patch(patch, force=force) + assert self.repo is not None + tag_name = f"seal5-{self.name}-stage{int(stage)}" + tag_msg = f"Patched Seal5 LLVM after {stage}" + self.repo.create_tag(tag_name, message=tag_msg, force=True) end = time.time() diff = end - start metrics["time_s"] = diff diff --git a/seal5/tools/llvm.py b/seal5/tools/llvm.py index 14cd2f44..d77f3aae 100644 --- a/seal5/tools/llvm.py +++ b/seal5/tools/llvm.py @@ -62,7 +62,7 @@ def clone_llvm_repo( repo = git.Repo(dest) repo.remotes.origin.set_url(clone_url) repo.remotes.origin.fetch() - if ref: + if ref and ref not in repo.tags: repo.git.checkout(ref) repo.git.pull("origin", ref) else: @@ -89,7 +89,7 @@ def clone_llvm_repo( version_info["rc"] = int(rc) sha = repo.head.commit.hexsha - return sha, version_info + return repo, sha, version_info def build_llvm( From 00385c68c7f49e8e9ba1c6e713b72457bfc8fb0b Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 10:37:51 +0100 Subject: [PATCH 36/80] lint --- seal5/backends/patterngen/writer.py | 2 ++ seal5/pass_list.py | 1 + 2 files changed, 3 insertions(+) diff --git a/seal5/backends/patterngen/writer.py b/seal5/backends/patterngen/writer.py index 25a09200..01ff02ef 100644 --- a/seal5/backends/patterngen/writer.py +++ b/seal5/backends/patterngen/writer.py @@ -114,6 +114,7 @@ def main(): ext_settings = set_def.settings set_dir = out_path / set_name includes = [] + def process_instrunction(instr_def): metrics["n_instructions"] += 1 input_file = out_path / set_name / f"{instr_def.name}.core_desc" @@ -181,6 +182,7 @@ def process_instrunction(instr_def): metrics["n_failed"] += 1 # errs.append((insn_name, str(ex))) return True + with ThreadPoolExecutor(args.parallel) as executor: futures = [] for instr_def in set_def.instructions.values(): diff --git a/seal5/pass_list.py b/seal5/pass_list.py index 15a1dd90..a7a716a4 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -806,6 +806,7 @@ def convert_behav_to_tablegen( args.extend(["--index", index_file]) if parallel: import multiprocessing + num_threads = multiprocessing.cpu_count() args.extend(["--parallel", str(num_threads)]) utils.python( From 7a573f5146ebf289de44d854ec87ee67dc1c1813 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 10:41:17 +0100 Subject: [PATCH 37/80] fix typo in example configs --- examples/cfg/xcorev/XCoreVAlu.yml | 2 +- examples/cfg/xcorev/XCoreVBitmanip.yml | 2 +- examples/cfg/xcorev/XCoreVBranchImmediate.yml | 2 +- examples/cfg/xcorev/XCoreVMac.yml | 2 +- examples/cfg/xcorev/XCoreVMem.yml | 2 +- examples/cfg/xcorev/XCoreVSimd.yml | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/examples/cfg/xcorev/XCoreVAlu.yml b/examples/cfg/xcorev/XCoreVAlu.yml index ad8fabdf..69f49a18 100644 --- a/examples/cfg/xcorev/XCoreVAlu.yml +++ b/examples/cfg/xcorev/XCoreVAlu.yml @@ -9,6 +9,6 @@ extensions: passes: per_model: XCoreVMac: - override: + overrides: convert_models: prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVBitmanip.yml b/examples/cfg/xcorev/XCoreVBitmanip.yml index af5fd982..8bd660c8 100644 --- a/examples/cfg/xcorev/XCoreVBitmanip.yml +++ b/examples/cfg/xcorev/XCoreVBitmanip.yml @@ -9,6 +9,6 @@ extensions: passes: per_model: XCoreVMac: - override: + overrides: convert_models: prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVBranchImmediate.yml b/examples/cfg/xcorev/XCoreVBranchImmediate.yml index bc1fa693..899c06ff 100644 --- a/examples/cfg/xcorev/XCoreVBranchImmediate.yml +++ b/examples/cfg/xcorev/XCoreVBranchImmediate.yml @@ -9,6 +9,6 @@ extensions: passes: per_model: XCoreVMac: - override: + overrides: convert_models: prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVMac.yml b/examples/cfg/xcorev/XCoreVMac.yml index ab135952..4aa6b9da 100644 --- a/examples/cfg/xcorev/XCoreVMac.yml +++ b/examples/cfg/xcorev/XCoreVMac.yml @@ -9,6 +9,6 @@ extensions: passes: per_model: XCoreVMac: - override: + overrides: convert_models: prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVMem.yml b/examples/cfg/xcorev/XCoreVMem.yml index 1091b8e7..35b205a0 100644 --- a/examples/cfg/xcorev/XCoreVMem.yml +++ b/examples/cfg/xcorev/XCoreVMem.yml @@ -9,6 +9,6 @@ extensions: passes: per_model: XCoreVMac: - override: + overrides: convert_models: prefix: "SEAL5" diff --git a/examples/cfg/xcorev/XCoreVSimd.yml b/examples/cfg/xcorev/XCoreVSimd.yml index 36b218a6..084d4707 100644 --- a/examples/cfg/xcorev/XCoreVSimd.yml +++ b/examples/cfg/xcorev/XCoreVSimd.yml @@ -9,6 +9,6 @@ extensions: passes: per_model: XCoreVMac: - override: + overrides: convert_models: prefix: "SEAL5" From 93a74bf2febfc8ad410817ab195d456540e9ffff Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 10:44:54 +0100 Subject: [PATCH 38/80] fix --- seal5/tools/llvm.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/seal5/tools/llvm.py b/seal5/tools/llvm.py index d77f3aae..21e93660 100644 --- a/seal5/tools/llvm.py +++ b/seal5/tools/llvm.py @@ -62,9 +62,10 @@ def clone_llvm_repo( repo = git.Repo(dest) repo.remotes.origin.set_url(clone_url) repo.remotes.origin.fetch() - if ref and ref not in repo.tags: + if ref: repo.git.checkout(ref) - repo.git.pull("origin", ref) + if ref not in repo.tags: + repo.git.pull("origin", ref) else: logger.debug("Cloning LLVM repository: %s", clone_url) repo = git.Repo.clone_from(clone_url, dest, no_checkout=ref is not None) From 00d11c10371b30f28c1acf4569a372c1c6c7eb51 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 10:47:30 +0100 Subject: [PATCH 39/80] fix prefix overrides --- seal5/pass_list.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/seal5/pass_list.py b/seal5/pass_list.py index a7a716a4..371dae2a 100644 --- a/seal5/pass_list.py +++ b/seal5/pass_list.py @@ -17,6 +17,7 @@ def convert_models( env: Optional[dict] = None, verbose: bool = False, inplace: bool = False, + prefix: Optional[str] = None, **kwargs, ): assert not inplace @@ -35,6 +36,9 @@ def convert_models( "info", # "debug", ] + if prefix: + assert isinstance(prefix, str) + args.extend(["--prefix", prefix]) utils.python( "-m", "seal5.transform.converter", From b42577f035fc9bb57811e189430f02955d1f00cc Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 10:55:03 +0100 Subject: [PATCH 40/80] fix prefix overrides --- examples/cfg/xcorev/XCoreVAlu.yml | 4 ++-- examples/cfg/xcorev/XCoreVBitmanip.yml | 4 ++-- examples/cfg/xcorev/XCoreVBranchImmediate.yml | 4 ++-- examples/cfg/xcorev/XCoreVMac.yml | 2 +- examples/cfg/xcorev/XCoreVMem.yml | 4 ++-- examples/cfg/xcorev/XCoreVSimd.yml | 4 ++-- seal5/transform/converter.py | 5 +++-- 7 files changed, 14 insertions(+), 13 deletions(-) diff --git a/examples/cfg/xcorev/XCoreVAlu.yml b/examples/cfg/xcorev/XCoreVAlu.yml index 69f49a18..c900d667 100644 --- a/examples/cfg/xcorev/XCoreVAlu.yml +++ b/examples/cfg/xcorev/XCoreVAlu.yml @@ -8,7 +8,7 @@ extensions: vendor: true passes: per_model: - XCoreVMac: + XCoreVAlu: overrides: convert_models: - prefix: "SEAL5" + prefix: "SEAL5_" diff --git a/examples/cfg/xcorev/XCoreVBitmanip.yml b/examples/cfg/xcorev/XCoreVBitmanip.yml index 8bd660c8..661e1f1f 100644 --- a/examples/cfg/xcorev/XCoreVBitmanip.yml +++ b/examples/cfg/xcorev/XCoreVBitmanip.yml @@ -8,7 +8,7 @@ extensions: vendor: true passes: per_model: - XCoreVMac: + XCoreVBitmanip: overrides: convert_models: - prefix: "SEAL5" + prefix: "SEAL5_" diff --git a/examples/cfg/xcorev/XCoreVBranchImmediate.yml b/examples/cfg/xcorev/XCoreVBranchImmediate.yml index 899c06ff..906fcf0d 100644 --- a/examples/cfg/xcorev/XCoreVBranchImmediate.yml +++ b/examples/cfg/xcorev/XCoreVBranchImmediate.yml @@ -8,7 +8,7 @@ extensions: vendor: true passes: per_model: - XCoreVMac: + XCoreVBranchImmediate: overrides: convert_models: - prefix: "SEAL5" + prefix: "SEAL5_" diff --git a/examples/cfg/xcorev/XCoreVMac.yml b/examples/cfg/xcorev/XCoreVMac.yml index 4aa6b9da..71f5b714 100644 --- a/examples/cfg/xcorev/XCoreVMac.yml +++ b/examples/cfg/xcorev/XCoreVMac.yml @@ -11,4 +11,4 @@ passes: XCoreVMac: overrides: convert_models: - prefix: "SEAL5" + prefix: "SEAL5_" diff --git a/examples/cfg/xcorev/XCoreVMem.yml b/examples/cfg/xcorev/XCoreVMem.yml index 35b205a0..0549417f 100644 --- a/examples/cfg/xcorev/XCoreVMem.yml +++ b/examples/cfg/xcorev/XCoreVMem.yml @@ -8,7 +8,7 @@ extensions: vendor: true passes: per_model: - XCoreVMac: + XCoreVMem: overrides: convert_models: - prefix: "SEAL5" + prefix: "SEAL5_" diff --git a/examples/cfg/xcorev/XCoreVSimd.yml b/examples/cfg/xcorev/XCoreVSimd.yml index 084d4707..fe71357e 100644 --- a/examples/cfg/xcorev/XCoreVSimd.yml +++ b/examples/cfg/xcorev/XCoreVSimd.yml @@ -8,7 +8,7 @@ extensions: vendor: true passes: per_model: - XCoreVMac: + XCoreVSimd: overrides: convert_models: - prefix: "SEAL5" + prefix: "SEAL5_" diff --git a/seal5/transform/converter.py b/seal5/transform/converter.py index 861f3568..372ff48c 100644 --- a/seal5/transform/converter.py +++ b/seal5/transform/converter.py @@ -67,8 +67,9 @@ def main(): logger.info("replacing set %s", set_name) for enc, instr_def in set_def.instructions.items(): if args.prefix: - instr_def.name = f"{args.prefix.upper()}_{instr_def.name}" - instr_def.mnemonic = f"{args.prefix.lower()}.{instr_def.mnemonic}" + instr_def.name = f"{args.prefix.upper()}{instr_def.name}" + prefix_ = args.prefix.lower().replace("_", ".") + instr_def.mnemonic = f"{prefix_}.{instr_def.mnemonic}" set_def.instructions[enc] = seal5_model.Seal5Instruction( instr_def.name, instr_def.attributes, From b0b1aef057c68282db042d77ffe8e4dc8d30b635 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 12:33:09 +0100 Subject: [PATCH 41/80] [ci] expose demo settings as workflow inputs --- .github/workflows/demo.yml | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/.github/workflows/demo.yml b/.github/workflows/demo.yml index d13376be..e2fe328f 100644 --- a/.github/workflows/demo.yml +++ b/.github/workflows/demo.yml @@ -20,7 +20,21 @@ # Seal5 demonstration (also serves as end-to-end testj name: Usage Demo -on: [workflow_dispatch] +on: + workflow_dispatch: + inputs: + verbose: + description: "Verbose (0/1)" + required: true + default: "0" + fast: + description: "Fast (0/1)" + required: true + default: "0" + build_config: + description: "Build Config (debug/release/...)" + required: true + default: "release" # push: # branches: # - main @@ -60,7 +74,7 @@ jobs: - name: Run the demo run: | source .venv/bin/activate - python examples/demo.py + VERBOSE=${{ github.event.inputs.verbose }} FAST=${{ github.event.inputs.fast }} BUILD_CONFIG=${{ github.event.inputs.build_config }} python examples/demo.py - uses: actions/upload-artifact@v4 with: name: demo-export From 219289ec58ef1a36f5b1a0362466cf2c85f1997f Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 17:06:38 +0100 Subject: [PATCH 42/80] fix --- seal5/dependencies.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/dependencies.py b/seal5/dependencies.py index 557cd0f3..47b59097 100644 --- a/seal5/dependencies.py +++ b/seal5/dependencies.py @@ -66,7 +66,7 @@ def __init__(self, clone_url="https://github.com/PhilippvK/M2-ISA-R-private.git" class CDSL2LLVMDependency(GitDependency): # def __init__(self, clone_url="https://github.com/mathis-s/CoreDSL2LLVM.git", ref="main"): - def __init__(self, clone_url="https://github.com/PhilippvK/CoreDSL2LLVM.git", ref="philippvk3-llvm18-ops"): + def __init__(self, clone_url="https://github.com/PhilippvK/CoreDSL2LLVM.git", ref="philippvk3-llvm18-ops-new"): super().__init__("cdsl2llvm", clone_url, ref=ref) From a3a1edee2bb8f5a4eaed3a114b015645a4990355 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 17:07:20 +0100 Subject: [PATCH 43/80] fix problems with reset and clean on fresh flow --- seal5/flow.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/seal5/flow.py b/seal5/flow.py index 30cc34a3..f4eb351b 100644 --- a/seal5/flow.py +++ b/seal5/flow.py @@ -90,7 +90,7 @@ def __init__(self, directory: Optional[Path] = None, name: str = "default"): self.name: str = name self.state: Seal5State = Seal5State.UNKNOWN self.passes: List[Seal5Pass] = [] # TODO: implement PassManager - self.repo: Optional[git.Repo] = git.Repo(self.directory) + self.repo: Optional[git.Repo] = git.Repo(self.directory) if self.directory.is_dir() else None self.check() self.settings = Seal5Settings.from_dict(DEFAULT_SETTINGS) # self.settings: Seal5Settings = Seal5Settings(directory=self.directory) @@ -713,13 +713,13 @@ def reset(self, settings: bool = True, verbose: bool = False, interactive: bool metrics = {} if interactive: raise NotImplementedError - if settings: - self.settings.reset() + self.settings.reset() end = time.time() diff = end - start metrics["time_s"] = diff self.settings.metrics.append({"reset": metrics}) - self.settings.save() + if self.settings.meta_dir.is_dir(): + self.settings.save() logger.info("Completed clean of Seal5 settings") def clean( @@ -764,5 +764,6 @@ def clean( diff = end - start metrics["time_s"] = diff self.settings.metrics.append({"clean": metrics}) - self.settings.save() + if self.settings.meta_dir.is_dir(): + self.settings.save() logger.info("Completed clean of Seal5 directories") From 2af2a01bc8857dec12e84e335a761a21cf08f671 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 19 Mar 2024 18:10:14 +0100 Subject: [PATCH 44/80] raise error if flow.load() does not find file --- seal5/flow.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/seal5/flow.py b/seal5/flow.py index f4eb351b..58341418 100644 --- a/seal5/flow.py +++ b/seal5/flow.py @@ -382,7 +382,13 @@ def load_cdsl(self, file: Path, verbose: bool = False, overwrite: bool = False): def load(self, files: List[Path], verbose: bool = False, overwrite: bool = False): logger.info("Loading Seal5 inputs") # Expand glob patterns - files = sum([list(map(Path, glob.glob(str(file)))) for file in files], []) + + def glob_helper(file): + res = glob.glob(str(file)) + assert len(res) > 0, f"No files found for pattern: {file}" + return list(map(Path, res)) + + files = sum([glob_helper(file) for file in files], []) for file in files: logger.info("Processing file: %s", file) ext = file.suffix From e6fe7b4e0d151409671e29965eac99bf2da987f1 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:04:20 +0100 Subject: [PATCH 45/80] update LIMITATIONS.md --- LIMITATIONS.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/LIMITATIONS.md b/LIMITATIONS.md index 0dd10fa7..37cbd54c 100644 --- a/LIMITATIONS.md +++ b/LIMITATIONS.md @@ -13,3 +13,12 @@ - No memory access - No branches/jumps - TODO + +## Known Bugs + +### Clang `-march` parser does not pick up new extensions + +Due to issues with the ordering of extensions in `RISCVISAInfo.cpp` the search algorithm will not find entries which not inserted in the correct order. To deal with this issue the following workaround is recommended: + +- Only generate patches for a single model (CoreDSL file) +- Make sure that the `arch` string always starts with an `x`, or better prefix every arch string with `xseal5`. From c1b5bcb2c3fada8640fea70174cdd06e67260627 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:04:31 +0100 Subject: [PATCH 46/80] update filter.yml --- examples/cfg/filter.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/cfg/filter.yml b/examples/cfg/filter.yml index 03a5ae75..dd8c9538 100644 --- a/examples/cfg/filter.yml +++ b/examples/cfg/filter.yml @@ -9,7 +9,7 @@ filter: # keep: [CV_ABS, CV_ADD_B] # keep: [SEAL5_simd_add16] # drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU, SEAL5_CV_SHUFFLE2_B, SEAL5_CV_SHUFFLE2_H, ".*_(SC|SCI)_.*"] - drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU] + drop: [SEAL5_CV_CLIPU, SEAL5_CV_CLIPR, SEAL5_CV_CLIPUR, SEAL5_CV_SLET, SEAL5_CV_SLETU, SEAL5_CV_PACK, SEAL5_CV_PACKLO_B] opcodes: keep: [custom-0, custom-1, custom-2 ,custom-3, 0b00000, OP-P, OP] encoding_sizes: From 153b1477085272ab37642857ba5b1a843b6ab565 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:04:53 +0100 Subject: [PATCH 47/80] add custom patch: legalizer_split --- examples/cfg/patches.yml | 1 + .../patches/llvm/legalizer_split.patch | 24 +++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 seal5/resources/patches/llvm/legalizer_split.patch diff --git a/examples/cfg/patches.yml b/examples/cfg/patches.yml index 66dbd55f..4961ea48 100644 --- a/examples/cfg/patches.yml +++ b/examples/cfg/patches.yml @@ -17,6 +17,7 @@ patches: # file: /absolute/path/to/gitlab_ci.patch # - name: insert_markers_llvm17 - name: insert_markers_llvm18 + - name: legalizer_split # TODO: automatially select patch depending on llvm version # generated patch (TODO: implement) # - name: ??? diff --git a/seal5/resources/patches/llvm/legalizer_split.patch b/seal5/resources/patches/llvm/legalizer_split.patch new file mode 100644 index 00000000..74e7ee12 --- /dev/null +++ b/seal5/resources/patches/llvm/legalizer_split.patch @@ -0,0 +1,24 @@ +diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp ++++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +@@ -299,11 +299,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) + AbsActions.customFor({s32, sXLen}).minScalar(0, sXLen); + AbsActions.lower(); + +- auto &MinMaxActions = +- getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN}); +- if (ST.hasStdExtZbb()) +- MinMaxActions.legalFor({sXLen}).minScalar(0, sXLen); +- MinMaxActions.lower(); ++ // auto &MinMaxActions = ++ // getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN}); ++ for (auto &Op : {G_UMAX, G_UMIN, G_SMAX, G_SMIN}) { ++ auto &Actions = getActionDefinitionsBuilder(Op); ++ if (ST.hasStdExtZbb()) ++ Actions.legalFor({sXLen}).minScalar(0, sXLen); ++ Actions.lower(); ++ } + + getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0}); + + From 855f0a395eaf608779e919e6b9741cda0c7fb117 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:05:28 +0100 Subject: [PATCH 48/80] backends: add missing newline --- seal5/backends/riscv_features/writer.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/backends/riscv_features/writer.py b/seal5/backends/riscv_features/writer.py index e495d20b..b87bc2f2 100644 --- a/seal5/backends/riscv_features/writer.py +++ b/seal5/backends/riscv_features/writer.py @@ -44,7 +44,7 @@ def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings): content_template = Template(MAKO_TEMPLATE) content_text = content_template.render(predicate=predicate, feature=feature, arch=arch, description=description) # content_text = content_text.rstrip("\n") - return content_text + return content_text + "\n" def main(): From 1168db97934b24da82c81faf894d9851155bd6e3 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:05:49 +0100 Subject: [PATCH 49/80] riscv_gisel_legalizer: fix --- seal5/backends/riscv_gisel_legalizer/writer.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/seal5/backends/riscv_gisel_legalizer/writer.py b/seal5/backends/riscv_gisel_legalizer/writer.py index 08379c23..73b444e6 100644 --- a/seal5/backends/riscv_gisel_legalizer/writer.py +++ b/seal5/backends/riscv_gisel_legalizer/writer.py @@ -71,7 +71,12 @@ def gen_riscv_gisel_legalizer_str(legalizer_settings: RISCVLegalizerSettings): line = type_helper(ty) types_lines.append(line) used_types.append(ty) - names_str = "{" + ", ".join(names) + "}" + assert len(names) > 0 + if len(names) == 1: + names_str = names[0] + else: # TODO: iterate over ops! + raise NotImplementedError + names_str = "{" + ", ".join(names) + "}" line = "" if onlyif: cond = " && ".join(["ST." + pred[0].lower() + pred[1:] + "()" for pred in onlyif]) From 41640f4f4e27bf838165207819587d7eabf54eea Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:06:15 +0100 Subject: [PATCH 50/80] riscv_isa_info: sort lines alphabetically --- seal5/backends/riscv_isa_info/writer.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/seal5/backends/riscv_isa_info/writer.py b/seal5/backends/riscv_isa_info/writer.py index 676b2adc..75c5001b 100644 --- a/seal5/backends/riscv_isa_info/writer.py +++ b/seal5/backends/riscv_isa_info/writer.py @@ -43,7 +43,7 @@ def gen_riscv_isa_info_str(name: str, ext_settings: ExtensionsSettings, llvm_ver content_template = Template(template) content_text = content_template.render(arch=arch, version_major=version_major, version_minor=version_minor) # content_text = content_text.rstrip("\n") - return content_text + return arch, (content_text) def main(): @@ -114,7 +114,8 @@ def main(): if args.splitted: raise NotImplementedError else: - content = "" + # content = "" + contents = [] # Extensions need to be sorted! # errs = [] settings = model.get("settings", None) llvm_version = None @@ -132,7 +133,10 @@ def main(): metrics["n_skipped"] += 1 continue metrics["n_success"] += 1 - content += gen_riscv_isa_info_str(set_name, ext_settings=ext_settings, llvm_version=llvm_version) + key, new_content = gen_riscv_isa_info_str(set_name, ext_settings=ext_settings, llvm_version=llvm_version) + contents.append((key, new_content)) + contents = sorted(contents, key=lambda x: x[0]) + content = "\n".join([x[1] for x in contents]) + "\n" if len(content) > 0: with open(out_path, "w") as f: f.write(content) From 381a04f6a75ba42da645df3b35bf89d2a45b8984 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:06:40 +0100 Subject: [PATCH 51/80] insert_markers_llvm18.patch: move riscv_isa_info markers up --- .../patches/llvm/insert_markers_llvm18.patch | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/seal5/resources/patches/llvm/insert_markers_llvm18.patch b/seal5/resources/patches/llvm/insert_markers_llvm18.patch index 8e4c8f45..de887f86 100644 --- a/seal5/resources/patches/llvm/insert_markers_llvm18.patch +++ b/seal5/resources/patches/llvm/insert_markers_llvm18.patch @@ -73,16 +73,16 @@ diff --git a/llvm/lib/CodeGen/GlobalISel/GlobalISel.cpp b/llvm/lib/CodeGen/Globa diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp -@@ -89,6 +89,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = { - {"xtheadvdot", {1, 0}}, - {"xventanacondops", {1, 0}}, +@@ -63,6 +63,9 @@ static const RISCVSupportedExtension SupportedExtensions[] = { + + {"v", {1, 0}}, +// RISCVISAInfo.cpp - riscv_isa_info - INSERTION_START +// RISCVISAInfo.cpp - riscv_isa_info - INSERTION_END + - {"za128rs", {1, 0}}, - {"za64rs", {1, 0}}, - {"zawrs", {1, 0}}, + // vendor-defined ('X') extensions + {"xcvalu", {1, 0}}, + {"xcvbi", {1, 0}}, @@ -192,6 +195,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = { // NOTE: This table should be sorted alphabetically by extension name. From 3eb89c7b96bcddf51047144618f3c3372859d329 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:07:04 +0100 Subject: [PATCH 52/80] cdsl2llvm fix --- seal5/settings.py | 6 ++++++ seal5/tools/cdsl2llvm.py | 5 +++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/seal5/settings.py b/seal5/settings.py index 3b4a1e5c..ddcc0434 100644 --- a/seal5/settings.py +++ b/seal5/settings.py @@ -553,6 +553,12 @@ def reset(self): ), per_model={}, ) + self.riscv = RISCVSettings( + xlen=None, + features=None, + transform_info=None, + legalization=None, + ) def save(self, dest: Optional[Path] = None): if dest is None: diff --git a/seal5/tools/cdsl2llvm.py b/seal5/tools/cdsl2llvm.py index 36ca6fd1..2efd969d 100644 --- a/seal5/tools/cdsl2llvm.py +++ b/seal5/tools/cdsl2llvm.py @@ -132,13 +132,14 @@ def run_pattern_gen( if not isinstance(build_dir, Path): build_dir = Path(build_dir) pattern_gen_args = [src] - pattern_gen_args.extend(["-custom-legalizer-settings=foo", "-disable-gisel-legality-check"]) + # pattern_gen_args.extend(["-custom-legalizer-settings=foo", "-disable-gisel-legality-check"]) if dest: pattern_gen_args.extend(["-o", str(dest)]) if ext: - pattern_gen_args.extend(["--ext", ext]) + # pattern_gen_args.extend(["--ext", ext]) + pattern_gen_args.extend(["-p", f"Has{ext}"]) if mattr is None: attrs = ["+m", "+fast-unaligned-access"] From 88aac0e90d2c72317d815e76dc6942834e6e24f7 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:07:24 +0100 Subject: [PATCH 53/80] add new rv_gen files --- examples/cdsl/rv_gen/all_v2.core_desc | 90 +++++ examples/cdsl/rv_gen/all_v5.core_desc | 517 ++++++++++++++++++++++++++ 2 files changed, 607 insertions(+) create mode 100644 examples/cdsl/rv_gen/all_v2.core_desc create mode 100644 examples/cdsl/rv_gen/all_v5.core_desc diff --git a/examples/cdsl/rv_gen/all_v2.core_desc b/examples/cdsl/rv_gen/all_v2.core_desc new file mode 100644 index 00000000..fbc3ce64 --- /dev/null +++ b/examples/cdsl/rv_gen/all_v2.core_desc @@ -0,0 +1,90 @@ +import "../rv_base/RV32I.core_desc" + +InstructionSet Seal5Test_alu extends RV32I { + instructions { + abs { + encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.abs", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) < 0 ? -(signed<32>)(X[rs1]) : (signed<32>)(X[rs1]); + } + } + min { + encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) < (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); + } + } + max { + encoding: 7'b0000010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) > (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); + } + } + slet { + encoding: 7'b0000011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.slet", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) <= (signed<32>)(X[rs2]) ? 1 : 0; + } + } + addNr { + encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; + } + } + subNr { + encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; + } + } + addRNr { + encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; + } + } + subRNr { + encoding: 7'b0000111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; + } + } + addN { + encoding: 2'b00 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) >> (unsigned<5>)(imm5); + } + } + subN { + encoding: 2'b01 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) >> (unsigned<5>)(imm5); + } + } + addRN { + encoding: 2'b10 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(imm5) - 1 >> (unsigned<5>)(imm5); + } + } + subRN { + encoding: 2'b11 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(imm5) - 1 >> (unsigned<5>)(imm5); + } + } + } +} diff --git a/examples/cdsl/rv_gen/all_v5.core_desc b/examples/cdsl/rv_gen/all_v5.core_desc new file mode 100644 index 00000000..62f98e0f --- /dev/null +++ b/examples/cdsl/rv_gen/all_v5.core_desc @@ -0,0 +1,517 @@ +import "../rv_base/RV32I.core_desc" + +InstructionSet Seal5Test_alu_cv_abs extends RV32I { + instructions { + cv_abs { + encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.abs", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)X[rs1] < 0 ? -X[rs1] : X[rs1]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_minu extends RV32I { + instructions { + cv_minu { + encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.minu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] < X[rs2] ? X[rs1] : X[rs2]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mins extends RV32I { + instructions { + cv_mins { + encoding: 7'b0000010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mins", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) < (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxu extends RV32I { + instructions { + cv_maxu { + encoding: 7'b0000011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] > X[rs2] ? X[rs1] : X[rs2]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxs extends RV32I { + instructions { + cv_maxs { + encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) > (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_sletu extends RV32I { + instructions { + cv_sletu { + encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.sletu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] <= X[rs2] ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_slets extends RV32I { + instructions { + cv_slets { + encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.slets", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) <= (signed<32>)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNru extends RV32I { + instructions { + cv_addNru { + encoding: 7'b0000111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNrs extends RV32I { + instructions { + cv_addNrs { + encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNru extends RV32I { + instructions { + cv_subNru { + encoding: 7'b0001001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNrs extends RV32I { + instructions { + cv_subNrs { + encoding: 7'b0001010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNru extends RV32I { + instructions { + cv_addRNru { + encoding: 7'b0001011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNrs extends RV32I { + instructions { + cv_addRNrs { + encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNru extends RV32I { + instructions { + cv_subRNru { + encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNrs extends RV32I { + instructions { + cv_subRNrs { + encoding: 7'b0001110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNu extends RV32I { + instructions { + cv_addNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] + X[rs2] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNs extends RV32I { + instructions { + cv_addNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNu extends RV32I { + instructions { + cv_subNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] - X[rs2] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNs extends RV32I { + instructions { + cv_subNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNu extends RV32I { + instructions { + cv_addRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] + X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNs extends RV32I { + instructions { + cv_addRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNu extends RV32I { + instructions { + cv_subRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] - X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNs extends RV32I { + instructions { + cv_subRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macu extends RV32I { + instructions { + cv_macu { + encoding: 7'b0001111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macs extends RV32I { + instructions { + cv_macs { + encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msuu extends RV32I { + instructions { + cv_msuu { + encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msuu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msus extends RV32I { + instructions { + cv_msus { + encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msus", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulNu extends RV32I { + instructions { + cv_mulNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulNs extends RV32I { + instructions { + cv_mulNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhNu extends RV32I { + instructions { + cv_mulhhNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhNs extends RV32I { + instructions { + cv_mulhhNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulRNu extends RV32I { + instructions { + cv_mulRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulRNs extends RV32I { + instructions { + cv_mulRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhRNu extends RV32I { + instructions { + cv_mulhhRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhRNs extends RV32I { + instructions { + cv_mulhhRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macNu extends RV32I { + instructions { + cv_macNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macNs extends RV32I { + instructions { + cv_macNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhNu extends RV32I { + instructions { + cv_machhNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.machhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { + instructions { + cv_machhNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.machhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macRNu extends RV32I { + instructions { + cv_macRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macRNs extends RV32I { + instructions { + cv_macRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhRNu extends RV32I { + instructions { + cv_machhRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.machhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhRNs extends RV32I { + instructions { + cv_machhRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.machhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} From 8bd61a267d1c23938fdeccbef83f0c4b6cbb9036 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:07:51 +0100 Subject: [PATCH 54/80] add new rv_tumeda files --- .../rv_tumeda/SEAL5_CV_SUBPKD820.core_desc | 124 ++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 examples/cdsl/rv_tumeda/SEAL5_CV_SUBPKD820.core_desc diff --git a/examples/cdsl/rv_tumeda/SEAL5_CV_SUBPKD820.core_desc b/examples/cdsl/rv_tumeda/SEAL5_CV_SUBPKD820.core_desc new file mode 100644 index 00000000..0a545b13 --- /dev/null +++ b/examples/cdsl/rv_tumeda/SEAL5_CV_SUBPKD820.core_desc @@ -0,0 +1,124 @@ +InstructionSet XCoreVSimd extends RV32I { + instructions { + // SEAL5_CV_SUBPKD810 { + // operands: { + // unsigned<5> rd [[is_reg]] [[out]]; + // unsigned<5> rs1 [[is_reg]] [[in]]; + // } + // encoding: 5'b01110 :: 1'b0 :: 1'b0 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + // assembly: "{name(rd)}, {name(rs1)}"; + // behavior: { + // { + // X[rd][15:0] = (signed<16>)(X[rs1][7:0]); + // X[rd][31:16] = (signed<16>)(X[rs1][15:8]); + // } + // } + // } + // SEAL5_CV_SUBPKD820 { + // operands: { + // unsigned<5> rd [[is_reg]] [[out]]; + // unsigned<5> rs1 [[is_reg]] [[in]]; + // } + // encoding: 5'b01110 :: 1'b0 :: 1'b0 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + // assembly: "{name(rd)}, {name(rs1)}"; + // behavior: { + // { + // X[rd][15:0] = (signed<16>)(X[rs1][7:0]); + // X[rd][31:16] = (signed<16>)(X[rs1][23:16]); + // } + // } + // } + // SEAL5_CV_SUBPKD820_ { + // operands: { + // unsigned<5> rd [[is_reg]] [[out]]; + // unsigned<5> rs1 [[is_reg]] [[in]]; + // } + // encoding: 5'b01110 :: 1'b0 :: 1'b0 :: 5'b00000 :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + // assembly: "{name(rd)}, {name(rs1)}"; + // behavior: { + // { + // X[rd][15:0] = (signed<16>)(signed)(X[rs1][7:0]); + // X[rd][31:16] = (signed<16>)(signed)(X[rs1][23:16]); + // } + // } + // } + // CV_MAC_H { + // operands: { + // unsigned<5> rd [[is_reg]] [[out]]; + // unsigned<5> rs1 [[is_reg]] [[in]]; + // unsigned<5> rs2 [[is_reg]] [[in]]; + // } + // encoding: 5'b1111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b0 :: rd[4:0] :: 7'b1111011; + // assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + // behavior: { + // if (rd != 0) { + // X[rd][15: 0] += (X[rs1][15: 0] * X[rs2][15: 0])[15:0]; + // X[rd][31:16] += (X[rs1][31:16] * X[rs2][31:16])[15:0]; + // } + + // } + // } + // CV_MAC_B { + // operands: { + // unsigned<5> rd [[is_reg]] [[out]]; + // unsigned<5> rs1 [[is_reg]] [[in]]; + // unsigned<5> rs2 [[is_reg]] [[in]]; + // } + // encoding: 5'b1111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b1 :: rd[4:0] :: 7'b1111011; + // assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + // behavior: { + // if (rd != 0) { + // X[rd][ 7: 0] += (X[rs1][ 7: 0] * X[rs2][ 7: 0])[7:0]; + // X[rd][15: 8] += (X[rs1][15: 8] * X[rs2][15: 8])[7:0]; + // X[rd][23:16] += (X[rs1][23:16] * X[rs2][23:16])[7:0]; + // X[rd][31:24] += (X[rs1][31:24] * X[rs2][31:24])[7:0]; + // } + // } + // } + // CV_MAC_B_820 { + // operands: { + // unsigned<5> rd [[is_reg]] [[out]]; + // unsigned<5> rs1 [[is_reg]] [[in]]; + // unsigned<5> rs2 [[is_reg]] [[in]]; + // } + // encoding: 5'b1111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b1 :: rd[4:0] :: 7'b1111011; + // assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + // behavior: { + // if (rd != 0) { + // X[rd][15: 0] += (X[rs1][ 7: 0] * X[rs2][ 7: 0])[15:0]; + // X[rd][31:16] += (X[rs1][23:16] * X[rs2][23:16])[15:0]; + // } + // } + // } + CV_MAC_B_810 { + operands: { + unsigned<5> rd [[is_reg]] [[out]]; + unsigned<5> rs1 [[is_reg]] [[in]]; + unsigned<5> rs2 [[is_reg]] [[in]]; + } + encoding: 5'b1111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b1 :: rd[4:0] :: 7'b1111011; + assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + behavior: { + if (rd != 0) { + X[rd][15: 0] += (X[rs1][ 7: 0] * X[rs2][ 7: 0])[15:0]; + X[rd][31:16] += (X[rs1][15: 8] * X[rs2][15: 8])[15:0]; + } + } + } + CV_MAC_B_832 { + operands: { + unsigned<5> rd [[is_reg]] [[out]]; + unsigned<5> rs1 [[is_reg]] [[in]]; + unsigned<5> rs2 [[is_reg]] [[in]]; + } + encoding: 5'b1111 :: 1'b0 :: 1'b0 :: rs2[4:0] :: rs1[4:0] :: 3'b1 :: rd[4:0] :: 7'b1111011; + assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + behavior: { + if (rd != 0) { + X[rd][15: 0] += (X[rs1][23:16] * X[rs2][23:16])[15:0]; + X[rd][31:16] += (X[rs1][31:24] * X[rs2][31:24])[15:0]; + } + } + } + } +} From ae236dff43eeb22a6876baecc3aef93213fff94f Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:08:06 +0100 Subject: [PATCH 55/80] refactor cfgs --- examples/cfg/gen/all.yml | 265 +++++++++++++++++++++++++++++ examples/cfg/gen/riscv.yml | 41 +++++ examples/cfg/passes.yml | 6 + examples/cfg/{ => s4e}/s4e-mac.yml | 0 examples/cfg/tumeda/OpenASIP.yml | 12 ++ examples/cfg/xcorev/filter.yml | 8 + examples/cfg/xcorev/riscv.yml | 21 +++ 7 files changed, 353 insertions(+) create mode 100644 examples/cfg/gen/all.yml create mode 100644 examples/cfg/gen/riscv.yml create mode 100644 examples/cfg/passes.yml rename examples/cfg/{ => s4e}/s4e-mac.yml (100%) create mode 100644 examples/cfg/tumeda/OpenASIP.yml create mode 100644 examples/cfg/xcorev/filter.yml create mode 100644 examples/cfg/xcorev/riscv.yml diff --git a/examples/cfg/gen/all.yml b/examples/cfg/gen/all.yml new file mode 100644 index 00000000..2e555aed --- /dev/null +++ b/examples/cfg/gen/all.yml @@ -0,0 +1,265 @@ +extensions: + Seal5Test_alu_cv_abs: + arch: xseal5testalucvabs + experimental: false + feature: seal5testalucvabs + vendor: false + version: '1.0' + Seal5Test_alu_cv_addNrs: + arch: xseal5testalucvaddnrs + experimental: false + feature: seal5testalucvaddnrs + vendor: false + version: '1.0' + Seal5Test_alu_cv_addNru: + arch: xseal5testalucvaddnru + experimental: false + feature: seal5testalucvaddnru + vendor: false + version: '1.0' + Seal5Test_alu_cv_addNs: + arch: xseal5testalucvaddns + experimental: false + feature: seal5testalucvaddns + vendor: false + version: '1.0' + Seal5Test_alu_cv_addNu: + arch: xseal5testalucvaddnu + experimental: false + feature: seal5testalucvaddnu + vendor: false + version: '1.0' + Seal5Test_alu_cv_addRNrs: + arch: xseal5testalucvaddrnrs + experimental: false + feature: seal5testalucvaddrnrs + vendor: false + version: '1.0' + Seal5Test_alu_cv_addRNru: + arch: xseal5testalucvaddrnru + experimental: false + feature: seal5testalucvaddrnru + vendor: false + version: '1.0' + Seal5Test_alu_cv_addRNs: + arch: xseal5testalucvaddrns + experimental: false + feature: seal5testalucvaddrns + vendor: false + version: '1.0' + Seal5Test_alu_cv_addRNu: + arch: xseal5testalucvaddrnu + experimental: false + feature: seal5testalucvaddrnu + vendor: false + version: '1.0' + Seal5Test_alu_cv_maxs: + arch: xseal5testalucvmaxs + experimental: false + feature: seal5testalucvmaxs + vendor: false + version: '1.0' + Seal5Test_alu_cv_maxu: + arch: xseal5testalucvmaxu + experimental: false + feature: seal5testalucvmaxu + vendor: false + version: '1.0' + Seal5Test_alu_cv_mins: + arch: xseal5testalucvmins + experimental: false + feature: seal5testalucvmins + vendor: false + version: '1.0' + Seal5Test_alu_cv_minu: + arch: xseal5testalucvminu + experimental: false + feature: seal5testalucvminu + vendor: false + version: '1.0' + Seal5Test_alu_cv_slets: + arch: xseal5testalucvslets + experimental: false + feature: seal5testalucvslets + vendor: false + version: '1.0' + Seal5Test_alu_cv_sletu: + arch: xseal5testalucvsletu + experimental: false + feature: seal5testalucvsletu + vendor: false + version: '1.0' + Seal5Test_alu_cv_subNrs: + arch: xseal5testalucvsubnrs + experimental: false + feature: seal5testalucvsubnrs + vendor: false + version: '1.0' + Seal5Test_alu_cv_subNru: + arch: xseal5testalucvsubnru + experimental: false + feature: seal5testalucvsubnru + vendor: false + version: '1.0' + Seal5Test_alu_cv_subNs: + arch: xseal5testalucvsubns + experimental: false + feature: seal5testalucvsubns + vendor: false + version: '1.0' + Seal5Test_alu_cv_subNu: + arch: xseal5testalucvsubnu + experimental: false + feature: seal5testalucvsubnu + vendor: false + version: '1.0' + Seal5Test_alu_cv_subRNrs: + arch: xseal5testalucvsubrnrs + experimental: false + feature: seal5testalucvsubrnrs + vendor: false + version: '1.0' + Seal5Test_alu_cv_subRNru: + arch: xseal5testalucvsubrnru + experimental: false + feature: seal5testalucvsubrnru + vendor: false + version: '1.0' + Seal5Test_alu_cv_subRNs: + arch: xseal5testalucvsubrns + experimental: false + feature: seal5testalucvsubrns + vendor: false + version: '1.0' + Seal5Test_alu_cv_subRNu: + arch: xseal5testalucvsubrnu + experimental: false + feature: seal5testalucvsubrnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_machhNs: + arch: xseal5testmaccvmachhns + experimental: false + feature: seal5testmaccvmachhns + vendor: false + version: '1.0' + Seal5Test_mac_cv_machhNu: + arch: xseal5testmaccvmachhnu + experimental: false + feature: seal5testmaccvmachhnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_machhRNs: + arch: xseal5testmaccvmachhrns + experimental: false + feature: seal5testmaccvmachhrns + vendor: false + version: '1.0' + Seal5Test_mac_cv_machhRNu: + arch: xseal5testmaccvmachhrnu + experimental: false + feature: seal5testmaccvmachhrnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_macNs: + arch: xseal5testmaccvmacns + experimental: false + feature: seal5testmaccvmacns + vendor: false + version: '1.0' + Seal5Test_mac_cv_macNu: + arch: xseal5testmaccvmacnu + experimental: false + feature: seal5testmaccvmacnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_macRNs: + arch: xseal5testmaccvmacrns + experimental: false + feature: seal5testmaccvmacrns + vendor: false + version: '1.0' + Seal5Test_mac_cv_macRNu: + arch: xseal5testmaccvmacrnu + experimental: false + feature: seal5testmaccvmacrnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_macs: + arch: xseal5testmaccvmacs + experimental: false + feature: seal5testmaccvmacs + vendor: false + version: '1.0' + Seal5Test_mac_cv_macu: + arch: xseal5testmaccvmacu + experimental: false + feature: seal5testmaccvmacu + vendor: false + version: '1.0' + Seal5Test_mac_cv_msus: + arch: xseal5testmaccvmsus + experimental: false + feature: seal5testmaccvmsus + vendor: false + version: '1.0' + Seal5Test_mac_cv_msuu: + arch: xseal5testmaccvmsuu + experimental: false + feature: seal5testmaccvmsuu + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulhhNs: + arch: xseal5testmaccvmulhhns + experimental: false + feature: seal5testmaccvmulhhns + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulhhNu: + arch: xseal5testmaccvmulhhnu + experimental: false + feature: seal5testmaccvmulhhnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulhhRNs: + arch: xseal5testmaccvmulhhrns + experimental: false + feature: seal5testmaccvmulhhrns + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulhhRNu: + arch: xseal5testmaccvmulhhrnu + experimental: false + feature: seal5testmaccvmulhhrnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulNs: + arch: xseal5testmaccvmulns + experimental: false + feature: seal5testmaccvmulns + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulNu: + arch: xseal5testmaccvmulnu + experimental: false + feature: seal5testmaccvmulnu + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulRNs: + arch: xseal5testmaccvmulrns + experimental: false + feature: seal5testmaccvmulrns + vendor: false + version: '1.0' + Seal5Test_mac_cv_mulRNu: + arch: xseal5testmaccvmulrnu + experimental: false + feature: seal5testmaccvmulrnu + vendor: false + version: '1.0' +passes: + per_model: + all_v2: + overrides: + convert_models: + prefix: "GEN_" diff --git a/examples/cfg/gen/riscv.yml b/examples/cfg/gen/riscv.yml new file mode 100644 index 00000000..d1350f27 --- /dev/null +++ b/examples/cfg/gen/riscv.yml @@ -0,0 +1,41 @@ +--- +riscv: + xlen: 32 + features: + - m + - fast-unaligned-access + # - gpr32v +riscv: + legalization: + gisel: + ops: + - name: + - G_ABS + onlyif: + - HasExtseal5testalucvabs + types: + - s32 + - name: + - G_UMIN + onlyif: + - HasExtseal5testalucvminu + types: + - s32 + - name: + - G_SMIN + onlyif: + - HasExtseal5testalucvmins + types: + - s32 + - name: + - G_UMAX + onlyif: + - HasExtseal5testalucvmaxu + types: + - s32 + - name: + - G_SMAX + onlyif: + - HasExtseal5testalucvmaxs + types: + - s32 diff --git a/examples/cfg/passes.yml b/examples/cfg/passes.yml new file mode 100644 index 00000000..9354d67e --- /dev/null +++ b/examples/cfg/passes.yml @@ -0,0 +1,6 @@ +--- +passes: + defaults: + overrides: + behav_to_pat: + parallel: true diff --git a/examples/cfg/s4e-mac.yml b/examples/cfg/s4e/s4e-mac.yml similarity index 100% rename from examples/cfg/s4e-mac.yml rename to examples/cfg/s4e/s4e-mac.yml diff --git a/examples/cfg/tumeda/OpenASIP.yml b/examples/cfg/tumeda/OpenASIP.yml new file mode 100644 index 00000000..d9d53a39 --- /dev/null +++ b/examples/cfg/tumeda/OpenASIP.yml @@ -0,0 +1,12 @@ +--- +extensions: + XISE: + version: "1.0" + experimental: true + vendor: true +passes: + per_model: + OpenASIP: + overrides: + convert_models: + prefix: "SEAL5_" diff --git a/examples/cfg/xcorev/filter.yml b/examples/cfg/xcorev/filter.yml new file mode 100644 index 00000000..fc0d0c70 --- /dev/null +++ b/examples/cfg/xcorev/filter.yml @@ -0,0 +1,8 @@ +--- +filter: + sets: + drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode] + instructions: + drop: [SEAL5_CV_CLIPU, SEAL5_CV_CLIPR, SEAL5_CV_CLIPUR, SEAL5_CV_SLET, SEAL5_CV_SLETU, SEAL5_CV_PACK, SEAL5_CV_PACKLO_B] + opcodes: + keep: [custom-0, custom-1, custom-2 ,custom-3, 0b00000, OP-P, OP] diff --git a/examples/cfg/xcorev/riscv.yml b/examples/cfg/xcorev/riscv.yml new file mode 100644 index 00000000..04117f55 --- /dev/null +++ b/examples/cfg/xcorev/riscv.yml @@ -0,0 +1,21 @@ +--- +riscv: + xlen: 32 + features: + - m + - fast-unaligned-access + - gpr32v + legalization: + gisel: + ops: + # TODO: simd shift? + # TODO: rotate left/right? + # - name: [G_SMAX, G_UMAX, G_SMIN, G_UMIN, G_ABS] + # types: [s32] + # onlyif: [HasVendorXCValu] + # - name: [G_ADD, G_SUB, G_AND, G_OR, G_XOR, G_ASHR, G_LSHR, G_SHL] + # types: [v4i8, v2i16] + # onlyif: [HasVendorXCVsimd] + # - name: G_INSERT_VECTOR_ELT + # types: [v4i8, v2i16] + # onlyif: [HasVendorXCVsimd] From 49c4b62f84fe1f50f9272fa06eab4a9938f48cef Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 20 Mar 2024 15:08:42 +0100 Subject: [PATCH 56/80] provide smaller demo scripts (grouped by corev, gen, s4e) --- examples/corev_demo.py | 155 +++++++++++++++++++++++++++++++++++++++++ examples/gen_demo.py | 141 +++++++++++++++++++++++++++++++++++++ examples/s4e_demo.py | 141 +++++++++++++++++++++++++++++++++++++ 3 files changed, 437 insertions(+) create mode 100644 examples/corev_demo.py create mode 100644 examples/gen_demo.py create mode 100644 examples/s4e_demo.py diff --git a/examples/corev_demo.py b/examples/corev_demo.py new file mode 100644 index 00000000..d75127ec --- /dev/null +++ b/examples/corev_demo.py @@ -0,0 +1,155 @@ +# +# Copyright (c) 2023 TUM Department of Electrical and Computer Engineering. +# +# This file is part of Seal5. +# See https://github.com/tum-ei-eda/seal5.git for further info. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +"""Demo script for Seal5 Python API.""" +import os + +# import logging +from pathlib import Path + +from seal5.flow import Seal5Flow +from seal5.logging import set_log_level +from seal5.types import PatchStage + +# set_log_level(console_level=logging.DEBUG, file_level=logging.DEBUG) +set_log_level(console_level="DEBUG", file_level="DEBUG") + +EXAMPLES_DIR = Path(os.path.dirname(os.path.realpath(__file__))) +VERBOSE = bool(int(os.environ.get("VERBOSE", 0))) +FAST = bool(int(os.environ.get("FAST", 1))) +SKIP_PATTERNS = bool(int(os.environ.get("SKIP_PATTERNS", 0))) +INTERACTIVE = bool(int(os.environ.get("INTERACTIVE", 0))) +PREPATCHED = bool(int(os.environ.get("PREPATCHED", 1))) +BUILD_CONFIG = os.environ.get("BUILD_CONFIG", "release") + + +seal5_flow = Seal5Flow("/tmp/seal5_llvm_corev", "corev") + +# Optional: clean existing settings/models for fresh run +seal5_flow.reset(settings=True, interactive=False) +seal5_flow.clean(temp=True, patches=True, models=True, inputs=True, interactive=INTERACTIVE) + +if PREPATCHED: + if seal5_flow.repo is None or "seal5-corev-stage0" not in seal5_flow.repo.tags: + raise RuntimeError("PREPATCHED can only be used after LLVM was patched at least once.") + +# Clone LLVM and init seal5 metadata directory +seal5_flow.initialize( + clone=True, + clone_url="https://github.com/llvm/llvm-project.git", + # clone_ref="llvmorg-17.0.6", + clone_ref="seal5-corev-stage0" if PREPATCHED else "llvmorg-18.1.0-rc3", + force=True, + verbose=VERBOSE, +) + +# Load CoreDSL inputs +cdsl_files = [ + # XCOREV + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMac.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVAlu.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBitmanip.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVSimd.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMem.core_desc", + # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBranchImmediate.core_desc", +] +seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True) + +# Load test inputs +test_files = [ + # EXAMPLES_DIR / "tests" / "xcorev" / "cv_abs.test.c", + # EXAMPLES_DIR / "tests" / "corev" / "*.asm.s", + # EXAMPLES_DIR / "tests" / "corev" / "*.invalid-asm.s", + EXAMPLES_DIR / "tests" / "corev" / "*.inline-asm.c", +] +seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) + +# Load YAML inputs +cfg_files = [ + # XCOREV + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMac.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVAlu.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBitmanip.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVSimd.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMem.yml", + # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBranchImmediate.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "filter.yml", + EXAMPLES_DIR / "cfg" / "xcorev" / "riscv.yml", + EXAMPLES_DIR / "cfg" / "llvm.yml", + EXAMPLES_DIR / "cfg" / "patches.yml", + EXAMPLES_DIR / "cfg" / "tests.yml", + EXAMPLES_DIR / "cfg" / "passes.yml", + EXAMPLES_DIR / "cfg" / "git.yml", +] +seal5_flow.load(cfg_files, verbose=VERBOSE, overwrite=False) + +# Override settings from Python +seal5_flow.settings.llvm.default_config = BUILD_CONFIG + +# Clone & install Seal5 dependencies +# 1. CDSL2LLVM (add PHASE_0 patches) +seal5_flow.setup(force=True, verbose=VERBOSE) + +# Apply initial patches +if not PREPATCHED: + seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_0]) + +if not FAST: + # Build initial LLVM + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) + +# Transform inputs +# 1. Create M2-ISA-R metamodel +# 2. Convert to Seal5 metamodel (including aliases, builtins,...) +# 3. Analyse/optimize instructions +seal5_flow.transform(verbose=VERBOSE) + +# Generate patches (except Patterns) +seal5_flow.generate(verbose=VERBOSE, skip=["pattern_gen"]) + +# Apply next patches +seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_1, PatchStage.PHASE_2]) + +if not FAST: + # Build patched LLVM + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) +if not SKIP_PATTERNS: + # Build PatternGen & llc + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="pattern-gen") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="llc") + + # Generate remaining patches + seal5_flow.generate(verbose=VERBOSE, only=["pattern_gen"]) + + # Apply patches + seal5_flow.patch(verbose=VERBOSE, stages=list(range(PatchStage.PHASE_3, PatchStage.PHASE_5 + 1))) + +# Build patched LLVM +seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) + +# Test patched LLVM +seal5_flow.test(verbose=VERBOSE, ignore_error=True) + +# Deploy patched LLVM (combine commits and create tag) +seal5_flow.deploy(verbose=VERBOSE) + +# Export patches, logs, reports +seal5_flow.export("/tmp/seal5_llvm_corev.tar.gz", verbose=VERBOSE) + +# Optional: cleanup temorary files, build dirs,... +# seal5.clean(temp=True, build=True, deps=True, interactive=INTERACTIVE) diff --git a/examples/gen_demo.py b/examples/gen_demo.py new file mode 100644 index 00000000..7acfafd1 --- /dev/null +++ b/examples/gen_demo.py @@ -0,0 +1,141 @@ +# +# Copyright (c) 2023 TUM Department of Electrical and Computer Engineering. +# +# This file is part of Seal5. +# See https://github.com/tum-ei-eda/seal5.git for further info. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +"""Demo script for Seal5 Python API.""" +import os + +# import logging +from pathlib import Path + +from seal5.flow import Seal5Flow +from seal5.logging import set_log_level +from seal5.types import PatchStage + +# set_log_level(console_level=logging.DEBUG, file_level=logging.DEBUG) +set_log_level(console_level="DEBUG", file_level="DEBUG") + +EXAMPLES_DIR = Path(os.path.dirname(os.path.realpath(__file__))) +# VERBOSE = False +VERBOSE = bool(int(os.environ.get("VERBOSE", 0))) +FAST = bool(int(os.environ.get("FAST", 1))) +SKIP_PATTERNS = bool(int(os.environ.get("SKIP_PATTERNS", 0))) +INTERACTIVE = bool(int(os.environ.get("INTERACTIVE", 0))) +PREPATCHED = bool(int(os.environ.get("PREPATCHED", 1))) +BUILD_CONFIG = os.environ.get("BUILD_CONFIG", "release") + + +seal5_flow = Seal5Flow("/tmp/seal5_llvm_gen", "gen") + +# Optional: clean existing settings/models for fresh run +seal5_flow.reset(settings=True, interactive=False) +seal5_flow.clean(temp=True, patches=True, models=True, inputs=True, interactive=INTERACTIVE) + +if PREPATCHED: + if seal5_flow.repo is None or "seal5-gen-stage0" not in seal5_flow.repo.tags: + raise RuntimeError("PREPATCHED can only be used after LLVM was patched at least once.") + +# Clone LLVM and init seal5 metadata directory +seal5_flow.initialize( + clone=True, + clone_url="https://github.com/llvm/llvm-project.git", + # clone_ref="llvmorg-17.0.6", + clone_ref="seal5-gen-stage0" if PREPATCHED else "llvmorg-18.1.0-rc3", + force=True, + verbose=VERBOSE, +) + +# Load CoreDSL inputs +cdsl_files = [ + EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v5.core_desc", +] +seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True) + +# Load test inputs +test_files = [ +] +seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) + +# Load YAML inputs +cfg_files = [ + # GENERATED + EXAMPLES_DIR / "cfg" / "gen" / "all.yml", + EXAMPLES_DIR / "cfg" / "gen" / "riscv.yml", + EXAMPLES_DIR / "cfg" / "llvm.yml", + EXAMPLES_DIR / "cfg" / "filter.yml", + EXAMPLES_DIR / "cfg" / "patches.yml", + EXAMPLES_DIR / "cfg" / "tests.yml", + EXAMPLES_DIR / "cfg" / "passes.yml", + EXAMPLES_DIR / "cfg" / "git.yml", +] +seal5_flow.load(cfg_files, verbose=VERBOSE, overwrite=False) + +# Override settings from Python +seal5_flow.settings.llvm.default_config = BUILD_CONFIG + +# Clone & install Seal5 dependencies +# 1. CDSL2LLVM (add PHASE_0 patches) +seal5_flow.setup(force=True, verbose=VERBOSE) + +# Apply initial patches +if not PREPATCHED: + seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_0]) + +if not FAST: + # Build initial LLVM + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) + +# Transform inputs +# 1. Create M2-ISA-R metamodel +# 2. Convert to Seal5 metamodel (including aliases, builtins,...) +# 3. Analyse/optimize instructions +seal5_flow.transform(verbose=VERBOSE) + +# Generate patches (except Patterns) +seal5_flow.generate(verbose=VERBOSE, skip=["pattern_gen"]) + +# Apply next patches +seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_1, PatchStage.PHASE_2]) + +if not FAST: + # Build patched LLVM + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) +if not SKIP_PATTERNS: + # Build PatternGen & llc + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="pattern-gen") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="llc") + + # Generate remaining patches + seal5_flow.generate(verbose=VERBOSE, only=["pattern_gen"]) + + # Apply patches + seal5_flow.patch(verbose=VERBOSE, stages=list(range(PatchStage.PHASE_3, PatchStage.PHASE_5 + 1))) + +# Build patched LLVM +seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) + +# Test patched LLVM +seal5_flow.test(verbose=VERBOSE, ignore_error=True) + +# Deploy patched LLVM (combine commits and create tag) +seal5_flow.deploy(verbose=VERBOSE) + +# Export patches, logs, reports +seal5_flow.export("/tmp/seal5_llvm_gen.tar.gz", verbose=VERBOSE) + +# Optional: cleanup temorary files, build dirs,... +# seal5.clean(temp=True, build=True, deps=True, interactive=INTERACTIVE) diff --git a/examples/s4e_demo.py b/examples/s4e_demo.py new file mode 100644 index 00000000..41d8182a --- /dev/null +++ b/examples/s4e_demo.py @@ -0,0 +1,141 @@ +# +# Copyright (c) 2023 TUM Department of Electrical and Computer Engineering. +# +# This file is part of Seal5. +# See https://github.com/tum-ei-eda/seal5.git for further info. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +"""Demo script for Seal5 Python API.""" +import os + +# import logging +from pathlib import Path + +from seal5.flow import Seal5Flow +from seal5.logging import set_log_level +from seal5.types import PatchStage + +# set_log_level(console_level=logging.DEBUG, file_level=logging.DEBUG) +set_log_level(console_level="DEBUG", file_level="DEBUG") + +EXAMPLES_DIR = Path(os.path.dirname(os.path.realpath(__file__))) +# VERBOSE = False +VERBOSE = bool(int(os.environ.get("VERBOSE", 0))) +FAST = bool(int(os.environ.get("FAST", 1))) +SKIP_PATTERNS = bool(int(os.environ.get("SKIP_PATTERNS", 0))) +INTERACTIVE = bool(int(os.environ.get("INTERACTIVE", 0))) +PREPATCHED = bool(int(os.environ.get("PREPATCHED", 1))) +BUILD_CONFIG = os.environ.get("BUILD_CONFIG", "release") + + +seal5_flow = Seal5Flow("/tmp/seal5_llvm_s4e", "s4e") + +# Optional: clean existing settings/models for fresh run +seal5_flow.reset(settings=True, interactive=False) +seal5_flow.clean(temp=True, patches=True, models=True, inputs=True, interactive=INTERACTIVE) + +if PREPATCHED: + if seal5_flow.repo is None or "seal5-s4e-stage0" not in seal5_flow.repo.tags: + raise RuntimeError("PREPATCHED can only be used after LLVM was patched at least once.") + +# Clone LLVM and init seal5 metadata directory +seal5_flow.initialize( + clone=True, + clone_url="https://github.com/llvm/llvm-project.git", + # clone_ref="llvmorg-17.0.6", + clone_ref="seal5-s4e-stage0" if PREPATCHED else "llvmorg-18.1.0-rc3", + force=True, + verbose=VERBOSE, +) + +# Load CoreDSL inputs +cdsl_files = [ + EXAMPLES_DIR / "cdsl" / "rv_s4e" / "s4e-mac.core_desc", +] +seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True) + +# Load test inputs +test_files = [ + # TODO: add s4e test files +] +seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) + +# Load YAML inputs +cfg_files = [ + EXAMPLES_DIR / "cfg" / "s4e" / "???.yml", + EXAMPLES_DIR / "cfg" / "llvm.yml", + EXAMPLES_DIR / "cfg" / "filter.yml", + EXAMPLES_DIR / "cfg" / "patches.yml", + EXAMPLES_DIR / "cfg" / "riscv.yml", + EXAMPLES_DIR / "cfg" / "tests.yml", + EXAMPLES_DIR / "cfg" / "passes.yml", + EXAMPLES_DIR / "cfg" / "git.yml", +] +seal5_flow.load(cfg_files, verbose=VERBOSE, overwrite=False) + +# Override settings from Python +seal5_flow.settings.llvm.default_config = BUILD_CONFIG + +# Clone & install Seal5 dependencies +# 1. CDSL2LLVM (add PHASE_0 patches) +seal5_flow.setup(force=True, verbose=VERBOSE) + +# Apply initial patches +if not PREPATCHED: + seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_0]) + +if not FAST: + # Build initial LLVM + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) + +# Transform inputs +# 1. Create M2-ISA-R metamodel +# 2. Convert to Seal5 metamodel (including aliases, builtins,...) +# 3. Analyse/optimize instructions +seal5_flow.transform(verbose=VERBOSE) + +# Generate patches (except Patterns) +seal5_flow.generate(verbose=VERBOSE, skip=["pattern_gen"]) + +# Apply next patches +seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_1, PatchStage.PHASE_2]) + +if not FAST: + # Build patched LLVM + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) +if not SKIP_PATTERNS: + # Build PatternGen & llc + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="pattern-gen") + seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG, target="llc") + + # Generate remaining patches + seal5_flow.generate(verbose=VERBOSE, only=["pattern_gen"]) + + # Apply patches + seal5_flow.patch(verbose=VERBOSE, stages=list(range(PatchStage.PHASE_3, PatchStage.PHASE_5 + 1))) + +# Build patched LLVM +seal5_flow.build(verbose=VERBOSE, config=BUILD_CONFIG) + +# Test patched LLVM +seal5_flow.test(verbose=VERBOSE, ignore_error=True) + +# Deploy patched LLVM (combine commits and create tag) +seal5_flow.deploy(verbose=VERBOSE) + +# Export patches, logs, reports +seal5_flow.export("/tmp/seal5_llvm_s4e.tar.gz", verbose=VERBOSE) + +# Optional: cleanup temorary files, build dirs,... +# seal5.clean(temp=True, build=True, deps=True, interactive=INTERACTIVE) From a748ae47e2fd770e40b5ca102afae77da8bc54ad Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Fri, 22 Mar 2024 11:50:27 +0100 Subject: [PATCH 57/80] notes --- .../cv_machhNs.core_desc | 17 + .../Seal5Test_mac_cv_machhNs/cv_machhNs.gmir | 125 + .../Seal5Test_mac_cv_machhNs/cv_machhNs.ll | 23 + .../Seal5Test_mac_cv_machhNs/cv_machhNs.td | 8 + .../cv_machhNs.td.out | 1 + .../cv_machhNs.td.pat | 1 + .../cv_macs_i16.core_desc | 16 + .../cv_macs_i16.gmir | 112 + .../Seal5Test_mac_cv_macs_i16/cv_macs_i16.ll | 21 + .../Seal5Test_mac_cv_macs_i16/cv_macs_i16.td | 8 + .../cv_macs_i16.td.out | 1 + .../cv_macs_i16.td.pat | 1 + .../cv_macs_i32.core_desc | 16 + .../cv_macs_i32.gmir | 98 + .../Seal5Test_mac_cv_macs_i32/cv_macs_i32.ll | 17 + .../Seal5Test_mac_cv_macs_i32/cv_macs_i32.td | 8 + .../cv_macs_i32.td.out | 1 + .../cv_macs_i32.td.pat | 1 + notes/macshh_gisel/cecil_test.c | 123 + notes/macshh_gisel/cmd.txt | 1 + notes/macshh_gisel/diff.txt | 20 + notes/macshh_gisel/err.txt | 12090 ++++++++++++++++ 22 files changed, 12709 insertions(+) create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.core_desc create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.gmir create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.ll create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.out create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.pat create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.core_desc create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.gmir create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.ll create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.out create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.pat create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.core_desc create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.gmir create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.ll create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.out create mode 100644 notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.pat create mode 100644 notes/macshh_gisel/cecil_test.c create mode 100644 notes/macshh_gisel/cmd.txt create mode 100644 notes/macshh_gisel/diff.txt create mode 100644 notes/macshh_gisel/err.txt diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.core_desc b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.core_desc new file mode 100644 index 00000000..1ffb438d --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.core_desc @@ -0,0 +1,17 @@ +InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { + instructions { + cv_machhNs { + operands: { + unsigned<5> rd [[is_reg]] [[inout]]; + unsigned<5> rs1 [[is_reg]] [[in]]; + unsigned<5> rs2 [[is_reg]] [[in]]; + unsigned<5> Is3 [[is_imm]] [[in]]; + } + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"; + behavior: { + X[rd] = ((signed<16>)((X[rs1])[31:16]) * (signed<16>)((X[rs2])[31:16]) + (signed)((X[rd])) >> (unsigned<5>)((Is3)))[31:0]; + } + } + } +} diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.gmir b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.gmir new file mode 100644 index 00000000..de0dadaf --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.gmir @@ -0,0 +1,125 @@ +--- | + ; ModuleID = '/tmp/seal5_llvm_gen/.seal5/temp/all_v9/Seal5Test_mac_cv_machhNs/cv_machhNs.ll' + source_filename = "mod" + target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" + target triple = "riscv32-unknown-unknown-elf" + + ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) + define void @implcv_machhNs(ptr noalias nocapture %rd, ptr nocapture readonly %rs1, ptr nocapture readonly %rs2, i32 %Is3) local_unnamed_addr #0 { + %1 = getelementptr i16, ptr %rs1, i32 1 + %.v = load i16, ptr %1, align 2 + %2 = getelementptr i16, ptr %rs2, i32 1 + %.v1 = load i16, ptr %2, align 2 + %3 = sext i16 %.v to i32 + %4 = sext i16 %.v1 to i32 + %5 = mul nsw i32 %4, %3 + %rd.v = load i32, ptr %rd, align 4 + %6 = add i32 %5, %rd.v + %7 = and i32 %Is3, 31 + %8 = ashr i32 %6, %7 + store i32 %8, ptr %rd, align 4 + ret void + } + + attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) } + +... +--- +name: implcv_machhNs +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } + - { id: 8, class: _, preferred-register: '' } + - { id: 9, class: _, preferred-register: '' } + - { id: 10, class: _, preferred-register: '' } + - { id: 11, class: _, preferred-register: '' } + - { id: 12, class: _, preferred-register: '' } + - { id: 13, class: _, preferred-register: '' } + - { id: 14, class: _, preferred-register: '' } + - { id: 15, class: _, preferred-register: '' } + - { id: 16, class: _, preferred-register: '' } + - { id: 17, class: _, preferred-register: '' } +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x11', virtual-reg: '' } + - { reg: '$x12', virtual-reg: '' } + - { reg: '$x13', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $x11, $x12, $x13 + + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + %3:_(s32) = COPY $x13 + %15:_(s32) = G_CONSTANT i32 31 + %4:_(s32) = G_CONSTANT i32 2 + %5:_(p0) = G_PTR_ADD %1, %4(s32) + %6:_(s16) = G_LOAD %5(p0) :: (load (s16) from %ir.1) + %7:_(s32) = G_CONSTANT i32 2 + %8:_(p0) = G_PTR_ADD %2, %7(s32) + %9:_(s16) = G_LOAD %8(p0) :: (load (s16) from %ir.2) + %10:_(s32) = G_SEXT %6(s16) + %11:_(s32) = G_SEXT %9(s16) + %12:_(s32) = nsw G_MUL %11, %10 + %13:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.rd) + %14:_(s32) = G_ADD %12, %13 + %16:_(s32) = G_AND %3, %15 + %17:_(s32) = G_ASHR %14, %16(s32) + G_STORE %17(s32), %0(p0) :: (store (s32) into %ir.rd) + PseudoRET + +... diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.ll b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.ll new file mode 100644 index 00000000..ff40740f --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.ll @@ -0,0 +1,23 @@ +; ModuleID = 'mod' +source_filename = "mod" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-linux-gnu" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) +define void @implcv_machhNs(ptr noalias nocapture %rd, ptr nocapture readonly %rs1, ptr nocapture readonly %rs2, i32 %Is3) local_unnamed_addr #0 { + %1 = getelementptr i16, ptr %rs1, i32 1 + %.v = load i16, ptr %1, align 2 + %2 = getelementptr i16, ptr %rs2, i32 1 + %.v1 = load i16, ptr %2, align 2 + %3 = sext i16 %.v to i32 + %4 = sext i16 %.v1 to i32 + %5 = mul nsw i32 %4, %3 + %rd.v = load i32, ptr %rd, align 4 + %6 = add i32 %5, %rd.v + %7 = and i32 %Is3, 31 + %8 = ashr i32 %6, %7 + store i32 %8, ptr %rd, align 4 + ret void +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) } diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td new file mode 100644 index 00000000..b6caf7f0 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td @@ -0,0 +1,8 @@ +let Predicates = [HasVendorSeal5TestmaccvmachhNs] in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def cv_machhNs_ : RVInst_cv_machhNs<(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; + +def : Pat< + (i32 (i32 (sra (add (mul (i32 (sra (i32 (shl (i32 (srl GPR:$rs2, (i32 16))), (i32 16))), (i32 16))), (i32 (sra (i32 (shl (i32 (srl GPR:$rs1, (i32 16))), (i32 16))), (i32 16)))), GPR:$rd), (and (i32 uimm5:$Is3), (i32 31))))), + (cv_machhNs_ GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; + +} diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.out b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.out new file mode 100644 index 00000000..97cce984 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.out @@ -0,0 +1 @@ +Pattern for cv_machhNs: (i32 (sra (add (mul (i32 (sra (i32 (shl (i32 (srl GPR:$rs2, (i32 16))), (i32 16))), (i32 16))), (i32 (sra (i32 (shl (i32 (srl GPR:$rs1, (i32 16))), (i32 16))), (i32 16)))), GPR:$rd), (and (i32 uimm5:$Is3), (i32 31)))) diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.pat b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.pat new file mode 100644 index 00000000..c9e225ae --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_machhNs/cv_machhNs.td.pat @@ -0,0 +1 @@ + (i32 (sra (add (mul (i32 (sra (i32 (shl (i32 (srl GPR:$rs2, (i32 16))), (i32 16))), (i32 16))), (i32 (sra (i32 (shl (i32 (srl GPR:$rs1, (i32 16))), (i32 16))), (i32 16)))), GPR:$rd), (and (i32 uimm5:$Is3), (i32 31)))) \ No newline at end of file diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.core_desc b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.core_desc new file mode 100644 index 00000000..c19491cb --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.core_desc @@ -0,0 +1,16 @@ +InstructionSet Seal5Test_mac_cv_macs_i16 extends RV32I { + instructions { + cv_macs_i16 { + operands: { + unsigned<5> rd [[is_reg]] [[inout]]; + unsigned<5> rs1 [[is_reg]] [[in]]; + unsigned<5> rs2 [[is_reg]] [[in]]; + } + encoding: 7'b0101100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + behavior: { + X[rd] = ((signed<16>)((X[rs1])) * (signed<16>)((X[rs2])) + (signed)((X[rd])))[31:0]; + } + } + } +} diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.gmir b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.gmir new file mode 100644 index 00000000..0628bc8f --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.gmir @@ -0,0 +1,112 @@ +--- | + ; ModuleID = '/tmp/seal5_llvm_gen/.seal5/temp/all_v9/Seal5Test_mac_cv_macs_i16/cv_macs_i16.ll' + source_filename = "mod" + target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" + target triple = "riscv32-unknown-unknown-elf" + + ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) + define void @implcv_macs_i16(ptr noalias nocapture %rd, ptr nocapture readonly %rs1, ptr nocapture readonly %rs2) local_unnamed_addr #0 { + %rs1.v = load i32, ptr %rs1, align 4 + %rs2.v = load i32, ptr %rs2, align 4 + %sext = shl i32 %rs1.v, 16 + %1 = ashr exact i32 %sext, 16 + %sext1 = shl i32 %rs2.v, 16 + %2 = ashr exact i32 %sext1, 16 + %3 = mul nsw i32 %2, %1 + %rd.v = load i32, ptr %rd, align 4 + %4 = add i32 %3, %rd.v + store i32 %4, ptr %rd, align 4 + ret void + } + + attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) } + +... +--- +name: implcv_macs_i16 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } + - { id: 8, class: _, preferred-register: '' } + - { id: 9, class: _, preferred-register: '' } + - { id: 10, class: _, preferred-register: '' } + - { id: 11, class: _, preferred-register: '' } + - { id: 12, class: _, preferred-register: '' } +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x11', virtual-reg: '' } + - { reg: '$x12', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $x11, $x12 + + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + %5:_(s32) = G_CONSTANT i32 16 + %3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.rs1) + %4:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.rs2) + %6:_(s32) = G_SHL %3, %5(s32) + %7:_(s32) = exact G_ASHR %6, %5(s32) + %8:_(s32) = G_SHL %4, %5(s32) + %9:_(s32) = exact G_ASHR %8, %5(s32) + %10:_(s32) = nsw G_MUL %9, %7 + %11:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.rd) + %12:_(s32) = G_ADD %10, %11 + G_STORE %12(s32), %0(p0) :: (store (s32) into %ir.rd) + PseudoRET + +... diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.ll b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.ll new file mode 100644 index 00000000..8a363bea --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.ll @@ -0,0 +1,21 @@ +; ModuleID = 'mod' +source_filename = "mod" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-linux-gnu" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) +define void @implcv_macs_i16(ptr noalias nocapture %rd, ptr nocapture readonly %rs1, ptr nocapture readonly %rs2) local_unnamed_addr #0 { + %rs1.v = load i32, ptr %rs1, align 4 + %rs2.v = load i32, ptr %rs2, align 4 + %sext = shl i32 %rs1.v, 16 + %1 = ashr exact i32 %sext, 16 + %sext1 = shl i32 %rs2.v, 16 + %2 = ashr exact i32 %sext1, 16 + %3 = mul nsw i32 %2, %1 + %rd.v = load i32, ptr %rd, align 4 + %4 = add i32 %3, %rd.v + store i32 %4, ptr %rd, align 4 + ret void +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) } diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td new file mode 100644 index 00000000..3b981457 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td @@ -0,0 +1,8 @@ +let Predicates = [HasVendorSeal5Testmaccvmacsi16] in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def cv_macs_i16_ : RVInst_cv_macs_i16<(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2)>; + +def : Pat< + (i32 (add (mul (i32 (sra (i32 (shl GPR:$rs2, (i32 16))), (i32 16))), (i32 (sra (i32 (shl GPR:$rs1, (i32 16))), (i32 16)))), GPR:$rd)), + (cv_macs_i16_ GPR:$rd, GPR:$rs1, GPR:$rs2)>; + +} diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.out b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.out new file mode 100644 index 00000000..d971b99e --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.out @@ -0,0 +1 @@ +Pattern for cv_macs_i16: (add (mul (i32 (sra (i32 (shl GPR:$rs2, (i32 16))), (i32 16))), (i32 (sra (i32 (shl GPR:$rs1, (i32 16))), (i32 16)))), GPR:$rd) diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.pat b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.pat new file mode 100644 index 00000000..24b89983 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i16/cv_macs_i16.td.pat @@ -0,0 +1 @@ + (add (mul (i32 (sra (i32 (shl GPR:$rs2, (i32 16))), (i32 16))), (i32 (sra (i32 (shl GPR:$rs1, (i32 16))), (i32 16)))), GPR:$rd) \ No newline at end of file diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.core_desc b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.core_desc new file mode 100644 index 00000000..d2684e0f --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.core_desc @@ -0,0 +1,16 @@ +InstructionSet Seal5Test_mac_cv_macs_i32 extends RV32I { + instructions { + cv_macs_i32 { + operands: { + unsigned<5> rd [[is_reg]] [[inout]]; + unsigned<5> rs1 [[is_reg]] [[in]]; + unsigned<5> rs2 [[is_reg]] [[in]]; + } + encoding: 7'b0101110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}"; + behavior: { + X[rd] = ((signed)((X[rs1])) * (signed)((X[rs2])) + (signed)((X[rd])))[31:0]; + } + } + } +} diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.gmir b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.gmir new file mode 100644 index 00000000..e0068161 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.gmir @@ -0,0 +1,98 @@ +--- | + ; ModuleID = '/tmp/seal5_llvm_gen/.seal5/temp/all_v9/Seal5Test_mac_cv_macs_i32/cv_macs_i32.ll' + source_filename = "mod" + target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" + target triple = "riscv32-unknown-unknown-elf" + + ; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) + define void @implcv_macs_i32(ptr noalias nocapture %rd, ptr nocapture readonly %rs1, ptr nocapture readonly %rs2) local_unnamed_addr #0 { + %rs1.v = load i32, ptr %rs1, align 4 + %rs2.v = load i32, ptr %rs2, align 4 + %1 = mul i32 %rs2.v, %rs1.v + %rd.v = load i32, ptr %rd, align 4 + %2 = add i32 %1, %rd.v + store i32 %2, ptr %rd, align 4 + ret void + } + + attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) } + +... +--- +name: implcv_macs_i32 +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: _, preferred-register: '' } + - { id: 1, class: _, preferred-register: '' } + - { id: 2, class: _, preferred-register: '' } + - { id: 3, class: _, preferred-register: '' } + - { id: 4, class: _, preferred-register: '' } + - { id: 5, class: _, preferred-register: '' } + - { id: 6, class: _, preferred-register: '' } + - { id: 7, class: _, preferred-register: '' } +liveins: + - { reg: '$x10', virtual-reg: '' } + - { reg: '$x11', virtual-reg: '' } + - { reg: '$x12', virtual-reg: '' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.1 (%ir-block.0): + liveins: $x10, $x11, $x12 + + %0:_(p0) = COPY $x10 + %1:_(p0) = COPY $x11 + %2:_(p0) = COPY $x12 + %3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.rs1) + %4:_(s32) = G_LOAD %2(p0) :: (load (s32) from %ir.rs2) + %5:_(s32) = G_MUL %4, %3 + %6:_(s32) = G_LOAD %0(p0) :: (load (s32) from %ir.rd) + %7:_(s32) = G_ADD %5, %6 + G_STORE %7(s32), %0(p0) :: (store (s32) into %ir.rd) + PseudoRET + +... diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.ll b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.ll new file mode 100644 index 00000000..cd7a67e7 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.ll @@ -0,0 +1,17 @@ +; ModuleID = 'mod' +source_filename = "mod" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-linux-gnu" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) +define void @implcv_macs_i32(ptr noalias nocapture %rd, ptr nocapture readonly %rs1, ptr nocapture readonly %rs2) local_unnamed_addr #0 { + %rs1.v = load i32, ptr %rs1, align 4 + %rs2.v = load i32, ptr %rs2, align 4 + %1 = mul i32 %rs2.v, %rs1.v + %rd.v = load i32, ptr %rd, align 4 + %2 = add i32 %1, %rd.v + store i32 %2, ptr %rd, align 4 + ret void +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(argmem: readwrite) } diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td new file mode 100644 index 00000000..2d4d8ef9 --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td @@ -0,0 +1,8 @@ +let Predicates = [HasVendorSeal5Testmaccvmacsi32] in { +let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def cv_macs_i32_ : RVInst_cv_macs_i32<(outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2)>; + +def : Pat< + (i32 (add (mul GPR:$rs2, GPR:$rs1), GPR:$rd)), + (cv_macs_i32_ GPR:$rd, GPR:$rs1, GPR:$rs2)>; + +} diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.out b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.out new file mode 100644 index 00000000..ecd6e20f --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.out @@ -0,0 +1 @@ +Pattern for cv_macs_i32: (add (mul GPR:$rs2, GPR:$rs1), GPR:$rd) diff --git a/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.pat b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.pat new file mode 100644 index 00000000..eaf4732a --- /dev/null +++ b/notes/macshh_gisel/Seal5Test_mac_cv_macs_i32/cv_macs_i32.td.pat @@ -0,0 +1 @@ + (add (mul GPR:$rs2, GPR:$rs1), GPR:$rd) \ No newline at end of file diff --git a/notes/macshh_gisel/cecil_test.c b/notes/macshh_gisel/cecil_test.c new file mode 100644 index 00000000..de7179b7 --- /dev/null +++ b/notes/macshh_gisel/cecil_test.c @@ -0,0 +1,123 @@ +#include + +// uint32_t test_maxu32(uint32_t x, uint32_t y) { +// return (x > y) ? x : y; +// } +// +// uint16_t test_maxu16(uint16_t x, uint16_t y) { +// return (x > y) ? x : y; +// } +// +// uint8_t test_maxu8(uint8_t x, uint8_t y) { +// return (x > y) ? x : y; +// } +// +// int32_t test_maxs32(int32_t x, int32_t y) { +// return (x > y) ? x : y; +// } +// +// int16_t test_maxs16(int16_t x, int16_t y) { +// return (x > y) ? x : y; +// } +// +// int8_t test_maxs8(int8_t x, int8_t y) { +// return (x > y) ? x : y; +// } +// +// uint32_t test_minu32(uint32_t x, uint32_t y) { +// return (x < y) ? x : y; +// } +// +// uint16_t test_minu16(uint16_t x, uint16_t y) { +// return (x < y) ? x : y; +// } +// +// uint8_t test_minu8(uint8_t x, uint8_t y) { +// return (x < y) ? x : y; +// } +// +// int32_t test_mins32(int32_t x, int32_t y) { +// return (x < y) ? x : y; +// } +// +// int16_t test_mins16(int16_t x, int16_t y) { +// return (x < y) ? x : y; +// } +// +// int8_t test_mins8(int8_t x, int8_t y) { +// return (x < y) ? x : y; +// } +// +// int32_t test_abs32(int32_t x) { +// return (x > 0) ? x : -x; +// } +// +// int16_t test_abs16(int16_t x) { +// return (x > 0) ? x : -x; +// } +// +// int8_t test_abs8(int8_t x) { +// return (x > 0) ? x : -x; +// } +// +// int32_t test_mac32(int32_t acc, int32_t x, int32_t y) { +// return acc + x * y; +// } +// +// int32_t test_macs32_16(int32_t acc, int16_t x, int16_t y) { +// return acc + x * y; +// } +// +int32_t test_macs32_v2i16(int32_t acc, int32_t x, int32_t y) { + acc += (int32_t)(int16_t)(x & 0xffff) * (int32_t)(int16_t)(y & 0xffff); + acc += (int32_t)(int16_t)((x >> 16) & 0xffff) * (int32_t)(int16_t)((y >> 16) & 0xffff); + return acc; +} +// +// uint32_t test_macu32_16(uint32_t acc, uint16_t x, uint16_t y) { +// return acc + x * y; +// } +// +// int32_t test_macs32_8(int32_t acc, int8_t x, int8_t y) { +// return acc + x * y; +// } +// +// uint32_t test_macu32_8(uint32_t acc, uint8_t x, uint8_t y) { +// return acc + x * y; +// } +// +// int32_t test_msu32(int32_t acc, int32_t x, int32_t y) { +// return acc - x * y; +// } +// +// int32_t test_msus32_16(int32_t acc, int16_t x, int16_t y) { +// return acc - x * y; +// } +// +// uint32_t test_msuu32_16(uint32_t acc, uint16_t x, uint16_t y) { +// return acc - x * y; +// } +// +// int32_t test_msus32_8(int32_t acc, int8_t x, int8_t y) { +// return acc - x * y; +// } +// +// uint32_t test_msuu32_8(uint32_t acc, uint8_t x, uint8_t y) { +// return acc - x * y; +// } +// +// int32_t test_slets(int32_t x, int32_t y) { +// return x <= y; +// } +// +// int32_t test_sletu(uint32_t x, uint32_t y) { +// return x <= y; +// } +// +// int32_t test_addns(int32_t x, int32_t y) { +// return (x + y) >> 8; +// } +// +// uint32_t test_addnu(uint32_t x, uint32_t y) { +// return (x + y) >> 8; +// } diff --git a/notes/macshh_gisel/cmd.txt b/notes/macshh_gisel/cmd.txt new file mode 100644 index 00000000..e8043215 --- /dev/null +++ b/notes/macshh_gisel/cmd.txt @@ -0,0 +1 @@ +/tmp/seal5_llvm_gen/.seal5/build/release_assertions/bin/clang -S -o out.S cecil_test.c --target=riscv32 -march=rv32im -O3 -mllvm -global-isel=1 -Xclang -target-feature -Xclang +xseal5testalucvabs16 -Xclang -target-feature -Xclang +xseal5testalucvabs32 -Xclang -target-feature -Xclang +xseal5testalucvabs8 -Xclang -target-feature -Xclang +xseal5testalucvaddnrsi16 -Xclang -target-feature -Xclang +xseal5testalucvaddnrsi32 -Xclang -target-feature -Xclang +xseal5testalucvaddnrui16 -Xclang -target-feature -Xclang +xseal5testalucvaddnrui32 -Xclang -target-feature -Xclang +xseal5testalucvaddns -Xclang -target-feature -Xclang +xseal5testalucvaddnu -Xclang -target-feature -Xclang +xseal5testalucvaddrnrsi16 -Xclang -target-feature -Xclang +xseal5testalucvaddrnrsi32 -Xclang -target-feature -Xclang +xseal5testalucvaddrnrui16 -Xclang -target-feature -Xclang +xseal5testalucvaddrnrui32 -Xclang -target-feature -Xclang +xseal5testalucvaddrns -Xclang -target-feature -Xclang +xseal5testalucvaddrnu -Xclang -target-feature -Xclang +xseal5testalucvextbs -Xclang -target-feature -Xclang +xseal5testalucvextbz -Xclang -target-feature -Xclang +xseal5testalucvexths -Xclang -target-feature -Xclang +xseal5testalucvexthz -Xclang -target-feature -Xclang +xseal5testalucvmaxi1216 -Xclang -target-feature -Xclang +xseal5testalucvmaxi1232 -Xclang -target-feature -Xclang +xseal5testalucvmaxi516 -Xclang -target-feature -Xclang +xseal5testalucvmaxi532 -Xclang -target-feature -Xclang +xseal5testalucvmaxs16 -Xclang -target-feature -Xclang +xseal5testalucvmaxs32 -Xclang -target-feature -Xclang +xseal5testalucvmaxs8 -Xclang -target-feature -Xclang +xseal5testalucvmaxu16 -Xclang -target-feature -Xclang +xseal5testalucvmaxu32 -Xclang -target-feature -Xclang +xseal5testalucvmaxu8 -Xclang -target-feature -Xclang +xseal5testalucvmini1216 -Xclang -target-feature -Xclang +xseal5testalucvmini1232 -Xclang -target-feature -Xclang +xseal5testalucvmini516 -Xclang -target-feature -Xclang +xseal5testalucvmini532 -Xclang -target-feature -Xclang +xseal5testalucvmins16 -Xclang -target-feature -Xclang +xseal5testalucvmins32 -Xclang -target-feature -Xclang +xseal5testalucvmins8 -Xclang -target-feature -Xclang +xseal5testalucvminu16 -Xclang -target-feature -Xclang +xseal5testalucvminu32 -Xclang -target-feature -Xclang +xseal5testalucvminu8 -Xclang -target-feature -Xclang +xseal5testalucvsletsi16 -Xclang -target-feature -Xclang +xseal5testalucvsletsi32 -Xclang -target-feature -Xclang +xseal5testalucvsletui16 -Xclang -target-feature -Xclang +xseal5testalucvsletui32 -Xclang -target-feature -Xclang +xseal5testalucvsubnrsi16 -Xclang -target-feature -Xclang +xseal5testalucvsubnrsi32 -Xclang -target-feature -Xclang +xseal5testalucvsubnrui16 -Xclang -target-feature -Xclang +xseal5testalucvsubnrui32 -Xclang -target-feature -Xclang +xseal5testalucvsubns -Xclang -target-feature -Xclang +xseal5testalucvsubnu -Xclang -target-feature -Xclang +xseal5testalucvsubrnrsi16 -Xclang -target-feature -Xclang +xseal5testalucvsubrnrsi32 -Xclang -target-feature -Xclang +xseal5testalucvsubrnrui16 -Xclang -target-feature -Xclang +xseal5testalucvsubrnrui32 -Xclang -target-feature -Xclang +xseal5testalucvsubrns -Xclang -target-feature -Xclang +xseal5testalucvsubrnu -Xclang -target-feature -Xclang +xseal5testmaccvmachhns -Xclang -target-feature -Xclang +xseal5testmaccvmachhnu -Xclang -target-feature -Xclang +xseal5testmaccvmachhrns -Xclang -target-feature -Xclang +xseal5testmaccvmachhrnu -Xclang -target-feature -Xclang +xseal5testmaccvmacns -Xclang -target-feature -Xclang +xseal5testmaccvmacnu -Xclang -target-feature -Xclang +xseal5testmaccvmacrns -Xclang -target-feature -Xclang +xseal5testmaccvmacrnu -Xclang -target-feature -Xclang +xseal5testmaccvmacsi16 -Xclang -target-feature -Xclang +xseal5testmaccvmacsi32 -Xclang -target-feature -Xclang +xseal5testmaccvmacui16 -Xclang -target-feature -Xclang +xseal5testmaccvmacui32 -Xclang -target-feature -Xclang +xseal5testmaccvmsusi16 -Xclang -target-feature -Xclang +xseal5testmaccvmsusi32 -Xclang -target-feature -Xclang +xseal5testmaccvmsuui16 -Xclang -target-feature -Xclang +xseal5testmaccvmsuui32 -Xclang -target-feature -Xclang +xseal5testmaccvmulhhns -Xclang -target-feature -Xclang +xseal5testmaccvmulhhnu -Xclang -target-feature -Xclang +xseal5testmaccvmulhhrns -Xclang -target-feature -Xclang +xseal5testmaccvmulhhrnu -Xclang -target-feature -Xclang +xseal5testmaccvmulns -Xclang -target-feature -Xclang +xseal5testmaccvmulnu -Xclang -target-feature -Xclang +xseal5testmaccvmulrns -Xclang -target-feature -Xclang +xseal5testmaccvmulrnu -mllvm -debug -mllvm -print-after-all -mllvm -print-before-all 2> err.txt diff --git a/notes/macshh_gisel/diff.txt b/notes/macshh_gisel/diff.txt new file mode 100644 index 00000000..0ce8c67b --- /dev/null +++ b/notes/macshh_gisel/diff.txt @@ -0,0 +1,20 @@ +diff --git a/llvm/lib/Target/RISCV/seal5/Seal5Test_mac_cv_machhNs/cv_machhNs.td b/llvm/lib/Target/RISCV/seal5/Seal5Test_mac_cv_machhNs/cv_machhNs.td +index 576ae24d39ff..c0bbaa39acb3 100644 +--- a/llvm/lib/Target/RISCV/seal5/Seal5Test_mac_cv_machhNs/cv_machhNs.td ++++ b/llvm/lib/Target/RISCV/seal5/Seal5Test_mac_cv_machhNs/cv_machhNs.td +@@ -4,6 +4,14 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraint + def : Pat< + (i32 (i32 (sra (add (mul (i32 (sra (i32 (shl (i32 (srl GPR:$rs2, (i32 16))), (i32 16))), (i32 16))), (i32 (sra (i32 (shl (i32 (srl GPR:$rs1, (i32 16))), (i32 16))), (i32 16)))), GPR:$rd), (and (i32 uimm5:$Is3), (i32 31))))), + (cv_machhNs_ GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>; ++def : Pat< ++ (i32 (add (mul (i32 (sra (i32 (shl (i32 (srl GPR:$rs2, (i32 16))), (i32 16))), (i32 16))), (i32 (sra (i32 (shl (i32 (srl GPR:$rs1, (i32 16))), (i32 16))), (i32 16)))), GPR:$rd)), ++ (cv_machhNs_ GPR:$rd, GPR:$rs1, GPR:$rs2, 0)>; ++def : Pat< ++ (i32 (add (mul (i32 (sra (i32 (shl (i32 (sra GPR:$rs2, (i32 16))), (i32 16))), (i32 16))), (i32 (sra (i32 (shl (i32 (sra GPR:$rs1, (i32 16))), (i32 16))), (i32 16)))), GPR:$rd)), ++ (cv_machhNs_ GPR:$rd, GPR:$rs1, GPR:$rs2, 0)>; ++def : Pat< ++ (i32 (add (mul (i32 (sra GPR:$rs2, (i32 16))), (i32 (sra GPR:$rs1, (i32 16)))), GPR:$rd)), ++ (cv_machhNs_ GPR:$rd, GPR:$rs1, GPR:$rs2, 0)>; + + } +- diff --git a/notes/macshh_gisel/err.txt b/notes/macshh_gisel/err.txt new file mode 100644 index 00000000..f48153b1 --- /dev/null +++ b/notes/macshh_gisel/err.txt @@ -0,0 +1,12090 @@ +Args: clang (LLVM option parsing) -global-isel=1 -debug -print-after-all -print-before-all +Clearing AST... +; *** IR Dump Before Annotation2MetadataPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump After Annotation2MetadataPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump Before ForceFunctionAttrsPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump After ForceFunctionAttrsPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump Before AssignmentTrackingPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump After AssignmentTrackingPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump Before InferFunctionAttrsPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump After InferFunctionAttrsPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump Before CoroEarlyPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump After CoroEarlyPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !6, i64 0} +!6 = !{!"omnipotent char", !7, i64 0} +!7 = !{!"Simple C/C++ TBAA"} +; *** IR Dump Before LowerExpectIntrinsicPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} +; *** IR Dump After LowerExpectIntrinsicPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} + +Features:+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b +CPU:generic-rv32 +TuneCPU:generic-rv32 + +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} +; *** IR Dump Before SROAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %acc.addr = alloca i32, align 4 + %x.addr = alloca i32, align 4 + %y.addr = alloca i32, align 4 + store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + store i32 %x, ptr %x.addr, align 4, !tbaa !4 + store i32 %y, ptr %y.addr, align 4, !tbaa !4 + %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + %and = and i32 %0, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + %and2 = and i32 %1, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add = add nsw i32 %2, %mul + store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + %3 = load i32, ptr %x.addr, align 4, !tbaa !4 + %shr = ashr i32 %3, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + %shr8 = ashr i32 %4, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %5 = load i32, ptr %acc.addr, align 4, !tbaa !4 + %add13 = add nsw i32 %5, %mul12 + store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + %6 = load i32, ptr %acc.addr, align 4, !tbaa !4 + ret i32 %6 +} +SROA function: test_macs32_v2i16 +SROA alloca: %y.addr = alloca i32, align 4 + Rewriting FCA loads and stores... +Slices of alloca: %y.addr = alloca i32, align 4 + [0,4) slice #0 (splittable) + used by: store i32 %y, ptr %y.addr, align 4, !tbaa !4 + [0,4) slice #1 (splittable) + used by: %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + [0,4) slice #2 (splittable) + used by: %4 = load i32, ptr %y.addr, align 4, !tbaa !4 +Pre-splitting loads and stores + Searching for candidate loads and stores +Rewriting alloca partition [0,4) to: %y.addr = alloca i32, align 4 + rewriting [0,4) slice #0 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: store i32 %y, ptr %y.addr, align 4, !tbaa !4 + to: store i32 %y, ptr %y.addr, align 4, !tbaa !4 + rewriting [0,4) slice #1 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %1 = load i32, ptr %y.addr, align 4, !tbaa !4 + to: %y.addr.0.load = load i32, ptr %y.addr, align 4 + rewriting [0,4) slice #2 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %4 = load i32, ptr %y.addr, align 4, !tbaa !4 + to: %y.addr.0.load14 = load i32, ptr %y.addr, align 4 + Speculating PHIs + Rewriting Selects +Deleting dead instruction: %4 = load i32, ptr %y.addr, align 4, !tbaa !4 +Deleting dead instruction: %1 = load i32, ptr %y.addr, align 4, !tbaa !4 +Deleting dead instruction: store i32 %y, ptr %y.addr, align 4, !tbaa !4 +SROA alloca: %x.addr = alloca i32, align 4 + Rewriting FCA loads and stores... +Slices of alloca: %x.addr = alloca i32, align 4 + [0,4) slice #0 (splittable) + used by: store i32 %x, ptr %x.addr, align 4, !tbaa !4 + [0,4) slice #1 (splittable) + used by: %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + [0,4) slice #2 (splittable) + used by: %2 = load i32, ptr %x.addr, align 4, !tbaa !4 +Pre-splitting loads and stores + Searching for candidate loads and stores +Rewriting alloca partition [0,4) to: %x.addr = alloca i32, align 4 + rewriting [0,4) slice #0 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: store i32 %x, ptr %x.addr, align 4, !tbaa !4 + to: store i32 %x, ptr %x.addr, align 4, !tbaa !4 + rewriting [0,4) slice #1 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %0 = load i32, ptr %x.addr, align 4, !tbaa !4 + to: %x.addr.0.load = load i32, ptr %x.addr, align 4 + rewriting [0,4) slice #2 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %2 = load i32, ptr %x.addr, align 4, !tbaa !4 + to: %x.addr.0.load15 = load i32, ptr %x.addr, align 4 + Speculating PHIs + Rewriting Selects +Deleting dead instruction: %2 = load i32, ptr %x.addr, align 4, !tbaa !4 +Deleting dead instruction: %0 = load i32, ptr %x.addr, align 4, !tbaa !4 +Deleting dead instruction: store i32 %x, ptr %x.addr, align 4, !tbaa !4 +SROA alloca: %acc.addr = alloca i32, align 4 + Rewriting FCA loads and stores... +Slices of alloca: %acc.addr = alloca i32, align 4 + [0,4) slice #0 (splittable) + used by: store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + [0,4) slice #1 (splittable) + used by: %0 = load i32, ptr %acc.addr, align 4, !tbaa !4 + [0,4) slice #2 (splittable) + used by: store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + [0,4) slice #3 (splittable) + used by: %1 = load i32, ptr %acc.addr, align 4, !tbaa !4 + [0,4) slice #4 (splittable) + used by: store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + [0,4) slice #5 (splittable) + used by: %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 +Pre-splitting loads and stores + Searching for candidate loads and stores +Rewriting alloca partition [0,4) to: %acc.addr = alloca i32, align 4 + rewriting [0,4) slice #0 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + to: store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 + rewriting [0,4) slice #1 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %0 = load i32, ptr %acc.addr, align 4, !tbaa !4 + to: %acc.addr.0.load = load i32, ptr %acc.addr, align 4 + rewriting [0,4) slice #2 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + to: store i32 %add, ptr %acc.addr, align 4, !tbaa !4 + rewriting [0,4) slice #3 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %1 = load i32, ptr %acc.addr, align 4, !tbaa !4 + to: %acc.addr.0.load16 = load i32, ptr %acc.addr, align 4 + rewriting [0,4) slice #4 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + to: store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 + rewriting [0,4) slice #5 (splittable) + Begin:(0, 4) NewBegin:(0, 4) NewAllocaBegin:(0, 4) + original: %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 + to: %acc.addr.0.load17 = load i32, ptr %acc.addr, align 4 + Speculating PHIs + Rewriting Selects +Deleting dead instruction: %2 = load i32, ptr %acc.addr, align 4, !tbaa !4 +Deleting dead instruction: store i32 %add13, ptr %acc.addr, align 4, !tbaa !4 +Deleting dead instruction: %1 = load i32, ptr %acc.addr, align 4, !tbaa !4 +Deleting dead instruction: store i32 %add, ptr %acc.addr, align 4, !tbaa !4 +Deleting dead instruction: %0 = load i32, ptr %acc.addr, align 4, !tbaa !4 +Deleting dead instruction: store i32 %acc, ptr %acc.addr, align 4, !tbaa !4 +Promoting allocas with mem2reg... +; *** IR Dump After SROAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before EarlyCSEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After EarlyCSEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before CallSiteSplittingPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After CallSiteSplittingPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before OpenMPOptPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After OpenMPOptPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before IPSCCPPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +Marking Block Executable: entry +markOverdefined: i32 %acc +markOverdefined: i32 %x +markOverdefined: i32 %y + +Popped off OI-WL: i32 %y +Merged constantrange<0, 65536> into %and2 = and i32 %y, 65535 : constantrange<0, 65536> +Merged constantrange<-32768, 32768> into %shr8 = ashr i32 %y, 16 : constantrange<-32768, 32768> + +Popped off OI-WL: i32 %x +Merged constantrange<0, 65536> into %and = and i32 %x, 65535 : constantrange<0, 65536> +Merged constantrange<-32768, 32768> into %shr = ashr i32 %x, 16 : constantrange<-32768, 32768> + +Popped off OI-WL: i32 %acc + +Popped off I-WL: %shr = ashr i32 %x, 16 +Merged constantrange<0, 65536> into %and5 = and i32 %shr, 65535 : constantrange<0, 65536> + +Popped off I-WL: %and5 = and i32 %shr, 65535 +Merged overdefined into %conv6 = trunc i32 %and5 to i16 : overdefined + +Popped off I-WL: %and = and i32 %x, 65535 +Merged overdefined into %conv = trunc i32 %and to i16 : overdefined + +Popped off I-WL: %shr8 = ashr i32 %y, 16 +Merged constantrange<0, 65536> into %and9 = and i32 %shr8, 65535 : constantrange<0, 65536> + +Popped off I-WL: %and9 = and i32 %shr8, 65535 +Merged overdefined into %conv10 = trunc i32 %and9 to i16 : overdefined + +Popped off I-WL: %and2 = and i32 %y, 65535 +Merged overdefined into %conv3 = trunc i32 %and2 to i16 : overdefined + +Popped off BBWL: +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 + +Merged constantrange<-32768, 32768> into %conv1 = sext i16 %conv to i32 : constantrange<-32768, 32768> +Merged constantrange<-32768, 32768> into %conv4 = sext i16 %conv3 to i32 : constantrange<-32768, 32768> +Merged constantrange<-1073709056, 1073741825> into %mul = mul nsw i32 %conv1, %conv4 : constantrange<-1073709056, 1073741825> +Merged overdefined into %add = add nsw i32 %acc, %mul : overdefined +Merged constantrange<-32768, 32768> into %conv7 = sext i16 %conv6 to i32 : constantrange<-32768, 32768> +Merged constantrange<-32768, 32768> into %conv11 = sext i16 %conv10 to i32 : constantrange<-32768, 32768> +Merged constantrange<-1073709056, 1073741825> into %mul12 = mul nsw i32 %conv7, %conv11 : constantrange<-1073709056, 1073741825> +Merged overdefined into %add13 = add nsw i32 %add, %mul12 : overdefined +Merged overdefined into ; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + : overdefined + +Popped off OI-WL: ; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + + +Popped off OI-WL: %add13 = add nsw i32 %add, %mul12 + +Popped off OI-WL: %add = add nsw i32 %acc, %mul + +Popped off OI-WL: %conv3 = trunc i32 %and2 to i16 + +Popped off OI-WL: %conv10 = trunc i32 %and9 to i16 + +Popped off OI-WL: %conv = trunc i32 %and to i16 + +Popped off OI-WL: %conv6 = trunc i32 %and5 to i16 + +Popped off I-WL: %mul12 = mul nsw i32 %conv7, %conv11 + +Popped off I-WL: %conv11 = sext i16 %conv10 to i32 + +Popped off I-WL: %conv7 = sext i16 %conv6 to i32 + +Popped off I-WL: %mul = mul nsw i32 %conv1, %conv4 + +Popped off I-WL: %conv4 = sext i16 %conv3 to i32 + +Popped off I-WL: %conv1 = sext i16 %conv to i32 +FnSpecialization: Try function: test_macs32_v2i16 +FnSpecialization: No possible specializations found in module +; *** IR Dump After IPSCCPPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before CalledValuePropagationPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +Marking Block Executable: entry + +Popped off BBWL: +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 + +Popped off V-WL: ; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + + +Popped off V-WL: %add13 = add nsw i32 %add, %mul12 + +Popped off V-WL: %mul12 = mul nsw i32 %conv7, %conv11 + +Popped off V-WL: %conv11 = sext i16 %conv10 to i32 + +Popped off V-WL: %conv10 = trunc i32 %and9 to i16 + +Popped off V-WL: %and9 = and i32 %shr8, 65535 + +Popped off V-WL: %shr8 = ashr i32 %y, 16 + +Popped off V-WL: %conv7 = sext i16 %conv6 to i32 + +Popped off V-WL: %conv6 = trunc i32 %and5 to i16 + +Popped off V-WL: %and5 = and i32 %shr, 65535 + +Popped off V-WL: %shr = ashr i32 %x, 16 + +Popped off V-WL: %add = add nsw i32 %acc, %mul + +Popped off V-WL: %mul = mul nsw i32 %conv1, %conv4 + +Popped off V-WL: %conv4 = sext i16 %conv3 to i32 + +Popped off V-WL: %conv3 = trunc i32 %and2 to i16 + +Popped off V-WL: %and2 = and i32 %y, 65535 + +Popped off V-WL: %conv1 = sext i16 %conv to i32 + +Popped off V-WL: %conv = trunc i32 %and to i16 + +Popped off V-WL: %and = and i32 %x, 65535 +; *** IR Dump After CalledValuePropagationPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before GlobalOptPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After GlobalOptPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before PromotePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After PromotePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %and = and i32 %x, 65535 + %conv = trunc i32 %and to i16 + %conv1 = sext i16 %conv to i32 + %and2 = and i32 %y, 65535 + %conv3 = trunc i32 %and2 to i16 + %conv4 = sext i16 %conv3 to i32 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %acc, %mul + %shr = ashr i32 %x, 16 + %and5 = and i32 %shr, 65535 + %conv6 = trunc i32 %and5 to i16 + %conv7 = sext i16 %conv6 to i32 + %shr8 = ashr i32 %y, 16 + %and9 = and i32 %shr8, 65535 + %conv10 = trunc i32 %and9 to i16 + %conv11 = sext i16 %conv10 to i32 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add nsw i32 %add, %mul12 +ADD: %mul12 = mul nsw i32 %conv7, %conv11 +ADD: %conv11 = sext i16 %conv10 to i32 +ADD: %conv10 = trunc i32 %and9 to i16 +ADD: %and9 = and i32 %shr8, 65535 +ADD: %shr8 = ashr i32 %y, 16 +ADD: %conv7 = sext i16 %conv6 to i32 +ADD: %conv6 = trunc i32 %and5 to i16 +ADD: %and5 = and i32 %shr, 65535 +ADD: %shr = ashr i32 %x, 16 +ADD: %add = add nsw i32 %acc, %mul +ADD: %mul = mul nsw i32 %conv1, %conv4 +ADD: %conv4 = sext i16 %conv3 to i32 +ADD: %conv3 = trunc i32 %and2 to i16 +ADD: %and2 = and i32 %y, 65535 +ADD: %conv1 = sext i16 %conv to i32 +ADD: %conv = trunc i32 %and to i16 +ADD: %and = and i32 %x, 65535 +IC: Visiting: %and = and i32 %x, 65535 +IC: Visiting: %conv = trunc i32 %and to i16 +ADD DEFERRED: %and = and i32 %x, 65535 +IC: Mod = %conv = trunc i32 %and to i16 + New = %conv = trunc i32 %x to i16 +ADD: %conv = trunc i32 %x to i16 +IC: ERASE %and = and i32 %x, 65535 +IC: Visiting: %conv = trunc i32 %x to i16 +IC: Visiting: %conv1 = sext i16 %conv to i32 +ICE: EvaluateInDifferentType converting expression type to avoid sign extend: %conv1 = sext i16 %conv to i32 +ADD DEFERRED: %sext = shl i32 %x, 16 +IC: Old = %conv1 = sext i16 %conv to i32 + New = = ashr i32 %sext, 16 +ADD: %conv1 = ashr i32 %sext, 16 +IC: ERASE %0 = sext i16 %conv to i32 +ADD DEFERRED: %conv = trunc i32 %x to i16 +IC: ERASE %conv = trunc i32 %x to i16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr i32 %sext, 16 +IC: Mod = %conv1 = ashr i32 %sext, 16 + New = %conv1 = ashr exact i32 %sext, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %and2 = and i32 %y, 65535 +IC: Visiting: %conv3 = trunc i32 %and2 to i16 +ADD DEFERRED: %and2 = and i32 %y, 65535 +IC: Mod = %conv3 = trunc i32 %and2 to i16 + New = %conv3 = trunc i32 %y to i16 +ADD: %conv3 = trunc i32 %y to i16 +IC: ERASE %and2 = and i32 %y, 65535 +IC: Visiting: %conv3 = trunc i32 %y to i16 +IC: Visiting: %conv4 = sext i16 %conv3 to i32 +ICE: EvaluateInDifferentType converting expression type to avoid sign extend: %conv4 = sext i16 %conv3 to i32 +ADD DEFERRED: %sext18 = shl i32 %y, 16 +IC: Old = %conv4 = sext i16 %conv3 to i32 + New = = ashr i32 %sext18, 16 +ADD: %conv4 = ashr i32 %sext18, 16 +IC: ERASE %0 = sext i16 %conv3 to i32 +ADD DEFERRED: %conv3 = trunc i32 %y to i16 +IC: ERASE %conv3 = trunc i32 %y to i16 +ADD: %sext18 = shl i32 %y, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr i32 %sext18, 16 +IC: Mod = %conv4 = ashr i32 %sext18, 16 + New = %conv4 = ashr exact i32 %sext18, 16 +ADD: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv1, %conv4 +IC: Visiting: %add = add nsw i32 %acc, %mul +IC: Mod = %add = add nsw i32 %acc, %mul + New = %add = add nsw i32 %mul, %acc +ADD: %add = add nsw i32 %mul, %acc +IC: Visiting: %add = add nsw i32 %mul, %acc +IC: Visiting: %shr = ashr i32 %x, 16 +IC: Visiting: %and5 = and i32 %shr, 65535 +ADD DEFERRED: %shr = lshr i32 %x, 16 +ADD DEFERRED: %0 = ashr i32 %x, 16 +IC: Mod = %and5 = and i32 %shr, 65535 + New = %and5 = and i32 %shr, 65535 +ADD: %and5 = and i32 %shr, 65535 +IC: ERASE %0 = ashr i32 %x, 16 +ADD: %shr = lshr i32 %x, 16 +IC: Visiting: %shr = lshr i32 %x, 16 +IC: Visiting: %and5 = and i32 %shr, 65535 +IC: Replacing %and5 = and i32 %shr, 65535 + with %shr = lshr i32 %x, 16 +IC: Mod = %and5 = and i32 %shr, 65535 + New = %and5 = and i32 %shr, 65535 +IC: ERASE %and5 = and i32 %shr, 65535 +ADD DEFERRED: %shr = lshr i32 %x, 16 +ADD DEFERRED: %conv6 = trunc i32 %shr to i16 +ADD: %shr = lshr i32 %x, 16 +IC: Visiting: %shr = lshr i32 %x, 16 +IC: Visiting: %conv6 = trunc i32 %shr to i16 +IC: Visiting: %conv7 = sext i16 %conv6 to i32 +ICE: EvaluateInDifferentType converting expression type to avoid sign extend: %conv7 = sext i16 %conv6 to i32 +ADD DEFERRED: %sext19 = shl i32 %shr, 16 +IC: Old = %conv7 = sext i16 %conv6 to i32 + New = = ashr i32 %sext19, 16 +ADD: %conv7 = ashr i32 %sext19, 16 +IC: ERASE %0 = sext i16 %conv6 to i32 +ADD DEFERRED: %conv6 = trunc i32 %shr to i16 +IC: ERASE %conv6 = trunc i32 %shr to i16 +ADD DEFERRED: %shr = lshr i32 %x, 16 +ADD: %shr = lshr i32 %x, 16 +ADD: %sext19 = shl i32 %shr, 16 +IC: Visiting: %sext19 = shl i32 %shr, 16 +ICE: GetShiftedValue propagating shift through expression to eliminate shift: + IN: %shr = lshr i32 %x, 16 + SH: %sext19 = shl i32 %shr, 16 +ADD DEFERRED: %0 = and i32 %x, -65536 +IC: Replacing %sext19 = shl i32 %0, 16 + with %shr = and i32 %x, -65536 +IC: Mod = %sext19 = shl i32 %shr, 16 + New = %sext19 = shl i32 %0, 16 +IC: ERASE %sext19 = shl i32 %0, 16 +ADD DEFERRED: %0 = lshr i32 %x, 16 +IC: ERASE %0 = lshr i32 %x, 16 +ADD: %shr = and i32 %x, -65536 +IC: Visiting: %shr = and i32 %x, -65536 +IC: Visiting: %conv7 = ashr i32 %shr, 16 +ADD DEFERRED: %shr = and i32 %x, -65536 +IC: Mod = %conv7 = ashr i32 %shr, 16 + New = %conv7 = ashr i32 %x, 16 +ADD: %conv7 = ashr i32 %x, 16 +IC: ERASE %shr = and i32 %x, -65536 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %shr8 = ashr i32 %y, 16 +IC: Visiting: %and9 = and i32 %shr8, 65535 +ADD DEFERRED: %shr8 = lshr i32 %y, 16 +ADD DEFERRED: %0 = ashr i32 %y, 16 +IC: Mod = %and9 = and i32 %shr8, 65535 + New = %and9 = and i32 %shr8, 65535 +ADD: %and9 = and i32 %shr8, 65535 +IC: ERASE %0 = ashr i32 %y, 16 +ADD: %shr8 = lshr i32 %y, 16 +IC: Visiting: %shr8 = lshr i32 %y, 16 +IC: Visiting: %and9 = and i32 %shr8, 65535 +IC: Replacing %and9 = and i32 %shr8, 65535 + with %shr8 = lshr i32 %y, 16 +IC: Mod = %and9 = and i32 %shr8, 65535 + New = %and9 = and i32 %shr8, 65535 +IC: ERASE %and9 = and i32 %shr8, 65535 +ADD DEFERRED: %shr8 = lshr i32 %y, 16 +ADD DEFERRED: %conv10 = trunc i32 %shr8 to i16 +ADD: %shr8 = lshr i32 %y, 16 +IC: Visiting: %shr8 = lshr i32 %y, 16 +IC: Visiting: %conv10 = trunc i32 %shr8 to i16 +IC: Visiting: %conv11 = sext i16 %conv10 to i32 +ICE: EvaluateInDifferentType converting expression type to avoid sign extend: %conv11 = sext i16 %conv10 to i32 +ADD DEFERRED: %sext20 = shl i32 %shr8, 16 +IC: Old = %conv11 = sext i16 %conv10 to i32 + New = = ashr i32 %sext20, 16 +ADD: %conv11 = ashr i32 %sext20, 16 +IC: ERASE %0 = sext i16 %conv10 to i32 +ADD DEFERRED: %conv10 = trunc i32 %shr8 to i16 +IC: ERASE %conv10 = trunc i32 %shr8 to i16 +ADD DEFERRED: %shr8 = lshr i32 %y, 16 +ADD: %shr8 = lshr i32 %y, 16 +ADD: %sext20 = shl i32 %shr8, 16 +IC: Visiting: %sext20 = shl i32 %shr8, 16 +ICE: GetShiftedValue propagating shift through expression to eliminate shift: + IN: %shr8 = lshr i32 %y, 16 + SH: %sext20 = shl i32 %shr8, 16 +ADD DEFERRED: %0 = and i32 %y, -65536 +IC: Replacing %sext20 = shl i32 %0, 16 + with %shr8 = and i32 %y, -65536 +IC: Mod = %sext20 = shl i32 %shr8, 16 + New = %sext20 = shl i32 %0, 16 +IC: ERASE %sext20 = shl i32 %0, 16 +ADD DEFERRED: %0 = lshr i32 %y, 16 +IC: ERASE %0 = lshr i32 %y, 16 +ADD: %shr8 = and i32 %y, -65536 +IC: Visiting: %shr8 = and i32 %y, -65536 +IC: Visiting: %conv11 = ashr i32 %shr8, 16 +ADD DEFERRED: %shr8 = and i32 %y, -65536 +IC: Mod = %conv11 = ashr i32 %shr8, 16 + New = %conv11 = ashr i32 %y, 16 +ADD: %conv11 = ashr i32 %y, 16 +IC: ERASE %shr8 = and i32 %y, -65536 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv7, %conv11 +IC: Visiting: %add13 = add nsw i32 %add, %mul12 +IC: Visiting: ret i32 %add13 + + +[IC] Iteration limit #1 on test_macs32_v2i16 reached; stopping without verifying fixpoint +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before AlwaysInlinerPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After AlwaysInlinerPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +Using default inliner heuristic. +; *** IR Dump Before RequireAnalysisPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After RequireAnalysisPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before InvalidateAnalysisPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After InvalidateAnalysisPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before RequireAnalysisPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After RequireAnalysisPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + +attributes #0 = { nounwind "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +Building CG for module: cecil_test.c + Adding 'test_macs32_v2i16' to entry set of the graph. + Added callable function: test_macs32_v2i16 + Adding functions referenced by global initializers to the entry set. + Adding functions called by 'test_macs32_v2i16' to the graph. +Running an SCC pass across the RefSCC: [(test_macs32_v2i16)] +; *** IR Dump Before InlinerPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After InlinerPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before PostOrderFunctionAttrsPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After PostOrderFunctionAttrsPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before ArgumentPromotionPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After ArgumentPromotionPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before OpenMPOptCGSCCPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After OpenMPOptCGSCCPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +Running function passes across an SCC: (test_macs32_v2i16) +; *** IR Dump Before SROAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +SROA function: test_macs32_v2i16 +; *** IR Dump After SROAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before EarlyCSEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After EarlyCSEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before SpeculativeExecutionPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +Not running SpeculativeExecution because TTI->hasBranchDivergence() is false. +; *** IR Dump After SpeculativeExecutionPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before JumpThreadingPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +Jump threading on function 'test_macs32_v2i16' +; *** IR Dump After JumpThreadingPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before CorrelatedValuePropagationPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +LVI Getting block end value i32 %x at 'entry' +PUSH: i32 %x in entry +POP i32 %x in entry = overdefined + Result = overdefined +LVI Getting block end value i32 16 at 'entry' + Result = constantrange<16, 17> +LVI Getting block end value %sext = shl i32 %x, 16 at 'entry' +PUSH: %sext = shl i32 %x, 16 in entry +POP %sext = shl i32 %x, 16 in entry = constantrange<0, -65535> + Result = constantrange<0, -65535> +LVI Getting block end value i32 %y at 'entry' +PUSH: i32 %y in entry +POP i32 %y in entry = overdefined + Result = overdefined +LVI Getting block end value i32 16 at 'entry' + Result = constantrange<16, 17> +LVI Getting block end value %sext18 = shl i32 %y, 16 at 'entry' +PUSH: %sext18 = shl i32 %y, 16 in entry +POP %sext18 = shl i32 %y, 16 in entry = constantrange<0, -65535> + Result = constantrange<0, -65535> +LVI Getting block end value %conv1 = ashr exact i32 %sext, 16 at 'entry' +PUSH: %conv1 = ashr exact i32 %sext, 16 in entry +POP %conv1 = ashr exact i32 %sext, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %conv4 = ashr exact i32 %sext18, 16 at 'entry' +PUSH: %conv4 = ashr exact i32 %sext18, 16 in entry +POP %conv4 = ashr exact i32 %sext18, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %mul = mul nsw i32 %conv1, %conv4 at 'entry' +PUSH: %mul = mul nsw i32 %conv1, %conv4 in entry +POP %mul = mul nsw i32 %conv1, %conv4 in entry = constantrange<-1073709056, 1073741825> + Result = constantrange<-1073709056, 1073741825> +LVI Getting block end value i32 %acc at 'entry' +PUSH: i32 %acc in entry +POP i32 %acc in entry = overdefined + Result = overdefined +LVI Getting block end value i32 %x at 'entry' + Result = overdefined +LVI Getting block end value i32 %y at 'entry' + Result = overdefined +LVI Getting block end value %conv7 = ashr i32 %x, 16 at 'entry' +PUSH: %conv7 = ashr i32 %x, 16 in entry +POP %conv7 = ashr i32 %x, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %conv11 = ashr i32 %y, 16 at 'entry' +PUSH: %conv11 = ashr i32 %y, 16 in entry +POP %conv11 = ashr i32 %y, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %add = add nsw i32 %mul, %acc at 'entry' +PUSH: %add = add nsw i32 %mul, %acc in entry +POP %add = add nsw i32 %mul, %acc in entry = overdefined + Result = overdefined +LVI Getting block end value %mul12 = mul nsw i32 %conv7, %conv11 at 'entry' +PUSH: %mul12 = mul nsw i32 %conv7, %conv11 in entry +POP %mul12 = mul nsw i32 %conv7, %conv11 in entry = constantrange<-1073709056, 1073741825> + Result = constantrange<-1073709056, 1073741825> +LVI Getting block end value %add13 = add nsw i32 %add, %mul12 at 'entry' +PUSH: %add13 = add nsw i32 %add, %mul12 in entry +POP %add13 = add nsw i32 %add, %mul12 in entry = overdefined + Result = overdefined +; *** IR Dump After CorrelatedValuePropagationPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add nsw i32 %add, %mul12 +ADD: %mul12 = mul nsw i32 %conv7, %conv11 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %add = add nsw i32 %mul, %acc +ADD: %mul = mul nsw i32 %conv1, %conv4 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv1, %conv4 +IC: Visiting: %add = add nsw i32 %mul, %acc +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv7, %conv11 +IC: Visiting: %add13 = add nsw i32 %add, %mul12 +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before AggressiveInstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After AggressiveInstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before LibCallsShrinkWrapPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After LibCallsShrinkWrapPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before TailCallElimPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After TailCallElimPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +; *** IR Dump Before ReassociatePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv1, %conv4 + %add = add nsw i32 %mul, %acc + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv7, %conv11 + %add13 = add nsw i32 %add, %mul12 + ret i32 %add13 +} +Calculated Rank[acc] = 3 +Calculated Rank[x] = 4 +Calculated Rank[y] = 5 +Combine negations for: %sext = shl i32 %x, 16 +Combine negations for: %conv1 = ashr exact i32 %sext, 16 +Combine negations for: %sext18 = shl i32 %y, 16 +Combine negations for: %conv4 = ashr exact i32 %sext18, 16 +Calculated Rank[sext18] = 6 +Calculated Rank[conv4] = 7 +Calculated Rank[sext] = 5 +Calculated Rank[conv1] = 6 +Combine negations for: %mul = mul nsw i32 %conv1, %conv4 +LINEARIZE: %mul = mul nsw i32 %conv1, %conv4 +OPERAND: %conv1 = ashr exact i32 %sext, 16 (1) +ADD LEAF: %conv1 = ashr exact i32 %sext, 16 (1) +OPERAND: %conv4 = ashr exact i32 %sext18, 16 (1) +ADD LEAF: %conv4 = ashr exact i32 %sext18, 16 (1) +RAIn: mul i32 [ %conv1, #6] [ %conv4, #7] +RAOut: mul i32 [ %conv4, #7] [ %conv1, #6] +RAOut after CSE reorder: mul i32 [ %conv4, #7] [ %conv1, #6] +RA: %mul = mul nsw i32 %conv1, %conv4 +TO: %mul = mul nsw i32 %conv4, %conv1 +Calculated Rank[mul] = 8 +Combine negations for: %add = add nsw i32 %acc, %mul +Combine negations for: %conv7 = ashr i32 %x, 16 +Combine negations for: %conv11 = ashr i32 %y, 16 +Calculated Rank[conv11] = 6 +Calculated Rank[conv7] = 5 +Combine negations for: %mul12 = mul nsw i32 %conv7, %conv11 +LINEARIZE: %mul12 = mul nsw i32 %conv7, %conv11 +OPERAND: %conv7 = ashr i32 %x, 16 (1) +ADD LEAF: %conv7 = ashr i32 %x, 16 (1) +OPERAND: %conv11 = ashr i32 %y, 16 (1) +ADD LEAF: %conv11 = ashr i32 %y, 16 (1) +RAIn: mul i32 [ %conv7, #5] [ %conv11, #6] +RAOut: mul i32 [ %conv11, #6] [ %conv7, #5] +RAOut after CSE reorder: mul i32 [ %conv11, #6] [ %conv7, #5] +RA: %mul12 = mul nsw i32 %conv7, %conv11 +TO: %mul12 = mul nsw i32 %conv11, %conv7 +Calculated Rank[mul12] = 7 +Calculated Rank[add] = 9 +Combine negations for: %add13 = add nsw i32 %mul12, %add +LINEARIZE: %add13 = add nsw i32 %mul12, %add +OPERAND: %mul12 = mul nsw i32 %conv11, %conv7 (1) +ADD LEAF: %mul12 = mul nsw i32 %conv11, %conv7 (1) +OPERAND: %add = add nsw i32 %acc, %mul (1) +DIRECT ADD: %add = add nsw i32 %acc, %mul (1) +OPERAND: i32 %acc (1) +ADD LEAF: i32 %acc (1) +OPERAND: %mul = mul nsw i32 %conv4, %conv1 (1) +ADD LEAF: %mul = mul nsw i32 %conv4, %conv1 (1) +RAIn: add i32 [ %mul12, #7] [ %acc, #3] [ %mul, #8] +RAOut: add i32 [ %mul, #8] [ %mul12, #7] [ %acc, #3] +RAOut after CSE reorder: add i32 [ %mul, #8] [ %mul12, #7] [ %acc, #3] +RA: %add13 = add nsw i32 %mul12, %add +TO: %add13 = add nsw i32 %mul12, %mul +RA: %add13 = add nsw i32 %mul12, %mul +TO: %add13 = add nsw i32 %add, %mul +RA: %add = add nsw i32 %acc, %mul +TO: %add = add nsw i32 %mul12, %acc +Combine negations for: %add13 = add i32 %mul, %add +LINEARIZE: %add13 = add i32 %mul, %add +OPERAND: %mul = mul nsw i32 %conv4, %conv1 (1) +ADD LEAF: %mul = mul nsw i32 %conv4, %conv1 (1) +OPERAND: %add = add i32 %mul12, %acc (1) +DIRECT ADD: %add = add i32 %mul12, %acc (1) +OPERAND: %mul12 = mul nsw i32 %conv11, %conv7 (1) +ADD LEAF: %mul12 = mul nsw i32 %conv11, %conv7 (1) +OPERAND: i32 %acc (1) +ADD LEAF: i32 %acc (1) +RAIn: add i32 [ %mul, #8] [ %mul12, #7] [ %acc, #3] +RAOut: add i32 [ %mul, #8] [ %mul12, #7] [ %acc, #3] +RAOut after CSE reorder: add i32 [ %mul, #8] [ %mul12, #7] [ %acc, #3] +RA: %add13 = add i32 %mul, %add +TO: %add13 = add i32 %add, %mul +; *** IR Dump After ReassociatePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before ConstraintEliminationPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After ConstraintEliminationPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add i32 %add, %mul +ADD: %add = add i32 %mul12, %acc +ADD: %mul12 = mul nsw i32 %conv11, %conv7 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %mul = mul nsw i32 %conv4, %conv1 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv4, %conv1 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +IC: Visiting: %add = add i32 %mul12, %acc +IC: Visiting: %add13 = add i32 %add, %mul +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SROAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +SROA function: test_macs32_v2i16 +; *** IR Dump After SROAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before VectorCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After VectorCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before MergedLoadStoreMotionPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +Instruction Merger +; *** IR Dump After MergedLoadStoreMotionPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before GVNPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +GVN iteration: 0 +; *** IR Dump After GVNPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SCCPPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +SCCP on function 'test_macs32_v2i16' +Marking Block Executable: entry +markOverdefined: i32 %acc +markOverdefined: i32 %x +markOverdefined: i32 %y + +Popped off OI-WL: i32 %y +Merged constantrange<-32768, 32768> into %conv11 = ashr i32 %y, 16 : constantrange<-32768, 32768> +Merged constantrange<0, -65535> into %sext18 = shl i32 %y, 16 : constantrange<0, -65535> + +Popped off OI-WL: i32 %x +Merged constantrange<-32768, 32768> into %conv7 = ashr i32 %x, 16 : constantrange<-32768, 32768> +Merged constantrange<0, -65535> into %sext = shl i32 %x, 16 : constantrange<0, -65535> + +Popped off OI-WL: i32 %acc + +Popped off I-WL: %sext = shl i32 %x, 16 +Merged constantrange<-32768, 32768> into %conv1 = ashr exact i32 %sext, 16 : constantrange<-32768, 32768> + +Popped off I-WL: %conv1 = ashr exact i32 %sext, 16 + +Popped off I-WL: %conv7 = ashr i32 %x, 16 +Merged constantrange<-1073709056, 1073741825> into %mul12 = mul nsw i32 %conv11, %conv7 : constantrange<-1073709056, 1073741825> + +Popped off I-WL: %mul12 = mul nsw i32 %conv11, %conv7 +Merged overdefined into %add = add i32 %mul12, %acc : overdefined + +Popped off I-WL: %sext18 = shl i32 %y, 16 +Merged constantrange<-32768, 32768> into %conv4 = ashr exact i32 %sext18, 16 : constantrange<-32768, 32768> + +Popped off I-WL: %conv4 = ashr exact i32 %sext18, 16 +Merged constantrange<-1073709056, 1073741825> into %mul = mul nsw i32 %conv4, %conv1 : constantrange<-1073709056, 1073741825> + +Popped off I-WL: %mul = mul nsw i32 %conv4, %conv1 +Merged overdefined into %add13 = add i32 %add, %mul : overdefined + +Popped off I-WL: %conv11 = ashr i32 %y, 16 + +Popped off BBWL: +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 + + +Popped off OI-WL: %add13 = add i32 %add, %mul + +Popped off OI-WL: %add = add i32 %mul12, %acc +RESOLVING UNDEFs +; *** IR Dump After SCCPPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before BDCEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +DemandedBits: Root: ret i32 %add13 +DemandedBits: Visiting: %add13 = add i32 %add, %mul Alive Out: 0xffffffff +DemandedBits: Visiting: %mul = mul nsw i32 %conv4, %conv1 Alive Out: 0xffffffff +DemandedBits: Visiting: %conv1 = ashr exact i32 %sext, 16 Alive Out: 0xffffffff +DemandedBits: Visiting: %sext = shl i32 %x, 16 Alive Out: 0xffffffff +DemandedBits: Visiting: %conv4 = ashr exact i32 %sext18, 16 Alive Out: 0xffffffff +DemandedBits: Visiting: %sext18 = shl i32 %y, 16 Alive Out: 0xffffffff +DemandedBits: Visiting: %add = add i32 %mul12, %acc Alive Out: 0xffffffff +DemandedBits: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 Alive Out: 0xffffffff +DemandedBits: Visiting: %conv7 = ashr i32 %x, 16 Alive Out: 0xffffffff +DemandedBits: Visiting: %conv11 = ashr i32 %y, 16 Alive Out: 0xffffffff +; *** IR Dump After BDCEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add i32 %add, %mul +ADD: %add = add i32 %mul12, %acc +ADD: %mul12 = mul nsw i32 %conv11, %conv7 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %mul = mul nsw i32 %conv4, %conv1 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv4, %conv1 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +IC: Visiting: %add = add i32 %mul12, %acc +IC: Visiting: %add13 = add i32 %add, %mul +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before JumpThreadingPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +Jump threading on function 'test_macs32_v2i16' +; *** IR Dump After JumpThreadingPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before CorrelatedValuePropagationPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +LVI Getting block end value i32 %x at 'entry' +PUSH: i32 %x in entry +POP i32 %x in entry = overdefined + Result = overdefined +LVI Getting block end value i32 16 at 'entry' + Result = constantrange<16, 17> +LVI Getting block end value %sext = shl i32 %x, 16 at 'entry' +PUSH: %sext = shl i32 %x, 16 in entry +POP %sext = shl i32 %x, 16 in entry = constantrange<0, -65535> + Result = constantrange<0, -65535> +LVI Getting block end value i32 %y at 'entry' +PUSH: i32 %y in entry +POP i32 %y in entry = overdefined + Result = overdefined +LVI Getting block end value i32 16 at 'entry' + Result = constantrange<16, 17> +LVI Getting block end value %sext18 = shl i32 %y, 16 at 'entry' +PUSH: %sext18 = shl i32 %y, 16 in entry +POP %sext18 = shl i32 %y, 16 in entry = constantrange<0, -65535> + Result = constantrange<0, -65535> +LVI Getting block end value %conv4 = ashr exact i32 %sext18, 16 at 'entry' +PUSH: %conv4 = ashr exact i32 %sext18, 16 in entry +POP %conv4 = ashr exact i32 %sext18, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %conv1 = ashr exact i32 %sext, 16 at 'entry' +PUSH: %conv1 = ashr exact i32 %sext, 16 in entry +POP %conv1 = ashr exact i32 %sext, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value i32 %x at 'entry' + Result = overdefined +LVI Getting block end value i32 %y at 'entry' + Result = overdefined +LVI Getting block end value %conv11 = ashr i32 %y, 16 at 'entry' +PUSH: %conv11 = ashr i32 %y, 16 in entry +POP %conv11 = ashr i32 %y, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %conv7 = ashr i32 %x, 16 at 'entry' +PUSH: %conv7 = ashr i32 %x, 16 in entry +POP %conv7 = ashr i32 %x, 16 in entry = constantrange<-32768, 32768> + Result = constantrange<-32768, 32768> +LVI Getting block end value %mul12 = mul nsw i32 %conv11, %conv7 at 'entry' +PUSH: %mul12 = mul nsw i32 %conv11, %conv7 in entry +POP %mul12 = mul nsw i32 %conv11, %conv7 in entry = constantrange<-1073709056, 1073741825> + Result = constantrange<-1073709056, 1073741825> +LVI Getting block end value i32 %acc at 'entry' +PUSH: i32 %acc in entry +POP i32 %acc in entry = overdefined + Result = overdefined +LVI Getting block end value %add = add i32 %mul12, %acc at 'entry' +PUSH: %add = add i32 %mul12, %acc in entry +POP %add = add i32 %mul12, %acc in entry = overdefined + Result = overdefined +LVI Getting block end value %mul = mul nsw i32 %conv4, %conv1 at 'entry' +PUSH: %mul = mul nsw i32 %conv4, %conv1 in entry +POP %mul = mul nsw i32 %conv4, %conv1 in entry = constantrange<-1073709056, 1073741825> + Result = constantrange<-1073709056, 1073741825> +LVI Getting block end value %add13 = add i32 %add, %mul at 'entry' +PUSH: %add13 = add i32 %add, %mul in entry +POP %add13 = add i32 %add, %mul in entry = overdefined + Result = overdefined +; *** IR Dump After CorrelatedValuePropagationPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before ADCEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + Looking for trivial roots +Found a new trivial root: %entry +Last visited node: %entry + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %entry +Found roots: %entry +mark live: ret i32 %add13 +mark block live: entry +post-dom root child is a return: entry +work live: ret i32 %add13 +mark live: %add13 = add i32 %add, %mul +work live: %add13 = add i32 %add, %mul +mark live: %add = add i32 %mul12, %acc +mark live: %mul = mul nsw i32 %conv4, %conv1 +work live: %mul = mul nsw i32 %conv4, %conv1 +mark live: %conv4 = ashr exact i32 %sext18, 16 +mark live: %conv1 = ashr exact i32 %sext, 16 +work live: %conv1 = ashr exact i32 %sext, 16 +mark live: %sext = shl i32 %x, 16 +work live: %sext = shl i32 %x, 16 +work live: %conv4 = ashr exact i32 %sext18, 16 +mark live: %sext18 = shl i32 %y, 16 +work live: %sext18 = shl i32 %y, 16 +work live: %add = add i32 %mul12, %acc +mark live: %mul12 = mul nsw i32 %conv11, %conv7 +work live: %mul12 = mul nsw i32 %conv11, %conv7 +mark live: %conv11 = ashr i32 %y, 16 +mark live: %conv7 = ashr i32 %x, 16 +work live: %conv7 = ashr i32 %x, 16 +work live: %conv11 = ashr i32 %y, 16 +final dead terminator blocks: +; *** IR Dump After ADCEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before MemCpyOptPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After MemCpyOptPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before DSEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +Trying to eliminate MemoryDefs that write the already existing value +Trying to eliminate MemoryDefs at the end of the function +; *** IR Dump After DSEPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before MoveAutoInitPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After MoveAutoInitPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before CoroElidePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After CoroElidePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add i32 %add, %mul +ADD: %add = add i32 %mul12, %acc +ADD: %mul12 = mul nsw i32 %conv11, %conv7 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %mul = mul nsw i32 %conv4, %conv1 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv4, %conv1 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +IC: Visiting: %add = add i32 %mul12, %acc +IC: Visiting: %add13 = add i32 %add, %mul +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before PostOrderFunctionAttrsPass on (test_macs32_v2i16) *** +; Function Attrs: nounwind +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +Adding nosync attr to fn test_macs32_v2i16 +; *** IR Dump After PostOrderFunctionAttrsPass on (test_macs32_v2i16) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +Running function passes across an SCC: (test_macs32_v2i16) +; *** IR Dump Before RequireAnalysisPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After RequireAnalysisPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before CoroSplitPass on (test_macs32_v2i16) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After CoroSplitPass on (test_macs32_v2i16) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InvalidateAnalysisPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After InvalidateAnalysisPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before DeadArgumentEliminationPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +DeadArgumentEliminationPass - Deleting dead varargs +DeadArgumentEliminationPass - Determining liveness +DeadArgumentEliminationPass - Intrinsically live fn: test_macs32_v2i16 +; *** IR Dump After DeadArgumentEliminationPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before CoroCleanupPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After CoroCleanupPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before GlobalOptPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After GlobalOptPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before GlobalDCEPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After GlobalDCEPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before EliminateAvailableExternallyPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After EliminateAvailableExternallyPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before ReversePostOrderFunctionAttrsPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After ReversePostOrderFunctionAttrsPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before RecomputeGlobalsAAPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After RecomputeGlobalsAAPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before Float2IntPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +F2I: Looking at function test_macs32_v2i16 +; *** IR Dump After Float2IntPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LowerConstantIntrinsicsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LowerConstantIntrinsicsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before ControlHeightReductionPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After ControlHeightReductionPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopDistributePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopDistributePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InjectTLIMappings on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After InjectTLIMappings on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopVectorizePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopVectorizePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InferAlignmentPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After InferAlignmentPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopLoadEliminationPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopLoadEliminationPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add i32 %add, %mul +ADD: %add = add i32 %mul12, %acc +ADD: %mul12 = mul nsw i32 %conv11, %conv7 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %mul = mul nsw i32 %conv4, %conv1 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv4, %conv1 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +IC: Visiting: %add = add i32 %mul12, %acc +IC: Visiting: %add13 = add i32 %add, %mul +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SLPVectorizerPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +SLP: Didn't find any vector registers for target, abort. +; *** IR Dump After SLPVectorizerPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before VectorCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After VectorCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add i32 %add, %mul +ADD: %add = add i32 %mul12, %acc +ADD: %mul12 = mul nsw i32 %conv11, %conv7 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %mul = mul nsw i32 %conv4, %conv1 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv4, %conv1 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +IC: Visiting: %add = add i32 %mul12, %acc +IC: Visiting: %add13 = add i32 %add, %mul +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopUnrollPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopUnrollPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before WarnMissedTransformationsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After WarnMissedTransformationsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SROAPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +SROA function: test_macs32_v2i16 +; *** IR Dump After SROAPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InferAlignmentPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After InferAlignmentPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + + +INSTCOMBINE ITERATION #1 on test_macs32_v2i16 +ADD: ret i32 %add13 +ADD: %add13 = add i32 %add, %mul +ADD: %add = add i32 %mul12, %acc +ADD: %mul12 = mul nsw i32 %conv11, %conv7 +ADD: %conv11 = ashr i32 %y, 16 +ADD: %conv7 = ashr i32 %x, 16 +ADD: %mul = mul nsw i32 %conv4, %conv1 +ADD: %conv4 = ashr exact i32 %sext18, 16 +ADD: %sext18 = shl i32 %y, 16 +ADD: %conv1 = ashr exact i32 %sext, 16 +ADD: %sext = shl i32 %x, 16 +IC: Visiting: %sext = shl i32 %x, 16 +IC: Visiting: %conv1 = ashr exact i32 %sext, 16 +IC: Visiting: %sext18 = shl i32 %y, 16 +IC: Visiting: %conv4 = ashr exact i32 %sext18, 16 +IC: Visiting: %mul = mul nsw i32 %conv4, %conv1 +IC: Visiting: %conv7 = ashr i32 %x, 16 +IC: Visiting: %conv11 = ashr i32 %y, 16 +IC: Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +IC: Visiting: %add = add i32 %mul12, %acc +IC: Visiting: %add13 = add i32 %add, %mul +IC: Visiting: ret i32 %add13 +; *** IR Dump After InstCombinePass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LCSSAPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before AlignmentFromAssumptionsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After AlignmentFromAssumptionsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before LoopSinkPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After LoopSinkPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before InstSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After InstSimplifyPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before DivRemPairsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After DivRemPairsPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before TailCallElimPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After TailCallElimPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After SimplifyCFGPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump Before GlobalDCEPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After GlobalDCEPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before ConstantMergePass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After ConstantMergePass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before CGProfilePass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After CGProfilePass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before RelLookupTableConverterPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump After RelLookupTableConverterPass on [module] *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +; *** IR Dump Before AnnotationRemarksPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +; *** IR Dump After AnnotationRemarksPass on test_macs32_v2i16 *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before ObjC ARC contraction (objc-arc-contract) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +**** ObjCARC Contract **** +Visiting: %sext = shl i32 %x, 16 +Visiting: %conv1 = ashr exact i32 %sext, 16 +Visiting: %sext18 = shl i32 %y, 16 +Visiting: %conv4 = ashr exact i32 %sext18, 16 +Visiting: %mul = mul nsw i32 %conv4, %conv1 +Visiting: %conv7 = ashr i32 %x, 16 +Visiting: %conv11 = ashr i32 %y, 16 +Visiting: %mul12 = mul nsw i32 %conv11, %conv7 +Visiting: %add = add i32 %mul12, %acc +Visiting: %add13 = add i32 %add, %mul +Visiting: ret i32 %add13 +*** IR Dump After ObjC ARC contraction (objc-arc-contract) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +*** IR Dump After Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +*** IR Dump Before Expand large div/rem (expand-large-div-rem) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Expand large div/rem (expand-large-div-rem) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Expand large fp convert (expand-large-fp-convert) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Expand large fp convert (expand-large-fp-convert) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Expand Atomic instructions (atomic-expand) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Expand Atomic instructions (atomic-expand) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Canonicalize natural loops (loop-simplify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Canonicalize natural loops (loop-simplify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Loop Data Prefetch (loop-data-prefetch) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +Please set both PrefetchDistance and CacheLineSize for loop data prefetch. +*** IR Dump After Loop Data Prefetch (loop-data-prefetch) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before RISC-V gather/scatter lowering (riscv-gather-scatter-lowering) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After RISC-V gather/scatter lowering (riscv-gather-scatter-lowering) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Interleaved Access Pass (interleaved-access) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** Interleaved Access Pass: test_macs32_v2i16 +*** IR Dump After Interleaved Access Pass (interleaved-access) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before RISC-V CodeGenPrepare (riscv-codegenprepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After RISC-V CodeGenPrepare (riscv-codegenprepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Module Verifier (verify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Module Verifier (verify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Canonicalize natural loops (loop-simplify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Canonicalize natural loops (loop-simplify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Merge contiguous icmps into a memcmp (mergeicmps) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +MergeICmpsLegacyPass: test_macs32_v2i16 +*** IR Dump After Merge contiguous icmps into a memcmp (mergeicmps) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Expand memcmp() to load/stores (expand-memcmp) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Expand memcmp() to load/stores (expand-memcmp) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Lower Garbage Collection Instructions (gc-lowering) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Lower Garbage Collection Instructions (gc-lowering) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Shadow Stack GC Lowering (shadow-stack-gc-lowering) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Shadow Stack GC Lowering (shadow-stack-gc-lowering) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Lower constant intrinsics (lower-constant-intrinsics) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Lower constant intrinsics (lower-constant-intrinsics) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Remove unreachable blocks from the CFG (unreachableblockelim) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Remove unreachable blocks from the CFG (unreachableblockelim) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + Looking for trivial roots +Found a new trivial root: %entry +Last visited node: %entry + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %entry +Found roots: %entry +---- Branch Probability Info : test_macs32_v2i16 ---- + +Computing probabilities for entry + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: entry +loop-detection +compute-mass-in-function + - node: entry + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - entry: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - entry: float = 1.0, int = 18014398509481984 + +*** IR Dump Before Constant Hoisting (consthoist) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +********** Begin Constant Hoisting ********** +********** Function: test_macs32_v2i16 +********** End Constant Hoisting ********** +*** IR Dump After Constant Hoisting (consthoist) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Replace intrinsics with calls to vector library (replace-with-veclib) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Replace intrinsics with calls to vector library (replace-with-veclib) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Partially inline calls to library functions (partially-inline-libcalls) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Partially inline calls to library functions (partially-inline-libcalls) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Expand vector predication intrinsics (expandvp) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Expand vector predication intrinsics (expandvp) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Expand reduction intrinsics (expand-reductions) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Expand reduction intrinsics (expand-reductions) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before TLS Variable Hoist (tlshoist) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +********** Begin TLS Variable Hoist ********** +********** Function: test_macs32_v2i16 +********** End TLS Variable Hoist ********** +*** IR Dump After TLS Variable Hoist (tlshoist) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before CodeGen Prepare (codegenprepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +---- Branch Probability Info : test_macs32_v2i16 ---- + + Looking for trivial roots +Found a new trivial root: %entry +Last visited node: %entry + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %entry +Found roots: %entry +Computing probabilities for entry + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: entry +loop-detection +compute-mass-in-function + - node: entry + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - entry: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - entry: float = 1.0, int = 18014398509481984 + +*** IR Dump After CodeGen Prepare (codegenprepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Exception handling preparation (dwarf-eh-prepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Exception handling preparation (dwarf-eh-prepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before A No-Op Barrier Pass (barrier) *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +*** IR Dump After A No-Op Barrier Pass (barrier) *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +*** IR Dump Before Prepare callbr (callbrprepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Prepare callbr (callbrprepare) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Safe Stack instrumentation pass (safe-stack) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +[SafeStack] Function: test_macs32_v2i16 +[SafeStack] safestack is not requested for this function +*** IR Dump After Safe Stack instrumentation pass (safe-stack) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump Before Module Verifier (verify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} +*** IR Dump After Module Verifier (verify) *** +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + Looking for trivial roots +Found a new trivial root: %entry +Last visited node: %entry + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %entry +Found roots: %entry +---- Branch Probability Info : test_macs32_v2i16 ---- + +Computing probabilities for entry +# *** IR Dump Before IRTranslator (irtranslator) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness + +# End machine code for function test_macs32_v2i16. + +Checking DILocation from %sext = shl i32 %x, 16 was copied to G_CONSTANT +Checking DILocation from %sext = shl i32 %x, 16 was copied to G_SHL +Checking DILocation from %conv1 = ashr exact i32 %sext, 16 was copied to G_ASHR +Checking DILocation from %sext18 = shl i32 %y, 16 was copied to G_SHL +Checking DILocation from %conv4 = ashr exact i32 %sext18, 16 was copied to G_ASHR +Checking DILocation from %mul = mul nsw i32 %conv4, %conv1 was copied to G_MUL +Checking DILocation from %conv7 = ashr i32 %x, 16 was copied to G_ASHR +Checking DILocation from %conv11 = ashr i32 %y, 16 was copied to G_ASHR +Checking DILocation from %mul12 = mul nsw i32 %conv11, %conv7 was copied to G_MUL +Checking DILocation from %add = add i32 %mul12, %acc was copied to G_ADD +Checking DILocation from %add13 = add i32 %add, %mul was copied to G_ADD +Checking DILocation from ret i32 %add13 was copied to COPY +Checking DILocation from ret i32 %add13 was copied to PseudoRET implicit $x10 +# *** IR Dump After IRTranslator (irtranslator) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %4:_(s32) = G_SHL %1:_, %3:_(s32) + %5:_(s32) = exact G_ASHR %4:_, %3:_(s32) + %6:_(s32) = G_SHL %2:_, %3:_(s32) + %7:_(s32) = exact G_ASHR %6:_, %3:_(s32) + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISCVPreLegalizerCombiner (riscv-prelegalizer-combiner) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %4:_(s32) = G_SHL %1:_, %3:_(s32) + %5:_(s32) = exact G_ASHR %4:_, %3:_(s32) + %6:_(s32) = G_SHL %2:_, %3:_(s32) + %7:_(s32) = exact G_ASHR %6:_, %3:_(s32) + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Generic MI Combiner for: test_macs32_v2i16 + +Try combining %0:_(s32) = COPY $x10 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %1:_(s32) = COPY $x11 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %2:_(s32) = COPY $x12 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %3:_(s32) = G_CONSTANT i32 16 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=120 +5126: GIM_Reject +5126: Rejected + +Try combining %4:_(s32) = G_SHL %1:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=127 +2736: Begin try-block +2743: GIM_CheckSimplePredicate(Predicate=15) +2747: GIM_CheckCxxPredicate(MIs[0], Predicate=11) +2747: Rejected +2751: Resume at 2751 (1 try-blocks remain) +2752: Begin try-block +2759: GIM_CheckSimplePredicate(Predicate=16) +2763: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +2763: Rejected +2767: Resume at 2767 (1 try-blocks remain) +2768: Begin try-block +2775: GIM_CheckSimplePredicate(Predicate=45) +2779: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +2779: Rejected +2783: Resume at 2783 (1 try-blocks remain) +2784: Begin try-block +2791: GIM_CheckSimplePredicate(Predicate=90) +2795: GIM_CheckCxxPredicate(MIs[0], Predicate=69) +2795: Rejected +2799: Resume at 2799 (1 try-blocks remain) +2800: Begin try-block +2807: GIM_CheckSimplePredicate(Predicate=91) +2811: GIM_CheckCxxPredicate(MIs[0], Predicate=70) +2811: Rejected +2815: Resume at 2815 (1 try-blocks remain) +2816: Begin try-block +2823: GIM_CheckSimplePredicate(Predicate=99) +2827: GIM_CheckCxxPredicate(MIs[0], Predicate=76) +2827: Rejected +2831: Resume at 2831 (1 try-blocks remain) +2832: Begin try-block +2839: GIM_CheckSimplePredicate(Predicate=104) +2843: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +2843: Rejected +2847: Resume at 2847 (1 try-blocks remain) +2848: Begin try-block +2855: GIM_CheckSimplePredicate(Predicate=122) +2859: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +2859: Rejected +2863: Resume at 2863 (1 try-blocks remain) +2864: Begin try-block +2871: GIM_CheckSimplePredicate(Predicate=25) +2875: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +2875: Rejected +2888: Resume at 2888 (1 try-blocks remain) +2889: Begin try-block +2896: GIM_CheckSimplePredicate(Predicate=51) +2900: GIM_CheckCxxPredicate(MIs[0], Predicate=38) +2900: Rejected +2904: Resume at 2904 (1 try-blocks remain) +2905: GIM_Reject +2905: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %5:_(s32) = exact G_ASHR %4:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129 +3060: Begin try-block +3067: GIM_CheckSimplePredicate(Predicate=16) +3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +3071: Rejected +3075: Resume at 3075 (1 try-blocks remain) +3076: Begin try-block +3083: GIM_CheckSimplePredicate(Predicate=45) +3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +3087: Rejected +3091: Resume at 3091 (1 try-blocks remain) +3092: Begin try-block +3099: GIM_CheckSimplePredicate(Predicate=49) +3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36) +3106: GIR_CustomAction(FnID=25) +Creating: G_SEXT_INREG + +Creating: G_SEXT_INREG + +Erasing: %5:_(s32) = exact G_ASHR %4:_, %3:_(s32) + +3107: GIR_Done +Created: %5:_(s32) = G_SEXT_INREG %1:_, 16 + +Try combining %5:_(s32) = G_SEXT_INREG %1:_, 16 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125 +2622: Begin try-block +2629: GIM_CheckSimplePredicate(Predicate=50) +2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37) +2633: Rejected +2637: Resume at 2637 (1 try-blocks remain) +2638: Begin try-block +2645: GIM_CheckSimplePredicate(Predicate=57) +2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43) +2649: Rejected +2653: Resume at 2653 (1 try-blocks remain) +2654: Begin try-block +2661: GIM_CheckSimplePredicate(Predicate=100) +2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +2665: Rejected +2669: Resume at 2669 (1 try-blocks remain) +2670: Begin try-block +2677: GIM_CheckSimplePredicate(Predicate=63) +2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49) +[0] Compute known bits: %1:_(s32) = COPY $x11 +[0] Computed for: %1:_(s32) = COPY $x11 +[0] Known: 0x0 +[0] Zero: 0x0 +[0] One: 0x0 +2681: Rejected +2685: Resume at 2685 (1 try-blocks remain) +2686: GIM_Reject +2686: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %6:_(s32) = G_SHL %2:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=127 +2736: Begin try-block +2743: GIM_CheckSimplePredicate(Predicate=15) +2747: GIM_CheckCxxPredicate(MIs[0], Predicate=11) +2747: Rejected +2751: Resume at 2751 (1 try-blocks remain) +2752: Begin try-block +2759: GIM_CheckSimplePredicate(Predicate=16) +2763: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +2763: Rejected +2767: Resume at 2767 (1 try-blocks remain) +2768: Begin try-block +2775: GIM_CheckSimplePredicate(Predicate=45) +2779: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +2779: Rejected +2783: Resume at 2783 (1 try-blocks remain) +2784: Begin try-block +2791: GIM_CheckSimplePredicate(Predicate=90) +2795: GIM_CheckCxxPredicate(MIs[0], Predicate=69) +2795: Rejected +2799: Resume at 2799 (1 try-blocks remain) +2800: Begin try-block +2807: GIM_CheckSimplePredicate(Predicate=91) +2811: GIM_CheckCxxPredicate(MIs[0], Predicate=70) +2811: Rejected +2815: Resume at 2815 (1 try-blocks remain) +2816: Begin try-block +2823: GIM_CheckSimplePredicate(Predicate=99) +2827: GIM_CheckCxxPredicate(MIs[0], Predicate=76) +2827: Rejected +2831: Resume at 2831 (1 try-blocks remain) +2832: Begin try-block +2839: GIM_CheckSimplePredicate(Predicate=104) +2843: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +2843: Rejected +2847: Resume at 2847 (1 try-blocks remain) +2848: Begin try-block +2855: GIM_CheckSimplePredicate(Predicate=122) +2859: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +2859: Rejected +2863: Resume at 2863 (1 try-blocks remain) +2864: Begin try-block +2871: GIM_CheckSimplePredicate(Predicate=25) +2875: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +2875: Rejected +2888: Resume at 2888 (1 try-blocks remain) +2889: Begin try-block +2896: GIM_CheckSimplePredicate(Predicate=51) +2900: GIM_CheckCxxPredicate(MIs[0], Predicate=38) +2900: Rejected +2904: Resume at 2904 (1 try-blocks remain) +2905: GIM_Reject +2905: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %7:_(s32) = exact G_ASHR %6:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129 +3060: Begin try-block +3067: GIM_CheckSimplePredicate(Predicate=16) +3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +3071: Rejected +3075: Resume at 3075 (1 try-blocks remain) +3076: Begin try-block +3083: GIM_CheckSimplePredicate(Predicate=45) +3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +3087: Rejected +3091: Resume at 3091 (1 try-blocks remain) +3092: Begin try-block +3099: GIM_CheckSimplePredicate(Predicate=49) +3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36) +3106: GIR_CustomAction(FnID=25) +Creating: G_SEXT_INREG + +Creating: G_SEXT_INREG + +Erasing: %7:_(s32) = exact G_ASHR %6:_, %3:_(s32) + +3107: GIR_Done +Created: %7:_(s32) = G_SEXT_INREG %2:_, 16 + +Try combining %7:_(s32) = G_SEXT_INREG %2:_, 16 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125 +2622: Begin try-block +2629: GIM_CheckSimplePredicate(Predicate=50) +2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37) +2633: Rejected +2637: Resume at 2637 (1 try-blocks remain) +2638: Begin try-block +2645: GIM_CheckSimplePredicate(Predicate=57) +2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43) +2649: Rejected +2653: Resume at 2653 (1 try-blocks remain) +2654: Begin try-block +2661: GIM_CheckSimplePredicate(Predicate=100) +2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +2665: Rejected +2669: Resume at 2669 (1 try-blocks remain) +2670: Begin try-block +2677: GIM_CheckSimplePredicate(Predicate=63) +2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49) +[0] Compute known bits: %2:_(s32) = COPY $x12 +[0] Computed for: %2:_(s32) = COPY $x12 +[0] Known: 0x0 +[0] Zero: 0x0 +[0] One: 0x0 +2681: Rejected +2685: Resume at 2685 (1 try-blocks remain) +2686: GIM_Reject +2686: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %8:_(s32) = nsw G_MUL %7:_, %5:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49 +1164: Begin try-block +1171: GIM_CheckSimplePredicate(Predicate=13) +1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +1175: Rejected +1179: Resume at 1179 (1 try-blocks remain) +1180: Begin try-block +1187: GIM_CheckSimplePredicate(Predicate=104) +1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +1191: Rejected +1195: Resume at 1195 (1 try-blocks remain) +1196: Begin try-block +1203: GIM_CheckSimplePredicate(Predicate=127) +1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +1207: Rejected +1211: Resume at 1211 (1 try-blocks remain) +1212: Begin try-block +1219: GIM_CheckSimplePredicate(Predicate=4) +1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1) +1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615) +1227: Rejected +1258: Resume at 1258 (1 try-blocks remain) +1259: Begin try-block +1266: GIM_CheckSimplePredicate(Predicate=28) +1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1270: Rejected +1283: Resume at 1283 (1 try-blocks remain) +1284: Begin try-block +1291: GIM_CheckSimplePredicate(Predicate=33) +1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1) +1295: Rejected +1308: Resume at 1308 (1 try-blocks remain) +1309: Begin try-block +1316: GIM_CheckSimplePredicate(Predicate=2) +1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2) +1320: Rejected +1324: Resume at 1324 (1 try-blocks remain) +1325: GIM_Reject +1325: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %9:_(s32) = G_ASHR %1:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129 +3060: Begin try-block +3067: GIM_CheckSimplePredicate(Predicate=16) +3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +3071: Rejected +3075: Resume at 3075 (1 try-blocks remain) +3076: Begin try-block +3083: GIM_CheckSimplePredicate(Predicate=45) +3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +3087: Rejected +3091: Resume at 3091 (1 try-blocks remain) +3092: Begin try-block +3099: GIM_CheckSimplePredicate(Predicate=49) +3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36) +3103: Rejected +3107: Resume at 3107 (1 try-blocks remain) +3108: Begin try-block +3115: GIM_CheckSimplePredicate(Predicate=90) +3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69) +3119: Rejected +3123: Resume at 3123 (1 try-blocks remain) +3124: Begin try-block +3131: GIM_CheckSimplePredicate(Predicate=91) +3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70) +3135: Rejected +3139: Resume at 3139 (1 try-blocks remain) +3140: Begin try-block +3147: GIM_CheckSimplePredicate(Predicate=102) +3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3151: Rejected +3155: Resume at 3155 (1 try-blocks remain) +3156: Begin try-block +3163: GIM_CheckSimplePredicate(Predicate=103) +3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80) +Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3167: Rejected +3171: Resume at 3171 (1 try-blocks remain) +3172: Begin try-block +3179: GIM_CheckSimplePredicate(Predicate=104) +3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +3183: Rejected +3187: Resume at 3187 (1 try-blocks remain) +3188: Begin try-block +3195: GIM_CheckSimplePredicate(Predicate=122) +3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +3199: Rejected +3203: Resume at 3203 (1 try-blocks remain) +3204: Begin try-block +3211: GIM_CheckSimplePredicate(Predicate=25) +3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +3215: Rejected +3228: Resume at 3228 (1 try-blocks remain) +3229: GIM_Reject +3229: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %10:_(s32) = G_ASHR %2:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129 +3060: Begin try-block +3067: GIM_CheckSimplePredicate(Predicate=16) +3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +3071: Rejected +3075: Resume at 3075 (1 try-blocks remain) +3076: Begin try-block +3083: GIM_CheckSimplePredicate(Predicate=45) +3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +3087: Rejected +3091: Resume at 3091 (1 try-blocks remain) +3092: Begin try-block +3099: GIM_CheckSimplePredicate(Predicate=49) +3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36) +3103: Rejected +3107: Resume at 3107 (1 try-blocks remain) +3108: Begin try-block +3115: GIM_CheckSimplePredicate(Predicate=90) +3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69) +3119: Rejected +3123: Resume at 3123 (1 try-blocks remain) +3124: Begin try-block +3131: GIM_CheckSimplePredicate(Predicate=91) +3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70) +3135: Rejected +3139: Resume at 3139 (1 try-blocks remain) +3140: Begin try-block +3147: GIM_CheckSimplePredicate(Predicate=102) +3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3151: Rejected +3155: Resume at 3155 (1 try-blocks remain) +3156: Begin try-block +3163: GIM_CheckSimplePredicate(Predicate=103) +3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80) +Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3167: Rejected +3171: Resume at 3171 (1 try-blocks remain) +3172: Begin try-block +3179: GIM_CheckSimplePredicate(Predicate=104) +3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +3183: Rejected +3187: Resume at 3187 (1 try-blocks remain) +3188: Begin try-block +3195: GIM_CheckSimplePredicate(Predicate=122) +3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +3199: Rejected +3203: Resume at 3203 (1 try-blocks remain) +3204: Begin try-block +3211: GIM_CheckSimplePredicate(Predicate=25) +3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +3215: Rejected +3228: Resume at 3228 (1 try-blocks remain) +3229: GIM_Reject +3229: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %11:_(s32) = nsw G_MUL %10:_, %9:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49 +1164: Begin try-block +1171: GIM_CheckSimplePredicate(Predicate=13) +1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +1175: Rejected +1179: Resume at 1179 (1 try-blocks remain) +1180: Begin try-block +1187: GIM_CheckSimplePredicate(Predicate=104) +1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +1191: Rejected +1195: Resume at 1195 (1 try-blocks remain) +1196: Begin try-block +1203: GIM_CheckSimplePredicate(Predicate=127) +1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +1207: Rejected +1211: Resume at 1211 (1 try-blocks remain) +1212: Begin try-block +1219: GIM_CheckSimplePredicate(Predicate=4) +1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1) +1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615) +1227: Rejected +1258: Resume at 1258 (1 try-blocks remain) +1259: Begin try-block +1266: GIM_CheckSimplePredicate(Predicate=28) +1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1270: Rejected +1283: Resume at 1283 (1 try-blocks remain) +1284: Begin try-block +1291: GIM_CheckSimplePredicate(Predicate=33) +1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1) +1295: Rejected +1308: Resume at 1308 (1 try-blocks remain) +1309: Begin try-block +1316: GIM_CheckSimplePredicate(Predicate=2) +1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2) +1320: Rejected +1324: Resume at 1324 (1 try-blocks remain) +1325: GIM_Reject +1325: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %12:_(s32) = G_ADD %11:_, %0:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47 +864: Begin try-block +871: GIM_CheckSimplePredicate(Predicate=3) +875: GIM_CheckCxxPredicate(MIs[0], Predicate=3) +875: Rejected +879: Resume at 879 (1 try-blocks remain) +880: Begin try-block +887: GIM_CheckSimplePredicate(Predicate=18) +891: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +891: Rejected +895: Resume at 895 (1 try-blocks remain) +896: Begin try-block +903: GIM_CheckSimplePredicate(Predicate=43) +907: GIM_CheckCxxPredicate(MIs[0], Predicate=30) +907: Rejected +911: Resume at 911 (1 try-blocks remain) +912: Begin try-block +919: GIM_CheckSimplePredicate(Predicate=104) +923: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +923: Rejected +927: Resume at 927 (1 try-blocks remain) +928: Begin try-block +935: GIM_CheckSimplePredicate(Predicate=122) +939: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +939: Rejected +943: Resume at 943 (1 try-blocks remain) +944: Begin try-block +951: GIM_CheckSimplePredicate(Predicate=127) +955: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +955: Rejected +959: Resume at 959 (1 try-blocks remain) +960: Begin try-block +967: GIM_CheckSimplePredicate(Predicate=35) +971: MIs[1] = GIM_RecordInsn(0, 1) +975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49 +975: Rejected +995: Resume at 995 (1 try-blocks remain) +996: Begin try-block +1003: GIM_CheckSimplePredicate(Predicate=35) +1007: MIs[1] = GIM_RecordInsn(0, 2) +1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=19 +1011: Rejected +1031: Resume at 1031 (1 try-blocks remain) +1032: Begin try-block +1039: GIM_CheckSimplePredicate(Predicate=25) +1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1043: Rejected +1056: Resume at 1056 (1 try-blocks remain) +1057: Begin try-block +1064: GIM_CheckSimplePredicate(Predicate=47) +1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34) +1068: Rejected +1072: Resume at 1072 (1 try-blocks remain) +1073: GIM_Reject +1073: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %13:_(s32) = G_ADD %12:_, %8:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47 +864: Begin try-block +871: GIM_CheckSimplePredicate(Predicate=3) +875: GIM_CheckCxxPredicate(MIs[0], Predicate=3) +875: Rejected +879: Resume at 879 (1 try-blocks remain) +880: Begin try-block +887: GIM_CheckSimplePredicate(Predicate=18) +891: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +891: Rejected +895: Resume at 895 (1 try-blocks remain) +896: Begin try-block +903: GIM_CheckSimplePredicate(Predicate=43) +907: GIM_CheckCxxPredicate(MIs[0], Predicate=30) +907: Rejected +911: Resume at 911 (1 try-blocks remain) +912: Begin try-block +919: GIM_CheckSimplePredicate(Predicate=104) +923: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +923: Rejected +927: Resume at 927 (1 try-blocks remain) +928: Begin try-block +935: GIM_CheckSimplePredicate(Predicate=122) +939: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +939: Rejected +943: Resume at 943 (1 try-blocks remain) +944: Begin try-block +951: GIM_CheckSimplePredicate(Predicate=127) +955: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +955: Rejected +959: Resume at 959 (1 try-blocks remain) +960: Begin try-block +967: GIM_CheckSimplePredicate(Predicate=35) +971: MIs[1] = GIM_RecordInsn(0, 1) +975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=47 +975: Rejected +995: Resume at 995 (1 try-blocks remain) +996: Begin try-block +1003: GIM_CheckSimplePredicate(Predicate=35) +1007: MIs[1] = GIM_RecordInsn(0, 2) +1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49 +1011: Rejected +1031: Resume at 1031 (1 try-blocks remain) +1032: Begin try-block +1039: GIM_CheckSimplePredicate(Predicate=25) +1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1043: Rejected +1056: Resume at 1056 (1 try-blocks remain) +1057: Begin try-block +1064: GIM_CheckSimplePredicate(Predicate=47) +1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34) +1068: Rejected +1072: Resume at 1072 (1 try-blocks remain) +1073: GIM_Reject +1073: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining $x10 = COPY %13:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining PseudoRET implicit $x10 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=377 +5126: GIM_Reject +5126: Rejected +%6:_(s32) = G_SHL %2:_, %3:_(s32) +Is dead; erasing. +Erasing: %6:_(s32) = G_SHL %2:_, %3:_(s32) + +%4:_(s32) = G_SHL %1:_, %3:_(s32) +Is dead; erasing. +Erasing: %4:_(s32) = G_SHL %1:_, %3:_(s32) + + +Try combining %0:_(s32) = COPY $x10 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %1:_(s32) = COPY $x11 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %2:_(s32) = COPY $x12 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %3:_(s32) = G_CONSTANT i32 16 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=120 +5126: GIM_Reject +5126: Rejected + +Try combining %5:_(s32) = G_SEXT_INREG %1:_, 16 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125 +2622: Begin try-block +2629: GIM_CheckSimplePredicate(Predicate=50) +2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37) +2633: Rejected +2637: Resume at 2637 (1 try-blocks remain) +2638: Begin try-block +2645: GIM_CheckSimplePredicate(Predicate=57) +2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43) +2649: Rejected +2653: Resume at 2653 (1 try-blocks remain) +2654: Begin try-block +2661: GIM_CheckSimplePredicate(Predicate=100) +2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +2665: Rejected +2669: Resume at 2669 (1 try-blocks remain) +2670: Begin try-block +2677: GIM_CheckSimplePredicate(Predicate=63) +2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49) +[0] Compute known bits: %1:_(s32) = COPY $x11 +[0] Computed for: %1:_(s32) = COPY $x11 +[0] Known: 0x0 +[0] Zero: 0x0 +[0] One: 0x0 +2681: Rejected +2685: Resume at 2685 (1 try-blocks remain) +2686: GIM_Reject +2686: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %7:_(s32) = G_SEXT_INREG %2:_, 16 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=125 +2622: Begin try-block +2629: GIM_CheckSimplePredicate(Predicate=50) +2633: GIM_CheckCxxPredicate(MIs[0], Predicate=37) +2633: Rejected +2637: Resume at 2637 (1 try-blocks remain) +2638: Begin try-block +2645: GIM_CheckSimplePredicate(Predicate=57) +2649: GIM_CheckCxxPredicate(MIs[0], Predicate=43) +2649: Rejected +2653: Resume at 2653 (1 try-blocks remain) +2654: Begin try-block +2661: GIM_CheckSimplePredicate(Predicate=100) +2665: GIM_CheckCxxPredicate(MIs[0], Predicate=77) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +2665: Rejected +2669: Resume at 2669 (1 try-blocks remain) +2670: Begin try-block +2677: GIM_CheckSimplePredicate(Predicate=63) +2681: GIM_CheckCxxPredicate(MIs[0], Predicate=49) +[0] Compute known bits: %2:_(s32) = COPY $x12 +[0] Computed for: %2:_(s32) = COPY $x12 +[0] Known: 0x0 +[0] Zero: 0x0 +[0] One: 0x0 +2681: Rejected +2685: Resume at 2685 (1 try-blocks remain) +2686: GIM_Reject +2686: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %8:_(s32) = nsw G_MUL %7:_, %5:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49 +1164: Begin try-block +1171: GIM_CheckSimplePredicate(Predicate=13) +1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +1175: Rejected +1179: Resume at 1179 (1 try-blocks remain) +1180: Begin try-block +1187: GIM_CheckSimplePredicate(Predicate=104) +1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +1191: Rejected +1195: Resume at 1195 (1 try-blocks remain) +1196: Begin try-block +1203: GIM_CheckSimplePredicate(Predicate=127) +1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +1207: Rejected +1211: Resume at 1211 (1 try-blocks remain) +1212: Begin try-block +1219: GIM_CheckSimplePredicate(Predicate=4) +1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1) +1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615) +1227: Rejected +1258: Resume at 1258 (1 try-blocks remain) +1259: Begin try-block +1266: GIM_CheckSimplePredicate(Predicate=28) +1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1270: Rejected +1283: Resume at 1283 (1 try-blocks remain) +1284: Begin try-block +1291: GIM_CheckSimplePredicate(Predicate=33) +1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1) +1295: Rejected +1308: Resume at 1308 (1 try-blocks remain) +1309: Begin try-block +1316: GIM_CheckSimplePredicate(Predicate=2) +1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2) +1320: Rejected +1324: Resume at 1324 (1 try-blocks remain) +1325: GIM_Reject +1325: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %9:_(s32) = G_ASHR %1:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129 +3060: Begin try-block +3067: GIM_CheckSimplePredicate(Predicate=16) +3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +3071: Rejected +3075: Resume at 3075 (1 try-blocks remain) +3076: Begin try-block +3083: GIM_CheckSimplePredicate(Predicate=45) +3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +3087: Rejected +3091: Resume at 3091 (1 try-blocks remain) +3092: Begin try-block +3099: GIM_CheckSimplePredicate(Predicate=49) +3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36) +3103: Rejected +3107: Resume at 3107 (1 try-blocks remain) +3108: Begin try-block +3115: GIM_CheckSimplePredicate(Predicate=90) +3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69) +3119: Rejected +3123: Resume at 3123 (1 try-blocks remain) +3124: Begin try-block +3131: GIM_CheckSimplePredicate(Predicate=91) +3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70) +3135: Rejected +3139: Resume at 3139 (1 try-blocks remain) +3140: Begin try-block +3147: GIM_CheckSimplePredicate(Predicate=102) +3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3151: Rejected +3155: Resume at 3155 (1 try-blocks remain) +3156: Begin try-block +3163: GIM_CheckSimplePredicate(Predicate=103) +3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80) +Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3167: Rejected +3171: Resume at 3171 (1 try-blocks remain) +3172: Begin try-block +3179: GIM_CheckSimplePredicate(Predicate=104) +3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +3183: Rejected +3187: Resume at 3187 (1 try-blocks remain) +3188: Begin try-block +3195: GIM_CheckSimplePredicate(Predicate=122) +3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +3199: Rejected +3203: Resume at 3203 (1 try-blocks remain) +3204: Begin try-block +3211: GIM_CheckSimplePredicate(Predicate=25) +3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +3215: Rejected +3228: Resume at 3228 (1 try-blocks remain) +3229: GIM_Reject +3229: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %10:_(s32) = G_ASHR %2:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=129 +3060: Begin try-block +3067: GIM_CheckSimplePredicate(Predicate=16) +3071: GIM_CheckCxxPredicate(MIs[0], Predicate=12) +3071: Rejected +3075: Resume at 3075 (1 try-blocks remain) +3076: Begin try-block +3083: GIM_CheckSimplePredicate(Predicate=45) +3087: GIM_CheckCxxPredicate(MIs[0], Predicate=32) +3087: Rejected +3091: Resume at 3091 (1 try-blocks remain) +3092: Begin try-block +3099: GIM_CheckSimplePredicate(Predicate=49) +3103: GIM_CheckCxxPredicate(MIs[0], Predicate=36) +3103: Rejected +3107: Resume at 3107 (1 try-blocks remain) +3108: Begin try-block +3115: GIM_CheckSimplePredicate(Predicate=90) +3119: GIM_CheckCxxPredicate(MIs[0], Predicate=69) +3119: Rejected +3123: Resume at 3123 (1 try-blocks remain) +3124: Begin try-block +3131: GIM_CheckSimplePredicate(Predicate=91) +3135: GIM_CheckCxxPredicate(MIs[0], Predicate=70) +3135: Rejected +3139: Resume at 3139 (1 try-blocks remain) +3140: Begin try-block +3147: GIM_CheckSimplePredicate(Predicate=102) +3151: GIM_CheckCxxPredicate(MIs[0], Predicate=79) +Applying legalizer ruleset to: Opcode=269, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3151: Rejected +3155: Resume at 3155 (1 try-blocks remain) +3156: Begin try-block +3163: GIM_CheckSimplePredicate(Predicate=103) +3167: GIM_CheckCxxPredicate(MIs[0], Predicate=80) +Applying legalizer ruleset to: Opcode=270, Tys={s32, s32, }, MMOs={} +.. fallback to legacy rules (no rules defined) +.. (legacy) Type 0 Action=NotFound, LLT_invalid +3167: Rejected +3171: Resume at 3171 (1 try-blocks remain) +3172: Begin try-block +3179: GIM_CheckSimplePredicate(Predicate=104) +3183: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +3183: Rejected +3187: Resume at 3187 (1 try-blocks remain) +3188: Begin try-block +3195: GIM_CheckSimplePredicate(Predicate=122) +3199: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +3199: Rejected +3203: Resume at 3203 (1 try-blocks remain) +3204: Begin try-block +3211: GIM_CheckSimplePredicate(Predicate=25) +3215: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +3215: Rejected +3228: Resume at 3228 (1 try-blocks remain) +3229: GIM_Reject +3229: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %11:_(s32) = nsw G_MUL %10:_, %9:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=49 +1164: Begin try-block +1171: GIM_CheckSimplePredicate(Predicate=13) +1175: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +1175: Rejected +1179: Resume at 1179 (1 try-blocks remain) +1180: Begin try-block +1187: GIM_CheckSimplePredicate(Predicate=104) +1191: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +1191: Rejected +1195: Resume at 1195 (1 try-blocks remain) +1196: Begin try-block +1203: GIM_CheckSimplePredicate(Predicate=127) +1207: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +1207: Rejected +1211: Resume at 1211 (1 try-blocks remain) +1212: Begin try-block +1219: GIM_CheckSimplePredicate(Predicate=4) +1223: GIM_RecordRegType(MIs[0]->getOperand(0), TypeIdx=-1) +1227: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=18446744073709551615) +1227: Rejected +1258: Resume at 1258 (1 try-blocks remain) +1259: Begin try-block +1266: GIM_CheckSimplePredicate(Predicate=28) +1270: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1270: Rejected +1283: Resume at 1283 (1 try-blocks remain) +1284: Begin try-block +1291: GIM_CheckSimplePredicate(Predicate=33) +1295: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1) +1295: Rejected +1308: Resume at 1308 (1 try-blocks remain) +1309: Begin try-block +1316: GIM_CheckSimplePredicate(Predicate=2) +1320: GIM_CheckCxxPredicate(MIs[0], Predicate=2) +1320: Rejected +1324: Resume at 1324 (1 try-blocks remain) +1325: GIM_Reject +1325: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %12:_(s32) = G_ADD %11:_, %0:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47 +864: Begin try-block +871: GIM_CheckSimplePredicate(Predicate=3) +875: GIM_CheckCxxPredicate(MIs[0], Predicate=3) +875: Rejected +879: Resume at 879 (1 try-blocks remain) +880: Begin try-block +887: GIM_CheckSimplePredicate(Predicate=18) +891: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +891: Rejected +895: Resume at 895 (1 try-blocks remain) +896: Begin try-block +903: GIM_CheckSimplePredicate(Predicate=43) +907: GIM_CheckCxxPredicate(MIs[0], Predicate=30) +907: Rejected +911: Resume at 911 (1 try-blocks remain) +912: Begin try-block +919: GIM_CheckSimplePredicate(Predicate=104) +923: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +923: Rejected +927: Resume at 927 (1 try-blocks remain) +928: Begin try-block +935: GIM_CheckSimplePredicate(Predicate=122) +939: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +939: Rejected +943: Resume at 943 (1 try-blocks remain) +944: Begin try-block +951: GIM_CheckSimplePredicate(Predicate=127) +955: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +955: Rejected +959: Resume at 959 (1 try-blocks remain) +960: Begin try-block +967: GIM_CheckSimplePredicate(Predicate=35) +971: MIs[1] = GIM_RecordInsn(0, 1) +975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49 +975: Rejected +995: Resume at 995 (1 try-blocks remain) +996: Begin try-block +1003: GIM_CheckSimplePredicate(Predicate=35) +1007: MIs[1] = GIM_RecordInsn(0, 2) +1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=19 +1011: Rejected +1031: Resume at 1031 (1 try-blocks remain) +1032: Begin try-block +1039: GIM_CheckSimplePredicate(Predicate=25) +1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1043: Rejected +1056: Resume at 1056 (1 try-blocks remain) +1057: Begin try-block +1064: GIM_CheckSimplePredicate(Predicate=47) +1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34) +1068: Rejected +1072: Resume at 1072 (1 try-blocks remain) +1073: GIM_Reject +1073: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining %13:_(s32) = G_ADD %12:_, %8:_ +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=47 +864: Begin try-block +871: GIM_CheckSimplePredicate(Predicate=3) +875: GIM_CheckCxxPredicate(MIs[0], Predicate=3) +875: Rejected +879: Resume at 879 (1 try-blocks remain) +880: Begin try-block +887: GIM_CheckSimplePredicate(Predicate=18) +891: GIM_CheckCxxPredicate(MIs[0], Predicate=10) +891: Rejected +895: Resume at 895 (1 try-blocks remain) +896: Begin try-block +903: GIM_CheckSimplePredicate(Predicate=43) +907: GIM_CheckCxxPredicate(MIs[0], Predicate=30) +907: Rejected +911: Resume at 911 (1 try-blocks remain) +912: Begin try-block +919: GIM_CheckSimplePredicate(Predicate=104) +923: GIM_CheckCxxPredicate(MIs[0], Predicate=81) +923: Rejected +927: Resume at 927 (1 try-blocks remain) +928: Begin try-block +935: GIM_CheckSimplePredicate(Predicate=122) +939: GIM_CheckCxxPredicate(MIs[0], Predicate=98) +939: Rejected +943: Resume at 943 (1 try-blocks remain) +944: Begin try-block +951: GIM_CheckSimplePredicate(Predicate=127) +955: GIM_CheckCxxPredicate(MIs[0], Predicate=103) +955: Rejected +959: Resume at 959 (1 try-blocks remain) +960: Begin try-block +967: GIM_CheckSimplePredicate(Predicate=35) +971: MIs[1] = GIM_RecordInsn(0, 1) +975: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=47 +975: Rejected +995: Resume at 995 (1 try-blocks remain) +996: Begin try-block +1003: GIM_CheckSimplePredicate(Predicate=35) +1007: MIs[1] = GIM_RecordInsn(0, 2) +1011: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49 +1011: Rejected +1031: Resume at 1031 (1 try-blocks remain) +1032: Begin try-block +1039: GIM_CheckSimplePredicate(Predicate=25) +1043: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1043: Rejected +1056: Resume at 1056 (1 try-blocks remain) +1057: Begin try-block +1064: GIM_CheckSimplePredicate(Predicate=47) +1068: GIM_CheckCxxPredicate(MIs[0], Predicate=34) +1068: Rejected +1072: Resume at 1072 (1 try-blocks remain) +1073: GIM_Reject +1073: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining $x10 = COPY %13:_(s32) +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=19 +847: Begin try-block +854: GIM_CheckSimplePredicate(Predicate=1) +858: GIM_CheckCxxPredicate(MIs[0], Predicate=1) +858: Rejected +862: Resume at 862 (1 try-blocks remain) +863: GIM_Reject +863: Rejected +5125: Resume at 5125 (0 try-blocks remain) +5126: GIM_Reject +5126: Rejected + +Try combining PseudoRET implicit $x10 +10: GIM_SwitchOpcode(MIs[0], [19, 228), Default=5125, JumpTable...) // Got=377 +5126: GIM_Reject +5126: Rejected +# *** IR Dump After RISCVPreLegalizerCombiner (riscv-prelegalizer-combiner) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %5:_(s32) = G_SEXT_INREG %1:_, 16 + %7:_(s32) = G_SEXT_INREG %2:_, 16 + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Legalizer (legalizer) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %5:_(s32) = G_SEXT_INREG %1:_, 16 + %7:_(s32) = G_SEXT_INREG %2:_, 16 + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Legalize Machine IR for: test_macs32_v2i16 +=== New Iteration === +Legalizing: %13:_(s32) = G_ADD %12:_, %8:_ +Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %12:_(s32) = G_ADD %11:_, %0:_ +Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %11:_(s32) = nsw G_MUL %10:_, %9:_ +Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %10:_(s32) = G_ASHR %2:_, %3:_(s32) +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %9:_(s32) = G_ASHR %1:_, %3:_(s32) +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %8:_(s32) = nsw G_MUL %7:_, %5:_ +Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %7:_(s32) = G_SEXT_INREG %2:_, 16 +Applying legalizer ruleset to: Opcode=125, Tys={s32, }, MMOs={} +.. no match +.. match +.. .. Lower, 0, LLT_invalid +.. Lower +.. .. Erasing: %7:_(s32) = G_SEXT_INREG %2:_, 16 +.. .. New MI: %15:_(s32) = G_CONSTANT i32 16 +.. .. New MI: %14:_(s32) = G_SHL %2:_, %15:_(s32) +.. .. New MI: %7:_(s32) = G_ASHR %14:_, %15:_(s32) +.. No debug info was present +Legalizing: %7:_(s32) = G_ASHR %14:_, %15:_(s32) +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %14:_(s32) = G_SHL %2:_, %15:_(s32) +.. opcode 127 is aliased to 129 +Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %15:_(s32) = G_CONSTANT i32 16 +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %5:_(s32) = G_SEXT_INREG %1:_, 16 +Applying legalizer ruleset to: Opcode=125, Tys={s32, }, MMOs={} +.. no match +.. match +.. .. Lower, 0, LLT_invalid +.. Lower +.. .. Erasing: %5:_(s32) = G_SEXT_INREG %1:_, 16 +.. .. New MI: %17:_(s32) = G_CONSTANT i32 16 +.. .. New MI: %16:_(s32) = G_SHL %1:_, %17:_(s32) +.. .. New MI: %5:_(s32) = G_ASHR %16:_, %17:_(s32) +.. No debug info was present +Legalizing: %5:_(s32) = G_ASHR %16:_, %17:_(s32) +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %16:_(s32) = G_SHL %1:_, %17:_(s32) +.. opcode 127 is aliased to 129 +Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %17:_(s32) = G_CONSTANT i32 16 +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +Legalizing: %3:_(s32) = G_CONSTANT i32 16 +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. Already legal +.. No debug info was present +.. No debug info was present +# *** IR Dump After Legalizer (legalizer) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %17:_(s32) = G_CONSTANT i32 16 + %16:_(s32) = G_SHL %1:_, %17:_(s32) + %5:_(s32) = G_ASHR %16:_, %17:_(s32) + %15:_(s32) = G_CONSTANT i32 16 + %14:_(s32) = G_SHL %2:_, %15:_(s32) + %7:_(s32) = G_ASHR %14:_, %15:_(s32) + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISCVPostLegalizerCombiner (riscv-postlegalizer-combiner) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %17:_(s32) = G_CONSTANT i32 16 + %16:_(s32) = G_SHL %1:_, %17:_(s32) + %5:_(s32) = G_ASHR %16:_, %17:_(s32) + %15:_(s32) = G_CONSTANT i32 16 + %14:_(s32) = G_SHL %2:_, %15:_(s32) + %7:_(s32) = G_ASHR %14:_, %15:_(s32) + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Generic MI Combiner for: test_macs32_v2i16 + +Try combining %0:_(s32) = COPY $x10 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19 +1442: GIM_Reject +1442: Rejected + +Try combining %1:_(s32) = COPY $x11 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19 +1442: GIM_Reject +1442: Rejected + +Try combining %2:_(s32) = COPY $x12 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19 +1442: GIM_Reject +1442: Rejected + +Try combining %3:_(s32) = G_CONSTANT i32 16 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=120 +1442: GIM_Reject +1442: Rejected + +Try combining %17:_(s32) = G_CONSTANT i32 16 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=120 +1442: GIM_Reject +1442: Rejected + +Try combining %16:_(s32) = G_SHL %1:_, %17:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=127 +1158: Begin try-block +1165: GIM_CheckSimplePredicate(Predicate=3) +1169: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1169: Rejected +1182: Resume at 1182 (1 try-blocks remain) +1183: GIM_Reject +1183: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %5:_(s32) = G_ASHR %16:_, %17:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129 +1210: Begin try-block +1217: GIM_CheckSimplePredicate(Predicate=3) +1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1221: Rejected +1234: Resume at 1234 (1 try-blocks remain) +1235: GIM_Reject +1235: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %15:_(s32) = G_CONSTANT i32 16 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=120 +1442: GIM_Reject +1442: Rejected + +Try combining %14:_(s32) = G_SHL %2:_, %15:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=127 +1158: Begin try-block +1165: GIM_CheckSimplePredicate(Predicate=3) +1169: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1169: Rejected +1182: Resume at 1182 (1 try-blocks remain) +1183: GIM_Reject +1183: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %7:_(s32) = G_ASHR %14:_, %15:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129 +1210: Begin try-block +1217: GIM_CheckSimplePredicate(Predicate=3) +1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1221: Rejected +1234: Resume at 1234 (1 try-blocks remain) +1235: GIM_Reject +1235: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %8:_(s32) = nsw G_MUL %7:_, %5:_ +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=49 +763: Begin try-block +770: GIM_CheckSimplePredicate(Predicate=6) +774: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +774: Rejected +787: Resume at 787 (1 try-blocks remain) +788: Begin try-block +795: GIM_CheckSimplePredicate(Predicate=11) +799: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1) +799: Rejected +812: Resume at 812 (1 try-blocks remain) +813: GIM_Reject +813: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %9:_(s32) = G_ASHR %1:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129 +1210: Begin try-block +1217: GIM_CheckSimplePredicate(Predicate=3) +1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1221: Rejected +1234: Resume at 1234 (1 try-blocks remain) +1235: GIM_Reject +1235: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %10:_(s32) = G_ASHR %2:_, %3:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=129 +1210: Begin try-block +1217: GIM_CheckSimplePredicate(Predicate=3) +1221: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +1221: Rejected +1234: Resume at 1234 (1 try-blocks remain) +1235: GIM_Reject +1235: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %11:_(s32) = nsw G_MUL %10:_, %9:_ +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=49 +763: Begin try-block +770: GIM_CheckSimplePredicate(Predicate=6) +774: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +774: Rejected +787: Resume at 787 (1 try-blocks remain) +788: Begin try-block +795: GIM_CheckSimplePredicate(Predicate=11) +799: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=1) +799: Rejected +812: Resume at 812 (1 try-blocks remain) +813: GIM_Reject +813: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %12:_(s32) = G_ADD %11:_, %0:_ +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=47 +639: Begin try-block +646: GIM_CheckSimplePredicate(Predicate=13) +650: MIs[1] = GIM_RecordInsn(0, 1) +654: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49 +654: Rejected +674: Resume at 674 (1 try-blocks remain) +675: Begin try-block +682: GIM_CheckSimplePredicate(Predicate=13) +686: MIs[1] = GIM_RecordInsn(0, 2) +690: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=19 +690: Rejected +710: Resume at 710 (1 try-blocks remain) +711: Begin try-block +718: GIM_CheckSimplePredicate(Predicate=3) +722: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +722: Rejected +735: Resume at 735 (1 try-blocks remain) +736: GIM_Reject +736: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining %13:_(s32) = G_ADD %12:_, %8:_ +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=47 +639: Begin try-block +646: GIM_CheckSimplePredicate(Predicate=13) +650: MIs[1] = GIM_RecordInsn(0, 1) +654: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=47 +654: Rejected +674: Resume at 674 (1 try-blocks remain) +675: Begin try-block +682: GIM_CheckSimplePredicate(Predicate=13) +686: MIs[1] = GIM_RecordInsn(0, 2) +690: GIM_CheckOpcode(MIs[1], ExpectedOpcode=48) // Got=49 +690: Rejected +710: Resume at 710 (1 try-blocks remain) +711: Begin try-block +718: GIM_CheckSimplePredicate(Predicate=3) +722: GIM_CheckConstantInt(MIs[0]->getOperand(2), Value=0) +722: Rejected +735: Resume at 735 (1 try-blocks remain) +736: GIM_Reject +736: Rejected +1441: Resume at 1441 (0 try-blocks remain) +1442: GIM_Reject +1442: Rejected + +Try combining $x10 = COPY %13:_(s32) +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=19 +1442: GIM_Reject +1442: Rejected + +Try combining PseudoRET implicit $x10 +10: GIM_SwitchOpcode(MIs[0], [47, 204), Default=1441, JumpTable...) // Got=377 +1442: GIM_Reject +1442: Rejected +# *** IR Dump After RISCVPostLegalizerCombiner (riscv-postlegalizer-combiner) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %17:_(s32) = G_CONSTANT i32 16 + %16:_(s32) = G_SHL %1:_, %17:_(s32) + %5:_(s32) = G_ASHR %16:_, %17:_(s32) + %15:_(s32) = G_CONSTANT i32 16 + %14:_(s32) = G_SHL %2:_, %15:_(s32) + %7:_(s32) = G_ASHR %14:_, %15:_(s32) + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RegBankSelect (regbankselect) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:_(s32) = COPY $x10 + %1:_(s32) = COPY $x11 + %2:_(s32) = COPY $x12 + %3:_(s32) = G_CONSTANT i32 16 + %17:_(s32) = G_CONSTANT i32 16 + %16:_(s32) = G_SHL %1:_, %17:_(s32) + %5:_(s32) = G_ASHR %16:_, %17:_(s32) + %15:_(s32) = G_CONSTANT i32 16 + %14:_(s32) = G_SHL %2:_, %15:_(s32) + %7:_(s32) = G_ASHR %14:_, %15:_(s32) + %8:_(s32) = nsw G_MUL %7:_, %5:_ + %9:_(s32) = G_ASHR %1:_, %3:_(s32) + %10:_(s32) = G_ASHR %2:_, %3:_(s32) + %11:_(s32) = nsw G_MUL %10:_, %9:_ + %12:_(s32) = G_ADD %11:_, %0:_ + %13:_(s32) = G_ADD %12:_, %8:_ + $x10 = COPY %13:_(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Assign register banks for: test_macs32_v2i16 +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. opcode 127 is aliased to 129 +Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. opcode 127 is aliased to 129 +Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Assign: %0:_(s32) = COPY $x10 +Evaluating mapping cost for: %0:_(s32) = COPY $x10 +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +Assign: %1:_(s32) = COPY $x11 +Evaluating mapping cost for: %1:_(s32) = COPY $x11 +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +Assign: %2:_(s32) = COPY $x12 +Evaluating mapping cost for: %2:_(s32) = COPY $x12 +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +Assign: %3:_(s32) = G_CONSTANT i32 16 +Evaluating mapping cost for: %3:_(s32) = G_CONSTANT i32 16 +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 } +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 } +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 is not a register, nothing to be done +Assign: %17:_(s32) = G_CONSTANT i32 16 +Evaluating mapping cost for: %17:_(s32) = G_CONSTANT i32 16 +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 } +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 } +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 is not a register, nothing to be done +Assign: %16:_(s32) = G_SHL %1:gprb, %17:gprb(s32) +Evaluating mapping cost for: %16:_(s32) = G_SHL %1:gprb, %17:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %5:_(s32) = G_ASHR %16:gprb, %17:gprb(s32) +Evaluating mapping cost for: %5:_(s32) = G_ASHR %16:gprb, %17:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %15:_(s32) = G_CONSTANT i32 16 +Evaluating mapping cost for: %15:_(s32) = G_CONSTANT i32 16 +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 } +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 0 } +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 is not a register, nothing to be done +Assign: %14:_(s32) = G_SHL %2:gprb, %15:gprb(s32) +Evaluating mapping cost for: %14:_(s32) = G_SHL %2:gprb, %15:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %7:_(s32) = G_ASHR %14:gprb, %15:gprb(s32) +Evaluating mapping cost for: %7:_(s32) = G_ASHR %14:gprb, %15:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %8:_(s32) = nsw G_MUL %7:gprb, %5:gprb +Evaluating mapping cost for: %8:_(s32) = nsw G_MUL %7:gprb, %5:gprb +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %9:_(s32) = G_ASHR %1:gprb, %3:gprb(s32) +Evaluating mapping cost for: %9:_(s32) = G_ASHR %1:gprb, %3:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %10:_(s32) = G_ASHR %2:gprb, %3:gprb(s32) +Evaluating mapping cost for: %10:_(s32) = G_ASHR %2:gprb, %3:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %11:_(s32) = nsw G_MUL %10:gprb, %9:gprb +Evaluating mapping cost for: %11:_(s32) = nsw G_MUL %10:gprb, %9:gprb +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %12:_(s32) = G_ADD %11:gprb, %0:gprb +Evaluating mapping cost for: %12:_(s32) = G_ADD %11:gprb, %0:gprb +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: %13:_(s32) = G_ADD %12:gprb, %8:gprb +Evaluating mapping cost for: %13:_(s32) = G_ADD %12:gprb, %8:gprb +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Opd0 +Does assignment already match: none against GPRB +=> is free (simple assignment). +Opd1 +Does assignment already match: GPRB against GPRB +=> is free (match). +Opd2 +Does assignment already match: GPRB against GPRB +=> is free (match). +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 1 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]}, { Idx: 2 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0 has not been repaired, nothing to be done +OpIdx 1 has not been repaired, nothing to be done +OpIdx 2 has not been repaired, nothing to be done +Assign: $x10 = COPY %13:gprb(s32) +Evaluating mapping cost for: $x10 = COPY %13:gprb(s32) +With: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Total cost is: 1 * 1 + 0 +Best Mapping: ID: 4294967295 Cost: 1 Mapping: { Idx: 0 Map: #BreakDown: 1 [[0, 31], RegBank = GPRB]} +Actual mapping of the operands: Mapping ID: 4294967295 Operand Mapping: +Applying default-like mapping +OpIdx 0# *** IR Dump After RegBankSelect (regbankselect) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = G_CONSTANT i32 16 + %17:gprb(s32) = G_CONSTANT i32 16 + %16:gprb(s32) = G_SHL %1:gprb, %17:gprb(s32) + %5:gprb(s32) = G_ASHR %16:gprb, %17:gprb(s32) + %15:gprb(s32) = G_CONSTANT i32 16 + %14:gprb(s32) = G_SHL %2:gprb, %15:gprb(s32) + %7:gprb(s32) = G_ASHR %14:gprb, %15:gprb(s32) + %8:gprb(s32) = nsw G_MUL %7:gprb, %5:gprb + %9:gprb(s32) = G_ASHR %1:gprb, %3:gprb(s32) + %10:gprb(s32) = G_ASHR %2:gprb, %3:gprb(s32) + %11:gprb(s32) = nsw G_MUL %10:gprb, %9:gprb + %12:gprb(s32) = G_ADD %11:gprb, %0:gprb + %13:gprb(s32) = G_ADD %12:gprb, %8:gprb + $x10 = COPY %13:gprb(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before InstructionSelect (instruction-select) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gprb(s32) = COPY $x10 + %1:gprb(s32) = COPY $x11 + %2:gprb(s32) = COPY $x12 + %3:gprb(s32) = G_CONSTANT i32 16 + %17:gprb(s32) = G_CONSTANT i32 16 + %16:gprb(s32) = G_SHL %1:gprb, %17:gprb(s32) + %5:gprb(s32) = G_ASHR %16:gprb, %17:gprb(s32) + %15:gprb(s32) = G_CONSTANT i32 16 + %14:gprb(s32) = G_SHL %2:gprb, %15:gprb(s32) + %7:gprb(s32) = G_ASHR %14:gprb, %15:gprb(s32) + %8:gprb(s32) = nsw G_MUL %7:gprb, %5:gprb + %9:gprb(s32) = G_ASHR %1:gprb, %3:gprb(s32) + %10:gprb(s32) = G_ASHR %2:gprb, %3:gprb(s32) + %11:gprb(s32) = nsw G_MUL %10:gprb, %9:gprb + %12:gprb(s32) = G_ADD %11:gprb, %0:gprb + %13:gprb(s32) = G_ADD %12:gprb, %8:gprb + $x10 = COPY %13:gprb(s32) + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Selecting function: test_macs32_v2i16 +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. opcode 127 is aliased to 129 +Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=120, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +.. opcode 127 is aliased to 129 +Applying legalizer ruleset to: Opcode=127, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=129, Tys={s32, s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=49, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Applying legalizer ruleset to: Opcode=47, Tys={s32, }, MMOs={} +.. match +.. .. Legal, 0, LLT_invalid +Selecting: + PseudoRET implicit $x10 +Into: + PseudoRET implicit $x10 + +Selecting: + $x10 = COPY %13:gprb(s32) +Into: + $x10 = COPY %13:gprb(s32) + +Selecting: + %13:gprb(s32) = G_ADD %12:gprb, %8:gprb +10: GIM_SwitchOpcode(MIs[0], [47, 276), Default=475249, JumpTable...) // Got=47 +937: GIM_SwitchType(MIs[0]->getOperand(0), [3, 34), Default=14879, JumpTable...) // Got=s32 +1062: Begin try-block +1070: GIM_CheckType(MIs[0]->getOperand(1), TypeID=3) +1074: GIM_CheckType(MIs[0]->getOperand(2), TypeID=3) +1075: Begin try-block +1082: GIM_CheckFeatures(ExpectedBitsetID=159) +1082: Rejected +1280: Resume at 1280 (3 try-blocks remain) +1281: Begin try-block +1288: GIM_CheckFeatures(ExpectedBitsetID=160) +1293: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +1297: MIs[1] = GIM_RecordInsn(0, 1) +1301: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=47 +1301: Rejected +1486: Resume at 1486 (3 try-blocks remain) +1487: Begin try-block +1494: GIM_CheckFeatures(ExpectedBitsetID=159) +1494: Rejected +1692: Resume at 1692 (3 try-blocks remain) +1693: Begin try-block +1700: GIM_CheckFeatures(ExpectedBitsetID=160) +1705: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +1709: MIs[1] = GIM_RecordInsn(0, 1) +1713: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=47 +1713: Rejected +1898: Resume at 1898 (3 try-blocks remain) +1899: Begin try-block +1906: GIM_CheckFeatures(ExpectedBitsetID=159) +1906: Rejected +2104: Resume at 2104 (3 try-blocks remain) +2105: Begin try-block +2112: GIM_CheckFeatures(ExpectedBitsetID=160) +2117: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +2122: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3) +2126: MIs[1] = GIM_RecordInsn(0, 2) +2130: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +2134: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +2138: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +2142: MIs[2] = GIM_RecordInsn(1, 1) +2146: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +2150: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +2154: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +2158: MIs[3] = GIM_RecordInsn(2, 1) +2162: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=127 +2166: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3) +2170: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3) +2174: MIs[4] = GIM_RecordInsn(3, 1) +2178: GIM_CheckOpcode(MIs[4], ExpectedOpcode=129) // Got=19 +2178: Rejected +2310: Resume at 2310 (3 try-blocks remain) +2311: Begin try-block +2318: GIM_CheckFeatures(ExpectedBitsetID=159) +2318: Rejected +2516: Resume at 2516 (3 try-blocks remain) +2517: Begin try-block +2524: GIM_CheckFeatures(ExpectedBitsetID=160) +2529: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +2534: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3) +2538: MIs[1] = GIM_RecordInsn(0, 2) +2542: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +2546: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +2550: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +2554: MIs[2] = GIM_RecordInsn(1, 1) +2558: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +2562: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +2566: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +2570: MIs[3] = GIM_RecordInsn(2, 1) +2574: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=127 +2578: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3) +2582: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3) +2586: MIs[4] = GIM_RecordInsn(3, 1) +2590: GIM_CheckOpcode(MIs[4], ExpectedOpcode=128) // Got=19 +2590: Rejected +2722: Resume at 2722 (3 try-blocks remain) +2723: Begin try-block +2730: GIM_CheckFeatures(ExpectedBitsetID=164) +2730: Rejected +2881: Resume at 2881 (3 try-blocks remain) +2882: Begin try-block +2889: GIM_CheckFeatures(ExpectedBitsetID=165) +2894: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +2898: MIs[1] = GIM_RecordInsn(0, 1) +2902: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=47 +2902: Rejected +3040: Resume at 3040 (3 try-blocks remain) +3041: Begin try-block +3048: GIM_CheckFeatures(ExpectedBitsetID=164) +3048: Rejected +3199: Resume at 3199 (3 try-blocks remain) +3200: Begin try-block +3207: GIM_CheckFeatures(ExpectedBitsetID=165) +3212: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +3217: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3) +3221: MIs[1] = GIM_RecordInsn(0, 2) +3225: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +3229: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +3233: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +3237: MIs[2] = GIM_RecordInsn(1, 1) +3241: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +3245: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +3249: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +3253: MIs[3] = GIM_RecordInsn(2, 1) +3257: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=127 +3261: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3) +3265: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3) +3270: GIM_CheckRegBankForClass(MIs[3]->getOperand(1), RCEnum=3) +3274: GIM_CheckConstantInt(MIs[3]->getOperand(2), Value=16) +3278: GIM_CheckConstantInt(MIs[2]->getOperand(2), Value=16) +3282: MIs[4] = GIM_RecordInsn(1, 2) +3286: GIM_CheckOpcode(MIs[4], ExpectedOpcode=129) // Got=129 +3290: GIM_CheckType(MIs[4]->getOperand(1), TypeID=3) +3294: GIM_CheckType(MIs[4]->getOperand(2), TypeID=3) +3298: MIs[5] = GIM_RecordInsn(4, 1) +3302: GIM_CheckOpcode(MIs[5], ExpectedOpcode=127) // Got=127 +3306: GIM_CheckType(MIs[5]->getOperand(1), TypeID=3) +3310: GIM_CheckType(MIs[5]->getOperand(2), TypeID=3) +3315: GIM_CheckRegBankForClass(MIs[5]->getOperand(1), RCEnum=3) +3319: GIM_CheckConstantInt(MIs[5]->getOperand(2), Value=16) +3323: GIM_CheckConstantInt(MIs[4]->getOperand(2), Value=16) +3325: GIM_CheckIsSafeToFold(MIs[1]) +3327: GIM_CheckIsSafeToFold(MIs[2]) +3329: GIM_CheckIsSafeToFold(MIs[3]) +3331: GIM_CheckIsSafeToFold(MIs[4]) +3333: GIM_CheckIsSafeToFold(MIs[5]) +3337: GIR_BuildMI(OutMIs[0], 13145) +3341: GIR_Copy(OutMIs[0], MIs[0], 0) +3345: GIR_Copy(OutMIs[0], MIs[0], 1) +3349: GIR_Copy(OutMIs[0], MIs[5], 1) +3353: GIR_Copy(OutMIs[0], MIs[3], 1) +Converting operand: %13:gprb +Converting operand: %12:gprb(tied-def 0) +Converting operand: %1:gprb +Converting operand: %2:gprb +3355: GIR_ConstrainSelectedInstOperands(OutMIs[0]) +3357: GIR_EraseFromParent(MIs[0]) +3358: GIR_Done +Into: + %13:gpr(s32) = cv_macs_i16_ %12:gpr(tied-def 0)(s32), %1:gpr(s32), %2:gpr(s32) + +Selecting: + %12:gpr(s32) = G_ADD %11:gprb, %0:gprb +10: GIM_SwitchOpcode(MIs[0], [47, 276), Default=475249, JumpTable...) // Got=47 +937: GIM_SwitchType(MIs[0]->getOperand(0), [3, 34), Default=14879, JumpTable...) // Got=s32 +1062: Begin try-block +1070: GIM_CheckType(MIs[0]->getOperand(1), TypeID=3) +1074: GIM_CheckType(MIs[0]->getOperand(2), TypeID=3) +1075: Begin try-block +1082: GIM_CheckFeatures(ExpectedBitsetID=159) +1082: Rejected +1280: Resume at 1280 (3 try-blocks remain) +1281: Begin try-block +1288: GIM_CheckFeatures(ExpectedBitsetID=160) +1293: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +1297: MIs[1] = GIM_RecordInsn(0, 1) +1301: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +1305: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +1309: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +1313: MIs[2] = GIM_RecordInsn(1, 1) +1317: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +1321: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +1325: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +1329: MIs[3] = GIM_RecordInsn(2, 1) +1333: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=19 +1333: Rejected +1486: Resume at 1486 (3 try-blocks remain) +1487: Begin try-block +1494: GIM_CheckFeatures(ExpectedBitsetID=159) +1494: Rejected +1692: Resume at 1692 (3 try-blocks remain) +1693: Begin try-block +1700: GIM_CheckFeatures(ExpectedBitsetID=160) +1705: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +1709: MIs[1] = GIM_RecordInsn(0, 1) +1713: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +1717: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +1721: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +1725: MIs[2] = GIM_RecordInsn(1, 1) +1729: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +1733: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +1737: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +1741: MIs[3] = GIM_RecordInsn(2, 1) +1745: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=19 +1745: Rejected +1898: Resume at 1898 (3 try-blocks remain) +1899: Begin try-block +1906: GIM_CheckFeatures(ExpectedBitsetID=159) +1906: Rejected +2104: Resume at 2104 (3 try-blocks remain) +2105: Begin try-block +2112: GIM_CheckFeatures(ExpectedBitsetID=160) +2117: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +2122: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3) +2126: MIs[1] = GIM_RecordInsn(0, 2) +2130: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=19 +2130: Rejected +2310: Resume at 2310 (3 try-blocks remain) +2311: Begin try-block +2318: GIM_CheckFeatures(ExpectedBitsetID=159) +2318: Rejected +2516: Resume at 2516 (3 try-blocks remain) +2517: Begin try-block +2524: GIM_CheckFeatures(ExpectedBitsetID=160) +2529: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +2534: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3) +2538: MIs[1] = GIM_RecordInsn(0, 2) +2542: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=19 +2542: Rejected +2722: Resume at 2722 (3 try-blocks remain) +2723: Begin try-block +2730: GIM_CheckFeatures(ExpectedBitsetID=164) +2730: Rejected +2881: Resume at 2881 (3 try-blocks remain) +2882: Begin try-block +2889: GIM_CheckFeatures(ExpectedBitsetID=165) +2894: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +2898: MIs[1] = GIM_RecordInsn(0, 1) +2902: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +2906: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +2910: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +2914: MIs[2] = GIM_RecordInsn(1, 1) +2918: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +2922: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +2926: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +2930: MIs[3] = GIM_RecordInsn(2, 1) +2934: GIM_CheckOpcode(MIs[3], ExpectedOpcode=127) // Got=19 +2934: Rejected +3040: Resume at 3040 (3 try-blocks remain) +3041: Begin try-block +3048: GIM_CheckFeatures(ExpectedBitsetID=164) +3048: Rejected +3199: Resume at 3199 (3 try-blocks remain) +3200: Begin try-block +3207: GIM_CheckFeatures(ExpectedBitsetID=165) +3212: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +3217: GIM_CheckRegBankForClass(MIs[0]->getOperand(1), RCEnum=3) +3221: MIs[1] = GIM_RecordInsn(0, 2) +3225: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=19 +3225: Rejected +3358: Resume at 3358 (3 try-blocks remain) +3359: Begin try-block +3366: GIM_CheckFeatures(ExpectedBitsetID=159) +3366: Rejected +3476: Resume at 3476 (3 try-blocks remain) +3477: Begin try-block +3484: GIM_CheckFeatures(ExpectedBitsetID=160) +3489: GIM_CheckRegBankForClass(MIs[0]->getOperand(0), RCEnum=3) +3493: MIs[1] = GIM_RecordInsn(0, 1) +3497: GIM_CheckOpcode(MIs[1], ExpectedOpcode=49) // Got=49 +3501: GIM_CheckType(MIs[1]->getOperand(1), TypeID=3) +3505: GIM_CheckType(MIs[1]->getOperand(2), TypeID=3) +3509: MIs[2] = GIM_RecordInsn(1, 1) +3513: GIM_CheckOpcode(MIs[2], ExpectedOpcode=129) // Got=129 +3517: GIM_CheckType(MIs[2]->getOperand(1), TypeID=3) +3521: GIM_CheckType(MIs[2]->getOperand(2), TypeID=3) +3526: GIM_CheckRegBankForClass(MIs[2]->getOperand(1), RCEnum=3) +3530: GIM_CheckConstantInt(MIs[2]->getOperand(2), Value=16) +3534: MIs[3] = GIM_RecordInsn(1, 2) +3538: GIM_CheckOpcode(MIs[3], ExpectedOpcode=129) // Got=129 +3542: GIM_CheckType(MIs[3]->getOperand(1), TypeID=3) +3546: GIM_CheckType(MIs[3]->getOperand(2), TypeID=3) +3551: GIM_CheckRegBankForClass(MIs[3]->getOperand(1), RCEnum=3) +3555: GIM_CheckConstantInt(MIs[3]->getOperand(2), Value=16) +3560: GIM_CheckRegBankForClass(MIs[0]->getOperand(2), RCEnum=3) +3562: GIM_CheckIsSafeToFold(MIs[1]) +3564: GIM_CheckIsSafeToFold(MIs[2]) +3566: GIM_CheckIsSafeToFold(MIs[3]) +3570: GIR_BuildMI(OutMIs[0], 13137) +3574: GIR_Copy(OutMIs[0], MIs[0], 0) +3578: GIR_Copy(OutMIs[0], MIs[0], 2) +3582: GIR_Copy(OutMIs[0], MIs[3], 1) +3586: GIR_Copy(OutMIs[0], MIs[2], 1) +3589: GIR_AddImm(OutMIs[0], 0) +Converting operand: %12:gpr +Converting operand: %0:gprb(tied-def 0) +Converting operand: %1:gpr +Converting operand: %2:gpr +3591: GIR_ConstrainSelectedInstOperands(OutMIs[0]) +3593: GIR_EraseFromParent(MIs[0]) +3594: GIR_Done +Into: + %12:gpr(s32) = cv_machhNs_ %0:gpr(tied-def 0)(s32), %1:gpr(s32), %2:gpr(s32), 0 + +Selecting: + %11:gprb(s32) = nsw G_MUL %10:gprb, %9:gprb +Is dead; erasing. +Selecting: + %10:gprb(s32) = G_ASHR %2:gpr, %3:gprb(s32) +Is dead; erasing. +Selecting: + %9:gprb(s32) = G_ASHR %1:gpr, %3:gprb(s32) +Is dead; erasing. +Selecting: + %8:gprb(s32) = nsw G_MUL %7:gprb, %5:gprb +Is dead; erasing. +Selecting: + %7:gprb(s32) = G_ASHR %14:gprb, %15:gprb(s32) +Is dead; erasing. +Selecting: + %14:gprb(s32) = G_SHL %2:gpr, %15:gprb(s32) +Is dead; erasing. +Selecting: + %15:gprb(s32) = G_CONSTANT i32 16 +Is dead; erasing. +Selecting: + %5:gprb(s32) = G_ASHR %16:gprb, %17:gprb(s32) +Is dead; erasing. +Selecting: + %16:gprb(s32) = G_SHL %1:gpr, %17:gprb(s32) +Is dead; erasing. +Selecting: + %17:gprb(s32) = G_CONSTANT i32 16 +Is dead; erasing. +Selecting: + %3:gprb(s32) = G_CONSTANT i32 16 +Is dead; erasing. +Selecting: + %2:gpr(s32) = COPY $x12 +Into: + %2:gpr(s32) = COPY $x12 + +Selecting: + %1:gpr(s32) = COPY $x11 +Into: + %1:gpr(s32) = COPY $x11 + +Selecting: + %0:gpr(s32) = COPY $x10 +Into: + %0:gpr(s32) = COPY $x10 + +Rules covered by selecting function: test_macs32_v2i16: + +# *** IR Dump After InstructionSelect (instruction-select) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Finalize ISel and expand pseudo-instructions (finalize-isel) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Finalize ISel and expand pseudo-instructions (finalize-isel) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Fold Masks (riscv-fold-masks) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Fold Masks (riscv-fold-masks) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Early Tail Duplication (early-tailduplication) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Early Tail Duplication (early-tailduplication) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Optimize machine instruction PHIs (opt-phis) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Optimize machine instruction PHIs (opt-phis) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Slot index numbering (slotindexes) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +0B bb.1.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +64B %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +80B %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr +96B $x10 = COPY %13:gpr +112B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Slot index numbering (slotindexes) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +0B bb.1.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +64B %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +80B %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr +96B $x10 = COPY %13:gpr +112B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Merge disjoint stack slots (stack-coloring) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +0B bb.1.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +64B %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +80B %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr +96B $x10 = COPY %13:gpr +112B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** Stack Coloring ********** +********** Function: test_macs32_v2i16 +# *** IR Dump After Merge disjoint stack slots (stack-coloring) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Local Stack Slot Allocation (localstackalloc) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Local Stack Slot Allocation (localstackalloc) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Remove dead machine instructions (dead-mi-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Remove dead machine instructions (dead-mi-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: BB1[entry] +loop-detection +compute-mass-in-function + - node: BB1[entry] + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - BB1[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - BB1[entry]: float = 1.0, int = 18014398509481984 + +# *** IR Dump Before Early Machine Loop Invariant Code Motion (early-machinelicm) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +******** Pre-regalloc Machine LICM: test_macs32_v2i16 ******** +# *** IR Dump After Early Machine Loop Invariant Code Motion (early-machinelicm) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: BB1[entry] +loop-detection +compute-mass-in-function + - node: BB1[entry] + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - BB1[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - BB1[entry]: float = 1.0, int = 18014398509481984 + +# *** IR Dump Before Machine Common Subexpression Elimination (machine-cse) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Entering: entry +Exiting: entry +# *** IR Dump After Machine Common Subexpression Elimination (machine-cse) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + Looking for trivial roots +Found a new trivial root: %bb.1 +Last visited node: %bb.1 + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %bb.1 +Found roots: %bb.1 +Computing cycles for function: test_macs32_v2i16 +Entry block: bb.1.entry +DFS visiting block: bb.1.entry + first encountered at depth 1 + preorder number: 1 +DFS visiting block: bb.1.entry + ended at 1 +Preorder: + bb.1.entry: 0 +# *** IR Dump Before Machine code sinking (machine-sink) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +******** Machine Sinking ******** +# *** IR Dump After Machine code sinking (machine-sink) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Peephole Optimizations (peephole-opt) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** PEEPHOLE OPTIMIZER ********** +********** Function: test_macs32_v2i16 +# *** IR Dump After Peephole Optimizations (peephole-opt) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Remove dead machine instructions (dead-mi-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Remove dead machine instructions (dead-mi-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine InstCombiner (machine-combiner) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Machine InstCombiner: test_macs32_v2i16 +Combining MBB entry +# *** IR Dump After Machine InstCombiner (machine-combiner) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Pre-RA pseudo instruction expansion pass (riscv-prera-expand-pseudo) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Pre-RA pseudo instruction expansion pass (riscv-prera-expand-pseudo) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Merge Base Offset (riscv-merge-base-offset) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +MBB: entry +# *** IR Dump After RISC-V Merge Base Offset (riscv-merge-base-offset) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Insert VSETVLI pass (riscv-insert-vsetvli) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Insert VSETVLI pass (riscv-insert-vsetvli) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Dead register definitions (riscv-dead-defs) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +***** RISCVDeadRegisterDefinitions ***** +# *** IR Dump After RISC-V Dead register definitions (riscv-dead-defs) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Insert Read/Write CSR Pass (riscv-insert-read-write-csr) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Insert Read/Write CSR Pass (riscv-insert-read-write-csr) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Insert Write VXRM Pass (riscv-insert-write-vxrm) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Insert Write VXRM Pass (riscv-insert-write-vxrm) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Detect Dead Lanes (detect-dead-lanes) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Defined/Used lanes: +%0 Used: 0000000000000001 Def: 0000000000000001 +%1 Used: 0000000000000001 Def: 0000000000000001 +%2 Used: 0000000000000001 Def: 0000000000000001 +%3 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%4 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%5 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%6 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%7 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%8 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%9 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%10 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%11 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%12 Used: 0000000000000001 Def: 0000000000000001 +%13 Used: 0000000000000001 Def: 0000000000000001 +%14 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%15 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%16 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF +%17 Used: 0000000000000000 Def: FFFFFFFFFFFFFFFF + +# *** IR Dump After Detect Dead Lanes (detect-dead-lanes) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V init undef pass (riscv-init-undef) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V init undef pass (riscv-init-undef) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Process Implicit Definitions (processimpdefs) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** PROCESS IMPLICIT DEFS ********** +********** Function: test_macs32_v2i16 +# *** IR Dump After Process Implicit Definitions (processimpdefs) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Remove unreachable machine basic blocks (unreachable-mbb-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.1.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Remove unreachable machine basic blocks (unreachable-mbb-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Live Variable Analysis (livevars) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %12:gpr = cv_machhNs_ %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %12:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Live Variable Analysis (livevars) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY killed $x10 + %1:gpr = COPY killed $x11 + %2:gpr = COPY killed $x12 + %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + $x10 = COPY killed %13:gpr + PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Eliminate PHI nodes for register allocation (phi-node-elimination) ***: +# Machine code for function test_macs32_v2i16: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY killed $x10 + %1:gpr = COPY killed $x11 + %2:gpr = COPY killed $x12 + %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + $x10 = COPY killed %13:gpr + PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Eliminate PHI nodes for register allocation (phi-node-elimination) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY killed $x10 + %1:gpr = COPY killed $x11 + %2:gpr = COPY killed $x12 + %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + $x10 = COPY killed %13:gpr + PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Two-Address instruction pass (twoaddressinstruction) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY killed $x10 + %1:gpr = COPY killed $x11 + %2:gpr = COPY killed $x12 + %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + $x10 = COPY killed %13:gpr + PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +********** REWRITING TWO-ADDR INSTRS ********** +********** Function: test_macs32_v2i16 + %12:gpr = cv_machhNs_ killed %0:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + prepend: %12:gpr = COPY %0:gpr + rewrite to: %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ killed %12:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + prepend: %13:gpr = COPY %12:gpr + rewrite to: %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr +# *** IR Dump After Two-Address instruction pass (twoaddressinstruction) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY killed $x10 + %1:gpr = COPY killed $x11 + %2:gpr = COPY killed $x12 + %12:gpr = COPY killed %0:gpr + %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = COPY killed %12:gpr + %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + $x10 = COPY killed %13:gpr + PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Slot index numbering (slotindexes) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %0:gpr = COPY killed $x10 + %1:gpr = COPY killed $x11 + %2:gpr = COPY killed $x12 + %12:gpr = COPY killed %0:gpr + %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = COPY killed %12:gpr + %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr + $x10 = COPY killed %13:gpr + PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY killed $x10 +32B %1:gpr = COPY killed $x11 +48B %2:gpr = COPY killed $x12 +64B %12:gpr = COPY killed %0:gpr +80B %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +96B %13:gpr = COPY killed %12:gpr +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr +128B $x10 = COPY killed %13:gpr +144B PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Slot index numbering (slotindexes) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY killed $x10 +32B %1:gpr = COPY killed $x11 +48B %2:gpr = COPY killed $x12 +64B %12:gpr = COPY killed %0:gpr +80B %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +96B %13:gpr = COPY killed %12:gpr +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr +128B $x10 = COPY killed %13:gpr +144B PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Live Interval Analysis (liveintervals) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY killed $x10 +32B %1:gpr = COPY killed $x11 +48B %2:gpr = COPY killed $x12 +64B %12:gpr = COPY killed %0:gpr +80B %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +96B %13:gpr = COPY killed %12:gpr +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr +128B $x10 = COPY killed %13:gpr +144B PseudoRET implicit killed $x10 + +# End machine code for function test_macs32_v2i16. + +Computing live-in reg-units in ABI blocks. +0B %bb.0 X10#0 X11#0 X12#0 +Created 3 new intervals. +********** INTERVALS ********** +X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +X11 [0B,32r:0) 0@0B-phi +X12 [0B,48r:0) 0@0B-phi +%0 [16r,64r:0) 0@16r weight:0.000000e+00 +%1 [32r,112r:0) 0@32r weight:0.000000e+00 +%2 [48r,112r:0) 0@48r weight:0.000000e+00 +%12 [64r,80r:0)[80r,96r:1) 0@64r 1@80r weight:0.000000e+00 +%13 [96r,112r:0)[112r,128r:1) 0@96r 1@112r weight:0.000000e+00 +RegMasks: +********** MACHINEINSTRS ********** +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +64B %12:gpr = COPY %0:gpr +80B %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +96B %13:gpr = COPY %12:gpr +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Live Interval Analysis (liveintervals) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +64B %12:gpr = COPY %0:gpr +80B %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +96B %13:gpr = COPY %12:gpr +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Register Coalescer (register-coalescer) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %0:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +64B %12:gpr = COPY %0:gpr +80B %12:gpr = cv_machhNs_ %12:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +96B %13:gpr = COPY %12:gpr +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** REGISTER COALESCER ********** +********** Function: test_macs32_v2i16 +********** JOINING INTERVALS *********** +entry: +16B %0:gpr = COPY $x10 + Considering merging %0 with $x10 + Can only merge into reserved registers. +32B %1:gpr = COPY $x11 + Considering merging %1 with $x11 + Can only merge into reserved registers. +48B %2:gpr = COPY $x12 + Considering merging %2 with $x12 + Can only merge into reserved registers. +128B $x10 = COPY %13:gpr + Considering merging %13 with $x10 + Can only merge into reserved registers. +64B %12:gpr = COPY %0:gpr + Considering merging to GPR with %0 in %12 + RHS = %0 [16r,64r:0) 0@16r weight:0.000000e+00 + LHS = %12 [64r,80r:0)[80r,96r:1) 0@64r 1@80r weight:0.000000e+00 + merge %12:0@64r into %0:0@16r --> @16r + erased: 64r %12:gpr = COPY %0:gpr +AllocationOrder(GPR) = [ $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x5 $x6 $x7 $x28 $x29 $x30 $x31 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x1 ] + updated: 16B %12:gpr = COPY $x10 + Success: %0 -> %12 + Result = %12 [16r,80r:0)[80r,96r:1) 0@16r 1@80r weight:0.000000e+00 +96B %13:gpr = COPY %12:gpr + Considering merging to GPR with %12 in %13 + RHS = %12 [16r,80r:0)[80r,96r:1) 0@16r 1@80r weight:0.000000e+00 + LHS = %13 [96r,112r:0)[112r,128r:1) 0@96r 1@112r weight:0.000000e+00 + merge %13:0@96r into %12:1@80r --> @80r + erased: 96r %13:gpr = COPY %12:gpr + updated: 16B %13:gpr = COPY $x10 + updated: 80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + Success: %12 -> %13 + Result = %13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r weight:0.000000e+00 +Trying to inflate 0 regs. +********** INTERVALS ********** +X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +X11 [0B,32r:0) 0@0B-phi +X12 [0B,48r:0) 0@0B-phi +%1 [32r,112r:0) 0@32r weight:0.000000e+00 +%2 [48r,112r:0) 0@48r weight:0.000000e+00 +%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r weight:0.000000e+00 +RegMasks: +********** MACHINEINSTRS ********** +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Register Coalescer (register-coalescer) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Rename Disconnected Subregister Components (rename-independent-subregs) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Renaming independent subregister live ranges in test_macs32_v2i16 +# *** IR Dump After Rename Disconnected Subregister Components (rename-independent-subregs) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Instruction Scheduler (machine-scheduler) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Before MISched: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + %13:gpr = COPY $x10 + %1:gpr = COPY $x11 + %2:gpr = COPY $x12 + %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr + $x10 = COPY %13:gpr + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +AllocationOrder(GPR) = [ $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x5 $x6 $x7 $x28 $x29 $x30 $x31 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x1 ] +********** MI Scheduling ********** +test_macs32_v2i16:%bb.0 entry + From: %13:gpr = COPY $x10 + To: PseudoRET implicit $x10 + RegionInstrs: 6 +ScheduleDAGMILive::schedule starting +GenericScheduler RegionPolicy: ShouldTrackPressure=0 OnlyTopDown=0 OnlyBottomUp=1 +Disabled scoreboard hazard recognizer +Disabled scoreboard hazard recognizer +SU(0): %13:gpr = COPY $x10 + # preds left : 0 + # succs left : 3 + # rdefs left : 0 + Latency : 0 + Depth : 0 + Height : 3 + Successors: + SU(3): Data Latency=0 Reg=%13 + SU(3): Out Latency=1 + SU(5): Anti Latency=0 + Single Issue : false; +SU(1): %1:gpr = COPY $x11 + # preds left : 0 + # succs left : 2 + # rdefs left : 0 + Latency : 0 + Depth : 0 + Height : 2 + Successors: + SU(4): Data Latency=0 Reg=%1 + SU(3): Data Latency=0 Reg=%1 + Single Issue : false; +SU(2): %2:gpr = COPY $x12 + # preds left : 0 + # succs left : 2 + # rdefs left : 0 + Latency : 0 + Depth : 0 + Height : 2 + Successors: + SU(4): Data Latency=0 Reg=%2 + SU(3): Data Latency=0 Reg=%2 + Single Issue : false; +SU(3): %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + # preds left : 4 + # succs left : 2 + # rdefs left : 0 + Latency : 1 + Depth : 1 + Height : 2 + Predecessors: + SU(2): Data Latency=0 Reg=%2 + SU(1): Data Latency=0 Reg=%1 + SU(0): Data Latency=0 Reg=%13 + SU(0): Out Latency=1 + Successors: + SU(4): Data Latency=1 Reg=%13 + SU(4): Out Latency=1 + Single Issue : false; +SU(4): %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr + # preds left : 4 + # succs left : 1 + # rdefs left : 0 + Latency : 1 + Depth : 2 + Height : 1 + Predecessors: + SU(3): Data Latency=1 Reg=%13 + SU(3): Out Latency=1 + SU(2): Data Latency=0 Reg=%2 + SU(1): Data Latency=0 Reg=%1 + Successors: + SU(5): Data Latency=1 Reg=%13 + Single Issue : false; +SU(5): $x10 = COPY %13:gpr + # preds left : 2 + # succs left : 1 + # rdefs left : 0 + Latency : 0 + Depth : 3 + Height : 0 + Predecessors: + SU(4): Data Latency=1 Reg=%13 + SU(0): Anti Latency=0 + Successors: + ExitSU: Ord Latency=0 Artificial + Single Issue : false; +ExitSU: PseudoRET implicit $x10 + # preds left : 1 + # succs left : 0 + # rdefs left : 0 + Latency : 0 + Depth : 3 + Height : 0 + Predecessors: + SU(5): Ord Latency=0 Artificial +Critical Path(GS-RR ): 3 +** ScheduleDAGMILive::schedule picking next node +Queue BotQ.P: +Queue BotQ.A: 5 +Scheduling SU(5) $x10 = COPY %13:gpr + Ready @0c + BotQ.A TopLatency SU(5) 3c +BotQ.A @0c + Retired: 0 + Executed: 0c + Critical: 0c, 0 MOps + ExpectedLatency: 0c + - Latency limited. +** ScheduleDAGMILive::schedule picking next node +Cycle: 1 BotQ.A +Queue BotQ.P: +Queue BotQ.A: 4 +Scheduling SU(4) %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr + Ready @1c + BotQ.A BotLatency SU(4) 1c + *** Max MOps 1 at cycle 1 +Cycle: 2 BotQ.A +BotQ.A @2c + Retired: 1 + Executed: 2c + Critical: 1c, 1 MOps + ExpectedLatency: 1c + - Latency limited. +** ScheduleDAGMILive::schedule picking next node +Queue BotQ.P: +Queue BotQ.A: 3 +Scheduling SU(3) %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 + Ready @2c + BotQ.A BotLatency SU(3) 2c + *** Max MOps 1 at cycle 2 +Cycle: 3 BotQ.A +BotQ.A @3c + Retired: 2 + Executed: 3c + Critical: 2c, 2 MOps + ExpectedLatency: 2c + - Latency limited. +** ScheduleDAGMILive::schedule picking next node +Queue BotQ.P: +Queue BotQ.A: 2 1 0 + Cand SU(2) ORDER +Pick Bot ORDER +Scheduling SU(2) %2:gpr = COPY $x12 + Ready @3c +BotQ.A @3c + Retired: 2 + Executed: 3c + Critical: 2c, 2 MOps + ExpectedLatency: 2c + - Latency limited. +** ScheduleDAGMILive::schedule picking next node +Queue BotQ.P: +Queue BotQ.A: 0 1 + Cand SU(0) ORDER + Cand SU(1) ORDER +Pick Bot ORDER +Scheduling SU(1) %1:gpr = COPY $x11 + Ready @3c +BotQ.A @3c + Retired: 2 + Executed: 3c + Critical: 2c, 2 MOps + ExpectedLatency: 2c + - Latency limited. +** ScheduleDAGMILive::schedule picking next node +Queue BotQ.P: +Queue BotQ.A: 0 +Scheduling SU(0) %13:gpr = COPY $x10 + Ready @3c + BotQ.A BotLatency SU(0) 3c +BotQ.A @3c + Retired: 2 + Executed: 3c + Critical: 2c, 2 MOps + ExpectedLatency: 3c + - Latency limited. +** ScheduleDAGMILive::schedule picking next node +*** Final schedule for %bb.0 *** +SU(0): %13:gpr = COPY $x10 +SU(1): %1:gpr = COPY $x11 +SU(2): %2:gpr = COPY $x12 +SU(3): %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +SU(4): %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +SU(5): $x10 = COPY %13:gpr + +********** INTERVALS ********** +X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +X11 [0B,32r:0) 0@0B-phi +X12 [0B,48r:0) 0@0B-phi +%1 [32r,112r:0) 0@32r weight:0.000000e+00 +%2 [48r,112r:0) 0@48r weight:0.000000e+00 +%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r weight:0.000000e+00 +RegMasks: +********** MACHINEINSTRS ********** +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Machine Instruction Scheduler (machine-scheduler) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: BB0[entry] +loop-detection +compute-mass-in-function + - node: BB0[entry] + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - BB0[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - BB0[entry]: float = 1.0, int = 18014398509481984 + +# *** IR Dump Before Debug Variable Analysis (livedebugvars) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Debug Variable Analysis (livedebugvars) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Live Stack Slot Analysis (livestacks) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Live Stack Slot Analysis (livestacks) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Virtual Register Map (virtregmap) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Virtual Register Map (virtregmap) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Live Register Matrix (liveregmatrix) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Live Register Matrix (liveregmatrix) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Greedy Register Allocator (greedy) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** GREEDY REGISTER ALLOCATION ********** +********** Function: test_macs32_v2i16 +# *** IR Dump After Greedy Register Allocator (greedy) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Virtual Register Rewriter (virtregrewriter) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** REWRITE VIRTUAL REGISTERS ********** +********** Function: test_macs32_v2i16 +********** REGISTER MAP ********** + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 +> %13:gpr = COPY $x10 +> %1:gpr = COPY $x11 +> %2:gpr = COPY $x12 +> %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +> %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +> $x10 = COPY %13:gpr +> PseudoRET implicit $x10 +# *** IR Dump After Virtual Register Rewriter (virtregrewriter) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Virtual Register Map (virtregmap) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Virtual Register Map (virtregmap) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Live Register Matrix (liveregmatrix) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Live Register Matrix (liveregmatrix) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Greedy Register Allocator (greedy) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** GREEDY REGISTER ALLOCATION ********** +********** Function: test_macs32_v2i16 +********** Compute Spill Weights ********** +********** Function: test_macs32_v2i16 +********** INTERVALS ********** +X10 [0B,16r:0)[128r,144r:1) 0@0B-phi 1@128r +X11 [0B,32r:0) 0@0B-phi +X12 [0B,48r:0) 0@0B-phi +%1 [32r,112r:0) 0@32r weight:6.312500e-03 +%2 [48r,112r:0) 0@48r weight:6.530172e-03 +%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r weight:1.183594e-02 +RegMasks: +********** MACHINEINSTRS ********** +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Enqueuing %1 +AllocationOrder(GPR) = [ $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x5 $x6 $x7 $x28 $x29 $x30 $x31 $x8 $x9 $x18 $x19 $x20 $x21 $x22 $x23 $x24 $x25 $x26 $x27 $x1 ] +Enqueuing %2 +Enqueuing %13 + +selectOrSplit GPR:%13 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r weight:1.183594e-02 w=1.183594e-02 +hints: $x10 +assigning %13 to $x10: X10 [16r,80r:2)[80r,112r:0)[112r,128r:1) 0@80r 1@112r 2@16r + +selectOrSplit GPR:%1 [32r,112r:0) 0@32r weight:6.312500e-03 w=6.312500e-03 +hints: $x11 +assigning %1 to $x11: X11 [32r,112r:0) 0@32r + +selectOrSplit GPR:%2 [48r,112r:0) 0@48r weight:6.530172e-03 w=6.530172e-03 +hints: $x12 +assigning %2 to $x12: X12 [48r,112r:0) 0@48r +# *** IR Dump After Greedy Register Allocator (greedy) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Virtual Register Rewriter (virtregrewriter) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ %13:gpr(tied-def 0), %1:gpr, %2:gpr +128B $x10 = COPY %13:gpr +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** REWRITE VIRTUAL REGISTERS ********** +********** Function: test_macs32_v2i16 +********** REGISTER MAP ********** +[%1 -> $x11] GPR +[%2 -> $x12] GPR +[%13 -> $x10] GPR + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +16B %13:gpr = COPY $x10 +32B %1:gpr = COPY $x11 +48B %2:gpr = COPY $x12 +80B %13:gpr = cv_machhNs_ killed %13:gpr(tied-def 0), %1:gpr, %2:gpr, 0 +112B %13:gpr = cv_macs_i16_ killed %13:gpr(tied-def 0), killed %1:gpr, killed %2:gpr +128B $x10 = COPY killed %13:gpr +144B PseudoRET implicit $x10 +> renamable $x10 = COPY $x10 +Identity copy: renamable $x10 = COPY $x10 + deleted. +> renamable $x11 = COPY $x11 +Identity copy: renamable $x11 = COPY $x11 + deleted. +> renamable $x12 = COPY $x12 +Identity copy: renamable $x12 = COPY $x12 + deleted. +> renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +> renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +> $x10 = COPY killed renamable $x10 +Identity copy: $x10 = COPY killed renamable $x10 + deleted. +> PseudoRET implicit $x10 +# *** IR Dump After Virtual Register Rewriter (virtregrewriter) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +80B renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +112B renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Register Allocation Pass Scoring (regallocscoringpass) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +80B renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +112B renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Register Allocation Pass Scoring (regallocscoringpass) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +80B renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +112B renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Stack Slot Coloring (stack-slot-coloring) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +80B renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +112B renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** Stack Slot Coloring ********** +********** Function: test_macs32_v2i16 +# *** IR Dump After Stack Slot Coloring (stack-slot-coloring) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +80B renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +112B renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Copy Propagation Pass (machine-cp) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +0B bb.0.entry: + liveins: $x10, $x11, $x12 +80B renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 +112B renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 +144B PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +MCP: BackwardCopyPropagateBlock entry +MCP: ForwardCopyPropagateBlock entry +# *** IR Dump After Machine Copy Propagation Pass (machine-cp) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Loop Invariant Code Motion (machinelicm) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +******** Post-regalloc Machine LICM: test_macs32_v2i16 ******** +# *** IR Dump After Machine Loop Invariant Code Motion (machinelicm) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Redundant Copy Elimination (riscv-copyelim) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Redundant Copy Elimination (riscv-copyelim) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Remove Redundant DEBUG_VALUE analysis (removeredundantdebugvalues) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Remove Redundant DEBUG_VALUE analysis (removeredundantdebugvalues) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Fixup Statepoint Caller Saved (fixup-statepoint-caller-saved) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Fixup Statepoint Caller Saved (fixup-statepoint-caller-saved) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before PostRA Machine Sink (postra-machine-sink) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After PostRA Machine Sink (postra-machine-sink) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: BB0[entry] +loop-detection +compute-mass-in-function + - node: BB0[entry] + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - BB0[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - BB0[entry]: float = 1.0, int = 18014398509481984 + + Looking for trivial roots +Found a new trivial root: %bb.0 +Last visited node: %bb.0 + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %bb.0 +Found roots: %bb.0 +# *** IR Dump Before Shrink Wrapping analysis (shrink-wrap) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +**** Analysing test_macs32_v2i16 +Look into: %bb.0 +Nothing to shrink-wrap +# *** IR Dump After Shrink Wrapping analysis (shrink-wrap) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Late Instructions Cleanup Pass (machine-latecleanup) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Machine Late Instructions Cleanup Pass (machine-latecleanup) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Control Flow Optimizer (branch-folder) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Control Flow Optimizer (branch-folder) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Tail Duplication (tailduplication) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Tail Duplication (tailduplication) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Copy Propagation Pass (machine-cp) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +MCP: BackwardCopyPropagateBlock entry +MCP: ForwardCopyPropagateBlock entry +# *** IR Dump After Machine Copy Propagation Pass (machine-cp) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Post-RA pseudo instruction expansion pass (postrapseudos) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Machine Function +********** EXPANDING POST-RA PSEUDO INSTRS ********** +********** Function: test_macs32_v2i16 +# *** IR Dump After Post-RA pseudo instruction expansion pass (postrapseudos) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V post-regalloc pseudo instruction expansion pass (riscv-expand-pseudolisimm32) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V post-regalloc pseudo instruction expansion pass (riscv-expand-pseudolisimm32) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Insert KCFI indirect call checks (kcfi) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Insert KCFI indirect call checks (kcfi) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before PostRA Machine Instruction Scheduler (postmisched) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +Subtarget disables post-MI-sched. +# *** IR Dump After PostRA Machine Instruction Scheduler (postmisched) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Analyze Machine Code For Garbage Collection (gc-analysis) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Analyze Machine Code For Garbage Collection (gc-analysis) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + +block-frequency: test_macs32_v2i16 +================================== +reverse-post-order-traversal + - 0: BB0[entry] +loop-detection +compute-mass-in-function + - node: BB0[entry] + => mass: ffffffffffffffff +float-to-int: min = 1.0, max = 1.0, factor = 18014398509481984.0 + - BB0[entry]: float = 1.0, scaled = 18014398509481984.0, int = 18014398509481984 +block-frequency-info: test_macs32_v2i16 + - BB0[entry]: float = 1.0, int = 18014398509481984 + + Looking for trivial roots +Found a new trivial root: %bb.0 +Last visited node: %bb.0 + Looking for non-trivial roots +Total: 1, Num: 2 +Discovered CFG nodes: +0: nullptr +1: nullptr +2: %bb.0 +Found roots: %bb.0 +# *** IR Dump Before Branch Probability Basic Block Placement (block-placement) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Branch Probability Basic Block Placement (block-placement) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Insert fentry calls (fentry-insert) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Insert fentry calls (fentry-insert) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Insert XRay ops (xray-instrumentation) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Insert XRay ops (xray-instrumentation) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Implement the 'patchable-function' attribute (patchable-function) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Implement the 'patchable-function' attribute (patchable-function) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Branch relaxation pass (branch-relaxation) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +***** BranchRelaxation ***** + Basic blocks before relaxation +%bb.0 offset=00000000 size=0xc + Basic blocks after relaxation + +%bb.0 offset=00000000 size=0xc +# *** IR Dump After Branch relaxation pass (branch-relaxation) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Make Compressible (riscv-make-compressible) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Make Compressible (riscv-make-compressible) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Copy Propagation Pass (machine-cp) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +MCP: BackwardCopyPropagateBlock entry +MCP: ForwardCopyPropagateBlock entry +# *** IR Dump After Machine Copy Propagation Pass (machine-cp) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Contiguously Lay Out Funclets (funclet-layout) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Contiguously Lay Out Funclets (funclet-layout) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before StackMap Liveness Analysis (stackmap-liveness) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +********** COMPUTING STACKMAP LIVENESS: test_macs32_v2i16 ********** +# *** IR Dump After StackMap Liveness Analysis (stackmap-liveness) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Live DEBUG_VALUE analysis (livedebugvalues) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + + +Debug Range Extension: test_macs32_v2i16 +# *** IR Dump After Live DEBUG_VALUE analysis (livedebugvalues) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Machine Sanitizer Binary Metadata (machine-sanmd) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Machine Sanitizer Binary Metadata (machine-sanmd) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +*** IR Dump Before Machine Outliner (machine-outliner) *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +Machine Outliner: Running on target-default functions +*** Populating mapper *** +MAPPING FUNCTION: test_macs32_v2i16 +SKIP: Target does not want to outline from function by default +*** Discarding overlapping candidates *** +Searching for overlaps in all repeated sequences... +*** Outlining *** +NUMBER OF POTENTIAL FUNCTIONS: 0 +WALKING FUNCTION LIST +OutlinedSomething = 0 +Stopped outlining at iteration 0 because no changes were found. +*** IR Dump After Machine Outliner (machine-outliner) *** +; ModuleID = 'cecil_test.c' +source_filename = "cecil_test.c" +target datalayout = "e-m:e-p:32:32-i64:64-n32-S128" +target triple = "riscv32-unknown-unknown" + +; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) +define dso_local i32 @test_macs32_v2i16(i32 noundef %acc, i32 noundef %x, i32 noundef %y) local_unnamed_addr #0 { +entry: + %sext = shl i32 %x, 16 + %conv1 = ashr exact i32 %sext, 16 + %sext18 = shl i32 %y, 16 + %conv4 = ashr exact i32 %sext18, 16 + %mul = mul nsw i32 %conv4, %conv1 + %conv7 = ashr i32 %x, 16 + %conv11 = ashr i32 %y, 16 + %mul12 = mul nsw i32 %conv11, %conv7 + %add = add i32 %mul12, %acc + %add13 = add i32 %add, %mul + ret i32 %add13 +} + +attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+m,+relax,+xseal5testalucvabs16,+xseal5testalucvabs32,+xseal5testalucvabs8,+xseal5testalucvaddnrsi16,+xseal5testalucvaddnrsi32,+xseal5testalucvaddnrui16,+xseal5testalucvaddnrui32,+xseal5testalucvaddns,+xseal5testalucvaddnu,+xseal5testalucvaddrnrsi16,+xseal5testalucvaddrnrsi32,+xseal5testalucvaddrnrui16,+xseal5testalucvaddrnrui32,+xseal5testalucvaddrns,+xseal5testalucvaddrnu,+xseal5testalucvextbs,+xseal5testalucvextbz,+xseal5testalucvexths,+xseal5testalucvexthz,+xseal5testalucvmaxi1216,+xseal5testalucvmaxi1232,+xseal5testalucvmaxi516,+xseal5testalucvmaxi532,+xseal5testalucvmaxs16,+xseal5testalucvmaxs32,+xseal5testalucvmaxs8,+xseal5testalucvmaxu16,+xseal5testalucvmaxu32,+xseal5testalucvmaxu8,+xseal5testalucvmini1216,+xseal5testalucvmini1232,+xseal5testalucvmini516,+xseal5testalucvmini532,+xseal5testalucvmins16,+xseal5testalucvmins32,+xseal5testalucvmins8,+xseal5testalucvminu16,+xseal5testalucvminu32,+xseal5testalucvminu8,+xseal5testalucvsletsi16,+xseal5testalucvsletsi32,+xseal5testalucvsletui16,+xseal5testalucvsletui32,+xseal5testalucvsubnrsi16,+xseal5testalucvsubnrsi32,+xseal5testalucvsubnrui16,+xseal5testalucvsubnrui32,+xseal5testalucvsubns,+xseal5testalucvsubnu,+xseal5testalucvsubrnrsi16,+xseal5testalucvsubrnrsi32,+xseal5testalucvsubrnrui16,+xseal5testalucvsubrnrui32,+xseal5testalucvsubrns,+xseal5testalucvsubrnu,+xseal5testmaccvmachhns,+xseal5testmaccvmachhnu,+xseal5testmaccvmachhrns,+xseal5testmaccvmachhrnu,+xseal5testmaccvmacns,+xseal5testmaccvmacnu,+xseal5testmaccvmacrns,+xseal5testmaccvmacrnu,+xseal5testmaccvmacsi16,+xseal5testmaccvmacsi32,+xseal5testmaccvmacui16,+xseal5testmaccvmacui32,+xseal5testmaccvmsusi16,+xseal5testmaccvmsusi32,+xseal5testmaccvmsuui16,+xseal5testmaccvmsuui32,+xseal5testmaccvmulhhns,+xseal5testmaccvmulhhnu,+xseal5testmaccvmulhhrns,+xseal5testmaccvmulhhrnu,+xseal5testmaccvmulns,+xseal5testmaccvmulnu,+xseal5testmaccvmulrns,+xseal5testmaccvmulrnu,-a,-c,-d,-e,-experimental-zacas,-experimental-zcmop,-experimental-zfbfmin,-experimental-zicfilp,-experimental-zicfiss,-experimental-zimop,-experimental-ztso,-experimental-zvfbfmin,-experimental-zvfbfwma,-f,-h,-smaia,-smepmp,-ssaia,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-za128rs,-za64rs,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmp,-zcmt,-zdinx,-zfa,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } + +!llvm.module.flags = !{!0, !1, !2} +!llvm.ident = !{!3} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"target-abi", !"ilp32"} +!2 = !{i32 8, !"SmallDataLimit", i32 8} +!3 = !{!"clang version 18.1.0rc (https://github.com/llvm/llvm-project.git 1acc4e456481e76822c76c850bad3994d4e04b59)"} +# *** IR Dump Before Stack Frame Layout Analysis (stack-frame-layout) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Stack Frame Layout Analysis (stack-frame-layout) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Zcmp move merging pass (riscv-move-merge) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Zcmp move merging pass (riscv-move-merge) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V Zcmp Push/Pop optimization pass (riscv-push-pop-opt) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V Zcmp Push/Pop optimization pass (riscv-push-pop-opt) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V pseudo instruction expansion pass (riscv-expand-pseudo) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V pseudo instruction expansion pass (riscv-expand-pseudo) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before RISC-V atomic pseudo instruction expansion pass (riscv-expand-atomic-pseudo) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After RISC-V atomic pseudo instruction expansion pass (riscv-expand-atomic-pseudo) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump Before Unpack machine instruction bundles (unpack-mi-bundles) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + +# *** IR Dump After Unpack machine instruction bundles (unpack-mi-bundles) ***: +# Machine code for function test_macs32_v2i16: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten, TracksDebugUserValues +Function Live Ins: $x10, $x11, $x12 + +bb.0.entry: + liveins: $x10, $x11, $x12 + renamable $x10 = cv_machhNs_ killed renamable $x10(tied-def 0), renamable $x11, renamable $x12, 0 + renamable $x10 = cv_macs_i16_ killed renamable $x10(tied-def 0), killed renamable $x11, killed renamable $x12 + PseudoRET implicit $x10 + +# End machine code for function test_macs32_v2i16. + From 82ce3b04e619489246c3c2940e40a21ddb7a02eb Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 25 Mar 2024 16:38:59 +0100 Subject: [PATCH 58/80] gen example updates --- examples/cfg/gen/all.yml | 516 ++++++++++++++++++++++++++----------- examples/cfg/gen/riscv.yml | 268 ++++++++++++++++--- 2 files changed, 603 insertions(+), 181 deletions(-) diff --git a/examples/cfg/gen/all.yml b/examples/cfg/gen/all.yml index 2e555aed..e9214634 100644 --- a/examples/cfg/gen/all.yml +++ b/examples/cfg/gen/all.yml @@ -1,265 +1,483 @@ +--- extensions: - Seal5Test_alu_cv_abs: - arch: xseal5testalucvabs + Seal5Test_alu_cv_abs16: + arch: xseal5testalucvabs16 experimental: false - feature: seal5testalucvabs - vendor: false + feature: Seal5Testalucvabs16 + vendor: true version: '1.0' - Seal5Test_alu_cv_addNrs: - arch: xseal5testalucvaddnrs + Seal5Test_alu_cv_abs32: + arch: xseal5testalucvabs32 experimental: false - feature: seal5testalucvaddnrs - vendor: false + feature: Seal5Testalucvabs32 + vendor: true version: '1.0' - Seal5Test_alu_cv_addNru: - arch: xseal5testalucvaddnru + Seal5Test_alu_cv_abs8: + arch: xseal5testalucvabs8 experimental: false - feature: seal5testalucvaddnru - vendor: false + feature: Seal5Testalucvabs8 + vendor: true + version: '1.0' + Seal5Test_alu_cv_addNrs_i16: + arch: xseal5testalucvaddnrsi16 + experimental: false + feature: Seal5TestalucvaddNrsi16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_addNrs_i32: + arch: xseal5testalucvaddnrsi32 + experimental: false + feature: Seal5TestalucvaddNrsi32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_addNru_i16: + arch: xseal5testalucvaddnrui16 + experimental: false + feature: Seal5TestalucvaddNrui16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_addNru_i32: + arch: xseal5testalucvaddnrui32 + experimental: false + feature: Seal5TestalucvaddNrui32 + vendor: true version: '1.0' Seal5Test_alu_cv_addNs: arch: xseal5testalucvaddns experimental: false - feature: seal5testalucvaddns - vendor: false + feature: Seal5TestalucvaddNs + vendor: true version: '1.0' Seal5Test_alu_cv_addNu: arch: xseal5testalucvaddnu experimental: false - feature: seal5testalucvaddnu - vendor: false + feature: Seal5TestalucvaddNu + vendor: true version: '1.0' - Seal5Test_alu_cv_addRNrs: - arch: xseal5testalucvaddrnrs + Seal5Test_alu_cv_addRNrs_i16: + arch: xseal5testalucvaddrnrsi16 experimental: false - feature: seal5testalucvaddrnrs - vendor: false + feature: Seal5TestalucvaddRNrsi16 + vendor: true version: '1.0' - Seal5Test_alu_cv_addRNru: - arch: xseal5testalucvaddrnru + Seal5Test_alu_cv_addRNrs_i32: + arch: xseal5testalucvaddrnrsi32 experimental: false - feature: seal5testalucvaddrnru - vendor: false + feature: Seal5TestalucvaddRNrsi32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_addRNru_i16: + arch: xseal5testalucvaddrnrui16 + experimental: false + feature: Seal5TestalucvaddRNrui16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_addRNru_i32: + arch: xseal5testalucvaddrnrui32 + experimental: false + feature: Seal5TestalucvaddRNrui32 + vendor: true version: '1.0' Seal5Test_alu_cv_addRNs: arch: xseal5testalucvaddrns experimental: false - feature: seal5testalucvaddrns - vendor: false + feature: Seal5TestalucvaddRNs + vendor: true version: '1.0' Seal5Test_alu_cv_addRNu: arch: xseal5testalucvaddrnu experimental: false - feature: seal5testalucvaddrnu - vendor: false + feature: Seal5TestalucvaddRNu + vendor: true version: '1.0' - Seal5Test_alu_cv_maxs: - arch: xseal5testalucvmaxs + Seal5Test_alu_cv_extbs: + arch: xseal5testalucvextbs experimental: false - feature: seal5testalucvmaxs - vendor: false + feature: Seal5Testalucvextbs + vendor: true version: '1.0' - Seal5Test_alu_cv_maxu: - arch: xseal5testalucvmaxu + Seal5Test_alu_cv_extbz: + arch: xseal5testalucvextbz experimental: false - feature: seal5testalucvmaxu - vendor: false + feature: Seal5Testalucvextbz + vendor: true version: '1.0' - Seal5Test_alu_cv_mins: - arch: xseal5testalucvmins + Seal5Test_alu_cv_exths: + arch: xseal5testalucvexths experimental: false - feature: seal5testalucvmins - vendor: false + feature: Seal5Testalucvexths + vendor: true version: '1.0' - Seal5Test_alu_cv_minu: - arch: xseal5testalucvminu + Seal5Test_alu_cv_exthz: + arch: xseal5testalucvexthz experimental: false - feature: seal5testalucvminu - vendor: false + feature: Seal5Testalucvexthz + vendor: true version: '1.0' - Seal5Test_alu_cv_slets: - arch: xseal5testalucvslets + Seal5Test_alu_cv_max_s_16: + arch: xseal5testalucvmaxs16 experimental: false - feature: seal5testalucvslets - vendor: false + feature: Seal5Testalucvmaxs16 + vendor: true version: '1.0' - Seal5Test_alu_cv_sletu: - arch: xseal5testalucvsletu + Seal5Test_alu_cv_max_s_32: + arch: xseal5testalucvmaxs32 experimental: false - feature: seal5testalucvsletu - vendor: false + feature: Seal5Testalucvmaxs32 + vendor: true version: '1.0' - Seal5Test_alu_cv_subNrs: - arch: xseal5testalucvsubnrs + Seal5Test_alu_cv_max_s_8: + arch: xseal5testalucvmaxs8 experimental: false - feature: seal5testalucvsubnrs - vendor: false + feature: Seal5Testalucvmaxs8 + vendor: true version: '1.0' - Seal5Test_alu_cv_subNru: - arch: xseal5testalucvsubnru + Seal5Test_alu_cv_max_u_16: + arch: xseal5testalucvmaxu16 experimental: false - feature: seal5testalucvsubnru - vendor: false + feature: Seal5Testalucvmaxu16 + vendor: true version: '1.0' - Seal5Test_alu_cv_subNs: - arch: xseal5testalucvsubns + Seal5Test_alu_cv_max_u_32: + arch: xseal5testalucvmaxu32 experimental: false - feature: seal5testalucvsubns - vendor: false + feature: Seal5Testalucvmaxu32 + vendor: true version: '1.0' - Seal5Test_alu_cv_subNu: - arch: xseal5testalucvsubnu + Seal5Test_alu_cv_max_u_8: + arch: xseal5testalucvmaxu8 experimental: false - feature: seal5testalucvsubnu - vendor: false + feature: Seal5Testalucvmaxu8 + vendor: true version: '1.0' - Seal5Test_alu_cv_subRNrs: - arch: xseal5testalucvsubrnrs + Seal5Test_alu_cv_maxi12_16: + arch: xseal5testalucvmaxi1216 experimental: false - feature: seal5testalucvsubrnrs - vendor: false + feature: Seal5Testalucvmaxi1216 + vendor: true version: '1.0' - Seal5Test_alu_cv_subRNru: - arch: xseal5testalucvsubrnru + Seal5Test_alu_cv_maxi12_32: + arch: xseal5testalucvmaxi1232 experimental: false - feature: seal5testalucvsubrnru - vendor: false + feature: Seal5Testalucvmaxi1232 + vendor: true version: '1.0' - Seal5Test_alu_cv_subRNs: - arch: xseal5testalucvsubrns + Seal5Test_alu_cv_maxi5_16: + arch: xseal5testalucvmaxi516 experimental: false - feature: seal5testalucvsubrns - vendor: false + feature: Seal5Testalucvmaxi516 + vendor: true version: '1.0' - Seal5Test_alu_cv_subRNu: - arch: xseal5testalucvsubrnu + Seal5Test_alu_cv_maxi5_32: + arch: xseal5testalucvmaxi532 experimental: false - feature: seal5testalucvsubrnu - vendor: false + feature: Seal5Testalucvmaxi532 + vendor: true version: '1.0' - Seal5Test_mac_cv_machhNs: - arch: xseal5testmaccvmachhns + Seal5Test_alu_cv_min_s_16: + arch: xseal5testalucvmins16 experimental: false - feature: seal5testmaccvmachhns - vendor: false + feature: Seal5Testalucvmins16 + vendor: true version: '1.0' - Seal5Test_mac_cv_machhNu: - arch: xseal5testmaccvmachhnu + Seal5Test_alu_cv_min_s_32: + arch: xseal5testalucvmins32 experimental: false - feature: seal5testmaccvmachhnu - vendor: false + feature: Seal5Testalucvmins32 + vendor: true version: '1.0' - Seal5Test_mac_cv_machhRNs: - arch: xseal5testmaccvmachhrns + Seal5Test_alu_cv_min_s_8: + arch: xseal5testalucvmins8 experimental: false - feature: seal5testmaccvmachhrns - vendor: false + feature: Seal5Testalucvmins8 + vendor: true version: '1.0' - Seal5Test_mac_cv_machhRNu: - arch: xseal5testmaccvmachhrnu + Seal5Test_alu_cv_min_u_16: + arch: xseal5testalucvminu16 + experimental: false + feature: Seal5Testalucvminu16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_min_u_32: + arch: xseal5testalucvminu32 + experimental: false + feature: Seal5Testalucvminu32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_min_u_8: + arch: xseal5testalucvminu8 + experimental: false + feature: Seal5Testalucvminu8 + vendor: true + version: '1.0' + Seal5Test_alu_cv_mini12_16: + arch: xseal5testalucvmini1216 + experimental: false + feature: Seal5Testalucvmini1216 + vendor: true + version: '1.0' + Seal5Test_alu_cv_mini12_32: + arch: xseal5testalucvmini1232 + experimental: false + feature: Seal5Testalucvmini1232 + vendor: true + version: '1.0' + Seal5Test_alu_cv_mini5_16: + arch: xseal5testalucvmini516 + experimental: false + feature: Seal5Testalucvmini516 + vendor: true + version: '1.0' + Seal5Test_alu_cv_mini5_32: + arch: xseal5testalucvmini532 + experimental: false + feature: Seal5Testalucvmini532 + vendor: true + version: '1.0' + Seal5Test_alu_cv_slets_i16: + arch: xseal5testalucvsletsi16 + experimental: false + feature: Seal5Testalucvsletsi16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_slets_i32: + arch: xseal5testalucvsletsi32 + experimental: false + feature: Seal5Testalucvsletsi32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_sletu_i16: + arch: xseal5testalucvsletui16 + experimental: false + feature: Seal5Testalucvsletui16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_sletu_i32: + arch: xseal5testalucvsletui32 + experimental: false + feature: Seal5Testalucvsletui32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subNrs_i16: + arch: xseal5testalucvsubnrsi16 + experimental: false + feature: Seal5TestalucvsubNrsi16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subNrs_i32: + arch: xseal5testalucvsubnrsi32 + experimental: false + feature: Seal5TestalucvsubNrsi32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subNru_i16: + arch: xseal5testalucvsubnrui16 + experimental: false + feature: Seal5TestalucvsubNrui16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subNru_i32: + arch: xseal5testalucvsubnrui32 + experimental: false + feature: Seal5TestalucvsubNrui32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subNs: + arch: xseal5testalucvsubns experimental: false - feature: seal5testmaccvmachhrnu - vendor: false + feature: Seal5TestalucvsubNs + vendor: true + version: '1.0' + Seal5Test_alu_cv_subNu: + arch: xseal5testalucvsubnu + experimental: false + feature: Seal5TestalucvsubNu + vendor: true + version: '1.0' + Seal5Test_alu_cv_subRNrs_i16: + arch: xseal5testalucvsubrnrsi16 + experimental: false + feature: Seal5TestalucvsubRNrsi16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subRNrs_i32: + arch: xseal5testalucvsubrnrsi32 + experimental: false + feature: Seal5TestalucvsubRNrsi32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subRNru_i16: + arch: xseal5testalucvsubrnrui16 + experimental: false + feature: Seal5TestalucvsubRNrui16 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subRNru_i32: + arch: xseal5testalucvsubrnrui32 + experimental: false + feature: Seal5TestalucvsubRNrui32 + vendor: true + version: '1.0' + Seal5Test_alu_cv_subRNs: + arch: xseal5testalucvsubrns + experimental: false + feature: Seal5TestalucvsubRNs + vendor: true + version: '1.0' + Seal5Test_alu_cv_subRNu: + arch: xseal5testalucvsubrnu + experimental: false + feature: Seal5TestalucvsubRNu + vendor: true version: '1.0' Seal5Test_mac_cv_macNs: arch: xseal5testmaccvmacns experimental: false - feature: seal5testmaccvmacns - vendor: false + feature: Seal5TestmaccvmacNs + vendor: true version: '1.0' Seal5Test_mac_cv_macNu: arch: xseal5testmaccvmacnu experimental: false - feature: seal5testmaccvmacnu - vendor: false + feature: Seal5TestmaccvmacNu + vendor: true version: '1.0' Seal5Test_mac_cv_macRNs: arch: xseal5testmaccvmacrns experimental: false - feature: seal5testmaccvmacrns - vendor: false + feature: Seal5TestmaccvmacRNs + vendor: true version: '1.0' Seal5Test_mac_cv_macRNu: arch: xseal5testmaccvmacrnu experimental: false - feature: seal5testmaccvmacrnu - vendor: false + feature: Seal5TestmaccvmacRNu + vendor: true version: '1.0' - Seal5Test_mac_cv_macs: - arch: xseal5testmaccvmacs + Seal5Test_mac_cv_machhNs: + arch: xseal5testmaccvmachhns experimental: false - feature: seal5testmaccvmacs - vendor: false + feature: Seal5TestmaccvmachhNs + vendor: true version: '1.0' - Seal5Test_mac_cv_macu: - arch: xseal5testmaccvmacu + Seal5Test_mac_cv_machhNu: + arch: xseal5testmaccvmachhnu experimental: false - feature: seal5testmaccvmacu - vendor: false + feature: Seal5TestmaccvmachhNu + vendor: true version: '1.0' - Seal5Test_mac_cv_msus: - arch: xseal5testmaccvmsus + Seal5Test_mac_cv_machhRNs: + arch: xseal5testmaccvmachhrns experimental: false - feature: seal5testmaccvmsus - vendor: false + feature: Seal5TestmaccvmachhRNs + vendor: true version: '1.0' - Seal5Test_mac_cv_msuu: - arch: xseal5testmaccvmsuu + Seal5Test_mac_cv_machhRNu: + arch: xseal5testmaccvmachhrnu experimental: false - feature: seal5testmaccvmsuu - vendor: false + feature: Seal5TestmaccvmachhRNu + vendor: true version: '1.0' - Seal5Test_mac_cv_mulhhNs: - arch: xseal5testmaccvmulhhns + Seal5Test_mac_cv_macs_i16: + arch: xseal5testmaccvmacsi16 experimental: false - feature: seal5testmaccvmulhhns - vendor: false + feature: Seal5Testmaccvmacsi16 + vendor: true version: '1.0' - Seal5Test_mac_cv_mulhhNu: - arch: xseal5testmaccvmulhhnu + Seal5Test_mac_cv_macs_i32: + arch: xseal5testmaccvmacsi32 experimental: false - feature: seal5testmaccvmulhhnu - vendor: false + feature: Seal5Testmaccvmacsi32 + vendor: true version: '1.0' - Seal5Test_mac_cv_mulhhRNs: - arch: xseal5testmaccvmulhhrns + Seal5Test_mac_cv_macu_i16: + arch: xseal5testmaccvmacui16 experimental: false - feature: seal5testmaccvmulhhrns - vendor: false + feature: Seal5Testmaccvmacui16 + vendor: true version: '1.0' - Seal5Test_mac_cv_mulhhRNu: - arch: xseal5testmaccvmulhhrnu + Seal5Test_mac_cv_macu_i32: + arch: xseal5testmaccvmacui32 + experimental: false + feature: Seal5Testmaccvmacui32 + vendor: true + version: '1.0' + Seal5Test_mac_cv_msus_i16: + arch: xseal5testmaccvmsusi16 experimental: false - feature: seal5testmaccvmulhhrnu - vendor: false + feature: Seal5Testmaccvmsusi16 + vendor: true + version: '1.0' + Seal5Test_mac_cv_msus_i32: + arch: xseal5testmaccvmsusi32 + experimental: false + feature: Seal5Testmaccvmsusi32 + vendor: true + version: '1.0' + Seal5Test_mac_cv_msuu_i16: + arch: xseal5testmaccvmsuui16 + experimental: false + feature: Seal5Testmaccvmsuui16 + vendor: true + version: '1.0' + Seal5Test_mac_cv_msuu_i32: + arch: xseal5testmaccvmsuui32 + experimental: false + feature: Seal5Testmaccvmsuui32 + vendor: true version: '1.0' Seal5Test_mac_cv_mulNs: arch: xseal5testmaccvmulns experimental: false - feature: seal5testmaccvmulns - vendor: false + feature: Seal5TestmaccvmulNs + vendor: true version: '1.0' Seal5Test_mac_cv_mulNu: arch: xseal5testmaccvmulnu experimental: false - feature: seal5testmaccvmulnu - vendor: false + feature: Seal5TestmaccvmulNu + vendor: true version: '1.0' Seal5Test_mac_cv_mulRNs: arch: xseal5testmaccvmulrns experimental: false - feature: seal5testmaccvmulrns - vendor: false + feature: Seal5TestmaccvmulRNs + vendor: true version: '1.0' Seal5Test_mac_cv_mulRNu: arch: xseal5testmaccvmulrnu experimental: false - feature: seal5testmaccvmulrnu - vendor: false + feature: Seal5TestmaccvmulRNu + vendor: true + version: '1.0' + Seal5Test_mac_cv_mulhhNs: + arch: xseal5testmaccvmulhhns + experimental: false + feature: Seal5TestmaccvmulhhNs + vendor: true + version: '1.0' + Seal5Test_mac_cv_mulhhNu: + arch: xseal5testmaccvmulhhnu + experimental: false + feature: Seal5TestmaccvmulhhNu + vendor: true + version: '1.0' + Seal5Test_mac_cv_mulhhRNs: + arch: xseal5testmaccvmulhhrns + experimental: false + feature: Seal5TestmaccvmulhhRNs + vendor: true + version: '1.0' + Seal5Test_mac_cv_mulhhRNu: + arch: xseal5testmaccvmulhhrnu + experimental: false + feature: Seal5TestmaccvmulhhRNu + vendor: true version: '1.0' passes: per_model: - all_v2: + all_v7: overrides: convert_models: prefix: "GEN_" + extensions: diff --git a/examples/cfg/gen/riscv.yml b/examples/cfg/gen/riscv.yml index d1350f27..75f5aa42 100644 --- a/examples/cfg/gen/riscv.yml +++ b/examples/cfg/gen/riscv.yml @@ -4,38 +4,242 @@ riscv: features: - m - fast-unaligned-access - # - gpr32v + - gpr32v riscv: legalization: gisel: - ops: - - name: - - G_ABS - onlyif: - - HasExtseal5testalucvabs - types: - - s32 - - name: - - G_UMIN - onlyif: - - HasExtseal5testalucvminu - types: - - s32 - - name: - - G_SMIN - onlyif: - - HasExtseal5testalucvmins - types: - - s32 - - name: - - G_UMAX - onlyif: - - HasExtseal5testalucvmaxu - types: - - s32 - - name: - - G_SMAX - onlyif: - - HasExtseal5testalucvmaxs - types: - - s32 + ops: [] + # - name: + # - G_ABS + # onlyif: + # - HasVendorseal5testalucvabs8 + # types: + # - s8 + # - name: + # - G_ABS + # onlyif: + # - HasVendorseal5testalucvabs16 + # types: + # - s16 + # - name: + # - G_ABS + # onlyif: + # - HasVendorseal5testalucvabs32 + # types: + # - s32 + # - name: + # - G_SEXT + # onlyif: + # - HasVendorseal5testalucvexths + # types: + # - s16 + # - name: + # - G_ZEXT + # onlyif: + # - HasVendorseal5testalucvexthz + # types: + # - s16 + # - name: + # - G_SEXT + # onlyif: + # - HasVendorseal5testalucvextbs + # types: + # - s8 + # - name: + # - G_ZEXT + # onlyif: + # - HasVendorseal5testalucvextbz + # types: + # - s8 + # - name: + # - G_UMIN + # onlyif: + # - HasVendorseal5testalucvminu8 + # types: + # - s8 + # - name: + # - G_SMIN + # onlyif: + # - HasVendorseal5testalucvmins8 + # types: + # - s8 + # - name: + # - G_UMIN + # onlyif: + # - HasVendorseal5testalucvminu16 + # types: + # - s16 + # - name: + # - G_SMIN + # onlyif: + # - HasVendorseal5testalucvmins16 + # types: + # - s16 + # - name: + # - G_UMIN + # onlyif: + # - HasVendorseal5testalucvminu32 + # types: + # - s32 + # - name: + # - G_SMIN + # onlyif: + # - HasVendorseal5testalucvmins32 + # types: + # - s32 + # - name: + # - G_UMAX + # onlyif: + # - HasVendorseal5testalucvmaxu8 + # types: + # - s8 + # - name: + # - G_SMAX + # onlyif: + # - HasVendorseal5testalucvmaxs8 + # types: + # - s8 + # - name: + # - G_UMAX + # onlyif: + # - HasVendorseal5testalucvmaxu16 + # types: + # - s16 + # - name: + # - G_SMAX + # onlyif: + # - HasVendorseal5testalucvmaxs16 + # types: + # - s16 + # - name: + # - G_UMAX + # onlyif: + # - HasVendorseal5testalucvmaxu32 + # types: + # - s32 + # - name: + # - G_SMAX + # onlyif: + # - HasVendorseal5testalucvmaxs32 + # types: + # - s32 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmacui16 + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmacsi16 + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmsuui16 + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmsusi16 + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulhhnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulhhns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulrnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulrns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulhhrnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmulhhrns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmacnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmacns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmachhnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmachhns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmacrnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmacrns + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmachhrnu + # types: + # - s16 + # - name: + # - G_MUL + # onlyif: + # - HasVendorseal5testmaccvmachhrns + # types: + # - s16 From 80cdd911b2ee1312eeb34f78e1cd6566267f0f12 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Mon, 25 Mar 2024 16:39:23 +0100 Subject: [PATCH 59/80] add manual uimm12_op.patch --- examples/cfg/patches.yml | 1 + seal5/resources/patches/llvm/uimm12_op.patch | 30 ++++++++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 seal5/resources/patches/llvm/uimm12_op.patch diff --git a/examples/cfg/patches.yml b/examples/cfg/patches.yml index 4961ea48..45e8dad7 100644 --- a/examples/cfg/patches.yml +++ b/examples/cfg/patches.yml @@ -18,6 +18,7 @@ patches: # - name: insert_markers_llvm17 - name: insert_markers_llvm18 - name: legalizer_split + - name: uimm12_op # TODO: automatially select patch depending on llvm version # generated patch (TODO: implement) # - name: ??? diff --git a/seal5/resources/patches/llvm/uimm12_op.patch b/seal5/resources/patches/llvm/uimm12_op.patch new file mode 100644 index 00000000..a9b641f0 --- /dev/null +++ b/seal5/resources/patches/llvm/uimm12_op.patch @@ -0,0 +1,30 @@ +commit db5d38843f9466245955714f0dff02883670ddfe +Author: Philipp van Kempen +Date: Wed Mar 20 15:52:54 2024 +0100 + + uimm12 patch + +diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +index 4adb3bd0d1bf..4088c9ac5c92 100644 +--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp ++++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +@@ -697,6 +697,7 @@ public: + bool isUImm8() const { return IsUImm<8>(); } + bool isUImm20() const { return IsUImm<20>(); } + // RISCVAsmParser.cpp - riscv_operands - INSERTION_START ++ bool isUImm12() const { return IsUImm<12>(); } + // RISCVAsmParser.cpp - riscv_operands - INSERTION_END + + bool isUImm8GE32() const { +diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +index ea0d3a0f54ba..e2cf99b53ab5 100644 +--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td +@@ -310,6 +310,7 @@ def simm21_lsb0_jal : Operand { + } + + // RISCVInstrInfo.td - field_types - INSERTION_START ++def uimm12 : RISCVUImmLeafOp<12>; + // RISCVInstrInfo.td - field_types - INSERTION_END + + def BareSymbol : AsmOperandClass { From b5b9585ab03b5a0b58492cc771cf6b5fe7512682 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 26 Mar 2024 13:57:39 +0100 Subject: [PATCH 60/80] gen example updates --- examples/gen_demo.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/examples/gen_demo.py b/examples/gen_demo.py index 7acfafd1..6de1e0f2 100644 --- a/examples/gen_demo.py +++ b/examples/gen_demo.py @@ -61,7 +61,8 @@ # Load CoreDSL inputs cdsl_files = [ - EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v5.core_desc", + # EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v7.core_desc", + EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v9.core_desc", ] seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True) From 5c12094b30f37b3a8ccd1026f974fa4b87926170 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 26 Mar 2024 13:58:10 +0100 Subject: [PATCH 61/80] riscv_instr_info: fix handling of writeback constraints --- seal5/backends/riscv_instr_info/writer.py | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/seal5/backends/riscv_instr_info/writer.py b/seal5/backends/riscv_instr_info/writer.py index a065d10a..1be5806d 100644 --- a/seal5/backends/riscv_instr_info/writer.py +++ b/seal5/backends/riscv_instr_info/writer.py @@ -170,6 +170,7 @@ def gen_riscv_instr_info_str(instr): print("operands", operands) reads = [] writes = [] + constraints = [] for op_name, op in operands.items(): print("op", op) print("op.constraints", op.constraints) @@ -195,6 +196,9 @@ def gen_riscv_instr_info_str(instr): writes.append(op_str2) op_str = f"{pre}:${op_name}" reads.append(op_str) + constraint = f"${op_name} = ${op_name}_wb" + constraints.append(constraint) + elif Seal5OperandAttribute.OUT in op.attributes: op_str = f"{pre}:${op_name}" writes.append(op_str) @@ -203,6 +207,8 @@ def gen_riscv_instr_info_str(instr): reads.append(op_str) print("reads", reads) print("writes", writes) + print("constraints", constraints) + # constraints_str = ", ".join(constraints) attributes = instr.attributes print("attributes", attributes) real_name = instr.mnemonic @@ -251,9 +257,9 @@ def gen_riscv_instr_info_str(instr): attrs["isTerminator"] = 1 else: attrs["isTerminator"] = 0 - constraints = instr.constraints - if len(constraints) > 0: - raise NotImplementedError + # constraints = instr.constraints + # if len(constraints) > 0: + # raise NotImplementedError formats = True tablegen_str = write_riscv_instruction_info( name, From 5f1e82d923e9560ed7d1c73bad16f41cfd583c83 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 26 Mar 2024 13:58:45 +0100 Subject: [PATCH 62/80] seal5.transform.converter: fix --- seal5/transform/converter.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/transform/converter.py b/seal5/transform/converter.py index 372ff48c..1de605a7 100644 --- a/seal5/transform/converter.py +++ b/seal5/transform/converter.py @@ -69,7 +69,7 @@ def main(): if args.prefix: instr_def.name = f"{args.prefix.upper()}{instr_def.name}" prefix_ = args.prefix.lower().replace("_", ".") - instr_def.mnemonic = f"{prefix_}.{instr_def.mnemonic}" + instr_def.mnemonic = f"{prefix_}{instr_def.mnemonic}" set_def.instructions[enc] = seal5_model.Seal5Instruction( instr_def.name, instr_def.attributes, From 1b991c51a0a80b23410cd09d6de8ee9670a68015 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 26 Mar 2024 13:59:16 +0100 Subject: [PATCH 63/80] seal5.transform.filter_model: make assertions more helpful --- seal5/transform/filter_model/filter.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/seal5/transform/filter_model/filter.py b/seal5/transform/filter_model/filter.py index 5284c587..a447c2d7 100644 --- a/seal5/transform/filter_model/filter.py +++ b/seal5/transform/filter_model/filter.py @@ -201,7 +201,7 @@ def check_filter_regex(name, keep, drop): return not any(re.compile(expr).match(name) for expr in drop) return True - def check_encoding_filter(enc, keep, drop, keep2, drop2): + def check_encoding_filter(name, enc, keep, drop, keep2, drop2): opcode = None size = 0 for e in reversed(enc): @@ -217,7 +217,7 @@ def check_encoding_filter(enc, keep, drop, keep2, drop2): else: assert False size += length - assert size in [16, 32, 64, 128], f"Invalid size: {size}" + assert size in [16, 32, 64, 128], f"Invalid size: {size} (Instruction: {name})" if drop2 and keep2: ret = size not in drop2 and size in keep2 elif keep2: @@ -247,7 +247,7 @@ def check_encoding_filter(enc, keep, drop, keep2, drop2): for key, instr_def in set_def.instructions.items() if check_filter_regex(instr_def.name, keep_instructions, drop_instructions) and check_encoding_filter( - instr_def.encoding, keep_opcodes, drop_opcodes, keep_encoding_sizes, drop_encoding_sizes + instr_def.name, instr_def.encoding, keep_opcodes, drop_opcodes, keep_encoding_sizes, drop_encoding_sizes ) } # for instr_name, instr_def in set_def.instructions.items(): From 9ffb140f0a9776f56d4ee7ff099de370dead32bf Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 26 Mar 2024 13:59:27 +0100 Subject: [PATCH 64/80] update demo --- examples/demo.py | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/demo.py b/examples/demo.py index e0478ddd..d6214a7d 100644 --- a/examples/demo.py +++ b/examples/demo.py @@ -107,6 +107,7 @@ # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBranchImmediate.yml", # S4E # TUMEDA + EXAMPLES_DIR / "cfg" / "tumeda" / "OpenASIP.yml", # GENERATED # OTHERS EXAMPLES_DIR / "cfg" / "llvm.yml", From 09a2608bf5edb31adca33ddf01b91759144af3a6 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Tue, 26 Mar 2024 14:47:25 +0100 Subject: [PATCH 65/80] add custom patches --- .../patches/llvm/legalizer_fix_1.patch | 14 ++++ .../patches/llvm/legalizer_fix_2.patch | 15 +++++ .../patches/llvm/regclass_gpr32v.patch | 66 +++++++++++++++++++ .../resources/patches/llvm/simd_gpr32v.patch | 63 ++++++++++++++++++ 4 files changed, 158 insertions(+) create mode 100644 seal5/resources/patches/llvm/legalizer_fix_1.patch create mode 100644 seal5/resources/patches/llvm/legalizer_fix_2.patch create mode 100644 seal5/resources/patches/llvm/regclass_gpr32v.patch create mode 100644 seal5/resources/patches/llvm/simd_gpr32v.patch diff --git a/seal5/resources/patches/llvm/legalizer_fix_1.patch b/seal5/resources/patches/llvm/legalizer_fix_1.patch new file mode 100644 index 00000000..e68693ad --- /dev/null +++ b/seal5/resources/patches/llvm/legalizer_fix_1.patch @@ -0,0 +1,14 @@ +diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp ++++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +@@ -189,6 +189,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) + .legalFor({s32, sXLen, p0}) + .widenScalarToNextPow2(0) + .clampScalar(0, s32, sXLen); ++ getActionDefinitionsBuilder(G_CONSTANT_FOLD_BARRIER) ++ .legalFor({s8, s16, s32, s64, p0}) ++ .widenScalarToNextPow2(0, /*Min=*/8) ++ .clampScalar(0, s8, sXLen); + + getActionDefinitionsBuilder(G_ICMP) + .legalFor({{sXLen, sXLen}, {sXLen, p0}}) diff --git a/seal5/resources/patches/llvm/legalizer_fix_2.patch b/seal5/resources/patches/llvm/legalizer_fix_2.patch new file mode 100644 index 00000000..427ec715 --- /dev/null +++ b/seal5/resources/patches/llvm/legalizer_fix_2.patch @@ -0,0 +1,15 @@ +diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp ++++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +@@ -121,7 +121,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) + .maxScalar(0, sXLen) + .lower(); + } else { +- getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}).maxScalar(0, sXLen); ++ // getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}).maxScalar(0, sXLen); ++ getActionDefinitionsBuilder(G_ZEXT).maxScalar(0, sXLen); ++ getActionDefinitionsBuilder(G_SEXT).maxScalar(0, sXLen); ++ getActionDefinitionsBuilder(G_ANYEXT).maxScalar(0, sXLen).alwaysLegal(); + + getActionDefinitionsBuilder(G_SEXT_INREG).maxScalar(0, sXLen).lower(); + } diff --git a/seal5/resources/patches/llvm/regclass_gpr32v.patch b/seal5/resources/patches/llvm/regclass_gpr32v.patch new file mode 100644 index 00000000..3ae4036c --- /dev/null +++ b/seal5/resources/patches/llvm/regclass_gpr32v.patch @@ -0,0 +1,66 @@ +diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp ++++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +@@ -74,6 +74,19 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo, + return MCDisassembler::Success; + } + ++// LLVMGEN: need to this to compile new reg classes ++static DecodeStatus DecodeGPR32V2RegisterClass(MCInst &Inst, uint64_t RegNo, ++ uint64_t Address, ++ const MCDisassembler *Decoder) { ++ return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); ++} ++ ++static DecodeStatus DecodeGPR32V4RegisterClass(MCInst &Inst, uint64_t RegNo, ++ uint64_t Address, ++ const MCDisassembler *Decoder) { ++ return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); ++} ++ + static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { +diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp +--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp ++++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp +@@ -80,6 +80,8 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, + switch (RC.getID()) { + default: + llvm_unreachable("Register class not supported"); ++ case RISCV::GPR32V2RegClassID: ++ case RISCV::GPR32V4RegClassID: + case RISCV::GPRRegClassID: + case RISCV::GPRF16RegClassID: + case RISCV::GPRF32RegClassID: +diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td ++++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +@@ -606,6 +606,27 @@ def FFLAGS : RISCVReg<0, "fflags">; + def FRM : RISCVReg<0, "frm">; + + // RISCVRegisterInfo.td - riscv_register_info - INSERTION_START ++def GPR32V2 : RegisterClass<"RISCV", [v2i16], 32, (add ++ (sequence "X%u", 10, 17), ++ (sequence "X%u", 5, 7), ++ (sequence "X%u", 28, 31), ++ (sequence "X%u", 8, 9), ++ (sequence "X%u", 18, 27), ++ (sequence "X%u", 0, 4) ++ )> { ++ let RegInfos = XLenRI; ++} ++ ++def GPR32V4 : RegisterClass<"RISCV", [v4i8], 32, (add ++ (sequence "X%u", 10, 17), ++ (sequence "X%u", 5, 7), ++ (sequence "X%u", 28, 31), ++ (sequence "X%u", 8, 9), ++ (sequence "X%u", 18, 27), ++ (sequence "X%u", 0, 4) ++ )> { ++ let RegInfos = XLenRI; ++} + // RISCVRegisterInfo.td - riscv_register_info - INSERTION_END + + // Shadow Stack register diff --git a/seal5/resources/patches/llvm/simd_gpr32v.patch b/seal5/resources/patches/llvm/simd_gpr32v.patch new file mode 100644 index 00000000..44850806 --- /dev/null +++ b/seal5/resources/patches/llvm/simd_gpr32v.patch @@ -0,0 +1,63 @@ +diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td +--- a/llvm/lib/Target/RISCV/RISCVFeatures.td ++++ b/llvm/lib/Target/RISCV/RISCVFeatures.td +@@ -771,6 +771,12 @@ def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">, + AssemblerPredicate<(all_of FeatureStdExtSvinval), + "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">; + ++def FeatureGPR32V : SubtargetFeature<"gpr32v", "HasGPR32V", "true", "TODO">; ++def HasGPR32V ++ : Predicate<"Subtarget->hasGPR32V)">, ++ AssemblerPredicate<(any_of FeatureGPR32V), ++ "'GPR32V' (TODO)">; ++ + // RISCVFeatures.td - riscv_features - INSERTION_START + // RISCVFeatures.td - riscv_features - INSERTION_END + +diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp ++++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +@@ -274,8 +274,9 @@ RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { + case TargetTransformInfo::RGK_Scalar: + return TypeSize::getFixed(ST->getXLen()); + case TargetTransformInfo::RGK_FixedWidthVector: +- return TypeSize::getFixed( +- ST->useRVVForFixedLengthVectors() ? LMUL * ST->getRealMinVLen() : 0); ++ return TypeSize::getFixed(ST->useRVVForFixedLengthVectors() ++ ? LMUL * ST->getRealMinVLen() ++ : (ST->hasGPR32V() ? 32 : 0)); + case TargetTransformInfo::RGK_ScalableVector: + return TypeSize::getScalable( + (ST->hasVInstructions() && +@@ -315,6 +316,10 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, + + std::pair LT = getTypeLegalizationCost(Tp); + ++ if (ST->hasGPR32V()) { ++ return 1; // placeholder ++ } ++ + // First, handle cases where having a fixed length vector enables us to + // give a more accurate cost than falling back to generic scalable codegen. + // TODO: Each of these cases hints at a modeling gap around scalable vectors. +@@ -1036,7 +1041,7 @@ InstructionCost RISCVTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src, + const Instruction *I) { + EVT VT = TLI->getValueType(DL, Src, true); + // Type legalization can't handle structs +- if (VT == MVT::Other) ++ if (VT == MVT::Other || ST->hasGPR32V()) + return BaseT::getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, + CostKind, OpInfo, I); + +diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h ++++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +@@ -332,7 +332,7 @@ public: + + unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const { + if (Vector) +- return RISCVRegisterClass::VRRC; ++ return ST->hasGPR32V() ? RISCVRegisterClass::GPRRC : RISCVRegisterClass::VRRC; + if (!Ty) + return RISCVRegisterClass::GPRRC; + From 62d4a3240d9e8a8bc8674cc349b35200d616e8ff Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 18:17:07 +0100 Subject: [PATCH 66/80] coredsl2_seal5: add more helpful error message for missing imports --- seal5/frontends/coredsl2_seal5/load_order.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/frontends/coredsl2_seal5/load_order.py b/seal5/frontends/coredsl2_seal5/load_order.py index 534d7b3f..23d3d0be 100644 --- a/seal5/frontends/coredsl2_seal5/load_order.py +++ b/seal5/frontends/coredsl2_seal5/load_order.py @@ -33,7 +33,7 @@ def visitInstruction_set(self, ctx: CoreDSL2Parser.Instruction_setContext): self.instruction_sets[name] = ctx stack = [] for e in ctx.extension: - assert e.text in self.stacks + assert e.text in self.stacks, f"Set not found: {e.text}. Missing include?" for x in self.stacks[e.text]: if x not in stack: stack.append(x) From aec7b0dbe399d81751979b337fd29b439b2eed32 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 18:34:06 +0100 Subject: [PATCH 67/80] small fix for seal5.backends.coredsl2.writer when list of operands is empty --- seal5/backends/coredsl2/writer.py | 1 + 1 file changed, 1 insertion(+) diff --git a/seal5/backends/coredsl2/writer.py b/seal5/backends/coredsl2/writer.py index 85f6181e..577ae979 100644 --- a/seal5/backends/coredsl2/writer.py +++ b/seal5/backends/coredsl2/writer.py @@ -205,6 +205,7 @@ def write_operands(self, operands): self.write("operands: ") if len(operands) == 0: self.write_line("{};") + return self.enter_block() # print("operands", operands) for i, op in enumerate(operands.values()): From 1392465f9dcc9bd5546d1814b5a796599368dbb8 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 18:34:34 +0100 Subject: [PATCH 68/80] whitespace fixes in some backends --- seal5/backends/riscv_features/writer.py | 2 +- seal5/backends/riscv_isa_info/writer.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/seal5/backends/riscv_features/writer.py b/seal5/backends/riscv_features/writer.py index b87bc2f2..b6a2e152 100644 --- a/seal5/backends/riscv_features/writer.py +++ b/seal5/backends/riscv_features/writer.py @@ -43,7 +43,6 @@ def gen_riscv_features_str(name: str, ext_settings: ExtensionsSettings): content_template = Template(MAKO_TEMPLATE) content_text = content_template.render(predicate=predicate, feature=feature, arch=arch, description=description) - # content_text = content_text.rstrip("\n") return content_text + "\n" @@ -126,6 +125,7 @@ def main(): continue metrics["n_success"] += 1 content += gen_riscv_features_str(set_name, ext_settings) + content = content.rstrip() if len(content) > 0: with open(out_path, "w") as f: f.write(content) diff --git a/seal5/backends/riscv_isa_info/writer.py b/seal5/backends/riscv_isa_info/writer.py index 75c5001b..44ced0b1 100644 --- a/seal5/backends/riscv_isa_info/writer.py +++ b/seal5/backends/riscv_isa_info/writer.py @@ -136,7 +136,7 @@ def main(): key, new_content = gen_riscv_isa_info_str(set_name, ext_settings=ext_settings, llvm_version=llvm_version) contents.append((key, new_content)) contents = sorted(contents, key=lambda x: x[0]) - content = "\n".join([x[1] for x in contents]) + "\n" + content = "\n".join([x[1] for x in contents]) if len(content) > 0: with open(out_path, "w") as f: f.write(content) From f80d907d5d6e4c88180b64790070ff1725e3ee6d Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 18:34:44 +0100 Subject: [PATCH 69/80] fix for filter_model --- seal5/transform/filter_model/filter.py | 1 + 1 file changed, 1 insertion(+) diff --git a/seal5/transform/filter_model/filter.py b/seal5/transform/filter_model/filter.py index a447c2d7..01603d49 100644 --- a/seal5/transform/filter_model/filter.py +++ b/seal5/transform/filter_model/filter.py @@ -218,6 +218,7 @@ def check_encoding_filter(name, enc, keep, drop, keep2, drop2): assert False size += length assert size in [16, 32, 64, 128], f"Invalid size: {size} (Instruction: {name})" + ret = True if drop2 and keep2: ret = size not in drop2 and size in keep2 elif keep2: From 6d037bd6c48b441f564aaa9a97cd2ad4067b639e Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 18:39:03 +0100 Subject: [PATCH 70/80] examples/corev_demo.py: fixes --- examples/corev_demo.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/examples/corev_demo.py b/examples/corev_demo.py index d75127ec..c9f09b50 100644 --- a/examples/corev_demo.py +++ b/examples/corev_demo.py @@ -72,10 +72,7 @@ # Load test inputs test_files = [ - # EXAMPLES_DIR / "tests" / "xcorev" / "cv_abs.test.c", - # EXAMPLES_DIR / "tests" / "corev" / "*.asm.s", - # EXAMPLES_DIR / "tests" / "corev" / "*.invalid-asm.s", - EXAMPLES_DIR / "tests" / "corev" / "*.inline-asm.c", + EXAMPLES_DIR / "tests" / "xcorev" / "*.inline_asm.c", ] seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) From 890c03803b32120bfb3b8784dabc0e8ec8bbcdc1 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 18:39:54 +0100 Subject: [PATCH 71/80] examples/s4e_demo.py: fixes --- examples/s4e_demo.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/s4e_demo.py b/examples/s4e_demo.py index 41d8182a..66f3457c 100644 --- a/examples/s4e_demo.py +++ b/examples/s4e_demo.py @@ -73,7 +73,7 @@ # Load YAML inputs cfg_files = [ - EXAMPLES_DIR / "cfg" / "s4e" / "???.yml", + EXAMPLES_DIR / "cfg" / "s4e" / "s4e-mac.yml", EXAMPLES_DIR / "cfg" / "llvm.yml", EXAMPLES_DIR / "cfg" / "filter.yml", EXAMPLES_DIR / "cfg" / "patches.yml", From b4f9eabd933341cc696f44b623d3c4ca746ded2d Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Wed, 27 Mar 2024 20:30:34 +0100 Subject: [PATCH 72/80] small fix for seal5.backends.coredsl2.writer when list of operands is empty 2 --- seal5/backends/coredsl2/writer.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/seal5/backends/coredsl2/writer.py b/seal5/backends/coredsl2/writer.py index 577ae979..abd45673 100644 --- a/seal5/backends/coredsl2/writer.py +++ b/seal5/backends/coredsl2/writer.py @@ -204,7 +204,7 @@ def write_instruction_constraints(self, constraints, operands): def write_operands(self, operands): self.write("operands: ") if len(operands) == 0: - self.write_line("{};") + self.write_line("{}") return self.enter_block() # print("operands", operands) From 7c4e8c21846a4ab54ddff82c57ebe7c28c3bf41c Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 07:07:09 +0100 Subject: [PATCH 73/80] examples/s4e_demo.py: load test file --- examples/s4e_demo.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/s4e_demo.py b/examples/s4e_demo.py index 66f3457c..1ad4abaf 100644 --- a/examples/s4e_demo.py +++ b/examples/s4e_demo.py @@ -67,7 +67,7 @@ # Load test inputs test_files = [ - # TODO: add s4e test files + EXAMPLES_DIR / "cdsl" / "rv_s4e" / "s4e-mac.test.c", ] seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) From e8719e57a9a5bab8adefa5aff8f16dc2b5d99bed Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 07:07:40 +0100 Subject: [PATCH 74/80] add missing cdsl files for rv_gen --- examples/cdsl/rv_gen/all_v7.core_desc | 869 +++++++++++++++++++++++ examples/cdsl/rv_gen/all_v9.core_desc | 949 ++++++++++++++++++++++++++ 2 files changed, 1818 insertions(+) create mode 100644 examples/cdsl/rv_gen/all_v7.core_desc create mode 100644 examples/cdsl/rv_gen/all_v9.core_desc diff --git a/examples/cdsl/rv_gen/all_v7.core_desc b/examples/cdsl/rv_gen/all_v7.core_desc new file mode 100644 index 00000000..03a8ef85 --- /dev/null +++ b/examples/cdsl/rv_gen/all_v7.core_desc @@ -0,0 +1,869 @@ +import "../rv_base/RV32I.core_desc" + +InstructionSet Seal5Test_alu_cv_abs extends RV32I { + instructions { + cv_abs { + encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.abs", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) < 0 ? -X[rs1] : X[rs1]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini5_16 extends RV32I { + instructions { + cv_mini5_16 { + encoding: 7'b0000001 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) < (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini5_32 extends RV32I { + instructions { + cv_mini5_32 { + encoding: 7'b0000010 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) < (signed<5>)(imm5) ? (signed<32>)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini12_16 extends RV32I { + instructions { + cv_mini12_16 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) < (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini12_32 extends RV32I { + instructions { + cv_mini12_32 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) < (signed<12>)(imm5) ? (signed<32>)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi5_16 extends RV32I { + instructions { + cv_maxi5_16 { + encoding: 7'b0000011 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) > (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi5_32 extends RV32I { + instructions { + cv_maxi5_32 { + encoding: 7'b0000100 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) > (signed<5>)(imm5) ? (signed<32>)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi12_16 extends RV32I { + instructions { + cv_maxi12_16 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) > (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi12_32 extends RV32I { + instructions { + cv_maxi12_32 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) > (signed<12>)(imm5) ? (signed<32>)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_minu_i16 extends RV32I { + instructions { + cv_minu_i16 { + encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.minu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1]) < (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mins_i16 extends RV32I { + instructions { + cv_mins_i16 { + encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mins.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) < (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_minu_i32 extends RV32I { + instructions { + cv_minu_i32 { + encoding: 7'b0000111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.minu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] < X[rs2] ? X[rs1] : X[rs2]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mins_i32 extends RV32I { + instructions { + cv_mins_i32 { + encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mins.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) < (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxu_i16 extends RV32I { + instructions { + cv_maxu_i16 { + encoding: 7'b0001001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1]) > (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxs_i16 extends RV32I { + instructions { + cv_maxs_i16 { + encoding: 7'b0001010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) > (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxu_i32 extends RV32I { + instructions { + cv_maxu_i32 { + encoding: 7'b0001011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] > X[rs2] ? X[rs1] : X[rs2]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxs_i32 extends RV32I { + instructions { + cv_maxs_i32 { + encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) > (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_sletu_i16 extends RV32I { + instructions { + cv_sletu_i16 { + encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.sletu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1]) <= (unsigned<16>)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_slets_i16 extends RV32I { + instructions { + cv_slets_i16 { + encoding: 7'b0001110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.slets.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) <= (signed<16>)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_sletu_i32 extends RV32I { + instructions { + cv_sletu_i32 { + encoding: 7'b0001111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.sletu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] <= X[rs2] ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_slets_i32 extends RV32I { + instructions { + cv_slets_i32 { + encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.slets.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) <= (signed<32>)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNru_i16 extends RV32I { + instructions { + cv_addNru_i16 { + encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNrs_i16 extends RV32I { + instructions { + cv_addNrs_i16 { + encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNru_i32 extends RV32I { + instructions { + cv_addNru_i32 { + encoding: 7'b0010011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNrs_i32 extends RV32I { + instructions { + cv_addNrs_i32 { + encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNru_i16 extends RV32I { + instructions { + cv_subNru_i16 { + encoding: 7'b0010101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNrs_i16 extends RV32I { + instructions { + cv_subNrs_i16 { + encoding: 7'b0010110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNru_i32 extends RV32I { + instructions { + cv_subNru_i32 { + encoding: 7'b0010111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNrs_i32 extends RV32I { + instructions { + cv_subNrs_i32 { + encoding: 7'b0011000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNru_i16 extends RV32I { + instructions { + cv_addRNru_i16 { + encoding: 7'b0011001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNrs_i16 extends RV32I { + instructions { + cv_addRNrs_i16 { + encoding: 7'b0011010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNru_i32 extends RV32I { + instructions { + cv_addRNru_i32 { + encoding: 7'b0011011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNrs_i32 extends RV32I { + instructions { + cv_addRNrs_i32 { + encoding: 7'b0011100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNru_i16 extends RV32I { + instructions { + cv_subRNru_i16 { + encoding: 7'b0011101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNrs_i16 extends RV32I { + instructions { + cv_subRNrs_i16 { + encoding: 7'b0011110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNru_i32 extends RV32I { + instructions { + cv_subRNru_i32 { + encoding: 7'b0011111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNrs_i32 extends RV32I { + instructions { + cv_subRNrs_i32 { + encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNu extends RV32I { + instructions { + cv_addNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] + X[rs2] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNs extends RV32I { + instructions { + cv_addNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNu extends RV32I { + instructions { + cv_subNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] - X[rs2] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNs extends RV32I { + instructions { + cv_subNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNu extends RV32I { + instructions { + cv_addRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] + X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNs extends RV32I { + instructions { + cv_addRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNu extends RV32I { + instructions { + cv_subRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] - X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNs extends RV32I { + instructions { + cv_subRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macu_i16 extends RV32I { + instructions { + cv_macu_i16 { + encoding: 7'b0100001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macs_i16 extends RV32I { + instructions { + cv_macs_i16 { + encoding: 7'b0100010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macu_i32 extends RV32I { + instructions { + cv_macu_i32 { + encoding: 7'b0100011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macs_i32 extends RV32I { + instructions { + cv_macs_i32 { + encoding: 7'b0100100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<32>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msuu_i16 extends RV32I { + instructions { + cv_msuu_i16 { + encoding: 7'b0100101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msuu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msus_i16 extends RV32I { + instructions { + cv_msus_i16 { + encoding: 7'b0100110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msus.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msuu_i32 extends RV32I { + instructions { + cv_msuu_i32 { + encoding: 7'b0100111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msuu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msus_i32 extends RV32I { + instructions { + cv_msus_i32 { + encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msus.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<32>)(X[rs1]) * (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulNu extends RV32I { + instructions { + cv_mulNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulNs extends RV32I { + instructions { + cv_mulNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhNu extends RV32I { + instructions { + cv_mulhhNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhNs extends RV32I { + instructions { + cv_mulhhNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulRNu extends RV32I { + instructions { + cv_mulRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulRNs extends RV32I { + instructions { + cv_mulRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhRNu extends RV32I { + instructions { + cv_mulhhRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulhhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhRNs extends RV32I { + instructions { + cv_mulhhRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulhhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macNu extends RV32I { + instructions { + cv_macNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macNs extends RV32I { + instructions { + cv_macNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhNu extends RV32I { + instructions { + cv_machhNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { + instructions { + cv_machhNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macRNu extends RV32I { + instructions { + cv_macRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macRNs extends RV32I { + instructions { + cv_macRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhRNu extends RV32I { + instructions { + cv_machhRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhRNs extends RV32I { + instructions { + cv_machhRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} +InstructionSet Seal5Test_ext extends RV32I { + instructions { + CV_EXTHS { + encoding: 7'b0110000 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; + assembly: {"cv.exths", "{name(rd)}, {name(rs1)}" }; + behavior: { + if (rd != 0) { + X[rd] = (signed)X[rs1][15:0]; + } + } + } + CV_EXTHZ { + encoding: 7'b0110001 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; + assembly: {"cv.exthz", "{name(rd)}, {name(rs1)}" }; + behavior: { + if (rd != 0) { + X[rd] = (unsigned)X[rs1][15:0]; + } + } + } + CV_EXTBS { + encoding: 7'b0110010 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; + assembly: {"cv.extbs", "{name(rd)}, {name(rs1)}" }; + behavior: { + if (rd != 0) { + X[rd] = (signed)X[rs1][7:0]; + } + } + } + CV_EXTBZ { + encoding: 7'b0110011 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; + assembly: {"cv.extbz", "{name(rd)}, {name(rs1)}" }; + behavior: { + if (rd != 0) { + X[rd] = (unsigned)X[rs1][7:0]; + } + } + } + } +} diff --git a/examples/cdsl/rv_gen/all_v9.core_desc b/examples/cdsl/rv_gen/all_v9.core_desc new file mode 100644 index 00000000..84d44b3c --- /dev/null +++ b/examples/cdsl/rv_gen/all_v9.core_desc @@ -0,0 +1,949 @@ +import "../rv_base/RV32I.core_desc" + +InstructionSet Seal5Test_alu_cv_abs8 extends RV32I { + instructions { + cv_abs8 { + encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.abs8", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)((signed<8>)(X[rs1])) < 0 ? -(signed<8>)(X[rs1]) : (signed<8>)(X[rs1]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_abs16 extends RV32I { + instructions { + cv_abs16 { + encoding: 7'b0000001 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.abs16", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)((signed<16>)(X[rs1])) < 0 ? -(signed<16>)(X[rs1]) : (signed<16>)(X[rs1]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_abs32 extends RV32I { + instructions { + cv_abs32 { + encoding: 7'b0000010 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.abs32", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)((signed)(X[rs1])) < 0 ? -(signed)(X[rs1]) : (signed)(X[rs1]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_exths extends RV32I { + instructions { + cv_exths { + encoding: 7'b0000011 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.exths", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1][15:0]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_exthz extends RV32I { + instructions { + cv_exthz { + encoding: 7'b0000100 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.exthz", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned)(X[rs1][15:0]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_extbs extends RV32I { + instructions { + cv_extbs { + encoding: 7'b0000101 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.extbs", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1][7:0]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_extbz extends RV32I { + instructions { + cv_extbz { + encoding: 7'b0000110 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.extbz", "{name(rd)}, {name(rs1)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned)(X[rs1][7:0]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini5_16 extends RV32I { + instructions { + cv_mini5_16 { + encoding: 7'b0000111 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) < (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini5_32 extends RV32I { + instructions { + cv_mini5_32 { + encoding: 7'b0001000 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) < (signed<5>)(imm5) ? (signed)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini12_16 extends RV32I { + instructions { + cv_mini12_16 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) < (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_mini12_32 extends RV32I { + instructions { + cv_mini12_32 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mini12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) < (signed<12>)(imm5) ? (signed)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi5_16 extends RV32I { + instructions { + cv_maxi5_16 { + encoding: 7'b0001001 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) > (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi5_32 extends RV32I { + instructions { + cv_maxi5_32 { + encoding: 7'b0001010 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) > (signed<5>)(imm5) ? (signed)(X[rs1]) : (signed<5>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi12_16 extends RV32I { + instructions { + cv_maxi12_16 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) > (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_maxi12_32 extends RV32I { + instructions { + cv_maxi12_32 { + encoding: imm5[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.maxi12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) > (signed<12>)(imm5) ? (signed)(X[rs1]) : (signed<12>)(imm5); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_min_u_8 extends RV32I { + instructions { + cv_min_u_8 { + encoding: 7'b0001011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min.u.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<8>)(X[rs1]) < (unsigned<8>)(X[rs2]) ? (unsigned<8>)(X[rs1]) : (unsigned<8>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_min_s_8 extends RV32I { + instructions { + cv_min_s_8 { + encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min.s.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<8>)(X[rs1]) < (signed<8>)(X[rs2]) ? (signed<8>)(X[rs1]) : (signed<8>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_min_u_16 extends RV32I { + instructions { + cv_min_u_16 { + encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min.u.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1]) < (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_min_s_16 extends RV32I { + instructions { + cv_min_s_16 { + encoding: 7'b0001110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min.s.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) < (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_min_u_32 extends RV32I { + instructions { + cv_min_u_32 { + encoding: 7'b0001111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min.u.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] < X[rs2] ? X[rs1] : X[rs2]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_min_s_32 extends RV32I { + instructions { + cv_min_s_32 { + encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.min.s.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) < (signed)(X[rs2]) ? (signed)(X[rs1]) : (signed)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_max_u_8 extends RV32I { + instructions { + cv_max_u_8 { + encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max.u.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<8>)(X[rs1]) > (unsigned<8>)(X[rs2]) ? (unsigned<8>)(X[rs1]) : (unsigned<8>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_max_s_8 extends RV32I { + instructions { + cv_max_s_8 { + encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max.s.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<8>)(X[rs1]) > (signed<8>)(X[rs2]) ? (signed<8>)(X[rs1]) : (signed<8>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_max_u_16 extends RV32I { + instructions { + cv_max_u_16 { + encoding: 7'b0010011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max.u.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1]) > (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_max_s_16 extends RV32I { + instructions { + cv_max_s_16 { + encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max.s.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) > (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_max_u_32 extends RV32I { + instructions { + cv_max_u_32 { + encoding: 7'b0010101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max.u.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] > X[rs2] ? X[rs1] : X[rs2]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_max_s_32 extends RV32I { + instructions { + cv_max_s_32 { + encoding: 7'b0010110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.max.s.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) > (signed)(X[rs2]) ? (signed)(X[rs1]) : (signed)(X[rs2]); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_sletu_i16 extends RV32I { + instructions { + cv_sletu_i16 { + encoding: 7'b0010111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.sletu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1]) <= (unsigned<16>)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_slets_i16 extends RV32I { + instructions { + cv_slets_i16 { + encoding: 7'b0011000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.slets.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1]) <= (signed<16>)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_sletu_i32 extends RV32I { + instructions { + cv_sletu_i32 { + encoding: 7'b0011001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.sletu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] <= X[rs2] ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_slets_i32 extends RV32I { + instructions { + cv_slets_i32 { + encoding: 7'b0011010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.slets.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) <= (signed)(X[rs2]) ? 1 : 0; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNru_i16 extends RV32I { + instructions { + cv_addNru_i16 { + encoding: 7'b0011011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNrs_i16 extends RV32I { + instructions { + cv_addNrs_i16 { + encoding: 7'b0011100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNru_i32 extends RV32I { + instructions { + cv_addNru_i32 { + encoding: 7'b0011101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNrs_i32 extends RV32I { + instructions { + cv_addNrs_i32 { + encoding: 7'b0011110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed)(X[rs1]) >> (signed)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNru_i16 extends RV32I { + instructions { + cv_subNru_i16 { + encoding: 7'b0011111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNrs_i16 extends RV32I { + instructions { + cv_subNrs_i16 { + encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNru_i32 extends RV32I { + instructions { + cv_subNru_i32 { + encoding: 7'b0100001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNrs_i32 extends RV32I { + instructions { + cv_subNrs_i32 { + encoding: 7'b0100010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed)(X[rs1]) >> (signed)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNru_i16 extends RV32I { + instructions { + cv_addRNru_i16 { + encoding: 7'b0100011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNrs_i16 extends RV32I { + instructions { + cv_addRNrs_i16 { + encoding: 7'b0100100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNru_i32 extends RV32I { + instructions { + cv_addRNru_i32 { + encoding: 7'b0100101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNrs_i32 extends RV32I { + instructions { + cv_addRNrs_i32 { + encoding: 7'b0100110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] + (signed)(X[rs1]) + 2 ^ (signed)(X[rs2])[4:0] - 1 >> (signed)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNru_i16 extends RV32I { + instructions { + cv_subRNru_i16 { + encoding: 7'b0100111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNrs_i16 extends RV32I { + instructions { + cv_subRNrs_i16 { + encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNru_i32 extends RV32I { + instructions { + cv_subRNru_i32 { + encoding: 7'b0101001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNrs_i32 extends RV32I { + instructions { + cv_subRNrs_i32 { + encoding: 7'b0101010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = X[rd] - (signed)(X[rs1]) + 2 ^ (signed)(X[rs2])[4:0] - 1 >> (signed)(X[rs2])[4:0]; + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNu extends RV32I { + instructions { + cv_addNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] + X[rs2] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addNs extends RV32I { + instructions { + cv_addNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) + (signed)(X[rs2]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNu extends RV32I { + instructions { + cv_subNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] - X[rs2] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subNs extends RV32I { + instructions { + cv_subNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) - (signed)(X[rs2]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNu extends RV32I { + instructions { + cv_addRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] + X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_addRNs extends RV32I { + instructions { + cv_addRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.addRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) + (signed)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNu extends RV32I { + instructions { + cv_subRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = X[rs1] - X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_alu_cv_subRNs extends RV32I { + instructions { + cv_subRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.subRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed)(X[rs1]) - (signed)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macu_i16 extends RV32I { + instructions { + cv_macu_i16 { + encoding: 7'b0101011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = ((unsigned<16>)(X[rs1]) * (unsigned<16>)(X[rs2]) + X[rd])[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macs_i16 extends RV32I { + instructions { + cv_macs_i16 { + encoding: 7'b0101100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = ((signed<16>)(X[rs1]) * (signed<16>)(X[rs2]) + (signed)(X[rd]))[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macu_i32 extends RV32I { + instructions { + cv_macu_i32 { + encoding: 7'b0101101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (X[rs1] * X[rs2] + X[rd])[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macs_i32 extends RV32I { + instructions { + cv_macs_i32 { + encoding: 7'b0101110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.macs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = ((signed)(X[rs1]) * (signed)(X[rs2]) + (signed)(X[rd]))[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msuu_i16 extends RV32I { + instructions { + cv_msuu_i16 { + encoding: 7'b0101111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msuu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = ((unsigned<16>)(X[rs1]) * (unsigned<16>)(X[rs2]) - X[rd])[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msus_i16 extends RV32I { + instructions { + cv_msus_i16 { + encoding: 7'b0110000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msus.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = ((signed<16>)(X[rs1]) * (signed<16>)(X[rs2]) - (signed)(X[rd]))[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msuu_i32 extends RV32I { + instructions { + cv_msuu_i32 { + encoding: 7'b0110001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msuu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = (X[rs1] * X[rs2] - X[rd])[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_msus_i32 extends RV32I { + instructions { + cv_msus_i32 { + encoding: 7'b0110010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.msus.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; + behavior: if (rd != 0) { + X[rd] = ((signed)(X[rs1]) * (signed)(X[rs2]) - (signed)(X[rd]))[31:0]; + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulNu extends RV32I { + instructions { + cv_mulNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulNs extends RV32I { + instructions { + cv_mulNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhNu extends RV32I { + instructions { + cv_mulhhNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhNs extends RV32I { + instructions { + cv_mulhhNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; + assembly: {"cv.mulhhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulRNu extends RV32I { + instructions { + cv_mulRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulRNs extends RV32I { + instructions { + cv_mulRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhRNu extends RV32I { + instructions { + cv_mulhhRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulhhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_mulhhRNs extends RV32I { + instructions { + cv_mulhhRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.mulhhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macNu extends RV32I { + instructions { + cv_macNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macNs extends RV32I { + instructions { + cv_macNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + (signed)(X[rd]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhNu extends RV32I { + instructions { + cv_machhNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { + instructions { + cv_machhNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + (signed)(X[rd]) >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macRNu extends RV32I { + instructions { + cv_macRNu { + encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_macRNs extends RV32I { + instructions { + cv_macRNs { + encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.macRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + (signed)(X[rd]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhRNu extends RV32I { + instructions { + cv_machhRNu { + encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} + +InstructionSet Seal5Test_mac_cv_machhRNs extends RV32I { + instructions { + cv_machhRNs { + encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; + assembly: {"cv.machhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; + behavior: if (rd != 0) { + X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + (signed)(X[rd]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); + } + } + } +} From 793f81b43c607ab03b50f8e332ab8273fddd5ea8 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 07:14:08 +0100 Subject: [PATCH 75/80] remove rv_gen dir --- examples/cdsl/rv_gen/.gitkeep | 0 examples/cdsl/rv_gen/all_v2.core_desc | 90 --- examples/cdsl/rv_gen/all_v5.core_desc | 517 -------------- examples/cdsl/rv_gen/all_v7.core_desc | 869 ----------------------- examples/cdsl/rv_gen/all_v9.core_desc | 949 -------------------------- examples/cdsl/rv_gen/test.core_desc | 64 -- 6 files changed, 2489 deletions(-) delete mode 100644 examples/cdsl/rv_gen/.gitkeep delete mode 100644 examples/cdsl/rv_gen/all_v2.core_desc delete mode 100644 examples/cdsl/rv_gen/all_v5.core_desc delete mode 100644 examples/cdsl/rv_gen/all_v7.core_desc delete mode 100644 examples/cdsl/rv_gen/all_v9.core_desc delete mode 100644 examples/cdsl/rv_gen/test.core_desc diff --git a/examples/cdsl/rv_gen/.gitkeep b/examples/cdsl/rv_gen/.gitkeep deleted file mode 100644 index e69de29b..00000000 diff --git a/examples/cdsl/rv_gen/all_v2.core_desc b/examples/cdsl/rv_gen/all_v2.core_desc deleted file mode 100644 index fbc3ce64..00000000 --- a/examples/cdsl/rv_gen/all_v2.core_desc +++ /dev/null @@ -1,90 +0,0 @@ -import "../rv_base/RV32I.core_desc" - -InstructionSet Seal5Test_alu extends RV32I { - instructions { - abs { - encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.abs", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) < 0 ? -(signed<32>)(X[rs1]) : (signed<32>)(X[rs1]); - } - } - min { - encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) < (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); - } - } - max { - encoding: 7'b0000010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) > (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); - } - } - slet { - encoding: 7'b0000011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.slet", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) <= (signed<32>)(X[rs2]) ? 1 : 0; - } - } - addNr { - encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; - } - } - subNr { - encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; - } - } - addRNr { - encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; - } - } - subRNr { - encoding: 7'b0000111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNr", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; - } - } - addN { - encoding: 2'b00 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) >> (unsigned<5>)(imm5); - } - } - subN { - encoding: 2'b01 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) >> (unsigned<5>)(imm5); - } - } - addRN { - encoding: 2'b10 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(imm5) - 1 >> (unsigned<5>)(imm5); - } - } - subRN { - encoding: 2'b11 :: imm5[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRN", "{name(rd)}, {name(rs1)}, {name(rs2)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(imm5) - 1 >> (unsigned<5>)(imm5); - } - } - } -} diff --git a/examples/cdsl/rv_gen/all_v5.core_desc b/examples/cdsl/rv_gen/all_v5.core_desc deleted file mode 100644 index 62f98e0f..00000000 --- a/examples/cdsl/rv_gen/all_v5.core_desc +++ /dev/null @@ -1,517 +0,0 @@ -import "../rv_base/RV32I.core_desc" - -InstructionSet Seal5Test_alu_cv_abs extends RV32I { - instructions { - cv_abs { - encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.abs", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)X[rs1] < 0 ? -X[rs1] : X[rs1]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_minu extends RV32I { - instructions { - cv_minu { - encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.minu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] < X[rs2] ? X[rs1] : X[rs2]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mins extends RV32I { - instructions { - cv_mins { - encoding: 7'b0000010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mins", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) < (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxu extends RV32I { - instructions { - cv_maxu { - encoding: 7'b0000011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] > X[rs2] ? X[rs1] : X[rs2]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxs extends RV32I { - instructions { - cv_maxs { - encoding: 7'b0000100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) > (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_sletu extends RV32I { - instructions { - cv_sletu { - encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.sletu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] <= X[rs2] ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_slets extends RV32I { - instructions { - cv_slets { - encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.slets", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) <= (signed<32>)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNru extends RV32I { - instructions { - cv_addNru { - encoding: 7'b0000111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNrs extends RV32I { - instructions { - cv_addNrs { - encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNru extends RV32I { - instructions { - cv_subNru { - encoding: 7'b0001001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNrs extends RV32I { - instructions { - cv_subNrs { - encoding: 7'b0001010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNru extends RV32I { - instructions { - cv_addRNru { - encoding: 7'b0001011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNrs extends RV32I { - instructions { - cv_addRNrs { - encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNru extends RV32I { - instructions { - cv_subRNru { - encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNru", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNrs extends RV32I { - instructions { - cv_subRNrs { - encoding: 7'b0001110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNrs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNu extends RV32I { - instructions { - cv_addNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] + X[rs2] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNs extends RV32I { - instructions { - cv_addNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNu extends RV32I { - instructions { - cv_subNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] - X[rs2] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNs extends RV32I { - instructions { - cv_subNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNu extends RV32I { - instructions { - cv_addRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] + X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNs extends RV32I { - instructions { - cv_addRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNu extends RV32I { - instructions { - cv_subRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] - X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNs extends RV32I { - instructions { - cv_subRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macu extends RV32I { - instructions { - cv_macu { - encoding: 7'b0001111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macs extends RV32I { - instructions { - cv_macs { - encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macs", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msuu extends RV32I { - instructions { - cv_msuu { - encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msuu", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msus extends RV32I { - instructions { - cv_msus { - encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msus", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulNu extends RV32I { - instructions { - cv_mulNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulNs extends RV32I { - instructions { - cv_mulNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhNu extends RV32I { - instructions { - cv_mulhhNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhNs extends RV32I { - instructions { - cv_mulhhNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulRNu extends RV32I { - instructions { - cv_mulRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulRNs extends RV32I { - instructions { - cv_mulRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhRNu extends RV32I { - instructions { - cv_mulhhRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhRNs extends RV32I { - instructions { - cv_mulhhRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macNu extends RV32I { - instructions { - cv_macNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macNs extends RV32I { - instructions { - cv_macNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhNu extends RV32I { - instructions { - cv_machhNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.machhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { - instructions { - cv_machhNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.machhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macRNu extends RV32I { - instructions { - cv_macRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macRNs extends RV32I { - instructions { - cv_macRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhRNu extends RV32I { - instructions { - cv_machhRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.machhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhRNs extends RV32I { - instructions { - cv_machhRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.machhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} diff --git a/examples/cdsl/rv_gen/all_v7.core_desc b/examples/cdsl/rv_gen/all_v7.core_desc deleted file mode 100644 index 03a8ef85..00000000 --- a/examples/cdsl/rv_gen/all_v7.core_desc +++ /dev/null @@ -1,869 +0,0 @@ -import "../rv_base/RV32I.core_desc" - -InstructionSet Seal5Test_alu_cv_abs extends RV32I { - instructions { - cv_abs { - encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.abs", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) < 0 ? -X[rs1] : X[rs1]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini5_16 extends RV32I { - instructions { - cv_mini5_16 { - encoding: 7'b0000001 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) < (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini5_32 extends RV32I { - instructions { - cv_mini5_32 { - encoding: 7'b0000010 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) < (signed<5>)(imm5) ? (signed<32>)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini12_16 extends RV32I { - instructions { - cv_mini12_16 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) < (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini12_32 extends RV32I { - instructions { - cv_mini12_32 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) < (signed<12>)(imm5) ? (signed<32>)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi5_16 extends RV32I { - instructions { - cv_maxi5_16 { - encoding: 7'b0000011 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) > (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi5_32 extends RV32I { - instructions { - cv_maxi5_32 { - encoding: 7'b0000100 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) > (signed<5>)(imm5) ? (signed<32>)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi12_16 extends RV32I { - instructions { - cv_maxi12_16 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) > (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi12_32 extends RV32I { - instructions { - cv_maxi12_32 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) > (signed<12>)(imm5) ? (signed<32>)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_minu_i16 extends RV32I { - instructions { - cv_minu_i16 { - encoding: 7'b0000101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.minu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1]) < (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mins_i16 extends RV32I { - instructions { - cv_mins_i16 { - encoding: 7'b0000110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mins.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) < (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_minu_i32 extends RV32I { - instructions { - cv_minu_i32 { - encoding: 7'b0000111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.minu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] < X[rs2] ? X[rs1] : X[rs2]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mins_i32 extends RV32I { - instructions { - cv_mins_i32 { - encoding: 7'b0001000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mins.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) < (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxu_i16 extends RV32I { - instructions { - cv_maxu_i16 { - encoding: 7'b0001001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1]) > (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxs_i16 extends RV32I { - instructions { - cv_maxs_i16 { - encoding: 7'b0001010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) > (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxu_i32 extends RV32I { - instructions { - cv_maxu_i32 { - encoding: 7'b0001011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] > X[rs2] ? X[rs1] : X[rs2]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxs_i32 extends RV32I { - instructions { - cv_maxs_i32 { - encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) > (signed<32>)(X[rs2]) ? (signed<32>)(X[rs1]) : (signed<32>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_sletu_i16 extends RV32I { - instructions { - cv_sletu_i16 { - encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.sletu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1]) <= (unsigned<16>)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_slets_i16 extends RV32I { - instructions { - cv_slets_i16 { - encoding: 7'b0001110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.slets.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) <= (signed<16>)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_sletu_i32 extends RV32I { - instructions { - cv_sletu_i32 { - encoding: 7'b0001111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.sletu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] <= X[rs2] ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_slets_i32 extends RV32I { - instructions { - cv_slets_i32 { - encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.slets.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) <= (signed<32>)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNru_i16 extends RV32I { - instructions { - cv_addNru_i16 { - encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNrs_i16 extends RV32I { - instructions { - cv_addNrs_i16 { - encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNru_i32 extends RV32I { - instructions { - cv_addNru_i32 { - encoding: 7'b0010011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNrs_i32 extends RV32I { - instructions { - cv_addNrs_i32 { - encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNru_i16 extends RV32I { - instructions { - cv_subNru_i16 { - encoding: 7'b0010101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNrs_i16 extends RV32I { - instructions { - cv_subNrs_i16 { - encoding: 7'b0010110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNru_i32 extends RV32I { - instructions { - cv_subNru_i32 { - encoding: 7'b0010111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNrs_i32 extends RV32I { - instructions { - cv_subNrs_i32 { - encoding: 7'b0011000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNru_i16 extends RV32I { - instructions { - cv_addRNru_i16 { - encoding: 7'b0011001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNrs_i16 extends RV32I { - instructions { - cv_addRNrs_i16 { - encoding: 7'b0011010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNru_i32 extends RV32I { - instructions { - cv_addRNru_i32 { - encoding: 7'b0011011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNrs_i32 extends RV32I { - instructions { - cv_addRNrs_i32 { - encoding: 7'b0011100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNru_i16 extends RV32I { - instructions { - cv_subRNru_i16 { - encoding: 7'b0011101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNrs_i16 extends RV32I { - instructions { - cv_subRNrs_i16 { - encoding: 7'b0011110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNru_i32 extends RV32I { - instructions { - cv_subRNru_i32 { - encoding: 7'b0011111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNrs_i32 extends RV32I { - instructions { - cv_subRNrs_i32 { - encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) + 2 ^ (signed<32>)(X[rs2])[4:0] - 1 >> (signed<32>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNu extends RV32I { - instructions { - cv_addNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] + X[rs2] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNs extends RV32I { - instructions { - cv_addNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNu extends RV32I { - instructions { - cv_subNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] - X[rs2] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNs extends RV32I { - instructions { - cv_subNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNu extends RV32I { - instructions { - cv_addRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] + X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNs extends RV32I { - instructions { - cv_addRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNu extends RV32I { - instructions { - cv_subRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] - X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNs extends RV32I { - instructions { - cv_subRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<32>)(X[rs1]) - (signed<32>)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macu_i16 extends RV32I { - instructions { - cv_macu_i16 { - encoding: 7'b0100001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macs_i16 extends RV32I { - instructions { - cv_macs_i16 { - encoding: 7'b0100010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macu_i32 extends RV32I { - instructions { - cv_macu_i32 { - encoding: 7'b0100011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macs_i32 extends RV32I { - instructions { - cv_macs_i32 { - encoding: 7'b0100100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<32>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msuu_i16 extends RV32I { - instructions { - cv_msuu_i16 { - encoding: 7'b0100101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msuu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (unsigned<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msus_i16 extends RV32I { - instructions { - cv_msus_i16 { - encoding: 7'b0100110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msus.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<16>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msuu_i32 extends RV32I { - instructions { - cv_msuu_i32 { - encoding: 7'b0100111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msuu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msus_i32 extends RV32I { - instructions { - cv_msus_i32 { - encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msus.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<32>)(X[rs1]) * (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulNu extends RV32I { - instructions { - cv_mulNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulNs extends RV32I { - instructions { - cv_mulNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhNu extends RV32I { - instructions { - cv_mulhhNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhNs extends RV32I { - instructions { - cv_mulhhNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulRNu extends RV32I { - instructions { - cv_mulRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulRNs extends RV32I { - instructions { - cv_mulRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhRNu extends RV32I { - instructions { - cv_mulhhRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulhhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhRNs extends RV32I { - instructions { - cv_mulhhRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulhhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macNu extends RV32I { - instructions { - cv_macNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macNs extends RV32I { - instructions { - cv_macNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhNu extends RV32I { - instructions { - cv_machhNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { - instructions { - cv_machhNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macRNu extends RV32I { - instructions { - cv_macRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macRNs extends RV32I { - instructions { - cv_macRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhRNu extends RV32I { - instructions { - cv_machhRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhRNs extends RV32I { - instructions { - cv_machhRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} -InstructionSet Seal5Test_ext extends RV32I { - instructions { - CV_EXTHS { - encoding: 7'b0110000 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; - assembly: {"cv.exths", "{name(rd)}, {name(rs1)}" }; - behavior: { - if (rd != 0) { - X[rd] = (signed)X[rs1][15:0]; - } - } - } - CV_EXTHZ { - encoding: 7'b0110001 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; - assembly: {"cv.exthz", "{name(rd)}, {name(rs1)}" }; - behavior: { - if (rd != 0) { - X[rd] = (unsigned)X[rs1][15:0]; - } - } - } - CV_EXTBS { - encoding: 7'b0110010 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; - assembly: {"cv.extbs", "{name(rd)}, {name(rs1)}" }; - behavior: { - if (rd != 0) { - X[rd] = (signed)X[rs1][7:0]; - } - } - } - CV_EXTBZ { - encoding: 7'b0110011 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011; - assembly: {"cv.extbz", "{name(rd)}, {name(rs1)}" }; - behavior: { - if (rd != 0) { - X[rd] = (unsigned)X[rs1][7:0]; - } - } - } - } -} diff --git a/examples/cdsl/rv_gen/all_v9.core_desc b/examples/cdsl/rv_gen/all_v9.core_desc deleted file mode 100644 index 84d44b3c..00000000 --- a/examples/cdsl/rv_gen/all_v9.core_desc +++ /dev/null @@ -1,949 +0,0 @@ -import "../rv_base/RV32I.core_desc" - -InstructionSet Seal5Test_alu_cv_abs8 extends RV32I { - instructions { - cv_abs8 { - encoding: 7'b0000000 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.abs8", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)((signed<8>)(X[rs1])) < 0 ? -(signed<8>)(X[rs1]) : (signed<8>)(X[rs1]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_abs16 extends RV32I { - instructions { - cv_abs16 { - encoding: 7'b0000001 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.abs16", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)((signed<16>)(X[rs1])) < 0 ? -(signed<16>)(X[rs1]) : (signed<16>)(X[rs1]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_abs32 extends RV32I { - instructions { - cv_abs32 { - encoding: 7'b0000010 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.abs32", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)((signed)(X[rs1])) < 0 ? -(signed)(X[rs1]) : (signed)(X[rs1]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_exths extends RV32I { - instructions { - cv_exths { - encoding: 7'b0000011 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.exths", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1][15:0]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_exthz extends RV32I { - instructions { - cv_exthz { - encoding: 7'b0000100 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.exthz", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned)(X[rs1][15:0]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_extbs extends RV32I { - instructions { - cv_extbs { - encoding: 7'b0000101 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.extbs", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1][7:0]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_extbz extends RV32I { - instructions { - cv_extbz { - encoding: 7'b0000110 :: 5'b00000 :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.extbz", "{name(rd)}, {name(rs1)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned)(X[rs1][7:0]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini5_16 extends RV32I { - instructions { - cv_mini5_16 { - encoding: 7'b0000111 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) < (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini5_32 extends RV32I { - instructions { - cv_mini5_32 { - encoding: 7'b0001000 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) < (signed<5>)(imm5) ? (signed)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini12_16 extends RV32I { - instructions { - cv_mini12_16 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) < (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_mini12_32 extends RV32I { - instructions { - cv_mini12_32 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mini12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) < (signed<12>)(imm5) ? (signed)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi5_16 extends RV32I { - instructions { - cv_maxi5_16 { - encoding: 7'b0001001 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi5.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) > (signed<5>)(imm5) ? (signed<16>)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi5_32 extends RV32I { - instructions { - cv_maxi5_32 { - encoding: 7'b0001010 :: imm5[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi5.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) > (signed<5>)(imm5) ? (signed)(X[rs1]) : (signed<5>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi12_16 extends RV32I { - instructions { - cv_maxi12_16 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi12.16", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) > (signed<12>)(imm5) ? (signed<16>)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_maxi12_32 extends RV32I { - instructions { - cv_maxi12_32 { - encoding: imm5[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.maxi12.32", "{name(rd)}, {name(rs1)}, {imm5}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) > (signed<12>)(imm5) ? (signed)(X[rs1]) : (signed<12>)(imm5); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_min_u_8 extends RV32I { - instructions { - cv_min_u_8 { - encoding: 7'b0001011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min.u.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<8>)(X[rs1]) < (unsigned<8>)(X[rs2]) ? (unsigned<8>)(X[rs1]) : (unsigned<8>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_min_s_8 extends RV32I { - instructions { - cv_min_s_8 { - encoding: 7'b0001100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min.s.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<8>)(X[rs1]) < (signed<8>)(X[rs2]) ? (signed<8>)(X[rs1]) : (signed<8>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_min_u_16 extends RV32I { - instructions { - cv_min_u_16 { - encoding: 7'b0001101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min.u.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1]) < (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_min_s_16 extends RV32I { - instructions { - cv_min_s_16 { - encoding: 7'b0001110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min.s.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) < (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_min_u_32 extends RV32I { - instructions { - cv_min_u_32 { - encoding: 7'b0001111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min.u.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] < X[rs2] ? X[rs1] : X[rs2]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_min_s_32 extends RV32I { - instructions { - cv_min_s_32 { - encoding: 7'b0010000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.min.s.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) < (signed)(X[rs2]) ? (signed)(X[rs1]) : (signed)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_max_u_8 extends RV32I { - instructions { - cv_max_u_8 { - encoding: 7'b0010001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max.u.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<8>)(X[rs1]) > (unsigned<8>)(X[rs2]) ? (unsigned<8>)(X[rs1]) : (unsigned<8>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_max_s_8 extends RV32I { - instructions { - cv_max_s_8 { - encoding: 7'b0010010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max.s.8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<8>)(X[rs1]) > (signed<8>)(X[rs2]) ? (signed<8>)(X[rs1]) : (signed<8>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_max_u_16 extends RV32I { - instructions { - cv_max_u_16 { - encoding: 7'b0010011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max.u.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1]) > (unsigned<16>)(X[rs2]) ? (unsigned<16>)(X[rs1]) : (unsigned<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_max_s_16 extends RV32I { - instructions { - cv_max_s_16 { - encoding: 7'b0010100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max.s.16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) > (signed<16>)(X[rs2]) ? (signed<16>)(X[rs1]) : (signed<16>)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_max_u_32 extends RV32I { - instructions { - cv_max_u_32 { - encoding: 7'b0010101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max.u.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] > X[rs2] ? X[rs1] : X[rs2]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_max_s_32 extends RV32I { - instructions { - cv_max_s_32 { - encoding: 7'b0010110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.max.s.32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) > (signed)(X[rs2]) ? (signed)(X[rs1]) : (signed)(X[rs2]); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_sletu_i16 extends RV32I { - instructions { - cv_sletu_i16 { - encoding: 7'b0010111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.sletu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1]) <= (unsigned<16>)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_slets_i16 extends RV32I { - instructions { - cv_slets_i16 { - encoding: 7'b0011000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.slets.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1]) <= (signed<16>)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_sletu_i32 extends RV32I { - instructions { - cv_sletu_i32 { - encoding: 7'b0011001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.sletu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] <= X[rs2] ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_slets_i32 extends RV32I { - instructions { - cv_slets_i32 { - encoding: 7'b0011010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.slets.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) <= (signed)(X[rs2]) ? 1 : 0; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNru_i16 extends RV32I { - instructions { - cv_addNru_i16 { - encoding: 7'b0011011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNrs_i16 extends RV32I { - instructions { - cv_addNrs_i16 { - encoding: 7'b0011100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNru_i32 extends RV32I { - instructions { - cv_addNru_i32 { - encoding: 7'b0011101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNrs_i32 extends RV32I { - instructions { - cv_addNrs_i32 { - encoding: 7'b0011110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed)(X[rs1]) >> (signed)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNru_i16 extends RV32I { - instructions { - cv_subNru_i16 { - encoding: 7'b0011111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (unsigned<16>)(X[rs1]) >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNrs_i16 extends RV32I { - instructions { - cv_subNrs_i16 { - encoding: 7'b0100000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<16>)(X[rs1]) >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNru_i32 extends RV32I { - instructions { - cv_subNru_i32 { - encoding: 7'b0100001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNrs_i32 extends RV32I { - instructions { - cv_subNrs_i32 { - encoding: 7'b0100010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed)(X[rs1]) >> (signed)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNru_i16 extends RV32I { - instructions { - cv_addRNru_i16 { - encoding: 7'b0100011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNrs_i16 extends RV32I { - instructions { - cv_addRNrs_i16 { - encoding: 7'b0100100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNru_i32 extends RV32I { - instructions { - cv_addRNru_i32 { - encoding: 7'b0100101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNrs_i32 extends RV32I { - instructions { - cv_addRNrs_i32 { - encoding: 7'b0100110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] + (signed)(X[rs1]) + 2 ^ (signed)(X[rs2])[4:0] - 1 >> (signed)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNru_i16 extends RV32I { - instructions { - cv_subRNru_i16 { - encoding: 7'b0100111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNru.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (unsigned<16>)(X[rs1]) + 2 ^ (unsigned<16>)(X[rs2])[4:0] - 1 >> (unsigned<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNrs_i16 extends RV32I { - instructions { - cv_subRNrs_i16 { - encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNrs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed<16>)(X[rs1]) + 2 ^ (signed<16>)(X[rs2])[4:0] - 1 >> (signed<16>)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNru_i32 extends RV32I { - instructions { - cv_subRNru_i32 { - encoding: 7'b0101001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNru.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - X[rs1] + 2 ^ X[rs2][4:0] - 1 >> X[rs2][4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNrs_i32 extends RV32I { - instructions { - cv_subRNrs_i32 { - encoding: 7'b0101010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNrs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = X[rd] - (signed)(X[rs1]) + 2 ^ (signed)(X[rs2])[4:0] - 1 >> (signed)(X[rs2])[4:0]; - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNu extends RV32I { - instructions { - cv_addNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] + X[rs2] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addNs extends RV32I { - instructions { - cv_addNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) + (signed)(X[rs2]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNu extends RV32I { - instructions { - cv_subNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] - X[rs2] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subNs extends RV32I { - instructions { - cv_subNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) - (signed)(X[rs2]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNu extends RV32I { - instructions { - cv_addRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] + X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_addRNs extends RV32I { - instructions { - cv_addRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.addRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) + (signed)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNu extends RV32I { - instructions { - cv_subRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = X[rs1] - X[rs2] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_alu_cv_subRNs extends RV32I { - instructions { - cv_subRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.subRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed)(X[rs1]) - (signed)(X[rs2]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macu_i16 extends RV32I { - instructions { - cv_macu_i16 { - encoding: 7'b0101011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = ((unsigned<16>)(X[rs1]) * (unsigned<16>)(X[rs2]) + X[rd])[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macs_i16 extends RV32I { - instructions { - cv_macs_i16 { - encoding: 7'b0101100 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macs.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = ((signed<16>)(X[rs1]) * (signed<16>)(X[rs2]) + (signed)(X[rd]))[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macu_i32 extends RV32I { - instructions { - cv_macu_i32 { - encoding: 7'b0101101 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (X[rs1] * X[rs2] + X[rd])[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macs_i32 extends RV32I { - instructions { - cv_macs_i32 { - encoding: 7'b0101110 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.macs.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = ((signed)(X[rs1]) * (signed)(X[rs2]) + (signed)(X[rd]))[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msuu_i16 extends RV32I { - instructions { - cv_msuu_i16 { - encoding: 7'b0101111 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msuu.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = ((unsigned<16>)(X[rs1]) * (unsigned<16>)(X[rs2]) - X[rd])[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msus_i16 extends RV32I { - instructions { - cv_msus_i16 { - encoding: 7'b0110000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msus.i16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = ((signed<16>)(X[rs1]) * (signed<16>)(X[rs2]) - (signed)(X[rd]))[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msuu_i32 extends RV32I { - instructions { - cv_msuu_i32 { - encoding: 7'b0110001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msuu.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = (X[rs1] * X[rs2] - X[rd])[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_msus_i32 extends RV32I { - instructions { - cv_msus_i32 { - encoding: 7'b0110010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.msus.i32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: if (rd != 0) { - X[rd] = ((signed)(X[rs1]) * (signed)(X[rs2]) - (signed)(X[rd]))[31:0]; - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulNu extends RV32I { - instructions { - cv_mulNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulNs extends RV32I { - instructions { - cv_mulNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhNu extends RV32I { - instructions { - cv_mulhhNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhNs extends RV32I { - instructions { - cv_mulhhNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b111 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.mulhhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulRNu extends RV32I { - instructions { - cv_mulRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulRNs extends RV32I { - instructions { - cv_mulRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhRNu extends RV32I { - instructions { - cv_mulhhRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulhhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_mulhhRNs extends RV32I { - instructions { - cv_mulhhRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.mulhhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macNu extends RV32I { - instructions { - cv_macNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macNs extends RV32I { - instructions { - cv_macNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + (signed)(X[rd]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhNu extends RV32I { - instructions { - cv_machhNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhNs extends RV32I { - instructions { - cv_machhNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + (signed)(X[rd]) >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macRNu extends RV32I { - instructions { - cv_macRNu { - encoding: 2'b00 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[15:0] * (unsigned<16>)(X[rs2])[15:0] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_macRNs extends RV32I { - instructions { - cv_macRNs { - encoding: 2'b01 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.macRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[15:0] * (signed<16>)(X[rs2])[15:0] + (signed)(X[rd]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhRNu extends RV32I { - instructions { - cv_machhRNu { - encoding: 2'b10 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhRNu", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (unsigned<16>)(X[rs1])[31:16] * (unsigned<16>)(X[rs2])[31:16] + X[rd] + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} - -InstructionSet Seal5Test_mac_cv_machhRNs extends RV32I { - instructions { - cv_machhRNs { - encoding: 2'b11 :: Is3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b1011011; - assembly: {"cv.machhRNs", "{name(rd)}, {name(rs1)}, {name(rs2)}, {Is3}"}; - behavior: if (rd != 0) { - X[rd] = (signed<16>)(X[rs1])[31:16] * (signed<16>)(X[rs2])[31:16] + (signed)(X[rd]) + 2 ^ (unsigned<5>)(Is3) - 1 >> (unsigned<5>)(Is3); - } - } - } -} diff --git a/examples/cdsl/rv_gen/test.core_desc b/examples/cdsl/rv_gen/test.core_desc deleted file mode 100644 index 12581691..00000000 --- a/examples/cdsl/rv_gen/test.core_desc +++ /dev/null @@ -1,64 +0,0 @@ -import "../rv_base/RV32I.core_desc" -// import "../rv_base/RVM.core_desc" -// import "../rv_base/RVC.core_desc" -// import "../rv_base/RVF.core_desc" -// import "../rv_base/RVD.core_desc" -// import "tum_mod.core_desc" -// import "tum_rva.core_desc" -// import "tum_rvm.core_desc" - -// InstructionSet myext_alu { -InstructionSet myext_alu extends RV32I { - instructions { - adds16 { - encoding: 7'b0000000 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.adds16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: X[rd] = (signed<16>)(X[rs1]) + (signed<16>)(X[rs2]); - } - adds32 { - encoding: 7'b0000001 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.adds32", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: X[rd] = (signed<32>)(X[rs1]) + (signed<32>)(X[rs2]); - } - } -} - -// InstructionSet myext_simd { -InstructionSet myext_simd extends RV32I { - instructions { - simd_add8 { - encoding: 7'b0000010 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.simd_add8", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: { - X[rd][7:0] = (signed<8>)(X[rs1])[7:0] + (signed<8>)(X[rs2])[7:0]; - X[rd][15:8] = (signed<8>)(X[rs1])[15:8] + (signed<8>)(X[rs2])[15:8]; - X[rd][23:16] = (signed<8>)(X[rs1])[23:16] + (signed<8>)(X[rs2])[23:16]; - X[rd][31:24] = (signed<8>)(X[rs1])[31:24] + (signed<8>)(X[rs2])[31:24]; - } - } - simd_add16 { - encoding: 7'b0000011 :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b1111011; - assembly: {"cv.simd_add16", "{name(rd)}, {name(rs1)}, {name(rs2)}"}; - behavior: { - X[rd][15:0] = (signed<16>)(X[rs1])[15:0] + (signed<16>)(X[rs2])[15:0]; - X[rd][31:16] = (signed<16>)(X[rs1])[31:16] + (signed<16>)(X[rs2])[31:16]; - } - } - } -} - -// Core TestCore provides RV32I, RV32IC, RV32M, RV32A, RV32F, RV32FC, RV32D, RV32DC, myext_alu, myext_simd, Zifencei, tum_csr, tum_ret, tum_rva, tum_semihosting { -// architectural_state { -// CSR[0x000] = 0x0000000B; // ustatus -// CSR[RV_CSR_SSTATUS] = 0x0000000B; // sstatus -// CSR[RV_CSR_MSTATUS] = 0x0000000B; // mstatus -// -// CSR[RV_CSR_MISA] = 0x4014112D; // misa -// -// CSR[0xC10] = 0x00000003; -// -// CSR[RV_CSR_MIE] = 0xFFFFFBBB; // mie -// CSR[RV_CSR_SIE] = CSR[0x304] & (~(0x888)); // sie -// CSR[0x004] = CSR[0x304] & (~(0xAAA)); // uie -// } -// } From ab36a8e86420f0e2cc94dae440206d3f3cc6a303 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 07:14:45 +0100 Subject: [PATCH 76/80] add rv_gen submodule --- .gitmodules | 3 +++ examples/cdsl/rv_gen | 1 + 2 files changed, 4 insertions(+) create mode 160000 examples/cdsl/rv_gen diff --git a/.gitmodules b/.gitmodules index 1a4c4fd6..ca460c24 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,3 +7,6 @@ [submodule "examples/cdsl/rv_s4e"] path = examples/cdsl/rv_s4e url = https://github.com/DLR-SE/riscv-coredsl-extensions.git +[submodule "examples/cdsl/rv_gen"] + path = examples/cdsl/rv_gen + url = https://github.com/PhilippvK/Gen_ISA_CoreDSL.git diff --git a/examples/cdsl/rv_gen b/examples/cdsl/rv_gen new file mode 160000 index 00000000..8c35ff74 --- /dev/null +++ b/examples/cdsl/rv_gen @@ -0,0 +1 @@ +Subproject commit 8c35ff74af3e1ac019d3aa389163622a7a9bd37a From 39b5e223ca4efc3bbf8dc3eb42232ac865c42cea Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 10:48:49 +0100 Subject: [PATCH 77/80] [CI] .github/workflows/demo.yml: allow chooing script name for demo --- .github/workflows/demo.yml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/.github/workflows/demo.yml b/.github/workflows/demo.yml index e2fe328f..b41704e1 100644 --- a/.github/workflows/demo.yml +++ b/.github/workflows/demo.yml @@ -23,6 +23,10 @@ name: Usage Demo on: workflow_dispatch: inputs: + script: + description: "Script" + required: true + default: "demo.py" verbose: description: "Verbose (0/1)" required: true @@ -74,7 +78,7 @@ jobs: - name: Run the demo run: | source .venv/bin/activate - VERBOSE=${{ github.event.inputs.verbose }} FAST=${{ github.event.inputs.fast }} BUILD_CONFIG=${{ github.event.inputs.build_config }} python examples/demo.py + VERBOSE=${{ github.event.inputs.verbose }} FAST=${{ github.event.inputs.fast }} BUILD_CONFIG=${{ github.event.inputs.build_config }} python examples/${{ github.event.inputs.script }} - uses: actions/upload-artifact@v4 with: name: demo-export From 866c183686fee125af3b25d7095772aaf5703dfd Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 17:13:25 +0100 Subject: [PATCH 78/80] update rv_s4e submodule ref --- examples/cdsl/rv_s4e | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/cdsl/rv_s4e b/examples/cdsl/rv_s4e index 14c55750..c5d5d945 160000 --- a/examples/cdsl/rv_s4e +++ b/examples/cdsl/rv_s4e @@ -1 +1 @@ -Subproject commit 14c55750eb247a09e3d8e6d42501857524bdbd69 +Subproject commit c5d5d9455499aac76426c60f78a9ced088a08054 From 7220421ff56ec780fa07a3fac77a9daad35b3ad3 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 17:14:22 +0100 Subject: [PATCH 79/80] [lint] run black formatter --- examples/gen_demo.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/examples/gen_demo.py b/examples/gen_demo.py index 6de1e0f2..37036144 100644 --- a/examples/gen_demo.py +++ b/examples/gen_demo.py @@ -62,13 +62,15 @@ # Load CoreDSL inputs cdsl_files = [ # EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v7.core_desc", - EXAMPLES_DIR / "cdsl" / "rv_gen" / "all_v9.core_desc", + EXAMPLES_DIR + / "cdsl" + / "rv_gen" + / "all_v9.core_desc", ] seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True) # Load test inputs -test_files = [ -] +test_files = [] seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True) # Load YAML inputs From af31695b4204f3227d9c535c01fcfd7e547ef489 Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 28 Mar 2024 17:15:21 +0100 Subject: [PATCH 80/80] [lint] make flake8 happy --- seal5/backends/riscv_instr_info/writer.py | 5 ----- 1 file changed, 5 deletions(-) diff --git a/seal5/backends/riscv_instr_info/writer.py b/seal5/backends/riscv_instr_info/writer.py index 1be5806d..f5ac72f4 100644 --- a/seal5/backends/riscv_instr_info/writer.py +++ b/seal5/backends/riscv_instr_info/writer.py @@ -29,11 +29,6 @@ logger = logging.getLogger("riscv_instr_info") -# MAKO_TEMPLATE = """def Feature${predicate} : SubtargetFeature<"${arch}", "Has${predicate}", "true", "'${feature}' (${description})">; -# -# def Has${predicate} : Predicate<"Subtarget->has${predicate}()">, AssemblerPredicate<(any_of Feature${predicate}), "'${feature}' (${description})">;""" - - class Operand: def __init__(self, name, lower, upper): self.name = name