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Investigation of TableGen freezes for some Core-V instructions #106

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PhilippvK opened this issue Jul 11, 2024 · 1 comment
Open
5 tasks

Investigation of TableGen freezes for some Core-V instructions #106

PhilippvK opened this issue Jul 11, 2024 · 1 comment
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priority:high type:bug Something isn't working type:help wanted Extra attention is needed

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@PhilippvK
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Affected Instructions

  • CV_MACUN (16 x 16 bit multiply + 32bit acc + right shift) -> 33 bit intermediate result
  • CV_MULURN (16 x 16 bit multiply + add(1 << (n-1))) + right shift) -> 33 bit intermediate result
  • CV_MULSRN -> 33 bit intermediate result
  • CV_MACHHSN -> 33 bit intermediate result
  • CV_MULHHURN -> 33 bit intermediate result
  • CV_MACHHUN -> 33 bit intermediate result
  • CV_MACSN -> 33 bit intermediate result
  • CV_MULHHSRN -> 33 bit intermediate result
  • CV_MACHHSRN -> 34 bit intermediate result
  • CV_MACSRN > 34 bit intermediate result
  • Most dot products…

Not affected

  • CV_ADDN (32 x 32 bit addition + trunc to 32 bits + right shift) -> 32 bit intermediate result
  • ...

Observations:

  • There is a mismatch between MUL and ALU in RTL of CV32E40P (MUL has 2 carry bits, while ALU just overflows)
  • Core-V LLVM compiler uses truncating patterns for MAC/MUL
  • CoreDSL (used as Seal5 input) reflects the behavior of the RTL; hence CV_ADDN is not affected by the freeze.
  • Needs more experiments

Workarounds

  • Currently we just filter out the broken instructions completely:
    - SEAL5_CV_MACUN
    (Skipping just the pattern gen would also work)
  • Adding explicit truncations to the CDSL heavior of the affected instructions would also help, but we would not match the RTL then...

Next steps

  • Test on newest version of LLVM
  • Build minimal example to reproduce bug (MACUN? ADDN with carry?  Map to pseudo instr to drop dependency on Core-V LLVM)
  • Find the reason for the freeze (endless loop?)
  • Report bug to LLVM community
  • Submit bugfix
@PhilippvK PhilippvK added type:bug Something isn't working type:help wanted Extra attention is needed priority:high labels Jul 11, 2024
@PhilippvK PhilippvK self-assigned this Jul 11, 2024
@PhilippvK PhilippvK added this to the Full Core-V Support milestone Jul 11, 2024
@PhilippvK
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Some more context here:

  • The patterns explode in size as the intermediate 33/34 bit results are handled as i64. As this type is not natively supported on 32bit targets, the legalizers expands them to a sequence of supported operations.
  • TODO @PhilippvK: add example of generated patterns here for affected vs unaffected instructions!

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