Merge pull request #58 from tum-ei-eda/philippvk-new

Merge latest changes

examples/cdsl/Example.core_desc

@@ -5,9 +5,8 @@ InstructionSet XExample extends RV32I {
   instructions {
     // TODO: remove/replace prefix
     CV_SUBINCACC {
-      // encoding: 7'b0101000 :: 5'b00000 :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
       encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
-      assembly: "{name(rd)}, {name(rs1)}";
+      assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
       behavior: {
         if (rd != 0) {
           X[rd] += X[rs1] - X[rs2] + 1;

examples/cdsl/rv_tumeda/XCoreVNand.core_desc

@@ -13,7 +13,7 @@ InstructionSet XCoreVNand extends RV32I {
         // }
         CV_NAND_BITWISE {
             encoding: 7'b1001001 :: rs2[4:0] :: rs1[4:0] :: 3'b110 :: rd[4:0] :: 7'b0101011;
-            assembly: {"cv.nand_bitwise", "{name(rd)}, {name(rs1)}, {name(rs2)}"};
+            assembly: {"cv.nand.bitwise", "{name(rd)}, {name(rs1)}, {name(rs2)}"};
             behavior: {
               if(rd != 0) X[rd] = ~(X[rs1] & X[rs2]);
             }

examples/cfg/filter.yml

@@ -2,11 +2,13 @@
 filter:
   sets:
     # keep: [XCoreVAlu]
-    drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode, XCoreVSimd]
+    # drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode, XCoreVSimd]
+    drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode]
+    # drop: [RISCVBase, RISCVEncoding, Zicsr, Zifencei, RVSMode, RVDebug, RV32I, RVNMode, RV32Zpsfoperand]
   instructions:
     # keep: [CV_ABS, CV_ADD_B]
-    drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR]
+    drop: [CV_CLIPU, CV_CLIPR, CV_CLIPUR, CV_SLET, CV_SLETU]
   opcodes:
-    keep: [custom-0, custom-1, custom-2 ,custom-3, 0b00000]
+    keep: [custom-0, custom-1, custom-2 ,custom-3, 0b00000, OP-P, OP]
   encoding_sizes:
     keep: [32]

examples/cfg/patches.yml

@@ -15,7 +15,9 @@ patches:
     # file: gitlab_ci.patch
     # file: llvm/gitlab_ci.patch
     # file: /absolute/path/to/gitlab_ci.patch
-  - name: insert_markers_llvm17
+  # - name: insert_markers_llvm17
+  - name: insert_markers_llvm18
+  # TODO:  automatially select patch depending on llvm version
   # generated patch (TODO: implement)
   # - name: ???
   #   target: llvm

examples/cfg/riscv.yml

@@ -0,0 +1,76 @@
+---
+riscv:
+  xlen: 32
+  features:
+  - m
+  - fast-unaligned-access
+  legalization:
+    gisel:
+      ops:
+      # TODO: simd shift?
+      # TODO: rotate left/right?
+      # - name: [G_SMAX, G_UMAX, G_SMIN, G_UMIN, G_ABS]
+      #   types: [s32]
+      #   onlyif: [HasVendorXCValu]
+      # - name: [G_ADD, G_SUB, G_AND, G_OR, G_XOR, G_ASHR, G_LSHR, G_SHL]
+      #   types: [v4i8, v2i16]
+      #   onlyif: [HasVendorXCVsimd]
+      # - name: G_INSERT_VECTOR_ELT
+      #   types: [v4i8, v2i16]
+      #   onlyif: [HasVendorXCVsimd]
+      # - name: [G_ADD]
+      #   types: [v4i8, v2i16]
+      #   onlyif: [HasExtmyextsimd]
+      - name: [G_ADD]
+        types: [s16, s32]
+        onlyif: [HasExtmyextalu]
+      # - name: [G_ADD, G_SMAX]
+      #   types: [v4i8, v2i16]
+      #   onlyif: [HasExtRV32Zpn]
+      # - name: [G_SHL, G_SMIN, G_SUB]
+      #   types: [v4i8]
+      #   onlyif: [HasExtRV32Zpn]
+      # - name: [G_SMIN, G_SMAX]  # TODO: CLZ, REV, CMIX
+      #   types: [s32]
+      #   onlyif: [HasExtRV32Zbpo]
+      # # TODO: RV32Zpsfoperand (register pairs)
+      # TODO: G_BITCAST
+  transform_info:
+    shouldFoldTerminatingConditionAfterLSR: true
+    prefersVectorizedAddressing: false
+    enableInterleavedAccessVectorization: true
+    enableMaskedInterleavedAccessVectorization: null
+    enableScalableVectorization: false
+    preferEpilogueVectorization: null
+    supportsScalableVectors: false
+    # getInliningThresholdMultiplier: ?
+    # getInliningCostBenefitAnalysisSavingsMultiplier: ?
+    # getInliningCostBenefitAnalysisProfitableMultiplier: ?
+    # getInlinerVectorBonusPercent: ?
+    # getFlatAddressSpace: ?
+    # getMinVectorRegisterBitWidth: ?
+    # getCacheLineSize: ?
+    # getPrefetchDistance: ?
+    # getMaxPrefetchIterationsAhead: ?
+    # getMaxMemIntrinsicInlineSizeThreshold: ?
+    # getAtomicMemIntrinsicMaxElementSize: ?
+    # getMaxNumArgs: ?
+    # getGISelRematGlobalCost: ?
+    # getMinTripCountTailFoldingThreshold: ?
+    # getMaxVScale: ?
+    # getVScaleForTuning: ?
+    # getPredictableBranchThreshold: ?
+    # isSingleThreaded: ?
+    # isNumRegsMajorCostOfLSR: ?
+    # canMacroFuseCmp: ?
+    # enableOrderedReductions: ?
+    # LSRWithInstrQueries: ?
+    # useAA: ?
+    # shouldBuildLookupTables: ?
+    # shouldBuildRelLookupTables: ?
+    # supportsEfficientVectorElementLoadStore: ?
+    # supportsTailCalls: ?
+    # enableSelectOptimize: ?
+    # isFPVectorizationPotentiallyUnsafe: ?
+    # isVScaleKnownToBeAPowerOfTwo: ?
+    # enableWritePrefetching: ?

examples/cfg/tests.yml

@@ -0,0 +1,5 @@
+---
+test:
+  paths: []
+  # - MC/RISCV
+  #   - CodeGen/RISCV

examples/cfg/xcorev/XCoreVAlu.yml

@@ -1,9 +1,16 @@
 ---
 extensions:
   XCoreVAlu:
-    feature: XCVAlu
+    feature: XCValu
     arch: xcvalu
     version: "1.0"
     experimental: false
     vendor: true
     # patches: []
+passes:
+  per_model:
+    XCoreVAlu:
+      skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat]
+      override:
+        behav_to_pat:
+          patterns: false

examples/cfg/xcorev/XCoreVBitmanip.yml

@@ -1,9 +1,16 @@
 ---
 extensions:
   XCoreVBitmanip:
-    feature: XCVBitmanip
+    feature: XCVbitmanip
     arch: xcvbitmanip
     version: "1.0"
     experimental: false
     vendor: true
     # patches: []
+passes:
+  per_model:
+    XCoreVBitmanip:
+      skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat]
+      override:
+        behav_to_pat:
+          patterns: false

examples/cfg/xcorev/XCoreVBranchImmediate.yml

@@ -1,9 +1,16 @@
 ---
 extensions:
   XCoreVBranchImmediate:
-    feature: XCVBi
+    feature: XCVbi
     arch: xcvbi
     version: "1.0"
     experimental: false
     vendor: true
     # patches: []
+passes:
+  per_model:
+    XCoreVBranchImmediate:
+      skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat]
+      override:
+        behav_to_pat:
+          patterns: false

examples/cfg/xcorev/XCoreVMac.yml

@@ -1,9 +1,16 @@
 ---
 extensions:
   XCoreVMac:
-    feature: XCVMac
+    feature: XCVmac
     arch: xcvmac
     version: "1.0"
     experimental: false
     vendor: true
     # patches: []
+passes:
+  per_model:
+    XCoreVMac:
+      skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat]
+      override:
+        behav_to_pat:
+          patterns: false

examples/cfg/xcorev/XCoreVMem.yml

@@ -1,9 +1,16 @@
 ---
 extensions:
   XCoreVMem:
-    feature: XCVMem
+    feature: XCVmem
     arch: xcvmem
     version: "1.0"
     experimental: false
     vendor: true
     # patches: []
+passes:
+  per_model:
+    XCoreVMem:
+      skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat]
+      override:
+        behav_to_pat:
+          patterns: false

examples/cfg/xcorev/XCoreVSimd.yml

@@ -1,9 +1,16 @@
 ---
 extensions:
   XCoreVSimd:
-    feature: XCVSimd
+    feature: XCVsimd
     arch: xcvsimd
     version: "1.0"
     experimental: false
     vendor: true
     # patches: []
+passes:
+  per_model:
+    XCoreVSimd:
+      skip: [riscv_features, riscv_isa_info, riscv_instr_formats, riscv_instr_info, behav_to_pat]
+      override:
+        behav_to_pat:
+          patterns: false

examples/demo.py

@@ -34,38 +34,38 @@
 # VERBOSE = True
 # FAST = False
 FAST = True
+SKIP_PATTERNS = False
+# SKIP_PATTERNS = True
+INTERACTIVE = False
 
 
 seal5_flow = Seal5Flow("/tmp/seal5_llvm_demo", "demo")
 
+# Optional: clean existing settings/models for fresh run
+seal5_flow.reset(settings=True, interactive=False)
+seal5_flow.clean(temp=True, patches=True, models=True, inputs=True, interactive=INTERACTIVE)
+
 # Clone LLVM and init seal5 metadata directory
 seal5_flow.initialize(
     clone=True,
     clone_url="https://github.com/llvm/llvm-project.git",
-    clone_ref="llvmorg-17.0.6",
+    # clone_ref="llvmorg-17.0.6",
+    clone_ref="llvmorg-18.1.0-rc3",
     force=True,
     verbose=VERBOSE,
 )
 
-# Optional: clean existing settings/models for fresh run
-seal5_flow.reset(settings=True, interactive=False)
-
-# Clone Seal5 dependencies
-# 1. M2-ISA-R (frontend only)
-# 2. CDSL2LLVM (later)
-# TODO: refresh refs
-seal5_flow.setup(force=True, verbose=VERBOSE)
-
 # Load CoreDSL inputs
 cdsl_files = [
     # XCOREV
     EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMac.core_desc",
     EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVAlu.core_desc",
-    EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBitmanip.core_desc",
-    EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVSimd.core_desc",
-    EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMem.core_desc",
-    EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBranchImmediate.core_desc",
+    # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBitmanip.core_desc",
+    # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVSimd.core_desc",
+    # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVMem.core_desc",
+    # EXAMPLES_DIR / "cdsl" / "rv_xcorev" / "XCoreVBranchImmediate.core_desc",
     # RVP (will not work)
+    # EXAMPLES_DIR / "cdsl" / "RV32P.core_desc",
     # EXAMPLES_DIR / "cdsl" / "RVP.core_desc",
     # S4E (untested) -> undefined XLEN
     # EXAMPLES_DIR / "cdsl" / "rv_s4e" / "s4e-mac.core_desc",
@@ -78,26 +78,43 @@
 ]
 seal5_flow.load(cdsl_files, verbose=VERBOSE, overwrite=True)
 
+# Load test inputs
+test_files = [
+    # EXAMPLES_DIR / "tests" / "xcorev" / "cv_abs.test.c",
+    EXAMPLES_DIR / "tests" / "cv_nand" / "cv_nand.c",
+    EXAMPLES_DIR / "tests" / "cv_nand" / "cv_nand.s",
+    EXAMPLES_DIR / "tests" / "cv_nand" / "cv_nand_invalid.s",
+    # TODO: support subdirectories to avoid duplicate test names (WARN!)
+    # EXAMPLES_DIR / "tests" / "cv_nand" / "*.c",  # TODO: support glob patterns
+]
+seal5_flow.load(test_files, verbose=VERBOSE, overwrite=True)
+
 # Load YAML inputs
 cfg_files = [
     # XCOREV
     EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMac.yml",
     EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVAlu.yml",
-    EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBitmanip.yml",
-    EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVSimd.yml",
-    EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMem.yml",
-    EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBranchImmediate.yml",
+    # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBitmanip.yml",
+    # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVSimd.yml",
+    # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVMem.yml",
+    # EXAMPLES_DIR / "cfg" / "xcorev" / "XCoreVBranchImmediate.yml",
     # S4E
     # TUMEDA
     # GENERATED
     # OTHERS
     EXAMPLES_DIR / "cfg" / "llvm.yml",
     EXAMPLES_DIR / "cfg" / "filter.yml",
     EXAMPLES_DIR / "cfg" / "patches.yml",
+    EXAMPLES_DIR / "cfg" / "riscv.yml",
+    EXAMPLES_DIR / "cfg" / "tests.yml",
     EXAMPLES_DIR / "cfg" / "git.yml",
 ]
 seal5_flow.load(cfg_files, verbose=VERBOSE, overwrite=False)
 
+# Clone & install Seal5 dependencies
+# 1. CDSL2LLVM (add PHASE_0 patches)
+seal5_flow.setup(force=True, verbose=VERBOSE)
+
 # Apply initial patches
 seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_0])
 
@@ -111,11 +128,25 @@
 #   3. Analyse/optimize instructions
 seal5_flow.transform(verbose=VERBOSE)
 
-# Generate patches
-seal5_flow.generate(verbose=VERBOSE)
+# Generate patches (except Patterns)
+seal5_flow.generate(verbose=VERBOSE, skip=["pattern_gen"])
+
+# Apply next patches
+seal5_flow.patch(verbose=VERBOSE, stages=[PatchStage.PHASE_1, PatchStage.PHASE_2])
+
+if not FAST:
+    # Build patched LLVM
+    seal5_flow.build(verbose=VERBOSE, config="release")
+if not SKIP_PATTERNS:
+    # Build PatternGen & llc
+    seal5_flow.build(verbose=VERBOSE, config="release", target="pattern-gen")
+    seal5_flow.build(verbose=VERBOSE, config="release", target="llc")
+
+    # Generate remaining patches
+    seal5_flow.generate(verbose=VERBOSE, only=["pattern_gen"])
 
-# Apply patches
-seal5_flow.patch(verbose=VERBOSE)
+    # Apply patches
+    seal5_flow.patch(verbose=VERBOSE)
 
 # Build patched LLVM
 seal5_flow.build(verbose=VERBOSE, config="release")
@@ -130,4 +161,4 @@
 seal5_flow.export("/tmp/seal5_llvm_demo.tar.gz", verbose=VERBOSE)
 
 # Optional: cleanup temorary files, build dirs,...
-# seal5.cleanup(temp=True, build=True, deps=True, force=True)
+# seal5.clean(temp=True, build=True, deps=True, interactive=INTERACTIVE)

examples/tests/cv_nand/cv_nand.c

@@ -0,0 +1,16 @@
+// RUN: clang -cc1 -triple riscv32 -target-feature +m -target-feature +xcorevnand -mllvm -global-isel=1 -S -O3 %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=CHECK
+
+// CHECK-LABEL: nand_bitwise_s32:
+// CHECK-COUNT-1: cv.nand.bitwise {{.*}}
+signed int nand_bitwise_s32(signed int a, signed int b)
+{
+  return ~(a & b);
+}
+
+// CHECK-LABEL: nand_bitwise_u32:
+// CHECK-COUNT-1: cv.nand.bitwise {{.*}}
+unsigned int nand_bitwise_u32(unsigned int a, unsigned int b)
+{
+  return ~(a & b);
+}