From 7f516bbd0301f042c116edc75f0e8a3ebd1ead79 Mon Sep 17 00:00:00 2001 From: Subash Kannoth Date: Thu, 23 Jun 2016 15:40:06 +0200 Subject: [PATCH 01/12] Add : Bankwise split. 1)Implement energy split up to each memory banks for the below components. act_energy pre_energy read_energy write_energy pre_stdby_energy act_stdby_energy 2) Configuration options "-o " and "-f " replaced by "-b ". The vendor specific power offset factor rho can be specified CLI argument -b . 3) Updated the LibDRAMPower library with the latest feature. 4) Added specs for SAMSUNG K4B1G1646E 1Gb DDR3-1600 16bit device. 5) Improved README description. --- README.md | 12 +-- ...SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml | 55 ++++++++++++ src/CommandAnalysis.cc | 53 ++++++++++- src/CommandAnalysis.h | 10 ++- src/MemoryPowerModel.cc | 88 ++++++++++++++++--- src/MemoryPowerModel.h | 17 +++- src/cli/drampower.cc | 41 +++++++-- src/libdrampower/LibDRAMPower.cc | 10 ++- src/libdrampower/LibDRAMPower.h | 6 +- 9 files changed, 253 insertions(+), 39 deletions(-) create mode 100644 memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml diff --git a/README.md b/README.md index 5d6eb6e8..b3396201 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ The master branch of the repository should be regarded as the bleeding-edge vers ## 1. Installation -Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. src/cli/drampower.cc file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: +Clone the repository, or download the zip file of the release you would like to use. The source code is available in src folder. [drampower.cc](src/cli/drampower.cc) file gives the user interface, where the user can specify the memory to be employed and the command/transaction trace to be analyzed. To build, use: ```bash make -j4 ``` @@ -36,7 +36,7 @@ An example is given in ```traces/commands.trace``` The format it uses is: ```,,```. For example, "500,ACT,2", where ACT is the command and 2 is the bank. Timestamp is in clock cycles (cc), the list of supported commands is -mentioned in src/MemCommand.h and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be +mentioned in [MemCommand.h](src/MemCommand.h) and the bank is the target bank number. For non-bank-specific commands, bank can be set to 0. Rank need not be specified. The timing correctness of the trace is not verified by the tool and is assumed to be accurate. However, warning messages are provided, to identify if the memory or bank state is inconsistent in the trace. A sample command trace is provided in the traces/ folder. ### Transaction Traces @@ -53,7 +53,7 @@ Four sample MediaBench application transaction traces have been provided. The Me ## 5. Usage -src/cli/drampower.cc is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. +[drampower.cc](src/cli/drampower.cc) is the main interface file, which accepts user inputs to specify memory to be employed and the command or transaction trace to be analyzed. If the transaction trace (DRAM command scheduler) is being used, the users can specify the degree of bank interleaving required, the request size and the use of power-down or self-refresh options. Also, for DDR4 memories bank group interleaving can be specified. Dual-rank DRAMs are not yet supported by the command scheduler. Note: Speculative use of power-down or self-refresh modes will increase the trace length due to the power-up latencies of these power-saving modes. To use DRAMPower at the command-level (command trace), after make, use the following: ```bash @@ -108,7 +108,7 @@ To include these XMLs in your simulations, simply use them as the target memory. ## 8. Example Usage An example of using this tool is provided below. To compile the example, -use the Makefile and make sure the Gcc and Xerces-c are installed. Then, run: +use the Makefile and make sure the gcc and Xerces-c are installed. Then, run: ``` make -j4 ``` @@ -242,9 +242,9 @@ It also reports the simulation start/end times and the total simulation time in ## 9. DRAMPower Library The DRAMPower tool has an additional feature and can be used as a library. -In order to use the library run "make lib", include src/libdrampower/LibDRAMPower.h in your project and +In order to use the library run "make lib", include [LibDRAMPower.h](src/libdrampower/LibDRAMPower.h) in your project and link the file src/libdrampower.a with your project. -An example for the usuage of the library can be found in the folder test/libdrampowertest/lib_test.cc +An example for the usuage of the library can be found in the folder [lib_test.cc](test/libdrampowertest/lib_test.cc). ## 10. Authors & Acknowledgment diff --git a/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml b/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml new file mode 100644 index 00000000..69571b2b --- /dev/null +++ b/memspecs/SAMSUNG_K4B1G1646E_1Gb_DDR3-1600_16bit.xml @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/CommandAnalysis.cc b/src/CommandAnalysis.cc index e557c292..4241d926 100644 --- a/src/CommandAnalysis.cc +++ b/src/CommandAnalysis.cc @@ -31,7 +31,7 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji, Sven Goossens + * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji, Sven Goossens, Subash Kannoth, Eder Zulian * */ @@ -57,6 +57,14 @@ bool commandSorter(const MemCommand& i, const MemCommand& j) CommandAnalysis::CommandAnalysis(const int64_t nbrofBanks) { // Initializing all counters and variables + numberofactsBanks.assign(static_cast(nbrofBanks), 0); + numberofpresBanks.assign(static_cast(nbrofBanks), 0); + numberofreadsBanks.assign(static_cast(nbrofBanks), 0); + numberofwritesBanks.assign(static_cast(nbrofBanks), 0); + actcyclesBanks.assign(static_cast(nbrofBanks), 0); + + first_act_cycle_banks.resize(static_cast(nbrofBanks), 0); + clearStats(0); zero = 0; @@ -68,11 +76,17 @@ CommandAnalysis::CommandAnalysis(const int64_t nbrofBanks) cmd_list.clear(); cached_cmd.clear(); activation_cycle.resize(static_cast(nbrofBanks), 0); + num_banks = nbrofBanks; } // function to clear counters void CommandAnalysis::clearStats(const int64_t timestamp) { + std::fill(numberofactsBanks.begin(), numberofactsBanks.end(), 0); + std::fill(numberofpresBanks.begin(), numberofpresBanks.end(), 0); + std::fill(numberofreadsBanks.begin(), numberofreadsBanks.end(), 0); + std::fill(numberofwritesBanks.begin(), numberofwritesBanks.end(), 0); + std::fill(actcyclesBanks.begin(), actcyclesBanks.end(), 0); numberofacts = 0; numberofpres = 0; @@ -104,6 +118,7 @@ void CommandAnalysis::clearStats(const int64_t timestamp) // reset count references to timestamp so that they are moved // to start of next stats generation + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); first_act_cycle = timestamp; last_pre_cycle = timestamp; pdn_cycle = timestamp; @@ -217,8 +232,11 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // target bank, first and latest activation cycle and the memory // state. Update the number of precharged/idle-precharged cycles. numberofacts++; + numberofactsBanks[bank]++; if (bankstate[static_cast(bank)] == 1) { printWarning("Bank is already active!", type, timestamp, bank); + } else { + first_act_cycle_banks[bank] = timestamp; } bankstate[static_cast(bank)] = 1; if (num_active_banks == 0) { @@ -236,6 +254,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, printWarning("Bank is not active!", type, timestamp, bank); } numberofreads++; + numberofreadsBanks[bank]++; idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); latest_read_cycle = timestamp; @@ -247,6 +266,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, printWarning("Bank is not active!", type, timestamp, bank); } numberofwrites++; + numberofwritesBanks[bank]++; idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); latest_write_cycle = timestamp; @@ -261,11 +281,16 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, numberofrefs++; idle_pre_update(memSpec, timestamp, latest_pre_cycle); first_act_cycle = timestamp; + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); precycles += max(zero, timestamp - last_pre_cycle); last_pre_cycle = timestamp + memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; latest_pre_cycle = last_pre_cycle; actcycles += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + for (auto &e : actcyclesBanks) { + e += memSpec.memTimingSpec.RFC - memSpec.memTimingSpec.RP; + } + num_active_banks = 0; for (auto& b : bankstate) { b = 0; @@ -280,6 +305,8 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // Update memory state if needed. if (bankstate[static_cast(bank)] == 1) { numberofpres++; + numberofpresBanks[bank]++; + actcyclesBanks[bank] += max(zero, timestamp - first_act_cycle_banks[bank]); } bankstate[static_cast(bank)] = 0; @@ -307,10 +334,16 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // Calculate the number of active cycles if the memory was in the // active state before, but there is a state transition to PRE now. // If not, update the number of precharged cycles and idle cycles. - numberofpres += num_active_banks; + numberofpres += num_active_banks; + numberofpresBanks[bank] += num_active_banks; if (num_active_banks > 0) { actcycles += max(zero, timestamp - first_act_cycle); + for (int i = 0; i < num_banks; i++) { + if (bankstate[static_cast(i)] == 1) { + actcyclesBanks[i] += max(zero, timestamp - first_act_cycle_banks[i]); + } + } idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); } else if (num_active_banks == 0) { @@ -337,6 +370,11 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, last_states = bankstate; pdn_cycle = timestamp; actcycles += max(zero, timestamp - first_act_cycle); + for (int i = 0; i < num_banks; i++) { + if (bankstate[static_cast(i)] == 1) { + actcyclesBanks[i] += max(zero, timestamp - first_act_cycle_banks[i]); + } + } idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); mem_state = CommandAnalysis::MS_PDN_F_ACT; @@ -351,6 +389,11 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, last_states = bankstate; pdn_cycle = timestamp; actcycles += max(zero, timestamp - first_act_cycle); + for (int i = 0; i < num_banks; i++) { + if (bankstate[static_cast(i)] == 1) { + actcyclesBanks[i] += max(zero, timestamp - first_act_cycle_banks[i]); + } + } idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); mem_state = CommandAnalysis::MS_PDN_S_ACT; @@ -410,6 +453,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, num_active_banks += static_cast(a); } first_act_cycle = timestamp; + std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp); } else if (type == MemCommand::PUP_PRE) { // If command is power-up in the precharged mode - check the power-down // exit-mode employed (fast or slow), update the number of power-down @@ -526,6 +570,11 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, } else if (type == MemCommand::END || type == MemCommand::NOP) { // May be optionally used at the end of memory trace for better accuracy // Update all counters based on completion of operations. + for (int i = 0; i < num_banks; i++) { + if (bankstate[static_cast(i)] == 1) { + actcyclesBanks[i] += max(zero, timestamp - first_act_cycle_banks[i]); + } + } if (num_active_banks > 0 && mem_state == 0) { actcycles += max(zero, timestamp - first_act_cycle); idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, diff --git a/src/CommandAnalysis.h b/src/CommandAnalysis.h index 15261fb2..cb204383 100644 --- a/src/CommandAnalysis.h +++ b/src/CommandAnalysis.h @@ -31,7 +31,7 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji + * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji, Subash Kannoth, Eder Zulian * */ @@ -63,18 +63,23 @@ class CommandAnalysis { // Number of activate commands int64_t numberofacts; + std::vector numberofactsBanks; // Number of precharge commands int64_t numberofpres; + std::vector numberofpresBanks; // Number of reads commands int64_t numberofreads; + std::vector numberofreadsBanks; // Number of writes commands int64_t numberofwrites; + std::vector numberofwritesBanks; // Number of refresh commands int64_t numberofrefs; // Number of precharge cycles int64_t precycles; // Number of active cycles int64_t actcycles; + std::vector actcyclesBanks; // Number of Idle cycles in the active state int64_t idlecycles_act; // Number of Idle cycles in the precharge state @@ -167,8 +172,11 @@ class CommandAnalysis { unsigned mem_state; unsigned num_active_banks; + int64_t num_banks; + // Clock cycle of first activate command when memory state changes to ACT int64_t first_act_cycle; + std::vector first_act_cycle_banks; // Clock cycle of last precharge command when memory state changes to PRE int64_t last_pre_cycle; diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index e020830e..99327417 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -31,7 +31,7 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji + * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji, Subash Kannoth, Eder Zulian * */ @@ -41,7 +41,7 @@ #include // For pow #include // fmtflags - +#include using namespace std; using namespace Data; @@ -50,11 +50,20 @@ using namespace Data; void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, const CommandAnalysis& c, - int term) + int term, bool bankwiseMode, + int64_t bwPowerFactor) { const MemTimingSpec& t = memSpec.memTimingSpec; const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; const MemPowerSpec& mps = memSpec.memPowerSpec; + const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks; + + energy.act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.read_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.write_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.act_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pre_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.act_energy = 0.0; energy.pre_energy = 0.0; @@ -153,6 +162,21 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.ref_energy = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd5 - mps.idd3n); energy.pre_stdby_energy = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n); energy.act_stdby_energy = vdd0Domain.calcTivEnergy(c.actcycles, mps.idd3n); + + // Using the number of cycles that at least one bank is active here + // But the current iddrho is less than idd3n + double iddrho = (static_cast(bwPowerFactor) / 100.0) * (mps.idd3n - mps.idd2n) + mps.idd2n; + double eshared = vdd0Domain.calcTivEnergy(c.actcycles, iddrho); + + for (int i = 0; i < nbrofBanks; i++) { + energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - mps.idd3n); + energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RC - t.RAS), mps.idd0 - mps.idd2n); + energy.read_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofreadsBanks[i] * burstCc, mps.idd4r - mps.idd3n); + energy.write_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofwritesBanks[i] * burstCc, mps.idd4w - mps.idd3n); + energy.pre_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n) / static_cast(nbrofBanks); + energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho)) / static_cast(nbrofBanks); + } + // Idle energy in the active standby clock cycles energy.idle_energy_act = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n); // Idle energy in the precharge standby clock cycles @@ -200,6 +224,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.ref_energy += vdd2Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd52 - mps.idd3n2); energy.pre_stdby_energy += vdd2Domain.calcTivEnergy(c.precycles, mps.idd2n2); energy.act_stdby_energy += vdd2Domain.calcTivEnergy(c.actcycles, mps.idd3n2); + // Idle energy in the active standby clock cycles energy.idle_energy_act += vdd2Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n2); // Idle energy in the precharge standby clock cycles @@ -243,28 +268,52 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // adding all energy components for the active rank and all background and idle // energy components for both ranks (in a dual-rank system) - energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + - energy.write_energy + energy.ref_energy + energy.io_term_energy + - static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + - energy.pre_stdby_energy + energy.sref_energy + - energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy - + energy.s_pre_pd_energy + energy.sref_ref_energy + energy.spup_ref_energy); + if (bankwiseMode) { + energy.total_energy = total(energy.act_energy_banks) + total(energy.pre_energy_banks) + total(energy.read_energy_banks) + + total(energy.write_energy_banks) + energy.ref_energy + energy.io_term_energy + + static_cast(memArchSpec.nbrOfRanks) * ( (eshared + total(energy.act_stdby_energy_banks)) + + energy.pre_stdby_energy + energy.sref_energy + + energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy + + energy.s_pre_pd_energy + energy.sref_ref_energy + energy.spup_ref_energy); + } else { + energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + + energy.write_energy + energy.ref_energy + energy.io_term_energy + + static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + + energy.pre_stdby_energy + energy.sref_energy + + energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy + + energy.s_pre_pd_energy + energy.sref_ref_energy + energy.spup_ref_energy); + } // Calculate the average power consumption power.average_power = energy.total_energy / (static_cast(total_cycles) * t.clkPeriod); } // MemoryPowerModel::power_calc -void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, const CommandAnalysis& c) const +void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, const CommandAnalysis& c, bool bankwiseMode) const { const MemTimingSpec& memTimingSpec = memSpec.memTimingSpec; const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; const uint64_t nRanks = static_cast(memArchSpec.nbrOfRanks); const char eUnit[] = " pJ"; + const int64_t nbrofBanks = memSpec.memArchSpec.nbrOfBanks; + double nRanksDouble = static_cast(nRanks); ios_base::fmtflags flags = cout.flags(); streamsize precision = cout.precision(); cout.precision(0); - cout << "* Trace Details:" << fixed << endl + + if (bankwiseMode) { + cout << endl << "* Bankwise Details:"; + for (int i = 0; i < nbrofBanks; i++) { + cout << endl << "## @ Bank " << i << fixed + << endl << " #ACT commands: " << c.numberofactsBanks[i] + << endl << " #RD + #RDA commands: " << c.numberofreadsBanks[i] + << endl << " #WR + #WRA commands: " << c.numberofwritesBanks[i] + << endl << " #PRE (+ PREA) commands: " << c.numberofpresBanks[i]; + } + cout << endl; + } + + cout << endl << "* Trace Details:" << fixed << endl << endl << "#ACT commands: " << c.numberofacts << endl << "#RD + #RDA commands: " << c.numberofreads << endl << "#WR + #WRA commands: " << c.numberofwrites @@ -300,6 +349,20 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << "Total Trace Length (clock cycles): " << total_cycles << endl << "----------------------------------------" << endl; + if (bankwiseMode) { + cout << endl << "* Bankwise Details:"; + for (int i = 0; i < nbrofBanks; i++) { + cout << endl << "## @ Bank " << i << fixed + << endl << " ACT Cmd Energy: " << energy.act_energy_banks[i] << eUnit + << endl << " PRE Cmd Energy: " << energy.pre_energy_banks[i] << eUnit + << endl << " RD Cmd Energy: " << energy.read_energy_banks[i] << eUnit + << endl << " WR Cmd Energy: " << energy.write_energy_banks[i] << eUnit + << endl << " ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy_banks[i] << eUnit + << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit; + } + cout << endl; + } + cout.precision(2); cout << endl << "* Trace Power and Energy Estimates:" << endl << endl << "ACT Cmd Energy: " << energy.act_energy << eUnit @@ -320,8 +383,6 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, } } - double nRanksDouble = static_cast(nRanks); - cout << "ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy << eUnit << endl << " Active Idle Energy: " << nRanksDouble * energy.idle_energy_act << eUnit << endl << " Active Power-Up Energy: " << nRanksDouble * energy.pup_act_energy << eUnit @@ -397,3 +458,4 @@ double EnergyDomain::calcTivEnergy(int64_t cycles, double current) const { return static_cast(cycles) * clkPeriod * current * voltage; } + diff --git a/src/MemoryPowerModel.h b/src/MemoryPowerModel.h index 2b230498..368ccfa3 100644 --- a/src/MemoryPowerModel.h +++ b/src/MemoryPowerModel.h @@ -31,13 +31,14 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji + * Authors: Karthik Chandrasekar, Matthias Jung, Omar Naji, Subash Kannoth, Eder Zulian * */ #ifndef MEMORY_POWER_MODEL_H #define MEMORY_POWER_MODEL_H +#include #include "MemorySpecification.h" #include "CommandAnalysis.h" @@ -48,7 +49,8 @@ class MemoryPowerModel { // command trace void power_calc(const MemorySpecification& memSpec, const CommandAnalysis& c, - int term); + int term, bool bankwiseMode, + int64_t bwPowerFactor); // Used to calculate self-refresh active energy static double engy_sref(double idd6, @@ -67,24 +69,30 @@ class MemoryPowerModel { struct Energy { // Total energy of all activates double act_energy; + std::vector act_energy_banks; // Total energy of all precharges double pre_energy; + std::vector pre_energy_banks; // Total energy of all reads double read_energy; + std::vector read_energy_banks; // Total energy of all writes double write_energy; + std::vector write_energy_banks; // Total energy of all refreshes double ref_energy; // Total background energy of all active standby cycles double act_stdby_energy; + std::vector act_stdby_energy_banks; // Total background energy of all precharge standby cycles double pre_stdby_energy; + std::vector pre_stdby_energy_banks; // Total energy of idle cycles in the active mode double idle_energy_act; @@ -147,7 +155,8 @@ class MemoryPowerModel { // Print the power and energy void power_print(const MemorySpecification& memSpec, int term, - const CommandAnalysis& c) const; + const CommandAnalysis& c, + bool bankwiseMode) const; // To derive IO and Termination Power measures using DRAM specification void io_term_power(const MemorySpecification& memSpec); @@ -157,6 +166,8 @@ class MemoryPowerModel { private: double calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const; + // Sum quantities (e.g., operations, energy, cycles) that are stored in a per bank basis returning the total amount. + template T total(const std::vector vec) const { return std::accumulate(vec.begin(), vec.end(), static_cast(0)); } }; class EnergyDomain { diff --git a/src/cli/drampower.cc b/src/cli/drampower.cc index 57c35d8b..81c53266 100644 --- a/src/cli/drampower.cc +++ b/src/cli/drampower.cc @@ -31,7 +31,7 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Karthik Chandrasekar, Omar Naji + * Authors: Karthik Chandrasekar, Omar Naji, Subash Kannoth, Eder Zulian, Matthias Jung * */ #include @@ -50,17 +50,23 @@ using namespace std; int error() { - cout << "Correct Usage: \n./drampower -m " - "[-t] [-c] [-i] " - " [-g] [-s] [-r] " - "[-p] < 1 - Power-Down, 2 - Self-Refresh>\n"; + cout << "Correct Usage: \n./drampower -m " << + "[-t] " << + "[-c] " << + "[-i] " << + "[-g] " << + "[-s] " << + "[-r] " << + "[-p] <1 - Power-Down, 2 - Self-Refresh> " << + "[-b] \n"; return 1; } int main(int argc, char* argv[]) { int trans = 0, cmds = 0, memory = 0, size = 0, term = 0, power_down = 0; + bool bankwiseMode = false; + unsigned bankwisePowerFactor = 100; char* src_trans = { 0 }; char* src_cmds = { 0 }; @@ -88,6 +94,9 @@ int main(int argc, char* argv[]) size = 1; } else if (string(argv[i]) == "-p") { power_down = atoi(argv[i + 1]); + } else if (string(argv[i]) == "-b") { + bankwiseMode = true; + bankwisePowerFactor = atoi(argv[i + 1]); } else { if (string(argv[i]) == "-r") { term = 1; @@ -102,6 +111,11 @@ int main(int argc, char* argv[]) } } + if (bankwisePowerFactor > 100) { + cout << endl << "Bankwise power offset factor out of range." << endl; + return error(); + } + if (memory == 0) { cout << endl << "No DRAM memory specified!" << endl; return error(); @@ -129,6 +143,11 @@ int main(int argc, char* argv[]) MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + if ((memArchSpec.twoVoltageDomains) && (bankwiseMode)){ + cout << endl << "Bankwise simulation for Two-Voltage domain devices not supported." << endl; + return error(); + } + if (interleaving > memArchSpec.nbrOfBanks) { cout << "Interleaving > Number of Banks" << endl; return error(); @@ -174,15 +193,21 @@ int main(int argc, char* argv[]) tm* starttm = localtime(&start); cout << "* Analysis start time: " << asctime(starttm); cout << "* Analyzing the input trace" << endl; + cout << "* Bankwise mode: "; + if (bankwiseMode) { + cout << "enabled (power offset factor is " << bankwisePowerFactor << "%)" << endl; + } else { + cout << "disabled" << endl; + } // Calculates average power consumption and energy for the input memory // command trace const int CMD_ANALYSIS_WINDOW_SIZE = 1000000; TraceParser traceparser(memSpec.memArchSpec.nbrOfBanks); traceparser.parseFile(memSpec, trace_file, CMD_ANALYSIS_WINDOW_SIZE, grouping, interleaving, burst, power_down, trans); - mpm.power_calc(memSpec, traceparser.counters, term); + mpm.power_calc(memSpec, traceparser.counters, term, bankwiseMode, bankwisePowerFactor); - mpm.power_print(memSpec, term, traceparser.counters); + mpm.power_print(memSpec, term, traceparser.counters, bankwiseMode); time_t end = time(0); tm* endtm = localtime(&end); cout << "* Power Computation End time: " << asctime(endtm); diff --git a/src/libdrampower/LibDRAMPower.cc b/src/libdrampower/LibDRAMPower.cc index 47ed15a9..e28fc608 100644 --- a/src/libdrampower/LibDRAMPower.cc +++ b/src/libdrampower/LibDRAMPower.cc @@ -31,7 +31,7 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Matthias Jung, Omar Naji + * Authors: Matthias Jung, Omar Naji, Subash Kannoth, Eder Zulian, Matthias Jung * */ @@ -39,10 +39,12 @@ using namespace Data; -libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination) : +libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination, bool bankwiseMode, int64_t bankwisePowerFactor) : memSpec(memSpec), counters(CommandAnalysis(memSpec.memArchSpec.nbrOfBanks)), - includeIoAndTermination(includeIoAndTermination) + includeIoAndTermination(includeIoAndTermination), + bankwiseMode(bankwiseMode), + bankwisePowerFactor(bankwisePowerFactor) { } @@ -64,7 +66,7 @@ void libDRAMPower::updateCounters(bool lastUpdate) void libDRAMPower::calcEnergy() { - mpm.power_calc(memSpec, counters, includeIoAndTermination); + mpm.power_calc(memSpec, counters, includeIoAndTermination, bankwiseMode, bankwisePowerFactor); } void libDRAMPower::clearState() diff --git a/src/libdrampower/LibDRAMPower.h b/src/libdrampower/LibDRAMPower.h index 4d9ccefe..7fb3a2df 100644 --- a/src/libdrampower/LibDRAMPower.h +++ b/src/libdrampower/LibDRAMPower.h @@ -31,7 +31,7 @@ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * Authors: Matthias Jung, Omar Naji + * Authors: Matthias Jung, Omar Naji, Subash Kannoth, Eder Zulian, Matthias Jung * */ @@ -47,7 +47,7 @@ class libDRAMPower { public: - libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination); + libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination, bool bankwiseMode = false, int64_t bankwisePowerFactor = 100); ~libDRAMPower(); void doCommand(Data::MemCommand::cmds type, @@ -73,6 +73,8 @@ class libDRAMPower { Data::CommandAnalysis counters; private: bool includeIoAndTermination; + bool bankwiseMode; + int64_t bankwisePowerFactor; // Object of MemoryPowerModel which contains the results // Energies(pJ) stored in energy, Powers(mW) stored in power. Number of // each command stored in timings. From 9abaeffc419d76824d216c82aebfc86b46c3fa99 Mon Sep 17 00:00:00 2001 From: Subash Kannoth Date: Thu, 4 Aug 2016 12:39:41 +0200 Subject: [PATCH 02/12] Add: Bankwise energy distribution 1) Implement bankwise energy distribution for the below components. idle_energy_act idle_energy_pre f_act_pd_energy f_pre_pd_energy s_act_pd_energy s_pre_pd_energy sref_energy sref_ref_energy sref_ref_act_energy sref_ref_pre_energy spup_energy spup_ref_energy spup_ref_act_energy spup_ref_pre_energy pup_act_energy pup_pre_energy 2) New class for Bankwise parameters . Implement explicit handling of PASR and Self-Refresh power factor Sigma.( New CLI arguments for both). --- Makefile | 2 +- src/MemBankWiseParams.cc | 138 ++++++++++++++++++++++++++++++ src/MemBankWiseParams.h | 80 +++++++++++++++++ src/MemoryPowerModel.cc | 128 ++++++++++++++++++++++++--- src/MemoryPowerModel.h | 44 +++++++++- src/cli/drampower.cc | 55 ++++++++++-- src/libdrampower/LibDRAMPower.cc | 7 +- src/libdrampower/LibDRAMPower.h | 6 +- test/libdrampowertest/lib_test.cc | 4 +- 9 files changed, 436 insertions(+), 28 deletions(-) create mode 100644 src/MemBankWiseParams.cc create mode 100644 src/MemBankWiseParams.h diff --git a/Makefile b/Makefile index 416d93c0..5a79742e 100644 --- a/Makefile +++ b/Makefile @@ -43,7 +43,7 @@ LIBS := src/libdrampower.a src/libdrampowerxml.a # Identifies the source files and derives name of object files. CLISOURCES := src/TraceParser.cc src/CmdScheduler.cc $(wildcard src/cli/*.cc) -LIBSOURCES := $(wildcard src/libdrampower/*.cc) src/CommandAnalysis.cc src/MemArchitectureSpec.cc src/MemCommand.cc src/MemoryPowerModel.cc src/MemorySpecification.cc src/MemPowerSpec.cc src/MemTimingSpec.cc src/Parameter.cc src/Parametrisable.cc +LIBSOURCES := $(wildcard src/libdrampower/*.cc) src/CommandAnalysis.cc src/MemArchitectureSpec.cc src/MemCommand.cc src/MemoryPowerModel.cc src/MemorySpecification.cc src/MemPowerSpec.cc src/MemTimingSpec.cc src/Parameter.cc src/Parametrisable.cc src/MemBankWiseParams.cc XMLPARSERSOURCES := $(wildcard src/xmlparser/*.cc) ALLSOURCES := $(wildcard src/cli/*.cc) $(wildcard src/*.cc) $(wildcard src/xmlparser/*.cc) $(wildcard src/libdrampower/*.cc) diff --git a/src/MemBankWiseParams.cc b/src/MemBankWiseParams.cc new file mode 100644 index 00000000..4ee62bd9 --- /dev/null +++ b/src/MemBankWiseParams.cc @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2016, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Subash Kannoth, Matthias Jung, Eder Zulian + * + */ + +#include "MemBankWiseParams.h" + +using namespace Data; +/** + * Sets all the bankwise parameters required in bankwise mode + */ +MemBankWiseParams::MemBankWiseParams(int64_t factRho, int64_t factSigma, bool hasPASR, int64_t pasrMode, bool opMode,int64_t nbrofBanks){ + + bwPowerFactRho = factRho; + bwPowerFactSigma = factSigma; + bwMode = opMode; + flgPASR = hasPASR; + /////////////////////////////////////////////////////////// + // Activate banks for self refresh based on the PASR mode + // ACTIVE - X + // NOT ACTIVE - 0 + /////////////////////////////////////////////////////////// + switch(pasrMode){ + + case(PASR_0):{ + // PASR MODE 0 + // FULL ARRAY + // |X X X X | + // |X X X X | + activeBanks.resize(nbrofBanks); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_1):{ + // PASR MODE 1 + // (1/2) ARRAY + // |X X X X | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 4); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_2):{ + // PASR MODE 2 + // (1/4) ARRAY + // |X X 0 0 | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 6); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_3):{ + // PASR MODE 3 + // (1/8) ARRAY + // |X 0 0 0 | + // |0 0 0 0 | + activeBanks.resize(nbrofBanks - 7); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } + case(PASR_4):{ + // PASR MODE 4 + // (3/4) ARRAY + // |0 0 X X | + // |X X X X | + activeBanks.resize(nbrofBanks - 2); + std::iota(activeBanks.begin(), activeBanks.end(), 2); + break; + } + case(PASR_5):{ + // PASR MODE 5 + // (1/2) ARRAY + // |0 0 0 0 | + // |X X X X | + activeBanks.resize(nbrofBanks - 4); + std::iota(activeBanks.begin(), activeBanks.end(), 4); + break; + } + case(PASR_6):{ + // PASR MODE 6 + // (1/4) ARRAY + // |0 0 0 0 | + // |0 0 X X | + activeBanks.resize(nbrofBanks - 6); + std::iota(activeBanks.begin(), activeBanks.end(), 6); + break; + } + case(PASR_7):{ + // PASR MODE 7 + // (1/8) ARRAY + // |0 0 0 0 | + // |0 0 0 X | + activeBanks.resize(nbrofBanks - 7); + std::iota(activeBanks.begin(), activeBanks.end(), 7); + break; + } + } +} + +/** + * Returns true if the given bank is active under the current PASR mode. + */ +bool MemBankWiseParams::isBankAciveInPasr(const int64_t bankIdx) const{ + return (std::find(activeBanks.begin(), activeBanks.end(), bankIdx) + != activeBanks.end()); +} diff --git a/src/MemBankWiseParams.h b/src/MemBankWiseParams.h new file mode 100644 index 00000000..c7d18084 --- /dev/null +++ b/src/MemBankWiseParams.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2012-2014, TU Delft + * Copyright (c) 2012-2014, TU Eindhoven + * Copyright (c) 2012-2016, TU Kaiserslautern + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Subash Kannoth, Matthias Jung, Eder Zulian + * + */ +#ifndef MEMBANKWISEPARAMS_H +#define MEMBANKWISEPARAMS_H + +#include +#include +#include + +namespace Data{ + class MemBankWiseParams{ + public: + // Set of possible PASR modes + enum pasrModes{ + PASR_0, + PASR_1, + PASR_2, + PASR_3, + PASR_4, + PASR_5, + PASR_6, + PASR_7 + }; + // List of active banks under the specified PASR mode + std::vector activeBanks; + // ACT Standby power factor + int64_t bwPowerFactRho; + // Self-Refresh power factor( true : Bankwise mode) + int64_t bwPowerFactSigma; + // Bankwise or Normal mode + bool bwMode; + // Wherther PASR is enabled ( true : enabled ) + bool flgPASR; + + MemBankWiseParams(int64_t factRho, + int64_t factSigma, + bool hasPASR, + int64_t pasrMode, + bool opMode, + int64_t nbrofBanks); + + + bool isBankAciveInPasr(const int64_t bankIdx) const; + }; +} +#endif // MEMBANKWISEPARAMS_H diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index 99327417..e8184428 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -50,8 +50,8 @@ using namespace Data; void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, const CommandAnalysis& c, - int term, bool bankwiseMode, - int64_t bwPowerFactor) + int term, + const MemBankWiseParams& bwPowerParams) { const MemTimingSpec& t = memSpec.memTimingSpec; const MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; @@ -64,6 +64,22 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.write_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.act_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.pre_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.idle_energy_act_banks.assign(static_cast(nbrofBanks), 0.0); + energy.idle_energy_pre_banks.assign(static_cast(nbrofBanks), 0.0); + energy.f_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.f_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.s_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.s_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.sref_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.spup_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pup_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.pup_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.act_energy = 0.0; energy.pre_energy = 0.0; @@ -165,9 +181,13 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // Using the number of cycles that at least one bank is active here // But the current iddrho is less than idd3n - double iddrho = (static_cast(bwPowerFactor) / 100.0) * (mps.idd3n - mps.idd2n) + mps.idd2n; - double eshared = vdd0Domain.calcTivEnergy(c.actcycles, iddrho); + double iddrho = (static_cast(bwPowerParams.bwPowerFactRho) / 100.0) * (mps.idd3n - mps.idd2n) + mps.idd2n; + double esharedActStdby = vdd0Domain.calcTivEnergy(c.actcycles, iddrho); + // Fixed componenent for PASR + double iddsigma = (static_cast(bwPowerParams.bwPowerFactSigma) / 100.0) * mps.idd6; + double esharedPASR = vdd0Domain.calcTivEnergy(c.sref_cycles, iddsigma); + //Distribution if energy componets to each banks for (int i = 0; i < nbrofBanks; i++) { energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - mps.idd3n); energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RC - t.RAS), mps.idd0 - mps.idd2n); @@ -175,6 +195,29 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.write_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofwritesBanks[i] * burstCc, mps.idd4w - mps.idd3n); energy.pre_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n) / static_cast(nbrofBanks); energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho)) / static_cast(nbrofBanks); + energy.idle_energy_act_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n) / static_cast(nbrofBanks); + energy.idle_energy_pre_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n) / static_cast(nbrofBanks); + energy.f_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p1) / static_cast(nbrofBanks); + energy.f_pre_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_pre_pdcycles, mps.idd2p1) / static_cast(nbrofBanks); + energy.s_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.s_act_pdcycles, mps.idd3p0) / static_cast(nbrofBanks); + energy.s_pre_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.s_pre_pdcycles, mps.idd2p0) / static_cast(nbrofBanks); + + energy.sref_energy_banks[i] = engy_sref_banks(mps.idd6, mps.idd3n, + mps.idd5, mps.vdd, + static_cast(c.sref_cycles), static_cast(c.sref_ref_act_cycles), + static_cast(c.sref_ref_pre_cycles), static_cast(c.spup_ref_act_cycles), + static_cast(c.spup_ref_pre_cycles), t.clkPeriod,esharedPASR,bwPowerParams,i,nbrofBanks + ); + energy.sref_ref_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.sref_ref_act_cycles, mps.idd3p0) / static_cast(nbrofBanks); + energy.sref_ref_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.sref_ref_pre_cycles, mps.idd2p0) / static_cast(nbrofBanks); + energy.sref_ref_energy_banks[i] = energy.sref_ref_act_energy_banks[i] + energy.sref_ref_pre_energy_banks[i] ;// + + energy.spup_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_cycles, mps.idd2n) / static_cast(nbrofBanks); + energy.spup_ref_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_ref_act_cycles, mps.idd3n) / static_cast(nbrofBanks);// + energy.spup_ref_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.spup_ref_pre_cycles, mps.idd2n) / static_cast(nbrofBanks); + energy.spup_ref_energy_banks[i] = ( energy.spup_ref_act_energy + energy.spup_ref_pre_energy ) / static_cast(nbrofBanks); + energy.pup_act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.pup_act_cycles, mps.idd3n) / static_cast(nbrofBanks); + energy.pup_pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.pup_pre_cycles, mps.idd2n) / static_cast(nbrofBanks); } // Idle energy in the active standby clock cycles @@ -268,13 +311,14 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // adding all energy components for the active rank and all background and idle // energy components for both ranks (in a dual-rank system) - if (bankwiseMode) { + if (bwPowerParams.bwMode) { energy.total_energy = total(energy.act_energy_banks) + total(energy.pre_energy_banks) + total(energy.read_energy_banks) + total(energy.write_energy_banks) + energy.ref_energy + energy.io_term_energy + - static_cast(memArchSpec.nbrOfRanks) * ( (eshared + total(energy.act_stdby_energy_banks)) + - energy.pre_stdby_energy + energy.sref_energy + - energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy - + energy.s_pre_pd_energy + energy.sref_ref_energy + energy.spup_ref_energy); + static_cast(memArchSpec.nbrOfRanks) * ( (esharedActStdby + total(energy.act_stdby_energy_banks)) + + total(energy.pre_stdby_energy_banks) + total(energy.sref_energy_banks) + + total(energy.f_act_pd_energy_banks) + total(energy.f_pre_pd_energy_banks) + + total(energy.s_act_pd_energy_banks) + total(energy.s_pre_pd_energy_banks) + + total(energy.sref_ref_energy_banks) + total(energy.spup_ref_energy_banks)); } else { energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + energy.write_energy + energy.ref_energy + energy.io_term_energy + @@ -358,7 +402,22 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << " RD Cmd Energy: " << energy.read_energy_banks[i] << eUnit << endl << " WR Cmd Energy: " << energy.write_energy_banks[i] << eUnit << endl << " ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy_banks[i] << eUnit - << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit; + << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit + << endl << " Active Idle Energy: "<< nRanksDouble * energy.idle_energy_act_banks[i] << eUnit + << endl << " Precharge Idle Energy: "<< nRanksDouble * energy.idle_energy_pre_banks[i] << eUnit + << endl << " Fast-Exit Active Power-Down Energy: "<< nRanksDouble * energy.f_act_pd_energy_banks[i] << eUnit + << endl << " Fast-Exit Precharged Power-Down Energy: "<< nRanksDouble * energy.f_pre_pd_energy_banks[i] << eUnit + << endl << " Slow-Exit Active Power-Down Energy: "<< nRanksDouble * energy.s_act_pd_energy_banks[i] << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy: "<< nRanksDouble * energy.s_pre_pd_energy_banks[i] << eUnit + << endl << " Self-Refresh Energy: "<< nRanksDouble * energy.sref_energy_banks[i] << eUnit + << endl << " Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: "<< nRanksDouble * energy.sref_ref_act_energy_banks[i] << eUnit + << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy_banks[i] << eUnit + << endl << " Self-Refresh Power-Up Energy: "<< nRanksDouble * energy.spup_energy_banks[i] << eUnit + << endl << " Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_act_energy_banks[i] << eUnit + << endl << " Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_pre_energy_banks[i] << eUnit + << endl << " Active Power-Up Energy: "<< nRanksDouble * energy.pup_act_energy_banks[i] << eUnit + << endl << " Precharged Power-Up Energy: "<< nRanksDouble * energy.pup_pre_energy_banks[i] << eUnit + << endl; } cout << endl; } @@ -425,6 +484,55 @@ double MemoryPowerModel::engy_sref(double idd6, double idd3n, double idd5, return sref_energy; } +// Self-refresh active energy estimation per banks +double MemoryPowerModel::engy_sref_banks(double idd6, double idd3n, double idd5, + double vdd, double sref_cycles, double sref_ref_act_cycles, + double sref_ref_pre_cycles, double spup_ref_act_cycles, + double spup_ref_pre_cycles, double clk, + double esharedPASR, const MemBankWiseParams& bwPowerParams, + int bnkIdx, int64_t nbrofBanks) +{ + // Bankwise Self-refresh energy + double sref_energy_banks; + // Dynamic componenents for PASR energy varying based on PASR mode + double iddsigmaDynBanks; + double pasr_energy_dyn; + // this compenets are distributed among all banks + double sref_energy_other = static_cast(((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles)) * vdd * clk) + / static_cast(nbrofBanks) ; + //Is PASR Active + if (bwPowerParams.flgPASR){ + // + sref_energy_other = (((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles)) * vdd * clk) + / static_cast(nbrofBanks); + + if (bwPowerParams.isBankAciveInPasr(bnkIdx)){ + + iddsigmaDynBanks = (static_cast(100 - bwPowerParams.bwPowerFactSigma) / (100.0 * static_cast(nbrofBanks))) * idd6; + // + pasr_energy_dyn = vdd * iddsigmaDynBanks * sref_cycles; + // + sref_energy_banks = sref_energy_other + pasr_energy_dyn + (esharedPASR /static_cast(nbrofBanks)); + + }else{ + sref_energy_banks = (esharedPASR /static_cast(nbrofBanks)); + } + } + //When PASR is not active total all the banks are in Self-Refresh. Thus total Self-Refresh energy is distributed across all banks + else{ + + + sref_energy_banks = (((idd6 * sref_cycles) + ((idd5 - idd3n) * (sref_ref_act_cycles + + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles))) + * vdd * clk) + / static_cast(nbrofBanks); + } + return sref_energy_banks; +} + + // IO and Termination power calculation based on Micron Power Calculators // Absolute power measures are obtained from Micron Power Calculator (mentioned in mW) void MemoryPowerModel::io_term_power(const MemorySpecification& memSpec) diff --git a/src/MemoryPowerModel.h b/src/MemoryPowerModel.h index 368ccfa3..f7571040 100644 --- a/src/MemoryPowerModel.h +++ b/src/MemoryPowerModel.h @@ -40,6 +40,7 @@ #include #include "MemorySpecification.h" +#include "MemBankWiseParams.h" #include "CommandAnalysis.h" namespace Data { @@ -49,8 +50,8 @@ class MemoryPowerModel { // command trace void power_calc(const MemorySpecification& memSpec, const CommandAnalysis& c, - int term, bool bankwiseMode, - int64_t bwPowerFactor); + int term, + const MemBankWiseParams& bwPowerParams); // Used to calculate self-refresh active energy static double engy_sref(double idd6, @@ -63,6 +64,20 @@ class MemoryPowerModel { double spup_ref_act_cycles, double spup_ref_pre_cycles, double clk); + static double engy_sref_banks(double idd6, + double idd3n, + double idd5, + double vdd, + double sref_cycles, + double sref_ref_act_cycles, + double sref_ref_pre_cycles, + double spup_ref_act_cycles, + double spup_ref_pre_cycles, + double clk, + double esharedPASR, + const MemBankWiseParams& bwPowerParams, + int bnkIdx, + int64_t nbrofBanks); int64_t total_cycles; @@ -96,9 +111,11 @@ class MemoryPowerModel { // Total energy of idle cycles in the active mode double idle_energy_act; + std::vector idle_energy_act_banks; // Total energy of idle cycles in the precharge mode double idle_energy_pre; + std::vector idle_energy_pre_banks; // Total trace/pattern energy double total_energy; @@ -108,29 +125,51 @@ class MemoryPowerModel { // Energy consumed in active/precharged fast/slow-exit modes double f_act_pd_energy; + std::vector f_act_pd_energy_banks; + double f_pre_pd_energy; + std::vector f_pre_pd_energy_banks; + double s_act_pd_energy; + std::vector s_act_pd_energy_banks; + double s_pre_pd_energy; + std::vector s_pre_pd_energy_banks; // Energy consumed in self-refresh mode double sref_energy; + std::vector sref_energy_banks; // Energy consumed in auto-refresh during self-refresh mode double sref_ref_energy; + std::vector sref_ref_energy_banks; + double sref_ref_act_energy; + std::vector sref_ref_act_energy_banks; + double sref_ref_pre_energy; + std::vector sref_ref_pre_energy_banks; // Energy consumed in powering-up from self-refresh mode double spup_energy; + std::vector spup_energy_banks; // Energy consumed in auto-refresh during self-refresh power-up double spup_ref_energy; + std::vector spup_ref_energy_banks; + double spup_ref_act_energy; + std::vector spup_ref_act_energy_banks; + double spup_ref_pre_energy; + std::vector spup_ref_pre_energy_banks; // Energy consumed in powering-up from active/precharged power-down modes double pup_act_energy; + std::vector pup_act_energy_banks; + double pup_pre_energy; + std::vector pup_pre_energy_banks; // Energy consumed by IO and Termination double read_io_energy; // Read IO Energy @@ -178,6 +217,7 @@ class EnergyDomain { {} double calcTivEnergy(int64_t cycles, double current) const; + double getVoltage() const{ return voltage; }; private: const double voltage; const double clkPeriod; diff --git a/src/cli/drampower.cc b/src/cli/drampower.cc index 81c53266..c11c0a2a 100644 --- a/src/cli/drampower.cc +++ b/src/cli/drampower.cc @@ -42,6 +42,7 @@ #include "MemorySpecification.h" #include "MemoryPowerModel.h" +#include "MemBankWiseParams.h" #include "xmlparser/MemSpecParser.h" #include "TraceParser.h" @@ -58,7 +59,8 @@ int error() "[-s] " << "[-r] " << "[-p] <1 - Power-Down, 2 - Self-Refresh> " << - "[-b] \n"; + "[-b] <ρ - ACT Standby bankwise power offset factor (0-100), σ - Self-Refresh bankwise power offset factor (0-100)> "<< + "[-pasr] \n"; return 1; } @@ -66,7 +68,10 @@ int main(int argc, char* argv[]) { int trans = 0, cmds = 0, memory = 0, size = 0, term = 0, power_down = 0; bool bankwiseMode = false; - unsigned bankwisePowerFactor = 100; + bool bankPASRact = false; + unsigned bankwisePowerFactRho = 100; + unsigned bankwisePowerFactSigma = 100; + unsigned pasrMode = 0; char* src_trans = { 0 }; char* src_cmds = { 0 }; @@ -95,8 +100,21 @@ int main(int argc, char* argv[]) } else if (string(argv[i]) == "-p") { power_down = atoi(argv[i + 1]); } else if (string(argv[i]) == "-b") { + string bwTuple = argv[i + 1]; + size_t idx; bankwiseMode = true; - bankwisePowerFactor = atoi(argv[i + 1]); + try{ + idx = bwTuple.find(","); + bankwisePowerFactRho = stoi(bwTuple.substr(0, idx)); + bwTuple.erase(0, idx + 1); + idx = bwTuple.find(","); + bankwisePowerFactSigma = stoi(bwTuple.substr(0, idx)); + }catch(const std::exception& e) { + return error(); + } + } else if (string(argv[i]) == "-pasr") { + pasrMode = atoi(argv[i + 1]); + bankPASRact = true; } else { if (string(argv[i]) == "-r") { term = 1; @@ -111,8 +129,18 @@ int main(int argc, char* argv[]) } } - if (bankwisePowerFactor > 100) { - cout << endl << "Bankwise power offset factor out of range." << endl; + if (bankwisePowerFactRho > 100) { + cout << endl << "ACT Standby bankwise power offset factor ρ out of range." << endl; + return error(); + } + + if (bankwisePowerFactSigma > 100) { + cout << endl << "Self-Refresh bankwise power offset factor σ out of range." << endl; + return error(); + } + + if (pasrMode > 7) { + cout << endl << "Wrong PASR mode." << endl; return error(); } @@ -142,6 +170,7 @@ int main(int argc, char* argv[]) MemorySpecification memSpec(MemSpecParser::getMemSpecFromXML(src_memory)); MemArchitectureSpec& memArchSpec = memSpec.memArchSpec; + MemBankWiseParams memBwParams(bankwisePowerFactRho, bankwisePowerFactSigma ,bankPASRact,pasrMode, bankwiseMode,memArchSpec.nbrOfBanks); if ((memArchSpec.twoVoltageDomains) && (bankwiseMode)){ cout << endl << "Bankwise simulation for Two-Voltage domain devices not supported." << endl; @@ -163,6 +192,11 @@ int main(int argc, char* argv[]) return error(); } + if ((!bankwiseMode) && (bankPASRact)){ + cout<(interleaving * grouping * memArchSpec.burstLength * memArchSpec.width / 8); if (size == 0) { @@ -195,17 +229,22 @@ int main(int argc, char* argv[]) cout << "* Analyzing the input trace" << endl; cout << "* Bankwise mode: "; if (bankwiseMode) { - cout << "enabled (power offset factor is " << bankwisePowerFactor << "%)" << endl; + cout << "enabled (power offset factors ρ=" << bankwisePowerFactRho << "% ,σ="< Date: Thu, 8 Sep 2016 15:59:24 +0200 Subject: [PATCH 03/12] Add and Refactor: 1) Corection :Added the shared energy component act_stdby_energy_banks[]. 2) Splitted the refresh energy per bank. 3) Splitted total energy per banks. --- src/MemoryPowerModel.cc | 29 +++++++++++++++++++---------- src/MemoryPowerModel.h | 2 ++ 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index e8184428..4903a32d 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -62,6 +62,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.read_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.write_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.act_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.pre_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.idle_energy_act_banks.assign(static_cast(nbrofBanks), 0.0); @@ -80,6 +81,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.spup_ref_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.pup_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.pup_pre_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.total_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.act_energy = 0.0; energy.pre_energy = 0.0; @@ -187,14 +189,16 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, double iddsigma = (static_cast(bwPowerParams.bwPowerFactSigma) / 100.0) * mps.idd6; double esharedPASR = vdd0Domain.calcTivEnergy(c.sref_cycles, iddsigma); - //Distribution if energy componets to each banks + //Distribution of energy componets to each banks for (int i = 0; i < nbrofBanks; i++) { energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - mps.idd3n); energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RC - t.RAS), mps.idd0 - mps.idd2n); energy.read_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofreadsBanks[i] * burstCc, mps.idd4r - mps.idd3n); energy.write_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofwritesBanks[i] * burstCc, mps.idd4w - mps.idd3n); + energy.ref_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd5 - mps.idd3n) / static_cast(nbrofBanks); energy.pre_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n) / static_cast(nbrofBanks); - energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho)) / static_cast(nbrofBanks); + energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho) / static_cast(nbrofBanks)) + + esharedActStdby / static_cast(nbrofBanks); energy.idle_energy_act_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_act, mps.idd3n) / static_cast(nbrofBanks); energy.idle_energy_pre_banks[i] = vdd0Domain.calcTivEnergy(c.idlecycles_pre, mps.idd2n) / static_cast(nbrofBanks); energy.f_act_pd_energy_banks[i] = vdd0Domain.calcTivEnergy(c.f_act_pdcycles, mps.idd3p1) / static_cast(nbrofBanks); @@ -312,13 +316,16 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // adding all energy components for the active rank and all background and idle // energy components for both ranks (in a dual-rank system) if (bwPowerParams.bwMode) { - energy.total_energy = total(energy.act_energy_banks) + total(energy.pre_energy_banks) + total(energy.read_energy_banks) + - total(energy.write_energy_banks) + energy.ref_energy + energy.io_term_energy + - static_cast(memArchSpec.nbrOfRanks) * ( (esharedActStdby + total(energy.act_stdby_energy_banks)) + - total(energy.pre_stdby_energy_banks) + total(energy.sref_energy_banks) + - total(energy.f_act_pd_energy_banks) + total(energy.f_pre_pd_energy_banks) + - total(energy.s_act_pd_energy_banks) + total(energy.s_pre_pd_energy_banks) + - total(energy.sref_ref_energy_banks) + total(energy.spup_ref_energy_banks)); + // Calculate total energy per bank. + for (int i = 0; i < nbrofBanks; i++) { + energy.total_energy_banks[i] = energy.act_energy_banks[i] + energy.pre_energy_banks[i] + energy.read_energy_banks[i] + energy.ref_energy_banks[i] + + energy.write_energy_banks[i] + static_cast(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i] + + energy.pre_stdby_energy_banks[i] + energy.f_pre_pd_energy_banks[i] + energy.s_act_pd_energy_banks[i] + + + energy.s_pre_pd_energy_banks[i]+ energy.sref_ref_energy_banks[i] + energy.spup_ref_energy_banks[i]; + } + // Calculate total energy for all banks. + energy.total_energy = total(energy.total_energy_banks) + energy.io_term_energy; + } else { energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + energy.write_energy + energy.ref_energy + energy.io_term_energy + @@ -401,6 +408,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << " PRE Cmd Energy: " << energy.pre_energy_banks[i] << eUnit << endl << " RD Cmd Energy: " << energy.read_energy_banks[i] << eUnit << endl << " WR Cmd Energy: " << energy.write_energy_banks[i] << eUnit + << endl << " Auto-Refresh Energy: " << energy.ref_energy_banks[i] << eUnit << endl << " ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy_banks[i] << eUnit << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit << endl << " Active Idle Energy: "<< nRanksDouble * energy.idle_energy_act_banks[i] << eUnit @@ -417,6 +425,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << " Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: "<< nRanksDouble * energy.spup_ref_pre_energy_banks[i] << eUnit << endl << " Active Power-Up Energy: "<< nRanksDouble * energy.pup_act_energy_banks[i] << eUnit << endl << " Precharged Power-Up Energy: "<< nRanksDouble * energy.pup_pre_energy_banks[i] << eUnit + << endl << " Total Energy: "<< energy.total_energy_banks[i] << eUnit << endl; } cout << endl; @@ -430,7 +439,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << "WR Cmd Energy: " << energy.write_energy << eUnit; if (term) { - cout << "RD I/O Energy: " << energy.read_io_energy << eUnit << endl; + cout < ref_energy_banks; // Total background energy of all active standby cycles double act_stdby_energy; @@ -119,6 +120,7 @@ class MemoryPowerModel { // Total trace/pattern energy double total_energy; + std::vector total_energy_banks; // Average Power double average_power; From 6d3d1984cf1db9e195b3320091821e9a78fe4998 Mon Sep 17 00:00:00 2001 From: Subash Kannoth Date: Fri, 23 Sep 2016 17:46:28 +0200 Subject: [PATCH 04/12] Add, Refactor and bugfix: 1) Overloaded the libDRAMPower constructor for adaptability. 2) Fixed the bug : last_pre_cycle was not updated with timestamp for PREA . 3) Added a default constructor for MemBankWiseParams and also added a default case for PASR modes. 4) Adapted the test_LPDDR2_1066_termination_matches_reference.out for unit test. --- src/CommandAnalysis.cc | 1 + src/MemBankWiseParams.cc | 21 ++++++++++++++++++- src/MemBankWiseParams.h | 5 +++-- src/MemoryPowerModel.cc | 20 +++++++----------- src/libdrampower/LibDRAMPower.cc | 9 ++++++++ src/libdrampower/LibDRAMPower.h | 1 + ...DR2_1066_termination_matches_reference.out | 3 ++- 7 files changed, 44 insertions(+), 16 deletions(-) diff --git a/src/CommandAnalysis.cc b/src/CommandAnalysis.cc index d230d9a3..a6efcb9b 100644 --- a/src/CommandAnalysis.cc +++ b/src/CommandAnalysis.cc @@ -348,6 +348,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // to PRE is happening. Add to the counter the amount of cycles the // memory remained in the ACT state. actcycles += max(zero, timestamp - first_act_cycle); + last_pre_cycle = timestamp; for (unsigned b = 0; b < num_banks; b++) { if (bank_state[b] == BANK_ACTIVE) { diff --git a/src/MemBankWiseParams.cc b/src/MemBankWiseParams.cc index 81bf4f94..c1328168 100644 --- a/src/MemBankWiseParams.cc +++ b/src/MemBankWiseParams.cc @@ -38,6 +38,16 @@ #include "MemBankWiseParams.h" using namespace Data; +/** + * Sets the default bankwise configurations. + */ +MemBankWiseParams::MemBankWiseParams(): + bwPowerFactRho(100), + bwPowerFactSigma(100), + bwMode(false), + flgPASR(false) +{ +} /** * Sets all the bankwise parameters required in bankwise mode */ @@ -129,13 +139,22 @@ MemBankWiseParams::MemBankWiseParams(int64_t factRho, int64_t factSigma, std::iota(activeBanks.begin(), activeBanks.end(), 7); break; } + default:{ + // PASR MODE 0 + // FULL ARRAY + // |X X X X | + // |X X X X | + activeBanks.resize(nbrofBanks); + std::iota(activeBanks.begin(), activeBanks.end(), 0); + break; + } } } /** * Returns true if the given bank is active under the current PASR mode. */ -bool MemBankWiseParams::isBankAciveInPasr(const unsigned bankIdx) const +bool MemBankWiseParams::isBankActiveInPasr(const unsigned bankIdx) const { return (std::find(activeBanks.begin(), activeBanks.end(), bankIdx) != activeBanks.end()); diff --git a/src/MemBankWiseParams.h b/src/MemBankWiseParams.h index 4d1ef320..dd8e9927 100644 --- a/src/MemBankWiseParams.h +++ b/src/MemBankWiseParams.h @@ -65,12 +65,13 @@ namespace Data { bool bwMode; // Wherther PASR is enabled ( true : enabled ) bool flgPASR; - + //Default constructor + MemBankWiseParams(); MemBankWiseParams(int64_t factRho, int64_t factSigma, bool hasPASR, int64_t pasrMode, bool opMode, unsigned nbrofBanks); - bool isBankAciveInPasr(const unsigned bankIdx) const; + bool isBankActiveInPasr(const unsigned bankIdx) const; }; } diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index 4903a32d..0132bb78 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -506,24 +506,20 @@ double MemoryPowerModel::engy_sref_banks(double idd6, double idd3n, double idd5, // Dynamic componenents for PASR energy varying based on PASR mode double iddsigmaDynBanks; double pasr_energy_dyn; - // this compenets are distributed among all banks - double sref_energy_other = static_cast(((idd5 - idd3n) * (sref_ref_act_cycles - + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles)) * vdd * clk) - / static_cast(nbrofBanks) ; + // This component is distributed among all banks + double sref_energy_shared; //Is PASR Active if (bwPowerParams.flgPASR){ - // - sref_energy_other = (((idd5 - idd3n) * (sref_ref_act_cycles + sref_energy_shared = (((idd5 - idd3n) * (sref_ref_act_cycles + spup_ref_act_cycles + sref_ref_pre_cycles + spup_ref_pre_cycles)) * vdd * clk) / static_cast(nbrofBanks); - - if (bwPowerParams.isBankAciveInPasr(bnkIdx)){ - + //if the bank is active under current PASR mode + if (bwPowerParams.isBankActiveInPasr(bnkIdx)){ + // Distribute the sref energy to the active banks iddsigmaDynBanks = (static_cast(100 - bwPowerParams.bwPowerFactSigma) / (100.0 * static_cast(nbrofBanks))) * idd6; - // pasr_energy_dyn = vdd * iddsigmaDynBanks * sref_cycles; - // - sref_energy_banks = sref_energy_other + pasr_energy_dyn + (esharedPASR /static_cast(nbrofBanks)); + // Add the static components + sref_energy_banks = sref_energy_shared + pasr_energy_dyn + (esharedPASR /static_cast(nbrofBanks)); }else{ sref_energy_banks = (esharedPASR /static_cast(nbrofBanks)); diff --git a/src/libdrampower/LibDRAMPower.cc b/src/libdrampower/LibDRAMPower.cc index 8710ddab..500ba266 100644 --- a/src/libdrampower/LibDRAMPower.cc +++ b/src/libdrampower/LibDRAMPower.cc @@ -39,6 +39,15 @@ using namespace Data; +libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination) : + memSpec(memSpec), + counters(CommandAnalysis(memSpec.memArchSpec.nbrOfBanks)), + includeIoAndTermination(includeIoAndTermination) +{ + MemBankWiseParams p (100,100,false,0,false,static_cast(memSpec.memArchSpec.nbrOfBanks)); + libDRAMPower DRAMPower = libDRAMPower(memSpec, 0, p); +} + libDRAMPower::libDRAMPower(const MemorySpecification& memSpec, bool includeIoAndTermination, const Data::MemBankWiseParams& bwPowerParams) : memSpec(memSpec), counters(CommandAnalysis(memSpec.memArchSpec.nbrOfBanks)), diff --git a/src/libdrampower/LibDRAMPower.h b/src/libdrampower/LibDRAMPower.h index bb54a527..a95e6e8a 100644 --- a/src/libdrampower/LibDRAMPower.h +++ b/src/libdrampower/LibDRAMPower.h @@ -49,6 +49,7 @@ class libDRAMPower { public: + libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination); libDRAMPower(const Data::MemorySpecification& memSpec, bool includeIoAndTermination,const Data::MemBankWiseParams& bwPowerParams); ~libDRAMPower(); diff --git a/test/reference/test_LPDDR2_1066_termination_matches_reference.out b/test/reference/test_LPDDR2_1066_termination_matches_reference.out index fa86e40b..9a813274 100644 --- a/test/reference/test_LPDDR2_1066_termination_matches_reference.out +++ b/test/reference/test_LPDDR2_1066_termination_matches_reference.out @@ -42,7 +42,8 @@ Total Trace Length (clock cycles): 41934 ACT Cmd Energy: 14333358.35 pJ PRE Cmd Energy: 6196322.70 pJ RD Cmd Energy: 14531482.18 pJ -WR Cmd Energy: 0.00 pJRD I/O Energy: 1036800.00 pJ +WR Cmd Energy: 0.00 pJ +RD I/O Energy: 1036800.00 pJ ACT Stdby Energy: 2966241.95 pJ Active Idle Energy: 0.00 pJ Active Power-Up Energy: 0.00 pJ From e8ee102a651e0cadc673a373c9f1cad553c76967 Mon Sep 17 00:00:00 2001 From: Subash Kannoth Date: Wed, 28 Sep 2016 18:51:48 +0200 Subject: [PATCH 05/12] Implement Bankwise refresh. 1) Implement bankwise refersh. 2) Bankwise ACT and PRE energy calculations are updated with new formulas as below. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ione := ( Idd3n + [ ρ.(Idd3n - Idd2n) + Idd2n ].(B -1) ) ------------------------------------------------ B Eact(b) = Vdd.[ Idd0 - Ione ].tRAS.Nact(b) Epre(b) = Vdd.[ Idd0 - Ione ].tRP.Npre(b) 3) Add new modified spec (modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml) with REFB parameters idd5b abd tREFB. 4) Add unit test for REFB calcuation. 5) Removed unwanted variable numberofacts. --- ...odified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml | 57 +++++++++++++++++ src/CommandAnalysis.cc | 20 +++++- src/CommandAnalysis.h | 5 +- src/MemCommand.h | 59 +++++++++--------- src/MemPowerSpec.cc | 2 + src/MemPowerSpec.h | 1 + src/MemTimingSpec.cc | 2 + src/MemTimingSpec.h | 1 + src/MemoryPowerModel.cc | 49 ++++++++++----- src/MemoryPowerModel.h | 3 + test/data/REFB.commands.trace.gz | Bin 0 -> 10279 bytes test/libdrampowertest/lib_test.cc | 4 +- .../test_LPDDR2_1066_matches_reference.out | 2 + ...st_LPDDR2_1066_short_matches_reference.out | 2 + ...DR2_1066_termination_matches_reference.out | 2 + ...ommands_trace_output_matches_reference.out | 2 + test/reference/test_transaction_scheduler.out | 2 + ...ransaction_scheduler_with_self_refresh.out | 2 + test/test.py | 11 ++++ 19 files changed, 177 insertions(+), 49 deletions(-) create mode 100644 memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml create mode 100644 test/data/REFB.commands.trace.gz diff --git a/memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml b/memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml new file mode 100644 index 00000000..fe68daa5 --- /dev/null +++ b/memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/CommandAnalysis.cc b/src/CommandAnalysis.cc index a6efcb9b..11678990 100644 --- a/src/CommandAnalysis.cc +++ b/src/CommandAnalysis.cc @@ -62,6 +62,7 @@ CommandAnalysis::CommandAnalysis(const int64_t nbrofBanks) numberofreadsBanks.assign(static_cast(nbrofBanks), 0); numberofwritesBanks.assign(static_cast(nbrofBanks), 0); actcyclesBanks.assign(static_cast(nbrofBanks), 0); + numberofrefbBanks.assign(static_cast(nbrofBanks), 0); first_act_cycle_banks.resize(static_cast(nbrofBanks), 0); @@ -87,7 +88,6 @@ void CommandAnalysis::clearStats(const int64_t timestamp) std::fill(numberofwritesBanks.begin(), numberofwritesBanks.end(), 0); std::fill(actcyclesBanks.begin(), actcyclesBanks.end(), 0); - numberofacts = 0; numberofpres = 0; numberofreads = 0; numberofwrites = 0; @@ -235,7 +235,6 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // If the bank is already active ignore the command and generate a // warning. if (bank_state[bank] == BANK_PRECHARGED) { - numberofacts++; numberofactsBanks[bank]++; if (num_active_banks == 0) { @@ -298,6 +297,21 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, for (auto& bs : bank_state) { bs = BANK_PRECHARGED; } + } else if (type == MemCommand::REFB){ + // A REFB command requires a previous PRE command. + if (bank_state[bank] == BANK_PRECHARGED) { + // This previous PRE command handler is also responsible + // for keeping the memory state updated. + // We consider that during a REFB the memory state is not changed + // in order to keep things simple, since the transition from + // PRE to ACT state takes time. + numberofrefbBanks[bank]++; + // Length of the refresh : here we have an approximation, we consider tRP + // also as act cycles because the bank will be precharged (stable) after tRP. + actcyclesBanks[bank] += memSpec.memTimingSpec.RAS + memSpec.memTimingSpec.RP; + }else{ + printWarning("Bank must be precharged for REFB!", type, timestamp, bank); + } } else if (type == MemCommand::PRE) { printWarningIfPoweredDown("Command issued while in power-down mode.", type, timestamp, bank); // If command is explicit PRE - update number of precharges, bank @@ -382,7 +396,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, for (unsigned b = 0; b < num_banks; b++) { if (bank_state[b] == BANK_ACTIVE) { actcyclesBanks[b] += max(zero, timestamp - first_act_cycle_banks[b]); - } + } } idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); diff --git a/src/CommandAnalysis.h b/src/CommandAnalysis.h index 2580083a..2a89794c 100644 --- a/src/CommandAnalysis.h +++ b/src/CommandAnalysis.h @@ -61,8 +61,7 @@ class CommandAnalysis { // Returns number of reads, writes, acts, pres and refs in the trace CommandAnalysis(const int64_t nbrofBanks); - // Number of activate commands - int64_t numberofacts; + // Number of activate commands per banks std::vector numberofactsBanks; // Number of precharge commands int64_t numberofpres; @@ -75,6 +74,8 @@ class CommandAnalysis { std::vector numberofwritesBanks; // Number of refresh commands int64_t numberofrefs; + // Number of bankwise refresh commands + std::vector numberofrefbBanks; // Number of precharge cycles int64_t precycles; // Number of active cycles diff --git a/src/MemCommand.h b/src/MemCommand.h index 9eb75108..3d7b70b5 100644 --- a/src/MemCommand.h +++ b/src/MemCommand.h @@ -53,19 +53,20 @@ class MemCommand { * 3. WR - Write * 4. PRE - Explicit Precharge per bank * 5. REF - Refresh all banks - * 6. END - To indicate end of trace - * 7. RDA - Read with auto-precharge - * 8. WRA - Write with auto-precharge - * 9. PREA - Precharge all banks - * 10. PDN_F_PRE - Precharge Power-down Entry command (Fast-Exit) - * 11. PDN_S_PRE - Precharge Power-down Entry command (Slow-Exit) - * 12. PDN_F_ACT - Active Power-down Entry command (Fast-Exit) - * 13. PDN_S_ACT - Active Power-down Entry command (Slow-Exit) - * 14. PUP_PRE - Precharge Power-down Exit - * 15. PUP_ACT - Active Power-down Exit - * 16. SREN - Self-Refresh Entry command - * 17. SREX - Self-refresh Exit - * 18. NOP - To indicate end of trace + * 6 REFB- Refresh a particular bank + * 7. END - To indicate end of trace + * 8. RDA - Read with auto-precharge + * 9. WRA - Write with auto-precharge + * 10. PREA - Precharge all banks + * 11. PDN_F_PRE - Precharge Power-down Entry command (Fast-Exit) + * 12. PDN_S_PRE - Precharge Power-down Entry command (Slow-Exit) + * 13. PDN_F_ACT - Active Power-down Entry command (Fast-Exit) + * 14. PDN_S_ACT - Active Power-down Entry command (Slow-Exit) + * 15. PUP_PRE - Precharge Power-down Exit + * 16. PUP_ACT - Active Power-down Exit + * 17. SREN - Self-Refresh Entry command + * 18. SREX - Self-refresh Exit + * 19. NOP - To indicate end of trace */ enum cmds { @@ -74,20 +75,21 @@ class MemCommand { WR = 2, PRE = 3, REF = 4, - END = 5, - RDA = 6, - WRA = 7, - PREA = 8, - PDN_F_PRE = 9, - PDN_S_PRE = 10, - PDN_F_ACT = 11, - PDN_S_ACT = 12, - PUP_PRE = 13, - PUP_ACT = 14, - SREN = 15, - SREX = 16, - NOP = 17, - UNINITIALIZED = 18 + REFB = 5, + END = 6, + RDA = 7, + WRA = 8, + PREA = 9, + PDN_F_PRE = 10, + PDN_S_PRE = 11, + PDN_F_ACT = 12, + PDN_S_ACT = 13, + PUP_PRE = 14, + PUP_ACT = 15, + SREN = 16, + SREX = 17, + NOP = 18, + UNINITIALIZED = 19 }; // MemCommand(); @@ -136,7 +138,7 @@ class MemCommand { } } - static const unsigned int nCommands = 19; + static const unsigned int nCommands = 20; static std::string* getCommandTypeStrings() { @@ -145,6 +147,7 @@ class MemCommand { "WR", "PRE", "REF", + "REFB", "END", "RDA", "WRA", diff --git a/src/MemPowerSpec.cc b/src/MemPowerSpec.cc index 3fbc5399..2f7011c0 100644 --- a/src/MemPowerSpec.cc +++ b/src/MemPowerSpec.cc @@ -60,6 +60,7 @@ MemPowerSpec::MemPowerSpec() : idd4w2(0.0), idd5(0.0), idd52(0.0), + idd5B(0.0), idd6(0.0), idd62(0.0), vdd(0.0), @@ -94,6 +95,7 @@ void MemPowerSpec::processParameters() idd4w2 = getParamValWithDefault("idd4w2", 0.0); idd5 = getParamValWithDefault("idd5", 0.0); idd52 = getParamValWithDefault("idd52", 0.0); + idd5B = getParamValWithDefault("idd5B", 0.0); idd6 = getParamValWithDefault("idd6", 0.0); idd62 = getParamValWithDefault("idd62", 0.0); vdd = getParamValWithDefault("vdd", 0.0); diff --git a/src/MemPowerSpec.h b/src/MemPowerSpec.h index f6958820..c5243dcd 100644 --- a/src/MemPowerSpec.h +++ b/src/MemPowerSpec.h @@ -63,6 +63,7 @@ class MemPowerSpec : public virtual Parametrisable { double idd4w2; double idd5; double idd52; + double idd5B; double idd6; double idd62; double vdd; diff --git a/src/MemTimingSpec.cc b/src/MemTimingSpec.cc index cf18c5f7..54b07e3b 100644 --- a/src/MemTimingSpec.cc +++ b/src/MemTimingSpec.cc @@ -58,6 +58,7 @@ MemTimingSpec::MemTimingSpec() : RL(0), RP(0), RFC(0), + REFB(0), RAS(0), WL(0), AL(0), @@ -94,6 +95,7 @@ void MemTimingSpec::processParameters() RL = getParamValWithDefault("RL", 0); RP = getParamValWithDefault("RP", 0); RFC = getParamValWithDefault("RFC", 0); + REFB = getParamValWithDefault("REFB", 0); RAS = getParamValWithDefault("RAS", 0); WL = getParamValWithDefault("WL", 0); AL = getParamValWithDefault("AL", 0); diff --git a/src/MemTimingSpec.h b/src/MemTimingSpec.h index 104bf5c7..2413177b 100644 --- a/src/MemTimingSpec.h +++ b/src/MemTimingSpec.h @@ -63,6 +63,7 @@ class MemTimingSpec : public virtual Parametrisable { int64_t RL; int64_t RP; int64_t RFC; + int64_t REFB; int64_t RAS; int64_t WL; int64_t AL; diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index 0132bb78..f74d1b38 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -63,6 +63,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.read_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.write_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.refb_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.act_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.pre_stdby_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.idle_energy_act_banks.assign(static_cast(nbrofBanks), 0.0); @@ -71,6 +72,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, energy.f_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.s_act_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.s_pre_pd_energy_banks.assign(static_cast(nbrofBanks), 0.0); + energy.ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.sref_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.sref_ref_energy_banks.assign(static_cast(nbrofBanks), 0.0); energy.sref_ref_act_energy_banks.assign(static_cast(nbrofBanks), 0.0); @@ -173,7 +175,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, EnergyDomain vdd0Domain(mps.vdd, t.clkPeriod); - energy.act_energy = vdd0Domain.calcTivEnergy(c.numberofacts * t.RAS , mps.idd0 - mps.idd3n); + energy.act_energy = vdd0Domain.calcTivEnergy(total(c.numberofactsBanks) * t.RAS , mps.idd0 - mps.idd3n); energy.pre_energy = vdd0Domain.calcTivEnergy(c.numberofpres * (t.RC - t.RAS) , mps.idd0 - mps.idd2n); energy.read_energy = vdd0Domain.calcTivEnergy(c.numberofreads * burstCc , mps.idd4r - mps.idd3n); energy.write_energy = vdd0Domain.calcTivEnergy(c.numberofwrites * burstCc , mps.idd4w - mps.idd3n); @@ -188,14 +190,27 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // Fixed componenent for PASR double iddsigma = (static_cast(bwPowerParams.bwPowerFactSigma) / 100.0) * mps.idd6; double esharedPASR = vdd0Domain.calcTivEnergy(c.sref_cycles, iddsigma); + // Active background current for a single bank + double ione = ( mps.idd3n + + ((((static_cast(bwPowerParams.bwPowerFactRho)/100.0)*(mps.idd3n -mps.idd2n)) + mps.idd2n) * + (static_cast(nbrofBanks) -1.0))) / + (static_cast(nbrofBanks)); + // If memory specification does not provide bank wise refresh current, + // approximate it to single bank background current removed from + // single bank active current + double idd5Blocal = (mps.idd5B == 0.0) ? (mps.idd0 - ione) :(mps.idd5B); + // if memory specification does not provide the REFB timing approximate it + // to time of ACT + PRE + int64_t tRefBlocal = (t.REFB == 0) ? (t.RAS + t.RP) : (t.REFB); //Distribution of energy componets to each banks for (int i = 0; i < nbrofBanks; i++) { - energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - mps.idd3n); - energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RC - t.RAS), mps.idd0 - mps.idd2n); + energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - ione); + energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RP), mps.idd0 - ione); energy.read_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofreadsBanks[i] * burstCc, mps.idd4r - mps.idd3n); energy.write_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofwritesBanks[i] * burstCc, mps.idd4w - mps.idd3n); - energy.ref_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd5 - mps.idd3n) / static_cast(nbrofBanks); + energy.ref_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC, mps.idd5 - mps.idd3n) / static_cast(nbrofBanks); + energy.refb_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofrefbBanks[i] * tRefBlocal, idd5Blocal); energy.pre_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n) / static_cast(nbrofBanks); energy.act_stdby_energy_banks[i] = vdd0Domain.calcTivEnergy(c.actcyclesBanks[i], (mps.idd3n - iddrho) / static_cast(nbrofBanks)) + esharedActStdby / static_cast(nbrofBanks); @@ -264,7 +279,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, if (memArchSpec.twoVoltageDomains) { EnergyDomain vdd2Domain(mps.vdd2, t.clkPeriod); - energy.act_energy += vdd2Domain.calcTivEnergy(c.numberofacts * t.RAS , mps.idd02 - mps.idd3n2); + energy.act_energy += vdd2Domain.calcTivEnergy(total(c.numberofactsBanks) * t.RAS , mps.idd02 - mps.idd3n2); energy.pre_energy += vdd2Domain.calcTivEnergy(c.numberofpres * (t.RC - t.RAS) , mps.idd02 - mps.idd2n2); energy.read_energy += vdd2Domain.calcTivEnergy(c.numberofreads * burstCc , mps.idd4r2 - mps.idd3n2); energy.write_energy += vdd2Domain.calcTivEnergy(c.numberofwrites * burstCc , mps.idd4w2 - mps.idd3n2); @@ -318,21 +333,22 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, if (bwPowerParams.bwMode) { // Calculate total energy per bank. for (int i = 0; i < nbrofBanks; i++) { - energy.total_energy_banks[i] = energy.act_energy_banks[i] + energy.pre_energy_banks[i] + energy.read_energy_banks[i] + energy.ref_energy_banks[i] - + energy.write_energy_banks[i] + static_cast(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i] - + energy.pre_stdby_energy_banks[i] + energy.f_pre_pd_energy_banks[i] + energy.s_act_pd_energy_banks[i] + + energy.total_energy_banks[i] = energy.act_energy_banks[i] + energy.pre_energy_banks[i] + energy.read_energy_banks[i] + + energy.ref_energy_banks[i] + energy.write_energy_banks[i] + energy.refb_energy_banks[i] + + static_cast(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i] + + energy.pre_stdby_energy_banks[i] + energy.f_pre_pd_energy_banks[i] + energy.s_act_pd_energy_banks[i] + energy.s_pre_pd_energy_banks[i]+ energy.sref_ref_energy_banks[i] + energy.spup_ref_energy_banks[i]; } // Calculate total energy for all banks. energy.total_energy = total(energy.total_energy_banks) + energy.io_term_energy; } else { - energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + - energy.write_energy + energy.ref_energy + energy.io_term_energy + - static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + - energy.pre_stdby_energy + energy.sref_energy + - energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy - + energy.s_pre_pd_energy + energy.sref_ref_energy + energy.spup_ref_energy); + energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + energy.write_energy + + energy.ref_energy + energy.io_term_energy + total(energy.refb_energy_banks) + + static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + + energy.pre_stdby_energy + energy.sref_energy + energy.f_act_pd_energy + + energy.f_pre_pd_energy + energy.s_act_pd_energy + energy.s_pre_pd_energy + + energy.sref_ref_energy + energy.spup_ref_energy); } // Calculate the average power consumption @@ -365,12 +381,13 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, } cout << endl << "* Trace Details:" << fixed << endl - << endl << "#ACT commands: " << c.numberofacts + << endl << "#ACT commands: " << total(c.numberofactsBanks) << endl << "#RD + #RDA commands: " << c.numberofreads << endl << "#WR + #WRA commands: " << c.numberofwrites /* #PRE commands (precharge all counts a number of #PRE commands equal to the number of active banks) */ << endl << "#PRE (+ PREA) commands: " << c.numberofpres << endl << "#REF commands: " << c.numberofrefs + << endl << "#REFB commands: " << total(c.numberofrefbBanks) << endl << "#Active Cycles: " << c.actcycles << endl << " #Active Idle Cycles: " << c.idlecycles_act << endl << " #Active Power-Up Cycles: " << c.pup_act_cycles @@ -409,6 +426,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << " RD Cmd Energy: " << energy.read_energy_banks[i] << eUnit << endl << " WR Cmd Energy: " << energy.write_energy_banks[i] << eUnit << endl << " Auto-Refresh Energy: " << energy.ref_energy_banks[i] << eUnit + << endl << " Bankwise-Refresh Energy: " << energy.refb_energy_banks[i] << eUnit << endl << " ACT Stdby Energy: " << nRanksDouble * energy.act_stdby_energy_banks[i] << eUnit << endl << " PRE Stdby Energy: " << nRanksDouble * energy.pre_stdby_energy_banks[i] << eUnit << endl << " Active Idle Energy: "<< nRanksDouble * energy.idle_energy_act_banks[i] << eUnit @@ -469,6 +487,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << " Slow-Exit Precharged Power-Down Energy: " << nRanksDouble * energy.s_pre_pd_energy << eUnit << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy << eUnit << endl << "Auto-Refresh Energy: " << energy.ref_energy << eUnit + << endl << "Bankwise-Refresh Energy: " << total(energy.refb_energy_banks) << eUnit << endl << "Self-Refresh Energy: " << nRanksDouble * energy.sref_energy << eUnit << endl << "----------------------------------------" << endl << "Total Trace Energy: " << energy.total_energy << eUnit diff --git a/src/MemoryPowerModel.h b/src/MemoryPowerModel.h index e82bab32..291e3d6f 100644 --- a/src/MemoryPowerModel.h +++ b/src/MemoryPowerModel.h @@ -102,6 +102,9 @@ class MemoryPowerModel { double ref_energy; std::vector ref_energy_banks; + // Bankwise refresh energy + std::vector refb_energy_banks; + // Total background energy of all active standby cycles double act_stdby_energy; std::vector act_stdby_energy_banks; diff --git a/test/data/REFB.commands.trace.gz b/test/data/REFB.commands.trace.gz new file mode 100644 index 0000000000000000000000000000000000000000..9bae89e97925ce7d5ec9f319dbb2e8e39782d501 GIT binary patch literal 10279 zcmaL7XH-*L)HZrV5TyzTgc?M84;_IZC?FjKkzN7_8X{dk$1 zd|)uwC+-0C)s{1=NEPJV8%m0~+|{F+ ze1=Dy6_F2$_Qoa==XmmYE&aaRZqbR`uJiHK!`d^YStEW?@_zDwqg6@+;$#gg^ND;q zhB!MQqY(ZOemD7)`c5r1^3&5ZgR)$ip+azcb?3k)!XLL$ZNyQ<{}DE!gRgqxMZZHP86F&XqpR?Hmo^k2_MIMnOD!@ojTa}`s@>iyg6=h6 zt8(Yeiszcn)~%0lb!~U?Xm>3LbtwtWx6Ln9t5R4U33Z!z#PWW8Iqz+7Y-Gc3k6dGo z63h}l{ey8o4|V2wG_pW{W4xIf*7@kyMT-R_%ACELeL6Q-3_7On-P)-pypcD=JX$;S z?MTUX!5y`eH^SKRRawNIeN!by_VnRS3^*dy=aQCcUfIj9+hW0=bDL$n>>G-4o3=Bq1o>C9PU?94e_^yXWJ?k8^_M`BNxhkqS+{_|&Xp;ouo%&+&@ zdM0*3;-LO3T0aTY8~_#RQTov&2;x%bxv=oJp_1KvBo0v>bBOeiI6t`)8ztR5Z#_ZXEQ zmTmI+aU6rL)J1mbF>Tn#1&P-!G{cu#q*W5PdeJj3nq8~N?ey^cuAzXgo7X&bh{$bv z=EnQC>{q-tA|e`p-@KsAG|dZZ_h|eLrcq|_PEuy)f=RS@>piQPc&D$Ihv8KBzBbJb ztMqLAP#LBB%u@H+#u_#3-T1>RFzfME+F6H^5w=-~wmq*GeN6LRuVETkXt6Zotb9og zMA`L`2o74To&0eGPf^Ea-xLz{~h1{53Ws`sy(?k^S5l<4u^0U+N|!uP2wS>eoT^ zBfZUMdlMXR83$+(z_tV$kl>gi}@HZO%(%8eSLm9@rK>0pK9t2D5v44q5< zbX<1@+y!D%$V)>M+JE*fQKtB{C^_JoBbx(78gBZI(?p-dg#-DnaVr5p^ zrZhD#p!)3WbYe3ml1Azit?*so5AE~fWCZD&_*OcK|6Wo(H|xA_~_3dx5RKCEtiN*uz31UTTZL*-D~ z6cY=l4w<1v-hCY`45T^tzK9qVB$$F#4)c5gs1CtUGm=3^^M@&>Jv;MS;k|bATHyL# zv6I<4V+ls}2ak3~+7I;)m2sJ23Kc2|VWOIQb@vEwEBIyBbRVv}-Y2yUa_$N;@73Kr zx<;buuxHxc&P$~(GDH;z7hUY=IFTV;>F5|Q3EsFu62Y;BwMehS;tVhqEx))zoPTT> zc0BoEr1D8+>#ke56ZdPhZbzd~QfAmALvGH!Z&`}g>*b(F44&VJ^pkHvNCUU*bm>6R zBv&);-Xg^p+A}(F-vAutAPqye?2O1QU-2YYOYYwHiZ3jFf4K1e8^F38grtNrr2{3C zV#8{kkLKQlANcK$#6%>FpknKMmNxB$PO|bMhI>)v4L&)W_OSgLrW5PYU<*0k6Di6T zMglG_sqGIxW9VGExj!8BERHaZuuVDk;XONt0c5cqN-mW>!qDlTKr#k;RWB^#`W{u4am;|5qXUw5Hvq?LgmK6O< zKe0a}?ti&Q|8KWRjVVZ#DTv`r)_x5^Gw_}jTV^B&Zck2UzFq_X{)+Y+k9Z9iJL*%d zxQs4wo)QF_qU4zPOhHUxR)hMlWfNm6U3jhT58(x!e?a5HOg>D#4y&n{dMrQ1m$U!& zBM&e+MslFLX&U3FcJN85cR-o6fH~Z0QE|%ukHOw?NH@ndoGlQei%EnpQZ0Er0b{bf zNgTL~Q#7*S3a44OF|Xja2*ZmEvJhNEI`dkDZT?aUb*L8ZVwkgtXGo?XK@a?4N_lU# z#3^9C>8;bkkBzu6XH&c^$8K{sil#P9DzwvWh@RgFvtmP%A9&TG7V#0X@JdC+8re=1 zUdxl!#FY(lVsy>yk@O3XaRKSFNcy6Lg*c@_$;sleJwk7+(we6m<8i$%CJA}FHl_Bw z7tzVXiGc1vG-;8KU*qipR_p>yJWeDURp!?f(M_ZMn`2}1I|fr<`dXQTUFG-LfdXNd&dew`n0j~WxPKl-4>S?aJi+lMb&Zb8G3Fah8Ma$@y< zra!23LR#)Emsh47v_=33#2vgQ|2a~BzG`$VT;nt}CC)9~Y%Ph%&s-z`jDs(C41}b_ znWd2@r+OET+e4586bd`EcVh z6RD5orF6@WbREZrO~-2TgAKqLa0nPjsUDQZEb5%itcJn5vXjzq^nb1oglkkAf;o>$ zouoqw8yUya-)U2p5ZBHTN(Ruh;LR2_e(Vwq2TKnQDTKG^AnL1oSx&5bP?_~U>}&Ql zv8cUfzd`#n=G~fLSE?A27ex zZy6vwJax^{(IEttuzYl0Hig(dPH`en@I=pMu}k0(yXX|m;Y6NR*dKkL^RHc)~ zaGRq@QOW%{=3`6HMD3V558=S$R`=&Lv$bF0w+X|~q7MX$bof1}ND@1!gHIl!v%_j$ zvQ9Y5Zr~&a`Bm(28uxvu>|D?3=dT5(KoFYDf8+`0Hq$fQW;rJ^-(iH5sK3s|1i`NCHp9xW{%e*H!2?IHTP z-Y=0Hro&GjHC;*08?b^ae-uAL0-%;uK{81eYu^Bw6k7ild8vuQo8JIGWs(vIRmuww z>Ur&7(ab~$6n#pKWUmNq17H!8-G`l@R2%h`5|KTvODgNGxJ-1EzHZ{~WVD}ZbZ$0U z?A4>h%51bMmm+$oI2e@Az>Reu2Z+W{l)HIBo4Wdb@?MGQ+HUy_PbTnI+y@yBmXGIc zR6+wt!iy0!AQATNj#}b` zD4@(tUav^py%V8czR6tmse^q^{c*rpMkCo39{~8wgQXk+<>VbNs`6<55P~8;EkS} z_tkVT>2OHl+Dx`+Sn_MFiq^@tdbldboak!Gr>siQs}I~|xs{+VAHwX}lP}U&Za*FN zb1}#igI01&4n*C*pOk==E8KEjQ9TV&J|lV`V`p{;8h)pEeg}@d(<(GUXyl#$8wkVx z=Cp@_E8-JW_OH%WJ2#I|J!G?%YY`SFJ;Ys%XlNK$QU5e#pUS*D61aqPk%&XGA3Z}T z&rK`LodZG_aJ@rieS0tTk@NxA+LZM&p>7#%82_NJ2K3k3G2@SM7VEQsrjHSHI`tbh zLCmDxdd+^hgKG1gSpa)&k_9QO3JW^mzM*%bqr3sBK5GuQIYF5V%>nLzO0p0Mhf$&5 zgOEu+?rkzM8VGRbac?>dmgo(|+ISbC_baqI%g?9(I8uWuZqq?hjV>QCkm3p4r&93g zMJ@iX2#suVh#Z;da*pjj9f(m{C9E$I9`llNaBR*&tbz|Rx?g*s4s1($~q?qton@& zH_ma8b3c8W=fuEUnv{Gd{|LQVH zj`K}`OzT*FKzDzDOvs_okvYkB(PZ)Sx4<+!msXPJX`^qmY(6l2NYL|jve`}9^CP`i z=b{DYqA`E%y|nVcbzbMvy{u{G0DQP=y|EWOZ$wzMNYGu9XQJ-A}agG@%oKl%{qRGAg{N`7aOnH_2UwEy= z1I+sgW<1!7KfuZA5Xgwh?=xyxZNGH@c1Zc81Ou=|3fi zk`Z&p=ZIeftnctIK+Al@Jo)7LX%h(UIST;h7B+tcu+8zZvGuK?Uruxk_il9NLfHnxu)4$p%7{?djLukPZR2)L5o9hWE*~2tv5&ZD1>S zc_gmE=`iD(lh1iR`~K?F<&XgN&gp~j$@r9Xf)BGat?Hob$ur*3XisZM$iss6HAjT< z$y0zuA;9Ub{w1UiYp*13FpAceMtb?!3bum`6f1m#%8pN+_V)$^_3(L6VK6=W}K zueuZnb(;;VZnfHd@DKv`5qV+EdRs)k=)sTv_rxu}<1g?9XzaqlRKMqIAH7JaozTmU zOtFNkcI)Q*XM_>?os$J6zX~bnvbpWL0Ns??w7C^qr}KRwm6UIat`&ZqxC5*4%jF1WyW>iGv5qJE_MrWP>wPZ9n{e7%|QiyC#1_pfD*_ofVUK@j+R zQFL%vBxpHY1B4o2QyznhPW{%228iy*qn=ck^^Y>$hkO!$M^bzAbM;!ycCH`HibUD{oVCz zIGbHxsY>32O9PN}H&6&r^u>W6WGybf1Sqm^5a}{<1#iba+N8+a9tc_c#yX}KM!Z6* z*UyOG-C~I^F%o?tQ!xEEqtl%er;lF5gN}R~rX%jf+Utw8N`suj3nGVvIoxv7AgAbp z@}cZ3b~$KpN*i_M-(op#LvVrNl=G(_aXF+26H@Pol&!=rj}TFNrx1JyBjKT%XJ@eG zz@OG?XyL$0zo8n^E2ZaeBPMDZV_y>Z{IkazNXs?2UenTmE(&@~@1>DV!J9%JRB^nk z(FJ$#|3Z_(6ui)UYrL8O7i#;~mbPk$*M1^dKs!_u$nW0rEi@XNIYRuh6wI*qY zSZ}paIf^1~Q=T@+J22k0O!9OW{);CK*3Rr59Pj$sNGbsy%iHYBJlmt`MSoB%|K(Zj zd`z=H^XwN*FUf;q7{&2pjyCJ>pO0C*;RiYpIMi|Ys(Bg3$Qi&KUEA|lPWSyQ3;mVB zSN_Uo|08q%l{+r|m20C2-Tm{>#c)b(?nC~+GK%*9TUJANtO5>lvGdU6fLgWDj#brz zT()_rsc)@XcgHIA0XNq?)ZMo>t-C|-(gAl4#qqCA8|u*GIN&bvae^GKQg$Zn-h9k+ ze7}T-tm#+HyUGUwOQC*{e9kEgY21yt@N{0Bp>d*nJY`jJflTX2);&&75o_<6j=>e& zaAr8U2bq4uO1mHJz@M6_?=2{8wj5s%c+J5PxqoUXvAcN`&%&4wnCOaS-o_sC8^FaR zAAI?;WLW?J{|w4V^44b^#AN|K%v({l&C^+muw)Dkk7tw1Wp%Orhx`-J+7m}-y4}wR z@ovI-c{V8w{{EWsJYqEVq(#v}(=5Z({h4{e;6Eid(=O-)30}Mt>399&9SB8qj3a-} zAb(Ef(y1-LId-OTl|~cu;qEW)CVst|34FYGP8-<}p9T^H$?FN}p)cRp{ueL%1_5aR zt{YbD6a-mUI>Te%qn}gA(_t%YG%10Tj*Nt7vM|rKejUhC^X9+oI!(Tazd{+D0i}36Q-D$$ z;c|TNyC0LAp0bQo%eTSsHn+Jt8#0`{Hi=29caX+tvfX&tJ=x&q0DlfY+~N85oa5=? zIuC2C6GIWas&{o@A-S40KJ9+bcHzlJo-yU!^`bHwoUfg}pK@eCuz%h-Re2-Po1Mmt z$n5bM6+-75Flc4bEzY-MmIfdmSE;oYDWrPCIi%;Ca2!}l>ak;5pK-+6$Iw@2MKb5uhRT*yuV zv%2!I=-@BxEL-s`6HlI?$xVx7l<_4_TCz$andjy8%4e=SZu#hewopiZ-h0)hhBp9k zc>Ge{8vrWwMa6i+Ql4k`p9uOw!g~?g4l&SfDeuzao+t4bUqm@hXpr+0{LZrh_>}mi zi#b(S-~wz#+NjG%Jw#OX<5)LeWW6e;rP;xo*Jrx>thdN7Gsim^~*Q2EH| zPPm)6$@jrkK+*u>E=(luzUncny{i$2Jr7`-N0{c*;ONw;r!<^vd!iL~`&4fqJc361 z*monEi3!Zd=G|5)ogAYLBqM(OY`ovct>LSAixi~R3dqL_>AkzU04*sBhwZX~L}F?1 zZ7aFNz?eR<3yUu=v}KQZsaLA~AWl(fJwLdTKNYTKrg6?SxSR@zcVfHo9V){UqR)!u z6Q5GMCaby|WWbP@SH!rmInTbB=Lm>UA6r$Bcq6o1)i+-2zi%n>&0X+?Pe3mgFOy3fLo03g(_Mr2=fnSrt|)O;#OD&Ro;S zs;iW9p8n+c^Kmsx24{Ib)q)dMvCrs)eOXXm@yR2#BxReJMeqlF$avszqaq;<5DWTJ zklwF-ZAFGoOa1Zk*=9v@_4Utka4E@>7-E=nE9PB{Pk4F?H+7I=L|5<+o{HzyI$#MV zA-$ofp0NY@`!Phg?8eKvp*JRA$Ul5D+A{n2^qg682skHxOu+d$yw9}Vtj|>B1vvn6 zs3oe5L0lqqDib=H2%U>$2mM{Tb4sNAof2t@oDVo3i@oltHTWt6V4KEzL-O^Bk!B>( zigLcGy>xD*6-f*vt)$joI5*OcBy!^tUi)PGoPSGoMsgf2<9Jpx2Npxz{E#KQK7aw9 z!JgLuTN{${e@utvOY9E5%BBC%HT>!DI@2UN+kwZe$444;I$1ev^9MVVi#Cx?JWy2r za`+bAt0~EJP_6oM>TY64Qcrf#heDUgo>~&bJkg5v+dfh3d<`moZ{r!Fdg1$qvHtoJ9rn zMFl)X1-+sYAb2S$Guq6m!zt#p*ORlylXLJsYv#8jBK{Wdov%@?dUT}9dFV6hP@M-4*jdPL3!yn0ggITOH~vTFC6L*Dza!-Ks3na* zDz=z^;Svr$tQ932ciN>cAF;^S)?e85KHtan{XmKc-pfB(1pmzJfz`MC1769{5uPb- zd`(jPQVVaU5Y1^D!)YkT(aw<>LlOBjI+jlfv{|ut1RjjzQ<{A7uUD_US@9QpzdO6N zc50ILX6;KhLlo{uIz z$$DBGGV<(n7Q`N?f39|S(gqtM`?F$$f`&Oru-60|m1dc09`+yF zsE)(jTgkD@JaD^v8;+ZK!2OY=h(9h1kOm*W=@w46AirWCe1xPUJQ0rb7XQOO+4u)i zEd$mDpSs_JMHLxC4u^zZ6dAi}Bs5$N$N-!xsL?NJrBgWmKk{Qb^^|xtD**ggVbi~~ zA`s_)wS-qljFvAWhX0Fptp9j1ulGHsr((30U%I2Qdqc$I=U`vBHc&N6p|(%;4;`0k zuVJD>b)Ra=-NZjHQ{x*d`&6qW7}N%F@T;pk249cNlL?EmqqMg9%%9YN?g8MzRZ1Yn zFer1(k*Vl2FE}_KJ7(WWHO7ZOzDOZXq7ME^BSCMHqCm^#e4I6v!b(kw{AUQOacwr8Ty>mo7u-fy_T7>SDVj%%YI0l9W!n_e zjd7%A!06hXjJ(><(@eb%ito4k@QLVQLk(v19CE9ReSs7#w&1vsDSsu()RsEqi(v76 zjtfox))F1P9I+5v>Wxy7?k^R(JFZutc&oOnR%7B+djYR*(G&=p-+mtmwVDv83JQGE zofiDWmije#gziqR_m#I1?bMP{xUk`S0<52h1WePl8!N?FJERN`ACcLj$P*J1@7BD8 zEdv{K#czg9WVDHhRDZNyzVo2Uue6F?ZQ^HT{@N1{)4-OSqQ_qmEk0xC2RBsDf_UC* z8TSJ(IL{b~5uTbS)Lnk=!x?qBW#o-9N$vh{`T0}MsOfE^{CysGKZ#QI*|tz+xqGnk zr&jhgd_S$d@vDQk5}N$gRg5m#n=dw9&IpmF(sfF>l`~ZdZ4k9T^@0+A+V$8ODRT9B z%e$mHu)KWz`A*})qDJTCci&B;j~e6ZQ@vQeR%j;n-${2-n=q0(O)o8g9gc$=W)<$@4zV2?Uy9B#s{yfL*OU76fp^oN?opIn})=~u&UF^q<&ml@!z zMG6A+PLl4PFf#eSzM7A_=4TCMfl6;V%E1WHzZau@+FKX%nuEI=JLuotwXmj1Pc7TD zHhb)^0P}C~^8Yh~TYWz?(lj(uHYEKp-TrR6saQGI&HN_#T{DMmjjlK!;<^S9)X_Bf zNSeE*zm@$k@Cgm-QaKiCaT7HwvRwsRM$L(Af2L5seS*c!(U=3l$w$&R?GluJ^J3M5 zHTf~{0Bx3aLGu^wm#Nn{qAvduYOJ~c5mw_5gJweQtLA6zRwgGUTAHofnwly{S*Dj^ zy8b>Jra65xtYt$257RF&M{u6-9i4vdG@l+D@ek3Htod>_{$B$ zQ>=!;mSE5Xa9XL^+ch@v<2$dscx>*>by3{Ig*$XlVE5aZ{i{+Kpwbmtj?|~%*Tqb`2w5TCQD5&)fkT7ziOAD$knK$-E^wL)p$?4sY{8g5u$yt z^3X_<)2abERLss$8E44#)mpyda)qj}GX>PpPFJ;(Qn7*=I=Yb=2?`7;cuc`7I^ph0 zoq*;~I=UKAT^6~iU!^e_bKb&nuU$q;)a)lH_({P`iG;maO@H1z6MQ}4nPmjywTVt$ zfztz4(|9`86OO3CMM-hI&$aq)T>;hB%NdN)g6hWvtxl?huhJH!dW*g+R@_xI&bB;619ZRDtYaX%u}-#(_&^(WAwCbrU*)rt|HYsHveOr<*Y zmMWW?y{nCby-TR#pV6j@e?+ut>I_-#U4mL(Fpj2MbWqt|oSUuu;j&Tjb{7?a7w zW@-n7Z{r<%Dv5{(&__mHubQbhC$gSt&a&3&+f(g(8FdwI=`J*Mtc5poMvU#35`H@E zcFZO?9o5S(HKH_B9JXf~b<{_u*ntf{WY z=n1_P@tzWMQ&Zib(H4J3_l%UNjV>Fq>F|-XHdj99+g%oUy9CQi_ Date: Wed, 28 Sep 2016 21:50:48 +0200 Subject: [PATCH 06/12] Implement Bankwise refresh. Add the missing reference file (test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh.out ) for REFB unit test.( missed in previous commit). --- ...b_DDR3_1600_8bit_G_3s_bankwise_refresh.out | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh.out diff --git a/test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh.out b/test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh.out new file mode 100644 index 00000000..630a859e --- /dev/null +++ b/test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh.out @@ -0,0 +1,74 @@ +* Parsing memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml +* Analysis start time: Wed Sep 28 18:08:55 2016 +* Analyzing the input trace +* Bankwise mode: disabled +* Partial Array Self-Refresh: disabled + +* Trace Details: + +#ACT commands: 1502 +#RD + #RDA commands: 1499 +#WR + #WRA commands: 3 +#PRE (+ PREA) commands: 1502 +#REF commands: 36 +#REFB commands: 9 +#Active Cycles: 41856 + #Active Idle Cycles: 8022 + #Active Power-Up Cycles: 0 + #Auto-Refresh Active cycles during Self-Refresh Power-Up: 0 +#Precharged Cycles: 73651 + #Precharged Idle Cycles: 61061 + #Precharged Power-Up Cycles: 0 + #Auto-Refresh Precharged cycles during Self-Refresh Power-Up: 0 + #Self-Refresh Power-Up Cycles: 0 +Total Idle Cycles (Active + Precharged): 69083 +#Power-Downs: 0 + #Active Fast-exit Power-Downs: 0 + #Active Slow-exit Power-Downs: 0 + #Precharged Fast-exit Power-Downs: 0 + #Precharged Slow-exit Power-Downs: 0 +#Power-Down Cycles: 0 + #Active Fast-exit Power-Down Cycles: 0 + #Active Slow-exit Power-Down Cycles: 0 + #Auto-Refresh Active cycles during Self-Refresh: 0 + #Precharged Fast-exit Power-Down Cycles: 0 + #Precharged Slow-exit Power-Down Cycles: 0 + #Auto-Refresh Precharged cycles during Self-Refresh: 0 +#Auto-Refresh Cycles: 3168 +#Self-Refreshes: 0 +#Self-Refresh Cycles: 0 +---------------------------------------- +Total Trace Length (clock cycles): 115507 +---------------------------------------- + +* Trace Power and Energy Estimates: + +ACT Cmd Energy: 1977683.40 pJ +PRE Cmd Energy: 707442.00 pJ +RD Cmd Energy: 1011262.87 pJ +WR Cmd Energy: 2101.50 pJACT Stdby Energy: 3273400.80 pJ + Active Idle Energy: 627370.54 pJ + Active Power-Up Energy: 0.00 pJ + Active Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ +PRE Stdby Energy: 5754444.69 pJ + Precharge Idle Energy: 4770772.26 pJ + Precharged Power-Up Energy: 0.00 pJ + Precharge Stdby Energy during Auto-Refresh cycles in Self-Refresh Power-Up: 0.00 pJ + Self-Refresh Power-Up Energy: 0.00 pJ +Total Idle Energy (Active + Precharged): 5398142.79 pJ +Total Power-Down Energy: 0.00 pJ + Fast-Exit Active Power-Down Energy: 0.00 pJ + Slow-Exit Active Power-Down Energy: 0.00 pJ + Slow-Exit Active Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ + Fast-Exit Precharged Power-Down Energy: 0.00 pJ + Slow-Exit Precharged Power-Down Energy: 0.00 pJ + Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: 0.00 pJ +Auto-Refresh Energy: 719571.60 pJ +Bankwise-Refresh Energy: 16082.55 pJ +Self-Refresh Energy: 0.00 pJ +---------------------------------------- +Total Trace Energy: 13461989.42 pJ +Average Power: 93.24 mW +---------------------------------------- +* Power Computation End time: Wed Sep 28 18:08:55 2016 +* Total Simulation time: 0.021644 seconds From 1b4acc3c45201a1f36fe5db7de4cb4016f3e2c5f Mon Sep 17 00:00:00 2001 From: Subash Kannoth Date: Fri, 30 Sep 2016 17:22:07 +0200 Subject: [PATCH 07/12] Review suggestions. 1) Removed the redundant variables numberofpres,numberofreads and numberofwrites and adapted the unit test accordingly. 2) Simplified the calculation of ione. --- src/CommandAnalysis.cc | 13 ++------ src/CommandAnalysis.h | 11 +++---- src/MemoryPowerModel.cc | 49 +++++++++++++++---------------- src/MemoryPowerModel.h | 2 +- test/libdrampowertest/lib_test.cc | 8 +++-- 5 files changed, 38 insertions(+), 45 deletions(-) diff --git a/src/CommandAnalysis.cc b/src/CommandAnalysis.cc index 11678990..d8e6e49c 100644 --- a/src/CommandAnalysis.cc +++ b/src/CommandAnalysis.cc @@ -88,9 +88,6 @@ void CommandAnalysis::clearStats(const int64_t timestamp) std::fill(numberofwritesBanks.begin(), numberofwritesBanks.end(), 0); std::fill(actcyclesBanks.begin(), actcyclesBanks.end(), 0); - numberofpres = 0; - numberofreads = 0; - numberofwrites = 0; numberofrefs = 0; f_act_pdns = 0; s_act_pdns = 0; @@ -257,7 +254,6 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, if (bank_state[bank] == BANK_PRECHARGED) { printWarning("Bank is not active!", type, timestamp, bank); } - numberofreads++; numberofreadsBanks[bank]++; idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); @@ -269,7 +265,6 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, if (bank_state[bank] == BANK_PRECHARGED) { printWarning("Bank is not active!", type, timestamp, bank); } - numberofwrites++; numberofwritesBanks[bank]++; idle_act_update(memSpec, latest_read_cycle, latest_write_cycle, latest_act_cycle, timestamp); @@ -297,7 +292,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, for (auto& bs : bank_state) { bs = BANK_PRECHARGED; } - } else if (type == MemCommand::REFB){ + } else if (type == MemCommand::REFB) { // A REFB command requires a previous PRE command. if (bank_state[bank] == BANK_PRECHARGED) { // This previous PRE command handler is also responsible @@ -309,7 +304,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // Length of the refresh : here we have an approximation, we consider tRP // also as act cycles because the bank will be precharged (stable) after tRP. actcyclesBanks[bank] += memSpec.memTimingSpec.RAS + memSpec.memTimingSpec.RP; - }else{ + } else { printWarning("Bank must be precharged for REFB!", type, timestamp, bank); } } else if (type == MemCommand::PRE) { @@ -324,7 +319,6 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // Precharge only if the target bank is active if (bank_state[bank] == BANK_ACTIVE) { - numberofpres++; numberofpresBanks[bank]++; actcyclesBanks[bank] += max(zero, timestamp - first_act_cycle_banks[bank]); // Since we got here, at least one bank is active @@ -355,8 +349,6 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, // active state before, but there is a state transition to PRE now. if (num_active_banks > 0) { - // Active banks are being precharged - numberofpres += num_active_banks; // At least one bank was active, therefore the current memory state is // ACT. Since all banks are being precharged a memory state transition // to PRE is happening. Add to the counter the amount of cycles the @@ -366,6 +358,7 @@ void CommandAnalysis::evaluate(const MemorySpecification& memSpec, for (unsigned b = 0; b < num_banks; b++) { if (bank_state[b] == BANK_ACTIVE) { + // Active banks are being precharged numberofpresBanks[b] += 1; actcyclesBanks[b] += max(zero, timestamp - first_act_cycle_banks[b]); } diff --git a/src/CommandAnalysis.h b/src/CommandAnalysis.h index 2a89794c..a27343d4 100644 --- a/src/CommandAnalysis.h +++ b/src/CommandAnalysis.h @@ -61,16 +61,13 @@ class CommandAnalysis { // Returns number of reads, writes, acts, pres and refs in the trace CommandAnalysis(const int64_t nbrofBanks); - // Number of activate commands per banks + // Number of activate commands per bank std::vector numberofactsBanks; - // Number of precharge commands - int64_t numberofpres; + // Number of precharge commands per bank std::vector numberofpresBanks; - // Number of reads commands - int64_t numberofreads; + // Number of reads commands per bank std::vector numberofreadsBanks; - // Number of writes commands - int64_t numberofwrites; + // Number of writes commands per bank std::vector numberofwritesBanks; // Number of refresh commands int64_t numberofrefs; diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index f74d1b38..4cd1a491 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -135,13 +135,13 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, double ddrPeriod = t.clkPeriod / static_cast(memArchSpec.dataRate); // Read IO power is consumed by each DQ (data) and DQS (data strobe) pin - energy.read_io_energy = calcIoTermEnergy(c.numberofreads * memArchSpec.burstLength, + energy.read_io_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength, ddrPeriod, power.IO_power, dqPlusDqsBits); // Write ODT power is consumed by each DQ (data), DQS (data strobe) and DM - energy.write_term_energy = calcIoTermEnergy(c.numberofwrites * memArchSpec.burstLength, + energy.write_term_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength, ddrPeriod, power.WR_ODT_power, dqPlusDqsPlusMaskBits); @@ -149,14 +149,14 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, if (memArchSpec.nbrOfRanks > 1) { // Termination power consumed in the idle rank during reads on the active // rank by each DQ (data) and DQS (data strobe) pin. - energy.read_oterm_energy = calcIoTermEnergy(c.numberofreads * memArchSpec.burstLength, + energy.read_oterm_energy = calcIoTermEnergy(sum(c.numberofreadsBanks) * memArchSpec.burstLength, ddrPeriod, power.TermRD_power, dqPlusDqsBits); // Termination power consumed in the idle rank during writes on the active // rank by each DQ (data), DQS (data strobe) and DM (data mask) pin. - energy.write_oterm_energy = calcIoTermEnergy(c.numberofwrites * memArchSpec.burstLength, + energy.write_oterm_energy = calcIoTermEnergy(sum(c.numberofwritesBanks) * memArchSpec.burstLength, ddrPeriod, power.TermWR_power, dqPlusDqsPlusMaskBits); @@ -175,10 +175,10 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, EnergyDomain vdd0Domain(mps.vdd, t.clkPeriod); - energy.act_energy = vdd0Domain.calcTivEnergy(total(c.numberofactsBanks) * t.RAS , mps.idd0 - mps.idd3n); - energy.pre_energy = vdd0Domain.calcTivEnergy(c.numberofpres * (t.RC - t.RAS) , mps.idd0 - mps.idd2n); - energy.read_energy = vdd0Domain.calcTivEnergy(c.numberofreads * burstCc , mps.idd4r - mps.idd3n); - energy.write_energy = vdd0Domain.calcTivEnergy(c.numberofwrites * burstCc , mps.idd4w - mps.idd3n); + energy.act_energy = vdd0Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd0 - mps.idd3n); + energy.pre_energy = vdd0Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd0 - mps.idd2n); + energy.read_energy = vdd0Domain.calcTivEnergy(sum(c.numberofreadsBanks) * burstCc , mps.idd4r - mps.idd3n); + energy.write_energy = vdd0Domain.calcTivEnergy(sum(c.numberofwritesBanks) * burstCc , mps.idd4w - mps.idd3n); energy.ref_energy = vdd0Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd5 - mps.idd3n); energy.pre_stdby_energy = vdd0Domain.calcTivEnergy(c.precycles, mps.idd2n); energy.act_stdby_energy = vdd0Domain.calcTivEnergy(c.actcycles, mps.idd3n); @@ -190,11 +190,10 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // Fixed componenent for PASR double iddsigma = (static_cast(bwPowerParams.bwPowerFactSigma) / 100.0) * mps.idd6; double esharedPASR = vdd0Domain.calcTivEnergy(c.sref_cycles, iddsigma); - // Active background current for a single bank - double ione = ( mps.idd3n + - ((((static_cast(bwPowerParams.bwPowerFactRho)/100.0)*(mps.idd3n -mps.idd2n)) + mps.idd2n) * - (static_cast(nbrofBanks) -1.0))) / - (static_cast(nbrofBanks)); + // ione is Active background current for a single bank. When a single bank is Active + //,all the other remainig (B-1) banks will consume a current of iddrho (based on factor Rho) + // So to derrive ione we add (B-1)*iddrho to the idd3n and distribute it to each banks. + double ione = (mps.idd3n + (iddrho * (static_cast(nbrofBanks - 1)))) / (static_cast(nbrofBanks)); // If memory specification does not provide bank wise refresh current, // approximate it to single bank background current removed from // single bank active current @@ -279,10 +278,10 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, if (memArchSpec.twoVoltageDomains) { EnergyDomain vdd2Domain(mps.vdd2, t.clkPeriod); - energy.act_energy += vdd2Domain.calcTivEnergy(total(c.numberofactsBanks) * t.RAS , mps.idd02 - mps.idd3n2); - energy.pre_energy += vdd2Domain.calcTivEnergy(c.numberofpres * (t.RC - t.RAS) , mps.idd02 - mps.idd2n2); - energy.read_energy += vdd2Domain.calcTivEnergy(c.numberofreads * burstCc , mps.idd4r2 - mps.idd3n2); - energy.write_energy += vdd2Domain.calcTivEnergy(c.numberofwrites * burstCc , mps.idd4w2 - mps.idd3n2); + energy.act_energy += vdd2Domain.calcTivEnergy(sum(c.numberofactsBanks) * t.RAS , mps.idd02 - mps.idd3n2); + energy.pre_energy += vdd2Domain.calcTivEnergy(sum(c.numberofpresBanks) * (t.RC - t.RAS) , mps.idd02 - mps.idd2n2); + energy.read_energy += vdd2Domain.calcTivEnergy(sum(c.numberofreadsBanks) * burstCc , mps.idd4r2 - mps.idd3n2); + energy.write_energy += vdd2Domain.calcTivEnergy(sum(c.numberofwritesBanks) * burstCc , mps.idd4w2 - mps.idd3n2); energy.ref_energy += vdd2Domain.calcTivEnergy(c.numberofrefs * t.RFC , mps.idd52 - mps.idd3n2); energy.pre_stdby_energy += vdd2Domain.calcTivEnergy(c.precycles, mps.idd2n2); energy.act_stdby_energy += vdd2Domain.calcTivEnergy(c.actcycles, mps.idd3n2); @@ -340,11 +339,11 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, + energy.s_pre_pd_energy_banks[i]+ energy.sref_ref_energy_banks[i] + energy.spup_ref_energy_banks[i]; } // Calculate total energy for all banks. - energy.total_energy = total(energy.total_energy_banks) + energy.io_term_energy; + energy.total_energy = sum(energy.total_energy_banks) + energy.io_term_energy; } else { energy.total_energy = energy.act_energy + energy.pre_energy + energy.read_energy + energy.write_energy - + energy.ref_energy + energy.io_term_energy + total(energy.refb_energy_banks) + + energy.ref_energy + energy.io_term_energy + sum(energy.refb_energy_banks) + static_cast(memArchSpec.nbrOfRanks) * (energy.act_stdby_energy + energy.pre_stdby_energy + energy.sref_energy + energy.f_act_pd_energy + energy.f_pre_pd_energy + energy.s_act_pd_energy + energy.s_pre_pd_energy @@ -381,13 +380,13 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, } cout << endl << "* Trace Details:" << fixed << endl - << endl << "#ACT commands: " << total(c.numberofactsBanks) - << endl << "#RD + #RDA commands: " << c.numberofreads - << endl << "#WR + #WRA commands: " << c.numberofwrites + << endl << "#ACT commands: " << sum(c.numberofactsBanks) + << endl << "#RD + #RDA commands: " << sum(c.numberofreadsBanks) + << endl << "#WR + #WRA commands: " << sum(c.numberofwritesBanks) /* #PRE commands (precharge all counts a number of #PRE commands equal to the number of active banks) */ - << endl << "#PRE (+ PREA) commands: " << c.numberofpres + << endl << "#PRE (+ PREA) commands: " << sum(c.numberofpresBanks) << endl << "#REF commands: " << c.numberofrefs - << endl << "#REFB commands: " << total(c.numberofrefbBanks) + << endl << "#REFB commands: " << sum(c.numberofrefbBanks) << endl << "#Active Cycles: " << c.actcycles << endl << " #Active Idle Cycles: " << c.idlecycles_act << endl << " #Active Power-Up Cycles: " << c.pup_act_cycles @@ -487,7 +486,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, << endl << " Slow-Exit Precharged Power-Down Energy: " << nRanksDouble * energy.s_pre_pd_energy << eUnit << endl << " Slow-Exit Precharged Power-Down Energy during Auto-Refresh cycles in Self-Refresh: " << nRanksDouble * energy.sref_ref_pre_energy << eUnit << endl << "Auto-Refresh Energy: " << energy.ref_energy << eUnit - << endl << "Bankwise-Refresh Energy: " << total(energy.refb_energy_banks) << eUnit + << endl << "Bankwise-Refresh Energy: " << sum(energy.refb_energy_banks) << eUnit << endl << "Self-Refresh Energy: " << nRanksDouble * energy.sref_energy << eUnit << endl << "----------------------------------------" << endl << "Total Trace Energy: " << energy.total_energy << eUnit diff --git a/src/MemoryPowerModel.h b/src/MemoryPowerModel.h index 291e3d6f..e8b19749 100644 --- a/src/MemoryPowerModel.h +++ b/src/MemoryPowerModel.h @@ -211,7 +211,7 @@ class MemoryPowerModel { private: double calcIoTermEnergy(int64_t cycles, double period, double power, int64_t numBits) const; // Sum quantities (e.g., operations, energy, cycles) that are stored in a per bank basis returning the total amount. - template T total(const std::vector vec) const { return std::accumulate(vec.begin(), vec.end(), static_cast(0)); } + template T sum(const std::vector vec) const { return std::accumulate(vec.begin(), vec.end(), static_cast(0)); } }; class EnergyDomain { diff --git a/test/libdrampowertest/lib_test.cc b/test/libdrampowertest/lib_test.cc index b0cdd61b..ea83eef0 100644 --- a/test/libdrampowertest/lib_test.cc +++ b/test/libdrampowertest/lib_test.cc @@ -112,8 +112,12 @@ int main(int argc, char* argv[]) std::cout << "# of acts" << "\t" < Date: Sun, 2 Oct 2016 22:02:13 +0200 Subject: [PATCH 08/12] Add bank-wise unit tests. Update the unit tests for bank-wise components. --- test/data/PASR.commands.trace | 3059 +++++++++++++++++ test/data/REFB.commands.trace | 3050 ++++++++++++++++ test/data/REFB.commands.trace.gz | Bin 10279 -> 0 bytes ...1600_8bit_G_Sigma_100_pasr_0_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_1_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_2_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_3_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_4_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_5_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_6_reference.out | 317 ++ ...1600_8bit_G_Sigma_100_pasr_7_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_0_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_1_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_2_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_3_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_4_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_5_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_6_reference.out | 317 ++ ...-1600_8bit_G_Sigma_25_pasr_7_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_0_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_1_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_2_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_3_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_4_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_5_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_6_reference.out | 317 ++ ...-1600_8bit_G_Sigma_50_pasr_7_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_0_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_1_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_2_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_3_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_4_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_5_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_6_reference.out | 317 ++ ...-1600_8bit_G_Sigma_75_pasr_7_reference.out | 317 ++ ...0_8bit_G_3s_bankwise_Rho_100_reference.out | 318 ++ ...00_8bit_G_3s_bankwise_Rho_25_reference.out | 318 ++ ...00_8bit_G_3s_bankwise_Rho_50_reference.out | 318 ++ ...00_8bit_G_3s_bankwise_Rho_75_reference.out | 318 ++ test/test.py | 222 +- 40 files changed, 17741 insertions(+), 6 deletions(-) create mode 100644 test/data/PASR.commands.trace create mode 100644 test/data/REFB.commands.trace delete mode 100644 test/data/REFB.commands.trace.gz create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_0_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_1_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_2_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_3_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_4_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_5_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_6_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_7_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_0_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_1_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_2_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_3_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_4_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_5_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_6_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_7_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_0_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_1_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_2_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_3_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_4_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_5_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_6_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_7_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_0_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_1_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_2_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_3_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_4_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_5_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_6_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_7_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_Rho_100_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_Rho_25_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_Rho_50_reference.out create mode 100644 test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_Rho_75_reference.out diff --git a/test/data/PASR.commands.trace b/test/data/PASR.commands.trace new file mode 100644 index 00000000..b96ee098 --- /dev/null +++ b/test/data/PASR.commands.trace @@ -0,0 +1,3059 @@ +35,ACT,0 +50,RDA,0 +51,ACT,4 +66,RDA,4 +86,ACT,0 +101,RDA,0 +102,ACT,2 +117,RDA,2 +119,ACT,5 +134,RDA,5 +137,ACT,0 +152,RDA,0 +171,PREA,0 +173,SREN,0 +1174,SREX,0 +1279,ACT,3 +1294,RDA,3 +1315,ACT,0 +1330,RDA,0 +1352,ACT,4 +1367,RDA,4 +1368,ACT,3 +1383,RDA,3 +1403,ACT,4 +1418,RDA,4 +1454,ACT,4 +1469,RDA,4 +1505,ACT,4 +1520,RDA,4 +1556,ACT,4 +1571,RDA,4 +1607,ACT,4 +1622,RDA,4 +1658,ACT,4 +1673,RDA,4 +1709,ACT,4 +1724,RDA,4 +1760,ACT,4 +1775,RDA,4 +1811,ACT,4 +1826,RDA,4 +1862,ACT,4 +1877,RDA,4 +1913,ACT,4 +1928,RDA,4 +1929,ACT,0 +1944,RDA,0 +1945,ACT,2 +1960,RDA,2 +1980,ACT,0 +1995,RDA,0 +2031,ACT,0 +2046,RDA,0 +2047,ACT,1 +2062,RDA,1 +2098,ACT,1 +2113,RDA,1 +2149,ACT,1 +2164,RDA,1 +2200,ACT,1 +2215,RDA,1 +2216,ACT,2 +2231,RDA,2 +2252,PREA,2 +2255,SREN,2 +3260,SREX,2 +3371,ACT,1 +3386,RDA,1 +3422,ACT,1 +3437,RDA,1 +3438,ACT,0 +3453,RDA,0 +3489,ACT,0 +3504,RDA,0 +3505,ACT,1 +3520,RDA,1 +3521,ACT,3 +3536,RDA,3 +3540,ACT,0 +3555,RDA,0 +3591,ACT,0 +3606,RDA,0 +3642,ACT,0 +3657,RDA,0 +3693,ACT,0 +3708,RDA,0 +3709,ACT,1 +3724,RDA,1 +3744,ACT,0 +3759,RDA,0 +3795,ACT,0 +3810,RDA,0 +3846,ACT,0 +3861,RDA,0 +3897,ACT,0 +3912,RDA,0 +3913,ACT,5 +3928,RDA,5 +3964,ACT,5 +3979,RDA,5 +3980,ACT,3 +3995,RDA,3 +4015,ACT,5 +4030,RDA,5 +4066,ACT,5 +4081,RDA,5 +4082,ACT,3 +4097,RDA,3 +4117,ACT,5 +4132,RDA,5 +4133,ACT,1 +4148,RDA,1 +4184,ACT,1 +4199,RDA,1 +4235,ACT,1 +4250,RDA,1 +4251,ACT,2 +4266,RDA,2 +4267,ACT,5 +4282,RDA,5 +4318,ACT,5 +4333,RDA,5 +4369,ACT,5 +4384,RDA,5 +4420,ACT,5 +4435,RDA,5 +4436,ACT,1 +4451,RDA,1 +4452,ACT,2 +4467,RDA,2 +4488,PREA,2 +4490,SREN,2 +5495,SREX,2 +5607,ACT,1 +5622,RDA,1 +5658,ACT,1 +5673,RDA,1 +5709,ACT,1 +5724,RDA,1 +5760,ACT,1 +5775,RDA,1 +5811,ACT,1 +5826,RDA,1 +5862,ACT,1 +5877,RDA,1 +5913,ACT,1 +5928,RDA,1 +5929,ACT,6 +5944,RDA,6 +5945,ACT,2 +5960,RDA,2 +5980,ACT,6 +5995,RDA,6 +6031,ACT,6 +6046,RDA,6 +6047,ACT,2 +6062,RDA,2 +6063,ACT,5 +6078,RDA,5 +6114,ACT,5 +6129,RDA,5 +6130,ACT,2 +6145,RDA,2 +6181,ACT,2 +6196,RDA,2 +6197,ACT,3 +6212,RDA,3 +6213,ACT,7 +6228,RDA,7 +6264,ACT,7 +6279,RDA,7 +6280,ACT,2 +6295,RDA,2 +6296,ACT,1 +6311,RDA,1 +6347,ACT,1 +6362,RDA,1 +6363,ACT,7 +6378,RDA,7 +6379,ACT,2 +6394,RDA,2 +6395,ACT,5 +6410,RDA,5 +6446,ACT,5 +6461,RDA,5 +6497,ACT,5 +6512,RDA,5 +6548,REF,0 +6652,ACT,1 +6667,RDA,1 +6703,ACT,1 +6718,RDA,1 +6719,ACT,3 +6734,RDA,3 +6754,ACT,1 +6769,RDA,1 +6770,ACT,3 +6785,RDA,3 +6821,ACT,3 +6836,RDA,3 +6872,ACT,3 +6887,RDA,3 +6923,ACT,3 +6938,RDA,3 +6974,ACT,3 +6989,RDA,3 +7025,ACT,3 +7040,RDA,3 +7076,ACT,3 +7091,RDA,3 +7127,ACT,3 +7142,RDA,3 +7178,ACT,3 +7193,RDA,3 +7229,ACT,3 +7244,RDA,3 +7280,ACT,3 +7295,RDA,3 +7331,ACT,3 +7346,RDA,3 +7382,ACT,3 +7397,RDA,3 +7433,ACT,3 +7448,RDA,3 +7484,ACT,3 +7499,RDA,3 +7535,ACT,3 +7550,RDA,3 +7586,ACT,3 +7601,RDA,3 +7637,ACT,3 +7652,RDA,3 +7688,ACT,3 +7703,RDA,3 +7739,ACT,3 +7754,RDA,3 +7790,ACT,3 +7805,RDA,3 +7841,ACT,3 +7856,RDA,3 +7892,ACT,3 +7907,RDA,3 +7943,ACT,3 +7958,RDA,3 +7994,ACT,3 +8009,RDA,3 +8045,ACT,3 +8060,RDA,3 +8096,ACT,3 +8111,RDA,3 +8147,ACT,3 +8162,RDA,3 +8198,ACT,3 +8213,RDA,3 +8249,ACT,3 +8264,RDA,3 +8300,ACT,3 +8315,RDA,3 +8351,ACT,3 +8366,RDA,3 +8402,ACT,3 +8417,RDA,3 +8453,ACT,3 +8468,RDA,3 +8504,ACT,3 +8519,RDA,3 +8555,ACT,3 +8570,RDA,3 +8606,ACT,3 +8621,RDA,3 +8657,ACT,3 +8672,RDA,3 +8708,ACT,3 +8723,RDA,3 +8759,ACT,3 +8774,RDA,3 +8810,ACT,3 +8825,RDA,3 +8861,ACT,3 +8876,RDA,3 +8912,ACT,3 +8927,RDA,3 +8963,ACT,3 +8978,RDA,3 +9014,ACT,3 +9029,RDA,3 +9065,ACT,3 +9080,RDA,3 +9116,ACT,3 +9131,RDA,3 +9167,ACT,3 +9182,RDA,3 +9218,ACT,3 +9233,RDA,3 +9269,ACT,3 +9284,RDA,3 +9320,ACT,3 +9335,RDA,3 +9371,ACT,3 +9386,RDA,3 +9422,ACT,3 +9437,RDA,3 +9473,ACT,3 +9488,RDA,3 +9524,ACT,3 +9539,RDA,3 +9575,ACT,3 +9590,RDA,3 +9626,ACT,3 +9641,RDA,3 +9662,PREA,3 +9665,SREN,3 +10670,SREX,3 +10797,REF,0 +10901,ACT,3 +10916,RDA,3 +10952,ACT,3 +10967,RDA,3 +11003,ACT,3 +11018,RDA,3 +11054,ACT,3 +11069,RDA,3 +11105,ACT,3 +11120,RDA,3 +11156,ACT,3 +11171,RDA,3 +11172,ACT,4 +11187,RDA,4 +11223,ACT,4 +11238,RDA,4 +11274,ACT,4 +11289,RDA,4 +11325,ACT,4 +11340,RDA,4 +11376,ACT,4 +11391,RDA,4 +11427,ACT,4 +11442,RDA,4 +11478,ACT,4 +11493,RDA,4 +11529,ACT,4 +11544,RDA,4 +11580,ACT,4 +11595,RDA,4 +11631,ACT,4 +11646,RDA,4 +11682,ACT,4 +11697,RDA,4 +11733,ACT,4 +11748,RDA,4 +11784,ACT,4 +11799,RDA,4 +11835,ACT,4 +11850,RDA,4 +11886,ACT,4 +11901,RDA,4 +11937,ACT,4 +11952,RDA,4 +11988,ACT,4 +12003,RDA,4 +12039,ACT,4 +12054,RDA,4 +12090,ACT,4 +12105,RDA,4 +12141,ACT,4 +12156,RDA,4 +12192,ACT,4 +12207,RDA,4 +12243,ACT,4 +12258,RDA,4 +12294,ACT,4 +12309,RDA,4 +12345,ACT,4 +12360,RDA,4 +12396,ACT,4 +12411,RDA,4 +12447,ACT,4 +12462,RDA,4 +12498,ACT,4 +12513,RDA,4 +12549,ACT,4 +12564,RDA,4 +12600,ACT,4 +12615,RDA,4 +12651,ACT,4 +12666,RDA,4 +12702,ACT,4 +12717,RDA,4 +12753,ACT,4 +12768,RDA,4 +12804,ACT,4 +12819,RDA,4 +12855,ACT,4 +12870,RDA,4 +12906,ACT,4 +12921,RDA,4 +12957,ACT,4 +12972,RDA,4 +13008,ACT,4 +13023,RDA,4 +13059,ACT,4 +13074,RDA,4 +13110,ACT,4 +13125,RDA,4 +13161,ACT,4 +13176,RDA,4 +13212,ACT,4 +13227,RDA,4 +13263,ACT,4 +13278,RDA,4 +13314,ACT,4 +13329,RDA,4 +13365,ACT,4 +13380,RDA,4 +13416,ACT,4 +13431,RDA,4 +13467,ACT,4 +13482,RDA,4 +13518,ACT,4 +13533,RDA,4 +13569,ACT,4 +13584,RDA,4 +13620,ACT,4 +13635,RDA,4 +13671,ACT,4 +13686,RDA,4 +13722,ACT,4 +13737,RDA,4 +13773,ACT,4 +13788,RDA,4 +13824,ACT,4 +13839,RDA,4 +13861,PREA,4 +13870,SREN,4 +14877,SREX,4 +14995,REF,0 +15099,ACT,4 +15114,RDA,4 +15150,ACT,4 +15165,RDA,4 +15201,ACT,4 +15216,RDA,4 +15252,ACT,4 +15267,RDA,4 +15303,ACT,4 +15318,RDA,4 +15354,ACT,4 +15369,RDA,4 +15405,ACT,4 +15420,RDA,4 +15456,ACT,4 +15471,RDA,4 +15507,ACT,4 +15522,RDA,4 +15558,ACT,4 +15573,RDA,4 +15609,ACT,4 +15624,RDA,4 +15660,ACT,4 +15675,RDA,4 +15711,ACT,4 +15726,RDA,4 +15762,ACT,4 +15777,RDA,4 +15813,ACT,4 +15828,RDA,4 +15864,ACT,4 +15879,RDA,4 +15915,ACT,4 +15930,RDA,4 +15966,ACT,4 +15981,RDA,4 +16017,ACT,4 +16032,RDA,4 +16068,ACT,4 +16083,RDA,4 +16119,ACT,4 +16134,RDA,4 +16170,ACT,4 +16185,RDA,4 +16221,ACT,4 +16236,RDA,4 +16272,ACT,4 +16287,RDA,4 +16323,ACT,4 +16338,RDA,4 +16374,ACT,4 +16389,RDA,4 +16425,ACT,4 +16440,RDA,4 +16476,ACT,4 +16491,RDA,4 +16527,ACT,4 +16542,RDA,4 +16578,ACT,4 +16593,RDA,4 +16629,ACT,4 +16644,RDA,4 +16680,ACT,4 +16695,RDA,4 +16731,ACT,4 +16746,RDA,4 +16782,ACT,4 +16797,RDA,4 +16833,ACT,4 +16848,RDA,4 +16884,ACT,4 +16899,RDA,4 +16935,ACT,4 +16950,RDA,4 +16986,ACT,4 +17001,RDA,4 +17037,ACT,4 +17052,RDA,4 +17088,ACT,4 +17103,RDA,4 +17139,ACT,4 +17154,RDA,4 +17190,ACT,4 +17205,RDA,4 +17241,ACT,4 +17256,RDA,4 +17292,ACT,4 +17307,RDA,4 +17343,ACT,4 +17358,RDA,4 +17394,ACT,4 +17409,RDA,4 +17445,ACT,4 +17460,RDA,4 +17496,ACT,4 +17511,RDA,4 +17547,ACT,4 +17562,RDA,4 +17598,ACT,4 +17613,RDA,4 +17649,ACT,4 +17664,RDA,4 +17700,ACT,4 +17715,RDA,4 +17751,ACT,4 +17766,RDA,4 +17802,ACT,4 +17817,RDA,4 +17853,ACT,4 +17868,RDA,4 +17904,ACT,4 +17919,RDA,4 +17955,ACT,4 +17970,RDA,4 +18006,ACT,4 +18021,RDA,4 +18057,ACT,4 +18072,RDA,4 +18108,ACT,4 +18123,RDA,4 +18159,REF,0 +18263,ACT,4 +18278,RDA,4 +18314,ACT,4 +18329,RDA,4 +18365,ACT,4 +18380,RDA,4 +18416,ACT,4 +18431,RDA,4 +18467,ACT,4 +18482,RDA,4 +18518,ACT,4 +18533,RDA,4 +18569,ACT,4 +18584,RDA,4 +18620,ACT,4 +18635,RDA,4 +18671,ACT,4 +18686,RDA,4 +18722,ACT,4 +18737,RDA,4 +18773,ACT,4 +18788,RDA,4 +18824,ACT,4 +18839,RDA,4 +18875,ACT,4 +18890,RDA,4 +18926,ACT,4 +18941,RDA,4 +18977,ACT,4 +18992,RDA,4 +18993,ACT,5 +19008,RDA,5 +19009,ACT,6 +19024,RDA,6 +19060,ACT,6 +19075,RDA,6 +19111,ACT,6 +19126,RDA,6 +19162,ACT,6 +19177,RDA,6 +19178,ACT,3 +19193,RDA,3 +19213,ACT,6 +19228,RDA,6 +19264,ACT,6 +19279,RDA,6 +19315,ACT,6 +19330,RDA,6 +19366,ACT,6 +19381,RDA,6 +19417,ACT,6 +19432,RDA,6 +19468,ACT,6 +19483,RDA,6 +19519,ACT,6 +19534,RDA,6 +19535,ACT,3 +19550,RDA,3 +19570,ACT,6 +19585,RDA,6 +19621,ACT,6 +19636,RDA,6 +19672,ACT,6 +19687,RDA,6 +19723,ACT,6 +19738,RDA,6 +19774,ACT,6 +19789,RDA,6 +19825,ACT,6 +19840,RDA,6 +19876,ACT,6 +19891,RDA,6 +19927,ACT,6 +19942,RDA,6 +19978,ACT,6 +19993,RDA,6 +20029,ACT,6 +20044,RDA,6 +20080,ACT,6 +20095,RDA,6 +20131,ACT,6 +20146,RDA,6 +20182,ACT,6 +20197,RDA,6 +20198,ACT,5 +20213,RDA,5 +20233,ACT,6 +20248,RDA,6 +20249,ACT,5 +20264,RDA,5 +20300,ACT,5 +20315,RDA,5 +20351,ACT,5 +20366,RDA,5 +20402,ACT,5 +20417,RDA,5 +20453,ACT,5 +20468,RDA,5 +20504,ACT,5 +20519,RDA,5 +20555,ACT,5 +20570,RDA,5 +20606,ACT,5 +20621,RDA,5 +20657,ACT,5 +20672,RDA,5 +20708,ACT,5 +20723,RDA,5 +20759,ACT,5 +20774,RDA,5 +20810,ACT,5 +20825,RDA,5 +20861,ACT,5 +20876,RDA,5 +20912,ACT,5 +20927,RDA,5 +20963,ACT,5 +20978,RDA,5 +21014,ACT,5 +21029,RDA,5 +21065,ACT,5 +21080,RDA,5 +21116,ACT,5 +21131,RDA,5 +21167,ACT,5 +21182,RDA,5 +21218,ACT,5 +21233,RDA,5 +21269,REF,0 +21373,ACT,5 +21388,RDA,5 +21424,ACT,5 +21439,RDA,5 +21475,ACT,5 +21490,RDA,5 +21526,ACT,5 +21541,RDA,5 +21577,ACT,5 +21592,RDA,5 +21628,ACT,5 +21643,RDA,5 +21679,ACT,5 +21694,RDA,5 +21730,ACT,5 +21745,RDA,5 +21781,ACT,5 +21796,RDA,5 +21832,ACT,5 +21847,RDA,5 +21848,ACT,6 +21863,RDA,6 +21899,ACT,6 +21914,RDA,6 +21950,ACT,6 +21965,RDA,6 +21966,ACT,5 +21981,RDA,5 +21982,ACT,7 +21997,RDA,7 +22033,ACT,7 +22048,RDA,7 +22049,ACT,5 +22064,RDA,5 +22084,ACT,7 +22099,RDA,7 +22100,ACT,1 +22115,RDA,1 +22116,ACT,5 +22131,RDA,5 +22132,ACT,2 +22147,RDA,2 +22183,ACT,2 +22198,RDA,2 +22234,ACT,2 +22249,RDA,2 +22285,ACT,2 +22300,RDA,2 +22301,ACT,7 +22316,RDA,7 +22352,ACT,7 +22367,RDA,7 +22368,ACT,2 +22383,RDA,2 +22384,ACT,5 +22399,RDA,5 +22435,ACT,5 +22450,RDA,5 +22451,ACT,0 +22466,RDA,0 +22502,ACT,0 +22517,RDA,0 +22518,ACT,7 +22533,RDA,7 +22569,ACT,7 +22584,RDA,7 +22620,ACT,7 +22635,RDA,7 +22671,ACT,7 +22686,RDA,7 +22722,ACT,7 +22737,RDA,7 +22773,ACT,7 +22788,RDA,7 +22824,ACT,7 +22839,RDA,7 +22875,ACT,7 +22890,RDA,7 +22926,ACT,7 +22941,RDA,7 +22977,ACT,7 +22992,RDA,7 +23028,ACT,7 +23043,RDA,7 +23079,ACT,7 +23094,RDA,7 +23130,ACT,7 +23145,RDA,7 +23181,ACT,7 +23196,RDA,7 +23232,ACT,7 +23247,RDA,7 +23248,ACT,0 +23263,RDA,0 +23283,ACT,7 +23298,RDA,7 +23299,ACT,2 +23314,RDA,2 +23350,ACT,2 +23365,RDA,2 +23401,ACT,2 +23416,RDA,2 +23417,ACT,7 +23432,RDA,7 +23452,ACT,2 +23467,RDA,2 +23503,ACT,2 +23518,RDA,2 +23554,ACT,2 +23569,RDA,2 +23570,ACT,7 +23585,RDA,7 +23621,ACT,7 +23636,RDA,7 +23672,ACT,7 +23687,RDA,7 +23723,ACT,7 +23738,RDA,7 +23774,ACT,7 +23789,RDA,7 +23825,ACT,7 +23840,RDA,7 +23876,ACT,7 +23891,RDA,7 +23927,ACT,7 +23942,RDA,7 +23978,ACT,7 +23993,RDA,7 +24029,ACT,7 +24044,RDA,7 +24080,ACT,7 +24095,RDA,7 +24096,ACT,6 +24111,RDA,6 +24147,ACT,6 +24162,RDA,6 +24198,ACT,6 +24213,RDA,6 +24249,ACT,6 +24264,RDA,6 +24300,ACT,6 +24315,RDA,6 +24351,ACT,6 +24366,RDA,6 +24402,REF,0 +24506,ACT,6 +24521,RDA,6 +24557,ACT,6 +24572,RDA,6 +24608,ACT,6 +24623,RDA,6 +24659,ACT,6 +24674,RDA,6 +24710,ACT,6 +24725,RDA,6 +24761,ACT,6 +24776,RDA,6 +24812,ACT,6 +24827,RDA,6 +24828,ACT,2 +24843,RDA,2 +24879,ACT,2 +24894,RDA,2 +24895,ACT,7 +24910,RDA,7 +24946,ACT,7 +24961,RDA,7 +24962,ACT,2 +24977,RDA,2 +24978,ACT,6 +24993,RDA,6 +25029,ACT,6 +25044,RDA,6 +25080,ACT,6 +25095,RDA,6 +25131,ACT,6 +25146,RDA,6 +25182,ACT,6 +25197,RDA,6 +25198,ACT,1 +25213,RDA,1 +25214,ACT,7 +25229,RDA,7 +25265,ACT,7 +25280,RDA,7 +25281,ACT,6 +25296,RDA,6 +25332,ACT,6 +25347,RDA,6 +25383,ACT,6 +25398,RDA,6 +25434,ACT,6 +25449,RDA,6 +25485,ACT,6 +25500,RDA,6 +25501,ACT,5 +25516,RDA,5 +25536,ACT,6 +25551,RDA,6 +25587,ACT,6 +25602,RDA,6 +25603,ACT,7 +25618,RDA,7 +25654,ACT,7 +25669,RDA,7 +25670,ACT,2 +25685,RDA,2 +25705,ACT,7 +25720,RDA,7 +25756,ACT,7 +25771,RDA,7 +25807,ACT,7 +25822,RDA,7 +25858,ACT,7 +25873,RDA,7 +25874,ACT,2 +25889,RDA,2 +25925,ACT,2 +25940,RDA,2 +25976,ACT,2 +25991,RDA,2 +25992,ACT,7 +26007,RDA,7 +26043,ACT,7 +26058,RDA,7 +26094,ACT,7 +26109,RDA,7 +26145,ACT,7 +26160,RDA,7 +26161,ACT,3 +26176,RDA,3 +26177,ACT,5 +26192,RDA,5 +26193,ACT,0 +26208,RDA,0 +26209,ACT,7 +26224,RDA,7 +26225,ACT,2 +26240,RDA,2 +26276,ACT,2 +26291,RDA,2 +26327,ACT,2 +26342,RDA,2 +26343,ACT,7 +26358,RDA,7 +26394,ACT,7 +26409,RDA,7 +26445,ACT,7 +26460,RDA,7 +26496,ACT,7 +26511,RDA,7 +26547,ACT,7 +26562,RDA,7 +26563,ACT,2 +26578,RDA,2 +26614,ACT,2 +26629,RDA,2 +26665,ACT,2 +26680,RDA,2 +26716,ACT,2 +26731,RDA,2 +26767,ACT,2 +26782,RDA,2 +26783,ACT,3 +26798,RDA,3 +26818,ACT,2 +26833,RDA,2 +26869,ACT,2 +26884,RDA,2 +26920,ACT,2 +26935,RDA,2 +26971,ACT,2 +26986,RDA,2 +26987,ACT,1 +27002,RDA,1 +27003,ACT,7 +27018,RDA,7 +27019,ACT,4 +27034,RDA,4 +27070,ACT,4 +27085,RDA,4 +27086,ACT,3 +27101,RDA,3 +27121,ACT,4 +27136,RDA,4 +27137,ACT,3 +27152,RDA,3 +27172,ACT,4 +27187,RDA,4 +27188,ACT,2 +27203,RDA,2 +27223,ACT,4 +27238,RDA,4 +27239,ACT,2 +27254,RDA,2 +27290,ACT,2 +27305,RDA,2 +27341,ACT,2 +27356,RDA,2 +27392,ACT,2 +27407,RDA,2 +27443,ACT,2 +27458,RDA,2 +27494,REF,0 +27598,ACT,2 +27613,RDA,2 +27649,ACT,2 +27664,RDA,2 +27700,ACT,2 +27715,RDA,2 +27751,ACT,2 +27766,RDA,2 +27767,ACT,3 +27782,RDA,3 +27783,ACT,1 +27798,RDA,1 +27802,ACT,2 +27817,RDA,2 +27853,ACT,2 +27868,RDA,2 +27904,ACT,2 +27919,RDA,2 +27955,ACT,2 +27970,RDA,2 +28006,ACT,2 +28021,RDA,2 +28057,ACT,2 +28072,RDA,2 +28108,ACT,2 +28123,RDA,2 +28159,ACT,2 +28174,RDA,2 +28210,ACT,2 +28225,RDA,2 +28226,ACT,1 +28241,RDA,1 +28261,ACT,2 +28276,RDA,2 +28277,ACT,0 +28292,RDA,0 +28293,ACT,3 +28308,RDA,3 +28344,ACT,3 +28359,RDA,3 +28395,ACT,3 +28410,RDA,3 +28446,ACT,3 +28461,RDA,3 +28497,ACT,3 +28512,RDA,3 +28548,ACT,3 +28563,RDA,3 +28599,ACT,3 +28614,RDA,3 +28615,ACT,2 +28630,RDA,2 +28650,ACT,3 +28665,RDA,3 +28701,ACT,3 +28716,RDA,3 +28752,ACT,3 +28767,RDA,3 +28803,ACT,3 +28818,RDA,3 +28854,ACT,3 +28869,RDA,3 +28870,ACT,7 +28885,RDA,7 +28921,ACT,7 +28936,RDA,7 +28972,ACT,7 +28987,RDA,7 +29023,ACT,7 +29038,RDA,7 +29074,ACT,7 +29089,RDA,7 +29090,ACT,0 +29105,RDA,0 +29141,ACT,0 +29156,RDA,0 +29192,ACT,0 +29207,RDA,0 +29208,ACT,3 +29223,RDA,3 +29259,ACT,3 +29274,RDA,3 +29310,ACT,3 +29325,RDA,3 +29326,ACT,5 +29341,RDA,5 +29342,ACT,0 +29357,RDA,0 +29358,ACT,2 +29373,RDA,2 +29377,ACT,5 +29392,RDA,5 +29393,ACT,0 +29408,RDA,0 +29409,ACT,2 +29424,RDA,2 +29444,ACT,0 +29459,RDA,0 +29460,ACT,5 +29475,RDA,5 +29476,ACT,2 +29491,RDA,2 +29495,ACT,0 +29510,RDA,0 +29511,ACT,5 +29526,RDA,5 +29527,ACT,2 +29542,RDA,2 +29546,ACT,0 +29561,RDA,0 +29562,ACT,5 +29577,RDA,5 +29597,ACT,0 +29612,RDA,0 +29613,ACT,3 +29628,RDA,3 +29664,ACT,3 +29679,RDA,3 +29715,ACT,3 +29730,RDA,3 +29766,ACT,3 +29781,RDA,3 +29817,ACT,3 +29832,RDA,3 +29868,ACT,3 +29883,RDA,3 +29919,ACT,3 +29934,RDA,3 +29935,ACT,1 +29950,RDA,1 +29970,ACT,3 +29985,RDA,3 +30021,ACT,3 +30036,RDA,3 +30072,ACT,3 +30087,RDA,3 +30123,ACT,3 +30138,RDA,3 +30174,ACT,3 +30189,RDA,3 +30225,ACT,3 +30240,RDA,3 +30276,ACT,3 +30291,RDA,3 +30327,ACT,3 +30342,RDA,3 +30343,ACT,7 +30358,RDA,7 +30394,ACT,7 +30409,RDA,7 +30445,ACT,7 +30460,RDA,7 +30496,ACT,7 +30511,RDA,7 +30547,ACT,7 +30562,RDA,7 +30598,REF,0 +30702,ACT,7 +30717,RDA,7 +30753,ACT,7 +30768,RDA,7 +30804,ACT,7 +30819,RDA,7 +30855,ACT,7 +30870,RDA,7 +30906,ACT,7 +30921,RDA,7 +30957,ACT,7 +30972,RDA,7 +31008,ACT,7 +31023,RDA,7 +31059,ACT,7 +31074,RDA,7 +31110,ACT,7 +31125,RDA,7 +31161,ACT,7 +31176,RDA,7 +31177,ACT,3 +31192,RDA,3 +31228,ACT,3 +31243,RDA,3 +31279,ACT,3 +31294,RDA,3 +31330,ACT,3 +31345,RDA,3 +31381,ACT,3 +31396,RDA,3 +31432,ACT,3 +31447,RDA,3 +31483,ACT,3 +31498,RDA,3 +31534,ACT,3 +31549,RDA,3 +31585,ACT,3 +31600,RDA,3 +31601,ACT,2 +31616,RDA,2 +31617,ACT,0 +31632,RDA,0 +31636,ACT,3 +31651,RDA,3 +31687,ACT,3 +31702,RDA,3 +31703,ACT,2 +31718,RDA,2 +31719,ACT,0 +31734,RDA,0 +31735,ACT,5 +31750,RDA,5 +31770,ACT,0 +31785,RDA,0 +31786,ACT,5 +31801,RDA,5 +31821,ACT,0 +31836,RDA,0 +31872,ACT,0 +31887,RDA,0 +31888,ACT,1 +31903,RDA,1 +31904,ACT,2 +31919,RDA,2 +31955,ACT,2 +31970,RDA,2 +32006,ACT,2 +32021,RDA,2 +32022,ACT,0 +32037,RDA,0 +32073,ACT,0 +32088,RDA,0 +32089,ACT,5 +32104,RDA,5 +32105,ACT,2 +32120,RDA,2 +32124,ACT,0 +32139,RDA,0 +32175,ACT,0 +32190,RDA,0 +32191,ACT,5 +32206,RDA,5 +32207,ACT,2 +32222,RDA,2 +32226,ACT,0 +32241,RDA,0 +32242,ACT,5 +32257,RDA,5 +32277,ACT,0 +32292,RDA,0 +32328,ACT,0 +32343,RDA,0 +32344,ACT,5 +32359,RDA,5 +32379,ACT,0 +32394,RDA,0 +32395,ACT,5 +32410,RDA,5 +32446,ACT,5 +32461,RDA,5 +32462,ACT,0 +32477,RDA,0 +32478,ACT,2 +32493,RDA,2 +32513,ACT,0 +32528,RDA,0 +32529,ACT,2 +32544,RDA,2 +32545,ACT,3 +32560,RDA,3 +32596,ACT,3 +32611,RDA,3 +32647,ACT,3 +32662,RDA,3 +32698,ACT,3 +32713,RDA,3 +32749,ACT,3 +32764,RDA,3 +32800,ACT,3 +32815,RDA,3 +32851,ACT,3 +32866,RDA,3 +32902,ACT,3 +32917,RDA,3 +32953,ACT,3 +32968,RDA,3 +33004,ACT,3 +33019,RDA,3 +33055,ACT,3 +33070,RDA,3 +33071,ACT,7 +33086,RDA,7 +33122,ACT,7 +33137,RDA,7 +33173,ACT,7 +33188,RDA,7 +33189,ACT,3 +33204,RDA,3 +33224,ACT,7 +33239,RDA,7 +33275,ACT,7 +33290,RDA,7 +33326,ACT,7 +33341,RDA,7 +33377,ACT,7 +33392,RDA,7 +33428,ACT,7 +33443,RDA,7 +33479,ACT,7 +33494,RDA,7 +33530,ACT,7 +33545,RDA,7 +33581,ACT,7 +33596,RDA,7 +33632,ACT,7 +33647,RDA,7 +33683,ACT,7 +33698,RDA,7 +33734,REF,0 +33838,ACT,1 +33853,RDA,1 +33854,ACT,7 +33869,RDA,7 +33905,ACT,7 +33920,RDA,7 +33956,ACT,7 +33971,RDA,7 +33972,ACT,1 +33987,RDA,1 +34023,ACT,1 +34038,RDA,1 +34074,ACT,1 +34089,RDA,1 +34125,ACT,1 +34140,RDA,1 +34141,ACT,2 +34156,RDA,2 +34176,ACT,1 +34191,RDA,1 +34227,ACT,1 +34242,RDA,1 +34243,ACT,7 +34258,RDA,7 +34294,ACT,7 +34309,RDA,7 +34345,ACT,7 +34360,RDA,7 +34361,ACT,1 +34376,RDA,1 +34377,ACT,3 +34392,RDA,3 +34428,ACT,3 +34443,RDA,3 +34479,ACT,3 +34494,RDA,3 +34530,ACT,3 +34545,RDA,3 +34581,ACT,3 +34596,RDA,3 +34632,ACT,3 +34647,RDA,3 +34683,ACT,3 +34698,RDA,3 +34734,ACT,3 +34749,RDA,3 +34750,ACT,1 +34765,RDA,1 +34801,ACT,1 +34816,RDA,1 +34817,ACT,7 +34832,RDA,7 +34868,ACT,7 +34883,RDA,7 +34919,ACT,7 +34934,RDA,7 +34935,ACT,3 +34950,RDA,3 +34986,ACT,3 +35001,RDA,3 +35037,ACT,3 +35052,RDA,3 +35053,ACT,0 +35068,RDA,0 +35569,ACT,5 +35584,RDA,5 +35717,ACT,0 +35732,RDA,0 +36169,ACT,5 +36184,RDA,5 +36752,ACT,0 +36767,RDA,0 +36803,REF,0 +36907,ACT,0 +36922,RDA,0 +37118,ACT,5 +37133,RDA,5 +37530,ACT,5 +37545,RDA,5 +37809,ACT,0 +37824,RDA,0 +38259,ACT,5 +38274,RDA,5 +38783,ACT,0 +38798,RDA,0 +38878,ACT,0 +38893,RDA,0 +39418,ACT,5 +39433,RDA,5 +39536,ACT,0 +39551,RDA,0 +39784,ACT,5 +39799,RDA,5 +39920,REF,0 +40178,ACT,5 +40193,RDA,5 +40707,ACT,0 +40722,RDA,0 +40879,ACT,0 +40894,RDA,0 +41283,ACT,5 +41298,RDA,5 +41830,ACT,0 +41845,RDA,0 +41975,ACT,0 +41990,RDA,0 +42522,ACT,5 +42537,RDA,5 +43040,REF,0 +43161,ACT,0 +43176,RDA,0 +43243,ACT,0 +43258,RDA,0 +43491,ACT,5 +43506,RDA,5 +43946,ACT,5 +43961,RDA,5 +44494,ACT,0 +44509,RDA,0 +44639,ACT,0 +44654,RDA,0 +44765,ACT,5 +44780,RDA,5 +45129,ACT,0 +45144,RDA,0 +45169,ACT,2 +45184,RDA,2 +45220,ACT,2 +45235,RDA,2 +45525,ACT,2 +45540,RDA,2 +45605,ACT,0 +45620,RDA,0 +45818,ACT,0 +45833,RDA,0 +45904,ACT,5 +45919,RDA,5 +46160,REF,0 +46264,ACT,0 +46279,RDA,0 +46754,ACT,2 +46769,RDA,2 +47117,ACT,0 +47132,RDA,0 +47455,ACT,3 +47470,RDA,3 +47580,ACT,0 +47595,RDA,0 +47713,ACT,5 +47728,RDA,5 +48576,ACT,0 +48591,RDA,0 +49233,ACT,0 +49248,RDA,0 +49284,REF,0 +49388,ACT,0 +49403,RDA,0 +49808,ACT,5 +49823,RDA,5 +49980,ACT,0 +49995,RDA,0 +50375,ACT,5 +50390,RDA,5 +50651,ACT,0 +50666,RDA,0 +51055,ACT,5 +51070,RDA,5 +51645,ACT,0 +51660,RDA,0 +51740,ACT,0 +51755,RDA,0 +52400,REF,0 +52516,ACT,5 +52531,RDA,5 +52608,ACT,0 +52623,RDA,0 +52856,ACT,5 +52871,RDA,5 +53338,ACT,5 +53353,RDA,5 +53610,ACT,0 +53625,RDA,0 +54049,ACT,5 +54064,RDA,5 +54272,ACT,0 +54287,RDA,0 +54754,ACT,5 +54769,RDA,5 +54929,ACT,0 +54944,RDA,0 +55478,ACT,5 +55493,RDA,5 +55529,REF,0 +55633,ACT,0 +55648,RDA,0 +56190,ACT,5 +56205,RDA,5 +56285,ACT,0 +56300,RDA,0 +56533,ACT,5 +56548,RDA,5 +56928,ACT,5 +56943,RDA,5 +56970,ACT,0 +56985,RDA,0 +57021,ACT,0 +57036,RDA,0 +57072,ACT,0 +57087,RDA,0 +57132,ACT,0 +57147,RDA,0 +57175,ACT,6 +57190,RDA,6 +57226,ACT,6 +57241,RDA,6 +57277,ACT,6 +57292,RDA,6 +57332,ACT,6 +57347,RDA,6 +57612,ACT,0 +57627,RDA,0 +57701,ACT,5 +57716,RDA,5 +57741,ACT,0 +57756,RDA,0 +57941,ACT,0 +57956,RDA,0 +58640,REF,0 +58759,ACT,0 +58774,RDA,0 +59018,ACT,0 +59033,RDA,0 +60192,ACT,5 +60207,RDA,5 +60341,ACT,5 +60356,RDA,5 +61366,ACT,0 +61381,RDA,0 +61760,REF,0 +61897,ACT,5 +61912,RDA,5 +62515,ACT,5 +62530,RDA,5 +63546,ACT,5 +63561,RDA,5 +63597,ACT,5 +63612,RDA,5 +63648,ACT,5 +63663,RDA,5 +63699,ACT,5 +63714,RDA,5 +63750,ACT,5 +63765,RDA,5 +63801,ACT,5 +63816,RDA,5 +63852,ACT,5 +63867,RDA,5 +63903,ACT,5 +63918,RDA,5 +63954,ACT,5 +63969,RDA,5 +63970,ACT,2 +63985,RDA,2 +64021,ACT,2 +64036,RDA,2 +64072,ACT,2 +64087,RDA,2 +64123,ACT,2 +64138,RDA,2 +64174,ACT,2 +64189,RDA,2 +64225,ACT,2 +64240,RDA,2 +64276,ACT,2 +64291,RDA,2 +64327,ACT,2 +64342,RDA,2 +64378,ACT,2 +64393,RDA,2 +64429,ACT,2 +64444,RDA,2 +64480,ACT,2 +64495,RDA,2 +64531,ACT,2 +64546,RDA,2 +64582,ACT,2 +64597,RDA,2 +64633,ACT,2 +64648,RDA,2 +64684,ACT,2 +64699,RDA,2 +64735,ACT,2 +64750,RDA,2 +64786,ACT,2 +64801,RDA,2 +64837,ACT,2 +64852,RDA,2 +64888,ACT,2 +64903,RDA,2 +64939,REF,0 +65043,ACT,2 +65058,RDA,2 +65059,ACT,5 +65074,RDA,5 +65094,ACT,2 +65109,RDA,2 +65110,ACT,4 +65125,RDA,4 +65145,ACT,2 +65160,RDA,2 +65196,ACT,2 +65211,RDA,2 +65247,ACT,2 +65262,RDA,2 +65298,ACT,2 +65313,RDA,2 +65314,ACT,5 +65329,RDA,5 +65330,ACT,0 +65345,RDA,0 +65381,ACT,0 +65396,RDA,0 +65432,ACT,0 +65447,RDA,0 +65483,ACT,0 +65498,RDA,0 +65534,ACT,0 +65549,RDA,0 +65585,ACT,0 +65600,RDA,0 +65636,ACT,0 +65651,RDA,0 +65687,ACT,0 +65702,RDA,0 +65703,ACT,1 +65718,RDA,1 +65754,ACT,1 +65769,RDA,1 +65805,ACT,1 +65820,RDA,1 +65856,ACT,1 +65871,RDA,1 +65907,ACT,1 +65922,RDA,1 +65958,ACT,1 +65973,RDA,1 +66009,ACT,1 +66024,RDA,1 +66060,ACT,1 +66075,RDA,1 +66111,ACT,1 +66126,RDA,1 +66162,ACT,1 +66177,RDA,1 +66213,ACT,1 +66228,RDA,1 +66264,ACT,1 +66279,RDA,1 +66315,ACT,1 +66330,RDA,1 +66366,ACT,1 +66381,RDA,1 +66382,ACT,2 +66397,RDA,2 +66417,ACT,1 +66432,RDA,1 +66468,ACT,1 +66483,RDA,1 +66519,ACT,1 +66534,RDA,1 +66570,ACT,1 +66585,RDA,1 +66621,ACT,1 +66636,RDA,1 +66672,ACT,1 +66687,RDA,1 +66723,ACT,1 +66738,RDA,1 +66774,ACT,1 +66789,RDA,1 +66825,ACT,1 +66840,RDA,1 +66876,ACT,1 +66891,RDA,1 +66927,ACT,1 +66942,RDA,1 +66978,ACT,1 +66993,RDA,1 +67029,ACT,1 +67044,RDA,1 +67080,ACT,1 +67095,RDA,1 +67131,ACT,1 +67146,RDA,1 +67182,ACT,1 +67197,RDA,1 +67233,ACT,1 +67248,RDA,1 +67284,ACT,1 +67299,RDA,1 +67335,ACT,1 +67350,RDA,1 +67386,ACT,1 +67401,RDA,1 +67437,ACT,1 +67452,RDA,1 +67488,ACT,1 +67503,RDA,1 +67539,ACT,1 +67554,RDA,1 +67590,ACT,1 +67605,RDA,1 +67641,ACT,1 +67656,RDA,1 +67657,ACT,0 +67672,RDA,0 +67708,ACT,0 +67723,RDA,0 +67724,ACT,1 +67739,RDA,1 +67759,ACT,0 +67774,RDA,0 +67810,ACT,0 +67825,RDA,0 +67861,ACT,0 +67876,RDA,0 +67877,ACT,1 +67892,RDA,1 +67928,ACT,1 +67943,RDA,1 +67979,ACT,1 +67994,RDA,1 +68030,ACT,1 +68045,RDA,1 +68081,REF,0 +68185,ACT,1 +68200,RDA,1 +68236,ACT,1 +68251,RDA,1 +68287,ACT,1 +68302,RDA,1 +68338,ACT,1 +68353,RDA,1 +68389,ACT,1 +68404,RDA,1 +68440,ACT,1 +68455,RDA,1 +68491,ACT,1 +68506,RDA,1 +68542,ACT,1 +68557,RDA,1 +68593,ACT,1 +68608,RDA,1 +68644,ACT,1 +68659,RDA,1 +68695,ACT,1 +68710,RDA,1 +68746,ACT,1 +68761,RDA,1 +68797,ACT,1 +68812,RDA,1 +68848,ACT,1 +68863,RDA,1 +68899,ACT,1 +68914,RDA,1 +68950,ACT,1 +68965,RDA,1 +68966,ACT,6 +68981,RDA,6 +69001,ACT,1 +69016,RDA,1 +69052,ACT,1 +69067,RDA,1 +69103,ACT,1 +69118,RDA,1 +69154,ACT,1 +69169,RDA,1 +69205,ACT,1 +69220,RDA,1 +69256,ACT,1 +69271,RDA,1 +69307,ACT,1 +69322,RDA,1 +69358,ACT,1 +69373,RDA,1 +69409,ACT,1 +69424,RDA,1 +69460,ACT,1 +69475,RDA,1 +69511,ACT,1 +69526,RDA,1 +69562,ACT,1 +69577,RDA,1 +69613,ACT,1 +69628,RDA,1 +69664,ACT,1 +69679,RDA,1 +69715,ACT,1 +69730,RDA,1 +69766,ACT,1 +69781,RDA,1 +69817,ACT,1 +69832,RDA,1 +69868,ACT,1 +69883,RDA,1 +69919,ACT,1 +69934,RDA,1 +69970,ACT,1 +69985,RDA,1 +70021,ACT,1 +70036,RDA,1 +70072,ACT,1 +70087,RDA,1 +70123,ACT,1 +70138,RDA,1 +70174,ACT,1 +70189,RDA,1 +70225,ACT,1 +70240,RDA,1 +70276,ACT,1 +70291,RDA,1 +70327,ACT,1 +70342,RDA,1 +70378,ACT,1 +70393,RDA,1 +70429,ACT,1 +70444,RDA,1 +70480,ACT,1 +70495,RDA,1 +70531,ACT,1 +70546,RDA,1 +70582,ACT,1 +70597,RDA,1 +70633,ACT,1 +70648,RDA,1 +70684,ACT,1 +70699,RDA,1 +70735,ACT,1 +70750,RDA,1 +70786,ACT,1 +70801,RDA,1 +70802,ACT,2 +70817,RDA,2 +70837,ACT,1 +70852,RDA,1 +70888,ACT,1 +70903,RDA,1 +70939,ACT,1 +70954,RDA,1 +70955,ACT,2 +70970,RDA,2 +70990,ACT,1 +71005,RDA,1 +71006,ACT,0 +71021,RDA,0 +71022,ACT,5 +71037,RDA,5 +71073,ACT,5 +71088,RDA,5 +71089,ACT,0 +71104,RDA,0 +71140,ACT,0 +71155,RDA,0 +71191,REF,0 +71295,ACT,4 +71310,RDA,4 +71311,ACT,2 +71326,RDA,2 +71327,ACT,3 +71342,RDA,3 +71378,ACT,3 +71393,RDA,3 +71394,ACT,2 +71409,RDA,2 +71445,ACT,2 +71460,RDA,2 +71461,ACT,3 +71476,RDA,3 +71512,ACT,3 +71527,RDA,3 +71563,ACT,3 +71578,RDA,3 +71579,ACT,0 +71594,RDA,0 +71595,ACT,2 +71610,RDA,2 +71630,ACT,0 +71645,RDA,0 +71646,ACT,3 +71661,RDA,3 +71681,ACT,0 +71696,RDA,0 +71697,ACT,2 +71712,RDA,2 +71713,ACT,3 +71728,RDA,3 +71729,ACT,4 +71744,RDA,4 +71780,ACT,4 +71795,RDA,4 +71831,ACT,4 +71846,RDA,4 +71847,ACT,2 +71862,RDA,2 +71882,ACT,4 +71897,RDA,4 +71933,ACT,4 +71948,RDA,4 +71984,ACT,4 +71999,RDA,4 +72000,ACT,2 +72015,RDA,2 +72035,ACT,4 +72050,RDA,4 +72086,ACT,4 +72101,RDA,4 +72137,ACT,4 +72152,RDA,4 +72188,ACT,4 +72203,RDA,4 +72239,ACT,4 +72254,RDA,4 +72290,ACT,4 +72305,RDA,4 +72341,ACT,4 +72356,RDA,4 +72392,ACT,4 +72407,RDA,4 +72443,ACT,4 +72458,RDA,4 +72494,ACT,4 +72509,RDA,4 +72545,ACT,4 +72560,RDA,4 +72561,ACT,0 +72576,RDA,0 +72612,ACT,0 +72627,RDA,0 +72628,ACT,2 +72643,RDA,2 +72663,ACT,0 +72678,RDA,0 +72679,ACT,3 +72694,RDA,3 +72695,ACT,2 +72710,RDA,2 +72714,ACT,0 +72729,RDA,0 +72765,ACT,0 +72780,RDA,0 +72781,ACT,2 +72796,RDA,2 +72816,ACT,0 +72831,RDA,0 +72867,ACT,0 +72882,RDA,0 +72929,ACT,0 +72944,RDA,0 +72980,ACT,0 +72995,RDA,0 +73031,ACT,0 +73046,RDA,0 +73082,ACT,0 +73097,RDA,0 +73373,ACT,0 +73388,RDA,0 +74240,REF,0 +74554,ACT,2 +74569,RDA,2 +75740,ACT,2 +75755,RDA,2 +76929,ACT,2 +76944,RDA,2 +77360,REF,0 +78114,ACT,2 +78129,RDA,2 +78330,ACT,2 +78345,RDA,2 +78370,ACT,4 +78385,RDA,4 +78421,ACT,4 +78436,RDA,4 +78472,ACT,4 +78487,RDA,4 +79473,ACT,4 +79488,RDA,4 +80480,REF,0 +80737,ACT,2 +80752,RDA,2 +81256,ACT,2 +81271,RDA,2 +81296,ACT,3 +81311,RDA,3 +81347,ACT,3 +81362,RDA,3 +81365,ACT,0 +81380,RDA,0 +81398,ACT,3 +81413,RDA,3 +81449,ACT,3 +81464,RDA,3 +81500,ACT,3 +81515,RDA,3 +81558,ACT,3 +81573,RDA,3 +81654,ACT,2 +81669,RDA,2 +81750,ACT,2 +81765,RDA,2 +81846,ACT,2 +81861,RDA,2 +81942,ACT,2 +81957,RDA,2 +82038,ACT,2 +82053,RDA,2 +82134,ACT,2 +82149,RDA,2 +82230,ACT,2 +82245,RDA,2 +82348,ACT,2 +82363,RDA,2 +82444,ACT,2 +82459,RDA,2 +82540,ACT,2 +82555,RDA,2 +82636,ACT,2 +82651,RDA,2 +82732,ACT,2 +82747,RDA,2 +82828,ACT,2 +82843,RDA,2 +82924,ACT,2 +82939,RDA,2 +83020,ACT,2 +83035,RDA,2 +83116,ACT,2 +83131,RDA,2 +83212,ACT,2 +83227,RDA,2 +83308,ACT,2 +83323,RDA,2 +83404,ACT,2 +83419,RDA,2 +83500,ACT,2 +83515,RDA,2 +83596,ACT,2 +83611,RDA,2 +83647,REF,0 +83751,ACT,2 +83766,RDA,2 +83802,ACT,2 +83817,RDA,2 +83899,ACT,2 +83914,RDA,2 +83995,ACT,2 +84010,RDA,2 +84091,ACT,2 +84106,RDA,2 +84187,ACT,2 +84202,RDA,2 +84283,ACT,2 +84298,RDA,2 +84379,ACT,2 +84394,RDA,2 +84475,ACT,2 +84490,RDA,2 +84571,ACT,2 +84586,RDA,2 +84631,ACT,2 +84646,RDA,2 +84675,ACT,0 +84690,RDA,0 +84726,ACT,0 +84741,RDA,0 +84777,ACT,0 +84792,RDA,0 +84828,ACT,0 +84843,RDA,0 +84879,ACT,0 +84894,RDA,0 +84930,ACT,0 +84945,RDA,0 +85009,ACT,0 +85024,RDA,0 +85294,ACT,3 +85309,RDA,3 +85338,ACT,5 +85353,RDA,5 +85389,ACT,5 +85404,RDA,5 +85440,ACT,5 +85455,RDA,5 +85456,ACT,0 +85471,RDA,0 +85507,ACT,0 +85522,RDA,0 +85558,ACT,0 +85573,RDA,0 +85574,ACT,5 +85589,RDA,5 +85726,ACT,0 +85741,RDA,0 +85918,ACT,5 +85933,RDA,5 +86110,ACT,5 +86125,RDA,5 +86302,ACT,5 +86317,RDA,5 +86494,ACT,5 +86509,RDA,5 +86688,ACT,5 +86703,RDA,5 +86739,REF,0 +86905,ACT,5 +86920,RDA,5 +87113,ACT,5 +87128,RDA,5 +87321,ACT,5 +87336,RDA,5 +87534,ACT,5 +87549,RDA,5 +87799,ACT,5 +87814,RDA,5 +88055,ACT,5 +88070,RDA,5 +88311,ACT,5 +88326,RDA,5 +88567,ACT,5 +88582,RDA,5 +88823,ACT,5 +88838,RDA,5 +89090,ACT,5 +89105,RDA,5 +89211,ACT,0 +89226,RDA,0 +89326,ACT,0 +89341,RDA,0 +89437,ACT,0 +89452,RDA,0 +89551,ACT,0 +89566,RDA,0 +89602,ACT,0 +89617,RDA,0 +89662,ACT,3 +89677,RDA,3 +89779,ACT,0 +89794,RDA,0 +89830,ACT,0 +89845,RDA,0 +89881,REF,0 +89985,ACT,3 +90000,RDA,3 +90001,ACT,0 +90016,RDA,0 +91067,ACT,0 +91082,RDA,0 +91211,ACT,0 +91226,RDA,0 +91340,ACT,0 +91355,RDA,0 +91391,ACT,0 +91406,RDA,0 +91687,ACT,0 +91702,RDA,0 +91862,ACT,5 +91877,RDA,5 +91898,ACT,0 +91913,RDA,0 +91967,ACT,0 +91982,RDA,0 +92010,ACT,1 +92025,RDA,1 +92052,ACT,4 +92067,RDA,4 +92103,ACT,4 +92118,RDA,4 +92141,ACT,0 +92156,RDA,0 +92192,ACT,0 +92207,RDA,0 +92243,ACT,0 +92258,RDA,0 +92294,ACT,0 +92309,RDA,0 +92310,ACT,4 +92325,RDA,4 +92361,ACT,4 +92376,RDA,4 +92412,ACT,4 +92427,RDA,4 +92463,ACT,4 +92478,RDA,4 +92514,ACT,4 +92529,RDA,4 +92565,ACT,4 +92580,RDA,4 +92616,ACT,4 +92631,RDA,4 +92632,ACT,2 +92647,RDA,2 +92667,ACT,4 +92682,RDA,4 +92718,ACT,4 +92733,RDA,4 +92769,ACT,4 +92784,RDA,4 +92820,ACT,4 +92835,RDA,4 +92841,ACT,0 +92856,RDA,0 +92892,ACT,0 +92907,RDA,0 +92943,ACT,0 +92958,RDA,0 +92994,REF,0 +93098,ACT,0 +93113,RDA,0 +93149,ACT,0 +93164,RDA,0 +93200,ACT,0 +93215,RDA,0 +93216,ACT,6 +93231,RDA,6 +93232,ACT,3 +93247,RDA,3 +93267,ACT,6 +93282,RDA,6 +93318,ACT,6 +93333,RDA,6 +93369,ACT,6 +93384,RDA,6 +93420,ACT,6 +93435,RDA,6 +93471,ACT,6 +93486,RDA,6 +93487,ACT,7 +93502,RDA,7 +93538,ACT,7 +93553,RDA,7 +93554,ACT,3 +93569,RDA,3 +93589,ACT,7 +93604,RDA,7 +93640,ACT,7 +93655,RDA,7 +93695,ACT,3 +93710,RDA,3 +93728,ACT,7 +93743,RDA,7 +93779,ACT,7 +93794,RDA,7 +93830,ACT,7 +93845,RDA,7 +93881,ACT,7 +93896,RDA,7 +93932,ACT,7 +93947,RDA,7 +93983,ACT,7 +93998,RDA,7 +93999,ACT,6 +94014,RDA,6 +94050,ACT,6 +94065,RDA,6 +94101,ACT,6 +94116,RDA,6 +94152,ACT,6 +94167,RDA,6 +94203,ACT,6 +94218,RDA,6 +94254,ACT,6 +94269,RDA,6 +94305,ACT,6 +94320,RDA,6 +94356,ACT,6 +94371,RDA,6 +94407,ACT,6 +94422,RDA,6 +94458,ACT,6 +94473,RDA,6 +94509,ACT,6 +94524,RDA,6 +94560,ACT,6 +94575,RDA,6 +94576,ACT,7 +94591,RDA,7 +94627,ACT,7 +94642,RDA,7 +94643,ACT,0 +94658,RDA,0 +94659,ACT,1 +94674,RDA,1 +94694,ACT,0 +94709,RDA,0 +94745,ACT,0 +94760,RDA,0 +94847,ACT,0 +94862,RDA,0 +94960,ACT,0 +94975,RDA,0 +95011,ACT,0 +95026,RDA,0 +95062,ACT,0 +95077,RDA,0 +95078,ACT,7 +95093,RDA,7 +95129,ACT,7 +95144,RDA,7 +95180,ACT,7 +95195,RDA,7 +95231,ACT,7 +95246,RDA,7 +95282,ACT,7 +95297,RDA,7 +95333,ACT,7 +95348,RDA,7 +95384,ACT,7 +95399,RDA,7 +95435,ACT,7 +95450,RDA,7 +95557,ACT,7 +95572,RDA,7 +95608,ACT,7 +95623,RDA,7 +95659,ACT,7 +95674,RDA,7 +95710,ACT,7 +95725,RDA,7 +95761,ACT,7 +95776,RDA,7 +95812,ACT,7 +95827,RDA,7 +95863,ACT,7 +95878,RDA,7 +95914,ACT,7 +95929,RDA,7 +95965,ACT,7 +95980,RDA,7 +95981,ACT,2 +95996,RDA,2 +96032,ACT,2 +96047,RDA,2 +96083,ACT,2 +96098,RDA,2 +96134,REF,0 +96238,ACT,2 +96253,RDA,2 +96254,ACT,7 +96269,RDA,7 +96270,ACT,1 +96285,RDA,1 +96305,ACT,7 +96320,RDA,7 +96356,ACT,7 +96371,RDA,7 +96372,ACT,2 +96387,RDA,2 +96407,ACT,7 +96422,RDA,7 +96458,ACT,7 +96473,RDA,7 +96474,ACT,2 +96489,RDA,2 +96525,ACT,2 +96540,RDA,2 +96541,ACT,7 +96556,RDA,7 +96592,ACT,7 +96607,RDA,7 +96643,ACT,7 +96658,RDA,7 +96694,ACT,7 +96709,RDA,7 +96745,ACT,7 +96760,RDA,7 +96761,ACT,1 +96776,RDA,1 +96812,ACT,1 +96827,RDA,1 +96863,ACT,1 +96878,RDA,1 +96914,ACT,1 +96929,RDA,1 +96930,ACT,4 +96945,RDA,4 +97190,ACT,0 +97205,RDA,0 +97237,ACT,7 +97252,RDA,7 +97288,ACT,7 +97303,RDA,7 +97339,ACT,7 +97354,RDA,7 +97390,ACT,7 +97405,RDA,7 +97441,ACT,7 +97456,RDA,7 +97492,ACT,7 +97507,RDA,7 +97543,ACT,7 +97558,RDA,7 +97586,ACT,2 +97601,RDA,2 +97625,ACT,0 +97640,RDA,0 +97676,ACT,0 +97691,RDA,0 +97727,ACT,0 +97742,RDA,0 +97778,ACT,0 +97793,RDA,0 +97829,ACT,0 +97844,RDA,0 +97880,ACT,0 +97895,RDA,0 +97931,ACT,0 +97946,RDA,0 +97982,ACT,0 +97997,RDA,0 +98033,ACT,0 +98048,RDA,0 +98084,ACT,0 +98099,RDA,0 +98135,ACT,0 +98150,RDA,0 +98186,ACT,0 +98201,RDA,0 +98237,ACT,0 +98252,RDA,0 +98288,ACT,0 +98303,RDA,0 +98339,ACT,0 +98354,RDA,0 +98390,ACT,0 +98405,RDA,0 +98441,ACT,0 +98456,RDA,0 +98492,ACT,0 +98507,RDA,0 +98543,ACT,0 +98558,RDA,0 +98594,ACT,0 +98609,RDA,0 +98645,ACT,0 +98660,RDA,0 +98696,ACT,0 +98711,RDA,0 +98747,ACT,0 +98762,RDA,0 +98798,ACT,0 +98813,RDA,0 +98849,ACT,0 +98864,RDA,0 +98900,ACT,0 +98915,RDA,0 +98951,ACT,0 +98966,RDA,0 +99002,ACT,0 +99017,RDA,0 +99018,ACT,1 +99033,RDA,1 +99069,ACT,1 +99084,RDA,1 +99120,ACT,1 +99135,RDA,1 +99171,ACT,1 +99186,RDA,1 +99222,ACT,1 +99237,RDA,1 +99273,REF,0 +99377,ACT,1 +99392,RDA,1 +99428,ACT,1 +99443,RDA,1 +99479,ACT,1 +99494,RDA,1 +99530,ACT,1 +99545,RDA,1 +99581,ACT,1 +99596,RDA,1 +99632,ACT,1 +99647,RDA,1 +99683,ACT,1 +99698,RDA,1 +99734,ACT,1 +99749,RDA,1 +99785,ACT,1 +99800,RDA,1 +99836,ACT,1 +99851,RDA,1 +99852,ACT,0 +99867,RDA,0 +99887,ACT,1 +99902,RDA,1 +99938,ACT,1 +99953,RDA,1 +99989,ACT,1 +100004,RDA,1 +100040,ACT,1 +100055,RDA,1 +100091,ACT,1 +100106,RDA,1 +100142,ACT,1 +100157,RDA,1 +100193,ACT,1 +100208,RDA,1 +100244,ACT,1 +100259,RDA,1 +100295,ACT,1 +100310,RDA,1 +100346,ACT,1 +100361,RDA,1 +100397,ACT,1 +100412,RDA,1 +100413,ACT,2 +100428,RDA,2 +100563,ACT,0 +100578,RDA,0 +100614,ACT,0 +100629,RDA,0 +100665,ACT,0 +100680,RDA,0 +100716,ACT,0 +100731,RDA,0 +100732,ACT,1 +100747,RDA,1 +100783,ACT,1 +100798,RDA,1 +100834,ACT,1 +100849,RDA,1 +100885,ACT,1 +100900,RDA,1 +100936,ACT,1 +100951,RDA,1 +100987,ACT,1 +101002,RDA,1 +101038,ACT,1 +101053,RDA,1 +101089,ACT,1 +101104,RDA,1 +101140,ACT,1 +101155,RDA,1 +101191,ACT,1 +101206,RDA,1 +101242,ACT,1 +101257,RDA,1 +101293,ACT,1 +101308,RDA,1 +101344,ACT,1 +101359,RDA,1 +101395,ACT,1 +101410,RDA,1 +101446,ACT,1 +101461,RDA,1 +101462,ACT,0 +101477,RDA,0 +101513,ACT,0 +101528,RDA,0 +102320,REF,0 +104066,ACT,0 +104081,RDA,0 +104256,ACT,4 +104271,RDA,4 +104568,ACT,0 +104583,RDA,0 +104621,ACT,7 +104636,RDA,7 +105440,REF,0 +105896,ACT,2 +105911,RDA,2 +106141,ACT,4 +106156,RDA,4 +106512,ACT,0 +106527,RDA,0 +108560,REF,0 +110279,ACT,2 +110294,RDA,2 +110579,ACT,0 +110594,RDA,0 +110717,ACT,2 +110732,RDA,2 +110756,ACT,0 +110771,RDA,0 +110807,ACT,0 +110822,RDA,0 +110876,ACT,0 +110891,RDA,0 +110908,ACT,1 +110923,RDA,1 +110959,ACT,1 +110974,RDA,1 +111010,ACT,1 +111025,RDA,1 +111061,ACT,1 +111076,RDA,1 +111112,ACT,1 +111127,RDA,1 +111163,ACT,1 +111178,RDA,1 +111214,ACT,1 +111229,RDA,1 +111265,ACT,1 +111280,RDA,1 +111281,ACT,4 +111296,RDA,4 +111332,ACT,4 +111347,RDA,4 +111383,ACT,4 +111398,RDA,4 +111434,ACT,4 +111449,RDA,4 +111450,ACT,3 +111465,RDA,3 +111501,ACT,3 +111516,RDA,3 +111517,ACT,4 +111532,RDA,4 +111533,ACT,1 +111548,RDA,1 +111568,ACT,4 +111583,RDA,4 +111584,ACT,3 +111599,RDA,3 +111619,ACT,4 +111634,RDA,4 +111670,ACT,4 +111685,RDA,4 +111721,REF,0 +111825,ACT,4 +111840,RDA,4 +111876,ACT,4 +111891,RDA,4 +111927,ACT,4 +111942,RDA,4 +111943,ACT,3 +111958,RDA,3 +111959,ACT,0 +111974,RDA,0 +112010,ACT,0 +112025,RDA,0 +112026,ACT,3 +112041,RDA,3 +112077,ACT,3 +112092,RDA,3 +112093,ACT,0 +112108,RDA,0 +112128,ACT,3 +112143,RDA,3 +112144,ACT,0 +112159,RDA,0 +112160,ACT,4 +112175,RDA,4 +112211,ACT,4 +112226,RDA,4 +112262,ACT,4 +112277,RDA,4 +112313,ACT,4 +112328,RDA,4 +112329,ACT,5 +112344,RDA,5 +112380,ACT,5 +112395,RDA,5 +112431,ACT,5 +112446,RDA,5 +112482,ACT,5 +112497,RDA,5 +112498,ACT,3 +112513,RDA,3 +112533,ACT,5 +112548,RDA,5 +112549,ACT,3 +112564,RDA,3 +112584,ACT,5 +112599,RDA,5 +112635,ACT,5 +112650,RDA,5 +112686,ACT,5 +112701,RDA,5 +112702,ACT,3 +112717,RDA,3 +112753,ACT,3 +112768,RDA,3 +112769,ACT,5 +112784,RDA,5 +112804,ACT,3 +112819,RDA,3 +112820,ACT,5 +112835,RDA,5 +112836,ACT,0 +112851,RDA,0 +112887,ACT,0 +112902,RDA,0 +112938,ACT,0 +112953,RDA,0 +112989,ACT,0 +113004,RDA,0 +113005,ACT,5 +113020,RDA,5 +113040,ACT,0 +113055,RDA,0 +113091,ACT,0 +113106,RDA,0 +113142,ACT,0 +113157,RDA,0 +113193,ACT,0 +113208,RDA,0 +113209,ACT,1 +113224,RDA,1 +113244,ACT,0 +113259,RDA,0 +113295,ACT,0 +113310,RDA,0 +113346,ACT,0 +113361,RDA,0 +113397,ACT,0 +113412,RDA,0 +113448,ACT,0 +113463,RDA,0 +113499,ACT,0 +113514,RDA,0 +113550,ACT,0 +113565,RDA,0 +113601,ACT,0 +113616,RDA,0 +113652,ACT,0 +113667,RDA,0 +113703,ACT,0 +113718,RDA,0 +113754,ACT,0 +113769,RDA,0 +113770,ACT,3 +113785,RDA,3 +113805,ACT,0 +113820,RDA,0 +113856,ACT,0 +113871,RDA,0 +113907,ACT,0 +113922,RDA,0 +113958,ACT,0 +113973,RDA,0 +114009,ACT,0 +114024,RDA,0 +114060,ACT,0 +114075,RDA,0 +114076,ACT,5 +114091,RDA,5 +114127,ACT,5 +114142,RDA,5 +114178,ACT,5 +114193,RDA,5 +114229,ACT,5 +114244,RDA,5 +114280,ACT,5 +114295,RDA,5 +114331,ACT,5 +114346,RDA,5 +114382,ACT,5 +114397,RDA,5 +114433,ACT,5 +114448,RDA,5 +114484,ACT,5 +114499,RDA,5 +114500,ACT,0 +114515,RDA,0 +114551,ACT,0 +114566,RDA,0 +114602,ACT,0 +114617,RDA,0 +114618,ACT,3 +114633,RDA,3 +114634,ACT,5 +114649,RDA,5 +114685,ACT,5 +114700,RDA,5 +114701,ACT,0 +114716,RDA,0 +114752,ACT,0 +114767,RDA,0 +114803,ACT,0 +114818,RDA,0 +114854,REF,0 +114958,ACT,0 +114973,RDA,0 +114974,ACT,5 +114989,RDA,5 +115025,ACT,5 +115040,RDA,5 +115076,ACT,5 +115091,RDA,5 +115127,ACT,5 +115142,RDA,5 +115178,ACT,5 +115193,RDA,5 +115229,ACT,5 +115244,RDA,5 +115280,ACT,5 +115295,RDA,5 +115331,ACT,5 +115346,RDA,5 +115382,ACT,5 +115397,RDA,5 +115398,ACT,3 +115413,RDA,3 +115433,ACT,5 +115448,RDA,5 +115484,ACT,5 +115499,RDA,5 +115535,ACT,5 +115550,RDA,5 +115551,ACT,0 +115566,RDA,0 +115586,ACT,5 +115601,RDA,5 +115637,ACT,5 +115652,RDA,5 +115688,ACT,5 +115703,RDA,5 +115739,ACT,5 +115754,RDA,5 +115790,ACT,5 +115805,RDA,5 +115841,ACT,5 +115856,RDA,5 +115892,ACT,5 +115907,RDA,5 +115943,ACT,5 +115958,RDA,5 +115994,ACT,5 +116009,RDA,5 +116045,ACT,5 +116060,RDA,5 +116096,ACT,5 +116111,RDA,5 +116147,ACT,5 +116162,RDA,5 +116198,ACT,5 +116213,RDA,5 +116249,ACT,5 +116264,RDA,5 +116300,ACT,5 +116315,RDA,5 +116351,ACT,5 +116366,RDA,5 +116402,ACT,5 +116417,RDA,5 +116453,ACT,5 +116468,RDA,5 +116504,ACT,5 +116519,RDA,5 +116555,ACT,5 +116570,RDA,5 +116606,ACT,5 +116621,RDA,5 +116622,ACT,3 +116637,RDA,3 +116657,ACT,5 +116672,RDA,5 +116708,ACT,5 +116723,RDA,5 +116759,ACT,5 +116774,RDA,5 +116810,ACT,5 +116825,RDA,5 +116861,ACT,5 +116876,RDA,5 +116877,ACT,1 +116892,RDA,1 +116912,ACT,5 +116927,RDA,5 +116963,ACT,5 +116978,RDA,5 +117014,ACT,5 +117029,RDA,5 +117065,ACT,5 +117080,RDA,5 +117081,ACT,0 +117096,RDA,0 +117132,ACT,0 +117147,RDA,0 +117148,ACT,3 +117163,RDA,3 +117183,ACT,0 +117198,RDA,0 +117234,ACT,0 +117249,RDA,0 +117250,ACT,4 +117265,WRA,4 +117285,ACT,0 +117300,RDA,0 +117336,ACT,0 +117351,RDA,0 +117387,ACT,0 +117402,RDA,0 +117438,ACT,0 +117453,RDA,0 +117489,ACT,0 +117504,RDA,0 +117540,ACT,0 +117555,RDA,0 +117591,ACT,0 +117606,RDA,0 +117642,ACT,0 +117657,RDA,0 +117693,ACT,0 +117708,RDA,0 +117744,ACT,0 +117759,RDA,0 +117795,ACT,0 +117810,RDA,0 +117846,ACT,0 +117861,RDA,0 +117897,ACT,0 +117912,RDA,0 +117948,ACT,0 +117963,RDA,0 +117999,REF,0 +118103,ACT,0 +118118,RDA,0 +118154,ACT,0 +118169,RDA,0 +118205,ACT,0 +118220,RDA,0 +118256,ACT,0 +118271,RDA,0 +118272,ACT,5 +118287,RDA,5 +118288,ACT,1 +118303,RDA,1 +118339,ACT,1 +118354,RDA,1 +118390,ACT,1 +118405,RDA,1 +118406,ACT,5 +118421,RDA,5 +118457,ACT,5 +118472,RDA,5 +118508,ACT,5 +118523,RDA,5 +118559,ACT,5 +118574,RDA,5 +118610,ACT,5 +118625,RDA,5 +118661,ACT,5 +118676,RDA,5 +118712,ACT,5 +118727,RDA,5 +118763,ACT,5 +118778,RDA,5 +118814,ACT,5 +118829,RDA,5 +118865,ACT,5 +118880,RDA,5 +118916,ACT,5 +118931,RDA,5 +118967,ACT,5 +118982,RDA,5 +119018,ACT,5 +119033,RDA,5 +119069,ACT,5 +119084,RDA,5 +119085,ACT,1 +119100,RDA,1 +119136,ACT,1 +119151,RDA,1 +119152,ACT,5 +119167,RDA,5 +119203,ACT,5 +119218,RDA,5 +119254,ACT,5 +119269,RDA,5 +119305,ACT,5 +119320,RDA,5 +119321,ACT,6 +119336,RDA,6 +119372,ACT,6 +119387,RDA,6 +119423,ACT,6 +119438,RDA,6 +119474,ACT,6 +119489,RDA,6 +119525,ACT,6 +119540,RDA,6 +119576,ACT,6 +119591,RDA,6 +119627,ACT,6 +119642,RDA,6 +119678,ACT,6 +119693,RDA,6 +119729,ACT,6 +119744,RDA,6 +119780,ACT,6 +119795,RDA,6 +119831,ACT,6 +119846,RDA,6 +119882,ACT,6 +119897,RDA,6 +119933,ACT,6 +119948,RDA,6 +119984,ACT,6 +119999,RDA,6 +120035,ACT,6 +120050,RDA,6 +120086,ACT,6 +120101,RDA,6 +120137,ACT,6 +120152,RDA,6 +120188,ACT,6 +120203,RDA,6 +120239,ACT,6 +120254,RDA,6 +120290,ACT,6 +120305,RDA,6 +120341,ACT,6 +120356,RDA,6 +120392,ACT,6 +120407,RDA,6 +120443,ACT,6 +120458,RDA,6 +120494,ACT,6 +120509,RDA,6 +120545,ACT,6 +120560,RDA,6 +120561,ACT,7 +120576,RDA,7 +120596,ACT,6 +120611,RDA,6 +120647,ACT,6 +120662,RDA,6 +120663,ACT,7 +120678,RDA,7 +120714,ACT,7 +120729,RDA,7 +120730,ACT,4 +120745,RDA,4 +120746,ACT,3 +120761,RDA,3 +120781,ACT,4 +120796,RDA,4 +120832,ACT,4 +120847,RDA,4 +120848,ACT,3 +120863,RDA,3 +120883,ACT,4 +120898,RDA,4 +120934,ACT,4 +120949,WRA,4 +120992,ACT,4 +121007,RDA,4 +121043,ACT,4 +121058,WRA,4 +121079,PREA,4 +121085,SREN,4 +122119,SREX,4 +122130,END,0 \ No newline at end of file diff --git a/test/data/REFB.commands.trace b/test/data/REFB.commands.trace new file mode 100644 index 00000000..4efc642c --- /dev/null +++ b/test/data/REFB.commands.trace @@ -0,0 +1,3050 @@ +35,ACT,0 +50,RDA,0 +51,ACT,4 +66,RDA,4 +86,ACT,0 +101,RDA,0 +102,ACT,2 +117,RDA,2 +119,ACT,5 +134,RDA,5 +135,REFB,0 +137,ACT,0 +152,RDA,0 +159,ACT,3 +174,RDA,3 +195,ACT,0 +210,RDA,0 +220,REFB,1 +232,ACT,4 +247,RDA,4 +248,ACT,3 +263,RDA,3 +283,ACT,4 +298,RDA,4 +334,ACT,4 +349,RDA,4 +385,ACT,4 +400,RDA,4 +420,REFB,2 +436,ACT,4 +451,RDA,4 +460,REFB,3 +487,ACT,4 +502,RDA,4 +538,ACT,4 +553,RDA,4 +589,ACT,4 +604,RDA,4 +640,ACT,4 +655,RDA,4 +691,ACT,4 +706,RDA,4 +742,ACT,4 +757,RDA,4 +793,ACT,4 +808,RDA,4 +809,ACT,0 +824,RDA,0 +825,ACT,2 +840,RDA,2 +860,ACT,0 +875,RDA,0 +911,ACT,0 +926,RDA,0 +927,ACT,1 +942,RDA,1 +978,ACT,1 +993,RDA,1 +1000,REFB,4 +1029,ACT,1 +1044,RDA,1 +1080,ACT,1 +1095,RDA,1 +1096,ACT,2 +1111,RDA,2 +1131,ACT,1 +1146,RDA,1 +1150,REFB,5 +1182,ACT,1 +1197,RDA,1 +1198,ACT,0 +1213,RDA,0 +1249,ACT,0 +1264,RDA,0 +1265,ACT,1 +1280,RDA,1 +1281,ACT,3 +1296,RDA,3 +1300,ACT,0 +1315,RDA,0 +1351,ACT,0 +1366,RDA,0 +1402,ACT,0 +1417,RDA,0 +1453,ACT,0 +1468,RDA,0 +1469,ACT,1 +1484,RDA,1 +1504,ACT,0 +1519,RDA,0 +1555,ACT,0 +1570,RDA,0 +1606,ACT,0 +1621,RDA,0 +1657,ACT,0 +1672,RDA,0 +1673,ACT,5 +1688,RDA,5 +1700,REFB,6 +1724,ACT,5 +1739,RDA,5 +1740,ACT,3 +1755,RDA,3 +1775,ACT,5 +1790,RDA,5 +1826,ACT,5 +1841,RDA,5 +1842,ACT,3 +1857,RDA,3 +1877,ACT,5 +1892,RDA,5 +1893,ACT,1 +1908,RDA,1 +1944,ACT,1 +1959,RDA,1 +1995,ACT,1 +2010,RDA,1 +2011,ACT,2 +2026,RDA,2 +2027,ACT,5 +2042,RDA,5 +2078,ACT,5 +2093,RDA,5 +2129,ACT,5 +2144,RDA,5 +2180,ACT,5 +2195,RDA,5 +2196,ACT,1 +2211,RDA,1 +2212,ACT,2 +2227,RDA,2 +2247,ACT,1 +2262,RDA,1 +2298,ACT,1 +2313,RDA,1 +2349,ACT,1 +2364,RDA,1 +2400,ACT,1 +2415,RDA,1 +2451,ACT,1 +2466,RDA,1 +2502,ACT,1 +2517,RDA,1 +2553,ACT,1 +2568,RDA,1 +2569,ACT,6 +2584,RDA,6 +2585,ACT,2 +2600,RDA,2 +2620,ACT,6 +2635,RDA,6 +2671,ACT,6 +2686,RDA,6 +2687,ACT,2 +2702,RDA,2 +2703,ACT,5 +2718,RDA,5 +2754,ACT,5 +2769,RDA,5 +2770,ACT,2 +2785,RDA,2 +2821,ACT,2 +2836,RDA,2 +2837,ACT,3 +2852,RDA,3 +2853,ACT,7 +2868,RDA,7 +2904,ACT,7 +2919,RDA,7 +2920,ACT,2 +2935,RDA,2 +2936,ACT,1 +2951,RDA,1 +2987,ACT,1 +3002,RDA,1 +3003,ACT,7 +3018,RDA,7 +3019,ACT,2 +3034,RDA,2 +3035,ACT,5 +3050,RDA,5 +3086,ACT,5 +3101,RDA,5 +3137,ACT,5 +3152,RDA,5 +3188,REF,0 +3292,ACT,1 +3307,RDA,1 +3343,ACT,1 +3358,RDA,1 +3359,ACT,3 +3374,RDA,3 +3394,ACT,1 +3409,RDA,1 +3410,ACT,3 +3425,RDA,3 +3461,ACT,3 +3476,RDA,3 +3512,ACT,3 +3527,RDA,3 +3563,ACT,3 +3578,RDA,3 +3614,ACT,3 +3629,RDA,3 +3665,ACT,3 +3680,RDA,3 +3716,ACT,3 +3731,RDA,3 +3767,ACT,3 +3782,RDA,3 +3818,ACT,3 +3833,RDA,3 +3869,ACT,3 +3884,RDA,3 +3920,ACT,3 +3935,RDA,3 +3971,ACT,3 +3986,RDA,3 +4022,ACT,3 +4037,RDA,3 +4073,ACT,3 +4088,RDA,3 +4124,ACT,3 +4139,RDA,3 +4175,ACT,3 +4190,RDA,3 +4226,ACT,3 +4241,RDA,3 +4277,ACT,3 +4292,RDA,3 +4328,ACT,3 +4343,RDA,3 +4379,ACT,3 +4394,RDA,3 +4430,ACT,3 +4445,RDA,3 +4481,ACT,3 +4496,RDA,3 +4532,ACT,3 +4547,RDA,3 +4583,ACT,3 +4598,RDA,3 +4634,ACT,3 +4649,RDA,3 +4685,ACT,3 +4700,RDA,3 +4736,ACT,3 +4751,RDA,3 +4787,ACT,3 +4802,RDA,3 +4838,ACT,3 +4853,RDA,3 +4889,ACT,3 +4904,RDA,3 +4940,ACT,3 +4955,RDA,3 +4991,ACT,3 +5006,RDA,3 +5042,ACT,3 +5057,RDA,3 +5093,ACT,3 +5108,RDA,3 +5144,ACT,3 +5159,RDA,3 +5195,ACT,3 +5210,RDA,3 +5246,ACT,3 +5261,RDA,3 +5297,ACT,3 +5312,RDA,3 +5348,ACT,3 +5363,RDA,3 +5399,ACT,3 +5414,RDA,3 +5450,ACT,3 +5465,RDA,3 +5501,ACT,3 +5516,RDA,3 +5552,ACT,3 +5567,RDA,3 +5603,ACT,3 +5618,RDA,3 +5654,ACT,3 +5669,RDA,3 +5705,ACT,3 +5720,RDA,3 +5756,ACT,3 +5771,RDA,3 +5807,ACT,3 +5822,RDA,3 +5858,ACT,3 +5873,RDA,3 +5909,ACT,3 +5924,RDA,3 +5960,ACT,3 +5975,RDA,3 +6011,ACT,3 +6026,RDA,3 +6062,ACT,3 +6077,RDA,3 +6113,ACT,3 +6128,RDA,3 +6164,ACT,3 +6179,RDA,3 +6215,ACT,3 +6230,RDA,3 +6266,ACT,3 +6281,RDA,3 +6317,REF,0 +6421,ACT,3 +6436,RDA,3 +6472,ACT,3 +6487,RDA,3 +6523,ACT,3 +6538,RDA,3 +6574,ACT,3 +6589,RDA,3 +6625,ACT,3 +6640,RDA,3 +6676,ACT,3 +6691,RDA,3 +6692,ACT,4 +6707,RDA,4 +6743,ACT,4 +6758,RDA,4 +6794,ACT,4 +6809,RDA,4 +6845,ACT,4 +6860,RDA,4 +6896,ACT,4 +6911,RDA,4 +6947,ACT,4 +6962,RDA,4 +6998,ACT,4 +7013,RDA,4 +7049,ACT,4 +7064,RDA,4 +7100,ACT,4 +7115,RDA,4 +7151,ACT,4 +7166,RDA,4 +7202,ACT,4 +7217,RDA,4 +7253,ACT,4 +7268,RDA,4 +7304,ACT,4 +7319,RDA,4 +7355,ACT,4 +7370,RDA,4 +7406,ACT,4 +7421,RDA,4 +7457,ACT,4 +7472,RDA,4 +7508,ACT,4 +7523,RDA,4 +7559,ACT,4 +7574,RDA,4 +7610,ACT,4 +7625,RDA,4 +7661,ACT,4 +7676,RDA,4 +7712,ACT,4 +7727,RDA,4 +7763,ACT,4 +7778,RDA,4 +7814,ACT,4 +7829,RDA,4 +7865,ACT,4 +7880,RDA,4 +7916,ACT,4 +7931,RDA,4 +7967,ACT,4 +7982,RDA,4 +8018,ACT,4 +8033,RDA,4 +8069,ACT,4 +8084,RDA,4 +8120,ACT,4 +8135,RDA,4 +8171,ACT,4 +8186,RDA,4 +8222,ACT,4 +8237,RDA,4 +8273,ACT,4 +8288,RDA,4 +8324,ACT,4 +8339,RDA,4 +8375,ACT,4 +8390,RDA,4 +8426,ACT,4 +8441,RDA,4 +8477,ACT,4 +8492,RDA,4 +8528,ACT,4 +8543,RDA,4 +8579,ACT,4 +8594,RDA,4 +8630,ACT,4 +8645,RDA,4 +8681,ACT,4 +8696,RDA,4 +8732,ACT,4 +8747,RDA,4 +8783,ACT,4 +8798,RDA,4 +8834,ACT,4 +8849,RDA,4 +8885,ACT,4 +8900,RDA,4 +8936,ACT,4 +8951,RDA,4 +8987,ACT,4 +9002,RDA,4 +9038,ACT,4 +9053,RDA,4 +9089,ACT,4 +9104,RDA,4 +9140,ACT,4 +9155,RDA,4 +9191,ACT,4 +9206,RDA,4 +9242,ACT,4 +9257,RDA,4 +9293,ACT,4 +9308,RDA,4 +9344,ACT,4 +9359,RDA,4 +9395,REF,0 +9499,ACT,4 +9514,RDA,4 +9550,ACT,4 +9565,RDA,4 +9601,ACT,4 +9616,RDA,4 +9652,ACT,4 +9667,RDA,4 +9703,ACT,4 +9718,RDA,4 +9754,ACT,4 +9769,RDA,4 +9805,ACT,4 +9820,RDA,4 +9856,ACT,4 +9871,RDA,4 +9907,ACT,4 +9922,RDA,4 +9958,ACT,4 +9973,RDA,4 +10009,ACT,4 +10024,RDA,4 +10060,ACT,4 +10075,RDA,4 +10111,ACT,4 +10126,RDA,4 +10162,ACT,4 +10177,RDA,4 +10213,ACT,4 +10228,RDA,4 +10264,ACT,4 +10279,RDA,4 +10315,ACT,4 +10330,RDA,4 +10366,ACT,4 +10381,RDA,4 +10417,ACT,4 +10432,RDA,4 +10468,ACT,4 +10483,RDA,4 +10519,ACT,4 +10534,RDA,4 +10570,ACT,4 +10585,RDA,4 +10621,ACT,4 +10636,RDA,4 +10672,ACT,4 +10687,RDA,4 +10723,ACT,4 +10738,RDA,4 +10774,ACT,4 +10789,RDA,4 +10825,ACT,4 +10840,RDA,4 +10876,ACT,4 +10891,RDA,4 +10927,ACT,4 +10942,RDA,4 +10978,ACT,4 +10993,RDA,4 +11029,ACT,4 +11044,RDA,4 +11080,ACT,4 +11095,RDA,4 +11131,ACT,4 +11146,RDA,4 +11182,ACT,4 +11197,RDA,4 +11233,ACT,4 +11248,RDA,4 +11284,ACT,4 +11299,RDA,4 +11335,ACT,4 +11350,RDA,4 +11386,ACT,4 +11401,RDA,4 +11437,ACT,4 +11452,RDA,4 +11488,ACT,4 +11503,RDA,4 +11539,ACT,4 +11554,RDA,4 +11590,ACT,4 +11605,RDA,4 +11641,ACT,4 +11656,RDA,4 +11692,ACT,4 +11707,RDA,4 +11743,ACT,4 +11758,RDA,4 +11794,ACT,4 +11809,RDA,4 +11845,ACT,4 +11860,RDA,4 +11896,ACT,4 +11911,RDA,4 +11947,ACT,4 +11962,RDA,4 +11998,ACT,4 +12013,RDA,4 +12049,ACT,4 +12064,RDA,4 +12100,ACT,4 +12115,RDA,4 +12151,ACT,4 +12166,RDA,4 +12202,ACT,4 +12217,RDA,4 +12253,ACT,4 +12268,RDA,4 +12304,ACT,4 +12319,RDA,4 +12355,ACT,4 +12370,RDA,4 +12406,ACT,4 +12421,RDA,4 +12457,ACT,4 +12472,RDA,4 +12508,ACT,4 +12523,RDA,4 +12559,REF,0 +12663,ACT,4 +12678,RDA,4 +12714,ACT,4 +12729,RDA,4 +12765,ACT,4 +12780,RDA,4 +12816,ACT,4 +12831,RDA,4 +12867,ACT,4 +12882,RDA,4 +12918,ACT,4 +12933,RDA,4 +12969,ACT,4 +12984,RDA,4 +13020,ACT,4 +13035,RDA,4 +13071,ACT,4 +13086,RDA,4 +13122,ACT,4 +13137,RDA,4 +13173,ACT,4 +13188,RDA,4 +13224,ACT,4 +13239,RDA,4 +13275,ACT,4 +13290,RDA,4 +13326,ACT,4 +13341,RDA,4 +13377,ACT,4 +13392,RDA,4 +13393,ACT,5 +13408,RDA,5 +13409,ACT,6 +13424,RDA,6 +13460,ACT,6 +13475,RDA,6 +13511,ACT,6 +13526,RDA,6 +13562,ACT,6 +13577,RDA,6 +13578,ACT,3 +13593,RDA,3 +13613,ACT,6 +13628,RDA,6 +13664,ACT,6 +13679,RDA,6 +13715,ACT,6 +13730,RDA,6 +13766,ACT,6 +13781,RDA,6 +13817,ACT,6 +13832,RDA,6 +13868,ACT,6 +13883,RDA,6 +13919,ACT,6 +13934,RDA,6 +13935,ACT,3 +13950,RDA,3 +13970,ACT,6 +13985,RDA,6 +14021,ACT,6 +14036,RDA,6 +14072,ACT,6 +14087,RDA,6 +14123,ACT,6 +14138,RDA,6 +14174,ACT,6 +14189,RDA,6 +14225,ACT,6 +14240,RDA,6 +14276,ACT,6 +14291,RDA,6 +14327,ACT,6 +14342,RDA,6 +14378,ACT,6 +14393,RDA,6 +14429,ACT,6 +14444,RDA,6 +14480,ACT,6 +14495,RDA,6 +14531,ACT,6 +14546,RDA,6 +14582,ACT,6 +14597,RDA,6 +14598,ACT,5 +14613,RDA,5 +14633,ACT,6 +14648,RDA,6 +14649,ACT,5 +14664,RDA,5 +14700,ACT,5 +14715,RDA,5 +14751,ACT,5 +14766,RDA,5 +14802,ACT,5 +14817,RDA,5 +14853,ACT,5 +14868,RDA,5 +14904,ACT,5 +14919,RDA,5 +14955,ACT,5 +14970,RDA,5 +15006,ACT,5 +15021,RDA,5 +15057,ACT,5 +15072,RDA,5 +15108,ACT,5 +15123,RDA,5 +15159,ACT,5 +15174,RDA,5 +15210,ACT,5 +15225,RDA,5 +15261,ACT,5 +15276,RDA,5 +15312,ACT,5 +15327,RDA,5 +15363,ACT,5 +15378,RDA,5 +15414,ACT,5 +15429,RDA,5 +15465,ACT,5 +15480,RDA,5 +15516,ACT,5 +15531,RDA,5 +15567,ACT,5 +15582,RDA,5 +15618,ACT,5 +15633,RDA,5 +15669,REF,0 +15773,ACT,5 +15788,RDA,5 +15824,ACT,5 +15839,RDA,5 +15875,ACT,5 +15890,RDA,5 +15926,ACT,5 +15941,RDA,5 +15977,ACT,5 +15992,RDA,5 +16028,ACT,5 +16043,RDA,5 +16079,ACT,5 +16094,RDA,5 +16130,ACT,5 +16145,RDA,5 +16181,ACT,5 +16196,RDA,5 +16232,ACT,5 +16247,RDA,5 +16248,ACT,6 +16263,RDA,6 +16299,ACT,6 +16314,RDA,6 +16350,ACT,6 +16365,RDA,6 +16366,ACT,5 +16381,RDA,5 +16382,ACT,7 +16397,RDA,7 +16433,ACT,7 +16448,RDA,7 +16449,ACT,5 +16464,RDA,5 +16484,ACT,7 +16499,RDA,7 +16500,ACT,1 +16515,RDA,1 +16516,ACT,5 +16531,RDA,5 +16532,ACT,2 +16547,RDA,2 +16583,ACT,2 +16598,RDA,2 +16634,ACT,2 +16649,RDA,2 +16685,ACT,2 +16700,RDA,2 +16701,ACT,7 +16716,RDA,7 +16752,ACT,7 +16767,RDA,7 +16768,ACT,2 +16783,RDA,2 +16784,ACT,5 +16799,RDA,5 +16835,ACT,5 +16850,RDA,5 +16851,ACT,0 +16866,RDA,0 +16902,ACT,0 +16917,RDA,0 +16918,ACT,7 +16933,RDA,7 +16969,ACT,7 +16984,RDA,7 +17020,ACT,7 +17035,RDA,7 +17071,ACT,7 +17086,RDA,7 +17122,ACT,7 +17137,RDA,7 +17173,ACT,7 +17188,RDA,7 +17224,ACT,7 +17239,RDA,7 +17275,ACT,7 +17290,RDA,7 +17326,ACT,7 +17341,RDA,7 +17377,ACT,7 +17392,RDA,7 +17428,ACT,7 +17443,RDA,7 +17479,ACT,7 +17494,RDA,7 +17530,ACT,7 +17545,RDA,7 +17581,ACT,7 +17596,RDA,7 +17632,ACT,7 +17647,RDA,7 +17648,ACT,0 +17663,RDA,0 +17683,ACT,7 +17698,RDA,7 +17699,ACT,2 +17714,RDA,2 +17750,ACT,2 +17765,RDA,2 +17801,ACT,2 +17816,RDA,2 +17817,ACT,7 +17832,RDA,7 +17852,ACT,2 +17867,RDA,2 +17903,ACT,2 +17918,RDA,2 +17954,ACT,2 +17969,RDA,2 +17970,ACT,7 +17985,RDA,7 +18021,ACT,7 +18036,RDA,7 +18072,ACT,7 +18087,RDA,7 +18123,ACT,7 +18138,RDA,7 +18174,ACT,7 +18189,RDA,7 +18225,ACT,7 +18240,RDA,7 +18276,ACT,7 +18291,RDA,7 +18327,ACT,7 +18342,RDA,7 +18378,ACT,7 +18393,RDA,7 +18429,ACT,7 +18444,RDA,7 +18480,ACT,7 +18495,RDA,7 +18496,ACT,6 +18511,RDA,6 +18547,ACT,6 +18562,RDA,6 +18598,ACT,6 +18613,RDA,6 +18649,ACT,6 +18664,RDA,6 +18700,ACT,6 +18715,RDA,6 +18751,ACT,6 +18766,RDA,6 +18802,REF,0 +18906,ACT,6 +18921,RDA,6 +18957,ACT,6 +18972,RDA,6 +19008,ACT,6 +19023,RDA,6 +19059,ACT,6 +19074,RDA,6 +19110,ACT,6 +19125,RDA,6 +19161,ACT,6 +19176,RDA,6 +19212,ACT,6 +19227,RDA,6 +19228,ACT,2 +19243,RDA,2 +19279,ACT,2 +19294,RDA,2 +19295,ACT,7 +19310,RDA,7 +19346,ACT,7 +19361,RDA,7 +19362,ACT,2 +19377,RDA,2 +19378,ACT,6 +19393,RDA,6 +19429,ACT,6 +19444,RDA,6 +19480,ACT,6 +19495,RDA,6 +19531,ACT,6 +19546,RDA,6 +19582,ACT,6 +19597,RDA,6 +19598,ACT,1 +19613,RDA,1 +19614,ACT,7 +19629,RDA,7 +19645,REFB,7 +19665,ACT,7 +19680,RDA,7 +19681,ACT,6 +19696,RDA,6 +19732,ACT,6 +19747,RDA,6 +19783,ACT,6 +19798,RDA,6 +19834,ACT,6 +19849,RDA,6 +19885,ACT,6 +19900,RDA,6 +19901,ACT,5 +19916,RDA,5 +19925,REFB,7 +19936,ACT,6 +19951,RDA,6 +19987,ACT,6 +20002,RDA,6 +20003,ACT,7 +20018,RDA,7 +20054,ACT,7 +20069,RDA,7 +20070,ACT,2 +20085,RDA,2 +20105,ACT,7 +20120,RDA,7 +20156,ACT,7 +20171,RDA,7 +20207,ACT,7 +20222,RDA,7 +20258,ACT,7 +20273,RDA,7 +20274,ACT,2 +20289,RDA,2 +20325,ACT,2 +20340,RDA,2 +20376,ACT,2 +20391,RDA,2 +20392,ACT,7 +20407,RDA,7 +20443,ACT,7 +20458,RDA,7 +20494,ACT,7 +20509,RDA,7 +20545,ACT,7 +20560,RDA,7 +20561,ACT,3 +20576,RDA,3 +20577,ACT,5 +20592,RDA,5 +20593,ACT,0 +20608,RDA,0 +20609,ACT,7 +20624,RDA,7 +20625,ACT,2 +20640,RDA,2 +20676,ACT,2 +20691,RDA,2 +20727,ACT,2 +20742,RDA,2 +20743,ACT,7 +20758,RDA,7 +20794,ACT,7 +20809,RDA,7 +20845,ACT,7 +20860,RDA,7 +20896,ACT,7 +20911,RDA,7 +20947,ACT,7 +20962,RDA,7 +20963,ACT,2 +20978,RDA,2 +21014,ACT,2 +21029,RDA,2 +21065,ACT,2 +21080,RDA,2 +21116,ACT,2 +21131,RDA,2 +21167,ACT,2 +21182,RDA,2 +21183,ACT,3 +21198,RDA,3 +21218,ACT,2 +21233,RDA,2 +21269,ACT,2 +21284,RDA,2 +21320,ACT,2 +21335,RDA,2 +21371,ACT,2 +21386,RDA,2 +21387,ACT,1 +21402,RDA,1 +21403,ACT,7 +21418,RDA,7 +21419,ACT,4 +21434,RDA,4 +21470,ACT,4 +21485,RDA,4 +21486,ACT,3 +21501,RDA,3 +21521,ACT,4 +21536,RDA,4 +21537,ACT,3 +21552,RDA,3 +21572,ACT,4 +21587,RDA,4 +21588,ACT,2 +21603,RDA,2 +21623,ACT,4 +21638,RDA,4 +21639,ACT,2 +21654,RDA,2 +21690,ACT,2 +21705,RDA,2 +21741,ACT,2 +21756,RDA,2 +21792,ACT,2 +21807,RDA,2 +21843,ACT,2 +21858,RDA,2 +21894,REF,0 +21998,ACT,2 +22013,RDA,2 +22049,ACT,2 +22064,RDA,2 +22100,ACT,2 +22115,RDA,2 +22151,ACT,2 +22166,RDA,2 +22167,ACT,3 +22182,RDA,3 +22183,ACT,1 +22198,RDA,1 +22202,ACT,2 +22217,RDA,2 +22253,ACT,2 +22268,RDA,2 +22304,ACT,2 +22319,RDA,2 +22355,ACT,2 +22370,RDA,2 +22406,ACT,2 +22421,RDA,2 +22457,ACT,2 +22472,RDA,2 +22508,ACT,2 +22523,RDA,2 +22559,ACT,2 +22574,RDA,2 +22610,ACT,2 +22625,RDA,2 +22626,ACT,1 +22641,RDA,1 +22661,ACT,2 +22676,RDA,2 +22677,ACT,0 +22692,RDA,0 +22693,ACT,3 +22708,RDA,3 +22744,ACT,3 +22759,RDA,3 +22795,ACT,3 +22810,RDA,3 +22846,ACT,3 +22861,RDA,3 +22897,ACT,3 +22912,RDA,3 +22948,ACT,3 +22963,RDA,3 +22999,ACT,3 +23014,RDA,3 +23015,ACT,2 +23030,RDA,2 +23050,ACT,3 +23065,RDA,3 +23101,ACT,3 +23116,RDA,3 +23152,ACT,3 +23167,RDA,3 +23203,ACT,3 +23218,RDA,3 +23254,ACT,3 +23269,RDA,3 +23270,ACT,7 +23285,RDA,7 +23321,ACT,7 +23336,RDA,7 +23372,ACT,7 +23387,RDA,7 +23423,ACT,7 +23438,RDA,7 +23474,ACT,7 +23489,RDA,7 +23490,ACT,0 +23505,RDA,0 +23541,ACT,0 +23556,RDA,0 +23592,ACT,0 +23607,RDA,0 +23608,ACT,3 +23623,RDA,3 +23659,ACT,3 +23674,RDA,3 +23710,ACT,3 +23725,RDA,3 +23726,ACT,5 +23741,RDA,5 +23742,ACT,0 +23757,RDA,0 +23758,ACT,2 +23773,RDA,2 +23777,ACT,5 +23792,RDA,5 +23793,ACT,0 +23808,RDA,0 +23809,ACT,2 +23824,RDA,2 +23844,ACT,0 +23859,RDA,0 +23860,ACT,5 +23875,RDA,5 +23876,ACT,2 +23891,RDA,2 +23895,ACT,0 +23910,RDA,0 +23911,ACT,5 +23926,RDA,5 +23927,ACT,2 +23942,RDA,2 +23946,ACT,0 +23961,RDA,0 +23962,ACT,5 +23977,RDA,5 +23997,ACT,0 +24012,RDA,0 +24013,ACT,3 +24028,RDA,3 +24064,ACT,3 +24079,RDA,3 +24115,ACT,3 +24130,RDA,3 +24166,ACT,3 +24181,RDA,3 +24217,ACT,3 +24232,RDA,3 +24268,ACT,3 +24283,RDA,3 +24319,ACT,3 +24334,RDA,3 +24335,ACT,1 +24350,RDA,1 +24370,ACT,3 +24385,RDA,3 +24421,ACT,3 +24436,RDA,3 +24472,ACT,3 +24487,RDA,3 +24523,ACT,3 +24538,RDA,3 +24574,ACT,3 +24589,RDA,3 +24625,ACT,3 +24640,RDA,3 +24676,ACT,3 +24691,RDA,3 +24727,ACT,3 +24742,RDA,3 +24743,ACT,7 +24758,RDA,7 +24794,ACT,7 +24809,RDA,7 +24845,ACT,7 +24860,RDA,7 +24896,ACT,7 +24911,RDA,7 +24947,ACT,7 +24962,RDA,7 +24998,REF,0 +25102,ACT,7 +25117,RDA,7 +25153,ACT,7 +25168,RDA,7 +25204,ACT,7 +25219,RDA,7 +25255,ACT,7 +25270,RDA,7 +25306,ACT,7 +25321,RDA,7 +25357,ACT,7 +25372,RDA,7 +25408,ACT,7 +25423,RDA,7 +25459,ACT,7 +25474,RDA,7 +25510,ACT,7 +25525,RDA,7 +25561,ACT,7 +25576,RDA,7 +25577,ACT,3 +25592,RDA,3 +25628,ACT,3 +25643,RDA,3 +25679,ACT,3 +25694,RDA,3 +25730,ACT,3 +25745,RDA,3 +25781,ACT,3 +25796,RDA,3 +25832,ACT,3 +25847,RDA,3 +25883,ACT,3 +25898,RDA,3 +25934,ACT,3 +25949,RDA,3 +25985,ACT,3 +26000,RDA,3 +26001,ACT,2 +26016,RDA,2 +26017,ACT,0 +26032,RDA,0 +26036,ACT,3 +26051,RDA,3 +26087,ACT,3 +26102,RDA,3 +26103,ACT,2 +26118,RDA,2 +26119,ACT,0 +26134,RDA,0 +26135,ACT,5 +26150,RDA,5 +26170,ACT,0 +26185,RDA,0 +26186,ACT,5 +26201,RDA,5 +26221,ACT,0 +26236,RDA,0 +26272,ACT,0 +26287,RDA,0 +26288,ACT,1 +26303,RDA,1 +26304,ACT,2 +26319,RDA,2 +26355,ACT,2 +26370,RDA,2 +26406,ACT,2 +26421,RDA,2 +26422,ACT,0 +26437,RDA,0 +26473,ACT,0 +26488,RDA,0 +26489,ACT,5 +26504,RDA,5 +26505,ACT,2 +26520,RDA,2 +26524,ACT,0 +26539,RDA,0 +26575,ACT,0 +26590,RDA,0 +26591,ACT,5 +26606,RDA,5 +26607,ACT,2 +26622,RDA,2 +26626,ACT,0 +26641,RDA,0 +26642,ACT,5 +26657,RDA,5 +26677,ACT,0 +26692,RDA,0 +26728,ACT,0 +26743,RDA,0 +26744,ACT,5 +26759,RDA,5 +26779,ACT,0 +26794,RDA,0 +26795,ACT,5 +26810,RDA,5 +26846,ACT,5 +26861,RDA,5 +26862,ACT,0 +26877,RDA,0 +26878,ACT,2 +26893,RDA,2 +26913,ACT,0 +26928,RDA,0 +26929,ACT,2 +26944,RDA,2 +26945,ACT,3 +26960,RDA,3 +26996,ACT,3 +27011,RDA,3 +27047,ACT,3 +27062,RDA,3 +27098,ACT,3 +27113,RDA,3 +27149,ACT,3 +27164,RDA,3 +27200,ACT,3 +27215,RDA,3 +27251,ACT,3 +27266,RDA,3 +27302,ACT,3 +27317,RDA,3 +27353,ACT,3 +27368,RDA,3 +27404,ACT,3 +27419,RDA,3 +27455,ACT,3 +27470,RDA,3 +27471,ACT,7 +27486,RDA,7 +27522,ACT,7 +27537,RDA,7 +27573,ACT,7 +27588,RDA,7 +27589,ACT,3 +27604,RDA,3 +27624,ACT,7 +27639,RDA,7 +27675,ACT,7 +27690,RDA,7 +27726,ACT,7 +27741,RDA,7 +27777,ACT,7 +27792,RDA,7 +27828,ACT,7 +27843,RDA,7 +27879,ACT,7 +27894,RDA,7 +27930,ACT,7 +27945,RDA,7 +27981,ACT,7 +27996,RDA,7 +28032,ACT,7 +28047,RDA,7 +28083,ACT,7 +28098,RDA,7 +28134,REF,0 +28238,ACT,1 +28253,RDA,1 +28254,ACT,7 +28269,RDA,7 +28305,ACT,7 +28320,RDA,7 +28356,ACT,7 +28371,RDA,7 +28372,ACT,1 +28387,RDA,1 +28423,ACT,1 +28438,RDA,1 +28474,ACT,1 +28489,RDA,1 +28525,ACT,1 +28540,RDA,1 +28541,ACT,2 +28556,RDA,2 +28576,ACT,1 +28591,RDA,1 +28627,ACT,1 +28642,RDA,1 +28643,ACT,7 +28658,RDA,7 +28694,ACT,7 +28709,RDA,7 +28745,ACT,7 +28760,RDA,7 +28761,ACT,1 +28776,RDA,1 +28777,ACT,3 +28792,RDA,3 +28828,ACT,3 +28843,RDA,3 +28879,ACT,3 +28894,RDA,3 +28930,ACT,3 +28945,RDA,3 +28981,ACT,3 +28996,RDA,3 +29032,ACT,3 +29047,RDA,3 +29083,ACT,3 +29098,RDA,3 +29134,ACT,3 +29149,RDA,3 +29150,ACT,1 +29165,RDA,1 +29201,ACT,1 +29216,RDA,1 +29217,ACT,7 +29232,RDA,7 +29268,ACT,7 +29283,RDA,7 +29319,ACT,7 +29334,RDA,7 +29335,ACT,3 +29350,RDA,3 +29386,ACT,3 +29401,RDA,3 +29437,ACT,3 +29452,RDA,3 +29453,ACT,0 +29468,RDA,0 +29969,ACT,5 +29984,RDA,5 +30117,ACT,0 +30132,RDA,0 +30569,ACT,5 +30584,RDA,5 +31152,ACT,0 +31167,RDA,0 +31203,REF,0 +31307,ACT,0 +31322,RDA,0 +31518,ACT,5 +31533,RDA,5 +31930,ACT,5 +31945,RDA,5 +32209,ACT,0 +32224,RDA,0 +32659,ACT,5 +32674,RDA,5 +33183,ACT,0 +33198,RDA,0 +33278,ACT,0 +33293,RDA,0 +33818,ACT,5 +33833,RDA,5 +33936,ACT,0 +33951,RDA,0 +34184,ACT,5 +34199,RDA,5 +34320,REF,0 +34578,ACT,5 +34593,RDA,5 +35107,ACT,0 +35122,RDA,0 +35279,ACT,0 +35294,RDA,0 +35683,ACT,5 +35698,RDA,5 +36230,ACT,0 +36245,RDA,0 +36375,ACT,0 +36390,RDA,0 +36922,ACT,5 +36937,RDA,5 +37440,REF,0 +37561,ACT,0 +37576,RDA,0 +37643,ACT,0 +37658,RDA,0 +37891,ACT,5 +37906,RDA,5 +38346,ACT,5 +38361,RDA,5 +38894,ACT,0 +38909,RDA,0 +39039,ACT,0 +39054,RDA,0 +39165,ACT,5 +39180,RDA,5 +39529,ACT,0 +39544,RDA,0 +39569,ACT,2 +39584,RDA,2 +39620,ACT,2 +39635,RDA,2 +39925,ACT,2 +39940,RDA,2 +40005,ACT,0 +40020,RDA,0 +40218,ACT,0 +40233,RDA,0 +40304,ACT,5 +40319,RDA,5 +40560,REF,0 +40664,ACT,0 +40679,RDA,0 +41154,ACT,2 +41169,RDA,2 +41517,ACT,0 +41532,RDA,0 +41855,ACT,3 +41870,RDA,3 +41980,ACT,0 +41995,RDA,0 +42113,ACT,5 +42128,RDA,5 +42976,ACT,0 +42991,RDA,0 +43633,ACT,0 +43648,RDA,0 +43684,REF,0 +43788,ACT,0 +43803,RDA,0 +44208,ACT,5 +44223,RDA,5 +44380,ACT,0 +44395,RDA,0 +44775,ACT,5 +44790,RDA,5 +45051,ACT,0 +45066,RDA,0 +45455,ACT,5 +45470,RDA,5 +46045,ACT,0 +46060,RDA,0 +46140,ACT,0 +46155,RDA,0 +46800,REF,0 +46916,ACT,5 +46931,RDA,5 +47008,ACT,0 +47023,RDA,0 +47256,ACT,5 +47271,RDA,5 +47738,ACT,5 +47753,RDA,5 +48010,ACT,0 +48025,RDA,0 +48449,ACT,5 +48464,RDA,5 +48672,ACT,0 +48687,RDA,0 +49154,ACT,5 +49169,RDA,5 +49329,ACT,0 +49344,RDA,0 +49878,ACT,5 +49893,RDA,5 +49929,REF,0 +50033,ACT,0 +50048,RDA,0 +50590,ACT,5 +50605,RDA,5 +50685,ACT,0 +50700,RDA,0 +50933,ACT,5 +50948,RDA,5 +51328,ACT,5 +51343,RDA,5 +51370,ACT,0 +51385,RDA,0 +51421,ACT,0 +51436,RDA,0 +51472,ACT,0 +51487,RDA,0 +51532,ACT,0 +51547,RDA,0 +51575,ACT,6 +51590,RDA,6 +51626,ACT,6 +51641,RDA,6 +51677,ACT,6 +51692,RDA,6 +51732,ACT,6 +51747,RDA,6 +52012,ACT,0 +52027,RDA,0 +52101,ACT,5 +52116,RDA,5 +52141,ACT,0 +52156,RDA,0 +52341,ACT,0 +52356,RDA,0 +53040,REF,0 +53159,ACT,0 +53174,RDA,0 +53418,ACT,0 +53433,RDA,0 +54592,ACT,5 +54607,RDA,5 +54741,ACT,5 +54756,RDA,5 +55766,ACT,0 +55781,RDA,0 +56160,REF,0 +56297,ACT,5 +56312,RDA,5 +56915,ACT,5 +56930,RDA,5 +57946,ACT,5 +57961,RDA,5 +57997,ACT,5 +58012,RDA,5 +58048,ACT,5 +58063,RDA,5 +58099,ACT,5 +58114,RDA,5 +58150,ACT,5 +58165,RDA,5 +58201,ACT,5 +58216,RDA,5 +58252,ACT,5 +58267,RDA,5 +58303,ACT,5 +58318,RDA,5 +58354,ACT,5 +58369,RDA,5 +58370,ACT,2 +58385,RDA,2 +58421,ACT,2 +58436,RDA,2 +58472,ACT,2 +58487,RDA,2 +58523,ACT,2 +58538,RDA,2 +58574,ACT,2 +58589,RDA,2 +58625,ACT,2 +58640,RDA,2 +58676,ACT,2 +58691,RDA,2 +58727,ACT,2 +58742,RDA,2 +58778,ACT,2 +58793,RDA,2 +58829,ACT,2 +58844,RDA,2 +58880,ACT,2 +58895,RDA,2 +58931,ACT,2 +58946,RDA,2 +58982,ACT,2 +58997,RDA,2 +59033,ACT,2 +59048,RDA,2 +59084,ACT,2 +59099,RDA,2 +59135,ACT,2 +59150,RDA,2 +59186,ACT,2 +59201,RDA,2 +59237,ACT,2 +59252,RDA,2 +59288,ACT,2 +59303,RDA,2 +59339,REF,0 +59443,ACT,2 +59458,RDA,2 +59459,ACT,5 +59474,RDA,5 +59494,ACT,2 +59509,RDA,2 +59510,ACT,4 +59525,RDA,4 +59545,ACT,2 +59560,RDA,2 +59596,ACT,2 +59611,RDA,2 +59647,ACT,2 +59662,RDA,2 +59698,ACT,2 +59713,RDA,2 +59714,ACT,5 +59729,RDA,5 +59730,ACT,0 +59745,RDA,0 +59781,ACT,0 +59796,RDA,0 +59832,ACT,0 +59847,RDA,0 +59883,ACT,0 +59898,RDA,0 +59934,ACT,0 +59949,RDA,0 +59985,ACT,0 +60000,RDA,0 +60036,ACT,0 +60051,RDA,0 +60087,ACT,0 +60102,RDA,0 +60103,ACT,1 +60118,RDA,1 +60154,ACT,1 +60169,RDA,1 +60205,ACT,1 +60220,RDA,1 +60256,ACT,1 +60271,RDA,1 +60307,ACT,1 +60322,RDA,1 +60358,ACT,1 +60373,RDA,1 +60409,ACT,1 +60424,RDA,1 +60460,ACT,1 +60475,RDA,1 +60511,ACT,1 +60526,RDA,1 +60562,ACT,1 +60577,RDA,1 +60613,ACT,1 +60628,RDA,1 +60664,ACT,1 +60679,RDA,1 +60715,ACT,1 +60730,RDA,1 +60766,ACT,1 +60781,RDA,1 +60782,ACT,2 +60797,RDA,2 +60817,ACT,1 +60832,RDA,1 +60868,ACT,1 +60883,RDA,1 +60919,ACT,1 +60934,RDA,1 +60970,ACT,1 +60985,RDA,1 +61021,ACT,1 +61036,RDA,1 +61072,ACT,1 +61087,RDA,1 +61123,ACT,1 +61138,RDA,1 +61174,ACT,1 +61189,RDA,1 +61225,ACT,1 +61240,RDA,1 +61276,ACT,1 +61291,RDA,1 +61327,ACT,1 +61342,RDA,1 +61378,ACT,1 +61393,RDA,1 +61429,ACT,1 +61444,RDA,1 +61480,ACT,1 +61495,RDA,1 +61531,ACT,1 +61546,RDA,1 +61582,ACT,1 +61597,RDA,1 +61633,ACT,1 +61648,RDA,1 +61684,ACT,1 +61699,RDA,1 +61735,ACT,1 +61750,RDA,1 +61786,ACT,1 +61801,RDA,1 +61837,ACT,1 +61852,RDA,1 +61888,ACT,1 +61903,RDA,1 +61939,ACT,1 +61954,RDA,1 +61990,ACT,1 +62005,RDA,1 +62041,ACT,1 +62056,RDA,1 +62057,ACT,0 +62072,RDA,0 +62108,ACT,0 +62123,RDA,0 +62124,ACT,1 +62139,RDA,1 +62159,ACT,0 +62174,RDA,0 +62210,ACT,0 +62225,RDA,0 +62261,ACT,0 +62276,RDA,0 +62277,ACT,1 +62292,RDA,1 +62328,ACT,1 +62343,RDA,1 +62379,ACT,1 +62394,RDA,1 +62430,ACT,1 +62445,RDA,1 +62481,REF,0 +62585,ACT,1 +62600,RDA,1 +62636,ACT,1 +62651,RDA,1 +62687,ACT,1 +62702,RDA,1 +62738,ACT,1 +62753,RDA,1 +62789,ACT,1 +62804,RDA,1 +62840,ACT,1 +62855,RDA,1 +62891,ACT,1 +62906,RDA,1 +62942,ACT,1 +62957,RDA,1 +62993,ACT,1 +63008,RDA,1 +63044,ACT,1 +63059,RDA,1 +63095,ACT,1 +63110,RDA,1 +63146,ACT,1 +63161,RDA,1 +63197,ACT,1 +63212,RDA,1 +63248,ACT,1 +63263,RDA,1 +63299,ACT,1 +63314,RDA,1 +63350,ACT,1 +63365,RDA,1 +63366,ACT,6 +63381,RDA,6 +63401,ACT,1 +63416,RDA,1 +63452,ACT,1 +63467,RDA,1 +63503,ACT,1 +63518,RDA,1 +63554,ACT,1 +63569,RDA,1 +63605,ACT,1 +63620,RDA,1 +63656,ACT,1 +63671,RDA,1 +63707,ACT,1 +63722,RDA,1 +63758,ACT,1 +63773,RDA,1 +63809,ACT,1 +63824,RDA,1 +63860,ACT,1 +63875,RDA,1 +63911,ACT,1 +63926,RDA,1 +63962,ACT,1 +63977,RDA,1 +64013,ACT,1 +64028,RDA,1 +64064,ACT,1 +64079,RDA,1 +64115,ACT,1 +64130,RDA,1 +64166,ACT,1 +64181,RDA,1 +64217,ACT,1 +64232,RDA,1 +64268,ACT,1 +64283,RDA,1 +64319,ACT,1 +64334,RDA,1 +64370,ACT,1 +64385,RDA,1 +64421,ACT,1 +64436,RDA,1 +64472,ACT,1 +64487,RDA,1 +64523,ACT,1 +64538,RDA,1 +64574,ACT,1 +64589,RDA,1 +64625,ACT,1 +64640,RDA,1 +64676,ACT,1 +64691,RDA,1 +64727,ACT,1 +64742,RDA,1 +64778,ACT,1 +64793,RDA,1 +64829,ACT,1 +64844,RDA,1 +64880,ACT,1 +64895,RDA,1 +64931,ACT,1 +64946,RDA,1 +64982,ACT,1 +64997,RDA,1 +65033,ACT,1 +65048,RDA,1 +65084,ACT,1 +65099,RDA,1 +65135,ACT,1 +65150,RDA,1 +65186,ACT,1 +65201,RDA,1 +65202,ACT,2 +65217,RDA,2 +65237,ACT,1 +65252,RDA,1 +65288,ACT,1 +65303,RDA,1 +65339,ACT,1 +65354,RDA,1 +65355,ACT,2 +65370,RDA,2 +65390,ACT,1 +65405,RDA,1 +65406,ACT,0 +65421,RDA,0 +65422,ACT,5 +65437,RDA,5 +65473,ACT,5 +65488,RDA,5 +65489,ACT,0 +65504,RDA,0 +65540,ACT,0 +65555,RDA,0 +65591,REF,0 +65695,ACT,4 +65710,RDA,4 +65711,ACT,2 +65726,RDA,2 +65727,ACT,3 +65742,RDA,3 +65778,ACT,3 +65793,RDA,3 +65794,ACT,2 +65809,RDA,2 +65845,ACT,2 +65860,RDA,2 +65861,ACT,3 +65876,RDA,3 +65912,ACT,3 +65927,RDA,3 +65963,ACT,3 +65978,RDA,3 +65979,ACT,0 +65994,RDA,0 +65995,ACT,2 +66010,RDA,2 +66030,ACT,0 +66045,RDA,0 +66046,ACT,3 +66061,RDA,3 +66081,ACT,0 +66096,RDA,0 +66097,ACT,2 +66112,RDA,2 +66113,ACT,3 +66128,RDA,3 +66129,ACT,4 +66144,RDA,4 +66180,ACT,4 +66195,RDA,4 +66231,ACT,4 +66246,RDA,4 +66247,ACT,2 +66262,RDA,2 +66282,ACT,4 +66297,RDA,4 +66333,ACT,4 +66348,RDA,4 +66384,ACT,4 +66399,RDA,4 +66400,ACT,2 +66415,RDA,2 +66435,ACT,4 +66450,RDA,4 +66486,ACT,4 +66501,RDA,4 +66537,ACT,4 +66552,RDA,4 +66588,ACT,4 +66603,RDA,4 +66639,ACT,4 +66654,RDA,4 +66690,ACT,4 +66705,RDA,4 +66741,ACT,4 +66756,RDA,4 +66792,ACT,4 +66807,RDA,4 +66843,ACT,4 +66858,RDA,4 +66894,ACT,4 +66909,RDA,4 +66945,ACT,4 +66960,RDA,4 +66961,ACT,0 +66976,RDA,0 +67012,ACT,0 +67027,RDA,0 +67028,ACT,2 +67043,RDA,2 +67063,ACT,0 +67078,RDA,0 +67079,ACT,3 +67094,RDA,3 +67095,ACT,2 +67110,RDA,2 +67114,ACT,0 +67129,RDA,0 +67165,ACT,0 +67180,RDA,0 +67181,ACT,2 +67196,RDA,2 +67216,ACT,0 +67231,RDA,0 +67267,ACT,0 +67282,RDA,0 +67329,ACT,0 +67344,RDA,0 +67380,ACT,0 +67395,RDA,0 +67431,ACT,0 +67446,RDA,0 +67482,ACT,0 +67497,RDA,0 +67773,ACT,0 +67788,RDA,0 +68640,REF,0 +68954,ACT,2 +68969,RDA,2 +70140,ACT,2 +70155,RDA,2 +71329,ACT,2 +71344,RDA,2 +71760,REF,0 +72514,ACT,2 +72529,RDA,2 +72730,ACT,2 +72745,RDA,2 +72770,ACT,4 +72785,RDA,4 +72821,ACT,4 +72836,RDA,4 +72872,ACT,4 +72887,RDA,4 +73873,ACT,4 +73888,RDA,4 +74880,REF,0 +75137,ACT,2 +75152,RDA,2 +75656,ACT,2 +75671,RDA,2 +75696,ACT,3 +75711,RDA,3 +75747,ACT,3 +75762,RDA,3 +75765,ACT,0 +75780,RDA,0 +75798,ACT,3 +75813,RDA,3 +75849,ACT,3 +75864,RDA,3 +75900,ACT,3 +75915,RDA,3 +75958,ACT,3 +75973,RDA,3 +76054,ACT,2 +76069,RDA,2 +76150,ACT,2 +76165,RDA,2 +76246,ACT,2 +76261,RDA,2 +76342,ACT,2 +76357,RDA,2 +76438,ACT,2 +76453,RDA,2 +76534,ACT,2 +76549,RDA,2 +76630,ACT,2 +76645,RDA,2 +76748,ACT,2 +76763,RDA,2 +76844,ACT,2 +76859,RDA,2 +76940,ACT,2 +76955,RDA,2 +77036,ACT,2 +77051,RDA,2 +77132,ACT,2 +77147,RDA,2 +77228,ACT,2 +77243,RDA,2 +77324,ACT,2 +77339,RDA,2 +77420,ACT,2 +77435,RDA,2 +77516,ACT,2 +77531,RDA,2 +77612,ACT,2 +77627,RDA,2 +77708,ACT,2 +77723,RDA,2 +77804,ACT,2 +77819,RDA,2 +77900,ACT,2 +77915,RDA,2 +77996,ACT,2 +78011,RDA,2 +78047,REF,0 +78151,ACT,2 +78166,RDA,2 +78202,ACT,2 +78217,RDA,2 +78299,ACT,2 +78314,RDA,2 +78395,ACT,2 +78410,RDA,2 +78491,ACT,2 +78506,RDA,2 +78587,ACT,2 +78602,RDA,2 +78683,ACT,2 +78698,RDA,2 +78779,ACT,2 +78794,RDA,2 +78875,ACT,2 +78890,RDA,2 +78971,ACT,2 +78986,RDA,2 +79031,ACT,2 +79046,RDA,2 +79075,ACT,0 +79090,RDA,0 +79126,ACT,0 +79141,RDA,0 +79177,ACT,0 +79192,RDA,0 +79228,ACT,0 +79243,RDA,0 +79279,ACT,0 +79294,RDA,0 +79330,ACT,0 +79345,RDA,0 +79409,ACT,0 +79424,RDA,0 +79694,ACT,3 +79709,RDA,3 +79738,ACT,5 +79753,RDA,5 +79789,ACT,5 +79804,RDA,5 +79840,ACT,5 +79855,RDA,5 +79856,ACT,0 +79871,RDA,0 +79907,ACT,0 +79922,RDA,0 +79958,ACT,0 +79973,RDA,0 +79974,ACT,5 +79989,RDA,5 +80126,ACT,0 +80141,RDA,0 +80318,ACT,5 +80333,RDA,5 +80510,ACT,5 +80525,RDA,5 +80702,ACT,5 +80717,RDA,5 +80894,ACT,5 +80909,RDA,5 +81088,ACT,5 +81103,RDA,5 +81139,REF,0 +81305,ACT,5 +81320,RDA,5 +81513,ACT,5 +81528,RDA,5 +81721,ACT,5 +81736,RDA,5 +81934,ACT,5 +81949,RDA,5 +82199,ACT,5 +82214,RDA,5 +82455,ACT,5 +82470,RDA,5 +82711,ACT,5 +82726,RDA,5 +82967,ACT,5 +82982,RDA,5 +83223,ACT,5 +83238,RDA,5 +83490,ACT,5 +83505,RDA,5 +83611,ACT,0 +83626,RDA,0 +83726,ACT,0 +83741,RDA,0 +83837,ACT,0 +83852,RDA,0 +83951,ACT,0 +83966,RDA,0 +84002,ACT,0 +84017,RDA,0 +84062,ACT,3 +84077,RDA,3 +84179,ACT,0 +84194,RDA,0 +84230,ACT,0 +84245,RDA,0 +84281,REF,0 +84385,ACT,3 +84400,RDA,3 +84401,ACT,0 +84416,RDA,0 +85467,ACT,0 +85482,RDA,0 +85611,ACT,0 +85626,RDA,0 +85740,ACT,0 +85755,RDA,0 +85791,ACT,0 +85806,RDA,0 +86087,ACT,0 +86102,RDA,0 +86262,ACT,5 +86277,RDA,5 +86298,ACT,0 +86313,RDA,0 +86367,ACT,0 +86382,RDA,0 +86410,ACT,1 +86425,RDA,1 +86452,ACT,4 +86467,RDA,4 +86503,ACT,4 +86518,RDA,4 +86541,ACT,0 +86556,RDA,0 +86592,ACT,0 +86607,RDA,0 +86643,ACT,0 +86658,RDA,0 +86694,ACT,0 +86709,RDA,0 +86710,ACT,4 +86725,RDA,4 +86761,ACT,4 +86776,RDA,4 +86812,ACT,4 +86827,RDA,4 +86863,ACT,4 +86878,RDA,4 +86914,ACT,4 +86929,RDA,4 +86965,ACT,4 +86980,RDA,4 +87016,ACT,4 +87031,RDA,4 +87032,ACT,2 +87047,RDA,2 +87067,ACT,4 +87082,RDA,4 +87118,ACT,4 +87133,RDA,4 +87169,ACT,4 +87184,RDA,4 +87220,ACT,4 +87235,RDA,4 +87241,ACT,0 +87256,RDA,0 +87292,ACT,0 +87307,RDA,0 +87343,ACT,0 +87358,RDA,0 +87394,REF,0 +87498,ACT,0 +87513,RDA,0 +87549,ACT,0 +87564,RDA,0 +87600,ACT,0 +87615,RDA,0 +87616,ACT,6 +87631,RDA,6 +87632,ACT,3 +87647,RDA,3 +87667,ACT,6 +87682,RDA,6 +87718,ACT,6 +87733,RDA,6 +87769,ACT,6 +87784,RDA,6 +87820,ACT,6 +87835,RDA,6 +87871,ACT,6 +87886,RDA,6 +87887,ACT,7 +87902,RDA,7 +87938,ACT,7 +87953,RDA,7 +87954,ACT,3 +87969,RDA,3 +87989,ACT,7 +88004,RDA,7 +88040,ACT,7 +88055,RDA,7 +88095,ACT,3 +88110,RDA,3 +88128,ACT,7 +88143,RDA,7 +88179,ACT,7 +88194,RDA,7 +88230,ACT,7 +88245,RDA,7 +88281,ACT,7 +88296,RDA,7 +88332,ACT,7 +88347,RDA,7 +88383,ACT,7 +88398,RDA,7 +88399,ACT,6 +88414,RDA,6 +88450,ACT,6 +88465,RDA,6 +88501,ACT,6 +88516,RDA,6 +88552,ACT,6 +88567,RDA,6 +88603,ACT,6 +88618,RDA,6 +88654,ACT,6 +88669,RDA,6 +88705,ACT,6 +88720,RDA,6 +88756,ACT,6 +88771,RDA,6 +88807,ACT,6 +88822,RDA,6 +88858,ACT,6 +88873,RDA,6 +88909,ACT,6 +88924,RDA,6 +88960,ACT,6 +88975,RDA,6 +88976,ACT,7 +88991,RDA,7 +89027,ACT,7 +89042,RDA,7 +89043,ACT,0 +89058,RDA,0 +89059,ACT,1 +89074,RDA,1 +89094,ACT,0 +89109,RDA,0 +89145,ACT,0 +89160,RDA,0 +89247,ACT,0 +89262,RDA,0 +89360,ACT,0 +89375,RDA,0 +89411,ACT,0 +89426,RDA,0 +89462,ACT,0 +89477,RDA,0 +89478,ACT,7 +89493,RDA,7 +89529,ACT,7 +89544,RDA,7 +89580,ACT,7 +89595,RDA,7 +89631,ACT,7 +89646,RDA,7 +89682,ACT,7 +89697,RDA,7 +89733,ACT,7 +89748,RDA,7 +89784,ACT,7 +89799,RDA,7 +89835,ACT,7 +89850,RDA,7 +89957,ACT,7 +89972,RDA,7 +90008,ACT,7 +90023,RDA,7 +90059,ACT,7 +90074,RDA,7 +90110,ACT,7 +90125,RDA,7 +90161,ACT,7 +90176,RDA,7 +90212,ACT,7 +90227,RDA,7 +90263,ACT,7 +90278,RDA,7 +90314,ACT,7 +90329,RDA,7 +90365,ACT,7 +90380,RDA,7 +90381,ACT,2 +90396,RDA,2 +90432,ACT,2 +90447,RDA,2 +90483,ACT,2 +90498,RDA,2 +90534,REF,0 +90638,ACT,2 +90653,RDA,2 +90654,ACT,7 +90669,RDA,7 +90670,ACT,1 +90685,RDA,1 +90705,ACT,7 +90720,RDA,7 +90756,ACT,7 +90771,RDA,7 +90772,ACT,2 +90787,RDA,2 +90807,ACT,7 +90822,RDA,7 +90858,ACT,7 +90873,RDA,7 +90874,ACT,2 +90889,RDA,2 +90925,ACT,2 +90940,RDA,2 +90941,ACT,7 +90956,RDA,7 +90992,ACT,7 +91007,RDA,7 +91043,ACT,7 +91058,RDA,7 +91094,ACT,7 +91109,RDA,7 +91145,ACT,7 +91160,RDA,7 +91161,ACT,1 +91176,RDA,1 +91212,ACT,1 +91227,RDA,1 +91263,ACT,1 +91278,RDA,1 +91314,ACT,1 +91329,RDA,1 +91330,ACT,4 +91345,RDA,4 +91590,ACT,0 +91605,RDA,0 +91637,ACT,7 +91652,RDA,7 +91688,ACT,7 +91703,RDA,7 +91739,ACT,7 +91754,RDA,7 +91790,ACT,7 +91805,RDA,7 +91841,ACT,7 +91856,RDA,7 +91892,ACT,7 +91907,RDA,7 +91943,ACT,7 +91958,RDA,7 +91986,ACT,2 +92001,RDA,2 +92025,ACT,0 +92040,RDA,0 +92076,ACT,0 +92091,RDA,0 +92127,ACT,0 +92142,RDA,0 +92178,ACT,0 +92193,RDA,0 +92229,ACT,0 +92244,RDA,0 +92280,ACT,0 +92295,RDA,0 +92331,ACT,0 +92346,RDA,0 +92382,ACT,0 +92397,RDA,0 +92433,ACT,0 +92448,RDA,0 +92484,ACT,0 +92499,RDA,0 +92535,ACT,0 +92550,RDA,0 +92586,ACT,0 +92601,RDA,0 +92637,ACT,0 +92652,RDA,0 +92688,ACT,0 +92703,RDA,0 +92739,ACT,0 +92754,RDA,0 +92790,ACT,0 +92805,RDA,0 +92841,ACT,0 +92856,RDA,0 +92892,ACT,0 +92907,RDA,0 +92943,ACT,0 +92958,RDA,0 +92994,ACT,0 +93009,RDA,0 +93045,ACT,0 +93060,RDA,0 +93096,ACT,0 +93111,RDA,0 +93147,ACT,0 +93162,RDA,0 +93198,ACT,0 +93213,RDA,0 +93249,ACT,0 +93264,RDA,0 +93300,ACT,0 +93315,RDA,0 +93351,ACT,0 +93366,RDA,0 +93402,ACT,0 +93417,RDA,0 +93418,ACT,1 +93433,RDA,1 +93469,ACT,1 +93484,RDA,1 +93520,ACT,1 +93535,RDA,1 +93571,ACT,1 +93586,RDA,1 +93622,ACT,1 +93637,RDA,1 +93673,REF,0 +93777,ACT,1 +93792,RDA,1 +93828,ACT,1 +93843,RDA,1 +93879,ACT,1 +93894,RDA,1 +93930,ACT,1 +93945,RDA,1 +93981,ACT,1 +93996,RDA,1 +94032,ACT,1 +94047,RDA,1 +94083,ACT,1 +94098,RDA,1 +94134,ACT,1 +94149,RDA,1 +94185,ACT,1 +94200,RDA,1 +94236,ACT,1 +94251,RDA,1 +94252,ACT,0 +94267,RDA,0 +94287,ACT,1 +94302,RDA,1 +94338,ACT,1 +94353,RDA,1 +94389,ACT,1 +94404,RDA,1 +94440,ACT,1 +94455,RDA,1 +94491,ACT,1 +94506,RDA,1 +94542,ACT,1 +94557,RDA,1 +94593,ACT,1 +94608,RDA,1 +94644,ACT,1 +94659,RDA,1 +94695,ACT,1 +94710,RDA,1 +94746,ACT,1 +94761,RDA,1 +94797,ACT,1 +94812,RDA,1 +94813,ACT,2 +94828,RDA,2 +94963,ACT,0 +94978,RDA,0 +95014,ACT,0 +95029,RDA,0 +95065,ACT,0 +95080,RDA,0 +95116,ACT,0 +95131,RDA,0 +95132,ACT,1 +95147,RDA,1 +95183,ACT,1 +95198,RDA,1 +95234,ACT,1 +95249,RDA,1 +95285,ACT,1 +95300,RDA,1 +95336,ACT,1 +95351,RDA,1 +95387,ACT,1 +95402,RDA,1 +95438,ACT,1 +95453,RDA,1 +95489,ACT,1 +95504,RDA,1 +95540,ACT,1 +95555,RDA,1 +95591,ACT,1 +95606,RDA,1 +95642,ACT,1 +95657,RDA,1 +95693,ACT,1 +95708,RDA,1 +95744,ACT,1 +95759,RDA,1 +95795,ACT,1 +95810,RDA,1 +95846,ACT,1 +95861,RDA,1 +95862,ACT,0 +95877,RDA,0 +95913,ACT,0 +95928,RDA,0 +96720,REF,0 +98466,ACT,0 +98481,RDA,0 +98656,ACT,4 +98671,RDA,4 +98968,ACT,0 +98983,RDA,0 +99021,ACT,7 +99036,RDA,7 +99840,REF,0 +100296,ACT,2 +100311,RDA,2 +100541,ACT,4 +100556,RDA,4 +100912,ACT,0 +100927,RDA,0 +102960,REF,0 +104679,ACT,2 +104694,RDA,2 +104979,ACT,0 +104994,RDA,0 +105117,ACT,2 +105132,RDA,2 +105156,ACT,0 +105171,RDA,0 +105207,ACT,0 +105222,RDA,0 +105276,ACT,0 +105291,RDA,0 +105308,ACT,1 +105323,RDA,1 +105359,ACT,1 +105374,RDA,1 +105410,ACT,1 +105425,RDA,1 +105461,ACT,1 +105476,RDA,1 +105512,ACT,1 +105527,RDA,1 +105563,ACT,1 +105578,RDA,1 +105614,ACT,1 +105629,RDA,1 +105665,ACT,1 +105680,RDA,1 +105681,ACT,4 +105696,RDA,4 +105732,ACT,4 +105747,RDA,4 +105783,ACT,4 +105798,RDA,4 +105834,ACT,4 +105849,RDA,4 +105850,ACT,3 +105865,RDA,3 +105901,ACT,3 +105916,RDA,3 +105917,ACT,4 +105932,RDA,4 +105933,ACT,1 +105948,RDA,1 +105968,ACT,4 +105983,RDA,4 +105984,ACT,3 +105999,RDA,3 +106019,ACT,4 +106034,RDA,4 +106070,ACT,4 +106085,RDA,4 +106121,REF,0 +106225,ACT,4 +106240,RDA,4 +106276,ACT,4 +106291,RDA,4 +106327,ACT,4 +106342,RDA,4 +106343,ACT,3 +106358,RDA,3 +106359,ACT,0 +106374,RDA,0 +106410,ACT,0 +106425,RDA,0 +106426,ACT,3 +106441,RDA,3 +106477,ACT,3 +106492,RDA,3 +106493,ACT,0 +106508,RDA,0 +106528,ACT,3 +106543,RDA,3 +106544,ACT,0 +106559,RDA,0 +106560,ACT,4 +106575,RDA,4 +106611,ACT,4 +106626,RDA,4 +106662,ACT,4 +106677,RDA,4 +106713,ACT,4 +106728,RDA,4 +106729,ACT,5 +106744,RDA,5 +106780,ACT,5 +106795,RDA,5 +106831,ACT,5 +106846,RDA,5 +106882,ACT,5 +106897,RDA,5 +106898,ACT,3 +106913,RDA,3 +106933,ACT,5 +106948,RDA,5 +106949,ACT,3 +106964,RDA,3 +106984,ACT,5 +106999,RDA,5 +107035,ACT,5 +107050,RDA,5 +107086,ACT,5 +107101,RDA,5 +107102,ACT,3 +107117,RDA,3 +107153,ACT,3 +107168,RDA,3 +107169,ACT,5 +107184,RDA,5 +107204,ACT,3 +107219,RDA,3 +107220,ACT,5 +107235,RDA,5 +107236,ACT,0 +107251,RDA,0 +107287,ACT,0 +107302,RDA,0 +107338,ACT,0 +107353,RDA,0 +107389,ACT,0 +107404,RDA,0 +107405,ACT,5 +107420,RDA,5 +107440,ACT,0 +107455,RDA,0 +107491,ACT,0 +107506,RDA,0 +107542,ACT,0 +107557,RDA,0 +107593,ACT,0 +107608,RDA,0 +107609,ACT,1 +107624,RDA,1 +107644,ACT,0 +107659,RDA,0 +107695,ACT,0 +107710,RDA,0 +107746,ACT,0 +107761,RDA,0 +107797,ACT,0 +107812,RDA,0 +107848,ACT,0 +107863,RDA,0 +107899,ACT,0 +107914,RDA,0 +107950,ACT,0 +107965,RDA,0 +108001,ACT,0 +108016,RDA,0 +108052,ACT,0 +108067,RDA,0 +108103,ACT,0 +108118,RDA,0 +108154,ACT,0 +108169,RDA,0 +108170,ACT,3 +108185,RDA,3 +108205,ACT,0 +108220,RDA,0 +108256,ACT,0 +108271,RDA,0 +108307,ACT,0 +108322,RDA,0 +108358,ACT,0 +108373,RDA,0 +108409,ACT,0 +108424,RDA,0 +108460,ACT,0 +108475,RDA,0 +108476,ACT,5 +108491,RDA,5 +108527,ACT,5 +108542,RDA,5 +108578,ACT,5 +108593,RDA,5 +108629,ACT,5 +108644,RDA,5 +108680,ACT,5 +108695,RDA,5 +108731,ACT,5 +108746,RDA,5 +108782,ACT,5 +108797,RDA,5 +108833,ACT,5 +108848,RDA,5 +108884,ACT,5 +108899,RDA,5 +108900,ACT,0 +108915,RDA,0 +108951,ACT,0 +108966,RDA,0 +109002,ACT,0 +109017,RDA,0 +109018,ACT,3 +109033,RDA,3 +109034,ACT,5 +109049,RDA,5 +109085,ACT,5 +109100,RDA,5 +109101,ACT,0 +109116,RDA,0 +109152,ACT,0 +109167,RDA,0 +109203,ACT,0 +109218,RDA,0 +109254,REF,0 +109358,ACT,0 +109373,RDA,0 +109374,ACT,5 +109389,RDA,5 +109425,ACT,5 +109440,RDA,5 +109476,ACT,5 +109491,RDA,5 +109527,ACT,5 +109542,RDA,5 +109578,ACT,5 +109593,RDA,5 +109629,ACT,5 +109644,RDA,5 +109680,ACT,5 +109695,RDA,5 +109731,ACT,5 +109746,RDA,5 +109782,ACT,5 +109797,RDA,5 +109798,ACT,3 +109813,RDA,3 +109833,ACT,5 +109848,RDA,5 +109884,ACT,5 +109899,RDA,5 +109935,ACT,5 +109950,RDA,5 +109951,ACT,0 +109966,RDA,0 +109986,ACT,5 +110001,RDA,5 +110037,ACT,5 +110052,RDA,5 +110088,ACT,5 +110103,RDA,5 +110139,ACT,5 +110154,RDA,5 +110190,ACT,5 +110205,RDA,5 +110241,ACT,5 +110256,RDA,5 +110292,ACT,5 +110307,RDA,5 +110343,ACT,5 +110358,RDA,5 +110394,ACT,5 +110409,RDA,5 +110445,ACT,5 +110460,RDA,5 +110496,ACT,5 +110511,RDA,5 +110547,ACT,5 +110562,RDA,5 +110598,ACT,5 +110613,RDA,5 +110649,ACT,5 +110664,RDA,5 +110700,ACT,5 +110715,RDA,5 +110751,ACT,5 +110766,RDA,5 +110802,ACT,5 +110817,RDA,5 +110853,ACT,5 +110868,RDA,5 +110904,ACT,5 +110919,RDA,5 +110955,ACT,5 +110970,RDA,5 +111006,ACT,5 +111021,RDA,5 +111022,ACT,3 +111037,RDA,3 +111057,ACT,5 +111072,RDA,5 +111108,ACT,5 +111123,RDA,5 +111159,ACT,5 +111174,RDA,5 +111210,ACT,5 +111225,RDA,5 +111261,ACT,5 +111276,RDA,5 +111277,ACT,1 +111292,RDA,1 +111312,ACT,5 +111327,RDA,5 +111363,ACT,5 +111378,RDA,5 +111414,ACT,5 +111429,RDA,5 +111465,ACT,5 +111480,RDA,5 +111481,ACT,0 +111496,RDA,0 +111532,ACT,0 +111547,RDA,0 +111548,ACT,3 +111563,RDA,3 +111583,ACT,0 +111598,RDA,0 +111634,ACT,0 +111649,RDA,0 +111650,ACT,4 +111665,WRA,4 +111685,ACT,0 +111700,RDA,0 +111736,ACT,0 +111751,RDA,0 +111787,ACT,0 +111802,RDA,0 +111838,ACT,0 +111853,RDA,0 +111889,ACT,0 +111904,RDA,0 +111940,ACT,0 +111955,RDA,0 +111991,ACT,0 +112006,RDA,0 +112042,ACT,0 +112057,RDA,0 +112093,ACT,0 +112108,RDA,0 +112144,ACT,0 +112159,RDA,0 +112195,ACT,0 +112210,RDA,0 +112246,ACT,0 +112261,RDA,0 +112297,ACT,0 +112312,RDA,0 +112348,ACT,0 +112363,RDA,0 +112399,REF,0 +112503,ACT,0 +112518,RDA,0 +112554,ACT,0 +112569,RDA,0 +112605,ACT,0 +112620,RDA,0 +112656,ACT,0 +112671,RDA,0 +112672,ACT,5 +112687,RDA,5 +112688,ACT,1 +112703,RDA,1 +112739,ACT,1 +112754,RDA,1 +112790,ACT,1 +112805,RDA,1 +112806,ACT,5 +112821,RDA,5 +112857,ACT,5 +112872,RDA,5 +112908,ACT,5 +112923,RDA,5 +112959,ACT,5 +112974,RDA,5 +113010,ACT,5 +113025,RDA,5 +113061,ACT,5 +113076,RDA,5 +113112,ACT,5 +113127,RDA,5 +113163,ACT,5 +113178,RDA,5 +113214,ACT,5 +113229,RDA,5 +113265,ACT,5 +113280,RDA,5 +113316,ACT,5 +113331,RDA,5 +113367,ACT,5 +113382,RDA,5 +113418,ACT,5 +113433,RDA,5 +113469,ACT,5 +113484,RDA,5 +113485,ACT,1 +113500,RDA,1 +113536,ACT,1 +113551,RDA,1 +113552,ACT,5 +113567,RDA,5 +113603,ACT,5 +113618,RDA,5 +113654,ACT,5 +113669,RDA,5 +113705,ACT,5 +113720,RDA,5 +113721,ACT,6 +113736,RDA,6 +113772,ACT,6 +113787,RDA,6 +113823,ACT,6 +113838,RDA,6 +113874,ACT,6 +113889,RDA,6 +113925,ACT,6 +113940,RDA,6 +113976,ACT,6 +113991,RDA,6 +114027,ACT,6 +114042,RDA,6 +114078,ACT,6 +114093,RDA,6 +114129,ACT,6 +114144,RDA,6 +114180,ACT,6 +114195,RDA,6 +114231,ACT,6 +114246,RDA,6 +114282,ACT,6 +114297,RDA,6 +114333,ACT,6 +114348,RDA,6 +114384,ACT,6 +114399,RDA,6 +114435,ACT,6 +114450,RDA,6 +114486,ACT,6 +114501,RDA,6 +114537,ACT,6 +114552,RDA,6 +114588,ACT,6 +114603,RDA,6 +114639,ACT,6 +114654,RDA,6 +114690,ACT,6 +114705,RDA,6 +114741,ACT,6 +114756,RDA,6 +114792,ACT,6 +114807,RDA,6 +114843,ACT,6 +114858,RDA,6 +114894,ACT,6 +114909,RDA,6 +114945,ACT,6 +114960,RDA,6 +114961,ACT,7 +114976,RDA,7 +114996,ACT,6 +115011,RDA,6 +115047,ACT,6 +115062,RDA,6 +115063,ACT,7 +115078,RDA,7 +115114,ACT,7 +115129,RDA,7 +115130,ACT,4 +115145,RDA,4 +115146,ACT,3 +115161,RDA,3 +115181,ACT,4 +115196,RDA,4 +115232,ACT,4 +115247,RDA,4 +115248,ACT,3 +115263,RDA,3 +115283,ACT,4 +115298,RDA,4 +115334,ACT,4 +115349,WRA,4 +115392,ACT,4 +115407,RDA,4 +115443,ACT,4 +115458,WRA,4 +115459,END,0 \ No newline at end of file diff --git a/test/data/REFB.commands.trace.gz b/test/data/REFB.commands.trace.gz deleted file mode 100644 index 9bae89e97925ce7d5ec9f319dbb2e8e39782d501..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 10279 zcmaL7XH-*L)HZrV5TyzTgc?M84;_IZC?FjKkzN7_8X{dk$1 zd|)uwC+-0C)s{1=NEPJV8%m0~+|{F+ ze1=Dy6_F2$_Qoa==XmmYE&aaRZqbR`uJiHK!`d^YStEW?@_zDwqg6@+;$#gg^ND;q zhB!MQqY(ZOemD7)`c5r1^3&5ZgR)$ip+azcb?3k)!XLL$ZNyQ<{}DE!gRgqxMZZHP86F&XqpR?Hmo^k2_MIMnOD!@ojTa}`s@>iyg6=h6 zt8(Yeiszcn)~%0lb!~U?Xm>3LbtwtWx6Ln9t5R4U33Z!z#PWW8Iqz+7Y-Gc3k6dGo z63h}l{ey8o4|V2wG_pW{W4xIf*7@kyMT-R_%ACELeL6Q-3_7On-P)-pypcD=JX$;S z?MTUX!5y`eH^SKRRawNIeN!by_VnRS3^*dy=aQCcUfIj9+hW0=bDL$n>>G-4o3=Bq1o>C9PU?94e_^yXWJ?k8^_M`BNxhkqS+{_|&Xp;ouo%&+&@ zdM0*3;-LO3T0aTY8~_#RQTov&2;x%bxv=oJp_1KvBo0v>bBOeiI6t`)8ztR5Z#_ZXEQ zmTmI+aU6rL)J1mbF>Tn#1&P-!G{cu#q*W5PdeJj3nq8~N?ey^cuAzXgo7X&bh{$bv z=EnQC>{q-tA|e`p-@KsAG|dZZ_h|eLrcq|_PEuy)f=RS@>piQPc&D$Ihv8KBzBbJb ztMqLAP#LBB%u@H+#u_#3-T1>RFzfME+F6H^5w=-~wmq*GeN6LRuVETkXt6Zotb9og zMA`L`2o74To&0eGPf^Ea-xLz{~h1{53Ws`sy(?k^S5l<4u^0U+N|!uP2wS>eoT^ zBfZUMdlMXR83$+(z_tV$kl>gi}@HZO%(%8eSLm9@rK>0pK9t2D5v44q5< zbX<1@+y!D%$V)>M+JE*fQKtB{C^_JoBbx(78gBZI(?p-dg#-DnaVr5p^ zrZhD#p!)3WbYe3ml1Azit?*so5AE~fWCZD&_*OcK|6Wo(H|xA_~_3dx5RKCEtiN*uz31UTTZL*-D~ z6cY=l4w<1v-hCY`45T^tzK9qVB$$F#4)c5gs1CtUGm=3^^M@&>Jv;MS;k|bATHyL# zv6I<4V+ls}2ak3~+7I;)m2sJ23Kc2|VWOIQb@vEwEBIyBbRVv}-Y2yUa_$N;@73Kr zx<;buuxHxc&P$~(GDH;z7hUY=IFTV;>F5|Q3EsFu62Y;BwMehS;tVhqEx))zoPTT> zc0BoEr1D8+>#ke56ZdPhZbzd~QfAmALvGH!Z&`}g>*b(F44&VJ^pkHvNCUU*bm>6R zBv&);-Xg^p+A}(F-vAutAPqye?2O1QU-2YYOYYwHiZ3jFf4K1e8^F38grtNrr2{3C zV#8{kkLKQlANcK$#6%>FpknKMmNxB$PO|bMhI>)v4L&)W_OSgLrW5PYU<*0k6Di6T zMglG_sqGIxW9VGExj!8BERHaZuuVDk;XONt0c5cqN-mW>!qDlTKr#k;RWB^#`W{u4am;|5qXUw5Hvq?LgmK6O< zKe0a}?ti&Q|8KWRjVVZ#DTv`r)_x5^Gw_}jTV^B&Zck2UzFq_X{)+Y+k9Z9iJL*%d zxQs4wo)QF_qU4zPOhHUxR)hMlWfNm6U3jhT58(x!e?a5HOg>D#4y&n{dMrQ1m$U!& zBM&e+MslFLX&U3FcJN85cR-o6fH~Z0QE|%ukHOw?NH@ndoGlQei%EnpQZ0Er0b{bf zNgTL~Q#7*S3a44OF|Xja2*ZmEvJhNEI`dkDZT?aUb*L8ZVwkgtXGo?XK@a?4N_lU# z#3^9C>8;bkkBzu6XH&c^$8K{sil#P9DzwvWh@RgFvtmP%A9&TG7V#0X@JdC+8re=1 zUdxl!#FY(lVsy>yk@O3XaRKSFNcy6Lg*c@_$;sleJwk7+(we6m<8i$%CJA}FHl_Bw z7tzVXiGc1vG-;8KU*qipR_p>yJWeDURp!?f(M_ZMn`2}1I|fr<`dXQTUFG-LfdXNd&dew`n0j~WxPKl-4>S?aJi+lMb&Zb8G3Fah8Ma$@y< zra!23LR#)Emsh47v_=33#2vgQ|2a~BzG`$VT;nt}CC)9~Y%Ph%&s-z`jDs(C41}b_ znWd2@r+OET+e4586bd`EcVh z6RD5orF6@WbREZrO~-2TgAKqLa0nPjsUDQZEb5%itcJn5vXjzq^nb1oglkkAf;o>$ zouoqw8yUya-)U2p5ZBHTN(Ruh;LR2_e(Vwq2TKnQDTKG^AnL1oSx&5bP?_~U>}&Ql zv8cUfzd`#n=G~fLSE?A27ex zZy6vwJax^{(IEttuzYl0Hig(dPH`en@I=pMu}k0(yXX|m;Y6NR*dKkL^RHc)~ zaGRq@QOW%{=3`6HMD3V558=S$R`=&Lv$bF0w+X|~q7MX$bof1}ND@1!gHIl!v%_j$ zvQ9Y5Zr~&a`Bm(28uxvu>|D?3=dT5(KoFYDf8+`0Hq$fQW;rJ^-(iH5sK3s|1i`NCHp9xW{%e*H!2?IHTP z-Y=0Hro&GjHC;*08?b^ae-uAL0-%;uK{81eYu^Bw6k7ild8vuQo8JIGWs(vIRmuww z>Ur&7(ab~$6n#pKWUmNq17H!8-G`l@R2%h`5|KTvODgNGxJ-1EzHZ{~WVD}ZbZ$0U z?A4>h%51bMmm+$oI2e@Az>Reu2Z+W{l)HIBo4Wdb@?MGQ+HUy_PbTnI+y@yBmXGIc zR6+wt!iy0!AQATNj#}b` zD4@(tUav^py%V8czR6tmse^q^{c*rpMkCo39{~8wgQXk+<>VbNs`6<55P~8;EkS} z_tkVT>2OHl+Dx`+Sn_MFiq^@tdbldboak!Gr>siQs}I~|xs{+VAHwX}lP}U&Za*FN zb1}#igI01&4n*C*pOk==E8KEjQ9TV&J|lV`V`p{;8h)pEeg}@d(<(GUXyl#$8wkVx z=Cp@_E8-JW_OH%WJ2#I|J!G?%YY`SFJ;Ys%XlNK$QU5e#pUS*D61aqPk%&XGA3Z}T z&rK`LodZG_aJ@rieS0tTk@NxA+LZM&p>7#%82_NJ2K3k3G2@SM7VEQsrjHSHI`tbh zLCmDxdd+^hgKG1gSpa)&k_9QO3JW^mzM*%bqr3sBK5GuQIYF5V%>nLzO0p0Mhf$&5 zgOEu+?rkzM8VGRbac?>dmgo(|+ISbC_baqI%g?9(I8uWuZqq?hjV>QCkm3p4r&93g zMJ@iX2#suVh#Z;da*pjj9f(m{C9E$I9`llNaBR*&tbz|Rx?g*s4s1($~q?qton@& zH_ma8b3c8W=fuEUnv{Gd{|LQVH zj`K}`OzT*FKzDzDOvs_okvYkB(PZ)Sx4<+!msXPJX`^qmY(6l2NYL|jve`}9^CP`i z=b{DYqA`E%y|nVcbzbMvy{u{G0DQP=y|EWOZ$wzMNYGu9XQJ-A}agG@%oKl%{qRGAg{N`7aOnH_2UwEy= z1I+sgW<1!7KfuZA5Xgwh?=xyxZNGH@c1Zc81Ou=|3fi zk`Z&p=ZIeftnctIK+Al@Jo)7LX%h(UIST;h7B+tcu+8zZvGuK?Uruxk_il9NLfHnxu)4$p%7{?djLukPZR2)L5o9hWE*~2tv5&ZD1>S zc_gmE=`iD(lh1iR`~K?F<&XgN&gp~j$@r9Xf)BGat?Hob$ur*3XisZM$iss6HAjT< z$y0zuA;9Ub{w1UiYp*13FpAceMtb?!3bum`6f1m#%8pN+_V)$^_3(L6VK6=W}K zueuZnb(;;VZnfHd@DKv`5qV+EdRs)k=)sTv_rxu}<1g?9XzaqlRKMqIAH7JaozTmU zOtFNkcI)Q*XM_>?os$J6zX~bnvbpWL0Ns??w7C^qr}KRwm6UIat`&ZqxC5*4%jF1WyW>iGv5qJE_MrWP>wPZ9n{e7%|QiyC#1_pfD*_ofVUK@j+R zQFL%vBxpHY1B4o2QyznhPW{%228iy*qn=ck^^Y>$hkO!$M^bzAbM;!ycCH`HibUD{oVCz zIGbHxsY>32O9PN}H&6&r^u>W6WGybf1Sqm^5a}{<1#iba+N8+a9tc_c#yX}KM!Z6* z*UyOG-C~I^F%o?tQ!xEEqtl%er;lF5gN}R~rX%jf+Utw8N`suj3nGVvIoxv7AgAbp z@}cZ3b~$KpN*i_M-(op#LvVrNl=G(_aXF+26H@Pol&!=rj}TFNrx1JyBjKT%XJ@eG zz@OG?XyL$0zo8n^E2ZaeBPMDZV_y>Z{IkazNXs?2UenTmE(&@~@1>DV!J9%JRB^nk z(FJ$#|3Z_(6ui)UYrL8O7i#;~mbPk$*M1^dKs!_u$nW0rEi@XNIYRuh6wI*qY zSZ}paIf^1~Q=T@+J22k0O!9OW{);CK*3Rr59Pj$sNGbsy%iHYBJlmt`MSoB%|K(Zj zd`z=H^XwN*FUf;q7{&2pjyCJ>pO0C*;RiYpIMi|Ys(Bg3$Qi&KUEA|lPWSyQ3;mVB zSN_Uo|08q%l{+r|m20C2-Tm{>#c)b(?nC~+GK%*9TUJANtO5>lvGdU6fLgWDj#brz zT()_rsc)@XcgHIA0XNq?)ZMo>t-C|-(gAl4#qqCA8|u*GIN&bvae^GKQg$Zn-h9k+ ze7}T-tm#+HyUGUwOQC*{e9kEgY21yt@N{0Bp>d*nJY`jJflTX2);&&75o_<6j=>e& zaAr8U2bq4uO1mHJz@M6_?=2{8wj5s%c+J5PxqoUXvAcN`&%&4wnCOaS-o_sC8^FaR zAAI?;WLW?J{|w4V^44b^#AN|K%v({l&C^+muw)Dkk7tw1Wp%Orhx`-J+7m}-y4}wR z@ovI-c{V8w{{EWsJYqEVq(#v}(=5Z({h4{e;6Eid(=O-)30}Mt>399&9SB8qj3a-} zAb(Ef(y1-LId-OTl|~cu;qEW)CVst|34FYGP8-<}p9T^H$?FN}p)cRp{ueL%1_5aR zt{YbD6a-mUI>Te%qn}gA(_t%YG%10Tj*Nt7vM|rKejUhC^X9+oI!(Tazd{+D0i}36Q-D$$ z;c|TNyC0LAp0bQo%eTSsHn+Jt8#0`{Hi=29caX+tvfX&tJ=x&q0DlfY+~N85oa5=? zIuC2C6GIWas&{o@A-S40KJ9+bcHzlJo-yU!^`bHwoUfg}pK@eCuz%h-Re2-Po1Mmt z$n5bM6+-75Flc4bEzY-MmIfdmSE;oYDWrPCIi%;Ca2!}l>ak;5pK-+6$Iw@2MKb5uhRT*yuV zv%2!I=-@BxEL-s`6HlI?$xVx7l<_4_TCz$andjy8%4e=SZu#hewopiZ-h0)hhBp9k zc>Ge{8vrWwMa6i+Ql4k`p9uOw!g~?g4l&SfDeuzao+t4bUqm@hXpr+0{LZrh_>}mi zi#b(S-~wz#+NjG%Jw#OX<5)LeWW6e;rP;xo*Jrx>thdN7Gsim^~*Q2EH| zPPm)6$@jrkK+*u>E=(luzUncny{i$2Jr7`-N0{c*;ONw;r!<^vd!iL~`&4fqJc361 z*monEi3!Zd=G|5)ogAYLBqM(OY`ovct>LSAixi~R3dqL_>AkzU04*sBhwZX~L}F?1 zZ7aFNz?eR<3yUu=v}KQZsaLA~AWl(fJwLdTKNYTKrg6?SxSR@zcVfHo9V){UqR)!u z6Q5GMCaby|WWbP@SH!rmInTbB=Lm>UA6r$Bcq6o1)i+-2zi%n>&0X+?Pe3mgFOy3fLo03g(_Mr2=fnSrt|)O;#OD&Ro;S zs;iW9p8n+c^Kmsx24{Ib)q)dMvCrs)eOXXm@yR2#BxReJMeqlF$avszqaq;<5DWTJ zklwF-ZAFGoOa1Zk*=9v@_4Utka4E@>7-E=nE9PB{Pk4F?H+7I=L|5<+o{HzyI$#MV zA-$ofp0NY@`!Phg?8eKvp*JRA$Ul5D+A{n2^qg682skHxOu+d$yw9}Vtj|>B1vvn6 zs3oe5L0lqqDib=H2%U>$2mM{Tb4sNAof2t@oDVo3i@oltHTWt6V4KEzL-O^Bk!B>( zigLcGy>xD*6-f*vt)$joI5*OcBy!^tUi)PGoPSGoMsgf2<9Jpx2Npxz{E#KQK7aw9 z!JgLuTN{${e@utvOY9E5%BBC%HT>!DI@2UN+kwZe$444;I$1ev^9MVVi#Cx?JWy2r za`+bAt0~EJP_6oM>TY64Qcrf#heDUgo>~&bJkg5v+dfh3d<`moZ{r!Fdg1$qvHtoJ9rn zMFl)X1-+sYAb2S$Guq6m!zt#p*ORlylXLJsYv#8jBK{Wdov%@?dUT}9dFV6hP@M-4*jdPL3!yn0ggITOH~vTFC6L*Dza!-Ks3na* zDz=z^;Svr$tQ932ciN>cAF;^S)?e85KHtan{XmKc-pfB(1pmzJfz`MC1769{5uPb- zd`(jPQVVaU5Y1^D!)YkT(aw<>LlOBjI+jlfv{|ut1RjjzQ<{A7uUD_US@9QpzdO6N zc50ILX6;KhLlo{uIz z$$DBGGV<(n7Q`N?f39|S(gqtM`?F$$f`&Oru-60|m1dc09`+yF zsE)(jTgkD@JaD^v8;+ZK!2OY=h(9h1kOm*W=@w46AirWCe1xPUJQ0rb7XQOO+4u)i zEd$mDpSs_JMHLxC4u^zZ6dAi}Bs5$N$N-!xsL?NJrBgWmKk{Qb^^|xtD**ggVbi~~ zA`s_)wS-qljFvAWhX0Fptp9j1ulGHsr((30U%I2Qdqc$I=U`vBHc&N6p|(%;4;`0k zuVJD>b)Ra=-NZjHQ{x*d`&6qW7}N%F@T;pk249cNlL?EmqqMg9%%9YN?g8MzRZ1Yn zFer1(k*Vl2FE}_KJ7(WWHO7ZOzDOZXq7ME^BSCMHqCm^#e4I6v!b(kw{AUQOacwr8Ty>mo7u-fy_T7>SDVj%%YI0l9W!n_e zjd7%A!06hXjJ(><(@eb%ito4k@QLVQLk(v19CE9ReSs7#w&1vsDSsu()RsEqi(v76 zjtfox))F1P9I+5v>Wxy7?k^R(JFZutc&oOnR%7B+djYR*(G&=p-+mtmwVDv83JQGE zofiDWmije#gziqR_m#I1?bMP{xUk`S0<52h1WePl8!N?FJERN`ACcLj$P*J1@7BD8 zEdv{K#czg9WVDHhRDZNyzVo2Uue6F?ZQ^HT{@N1{)4-OSqQ_qmEk0xC2RBsDf_UC* z8TSJ(IL{b~5uTbS)Lnk=!x?qBW#o-9N$vh{`T0}MsOfE^{CysGKZ#QI*|tz+xqGnk zr&jhgd_S$d@vDQk5}N$gRg5m#n=dw9&IpmF(sfF>l`~ZdZ4k9T^@0+A+V$8ODRT9B z%e$mHu)KWz`A*})qDJTCci&B;j~e6ZQ@vQeR%j;n-${2-n=q0(O)o8g9gc$=W)<$@4zV2?Uy9B#s{yfL*OU76fp^oN?opIn})=~u&UF^q<&ml@!z zMG6A+PLl4PFf#eSzM7A_=4TCMfl6;V%E1WHzZau@+FKX%nuEI=JLuotwXmj1Pc7TD zHhb)^0P}C~^8Yh~TYWz?(lj(uHYEKp-TrR6saQGI&HN_#T{DMmjjlK!;<^S9)X_Bf zNSeE*zm@$k@Cgm-QaKiCaT7HwvRwsRM$L(Af2L5seS*c!(U=3l$w$&R?GluJ^J3M5 zHTf~{0Bx3aLGu^wm#Nn{qAvduYOJ~c5mw_5gJweQtLA6zRwgGUTAHofnwly{S*Dj^ zy8b>Jra65xtYt$257RF&M{u6-9i4vdG@l+D@ek3Htod>_{$B$ zQ>=!;mSE5Xa9XL^+ch@v<2$dscx>*>by3{Ig*$XlVE5aZ{i{+Kpwbmtj?|~%*Tqb`2w5TCQD5&)fkT7ziOAD$knK$-E^wL)p$?4sY{8g5u$yt z^3X_<)2abERLss$8E44#)mpyda)qj}GX>PpPFJ;(Qn7*=I=Yb=2?`7;cuc`7I^ph0 zoq*;~I=UKAT^6~iU!^e_bKb&nuU$q;)a)lH_({P`iG;maO@H1z6MQ}4nPmjywTVt$ zfztz4(|9`86OO3CMM-hI&$aq)T>;hB%NdN)g6hWvtxl?huhJH!dW*g+R@_xI&bB;619ZRDtYaX%u}-#(_&^(WAwCbrU*)rt|HYsHveOr<*Y zmMWW?y{nCby-TR#pV6j@e?+ut>I_-#U4mL(Fpj2MbWqt|oSUuu;j&Tjb{7?a7w zW@-n7Z{r<%Dv5{(&__mHubQbhC$gSt&a&3&+f(g(8FdwI=`J*Mtc5poMvU#35`H@E zcFZO?9o5S(HKH_B9JXf~b<{_u*ntf{WY z=n1_P@tzWMQ&Zib(H4J3_l%UNjV>Fq>F|-XHdj99+g%oUy9CQi_ Date: Mon, 3 Oct 2016 10:32:01 +0200 Subject: [PATCH 09/12] Correction of unit test. Fix the path in the test.py referring the command trace which was wrong in previous commit, also replaced the PASR.commands.trace. --- test/data/PASR.commands.trace | 6 ---- test/test.py | 66 +++++++++++++++++------------------ 2 files changed, 33 insertions(+), 39 deletions(-) diff --git a/test/data/PASR.commands.trace b/test/data/PASR.commands.trace index b96ee098..74daf56e 100644 --- a/test/data/PASR.commands.trace +++ b/test/data/PASR.commands.trace @@ -10,7 +10,6 @@ 134,RDA,5 137,ACT,0 152,RDA,0 -171,PREA,0 173,SREN,0 1174,SREX,0 1279,ACT,3 @@ -61,7 +60,6 @@ 2215,RDA,1 2216,ACT,2 2231,RDA,2 -2252,PREA,2 2255,SREN,2 3260,SREX,2 3371,ACT,1 @@ -128,7 +126,6 @@ 4451,RDA,1 4452,ACT,2 4467,RDA,2 -4488,PREA,2 4490,SREN,2 5495,SREX,2 5607,ACT,1 @@ -308,7 +305,6 @@ 9590,RDA,3 9626,ACT,3 9641,RDA,3 -9662,PREA,3 9665,SREN,3 10670,SREX,3 10797,REF,0 @@ -430,7 +426,6 @@ 13788,RDA,4 13824,ACT,4 13839,RDA,4 -13861,PREA,4 13870,SREN,4 14877,SREX,4 14995,REF,0 @@ -3053,7 +3048,6 @@ 121007,RDA,4 121043,ACT,4 121058,WRA,4 -121079,PREA,4 121085,SREN,4 122119,SREX,4 122130,END,0 \ No newline at end of file diff --git a/test/test.py b/test/test.py index c8e07537..fe37c2c1 100644 --- a/test/test.py +++ b/test/test.py @@ -116,7 +116,7 @@ def test_transaction_scheduler_with_self_refresh(self): def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh(self): """ drampower output for REFB trace matches reference """ - refBCmdTrace = 'traces/REFB.commands.trace' + refBCmdTrace = 'test/data/REFB.commands.trace' cmd = ['./drampower', '-m', 'memspecs/modified_MICRON_1Gb_DDR3-1600_8bit_G_3s.xml', '-c', refBCmdTrace] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_refresh.out') @@ -147,192 +147,192 @@ def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_bankwise_Rho_100(self): def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_0(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 0 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','0'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','0'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_0_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_0(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 0 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','0'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','0'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_0_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_0(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 0 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','0'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','0'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_0_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_0(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 0 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','0'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','0'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_0_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_1(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 1 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','1'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','1'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_1_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_1(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 1 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','1'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','1'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_1_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_1(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 1 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','1'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','1'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_1_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_1(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 1 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','1'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','1'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_1_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_2(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 2 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','2'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','2'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_2_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_2(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 2 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','2'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','2'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_2_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_2(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 2 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','2'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','2'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_2_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_2(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 2 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','2'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','2'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_2_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_3(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 3 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','3'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','3'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_3_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_3(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 3 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','3'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','3'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_3_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_3(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 3 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','3'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','3'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_3_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_3(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 3 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','3'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','3'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_3_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_4(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 4 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','4'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','4'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_4_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_4(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 4 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','4'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','4'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_4_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_4(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 4 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','4'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','4'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_4_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_4(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 4 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','4'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','4'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_4_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_5(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 5 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','5'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','5'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_5_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_5(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 5 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','5'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','5'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_5_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_5(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 5 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','5'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','5'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_5_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_5(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 5 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','5'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','5'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_5_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_6(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 6 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','6'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','6'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_6_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_6(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 6 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','6'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','6'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_6_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_6(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 6 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','6'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','6'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_6_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_6(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 6 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','6'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','6'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_6_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_25_pasr_7(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 25% and PASR mode = 7 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,25' , '-pasr','7'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,25' , '-pasr','7'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_25_pasr_7_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_50_pasr_7(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 50% and PASR mode = 7 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,50' , '-pasr','7'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,50' , '-pasr','7'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_50_pasr_7_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_75_pasr_7(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 75% and PASR mode = 7 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,75' , '-pasr','7'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,75' , '-pasr','7'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_75_pasr_7_reference.out') def test_MICRON_1Gb_DDR3_1600_8bit_G_3s_Sigma_100_pasr_7(self): """Bank-wise drampower output for MICRONMICRON_1Gb_DDR3-1600_8bit_G with the PASR commands trace with Sigma = 100% and PASR mode = 7 """'' cmd = ['./drampower', '-m', 'memspecs/MICRON_1Gb_DDR3-1600_8bit_G.xml', - '-c', 'traces/PASR.commands.trace', '-b', '100,100' , '-pasr','7'] + '-c', 'test/data/PASR.commands.trace', '-b', '100,100' , '-pasr','7'] self.run_and_compare_to_reference(cmd, 'test/reference/test_MICRON_1Gb_DDR3-1600_8bit_G_Sigma_100_pasr_7_reference.out') def test_broken_trace(self): From b1b78f992ccc862e40f717b4ca1aec2c3e3d37a4 Mon Sep 17 00:00:00 2001 From: Subash Kannoth Date: Fri, 7 Oct 2016 17:18:50 +0200 Subject: [PATCH 10/12] Fix for clang compiler Clang throws "implicit conversion changes signedness" for when signed type "int" was used for array indexing. This replaced with unsiged. --- src/MemoryPowerModel.cc | 10 +++++----- src/MemoryPowerModel.h | 2 +- src/cli/drampower.cc | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/MemoryPowerModel.cc b/src/MemoryPowerModel.cc index 4cd1a491..4ff47b9e 100644 --- a/src/MemoryPowerModel.cc +++ b/src/MemoryPowerModel.cc @@ -203,7 +203,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, int64_t tRefBlocal = (t.REFB == 0) ? (t.RAS + t.RP) : (t.REFB); //Distribution of energy componets to each banks - for (int i = 0; i < nbrofBanks; i++) { + for (unsigned i = 0; i < nbrofBanks; i++) { energy.act_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofactsBanks[i] * t.RAS, mps.idd0 - ione); energy.pre_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofpresBanks[i] * (t.RP), mps.idd0 - ione); energy.read_energy_banks[i] = vdd0Domain.calcTivEnergy(c.numberofreadsBanks[i] * burstCc, mps.idd4r - mps.idd3n); @@ -331,7 +331,7 @@ void MemoryPowerModel::power_calc(const MemorySpecification& memSpec, // energy components for both ranks (in a dual-rank system) if (bwPowerParams.bwMode) { // Calculate total energy per bank. - for (int i = 0; i < nbrofBanks; i++) { + for (unsigned i = 0; i < nbrofBanks; i++) { energy.total_energy_banks[i] = energy.act_energy_banks[i] + energy.pre_energy_banks[i] + energy.read_energy_banks[i] + energy.ref_energy_banks[i] + energy.write_energy_banks[i] + energy.refb_energy_banks[i] + static_cast(memArchSpec.nbrOfRanks) * energy.act_stdby_energy_banks[i] @@ -369,7 +369,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, if (bankwiseMode) { cout << endl << "* Bankwise Details:"; - for (int i = 0; i < nbrofBanks; i++) { + for (unsigned i = 0; i < nbrofBanks; i++) { cout << endl << "## @ Bank " << i << fixed << endl << " #ACT commands: " << c.numberofactsBanks[i] << endl << " #RD + #RDA commands: " << c.numberofreadsBanks[i] @@ -418,7 +418,7 @@ void MemoryPowerModel::power_print(const MemorySpecification& memSpec, int term, if (bankwiseMode) { cout << endl << "* Bankwise Details:"; - for (int i = 0; i < nbrofBanks; i++) { + for (unsigned i = 0; i < nbrofBanks; i++) { cout << endl << "## @ Bank " << i << fixed << endl << " ACT Cmd Energy: " << energy.act_energy_banks[i] << eUnit << endl << " PRE Cmd Energy: " << energy.pre_energy_banks[i] << eUnit @@ -517,7 +517,7 @@ double MemoryPowerModel::engy_sref_banks(double idd6, double idd3n, double idd5, double sref_ref_pre_cycles, double spup_ref_act_cycles, double spup_ref_pre_cycles, double clk, double esharedPASR, const MemBankWiseParams& bwPowerParams, - int bnkIdx, int64_t nbrofBanks) + unsigned bnkIdx, int64_t nbrofBanks) { // Bankwise Self-refresh energy double sref_energy_banks; diff --git a/src/MemoryPowerModel.h b/src/MemoryPowerModel.h index e8b19749..4202e84d 100644 --- a/src/MemoryPowerModel.h +++ b/src/MemoryPowerModel.h @@ -76,7 +76,7 @@ class MemoryPowerModel { double clk, double esharedPASR, const MemBankWiseParams& bwPowerParams, - int bnkIdx, + unsigned bnkIdx, int64_t nbrofBanks); int64_t total_cycles; diff --git a/src/cli/drampower.cc b/src/cli/drampower.cc index 3e553e3c..b1be5eeb 100644 --- a/src/cli/drampower.cc +++ b/src/cli/drampower.cc @@ -105,15 +105,15 @@ int main(int argc, char* argv[]) bankwiseMode = true; try{ idx = bwTuple.find(","); - bankwisePowerFactRho = stoi(bwTuple.substr(0, idx)); + bankwisePowerFactRho = static_cast(stoi(bwTuple.substr(0, idx))); bwTuple.erase(0, idx + 1); idx = bwTuple.find(","); - bankwisePowerFactSigma = stoi(bwTuple.substr(0, idx)); + bankwisePowerFactSigma = static_cast(stoi(bwTuple.substr(0, idx))); }catch(const std::exception& e) { return error(); } } else if (string(argv[i]) == "-pasr") { - pasrMode = atoi(argv[i + 1]); + pasrMode = static_cast(atoi(argv[i + 1])); bankPASRact = true; } else { if (string(argv[i]) == "-r") { From abcdd0184e846fcf033ca82af9b559341d840d97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Mon, 24 Oct 2016 23:48:30 +0200 Subject: [PATCH 11/12] Update MemBankWiseParams.h --- src/MemBankWiseParams.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/MemBankWiseParams.h b/src/MemBankWiseParams.h index dd8e9927..0cc98fb4 100644 --- a/src/MemBankWiseParams.h +++ b/src/MemBankWiseParams.h @@ -40,6 +40,7 @@ #include #include #include +#include namespace Data { class MemBankWiseParams { From 767cb378c649a39aa5b0e8630be5c9130ec03ec8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=89der=20F=2E=20Zulian?= Date: Tue, 25 Oct 2016 12:42:23 +0200 Subject: [PATCH 12/12] Apple auto-generated directory added to gitignore --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 9e8b7069..39d47569 100644 --- a/.gitignore +++ b/.gitignore @@ -15,3 +15,4 @@ traces.zip cscope.* commands.trace coverage_report +.DS_Store