diff --git a/src/bootload.rs b/src/bootload.rs
index defc627..f10701f 100644
--- a/src/bootload.rs
+++ b/src/bootload.rs
@@ -28,9 +28,9 @@ pub fn jump_to_bootloader_if_requested(dp: &stm32::Peripherals) {
     let magic_num: u32 = read_backup_register(dp);
 
     if magic_num == MAGIC_BOOTLOADER_NUMBER {
-        enable_backup_domain(&dp);
+        enable_backup_domain(dp);
         write_to_backup_register(0, dp);
-        disable_backup_domain(&dp);
+        disable_backup_domain(dp);
 
         unsafe {
             cortex_m::asm::bootload(BOOTLOADER_FIRMWARE_MEMORY_LOCATION as *const u32);
diff --git a/src/counter.rs b/src/counter.rs
index a100a7a..ef174a5 100644
--- a/src/counter.rs
+++ b/src/counter.rs
@@ -8,6 +8,16 @@ pub struct Counter<PINS> {
 
 impl<PINS> Counter<PINS> {
     pub fn new(qei: Qei<TIM1, PINS>) -> Self {
+        unsafe {
+            // TODO(bschwind) - Expose this functionality with a safe interface
+            //                  in stm32f4xx-hal.
+            // Change the mode of the QEI decoder to mode 1:
+            // Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
+            // Or in layman's terms, the encoder counts up and down on encoder
+            // pin A edges, while referencing the state of encoder pin B.
+            (*TIM1::ptr()).smcr.write(|w| w.sms().encoder_mode_1());
+        }
+
         let last_count = qei.count();
         Counter { qei, last_count }
     }
@@ -16,9 +26,9 @@ impl<PINS> Counter<PINS> {
         let count = self.qei.count();
         let diff = count.wrapping_sub(self.last_count) as i16;
 
-        if diff.abs() >= 4 {
+        if diff.abs() >= 2 {
             self.last_count = count;
-            Some((diff / 4) as i8)
+            Some((diff / 2) as i8)
         } else {
             None
         }