From 932953a315b28b58984430e4746cc52186234c69 Mon Sep 17 00:00:00 2001 From: Brad Campbell Date: Wed, 9 Feb 2022 15:12:54 -0500 Subject: [PATCH 1/3] update nightly 2022-02-09 --- .vscode/settings.json | 2 +- doc/Getting_Started.md | 4 ++-- rust-toolchain | 2 +- tools/netlify-build.sh | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/.vscode/settings.json b/.vscode/settings.json index 4c86406b2c..7e105b2341 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,4 +1,4 @@ { "editor.formatOnSave": true, - "rust-client.channel": "nightly-2021-12-04", + "rust-client.channel": "nightly-2022-02-23", } diff --git a/doc/Getting_Started.md b/doc/Getting_Started.md index 3a5b5ee02a..284f97664f 100644 --- a/doc/Getting_Started.md +++ b/doc/Getting_Started.md @@ -75,7 +75,7 @@ of installing some of these tools, but you can also install them yourself. #### Rust (nightly) -We are using `nightly-2021-12-04`. We require +We are using `nightly-2022-02-23`. We require installing it with [rustup](http://www.rustup.rs) so you can manage multiple versions of Rust and continue using stable versions for other Rust code: @@ -90,7 +90,7 @@ to your `$PATH`. Then install the correct nightly version of Rust: ```bash -$ rustup install nightly-2021-12-04 +$ rustup install nightly-2022-02-23 ``` #### Tockloader diff --git a/rust-toolchain b/rust-toolchain index db56ccbd24..480e8aa7c1 100644 --- a/rust-toolchain +++ b/rust-toolchain @@ -1 +1 @@ -nightly-2021-12-04 +nightly-2022-02-23 diff --git a/tools/netlify-build.sh b/tools/netlify-build.sh index 19673f2f25..fbbadbc1d0 100755 --- a/tools/netlify-build.sh +++ b/tools/netlify-build.sh @@ -12,7 +12,7 @@ set -u set -x # Install rust stuff that we need -curl https://sh.rustup.rs -sSf | sh -s -- -y --default-toolchain nightly-2021-12-04 +curl https://sh.rustup.rs -sSf | sh -s -- -y --default-toolchain nightly-2022-02-23 # And fixup path for the newly installed rust stuff export PATH="$PATH:$HOME/.cargo/bin" From 6b34875fcc9b98be98a355fefd46c6e608cde32a Mon Sep 17 00:00:00 2001 From: Brad Campbell Date: Wed, 9 Feb 2022 15:32:29 -0500 Subject: [PATCH 2/3] remove asm feature The `asm!()` macro was stabilized in https://github.com/rust-lang/rust/pull/91728. This removes the feature and imports it through `core::arch` instead. --- arch/cortex-m/src/lib.rs | 3 ++- arch/cortex-m/src/scb.rs | 2 ++ arch/cortex-m/src/support.rs | 1 + arch/cortex-m0/src/lib.rs | 4 +++- arch/cortex-m0p/src/lib.rs | 3 ++- arch/rv32i/src/lib.rs | 3 ++- arch/rv32i/src/support.rs | 1 + arch/rv32i/src/syscall.rs | 1 + boards/nano_rp2040_connect/src/main.rs | 4 +++- boards/pico_explorer_base/src/main.rs | 4 +++- boards/raspberry_pi_pico/src/main.rs | 4 +++- chips/apollo3/src/lib.rs | 4 +++- chips/arty_e21_chip/src/chip.rs | 1 + chips/arty_e21_chip/src/lib.rs | 1 - chips/earlgrey/src/chip.rs | 1 + chips/earlgrey/src/lib.rs | 2 +- chips/esp32-c3/src/chip.rs | 1 + chips/esp32-c3/src/lib.rs | 2 +- chips/litex_vexriscv/src/interrupt_controller.rs | 3 +++ chips/litex_vexriscv/src/lib.rs | 2 +- chips/msp432/src/lib.rs | 2 +- chips/rp2040/src/clocks.rs | 1 + chips/rp2040/src/lib.rs | 2 +- chips/stm32f4xx/src/fsmc.rs | 1 + chips/stm32f4xx/src/lib.rs | 1 - chips/swervolf-eh1/src/lib.rs | 2 +- libraries/riscv-csr/src/csr.rs | 1 + libraries/riscv-csr/src/lib.rs | 2 +- 28 files changed, 42 insertions(+), 17 deletions(-) diff --git a/arch/cortex-m/src/lib.rs b/arch/cortex-m/src/lib.rs index 820f6e9245..a7c8729229 100644 --- a/arch/cortex-m/src/lib.rs +++ b/arch/cortex-m/src/lib.rs @@ -2,10 +2,11 @@ #![crate_name = "cortexm"] #![crate_type = "rlib"] -#![feature(asm, asm_sym)] +#![feature(asm_sym)] #![feature(naked_functions)] #![no_std] +use core::arch::asm; use core::fmt::Write; pub mod mpu; diff --git a/arch/cortex-m/src/scb.rs b/arch/cortex-m/src/scb.rs index 9dce9adc8d..8675f8a26c 100644 --- a/arch/cortex-m/src/scb.rs +++ b/arch/cortex-m/src/scb.rs @@ -2,6 +2,8 @@ //! //! +use core::arch::asm; + use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable}; use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite}; use kernel::utilities::StaticRef; diff --git a/arch/cortex-m/src/support.rs b/arch/cortex-m/src/support.rs index 18352ee853..58a1274f56 100644 --- a/arch/cortex-m/src/support.rs +++ b/arch/cortex-m/src/support.rs @@ -1,3 +1,4 @@ +use core::arch::asm; use core::ops::FnOnce; #[cfg(all(target_arch = "arm", target_os = "none"))] diff --git a/arch/cortex-m0/src/lib.rs b/arch/cortex-m0/src/lib.rs index dbaf32a662..50210d314a 100644 --- a/arch/cortex-m0/src/lib.rs +++ b/arch/cortex-m0/src/lib.rs @@ -2,7 +2,7 @@ #![crate_name = "cortexm0"] #![crate_type = "rlib"] -#![feature(asm, asm_sym, naked_functions)] +#![feature(asm_sym, naked_functions)] #![no_std] // Re-export the base generic cortex-m functions here as they are @@ -13,6 +13,8 @@ pub use cortexm::nvic; pub use cortexm::print_cortexm_state as print_cortexm0_state; pub use cortexm::syscall; +use core::arch::asm; + extern "C" { // _estack is not really a function, but it makes the types work // You should never actually invoke it!! diff --git a/arch/cortex-m0p/src/lib.rs b/arch/cortex-m0p/src/lib.rs index 493814647d..dfaede5e3f 100644 --- a/arch/cortex-m0p/src/lib.rs +++ b/arch/cortex-m0p/src/lib.rs @@ -2,7 +2,6 @@ #![crate_name = "cortexm0p"] #![crate_type = "rlib"] -#![feature(asm)] #![feature(naked_functions)] #![no_std] @@ -26,6 +25,8 @@ pub use cortexm0::generic_isr; pub use cortexm0::hard_fault_handler; pub use cortexm0::systick_handler; +use core::arch::asm; + // Mock implementation for tests on Travis-CI. #[cfg(not(any(target_arch = "arm", target_os = "none")))] pub unsafe extern "C" fn switch_to_user( diff --git a/arch/rv32i/src/lib.rs b/arch/rv32i/src/lib.rs index 7f710a213b..33247e9a34 100644 --- a/arch/rv32i/src/lib.rs +++ b/arch/rv32i/src/lib.rs @@ -2,9 +2,10 @@ #![crate_name = "rv32i"] #![crate_type = "rlib"] -#![feature(asm, asm_sym, const_fn_trait_bound, naked_functions)] +#![feature(asm_sym, const_fn_trait_bound, naked_functions)] #![no_std] +use core::arch::asm; use core::fmt::Write; use kernel::utilities::registers::interfaces::{Readable, Writeable}; diff --git a/arch/rv32i/src/support.rs b/arch/rv32i/src/support.rs index b824675575..53bf00a64a 100644 --- a/arch/rv32i/src/support.rs +++ b/arch/rv32i/src/support.rs @@ -1,6 +1,7 @@ //! Core low-level operations. use crate::csr::{mstatus::mstatus, CSR}; +use core::arch::asm; use core::ops::FnOnce; #[cfg(all(target_arch = "riscv32", target_os = "none"))] diff --git a/arch/rv32i/src/syscall.rs b/arch/rv32i/src/syscall.rs index 8b359df162..f95562893e 100644 --- a/arch/rv32i/src/syscall.rs +++ b/arch/rv32i/src/syscall.rs @@ -1,5 +1,6 @@ //! Kernel-userland system call interface for RISC-V architecture. +use core::arch::asm; use core::convert::TryInto; use core::fmt::Write; use core::mem::size_of; diff --git a/boards/nano_rp2040_connect/src/main.rs b/boards/nano_rp2040_connect/src/main.rs index 8bc4fa2dd7..d3fd8f6643 100644 --- a/boards/nano_rp2040_connect/src/main.rs +++ b/boards/nano_rp2040_connect/src/main.rs @@ -7,7 +7,9 @@ // https://github.com/rust-lang/rust/issues/62184. #![cfg_attr(not(doc), no_main)] #![deny(missing_docs)] -#![feature(asm, naked_functions)] +#![feature(naked_functions)] + +use core::arch::asm; use capsules::virtual_alarm::VirtualMuxAlarm; use components::gpio::GpioComponent; diff --git a/boards/pico_explorer_base/src/main.rs b/boards/pico_explorer_base/src/main.rs index 8d3f8a7aa5..c7ed03a64b 100644 --- a/boards/pico_explorer_base/src/main.rs +++ b/boards/pico_explorer_base/src/main.rs @@ -7,7 +7,9 @@ // https://github.com/rust-lang/rust/issues/62184. #![cfg_attr(not(doc), no_main)] #![deny(missing_docs)] -#![feature(asm, naked_functions)] +#![feature(naked_functions)] + +use core::arch::asm; use kernel::dynamic_deferred_call::{DynamicDeferredCall, DynamicDeferredCallClientState}; diff --git a/boards/raspberry_pi_pico/src/main.rs b/boards/raspberry_pi_pico/src/main.rs index ca65784a33..f88d7152e7 100644 --- a/boards/raspberry_pi_pico/src/main.rs +++ b/boards/raspberry_pi_pico/src/main.rs @@ -7,7 +7,9 @@ // https://github.com/rust-lang/rust/issues/62184. #![cfg_attr(not(doc), no_main)] #![deny(missing_docs)] -#![feature(asm, naked_functions)] +#![feature(naked_functions)] + +use core::arch::asm; use capsules::i2c_master::I2CMasterDriver; use capsules::virtual_alarm::VirtualMuxAlarm; diff --git a/chips/apollo3/src/lib.rs b/chips/apollo3/src/lib.rs index 7043bffd16..5d2288ce77 100644 --- a/chips/apollo3/src/lib.rs +++ b/chips/apollo3/src/lib.rs @@ -2,7 +2,7 @@ #![crate_name = "apollo3"] #![crate_type = "rlib"] -#![feature(asm, const_fn_trait_bound)] +#![feature(const_fn_trait_bound)] #![no_std] // Peripherals @@ -18,6 +18,8 @@ pub mod pwrctrl; pub mod stimer; pub mod uart; +use core::arch::asm; + use cortexm4::{ generic_isr, hard_fault_handler, initialize_ram_jump_to_main, scb, svc_handler, systick_handler, unhandled_interrupt, diff --git a/chips/arty_e21_chip/src/chip.rs b/chips/arty_e21_chip/src/chip.rs index 6ff85dff79..96fe148b7f 100644 --- a/chips/arty_e21_chip/src/chip.rs +++ b/chips/arty_e21_chip/src/chip.rs @@ -1,3 +1,4 @@ +use core::arch::asm; use core::fmt::Write; use kernel; use kernel::debug; diff --git a/chips/arty_e21_chip/src/lib.rs b/chips/arty_e21_chip/src/lib.rs index 99e9ea0112..265d6e6ee2 100644 --- a/chips/arty_e21_chip/src/lib.rs +++ b/chips/arty_e21_chip/src/lib.rs @@ -1,6 +1,5 @@ //! Drivers and chip support for the E21 soft core. -#![feature(asm)] #![no_std] #![crate_name = "arty_e21_chip"] #![crate_type = "rlib"] diff --git a/chips/earlgrey/src/chip.rs b/chips/earlgrey/src/chip.rs index 4ffb3f6a33..02ea4f7267 100644 --- a/chips/earlgrey/src/chip.rs +++ b/chips/earlgrey/src/chip.rs @@ -1,5 +1,6 @@ //! High-level setup and interrupt mapping for the chip. +use core::arch::asm; use core::fmt::Write; use kernel; use kernel::dynamic_deferred_call::DynamicDeferredCall; diff --git a/chips/earlgrey/src/lib.rs b/chips/earlgrey/src/lib.rs index 05b42032d5..877c12f7ef 100644 --- a/chips/earlgrey/src/lib.rs +++ b/chips/earlgrey/src/lib.rs @@ -1,6 +1,6 @@ //! Drivers and chip support for EarlGrey. -#![feature(asm, const_fn_trait_bound, naked_functions)] +#![feature(const_fn_trait_bound, naked_functions)] #![no_std] #![crate_name = "earlgrey"] #![crate_type = "rlib"] diff --git a/chips/esp32-c3/src/chip.rs b/chips/esp32-c3/src/chip.rs index abad6fe988..dbacacae60 100644 --- a/chips/esp32-c3/src/chip.rs +++ b/chips/esp32-c3/src/chip.rs @@ -1,5 +1,6 @@ //! High-level setup and interrupt mapping for the chip. +use core::arch::asm; use core::fmt::Write; use kernel; diff --git a/chips/esp32-c3/src/lib.rs b/chips/esp32-c3/src/lib.rs index f81fc99c90..beef722880 100644 --- a/chips/esp32-c3/src/lib.rs +++ b/chips/esp32-c3/src/lib.rs @@ -1,6 +1,6 @@ //! Drivers and chip support for ESP32-C3. -#![feature(const_fn_trait_bound, naked_functions, asm)] +#![feature(const_fn_trait_bound, naked_functions)] #![no_std] #![crate_name = "esp32_c3"] #![crate_type = "rlib"] diff --git a/chips/litex_vexriscv/src/interrupt_controller.rs b/chips/litex_vexriscv/src/interrupt_controller.rs index 0709a2725e..800dabea38 100644 --- a/chips/litex_vexriscv/src/interrupt_controller.rs +++ b/chips/litex_vexriscv/src/interrupt_controller.rs @@ -107,6 +107,7 @@ mod vexriscv_irq_raw { #[cfg(all(target_arch = "riscv32", target_os = "none"))] pub unsafe fn irq_getmask() -> usize { let mask: usize; + use core::arch::asm; asm!("csrr {mask}, {csr}", mask = out(reg) mask, csr = const CSR_IRQ_MASK); mask } @@ -116,6 +117,7 @@ mod vexriscv_irq_raw { #[cfg(all(target_arch = "riscv32", target_os = "none"))] pub unsafe fn irq_setmask(mask: usize) { + use core::arch::asm; asm!("csrw {csr}, {mask}", csr = const CSR_IRQ_MASK, mask = in(reg) mask); } @@ -127,6 +129,7 @@ mod vexriscv_irq_raw { #[cfg(all(target_arch = "riscv32", target_os = "none"))] pub unsafe fn irq_pending() -> usize { let pending: usize; + use core::arch::asm; asm!("csrr {pending}, {csr}", pending = out(reg) pending, csr = const CSR_IRQ_PENDING); pending } diff --git a/chips/litex_vexriscv/src/lib.rs b/chips/litex_vexriscv/src/lib.rs index 849e02a5a2..08683c4295 100644 --- a/chips/litex_vexriscv/src/lib.rs +++ b/chips/litex_vexriscv/src/lib.rs @@ -1,6 +1,6 @@ //! LiteX SoCs based around a VexRiscv CPU -#![feature(asm, asm_const, const_fn_trait_bound)] +#![feature(asm_const, const_fn_trait_bound)] #![no_std] #![crate_name = "litex_vexriscv"] #![crate_type = "rlib"] diff --git a/chips/msp432/src/lib.rs b/chips/msp432/src/lib.rs index 0f96b55394..ecb79aa21b 100644 --- a/chips/msp432/src/lib.rs +++ b/chips/msp432/src/lib.rs @@ -1,6 +1,6 @@ #![crate_name = "msp432"] #![crate_type = "rlib"] -#![feature(asm, const_fn_trait_bound)] +#![feature(const_fn_trait_bound)] #![no_std] use cortexm4::{ diff --git a/chips/rp2040/src/clocks.rs b/chips/rp2040/src/clocks.rs index 75b928e82d..933247e8f6 100644 --- a/chips/rp2040/src/clocks.rs +++ b/chips/rp2040/src/clocks.rs @@ -1,3 +1,4 @@ +use core::arch::asm; use core::cell::Cell; use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable}; use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite}; diff --git a/chips/rp2040/src/lib.rs b/chips/rp2040/src/lib.rs index c093273b03..8e5647434f 100644 --- a/chips/rp2040/src/lib.rs +++ b/chips/rp2040/src/lib.rs @@ -1,4 +1,4 @@ -#![feature(const_fn_trait_bound, asm)] +#![feature(const_fn_trait_bound)] #![no_std] pub mod adc; diff --git a/chips/stm32f4xx/src/fsmc.rs b/chips/stm32f4xx/src/fsmc.rs index ee4775b295..7e426480d8 100644 --- a/chips/stm32f4xx/src/fsmc.rs +++ b/chips/stm32f4xx/src/fsmc.rs @@ -1,4 +1,5 @@ use crate::rcc; +use core::arch::asm; use core::cell::Cell; use kernel::deferred_call::DeferredCall; use kernel::hil::bus8080::{Bus8080, BusWidth, Client}; diff --git a/chips/stm32f4xx/src/lib.rs b/chips/stm32f4xx/src/lib.rs index 3fbca4387f..721e9897fe 100644 --- a/chips/stm32f4xx/src/lib.rs +++ b/chips/stm32f4xx/src/lib.rs @@ -5,7 +5,6 @@ #![crate_name = "stm32f4xx"] #![crate_type = "rlib"] #![feature(const_fn_trait_bound)] -#![feature(asm)] #![no_std] pub mod chip; diff --git a/chips/swervolf-eh1/src/lib.rs b/chips/swervolf-eh1/src/lib.rs index 004e947873..0f3554843c 100644 --- a/chips/swervolf-eh1/src/lib.rs +++ b/chips/swervolf-eh1/src/lib.rs @@ -1,6 +1,6 @@ //! Drivers and chip support for SweRVolf. -#![feature(asm, const_fn_trait_bound, naked_functions)] +#![feature(const_fn_trait_bound, naked_functions)] #![no_std] #![crate_name = "swervolf_eh1"] #![crate_type = "rlib"] diff --git a/libraries/riscv-csr/src/csr.rs b/libraries/riscv-csr/src/csr.rs index 62716496c0..5de6f0727a 100644 --- a/libraries/riscv-csr/src/csr.rs +++ b/libraries/riscv-csr/src/csr.rs @@ -1,5 +1,6 @@ //! `ReadWriteRiscvCsr` type for RISC-V CSRs. +use core::arch::asm; use core::marker::PhantomData; use tock_registers::fields::Field; diff --git a/libraries/riscv-csr/src/lib.rs b/libraries/riscv-csr/src/lib.rs index af1f967775..9973435ab8 100644 --- a/libraries/riscv-csr/src/lib.rs +++ b/libraries/riscv-csr/src/lib.rs @@ -2,7 +2,7 @@ //! //! Uses the Tock Register Interface to control RISC-V CSRs. -#![feature(asm, asm_const)] +#![feature(asm_const)] #![feature(const_fn_trait_bound)] #![no_std] From dab6ffa0db0be7d3f1712dcf649a102c2d6f9a0e Mon Sep 17 00:00:00 2001 From: Brad Campbell Date: Fri, 25 Feb 2022 13:30:14 -0500 Subject: [PATCH 3/3] i hate cfgs --- arch/cortex-m/src/lib.rs | 9 ++++++++- arch/cortex-m/src/scb.rs | 3 +-- arch/cortex-m/src/support.rs | 4 +++- arch/cortex-m0/src/lib.rs | 8 ++++++-- arch/cortex-m0p/src/lib.rs | 3 +-- arch/rv32i/src/lib.rs | 4 +++- arch/rv32i/src/support.rs | 3 ++- arch/rv32i/src/syscall.rs | 2 +- chips/apollo3/src/lib.rs | 3 +-- chips/arty_e21_chip/src/chip.rs | 2 +- chips/earlgrey/src/chip.rs | 2 +- chips/esp32-c3/src/chip.rs | 2 +- chips/rp2040/src/clocks.rs | 2 +- chips/stm32f4xx/src/fsmc.rs | 3 ++- libraries/riscv-csr/src/csr.rs | 6 +++++- 15 files changed, 37 insertions(+), 19 deletions(-) diff --git a/arch/cortex-m/src/lib.rs b/arch/cortex-m/src/lib.rs index a7c8729229..1054afb2a2 100644 --- a/arch/cortex-m/src/lib.rs +++ b/arch/cortex-m/src/lib.rs @@ -6,7 +6,6 @@ #![feature(naked_functions)] #![no_std] -use core::arch::asm; use core::fmt::Write; pub mod mpu; @@ -41,6 +40,7 @@ extern "C" { ))] #[naked] pub unsafe extern "C" fn systick_handler_arm_v7m() { + use core::arch::asm; asm!( " // Set thread mode to privileged to switch back to kernel mode. @@ -71,6 +71,7 @@ pub unsafe extern "C" fn systick_handler_arm_v7m() { ))] #[naked] pub unsafe extern "C" fn svc_handler_arm_v7m() { + use core::arch::asm; asm!( " // First check to see which direction we are going in. If the link register @@ -133,6 +134,7 @@ pub unsafe extern "C" fn svc_handler_arm_v7m() { ))] #[naked] pub unsafe extern "C" fn generic_isr_arm_v7m() { + use core::arch::asm; asm!( " // Set thread mode to privileged to ensure we are executing as the kernel. @@ -210,6 +212,7 @@ pub unsafe extern "C" fn generic_isr_arm_v7m() { #[cfg(all(target_arch = "arm", target_os = "none"))] pub unsafe extern "C" fn unhandled_interrupt() { + use core::arch::asm; let mut interrupt_number: u32; // IPSR[8:0] holds the currently active interrupt @@ -233,6 +236,7 @@ pub unsafe extern "C" fn unhandled_interrupt() { #[cfg(all(target_arch = "arm", target_os = "none"))] #[naked] pub unsafe extern "C" fn initialize_ram_jump_to_main() { + use core::arch::asm; asm!( " // Start by initializing .bss memory. The Tock linker script defines @@ -299,6 +303,7 @@ pub unsafe extern "C" fn switch_to_user_arm_v7m( mut user_stack: *const usize, process_regs: &mut [usize; 8], ) -> *const usize { + use core::arch::asm; asm!( " // Rust `asm!()` macro (as of May 2021) will not let us mark r6, r7 and r9 @@ -515,6 +520,7 @@ unsafe extern "C" fn hard_fault_handler_arm_v7m_continued( kernel_stack: u32, stack_overflow: u32, ) { + use core::arch::asm; if kernel_stack != 0 { if stack_overflow != 0 { // Panic to show the correct error. @@ -571,6 +577,7 @@ unsafe extern "C" fn hard_fault_handler_arm_v7m_continued( ))] #[naked] pub unsafe extern "C" fn hard_fault_handler_arm_v7m() { + use core::arch::asm; // First need to determine if this a kernel fault or a userspace fault, and store // the unmodified stack pointer. Place these values in registers, then call // a non-naked function, to allow for use of rust code alongside inline asm. diff --git a/arch/cortex-m/src/scb.rs b/arch/cortex-m/src/scb.rs index 8675f8a26c..c504706cab 100644 --- a/arch/cortex-m/src/scb.rs +++ b/arch/cortex-m/src/scb.rs @@ -2,8 +2,6 @@ //! //! -use core::arch::asm; - use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable}; use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite}; use kernel::utilities::StaticRef; @@ -300,6 +298,7 @@ pub unsafe fn set_vector_table_offset(offset: *const ()) { /// Disable the FPU #[cfg(all(target_arch = "arm", target_os = "none"))] pub unsafe fn disable_fpca() { + use core::arch::asm; SCB.cpacr .modify(CoprocessorAccessControl::CP10::CLEAR + CoprocessorAccessControl::CP11::CLEAR); diff --git a/arch/cortex-m/src/support.rs b/arch/cortex-m/src/support.rs index 58a1274f56..78c3973aab 100644 --- a/arch/cortex-m/src/support.rs +++ b/arch/cortex-m/src/support.rs @@ -1,10 +1,10 @@ -use core::arch::asm; use core::ops::FnOnce; #[cfg(all(target_arch = "arm", target_os = "none"))] #[inline(always)] /// NOP instruction pub fn nop() { + use core::arch::asm; unsafe { asm!("nop", options(nomem, nostack, preserves_flags)); } @@ -14,6 +14,7 @@ pub fn nop() { #[inline(always)] /// WFI instruction pub unsafe fn wfi() { + use core::arch::asm; asm!("wfi", options(nomem, preserves_flags)); } @@ -22,6 +23,7 @@ pub unsafe fn atomic(f: F) -> R where F: FnOnce() -> R, { + use core::arch::asm; // Set PRIMASK asm!("cpsid i", options(nomem, nostack)); diff --git a/arch/cortex-m0/src/lib.rs b/arch/cortex-m0/src/lib.rs index 50210d314a..0cb44ab920 100644 --- a/arch/cortex-m0/src/lib.rs +++ b/arch/cortex-m0/src/lib.rs @@ -13,8 +13,6 @@ pub use cortexm::nvic; pub use cortexm::print_cortexm_state as print_cortexm0_state; pub use cortexm::syscall; -use core::arch::asm; - extern "C" { // _estack is not really a function, but it makes the types work // You should never actually invoke it!! @@ -37,6 +35,7 @@ pub unsafe extern "C" fn generic_isr() { #[naked] /// All ISRs are caught by this handler which disables the NVIC and switches to the kernel. pub unsafe extern "C" fn generic_isr() { + use core::arch::asm; asm!( " /* Skip saving process state if not coming from user-space */ @@ -132,6 +131,7 @@ pub unsafe extern "C" fn systick_handler() { #[cfg(all(target_arch = "arm", target_os = "none"))] #[naked] pub unsafe extern "C" fn systick_handler() { + use core::arch::asm; asm!( " // Set thread mode to privileged to switch back to kernel mode. @@ -163,6 +163,7 @@ pub unsafe extern "C" fn svc_handler() { #[cfg(all(target_arch = "arm", target_os = "none"))] #[naked] pub unsafe extern "C" fn svc_handler() { + use core::arch::asm; asm!( " ldr r0, 200f // EXC_RETURN_MSP @@ -203,6 +204,7 @@ pub unsafe extern "C" fn switch_to_user( mut user_stack: *const u8, process_regs: &mut [usize; 8], ) -> *mut u8 { + use core::arch::asm; asm!(" // Rust `asm!()` macro (as of May 2021) will not let us mark r6, r7 and r9 // as clobbers. r6 and r9 is used internally by LLVM, and r7 is used for @@ -325,6 +327,7 @@ pub unsafe extern "C" fn hard_fault_handler() { /// can mix `asm!()` and Rust. We separate this logic to not have to write the /// entire fault handler entirely in assembly. unsafe extern "C" fn hard_fault_handler_continued(faulting_stack: *mut u32, kernel_stack: u32) { + use core::arch::asm; if kernel_stack != 0 { kernel_hardfault(faulting_stack); } else { @@ -387,6 +390,7 @@ unsafe extern "C" fn hard_fault_handler_continued(faulting_stack: *mut u32, kern #[cfg(all(target_arch = "arm", target_os = "none"))] #[naked] pub unsafe extern "C" fn hard_fault_handler() { + use core::arch::asm; // If `kernel_stack` is non-zero, then hard-fault occurred in // kernel, otherwise the hard-fault occurred in user. asm!(" diff --git a/arch/cortex-m0p/src/lib.rs b/arch/cortex-m0p/src/lib.rs index dfaede5e3f..190e02a5ae 100644 --- a/arch/cortex-m0p/src/lib.rs +++ b/arch/cortex-m0p/src/lib.rs @@ -25,8 +25,6 @@ pub use cortexm0::generic_isr; pub use cortexm0::hard_fault_handler; pub use cortexm0::systick_handler; -use core::arch::asm; - // Mock implementation for tests on Travis-CI. #[cfg(not(any(target_arch = "arm", target_os = "none")))] pub unsafe extern "C" fn switch_to_user( @@ -45,6 +43,7 @@ pub unsafe extern "C" fn svc_handler() { #[cfg(all(target_arch = "arm", target_os = "none"))] #[naked] pub unsafe extern "C" fn svc_handler() { + use core::arch::asm; asm!( " ldr r0, 100f // EXC_RETURN_MSP diff --git a/arch/rv32i/src/lib.rs b/arch/rv32i/src/lib.rs index 33247e9a34..f3245acdea 100644 --- a/arch/rv32i/src/lib.rs +++ b/arch/rv32i/src/lib.rs @@ -5,7 +5,6 @@ #![feature(asm_sym, const_fn_trait_bound, naked_functions)] #![no_std] -use core::arch::asm; use core::fmt::Write; use kernel::utilities::registers::interfaces::{Readable, Writeable}; @@ -56,6 +55,7 @@ extern "C" { #[export_name = "_start"] #[naked] pub extern "C" fn _start() { + use core::arch::asm; unsafe { asm! (" // Set the global pointer register using the variable defined in the @@ -192,6 +192,7 @@ pub extern "C" fn _start_trap() { #[export_name = "_start_trap"] #[naked] pub extern "C" fn _start_trap() { + use core::arch::asm; unsafe { asm!( " @@ -439,6 +440,7 @@ pub extern "C" fn _start_trap() { /// https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/XKkYacERM04/m/CdpOcqtRAgAJ #[cfg(all(target_arch = "riscv32", target_os = "none"))] pub unsafe fn semihost_command(command: usize, arg0: usize, arg1: usize) -> usize { + use core::arch::asm; let res; asm!( " diff --git a/arch/rv32i/src/support.rs b/arch/rv32i/src/support.rs index 53bf00a64a..f652e4d3d3 100644 --- a/arch/rv32i/src/support.rs +++ b/arch/rv32i/src/support.rs @@ -1,13 +1,13 @@ //! Core low-level operations. use crate::csr::{mstatus::mstatus, CSR}; -use core::arch::asm; use core::ops::FnOnce; #[cfg(all(target_arch = "riscv32", target_os = "none"))] #[inline(always)] /// NOP instruction pub fn nop() { + use core::arch::asm; unsafe { asm!("nop", options(nomem, nostack, preserves_flags)); } @@ -17,6 +17,7 @@ pub fn nop() { #[inline(always)] /// WFI instruction pub unsafe fn wfi() { + use core::arch::asm; asm!("wfi", options(nomem, nostack)); } diff --git a/arch/rv32i/src/syscall.rs b/arch/rv32i/src/syscall.rs index f95562893e..04516cf4c0 100644 --- a/arch/rv32i/src/syscall.rs +++ b/arch/rv32i/src/syscall.rs @@ -1,6 +1,5 @@ //! Kernel-userland system call interface for RISC-V architecture. -use core::arch::asm; use core::convert::TryInto; use core::fmt::Write; use core::mem::size_of; @@ -231,6 +230,7 @@ impl kernel::syscall::UserspaceKernelBoundary for SysCall { _app_brk: *const u8, state: &mut Riscv32iStoredState, ) -> (ContextSwitchReason, Option<*const u8>) { + use core::arch::asm; // We need to ensure that the compiler does not reorder // kernel memory writes to after the userspace context switch // to ensure we provide a consistent memory view of diff --git a/chips/apollo3/src/lib.rs b/chips/apollo3/src/lib.rs index 5d2288ce77..c66e97eeb9 100644 --- a/chips/apollo3/src/lib.rs +++ b/chips/apollo3/src/lib.rs @@ -18,8 +18,6 @@ pub mod pwrctrl; pub mod stimer; pub mod uart; -use core::arch::asm; - use cortexm4::{ generic_isr, hard_fault_handler, initialize_ram_jump_to_main, scb, svc_handler, systick_handler, unhandled_interrupt, @@ -78,6 +76,7 @@ pub static PATCH: [unsafe extern "C" fn(); 16] = [unhandled_interrupt; 16]; #[cfg(all(target_arch = "arm", target_os = "none"))] pub unsafe fn init() { + use core::arch::asm; let cache_ctrl = crate::cachectrl::CacheCtrl::new(); cache_ctrl.enable_cache(); diff --git a/chips/arty_e21_chip/src/chip.rs b/chips/arty_e21_chip/src/chip.rs index 96fe148b7f..cd798d32ba 100644 --- a/chips/arty_e21_chip/src/chip.rs +++ b/chips/arty_e21_chip/src/chip.rs @@ -1,4 +1,3 @@ -use core::arch::asm; use core::fmt::Write; use kernel; use kernel::debug; @@ -110,6 +109,7 @@ impl<'a, I: InterruptService<()> + 'a> ArtyExx<'a, I> { /// valid for platforms with a CLIC. #[cfg(all(target_arch = "riscv32", target_os = "none"))] pub unsafe fn configure_trap_handler(&self) { + use core::arch::asm; asm!( " // The csrw instruction writes a Control and Status Register (CSR) diff --git a/chips/earlgrey/src/chip.rs b/chips/earlgrey/src/chip.rs index 02ea4f7267..babec25b42 100644 --- a/chips/earlgrey/src/chip.rs +++ b/chips/earlgrey/src/chip.rs @@ -1,6 +1,5 @@ //! High-level setup and interrupt mapping for the chip. -use core::arch::asm; use core::fmt::Write; use kernel; use kernel::dynamic_deferred_call::DynamicDeferredCall; @@ -385,6 +384,7 @@ pub extern "C" fn _start_trap_vectored() { #[export_name = "_start_trap_vectored"] #[naked] pub extern "C" fn _start_trap_vectored() -> ! { + use core::arch::asm; unsafe { // According to the Ibex user manual: // [NMI] has interrupt ID 31, i.e., it has the highest priority of all diff --git a/chips/esp32-c3/src/chip.rs b/chips/esp32-c3/src/chip.rs index dbacacae60..6085dcae24 100644 --- a/chips/esp32-c3/src/chip.rs +++ b/chips/esp32-c3/src/chip.rs @@ -1,6 +1,5 @@ //! High-level setup and interrupt mapping for the chip. -use core::arch::asm; use core::fmt::Write; use kernel; @@ -300,6 +299,7 @@ pub extern "C" fn _start_trap_vectored() { #[export_name = "_start_trap_vectored"] #[naked] pub extern "C" fn _start_trap_vectored() -> ! { + use core::arch::asm; unsafe { // Below are 32 (non-compressed) jumps to cover the entire possible // range of vectored traps. diff --git a/chips/rp2040/src/clocks.rs b/chips/rp2040/src/clocks.rs index 933247e8f6..65a2a64c40 100644 --- a/chips/rp2040/src/clocks.rs +++ b/chips/rp2040/src/clocks.rs @@ -1,4 +1,3 @@ -use core::arch::asm; use core::cell::Cell; use kernel::utilities::registers::interfaces::{ReadWriteable, Readable, Writeable}; use kernel::utilities::registers::{register_bitfields, register_structs, ReadOnly, ReadWrite}; @@ -1045,6 +1044,7 @@ impl Clocks { let _delay_cyc: u32 = self.get_frequency(Clock::System) / self.get_frequency(clock) + 1; #[cfg(target_arch = "arm")] unsafe { + use core::arch::asm; asm! ( "1:", "subs {0}, #1", diff --git a/chips/stm32f4xx/src/fsmc.rs b/chips/stm32f4xx/src/fsmc.rs index 7e426480d8..fa7839a3ec 100644 --- a/chips/stm32f4xx/src/fsmc.rs +++ b/chips/stm32f4xx/src/fsmc.rs @@ -1,5 +1,4 @@ use crate::rcc; -use core::arch::asm; use core::cell::Cell; use kernel::deferred_call::DeferredCall; use kernel::hil::bus8080::{Bus8080, BusWidth, Client}; @@ -264,6 +263,7 @@ impl<'a> Fsmc<'a> { self.bank[bank as usize].map(|bank| bank.reg.set(addr)); #[cfg(all(target_arch = "arm", target_os = "none"))] unsafe { + use core::arch::asm; asm!("dsb 0xf"); } } @@ -273,6 +273,7 @@ impl<'a> Fsmc<'a> { self.bank[bank as usize].map(|bank| bank.ram.set(data)); #[cfg(all(target_arch = "arm", target_os = "none"))] unsafe { + use core::arch::asm; asm!("dsb 0xf"); } } diff --git a/libraries/riscv-csr/src/csr.rs b/libraries/riscv-csr/src/csr.rs index 5de6f0727a..45cf695157 100644 --- a/libraries/riscv-csr/src/csr.rs +++ b/libraries/riscv-csr/src/csr.rs @@ -1,6 +1,5 @@ //! `ReadWriteRiscvCsr` type for RISC-V CSRs. -use core::arch::asm; use core::marker::PhantomData; use tock_registers::fields::Field; @@ -147,6 +146,7 @@ impl ReadWriteRiscvCsr { ))] #[inline] pub fn atomic_replace(&self, val_to_set: usize) -> usize { + use core::arch::asm; let r: usize; unsafe { asm!("csrrw {rd}, {csr}, {rs1}", @@ -183,6 +183,7 @@ impl ReadWriteRiscvCsr { ))] #[inline] pub fn read_and_set_bits(&self, bitmask: usize) -> usize { + use core::arch::asm; let r: usize; unsafe { asm!("csrrs {rd}, {csr}, {rs1}", @@ -219,6 +220,7 @@ impl ReadWriteRiscvCsr { ))] #[inline] pub fn read_and_clear_bits(&self, bitmask: usize) -> usize { + use core::arch::asm; let r: usize; unsafe { asm!("csrrc {rd}, {csr}, {rs1}", @@ -279,6 +281,7 @@ impl Readable for ReadWriteRiscvCsr usize { + use core::arch::asm; let r: usize; unsafe { asm!("csrr {rd}, {csr}", rd = out(reg) r, csr = const V); @@ -303,6 +306,7 @@ impl Writeable for ReadWriteRiscvCsr