From b54b187ba294e1c47f1dcc7dd8befaca74e6caf9 Mon Sep 17 00:00:00 2001 From: Khagan Khan Karimov Date: Fri, 26 Jul 2024 18:27:00 +0000 Subject: [PATCH] Add 'negn_r' instruction to lib/asm/x86-64 --- lib/asm/x86-64/X86_64Assembler.v3 | 14 ++++++++++++++ test/asm/x86-64/X86_64AssemblerTestGen.v3 | 13 ++++++++++++- 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/lib/asm/x86-64/X86_64Assembler.v3 b/lib/asm/x86-64/X86_64Assembler.v3 index 36333e020..f7e2a0dd7 100644 --- a/lib/asm/x86-64/X86_64Assembler.v3 +++ b/lib/asm/x86-64/X86_64Assembler.v3 @@ -1001,6 +1001,20 @@ class X86_64Assembler(w: DataWriter, OP_REX: byte) { def negq_m(a: X86_64Addr) -> this { emit_rex_b_m_x(a, REX_W, 0xF7, 3); } + def negb_r(a: X86_64Gpr) -> this { + emit_rex_b_r_x(a, NO_REX, 0xF6, 3); + } + def negw_r(a: X86_64Gpr) -> this { + emitb(PREFIX_W); + emit_rex_b_r_x(a, NO_REX, 0xF7, 3); + } + def negd_r(a: X86_64Gpr) -> this { + emit_rex_b_r_x(a, NO_REX, 0xF7, 3); + } + def negq_r(a: X86_64Gpr) -> this { + emit_rex_b_r_x(a, REX_W, 0xF7, 3); + } + def pushq_m(a: X86_64Addr) -> this { emit_rex_b_m_x(a, NO_REX, 0xFF, 6); } diff --git a/test/asm/x86-64/X86_64AssemblerTestGen.v3 b/test/asm/x86-64/X86_64AssemblerTestGen.v3 index 061f68381..17238e4d2 100644 --- a/test/asm/x86-64/X86_64AssemblerTestGen.v3 +++ b/test/asm/x86-64/X86_64AssemblerTestGen.v3 @@ -125,7 +125,7 @@ def main(a: Array) -> int { do_orn(); do_andn(); do_negn(); - + do_negn_r(); do_r_dq("xchg", do_r_r, asm.d.xchg_r_r, asm.q.xchg_r_r); do_m_dq("xchg", do_m_r, asm.d.xchg_m_r, asm.q.xchg_m_r); do_r_dq("xadd", do_r_r, asm.d.xadd_r_r, asm.q.xadd_r_r); @@ -406,6 +406,17 @@ def do_negn() { do_m("neg qword", asm.negq_m); } +def do_negn_r() { + regSize = 8; + do_r("and byte", asm.negb_r); + regSize = 16; + do_r("and word", asm.negw_r); + regSize = 32; + do_r("and dword", asm.negd_r); + regSize = 64; + do_r("and qword", asm.negq_r); + } + def do_set() { var buf = StringBuilder.new(); for (cond in X86_64Conds.all) {