From b94b03e985e165ef5808d5d73a3498ec36449ca8 Mon Sep 17 00:00:00 2001 From: "Ben L. Titzer" Date: Tue, 3 Sep 2024 12:07:33 -0400 Subject: [PATCH] [test] Use Unit testing framework in ArmAssemblerTest --- aeneas/test/ArmAssemblerTest.v3 | 161 ++++++++++++++++--------------- aeneas/test/PackingSolverTest.v3 | 2 +- 2 files changed, 84 insertions(+), 79 deletions(-) diff --git a/aeneas/test/ArmAssemblerTest.v3 b/aeneas/test/ArmAssemblerTest.v3 index 8c423df9d..f88961a02 100644 --- a/aeneas/test/ArmAssemblerTest.v3 +++ b/aeneas/test/ArmAssemblerTest.v3 @@ -1,23 +1,48 @@ -var TEST = UnitTest.new("ArmAssembler", test); - -def test() { - test_shifter(); - test_offset(); - test_pc(); - test_add(); - test_and(); - test_eor(); - test_orr(); - test_cmp(); - - test_ldr(); - test_str(); - - test_mov(); - test_mul(); - - test_3addr(); - test_cond(); +// Copyright 2024 Virgil authors. All rights reserved. +// See LICENSE for details of Apache 2.0 license. + +def T = UnitTests.registerT("arm:", _, ArmTester.new, _); +def X_ = [ + T("shifter", test_shifter), + T("offset", test_offset), + T("pc", test_pc), + T("add", test_add), + T("and", test_and), + T("eor", test_eor), + T("orr", test_orr), + T("cmp", test_cmp), + + T("ldr", test_ldr), + T("ldrsb", test_ldrsb), + T("ldrsh", test_ldrsh), + T("ldrh", test_ldrh), + T("str", test_str), + T("strh", test_strh), + + T("mov", test_mov), + T("mul", test_mul), + + T("3addr", test_3addr), + T("cond", test_cond), + () +]; + +def data = Array.new(128); +def w = DataWriter.new(); +def asm = ArmAssembler.new(w); + +def BIT25 = 1u << 25; + +class ArmTester(t: Tester) { + def check(expected: u32, v: void) { + asm.w.at(0); + var d = asm.w.data; + t.assert_eq(expected, + (u32.!(d[3]) << 24) | + (u32.!(d[2]) << 16) | + (u32.!(d[1]) << 8) | + (u32.!(d[0]) << 0)); + } } def R0 = ArmReg.R0; @@ -63,13 +88,8 @@ def ALL_REGS = [ ArmReg.R15 ]; -def data = Array.new(128); -def w = DataWriter.new(); -def asm = ArmAssembler.new(w); - -def BIT25 = 1u << 25; -def test_shifter() { - def T = test_shifter_output; +def test_shifter(t: ArmTester) { + def T = test_shifter_output(t.t, _, _); // Reg addressing mode for (r in ALL_REGS) T(r.tag, ArmOperand.Reg(r)); // Imm8 + ROR addressing mode @@ -103,18 +123,18 @@ def test_shifter() { // TODO: Reg rotate extended addresing mode } -def test_offset() { +def test_offset(t: ArmTester) { // TODO: check encoding of load/store offsets } -def test_shifter_output(expected: u32, op: ArmOperand) { +def test_shifter_output(t: Tester, expected: u32, op: ArmOperand) { var bits = asm.shifter(op); - TEST.eq(expected, bits); + t.assert_eq(expected, bits); } -def test_add() { +def test_add(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def ADD = asm.add; def OP = ArmOperand.Reg; @@ -178,9 +198,9 @@ def test_add() { T(0xE09FB001u, ADDS(FP, PC, OP(R1))); } -def test_and() { +def test_and(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def AND = asm.and; def OP = ArmOperand.Reg; @@ -240,9 +260,9 @@ def test_and() { T(0xE010B008u, ANDS(FP, R0, OP(R8))); } -def test_eor() { +def test_eor(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def EOR = asm.eor; def OP = ArmOperand.Reg; @@ -297,9 +317,9 @@ def test_eor() { T(0xE030B008u, EORS(FP, R0, OP(R8))); } -def test_orr() { +def test_orr(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def ORR = asm.orr; def OP = ArmOperand.Reg; @@ -354,9 +374,9 @@ def test_orr() { T(0xE190B008u, ORRS(FP, R0, OP(R8))); } -def test_3addr() { +def test_3addr(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def OP = ArmOperand.Reg; T(0xE0800000u, asm.add(R0, R0, OP(R0))); @@ -399,9 +419,9 @@ def test_3addr() { // TODO: shifted operands } -def test_cond() { +def test_cond(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def PR = ArmOperand.Reg; T(0x00800000u, asm.eq().add(R0, R0, PR(R0))); @@ -495,9 +515,9 @@ def test_cond() { T(0xE180F000u, asm.al().orr(PC, R0, PR(R0))); } -def test_cmp() { +def test_cmp(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def CMP = asm.cmp; def OP = ArmOperand.Reg; @@ -528,9 +548,9 @@ def test_cmp() { T(0xE1510000u, CMP(R1, OP(R0))); } -def test_cmn() { +def test_cmn(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def CMN = asm.cmn; def OP = ArmOperand.Reg; @@ -561,9 +581,9 @@ def test_cmn() { T(0xE1710000u, CMN(R1, OP(R0))); } -def test_ldr() { +def test_ldr(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def LDR = asm.ldrw; def LDRB = asm.ldrbzx; def LDRSB = asm.ldrbsx; @@ -747,14 +767,11 @@ def test_ldr() { T(0xE7189003u, LDR(R9, R8, NR(R3))); // TODO T(0xE71EE001u, LDR(RR, LR, NR(R1))); // TODO T(0xE71EE000u, LDR(RR, LR, NR(R0))); - test_ldrsb(); - test_ldrsh(); - test_ldrh(); } -def test_ldrsb() { +def test_ldrsb(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def LDRSB = asm.ldrbsx; def ZERO: ArmSmallOffset; def P = ArmSmallOffset.AddImm; @@ -856,9 +873,9 @@ def test_ldrsb() { T(0xE11BA0D6u, LDRSB(SL, FP, NR(R6))); } -def test_ldrsh() { +def test_ldrsh(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def LDRSH = asm.ldrhsx; def ZERO: ArmSmallOffset; def P = ArmSmallOffset.AddImm; @@ -947,9 +964,9 @@ def test_ldrsh() { T(0xE11BD0F6u, LDRSH(SP, FP, NR(R6))); } -def test_ldrh() { +def test_ldrh(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def LDRH = asm.ldrhzx; def ZERO: ArmSmallOffset; def P = ArmSmallOffset.AddImm; @@ -1038,9 +1055,9 @@ def test_ldrh() { T(0xE11BD0B6u, LDRH(SP, FP, NR(R6))); } -def test_str() { +def test_str(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def STRW = asm.strw; def STRB = asm.strb; def STRH = asm.strh; @@ -1200,13 +1217,11 @@ def test_str() { T(0xE7802003u, STRW(R2, R0, PR(R3))); T(0xE7881002u, STRW(R1, R8, PR(R2))); T(0xE7870001u, STRW(R0, R7, PR(R1))); - - test_strh(); } -def test_strh() { +def test_strh(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def STRH = asm.strh; def ZERO: ArmSmallOffset; def P = ArmSmallOffset.AddImm; @@ -1295,9 +1310,9 @@ def test_strh() { T(0xE10BD0B6u, STRH(SP, FP, NR(R6))); } -def test_mov() { +def test_mov(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def MOV = asm.mov; def MOVS = asm.movs; def R = ArmOperand.Reg; @@ -1454,9 +1469,9 @@ def test_mov() { T(0xE1A0DFE0u, MOV(SP, ROR(R0, 31))); } -def test_mul() { +def test_mul(t: ArmTester) { asm.w.at(0); - def T = check; + def T = t.check; def MUL = asm.mul; def MULS = asm.muls; def R = ArmOperand.Reg; @@ -1502,16 +1517,6 @@ def test_mul() { T(0xE0100B90u, MULS(R0, R0, FP)); } -def test_pc() { +def test_pc(t: ArmTester) { // TODO: test use of PC register. } - -def check(expected: u32, v: void) { - asm.w.at(0); - var d = asm.w.data; - TEST.eq(expected, - (u32.!(d[3]) << 24) | - (u32.!(d[2]) << 16) | - (u32.!(d[1]) << 8) | - (u32.!(d[0]) << 0)); -} diff --git a/aeneas/test/PackingSolverTest.v3 b/aeneas/test/PackingSolverTest.v3 index 9265b3458..d4d55754c 100644 --- a/aeneas/test/PackingSolverTest.v3 +++ b/aeneas/test/PackingSolverTest.v3 @@ -2,7 +2,7 @@ // See LICENSE for details of Apache 2.0 license. def T = UnitTests.registerT("packing:", _, PackingSolverTester.new, _); -def X = [ +def X_ = [ T("distinguishable", test_distinguishable), T("nonrefs", test_nonrefs), T("nonrefs_64", test_nonrefs_64),