diff --git a/hw/application_fpga/core/uart/README.md b/hw/application_fpga/core/uart/README.md
index f680e6f1..95c47ea4 100644
--- a/hw/application_fpga/core/uart/README.md
+++ b/hw/application_fpga/core/uart/README.md
@@ -15,26 +15,24 @@ have to wait for bytes and poll them as soon as they are received. The
 number of bytes in the FIFO is also exposed to the SW through the
 ADDR_RX_BYTES address.
 
-The number of data and data bits can be set by SW. The default is
-eight data bits and one stop bit.
+The number of data and stop bits can be configured prior to building
+the core.
 
-The default bit rate is based on target clock frequency divided by the
-bit rate times in order to hit the center of the bits. I.e.  Clock: 18
-MHz, 62500 bps Divisor = 18E6 / 62500 = 288
+The bit rate can also be configured prior to building the core. It
+should be based on the target clock frequency divided by the bit rate
+in order to hit the center of the bits. For example, a clock of 18 MHz
+and a target bit rate of 62500 bps yields:
+Divisor = 18E6 / 62500 = 288
 
 ## API
 
 ```
-  ADDR_BIT_RATE:  0x10
-  ADDR_DATA_BITS: 0x11
-  ADDR_STOP_BITS: 0x12
+ADDR_RX_STATUS: 0x20
+ADDR_RX_DATA:   0x21
+ADDR_RX_BYTES:  0x22
 
-  ADDR_RX_STATUS: 0x20
-  ADDR_RX_DATA:   0x21
-  ADDR_RX_BYTES:  0x22
-
-  ADDR_TX_STATUS: 0x40
-  ADDR_TX_DATA:   0x41
+ADDR_TX_STATUS: 0x40
+ADDR_TX_DATA:   0x41
 ```
 
 ## Implementation notes.
diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v
index d911b703..e4334bc3 100644
--- a/hw/application_fpga/core/uart/rtl/uart.v
+++ b/hw/application_fpga/core/uart/rtl/uart.v
@@ -69,10 +69,6 @@ module uart (
   //----------------------------------------------------------------
   // Internal constant and parameter definitions.
   //----------------------------------------------------------------
-  localparam ADDR_BIT_RATE = 8'h10;
-  localparam ADDR_DATA_BITS = 8'h11;
-  localparam ADDR_STOP_BITS = 8'h12;
-
   localparam ADDR_RX_STATUS = 8'h20;
   localparam ADDR_RX_DATA = 8'h21;
   localparam ADDR_RX_BYTES = 8'h22;
@@ -94,15 +90,6 @@ module uart (
   //----------------------------------------------------------------
   // Registers including update variables and write enable.
   //----------------------------------------------------------------
-  reg  [15 : 0] bit_rate_reg;
-  reg           bit_rate_we;
-
-  reg  [ 3 : 0] data_bits_reg;
-  reg           data_bits_we;
-
-  reg  [ 1 : 0] stop_bits_reg;
-  reg           stop_bits_we;
-
 
   //----------------------------------------------------------------
   // Wires.
@@ -139,9 +126,9 @@ module uart (
       .reset_n(reset_n),
 
       // Configuration parameters
-      .bit_rate (bit_rate_reg),
-      .data_bits(data_bits_reg),
-      .stop_bits(stop_bits_reg),
+      .bit_rate (DEFAULT_BIT_RATE),
+      .data_bits(DEFAULT_DATA_BITS),
+      .stop_bits(DEFAULT_STOP_BITS),
 
       // External data interface
       .rxd(rxd),
@@ -174,36 +161,6 @@ module uart (
       .out_ack (fifo_out_ack)
   );
 
-
-  //----------------------------------------------------------------
-  // reg_update
-  //
-  // Update functionality for all registers in the core.
-  // All registers are positive edge triggered with synchronous
-  // active low reset.
-  //----------------------------------------------------------------
-  always @(posedge clk) begin : reg_update
-    if (!reset_n) begin
-      bit_rate_reg  <= DEFAULT_BIT_RATE;
-      data_bits_reg <= DEFAULT_DATA_BITS;
-      stop_bits_reg <= DEFAULT_STOP_BITS;
-    end
-    else begin
-      if (bit_rate_we) begin
-        bit_rate_reg <= write_data[15 : 0];
-      end
-
-      if (data_bits_we) begin
-        data_bits_reg <= write_data[3 : 0];
-      end
-
-      if (stop_bits_we) begin
-        stop_bits_reg <= write_data[1 : 0];
-      end
-    end
-  end  // reg_update
-
-
   //----------------------------------------------------------------
   // api
   //
@@ -212,9 +169,6 @@ module uart (
   //----------------------------------------------------------------
   always @* begin : api
     // Default assignments.
-    bit_rate_we   = 1'h0;
-    data_bits_we  = 1'h0;
-    stop_bits_we  = 1'h0;
     core_txd_syn  = 1'h0;
     fifo_out_ack  = 1'h0;
     tmp_read_data = 32'h0;
@@ -227,18 +181,6 @@ module uart (
 
       if (we) begin
         case (address)
-          ADDR_BIT_RATE: begin
-            bit_rate_we = 1;
-          end
-
-          ADDR_DATA_BITS: begin
-            data_bits_we = 1;
-          end
-
-          ADDR_STOP_BITS: begin
-            stop_bits_we = 1;
-          end
-
           ADDR_TX_DATA: begin
             if (core_txd_ready) begin
               core_txd_syn = 1'h1;
@@ -252,18 +194,6 @@ module uart (
 
       else begin
         case (address)
-          ADDR_BIT_RATE: begin
-            tmp_read_data = {16'h0, bit_rate_reg};
-          end
-
-          ADDR_DATA_BITS: begin
-            tmp_read_data = {28'h0, data_bits_reg};
-          end
-
-          ADDR_STOP_BITS: begin
-            tmp_read_data = {30'h0, stop_bits_reg};
-          end
-
           ADDR_RX_STATUS: begin
             tmp_read_data = {31'h0, fifo_out_syn};
           end
diff --git a/hw/application_fpga/fw/tk1_mem.h b/hw/application_fpga/fw/tk1_mem.h
index 565d818c..246097b7 100644
--- a/hw/application_fpga/fw/tk1_mem.h
+++ b/hw/application_fpga/fw/tk1_mem.h
@@ -86,9 +86,6 @@
 #define TK1_MMIO_UDS_LAST 0xc200005c
 
 #define TK1_MMIO_UART_BASE 0xc3000000
-#define TK1_MMIO_UART_BIT_RATE 0xc3000040
-#define TK1_MMIO_UART_DATA_BITS 0xc3000044
-#define TK1_MMIO_UART_STOP_BITS 0xc3000048
 #define TK1_MMIO_UART_RX_STATUS 0xc3000080
 #define TK1_MMIO_UART_RX_DATA 0xc3000084
 #define TK1_MMIO_UART_RX_BYTES 0xc3000088