[DRAFT] LLEXT DRAM data #9721
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[DRAFT] LLEXT DRAM data #9721
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With this data can be assigned to a separate read-only section, which then will be kept in DRAM without copying it to SRAM on module instantiation. Signed-off-by: Guennadi Liakhovetski <[email protected]>
This adds a __cold_data macro, that can be used to designate read- only data to be kept in DRAM. Signed-off-by: Guennadi Liakhovetski <[email protected]>
src coefficients take a lot of space, keep them in DRAM to only copy used sets in SRAM. Signed-off-by: Guennadi Liakhovetski <[email protected]>
lgirdwood
reviewed
Dec 11, 2024
| @@ -76,6 +76,7 @@ def main(): | |||
| executable = [] | |||
| writable = [] | |||
| readonly = [] | |||
| readonly_dram = [] | |||
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I assume this will all be dumped when we build the target i.e. xkB hybrid RODATA in DRAM ?
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This is an illustration of how data can be assigned to be kept in DRAM. This specific change should be done by adjusting scripts, creating those headers, not by patching headers directly. Besides additional code is needed to copy selected coefficient sets to SRAM for fast access during operation