diff --git a/src/audio/base_fw.c b/src/audio/base_fw.c index a425e56e180d..ea495a433a0e 100644 --- a/src/audio/base_fw.c +++ b/src/audio/base_fw.c @@ -17,8 +17,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -57,6 +57,7 @@ static int basefw_config(uint32_t *data_offset, char *data) tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_MEMORY_RECLAIMED_FW_CFG, 1); +#ifndef CONFIG_SOF_ZEPHYR_NO_SOF_CLOCK tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_FAST_CLOCK_FREQ_HZ_FW_CFG, CLK_MAX_CPU_HZ); @@ -64,6 +65,7 @@ static int basefw_config(uint32_t *data_offset, char *data) tlv_value_uint32_set(tuple, IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG, clock_get_freq(CPU_LOWEST_FREQ_IDX)); +#endif tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_DL_MAILBOX_BYTES_FW_CFG, MAILBOX_HOSTBOX_SIZE); @@ -219,17 +221,21 @@ static int basefw_register_kcps(bool first_block, if (!(first_block && last_block)) return IPC4_ERROR_INVALID_PARAM; +#if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL /* value of kcps to request on core 0. Can be negative */ if (core_kcps_adjust(0, *(int32_t *)data)) return IPC4_ERROR_INVALID_PARAM; +#endif return IPC4_SUCCESS; } static int basefw_kcps_allocation_request(struct ipc4_resource_kcps *request) { +#if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL if (core_kcps_adjust(request->core_id, request->kcps)) return IPC4_ERROR_INVALID_PARAM; +#endif return IPC4_SUCCESS; } @@ -258,6 +264,7 @@ static int basefw_resource_allocation_request(bool first_block, static int basefw_power_state_info_get(uint32_t *data_offset, char *data) { +#if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL struct sof_tlv *tuple = (struct sof_tlv *)data; uint32_t core_kcps[CONFIG_CORE_COUNT] = {0}; int core_id; @@ -274,6 +281,9 @@ static int basefw_power_state_info_get(uint32_t *data_offset, char *data) tuple = tlv_next(tuple); *data_offset = (int)((char *)tuple - data); return IPC4_SUCCESS; +#else + return IPC4_UNAVAILABLE; +#endif } static int basefw_libraries_info_get(uint32_t *data_offset, char *data) diff --git a/src/audio/pipeline/pipeline-graph.c b/src/audio/pipeline/pipeline-graph.c index 7abc5ed8c461..f30731fa4874 100644 --- a/src/audio/pipeline/pipeline-graph.c +++ b/src/audio/pipeline/pipeline-graph.c @@ -282,7 +282,7 @@ int pipeline_complete(struct pipeline *p, struct comp_dev *source, .comp_data = &data, }; -#if !UNIT_TEST && !CONFIG_LIBRARY +#if !UNIT_TEST && !CONFIG_LIBRARY && CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL int __maybe_unused freq = clock_get_freq(cpu_get_id()); #else int __maybe_unused freq = 0; diff --git a/src/audio/pipeline/pipeline-stream.c b/src/audio/pipeline/pipeline-stream.c index d4afe98b8f49..8f0d70e90b66 100644 --- a/src/audio/pipeline/pipeline-stream.c +++ b/src/audio/pipeline/pipeline-stream.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/src/library_manager/lib_manager.c b/src/library_manager/lib_manager.c index 39885b4ed89c..350625cae70e 100644 --- a/src/library_manager/lib_manager.c +++ b/src/library_manager/lib_manager.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -962,6 +963,7 @@ static int lib_manager_setup(uint32_t dma_id) dma_block_cfg.dest_address = dma_ext->dma_addr; +#if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL /* * make sure that the DSP is running full speed for the duration of * library loading @@ -969,6 +971,7 @@ static int lib_manager_setup(uint32_t dma_id) ret = core_kcps_adjust(cpu_get_id(), CLK_MAX_CPU_HZ / 1000); if (ret < 0) goto err_dma_buffer; +#endif ret = dma_config(dma_ext->chan->dma->z_dev, dma_ext->chan->index, &config); if (ret < 0) @@ -983,7 +986,9 @@ static int lib_manager_setup(uint32_t dma_id) return 0; err_dma: +#if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL core_kcps_adjust(cpu_get_id(), -(CLK_MAX_CPU_HZ / 1000)); +#endif err_dma_buffer: lib_manager_dma_deinit(dma_ext, dma_id); @@ -1061,7 +1066,9 @@ int lib_manager_load_library(uint32_t dma_id, uint32_t lib_id, uint32_t type) rfree((__sparse_force void *)man_tmp_buffer); cleanup: +#if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL core_kcps_adjust(cpu_get_id(), -(CLK_MAX_CPU_HZ / 1000)); +#endif rfree((void *)dma_ext->dma_addr); lib_manager_dma_deinit(dma_ext, dma_id); rfree(dma_ext); diff --git a/src/platform/Kconfig b/src/platform/Kconfig index ce972d1d9fc8..c558d371806e 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -340,6 +340,7 @@ config CAVS default n select INTEL select INTEL_MN + select SOF_ZEPHYR_NO_SOF_CLOCK config CAVS_VERSION_2_5 depends on CAVS diff --git a/src/platform/intel/ace/platform.c b/src/platform/intel/ace/platform.c index 88ccd2c2ac61..50453bb637b4 100644 --- a/src/platform/intel/ace/platform.c +++ b/src/platform/intel/ace/platform.c @@ -90,15 +90,14 @@ int platform_init(struct sof *sof) trace_point(TRACE_BOOT_PLATFORM_CLOCK); platform_clock_init(sof); - kcps_budget_init(); #if CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL + kcps_budget_init(); + ret = core_kcps_adjust(cpu_get_id(), PRIMARY_CORE_BASE_CPS_USAGE); -#else - ret = core_kcps_adjust(cpu_get_id(), CLK_MAX_CPU_HZ / 1000); -#endif if (ret < 0) return ret; +#endif trace_point(TRACE_BOOT_PLATFORM_SCHED); scheduler_init_edf(); diff --git a/src/platform/intel/cavs/include/cavs/lib/clk.h b/src/platform/intel/cavs/include/cavs/lib/clk.h deleted file mode 100644 index eec51ac3963e..000000000000 --- a/src/platform/intel/cavs/include/cavs/lib/clk.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -/** - * \file cavs/lib/clk.h - * \brief Clk parameters for run-time clock data, common for cAVS platforms. - */ - -#ifdef __PLATFORM_LIB_CLK_H__ - -#ifndef __CAVS_LIB_CLK_H__ -#define __CAVS_LIB_CLK_H__ - -#include -#include -#include -#include -#include - -struct sof; - -/** \brief Core(s) settings, up to CONFIG_CORE_COUNT */ -#define CLK_CPU(x) (x) - -/** \brief SSP clock r-t settings are after the core(s) settings */ -#define CLK_SSP CONFIG_CORE_COUNT - -/* SSP clock run-time data is the last one, so total number is ssp idx +1 */ - -/** \brief Total number of clocks */ -#define NUM_CLOCKS (CLK_SSP + 1) - -extern const struct freq_table *cpu_freq; -extern const uint32_t cpu_freq_enc[]; -extern const uint32_t cpu_freq_status_mask[]; - -void platform_clock_init(struct sof *sof); - -void platform_clock_on_waiti(void); -void platform_clock_on_wakeup(void); - -#endif /* __CAVS_LIB_CLK_H__ */ - -#else - -#error "This file shouldn't be included from outside of platform/lib/clk.h" - -#endif /* __PLATFORM_LIB_CLK_H__ */ diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c index fde0f22f0a22..366424bae1dd 100644 --- a/src/platform/intel/cavs/platform.c +++ b/src/platform/intel/cavs/platform.c @@ -116,14 +116,12 @@ int platform_init(struct sof *sof) { int ret; - trace_point(TRACE_BOOT_PLATFORM_CLOCK); - platform_clock_init(sof); - trace_point(TRACE_BOOT_PLATFORM_SCHED); scheduler_init_edf(); /* init low latency timer domain and scheduler */ - sof->platform_timer_domain = timer_domain_init(sof->platform_timer, PLATFORM_DEFAULT_CLOCK); + /* clk is ignored on Zephyr so pass 0 */ + sof->platform_timer_domain = timer_domain_init(sof->platform_timer, 0); scheduler_init_ll(sof->platform_timer_domain); /* init the system agent */ diff --git a/src/platform/tigerlake/include/platform/lib/clk.h b/src/platform/tigerlake/include/platform/lib/clk.h deleted file mode 100644 index ff44f00d544d..000000000000 --- a/src/platform/tigerlake/include/platform/lib/clk.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2017 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -#ifdef __SOF_LIB_CLK_H__ - -#ifndef __PLATFORM_LIB_CLK_H__ -#define __PLATFORM_LIB_CLK_H__ - -#include - -#define CLK_MAX_CPU_HZ 400000000 - -#define CPU_WOVCRO_FREQ_IDX 0 - -#define CPU_LPRO_FREQ_IDX 1 - -#define CPU_HPRO_FREQ_IDX 2 - -#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX - -#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX - -#define SSP_DEFAULT_IDX 1 - -#define NUM_CPU_FREQ 3 - -#define NUM_SSP_FREQ 3 - -#endif /* __PLATFORM_LIB_CLK_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/clk.h" - -#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/tigerlake/include/platform/platform.h b/src/platform/tigerlake/include/platform/platform.h index 74e0cd187aab..46bd196ebf44 100644 --- a/src/platform/tigerlake/include/platform/platform.h +++ b/src/platform/tigerlake/include/platform/platform.h @@ -19,18 +19,11 @@ #include #include +#include + struct ll_schedule_domain; struct timer; -/*! \def PLATFORM_DEFAULT_CLOCK - * \brief clock source for audio pipeline - * - * There are two types of clock: cpu clock which is a internal clock in - * xtensa core, and ssp clock which is provided by external HW IP. - * The choice depends on HW features on different platform - */ -#define PLATFORM_DEFAULT_CLOCK CLK_SSP - /* Host page size */ #define HOST_PAGE_SIZE 4096 diff --git a/src/platform/tigerlake/lib/clk.c b/src/platform/tigerlake/lib/clk.c deleted file mode 100644 index 581e9ba3eb40..000000000000 --- a/src/platform/tigerlake/lib/clk.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -// -// Copyright(c) 2019 Intel Corporation. All rights reserved. -// -// Author: Tomasz Lauda -// Janusz Jankowski - -#include -#include -#include - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request WOVCRO Clock */ -#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 -#define SHIM_CLKCTL_WOVCROSC BIT(3) - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV2 0 -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 -#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief WOVCRO Clock Status */ -#define SHIM_CLKSTS_WOV_CRO BIT(4) - -/** \brief XTAL Oscillator Clock Status */ -#define SHIM_CLKSTS_XOSCCS BIT(30) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -static const struct freq_table platform_cpu_freq[] = { - { 38400000, 38400 }, - { 120000000, 120000 }, - { CLK_MAX_CPU_HZ, 400000 }, -}; - -const uint32_t cpu_freq_enc[] = { - SHIM_CLKCTL_WOVCROSC | SHIM_CLKCTL_WOV_CRO_REQUEST | - SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, - SHIM_CLKCTL_RLROSCC | SHIM_CLKCTL_OCS_LP_RING | - SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, - SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_OCS_HP_RING | - SHIM_CLKCTL_HMCS_DIV2 | SHIM_CLKCTL_LMCS_DIV4, -}; - -const uint32_t cpu_freq_status_mask[] = { - SHIM_CLKSTS_WOV_CRO, - SHIM_CLKSTS_LROSCCS, - SHIM_CLKSTS_HROSCCS -}; - -STATIC_ASSERT(NUM_CPU_FREQ == ARRAY_SIZE(platform_cpu_freq), - invalid_number_of_cpu_frequencies); - -const struct freq_table *cpu_freq = platform_cpu_freq; - -/* IMPORTANT: array should be filled in increasing order - * (regarding to .freq field) - */ -static const struct freq_table platform_ssp_freq[] = { - { 24576000, 24576 }, - { 38400000, 38400 }, - { 96000000, 96000 }, -}; - -static const uint32_t platform_ssp_freq_sources[] = { - SSP_CLOCK_AUDIO_CARDINAL, - SSP_CLOCK_XTAL_OSCILLATOR, - SSP_CLOCK_PLL_FIXED, -}; - -STATIC_ASSERT(NUM_SSP_FREQ == ARRAY_SIZE(platform_ssp_freq), - invalid_number_of_ssp_frequencies); - -const struct freq_table *ssp_freq = platform_ssp_freq; -const uint32_t *ssp_freq_sources = platform_ssp_freq_sources; diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index c583a837203d..2575067bb5aa 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -222,8 +222,6 @@ if (CONFIG_SOC_SERIES_INTEL_CAVS_V25) # Platform sources zephyr_library_sources( ${SOF_PLATFORM_PATH}/intel/cavs/platform.c - ${SOF_PLATFORM_PATH}/tigerlake/lib/clk.c - lib/clk.c lib/dma.c ) @@ -490,9 +488,7 @@ zephyr_library_sources( ${SOF_MATH_PATH}/exp_fcn_hifi.c # SOF library - parts to transition to Zephyr over time - ${SOF_LIB_PATH}/clk.c ${SOF_LIB_PATH}/notifier.c - ${SOF_LIB_PATH}/cpu-clk-manager.c ${SOF_LIB_PATH}/dma.c ${SOF_LIB_PATH}/dai.c @@ -530,6 +526,14 @@ zephyr_library_sources( lib.c ) +if(NOT CONFIG_SOF_ZEPHYR_NO_SOF_CLOCK) + zephyr_library_sources(${SOF_LIB_PATH}/clk.c) +endif() + +zephyr_library_sources_ifdef(CONFIG_KCPS_DYNAMIC_CLOCK_CONTROL + ${SOF_LIB_PATH}/cpu-clk-manager.c +) + # Optional math utility zephyr_library_sources_ifdef(CONFIG_MATH_LUT_SINE_FIXED ${SOF_MATH_PATH}/lut_trig.c diff --git a/zephyr/Kconfig b/zephyr/Kconfig index b348fd7b9728..535cb6bc59ea 100644 --- a/zephyr/Kconfig +++ b/zephyr/Kconfig @@ -76,4 +76,10 @@ config SOF_BOOT_TEST initialized. After that SOF will continue running and be usable as usual. +config SOF_ZEPHYR_NO_SOF_CLOCK + bool + help + Do not use SOF clk.h interface to set the DSP clock frequency. + Requires implementation of platform/lib/clk.h. + endif diff --git a/zephyr/include/rtos/clk.h b/zephyr/include/rtos/clk.h index b0fefc748334..6db452bdab88 100644 --- a/zephyr/include/rtos/clk.h +++ b/zephyr/include/rtos/clk.h @@ -6,9 +6,10 @@ #ifndef __ZEPHYR_RTOS_CLK_H__ #define __ZEPHYR_RTOS_CLK_H__ +#ifndef CONFIG_SOF_ZEPHYR_NO_SOF_CLOCK + #include -/* TODO remove once drivers upstream */ #define __SOF_LIB_CLK_H__ #include @@ -77,4 +78,6 @@ static inline struct clock_info *clocks_get(void) return sof_get()->clocks; } +#endif /* CONFIG_SOF_ZEPHYR_NO_SOF_CLOCK */ + #endif /* __ZEPHYR_RTOS_CLK_H__ */ diff --git a/zephyr/include/rtos/timer.h b/zephyr/include/rtos/timer.h index a7829a209372..412ceeda0038 100644 --- a/zephyr/include/rtos/timer.h +++ b/zephyr/include/rtos/timer.h @@ -23,6 +23,11 @@ static inline uint64_t sof_cycle_get_64(void) return k_ticks_to_cyc_floor64(k_uptime_ticks()); } +static inline uint64_t sys_cycle_get_64_rate(void) +{ + return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; +} + #define sof_cycle_get_64_safe() sof_cycle_get_64() #define sof_cycle_get_64_atomic() sof_cycle_get_64() #define platform_timer_stop(x) diff --git a/zephyr/wrapper.c b/zephyr/wrapper.c index f79edc6bbcdb..bff29e70cd2a 100644 --- a/zephyr/wrapper.c +++ b/zephyr/wrapper.c @@ -237,7 +237,7 @@ void platform_dai_timestamp(struct comp_dev *dai, /* get SSP wallclock - DAI sets this to stream start value */ posn->wallclock = sof_cycle_get_64() - posn->wallclock; - posn->wallclock_hz = clock_get_freq(PLATFORM_DEFAULT_CLOCK); + posn->wallclock_hz = sys_cycle_get_64_rate(); posn->flags |= SOF_TIME_WALL_VALID; }