diff --git a/app/boards/imx95_evk_mimx9596_m7_ddr.conf b/app/boards/imx95_evk_mimx9596_m7_ddr.conf new file mode 100644 index 000000000000..e3a0c5659c7d --- /dev/null +++ b/app/boards/imx95_evk_mimx9596_m7_ddr.conf @@ -0,0 +1,11 @@ +CONFIG_DYNAMIC_INTERRUPTS=y +CONFIG_TRACE=n +CONFIG_ZEPHYR_NATIVE_DRIVERS=y +CONFIG_IMX95=y + +CONFIG_SAI_HAS_MCLK_CONFIG_OPTION=y + +CONFIG_DMA=y +CONFIG_DMA_NXP_EDMA_ENABLE_HALFMAJOR_IRQ=y + +CONFIG_SHARED_INTERRUPTS=y diff --git a/app/boards/imx95_evk_mimx9596_m7_ddr.overlay b/app/boards/imx95_evk_mimx9596_m7_ddr.overlay new file mode 100644 index 000000000000..34882b5d59fd --- /dev/null +++ b/app/boards/imx95_evk_mimx9596_m7_ddr.overlay @@ -0,0 +1,25 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + host_dma: dma { + compatible = "nxp,sof-host-dma"; + dma-channels = <32>; + #dma-cells = <0>; + }; +}; + +&sai3 { + tx-fifo-watermark = <8>; + rx-fifo-watermark = <96>; + fifo-depth = <96>; + rx-sync-mode = <1>; + status = "okay"; +}; + +&edma2 { + status = "okay"; +}; diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index c4d360e65609..b7640ea8ce58 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -164,6 +164,10 @@ class PlatformConfig: "hifi4_nxp2_s7_v2_1a_prod", RIMAGE_KEY = "key param ignored by imx8ulp" ), + "imx95" : PlatformConfig( + "imx", "imx95_evk/mimx9596/m7/ddr", + "", "", "", "" + ), } platform_configs = platform_configs_all.copy() @@ -1160,7 +1164,7 @@ def gzip_compress(fname, gzdst=None): # Don't run sof_ri_info and ignore silently .ri files that don't have one. RI_INFO_UNSUPPORTED = [] -RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8ulp'] +RI_INFO_UNSUPPORTED += ['imx8', 'imx8x', 'imx8m', 'imx8ulp', 'imx95'] RI_INFO_UNSUPPORTED += ['rn'] RI_INFO_UNSUPPORTED += ['mt8186', 'mt8195'] diff --git a/src/include/sof/drivers/mu.h b/src/include/sof/drivers/mu.h index a8b2715c05d4..9707dd32fb5c 100644 --- a/src/include/sof/drivers/mu.h +++ b/src/include/sof/drivers/mu.h @@ -19,7 +19,7 @@ enum imx_mu_type { IMX_MU_V2, }; -#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55) +#if defined(CONFIG_IMX8ULP) || defined(CONFIG_IMX93_A55) || defined(CONFIG_IMX95) #define IMX_MU_VERSION IMX_MU_V2 #else #define IMX_MU_VERSION IMX_MU_V1 diff --git a/src/platform/Kconfig b/src/platform/Kconfig index 0ceedd772da4..68633616a7d8 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -157,6 +157,15 @@ config IMX93_A55 help Select if your target platform is imx93-compatible. +config IMX95 + bool "Build for NXP i.MX95" + select ZEPHYR_LOG + select BUILD_OUTPUT_BIN + select HOST_PTABLE + select IMX + help + Select if your target platform is imx95-compatible. + config RENOIR bool "Build for Renoir" select XT_INTERRUPT_LEVEL_5 diff --git a/src/platform/imx95/include/platform/lib/clk.h b/src/platform/imx95/include/platform/lib/clk.h new file mode 100644 index 000000000000..ad8b193fab1d --- /dev/null +++ b/src/platform/imx95/include/platform/lib/clk.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#define CLK_MAX_CPU_HZ 800000000 +#define CPU_DEFAULT_IDX 0 +#define NUM_CPU_FREQ 1 +#define NUM_CLOCKS 1 + +struct sof; + +void platform_clock_init(struct sof *sof); + +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/imx95/include/platform/lib/cpu.h b/src/platform/imx95/include/platform/lib/cpu.h new file mode 100644 index 000000000000..54fd25cf4b37 --- /dev/null +++ b/src/platform/imx95/include/platform/lib/cpu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_LIB_CPU_H__ + +#ifndef __PLATFORM_LIB_CPU_H__ +#define __PLATFORM_LIB_CPU_H__ + +#define PLATFORM_PRIMARY_CORE_ID 0 + +#endif /* __PLATFORM_LIB_CPU_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/cpu.h" + +#endif /* __SOF_LIB_CPU_H__ */ diff --git a/src/platform/imx95/include/platform/lib/dai.h b/src/platform/imx95/include/platform/lib/dai.h new file mode 100644 index 000000000000..4a64614f6092 --- /dev/null +++ b/src/platform/imx95/include/platform/lib/dai.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_LIB_DAI_H__ + +#ifndef __PLATFORM_LIB_DAI_H__ +#define __PLATFORM_LIB_DAI_H__ + +/* TODO: remove me whenever possible */ + +#endif /* __PLATFORM_LIB_DAI_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dai.h" + +#endif /* __SOF_LIB_DAI_H__ */ diff --git a/src/platform/imx95/include/platform/lib/dma.h b/src/platform/imx95/include/platform/lib/dma.h new file mode 100644 index 000000000000..5f1c725f693d --- /dev/null +++ b/src/platform/imx95/include/platform/lib/dma.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_LIB_DMA_H__ + +#ifndef __PLATFORM_LIB_DMA_H__ +#define __PLATFORM_LIB_DMA_H__ + +/* TODO: remove me whenever possible */ + +#endif /* __PLATFORM_LIB_DMA_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/dma.h" + +#endif /* __SOF_LIB_DMA_H__ */ diff --git a/src/platform/imx95/include/platform/lib/mailbox.h b/src/platform/imx95/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..ffdb39b34398 --- /dev/null +++ b/src/platform/imx95/include/platform/lib/mailbox.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +/* i.MX95's mailbox is organized as follows: + * + * +---------------+-------------------------+ + * | Region name | Base address | Size | + * +---------------+---------------+---------+ + * | Inbox region | 0x8fffd000 | 0x1000 | + * +---------------+---------------+---------+ + * | Outbox region | 0x8fffe000 | 0x1000 | + * +---------------+---------------+---------+ + * | Stream region | 0x8ffff000 | 0x1000 | + * +---------------+---------------+---------+ + * + * IMPORTANT: all regions should be 32-byte aligned. + * This is required because cache maintenance might + * be performed on them. + */ + +/* inbox */ +#define MAILBOX_HOSTBOX_SIZE 0x1000 +#define MAILBOX_HOSTBOX_BASE 0x86000000 +#define MAILBOX_HOSTBOX_OFFSET 0 + +/* outbox */ +#define MAILBOX_DSPBOX_SIZE 0x1000 +#define MAILBOX_DSPBOX_BASE 0x86001000 +#define MAILBOX_DSPBOX_OFFSET (MAILBOX_HOSTBOX_OFFSET + MAILBOX_HOSTBOX_SIZE) + +/* stream */ +#define MAILBOX_STREAM_SIZE 0x1000 +#define MAILBOX_STREAM_BASE 0x86002000 +#define MAILBOX_STREAM_OFFSET (MAILBOX_DSPBOX_OFFSET + MAILBOX_DSPBOX_SIZE) + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/imx95/include/platform/lib/memory.h b/src/platform/imx95/include/platform/lib/memory.h new file mode 100644 index 000000000000..bf3ff05a5c69 --- /dev/null +++ b/src/platform/imx95/include/platform/lib/memory.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +#include + +#define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE + +#define SHARED_DATA + +#define uncache_to_cache(address) address +#define cache_to_uncache(address) address +#define cache_to_uncache_init(address) address +#define is_uncached(address) 0 + +/* no address translation required */ +#define host_to_local(addr) (addr) +#define local_to_host(addr) (addr) + +#define HEAPMEM_SIZE 0x00010000 + +/* WAKEUP domain MU7 side B */ +#define MU_BASE 0x42440000UL + +static inline void *platform_shared_get(void *ptr, int bytes) +{ + return ptr; +} + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__*/ diff --git a/src/platform/imx95/include/platform/platform.h b/src/platform/imx95/include/platform/platform.h new file mode 100644 index 000000000000..c676dfc742cb --- /dev/null +++ b/src/platform/imx95/include/platform/platform.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +/* refers to M7 core clock - one core, one clock */ +#define PLATFORM_DEFAULT_CLOCK 0 + +#define HOST_PAGE_SIZE 4096 + +#define PLATFORM_PAGE_TABLE_SIZE 256 + +/* TODO: generous (SOF is usually used with 2 channels at most on i.MX + * platforms) and (potentially) not true. Can be adjusted later on if + * need be. + */ +#define PLATFORM_MAX_CHANNELS 4 +/* TODO: same as PLATFORM_MAX_CHANNELS */ +#define PLATFORM_MAX_STREAMS 5 + +/* WAKEUP domain MU7 side B */ +#define PLATFORM_IPC_INTERRUPT 207 + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/imx95/include/platform/trace/trace.h b/src/platform/imx95/include/platform/trace/trace.h new file mode 100644 index 000000000000..a1702e324436 --- /dev/null +++ b/src/platform/imx95/include/platform/trace/trace.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2024 NXP + */ + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +/* TODO: remove me whenever possible */ + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/imx95/lib/clk.c b/src/platform/imx95/lib/clk.c new file mode 100644 index 000000000000..8f9e2763057d --- /dev/null +++ b/src/platform/imx95/lib/clk.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + */ + +#include +#include + +static const struct freq_table platform_cpu_freq[] = { + { + .freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, + .ticks_per_msec = CONFIG_SYS_CLOCK_TICKS_PER_SEC * 1000, + }, +}; + +static struct clock_info platform_clocks_info[NUM_CLOCKS]; + +void platform_clock_init(struct sof *sof) +{ + int i; + + sof->clocks = platform_clocks_info; + + for (i = 0; i < CONFIG_CORE_COUNT; i++) { + sof->clocks[i] = (struct clock_info) { + .freqs_num = NUM_CPU_FREQ, + .freqs = platform_cpu_freq, + .default_freq_idx = CPU_DEFAULT_IDX, + .current_freq_idx = CPU_DEFAULT_IDX, + .notification_id = NOTIFIER_ID_CPU_FREQ, + .notification_mask = NOTIFIER_TARGET_CORE_MASK(i), + .set_freq = NULL, + }; + } +} diff --git a/src/platform/imx95/linker/data-sections.ld b/src/platform/imx95/linker/data-sections.ld new file mode 100644 index 000000000000..cc4c0872545b --- /dev/null +++ b/src/platform/imx95/linker/data-sections.ld @@ -0,0 +1,5 @@ +SECTION_PROLOGUE(.fw_metadata,,) +{ + KEEP (*(*.fw_metadata)) + . = ALIGN(16); +} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) diff --git a/src/platform/imx95/platform.c b/src/platform/imx95/platform.c new file mode 100644 index 000000000000..f46500907c91 --- /dev/null +++ b/src/platform/imx95/platform.c @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const struct sof_ipc_fw_ready ready = { + .hdr = { + .cmd = SOF_IPC_FW_READY, + .size = sizeof(struct sof_ipc_fw_ready), + }, + .version = { + .hdr.size = sizeof(struct sof_ipc_fw_version), + .micro = SOF_MICRO, + .minor = SOF_MINOR, + .major = SOF_MAJOR, + .build = -1, + .date = "dtermin.\0", + .time = "fwready.\0", + .tag = SOF_TAG, + .abi_version = SOF_ABI_VERSION, + .src_hash = SOF_SRC_HASH, + }, + .flags = DEBUG_SET_FW_READY_FLAGS, +}; + +const struct ext_man_windows windows + __aligned(EXT_MAN_ALIGN) __section(".fw_metadata") __unused = { + .hdr = { + .type = EXT_MAN_ELEM_WINDOW, + .elem_size = ALIGN_UP_COMPILE(sizeof(struct ext_man_windows), EXT_MAN_ALIGN), + }, + .window = { + .ext_hdr = { + .hdr.cmd = SOF_IPC_FW_READY, + .hdr.size = sizeof(struct sof_ipc_window), + .type = SOF_IPC_EXT_WINDOW, + }, + .num_windows = 3, + .window = { + { + .type = SOF_IPC_REGION_DOWNBOX, + .size = MAILBOX_HOSTBOX_SIZE, + .offset = MAILBOX_HOSTBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_UPBOX, + .size = MAILBOX_DSPBOX_SIZE, + .offset = MAILBOX_DSPBOX_OFFSET, + }, + { + .type = SOF_IPC_REGION_STREAM, + .size = MAILBOX_STREAM_SIZE, + .offset = MAILBOX_STREAM_OFFSET, + }, + }, + }, +}; + +int platform_boot_complete(uint32_t boot_message) +{ + mailbox_dspbox_write(0, &ready, sizeof(ready)); + + imx_mu_xcr_rmw(IMX_MU_VERSION, IMX_MU_GCR, + IMX_MU_xCR_GIRn(IMX_MU_VERSION, 1), 0); + + return 0; +} + +int platform_context_save(struct sof *sof) +{ + /* nothing to be done here */ + return 0; +} + +int platform_init(struct sof *sof) +{ + int ret; + + platform_clock_init(sof); + + scheduler_init_edf(); + + sof->platform_timer_domain = zephyr_domain_init(PLATFORM_DEFAULT_CLOCK); + zephyr_ll_scheduler_init(sof->platform_timer_domain); + + ret = dmac_init(sof); + if (ret < 0) + return ret; + + ipc_init(sof); + + dai_init(sof); + + return 0; +} diff --git a/tools/rimage/config/imx95.toml b/tools/rimage/config/imx95.toml new file mode 100644 index 000000000000..69e6811be3bc --- /dev/null +++ b/tools/rimage/config/imx95.toml @@ -0,0 +1,9 @@ +version = [1, 0] + +[adsp] +name = "imx95" + +[[adsp.mem_zone]] +type = "DRAM" +base = "0x80000000" +size = "0x100000" diff --git a/tools/topology/topology1/CMakeLists.txt b/tools/topology/topology1/CMakeLists.txt index 2f120fa593a2..b7bf189c284c 100644 --- a/tools/topology/topology1/CMakeLists.txt +++ b/tools/topology/topology1/CMakeLists.txt @@ -70,6 +70,11 @@ set(TPLGS "sof-imx93-wm8962\;sof-imx93-wm8962\;-DPPROC=volume" ## end i.MX93 topologies + ## i.MX95 topologies + "sof-imx95-wm8962\;sof-imx95-wm8962\;-DPPROC=volume" + "sof-imx95-wm8962\;sof-imx95-passthrough-wm8962\;-DPPROC=passthrough" + ## end i.MX95 topologies + "sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-rt1019-rt5682" "sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-rt1019-rt5682-dts\;-DDTS=`DTS'" "sof-mt8195-mt6359-rt1019-rt5682\;sof-mt8195-mt6359-max98390-rt5682" diff --git a/tools/topology/topology1/sof-imx95-wm8962.m4 b/tools/topology/topology1/sof-imx95-wm8962.m4 new file mode 100644 index 000000000000..c920c6e9c99e --- /dev/null +++ b/tools/topology/topology1/sof-imx95-wm8962.m4 @@ -0,0 +1,82 @@ +# +# Topology for i.MX95 with WM8962 codec +# + +# Include topology builder +include(`utils.m4') +include(`dai.m4') +include(`pipeline.m4') +include(`sai.m4') +include(`pcm.m4') +include(`buffer.m4') + +# Include TLV library +include(`common/tlv.m4') + +# Include Token library +include(`sof/tokens.m4') + +# Include DSP configuration +include(`platform/imx/imx8.m4') + +# +# Define the pipelines +# +# PCM0 <----> PPROC <-----> SAI3 +# + +dnl PIPELINE_PCM_ADD(pipeline, +dnl pipe id, pcm, max channels, format, +dnl period, priority, core, +dnl pcm_min_rate, pcm_max_rate, pipeline_rate, +dnl time_domain, sched_comp) + +# Low Latency playback pipeline 1 on PCM 0 using max 2 channels of s32le. +# Set 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-`PPROC'-playback.m4, + 1, 0, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) + +# Low Latency capture pipeline 2 on PCM 0 using max 2 channels of s32le. +# Set 1000us deadline with priority 0 on core 0 +PIPELINE_PCM_ADD(sof/pipe-`PPROC'-capture.m4, + 2, 0, 2, s32le, + 1000, 0, 0, + 48000, 48000, 48000) +# +# DAIs configuration +# + +dnl DAI_ADD(pipeline, +dnl pipe id, dai type, dai_index, dai_be, +dnl buffer, periods, format, +dnl period, priority, core, time_domain) + +# playback DAI is SAI_SAI_INDEX using 2 periods +# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-playback.m4, + 1, SAI, 3, sai3-wm8962, + PIPELINE_SOURCE_1, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + +# capture DAI is SAI_SAI_INDEX using 2 periods +# Buffers use s32le format, with 48 frame per 1000us on core 0 with priority 0 +DAI_ADD(sof/pipe-dai-capture.m4, + 2, SAI, 3, sai3-wm8962, + PIPELINE_SINK_2, 2, s32le, + 1000, 0, 0, SCHEDULE_TIME_DOMAIN_TIMER) + + +# PCM Low Latency, id 0 + +dnl PCM_DUPLEX_ADD(name, pcm_id, playback, capture) +PCM_DUPLEX_ADD(Port0, 0, PIPELINE_PCM_1, PIPELINE_PCM_2) + +dnl DAI_CONFIG(type, idx, link_id, name, sai_config) +DAI_CONFIG(SAI, 3, 0, sai3-wm8962, + SAI_CONFIG(I2S, SAI_CLOCK(mclk, 12288000, codec_mclk_in), + SAI_CLOCK(bclk, 3072000, codec_provider), + SAI_CLOCK(fsync, 48000, codec_provider), + SAI_TDM(2, 32, 3, 3), + SAI_CONFIG_DATA(SAI, 3, 0))) diff --git a/west.yml b/west.yml index 91657cff8c0a..7f36f02881bb 100644 --- a/west.yml +++ b/west.yml @@ -59,6 +59,7 @@ manifest: - mipi-sys-t - lz4 - tinycrypt + - cmsis self: # Changes to submanifests/*.yml files _are_ effective; these have no diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index 36c6126f4dd0..90bdf710dad3 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -391,6 +391,28 @@ if (CONFIG_SOC_MIMX9352_A55) set(PLATFORM "imx93_a55") endif() +if (CONFIG_SOC_MIMX9596_M7) + + zephyr_library_sources( + ${SOF_PLATFORM_PATH}/imx95/platform.c + ${SOF_PLATFORM_PATH}/imx95/lib/clk.c + lib/dma.c + ) + + zephyr_library_sources( + ${SOF_DRIVERS_PATH}/imx/ipc.c + ) + + zephyr_library_sources( + ${SOF_SRC_PATH}/schedule/zephyr_ll.c + ) + + # SOF-specific linker script additions + zephyr_linker_sources(DATA_SECTIONS ${sof_top_dir}/src/platform/imx95/linker/data-sections.ld) + + set(PLATFORM "imx95") +endif() + # Building for native_posix-based whole-OS host emulator zephyr_library_sources_ifdef(CONFIG_ZEPHYR_POSIX ${SOF_SRC_PATH}/schedule/zephyr_ll.c diff --git a/zephyr/lib/dma.c b/zephyr/lib/dma.c index 9a641128da69..4d734026f322 100644 --- a/zephyr/lib/dma.c +++ b/zephyr/lib/dma.c @@ -170,6 +170,26 @@ SHARED_DATA struct dma dma[] = { .z_dev = DEVICE_DT_GET(DT_NODELABEL(host_dma)), }, #endif /* CONFIG_SOC_MIMX8UD7_ADSP */ +#ifdef CONFIG_SOC_MIMX9596_M7 +{ + .plat_data = { + .dir = DMA_DIR_MEM_TO_DEV | DMA_DIR_DEV_TO_MEM, + .devs = DMA_DEV_SAI, + .channels = 64, + .period_count = 2, + }, + .z_dev = DEVICE_DT_GET(DT_NODELABEL(edma2)), +}, +{ + .plat_data = { + .dir = DMA_DIR_HMEM_TO_LMEM | DMA_DIR_LMEM_TO_HMEM, + .devs = DMA_DEV_HOST, + .channels = DT_PROP(DT_NODELABEL(host_dma), dma_channels), + .period_count = 2, + }, + .z_dev = DEVICE_DT_GET(DT_NODELABEL(host_dma)), +}, +#endif /* CONFIG_SOC_MIMX9596_M7 */ }; const struct dma_info lib_dma = {