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ASoC: SOF: ipc3-topology: subtract ALH dai_index by 2 #5217
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@bardliao do we need to state this is a fix in our commit message as some users SDW wont work without this patch ?
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I think this is way to go. A few comments on the commit message and inline commets. I wonder if we could somehow also highlight that we have to support existing topology files, so renumbering (in Linux code) is not an option.
sound/soc/sof/ipc3-topology.c
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if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) { | ||
/* | ||
* DAI 2 is used as the first DAI for SDW in topology, normalize | ||
* it to 0 |
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Maybe refer to sof_sdw.c (something like "see SOC_SDW_INTEL_BIDIR_PDI_BASE in sof_sdw.c") defitinion to explain where the value "2" comes from?
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Maybe refer to sof_sdw.c (something like "see SOC_SDW_INTEL_BIDIR_PDI_BASE in sof_sdw.c") defitinion to explain where the value "2" comes from?
Added. But on the second thought, this is Intel specific. Should we do it here?
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Added sdw_bidir_base in sof_dev_desc struct. But I am not sure if it is the best place to add the base.
sound/soc/sof/ipc3-topology.c
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comp_dai->dai_index -= 2; | ||
if (comp_dai->dai_index < 0) { | ||
dev_err(sdev->dev, | ||
"Invalid ALH dai index %d, Please use SDW Pin 2 and above\n", |
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maybe we can say that only Pin numbers > 1 are supported instead of saying please use Pin 2
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maybe we can say that only Pin numbers > 1 are supported instead of saying please use Pin 2
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Yes, Fixes tag added. |
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Thanks @bardliao . All my concerns covered. I'll let other kernel folks comment on the sdw_bidir_base added -- not sure whether this is ok or not (it's always 2 now). It does make the logic more explicit, which I do like.
@bardliao I think we should squash both patches or at least split out the addition of the base field and setting the base into a seaprate patch first following by the next patch using it |
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Done |
@ujfalusi pls review. Thanks |
sound/soc/sof/ipc3-topology.c
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/* Subtract the base to match the IPC3 FW dai index. */ | ||
if (comp_dai->type == SOF_DAI_INTEL_ALH) { | ||
comp_dai->dai_index -= desc->sdw_bidir_base; | ||
if (comp_dai->dai_index < 0) { |
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dai_index is uint32_t ...
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dai_index is uint32_t ...
Thanks, move the check before subtracting.
sound/soc/sof/intel/pci-icl.c
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@@ -27,6 +27,7 @@ static const struct sof_dev_desc icl_desc = { | |||
.resindex_pcicfg_base = -1, | |||
.resindex_imr_base = -1, | |||
.irqindex_host_ipc = -1, | |||
.sdw_bidir_base = 2, |
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This is not really platform related, does it? It is IPC3 related, IPC4's bidir base is 0, right?
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This is not really platform related, does it? It is IPC3 related, IPC4's bidir base is 0, right?
That is platform related. SDW bidirectional pins are the same on IPC3 and IPC4. But, IPC4 FW supports all SDW pins. So, we don't need to shift the dai index in IPC4.
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Right, so, if you boot cAVS2.5 (TGL/ADL/etc) the sdw_bidir_base is applicable, but it is applicable only if you boot to use IPC3. Same platform, different IPC version.
sdw_bidir_base is not platform related option, it is IPC version specific, no?
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or you are saying that with both IPC3/4 the topology's sdw bidir index starts at 2 and we don't need to normalize this in case of IPC4?
Or to put this the other way: On MTL+ the bidir_base is 0 in (IPC4) topology and it is 2 in (IPC4) cAVS2.5?
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sdw_bidir_base will be applied to IPC3 only because dai_index 4, and 5 are acceptable by IPC4. As far as I know we always use 2+ SDW Pins even on MTL+ platforms.
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you are not touching pci-mtl, pci-lnl, for those platforms the sdw_bidir_base is 0.
Why do you even need this in the
struct sof_dev_desc
when the subtraction is only applicable for INTEL_ALH with IPC3 and it is always applicable in this case?
Because AMD or other vendors may not need the offset.
If you are saying that this is somehow a platform variable and applicable to all Intel platforms, then you should set the correct value for all platforms that this applies.
Sure I will add sdw_bidir_base to all Intel platforms. We define SOC_SDW_INTEL_BIDIR_PDI_BASE 2 and apply it to all Intel platforms. But, that doesn't match to the HW capabilities. I am not sure about older platforms, but I checked TGL, MTL, and LNL, all SDW pins are bidirectional. You can check the HW capabilities by the dmesg log below.
soundwire_intel:intel_pdi_init: soundwire_intel soundwire_intel.link.0: PCM cap bd:12 in:0 out:0
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AMD and other vendors don't use dai type SOF_DAI_INTEL_ALH
?
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Added sdw_bidir_base to all Intel platforms.
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AMD and other vendors don't use dai type
SOF_DAI_INTEL_ALH
?
Oh, yes, that is a valid point. Then I think we don't need sdw_bidir_base.
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sound/soc/sof/ipc3-topology.c
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if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) | ||
config->dai_index = data->dai_index; | ||
if (flags & SOF_DAI_CONFIG_FLAGS_HW_PARAMS) { | ||
/* Subtract the base to match the IPC3 FW dai index. */ |
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The IPC3
is not needed, we are in ipc3-topology.c
file anyways.
I think the comment should be somehow different, probably 'Convert the topology pin index to ALH dai index, the mapping is using 2-off indexing, iow, pin #2 is ALH dai #0' or around these lines?
This looks much cleaner already, imho.
…ndex Intel SoundWire machine driver always uses Pin number 2 and above. Currently, the pin number is used as the FW DAI index directly. As a result, FW DAI 0 and 1 are never used. That worked fine because we use up to 2 DAIs in a SDW link. Convert the topology pin index to ALH dai index, the mapping is using 2-off indexing, iow, pin #2 is ALH dai #0. The issue exists since beginning. And the Fixes tag is the first commit that this commit can be applied. Fixes: b66bfc3 ("ASoC: SOF: sof-audio: Fix broken early bclk feature for SSP") Signed-off-by: Bard Liao <[email protected]>
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@kv2019i good for you ?
We use SDW pin 2 as for ALH dai 0. However, IPC3 ALH dai index should start from 0.
Fixes: thesofproject/sof#9571