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Implement method to guarantee that within a every pair of cores only 1 can work at the same time.
This should help with heavily DM bound workload like convolutions and LM head, while still keeping effective AICLK at 1GHz.
This requires modifications in data movement APIs to free up one NOC command buffer so TRISCs can issue NOC transactions over L1.
The text was updated successfully, but these errors were encountered:
Implement method to guarantee that within a every pair of cores only 1 can work at the same time.
This should help with heavily DM bound workload like convolutions and LM head, while still keeping effective AICLK at 1GHz.
This requires modifications in data movement APIs to free up one NOC command buffer so TRISCs can issue NOC transactions over L1.
The text was updated successfully, but these errors were encountered: