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td_2022-11-27_13-09-25.log
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td_2022-11-27_13-09-25.log
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============================================================
Tang Dynasty, V4.6.18154
Copyright: Shanghai Anlogic Infotech Co., Ltd.
2011 - 2021
Executable = C:/Anlogic/TD4.6.4/bin/td.exe
Built at = 16:39:36 Mar 27 2020
Run by = MxD
Run Date = Sun Nov 27 13:09:25 2022
Run on = DESKTOP-6NPNTAP
============================================================
RUN-1002 : start command "open_project synthesizer.al"
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file osc.v
RUN-1002 : start command "import_device eagle_s20.db -package BG256"
ARC-1001 : Device Initialization.
ARC-1001 : ------------------------------------------------------------------
ARC-1001 : OPTION | IO | SETTING
ARC-1001 : ------------------------------------------------------------------
ARC-1001 : cso_b/cclk/mosi/miso/dout | T3/R11/T10/P10/S11 | gpio
ARC-1001 : done | P13 | gpio
ARC-1001 : program_b | T2 | dedicated
ARC-1001 : tdi/tms/tck/tdo | C12/A15/C14/E14 | dedicated
ARC-1001 : ------------------------------------------------------------------
ARC-1004 : Device setting, marked 5 dedicate IOs in total.
RUN-1002 : start command "import_db synthesizer_pr.db"
RUN-1001 : Importing database generated by Tang Dynasty, V4.6.18154.
RUN-1001 : Database version number 46116.
RUN-1001 : Import IO constraints
RUN-1001 : Import Inst constraints
RUN-1001 : Import flow parameters
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file osc.v
HDL-1007 : analyze verilog file dfilter.v
HDL-1007 : analyze verilog file osc.v
HDL-1007 : analyze verilog file top.v
HDL-8007 ERROR: syntax error near 'endmodule' in top.v(13)
HDL-8007 ERROR: Verilog 2000 keyword endmodule used in incorrect context in top.v(13)
HDL-1007 : Verilog file 'top.v' ignored due to errors
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file osc.v
HDL-1007 : analyze verilog file dfilter.v
RUN-1002 : start command "elaborate -top top"
HDL-1007 : elaborate module top in top.v(1)
HDL-1007 : elaborate module osc in osc.v(1)
HDL-1007 : elaborate module dfilter in dfilter.v(1)
HDL-1200 : Current top model is top
HDL-1100 : Inferred 0 RAMs.
RUN-1002 : start command "read_adc top.adc"
RUN-1002 : start command "set_pin_assignment cap LOCATION = E16; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment res LOCATION = C15; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment vib LOCATION = F16; "
USR-6010 WARNING: ADC constraints: pin clk has no constraint.
USR-6010 WARNING: ADC constraints: pin out has no constraint.
RUN-1002 : start command "optimize_rtl"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
RUN-8418 ERROR: License expired!
RUN-1002 : start command "read_adc top.adc"
RUN-1002 : start command "set_pin_assignment cap LOCATION = E16; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment res LOCATION = C15; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment vib LOCATION = F16; "
USR-6010 WARNING: ADC constraints: pin clk has no constraint.
USR-6010 WARNING: ADC constraints: pin out has no constraint.
RUN-1002 : start command "optimize_rtl"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
SYN-1012 : SanityCheck: Model "top"
SYN-1012 : SanityCheck: Model "dfilter"
SYN-1012 : SanityCheck: Model "osc"
SYN-1011 : Flatten model top
SYN-1011 : Flatten model dfilter
SYN-1011 : Flatten model osc
SYN-1014 : Optimize round 1
SYN-1032 : 109/0 useful/useless nets, 73/0 useful/useless insts
SYN-1019 : Optimized 0 mux instances.
SYN-1016 : Merged 2 instances.
SYN-1015 : Optimize round 1, 31 better
SYN-1014 : Optimize round 2
SYN-1032 : 80/29 useful/useless nets, 44/0 useful/useless insts
SYN-1019 : Optimized 0 mux instances.
SYN-1015 : Optimize round 2, 0 better
RUN-1002 : start command "report_area -file synthesizer_rtl.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Gate Statistics
#Basic gates 32
#and 0
#nand 0
#or 0
#nor 0
#xor 0
#xnor 0
#buf 0
#not 1
#bufif1 0
#MX21 2
#FADD 0
#DFF 29
#LATCH 0
#MACRO_ADD 9
#MACRO_EQ 1
RUN-1001 :
Report Hierarchy Area:
+-----------------------------------------+
|Instance |Module |gates |seq |macros |
+-----------------------------------------+
|top |top |3 |29 |10 |
+-----------------------------------------+
RUN-1002 : start command "export_db synthesizer_rtl.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
RUN-1002 : start command "optimize_gate -packarea synthesizer_gate.area"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
SYN-2001 : Map 5 IOs to PADs
SYN-2501 : Processed 0 LOGIC_BUF instances.
SYN-2571 : Optimize after map_dsp, round 1
SYN-1032 : 85/0 useful/useless nets, 49/0 useful/useless insts
SYN-2571 : Optimize after map_dsp, round 1, 0 better
SYN-2501 : Optimize round 1
SYN-1032 : 87/0 useful/useless nets, 67/0 useful/useless insts
SYN-1017 : Remove 3 const input seq instances
SYN-1002 : dfilter/reg1_b3
SYN-1002 : dfilter/reg1_b4
SYN-1002 : dfilter/reg1_b5
SYN-2501 : Optimize round 1, 18 better
SYN-2501 : Optimize round 2
SYN-1032 : 84/0 useful/useless nets, 64/0 useful/useless insts
SYN-2501 : Optimize round 2, 0 better
SYN-2501 : Map 6 macro adder
SYN-1032 : 123/0 useful/useless nets, 103/0 useful/useless insts
SYN-3001 : Running gate level optimization.
SYN-2581 : Mapping with K=4, #lut = 14 (3.29), #lev = 3 (1.50)
SYN-2551 : Post LUT mapping optimization.
SYN-3001 : Logic optimization runtime opt = 0.01 sec, map = 0.00 sec
SYN-3001 : Mapper mapped 53 instances into 15 LUTs, name keeping = 40%.
SYN-1001 : Packing model "top" ...
SYN-4010 : Pack lib has 42 rtl pack models with 15 top pack blocks
SYN-1014 : Optimize round 1
SYN-1032 : 78/1 useful/useless nets, 62/2 useful/useless insts
SYN-1015 : Optimize round 1, 3 better
SYN-1014 : Optimize round 2
SYN-1032 : 78/0 useful/useless nets, 62/0 useful/useless insts
SYN-1015 : Optimize round 2, 0 better
SYN-4002 : Packing 24 DFF/LATCH to SEQ ...
SYN-4009 : Pack 1 carry chain into lslice
SYN-4007 : Packing 0 adder to BLE ...
SYN-4008 : Packed 0 adder and 0 SEQ to BLE.
SYN-4007 : Packing 0 gate4 to BLE ...
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
SYN-4012 : Packed 0 FxMUX
SYN-4007 : Packing 0 MUX to BLE ...
SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
SYN-4007 : Packing 14 LUT to BLE ...
SYN-4008 : Packed 14 LUT and 3 SEQ to BLE.
SYN-4003 : Packing 21 remaining SEQ's ...
SYN-4004 : #0: Packed 0 SEQ (21 nodes)...
SYN-4004 : #1: Packed 11 SEQ (33 nodes)...
SYN-4005 : Packed 11 SEQ with LUT/SLICE
SYN-4006 : 2 single LUT's are left
SYN-4006 : 10 single SEQ's are left
SYN-4011 : Packing model "top" (AL_USER_NORMAL) with 24/36 primitive instances ...
RUN-1002 : start command "report_area -file synthesizer_gate.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Utilization Statistics
#lut 22 out of 19600 0.11%
#reg 24 out of 19600 0.12%
#le 32
#lut only 8 out of 32 25.00%
#reg only 10 out of 32 31.25%
#lut® 14 out of 32 43.75%
#dsp 0 out of 29 0.00%
#bram 0 out of 64 0.00%
#bram9k 0
#fifo9k 0
#bram32k 0 out of 16 0.00%
#pad 5 out of 188 2.66%
#ireg 1
#oreg 0
#treg 0
#pll 0 out of 4 0.00%
RUN-1001 :
Report Hierarchy Area:
+--------------------------------------+
|Instance |Module |le |lut |seq |
+--------------------------------------+
|top |top |32 |22 |24 |
+--------------------------------------+
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model top
RUN-1002 : start command "export_db synthesizer_gate.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
GUI-5004 WARNING: clk has not been assigned location ...
GUI-5004 WARNING: out has not been assigned location ...
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file osc.v
HDL-1007 : analyze verilog file dfilter.v
RUN-1002 : start command "elaborate -top top"
HDL-1007 : elaborate module top in top.v(1)
HDL-1007 : elaborate module osc in osc.v(1)
HDL-1007 : elaborate module dfilter in dfilter.v(1)
HDL-1200 : Current top model is top
HDL-1100 : Inferred 0 RAMs.
RUN-1002 : start command "read_adc top.adc"
RUN-1002 : start command "set_pin_assignment cap LOCATION = E16; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment clk LOCATION = K14; "
RUN-1002 : start command "set_pin_assignment out LOCATION = C16; "
RUN-1002 : start command "set_pin_assignment res LOCATION = C15; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment vib LOCATION = F16; "
RUN-1002 : start command "optimize_rtl"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
SYN-1012 : SanityCheck: Model "top"
SYN-1012 : SanityCheck: Model "dfilter"
SYN-1012 : SanityCheck: Model "osc"
SYN-1011 : Flatten model top
SYN-1011 : Flatten model dfilter
SYN-1011 : Flatten model osc
SYN-1014 : Optimize round 1
SYN-1032 : 109/0 useful/useless nets, 73/0 useful/useless insts
SYN-1019 : Optimized 0 mux instances.
SYN-1016 : Merged 2 instances.
SYN-1015 : Optimize round 1, 31 better
SYN-1014 : Optimize round 2
SYN-1032 : 80/29 useful/useless nets, 44/0 useful/useless insts
SYN-1019 : Optimized 0 mux instances.
SYN-1015 : Optimize round 2, 0 better
RUN-1002 : start command "report_area -file synthesizer_rtl.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Gate Statistics
#Basic gates 32
#and 0
#nand 0
#or 0
#nor 0
#xor 0
#xnor 0
#buf 0
#not 1
#bufif1 0
#MX21 2
#FADD 0
#DFF 29
#LATCH 0
#MACRO_ADD 9
#MACRO_EQ 1
RUN-1001 :
Report Hierarchy Area:
+-----------------------------------------+
|Instance |Module |gates |seq |macros |
+-----------------------------------------+
|top |top |3 |29 |10 |
+-----------------------------------------+
RUN-1002 : start command "export_db synthesizer_rtl.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
RUN-1002 : start command "optimize_gate -packarea synthesizer_gate.area"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
SYN-2001 : Map 5 IOs to PADs
SYN-2501 : Processed 0 LOGIC_BUF instances.
SYN-2571 : Optimize after map_dsp, round 1
SYN-1032 : 85/0 useful/useless nets, 49/0 useful/useless insts
SYN-2571 : Optimize after map_dsp, round 1, 0 better
SYN-2501 : Optimize round 1
SYN-1032 : 87/0 useful/useless nets, 67/0 useful/useless insts
SYN-1017 : Remove 3 const input seq instances
SYN-1002 : dfilter/reg1_b3
SYN-1002 : dfilter/reg1_b4
SYN-1002 : dfilter/reg1_b5
SYN-2501 : Optimize round 1, 18 better
SYN-2501 : Optimize round 2
SYN-1032 : 84/0 useful/useless nets, 64/0 useful/useless insts
SYN-2501 : Optimize round 2, 0 better
SYN-2501 : Map 6 macro adder
SYN-1032 : 123/0 useful/useless nets, 103/0 useful/useless insts
SYN-3001 : Running gate level optimization.
SYN-2581 : Mapping with K=4, #lut = 14 (3.29), #lev = 3 (1.50)
SYN-2551 : Post LUT mapping optimization.
SYN-3001 : Logic optimization runtime opt = 0.00 sec, map = 0.00 sec
SYN-3001 : Mapper mapped 53 instances into 15 LUTs, name keeping = 40%.
SYN-1001 : Packing model "top" ...
SYN-4010 : Pack lib has 42 rtl pack models with 15 top pack blocks
SYN-1014 : Optimize round 1
SYN-1032 : 78/1 useful/useless nets, 62/2 useful/useless insts
SYN-1015 : Optimize round 1, 3 better
SYN-1014 : Optimize round 2
SYN-1032 : 78/0 useful/useless nets, 62/0 useful/useless insts
SYN-1015 : Optimize round 2, 0 better
SYN-4002 : Packing 24 DFF/LATCH to SEQ ...
SYN-4009 : Pack 1 carry chain into lslice
SYN-4007 : Packing 0 adder to BLE ...
SYN-4008 : Packed 0 adder and 0 SEQ to BLE.
SYN-4007 : Packing 0 gate4 to BLE ...
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
SYN-4012 : Packed 0 FxMUX
SYN-4007 : Packing 0 MUX to BLE ...
SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
SYN-4007 : Packing 14 LUT to BLE ...
SYN-4008 : Packed 14 LUT and 3 SEQ to BLE.
SYN-4003 : Packing 21 remaining SEQ's ...
SYN-4004 : #0: Packed 0 SEQ (21 nodes)...
SYN-4004 : #1: Packed 11 SEQ (33 nodes)...
SYN-4005 : Packed 11 SEQ with LUT/SLICE
SYN-4006 : 2 single LUT's are left
SYN-4006 : 10 single SEQ's are left
SYN-4011 : Packing model "top" (AL_USER_NORMAL) with 24/36 primitive instances ...
RUN-1002 : start command "report_area -file synthesizer_gate.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Utilization Statistics
#lut 22 out of 19600 0.11%
#reg 24 out of 19600 0.12%
#le 32
#lut only 8 out of 32 25.00%
#reg only 10 out of 32 31.25%
#lut® 14 out of 32 43.75%
#dsp 0 out of 29 0.00%
#bram 0 out of 64 0.00%
#bram9k 0
#fifo9k 0
#bram32k 0 out of 16 0.00%
#pad 5 out of 188 2.66%
#ireg 1
#oreg 0
#treg 0
#pll 0 out of 4 0.00%
RUN-1001 :
Report Hierarchy Area:
+--------------------------------------+
|Instance |Module |le |lut |seq |
+--------------------------------------+
|top |top |32 |22 |24 |
+--------------------------------------+
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model top
RUN-1002 : start command "export_db synthesizer_gate.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
RUN-1002 : start command "place"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
PHY-3001 : Placer runs in 12 thread(s).
SYN-4024 : Net "clk_pad" drive clk pins.
SYN-4025 : Tag rtl::Net clk_pad as clock net
SYN-4026 : Tagged 1 rtl::Net as clock net
PHY-1001 : Populate physical database.
RUN-1001 : There are total 25 instances
RUN-1001 : 9 mslices, 8 lslices, 5 pads, 0 brams, 0 dsps
RUN-1001 : There are total 63 nets
RUN-1001 : 33 nets have 2 pins
RUN-1001 : 27 nets have [3 - 5] pins
RUN-1001 : 2 nets have [11 - 20] pins
RUN-1001 : 1 nets have [21 - 99] pins
PHY-3001 : Initial placement ...
PHY-3001 : design contains 23 instances, 17 slices, 1 macros(4 instances)
PHY-3001 : Start timing update ...
RUN-1002 : start command "start_timer"
TMR-5001 WARNING: No sdc constraints found while initiating timer.
TMR-2505 : Start building timing graph for model top.
TMR-2506 : Build timing graph completely. Port num: 5, tpin num: 182, tnet num: 61, tinst num: 23, tnode num: 241, tedge num: 302.
TMR-2507 : Eliminate loop in the timing graph, delete 0 tedges.
TMR-2508 : Levelizing timing graph completed, there are 13 levels in total.
TMR-2501 : Timing graph initialized successfully.
TMR-2503 : Start to update net delay, extr mode = 2.
TMR-2504 : Update delay of 61 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
TMR-3002 : No user constraint, initiate default constraint.
TMR-1501 : Assign derive clock DeriveClock to 30 clock pins, and constraint 55 relative nodes.
TMR-3005 : Start mapping report constraints, there are 0 constraints in total.
TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
PHY-3001 : End timing update; 0.007184s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Global placement ...
PHY-3001 : Initial: Len = 20059
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
PHY-3002 : Step(1): len = 11592.6, overlap = 0
PHY-3002 : Step(2): len = 8304.4, overlap = 0
PHY-3002 : Step(3): len = 6997.7, overlap = 0
PHY-3002 : Step(4): len = 5658, overlap = 0
PHY-3002 : Step(5): len = 4777.8, overlap = 0
PHY-3002 : Step(6): len = 4187.2, overlap = 0
PHY-3002 : Step(7): len = 3737, overlap = 0
PHY-3002 : Step(8): len = 3254.7, overlap = 0
PHY-3002 : Step(9): len = 2926.5, overlap = 0
PHY-3002 : Step(10): len = 2709.8, overlap = 0
PHY-3002 : Step(11): len = 2544, overlap = 0
PHY-3002 : Step(12): len = 2223.3, overlap = 0
PHY-3002 : Step(13): len = 2057, overlap = 0
PHY-3002 : Step(14): len = 1893.5, overlap = 0
PHY-3002 : Step(15): len = 1822, overlap = 0
PHY-3002 : Step(16): len = 1684.6, overlap = 0
PHY-3002 : Step(17): len = 1573.3, overlap = 0
PHY-3002 : Step(18): len = 1553.5, overlap = 0
PHY-3002 : Step(19): len = 531, overlap = 0
PHY-3002 : Step(20): len = 528.6, overlap = 0
PHY-3002 : Step(21): len = 526, overlap = 0
PHY-3001 : Legalization ...
PHY-3001 : End legalization; 0.003045s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000127427
PHY-3002 : Step(22): len = 522.2, overlap = 0
PHY-3002 : Step(23): len = 522.2, overlap = 0
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.78189e-05
PHY-3002 : Step(24): len = 519.4, overlap = 2.25
PHY-3002 : Step(25): len = 522, overlap = 2
PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000115638
PHY-3002 : Step(26): len = 524.3, overlap = 2.25
PHY-3002 : Step(27): len = 532.6, overlap = 2
PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000231276
PHY-3002 : Step(28): len = 533.4, overlap = 1.5
PHY-3002 : Step(29): len = 534.5, overlap = 1.5
PHY-3001 : Legalization ...
PHY-3001 : End legalization; 0.008620s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0653217
PHY-3002 : Step(30): len = 855.9, overlap = 0.25
PHY-3002 : Step(31): len = 720.7, overlap = 0.25
PHY-3002 : Step(32): len = 673.6, overlap = 0.25
PHY-3002 : Step(33): len = 664.6, overlap = 0.25
PHY-3002 : Step(34): len = 654.6, overlap = 0.25
PHY-3001 : Legalization ...
PHY-3001 : End legalization; 0.004453s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Legalized: Len = 750, Over = 0
PHY-3001 : Final: Len = 750, Over = 0
PHY-3001 : Improving timing with driver duplication.
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Global iterations in 12 thread ...
PHY-1002 : len = 712, over cnt = 4(0%), over = 6, worst = 2
PHY-1002 : len = 808, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End global iterations; 0.010315s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
RUN-1003 : finish command "place" in 1.094822s wall, 1.265625s user + 0.765625s system = 2.031250s CPU (185.5%)
RUN-1004 : used memory is 197 MB, reserved memory is 149 MB, peak memory is 212 MB
RUN-1002 : start command "route"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
PHY-1001 : Pin misalignment score is improved from 21 to 17
PHY-1001 : Pin misalignment score is improved from 17 to 17
PHY-1001 : Route runs in 12 thread(s)
RUN-1001 : There are total 25 instances
RUN-1001 : 9 mslices, 8 lslices, 5 pads, 0 brams, 0 dsps
RUN-1001 : There are total 63 nets
RUN-1001 : 33 nets have 2 pins
RUN-1001 : 27 nets have [3 - 5] pins
RUN-1001 : 2 nets have [11 - 20] pins
RUN-1001 : 1 nets have [21 - 99] pins
PHY-1001 : Start global routing ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Global iterations in 12 thread ...
PHY-1002 : len = 712, over cnt = 4(0%), over = 6, worst = 2
PHY-1002 : len = 808, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End global iterations; 0.011367s wall, 0.015625s user + 0.015625s system = 0.031250s CPU (274.9%)
PHY-1001 : End global routing; 0.063115s wall, 0.062500s user + 0.015625s system = 0.078125s CPU (123.8%)
PHY-1001 : Start detail routing ...
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net clk_pad will be routed on clock mesh
PHY-1001 : Detail Route ...
PHY-1001 : ===== Detail Route Phase 1 =====
PHY-1001 : Routed 1% nets.
PHY-1002 : len = 1448, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End Routed; 0.003330s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-1001 : ===== Detail Route Phase 2 =====
PHY-1001 : Routed 1% nets.
PHY-1002 : len = 1448, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End Routed; 0.000012s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-1001 : ===== Detail Route Phase 3 =====
PHY-1001 : Routed 49% nets.
PHY-1001 : Routed 61% nets.
PHY-1001 : Routed 63% nets.
PHY-1001 : Routed 77% nets.
PHY-1001 : Routed 84% nets.
PHY-1002 : len = 2728, over cnt = 0(0%), over = 0, worst = 0
PHY-1003 : Routed, final wirelength = 2728
PHY-1001 : End Routed; 0.011919s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-1001 : 0 feed throughs used by 0 nets
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net clk_pad will be routed on clock mesh
PHY-1001 : eco open net = 0
PHY-1001 : End detail routing; 4.701854s wall, 4.437500s user + 0.312500s system = 4.750000s CPU (101.0%)
PHY-1001 : Routing violations:
PHY-1001 : End of Routing Violations.
RUN-1003 : finish command "route" in 4.883861s wall, 4.625000s user + 0.328125s system = 4.953125s CPU (101.4%)
RUN-1004 : used memory is 296 MB, reserved memory is 253 MB, peak memory is 832 MB
RUN-1002 : start command "report_area -io_info -file synthesizer_phy.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Utilization Statistics
#lut 22 out of 19600 0.11%
#reg 24 out of 19600 0.12%
#le 32
#lut only 8 out of 32 25.00%
#reg only 10 out of 32 31.25%
#lut® 14 out of 32 43.75%
#dsp 0 out of 29 0.00%
#bram 0 out of 64 0.00%
#bram9k 0
#fifo9k 0
#bram32k 0 out of 16 0.00%
#pad 5 out of 188 2.66%
#ireg 1
#oreg 0
#treg 0
#pll 0 out of 4 0.00%
RUN-1001 :
RUN-1002 : start command "export_db synthesizer_pr.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
RUN-1002 : start command "bitgen -bit synthesizer.bit -version 0X00 -g ucode:00000000000000000000000000000000"
BIT-1003 : Start to generate bitstream.
BIT-1002 : Init instances with 12 threads.
BIT-1002 : Init instances completely, inst num: 25
BIT-1002 : Init pips with 12 threads.
BIT-1002 : Init pips completely, net num: 63, pip num: 297
BIT-1003 : Multithreading accelaration with 12 threads.
BIT-1003 : Generate bitstream completely, there are 55 valid insts, and 905 bits set as '1'.
BIT-1004 : PLL setting string = 0000
BIT-1004 : Generate bits file synthesizer.bit.
RUN-1002 : start command "download -bit synthesizer.bit -mode program_spi -v -spd 6 -sec 64 -cable 0"
PRG-2014 : Chip validation success: EAGLE_S20_BG256
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_BG256 -m program_spi -bit synthesizer.bit"
RUN-1003 : finish command "bit_to_vec -chip EAGLE_S20_BG256 -m program_spi -bit synthesizer.bit" in 1.852234s wall, 1.843750s user + 0.062500s system = 1.906250s CPU (102.9%)
RUN-1004 : used memory is 663 MB, reserved memory is 632 MB, peak memory is 832 MB
RUN-1002 : start command "program_spi -cable 0 -spd 6"
RUN-1003 : finish command "program_spi -cable 0 -spd 6" in 91.925326s wall, 2.312500s user + 0.828125s system = 3.140625s CPU (3.4%)
RUN-1004 : used memory is 665 MB, reserved memory is 634 MB, peak memory is 832 MB
RUN-1002 : start command "bit_to_vec -chip EAGLE_S20_BG256 -m verify_spi -bit synthesizer.bit"
RUN-1002 : start command "program -cable 0 -spd 4"
RUN-1003 : finish command "program -cable 0 -spd 4" in 24.812606s wall, 0.406250s user + 0.156250s system = 0.562500s CPU (2.3%)
RUN-1004 : used memory is 465 MB, reserved memory is 428 MB, peak memory is 832 MB
RUN-1002 : start command "program -cable 0 -spd 1"
RUN-1003 : finish command "download -bit synthesizer.bit -mode program_spi -v -spd 6 -sec 64 -cable 0" in 121.304175s wall, 5.312500s user + 1.265625s system = 6.578125s CPU (5.4%)
RUN-1004 : used memory is 325 MB, reserved memory is 280 MB, peak memory is 832 MB
GUI-1001 : Download success!
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file osc.v
HDL-1007 : analyze verilog file dfilter.v
HDL-1007 : analyze verilog file top.v
HDL-1007 : analyze verilog file osc.v
HDL-1007 : analyze verilog file dfilter.v
RUN-1002 : start command "elaborate -top top"
HDL-1007 : elaborate module top in top.v(1)
HDL-1007 : elaborate module osc in osc.v(1)
HDL-1007 : elaborate module dfilter in dfilter.v(1)
HDL-1200 : Current top model is top
HDL-1100 : Inferred 0 RAMs.
RUN-1002 : start command "read_adc top.adc"
RUN-1002 : start command "set_pin_assignment cap LOCATION = E16; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment clk LOCATION = K14; "
RUN-1002 : start command "set_pin_assignment out LOCATION = C16; "
RUN-1002 : start command "set_pin_assignment res LOCATION = C15; PULLTYPE = NONE; "
RUN-1002 : start command "set_pin_assignment vib LOCATION = F16; "
RUN-1002 : start command "optimize_rtl"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
SYN-1012 : SanityCheck: Model "top"
SYN-1012 : SanityCheck: Model "dfilter"
SYN-1012 : SanityCheck: Model "osc"
SYN-1011 : Flatten model top
SYN-1011 : Flatten model dfilter
SYN-1011 : Flatten model osc
SYN-1014 : Optimize round 1
SYN-1032 : 109/0 useful/useless nets, 73/0 useful/useless insts
SYN-1019 : Optimized 0 mux instances.
SYN-1016 : Merged 2 instances.
SYN-1015 : Optimize round 1, 31 better
SYN-1014 : Optimize round 2
SYN-1032 : 80/29 useful/useless nets, 44/0 useful/useless insts
SYN-1019 : Optimized 0 mux instances.
SYN-1015 : Optimize round 2, 0 better
RUN-1002 : start command "report_area -file synthesizer_rtl.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Gate Statistics
#Basic gates 32
#and 0
#nand 0
#or 0
#nor 0
#xor 0
#xnor 0
#buf 0
#not 1
#bufif1 0
#MX21 2
#FADD 0
#DFF 29
#LATCH 0
#MACRO_ADD 9
#MACRO_EQ 1
RUN-1001 :
Report Hierarchy Area:
+-----------------------------------------+
|Instance |Module |gates |seq |macros |
+-----------------------------------------+
|top |top |3 |29 |10 |
+-----------------------------------------+
RUN-1002 : start command "export_db synthesizer_rtl.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
RUN-1002 : start command "optimize_gate -packarea synthesizer_gate.area"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
SYN-2001 : Map 5 IOs to PADs
SYN-2501 : Processed 0 LOGIC_BUF instances.
SYN-2571 : Optimize after map_dsp, round 1
SYN-1032 : 85/0 useful/useless nets, 49/0 useful/useless insts
SYN-2571 : Optimize after map_dsp, round 1, 0 better
SYN-2501 : Optimize round 1
SYN-1032 : 87/0 useful/useless nets, 67/0 useful/useless insts
SYN-1017 : Remove 3 const input seq instances
SYN-1002 : dfilter/reg1_b3
SYN-1002 : dfilter/reg1_b4
SYN-1002 : dfilter/reg1_b5
SYN-2501 : Optimize round 1, 18 better
SYN-2501 : Optimize round 2
SYN-1032 : 84/0 useful/useless nets, 64/0 useful/useless insts
SYN-2501 : Optimize round 2, 0 better
SYN-2501 : Map 6 macro adder
SYN-1032 : 123/0 useful/useless nets, 103/0 useful/useless insts
SYN-3001 : Running gate level optimization.
SYN-2581 : Mapping with K=4, #lut = 14 (3.29), #lev = 3 (1.50)
SYN-2551 : Post LUT mapping optimization.
SYN-3001 : Logic optimization runtime opt = 0.00 sec, map = 0.00 sec
SYN-3001 : Mapper mapped 53 instances into 15 LUTs, name keeping = 40%.
SYN-1001 : Packing model "top" ...
SYN-4010 : Pack lib has 42 rtl pack models with 15 top pack blocks
SYN-1014 : Optimize round 1
SYN-1032 : 78/1 useful/useless nets, 62/2 useful/useless insts
SYN-1015 : Optimize round 1, 3 better
SYN-1014 : Optimize round 2
SYN-1032 : 78/0 useful/useless nets, 62/0 useful/useless insts
SYN-1015 : Optimize round 2, 0 better
SYN-4002 : Packing 24 DFF/LATCH to SEQ ...
SYN-4009 : Pack 1 carry chain into lslice
SYN-4007 : Packing 0 adder to BLE ...
SYN-4008 : Packed 0 adder and 0 SEQ to BLE.
SYN-4007 : Packing 0 gate4 to BLE ...
SYN-4008 : Packed 0 gate4 and 0 SEQ to BLE.
SYN-4012 : Packed 0 FxMUX
SYN-4007 : Packing 0 MUX to BLE ...
SYN-4008 : Packed 0 MUX and 0 SEQ to BLE.
SYN-4007 : Packing 14 LUT to BLE ...
SYN-4008 : Packed 14 LUT and 3 SEQ to BLE.
SYN-4003 : Packing 21 remaining SEQ's ...
SYN-4004 : #0: Packed 0 SEQ (21 nodes)...
SYN-4004 : #1: Packed 11 SEQ (33 nodes)...
SYN-4005 : Packed 11 SEQ with LUT/SLICE
SYN-4006 : 2 single LUT's are left
SYN-4006 : 10 single SEQ's are left
SYN-4011 : Packing model "top" (AL_USER_NORMAL) with 24/36 primitive instances ...
RUN-1002 : start command "report_area -file synthesizer_gate.area"
RUN-1001 : standard
***Report Model: top***
IO Statistics
#IO 5
#input 2
#output 1
#inout 2
Utilization Statistics
#lut 22 out of 19600 0.11%
#reg 24 out of 19600 0.12%
#le 32
#lut only 8 out of 32 25.00%
#reg only 10 out of 32 31.25%
#lut® 14 out of 32 43.75%
#dsp 0 out of 29 0.00%
#bram 0 out of 64 0.00%
#bram9k 0
#fifo9k 0
#bram32k 0 out of 16 0.00%
#pad 5 out of 188 2.66%
#ireg 1
#oreg 0
#treg 0
#pll 0 out of 4 0.00%
RUN-1001 :
Report Hierarchy Area:
+--------------------------------------+
|Instance |Module |le |lut |seq |
+--------------------------------------+
|top |top |32 |22 |24 |
+--------------------------------------+
RUN-1002 : start command "legalize_phy_inst"
SYN-1011 : Flatten model top
RUN-1002 : start command "export_db synthesizer_gate.db"
RUN-1001 : Exported /
RUN-1001 : Exported libs
RUN-1001 : Exported entities
RUN-1001 : Exported ports
RUN-1001 : Exported pins
RUN-1001 : Exported instances
RUN-1001 : Exported nets
RUN-1001 : Exported buses
RUN-1001 : Exported models
RUN-1001 : Exported congestions
RUN-1001 : Exported violations
RUN-1001 : Exported IO constraints
RUN-1001 : Exported Inst constraints
RUN-1001 : Exported flow parameters
RUN-1002 : start command "place"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
PHY-3001 : Placer runs in 12 thread(s).
SYN-4024 : Net "clk_pad" drive clk pins.
SYN-4025 : Tag rtl::Net clk_pad as clock net
SYN-4026 : Tagged 1 rtl::Net as clock net
PHY-1001 : Populate physical database.
RUN-1001 : There are total 25 instances
RUN-1001 : 9 mslices, 8 lslices, 5 pads, 0 brams, 0 dsps
RUN-1001 : There are total 63 nets
RUN-1001 : 33 nets have 2 pins
RUN-1001 : 27 nets have [3 - 5] pins
RUN-1001 : 2 nets have [11 - 20] pins
RUN-1001 : 1 nets have [21 - 99] pins
PHY-3001 : Initial placement ...
PHY-3001 : design contains 23 instances, 17 slices, 1 macros(4 instances)
PHY-3001 : Start timing update ...
RUN-1002 : start command "start_timer"
TMR-5001 WARNING: No sdc constraints found while initiating timer.
TMR-2505 : Start building timing graph for model top.
TMR-2506 : Build timing graph completely. Port num: 5, tpin num: 182, tnet num: 61, tinst num: 23, tnode num: 241, tedge num: 302.
TMR-2507 : Eliminate loop in the timing graph, delete 0 tedges.
TMR-2508 : Levelizing timing graph completed, there are 13 levels in total.
TMR-2501 : Timing graph initialized successfully.
TMR-2503 : Start to update net delay, extr mode = 2.
TMR-2504 : Update delay of 61 nets completely.
TMR-2502 : Annotate delay completely, extr mode = 2.
TMR-3002 : No user constraint, initiate default constraint.
TMR-1501 : Assign derive clock DeriveClock to 30 clock pins, and constraint 55 relative nodes.
TMR-3005 : Start mapping report constraints, there are 0 constraints in total.
TMR-3003 : Constraints initiated successfully.
TMR-3501 : Forward propagation: start to calculate arrival time...
TMR-3502 : Backward propagation: start to calculate required time...
TMR-3503 : Timing propagation completes.
PHY-3001 : End timing update; 0.004323s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Global placement ...
PHY-3001 : Initial: Len = 20059
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0
PHY-3002 : Step(35): len = 11592.6, overlap = 0
PHY-3002 : Step(36): len = 8304.4, overlap = 0
PHY-3002 : Step(37): len = 6997.7, overlap = 0
PHY-3002 : Step(38): len = 5658, overlap = 0
PHY-3002 : Step(39): len = 4777.8, overlap = 0
PHY-3002 : Step(40): len = 4187.2, overlap = 0
PHY-3002 : Step(41): len = 3737, overlap = 0
PHY-3002 : Step(42): len = 3254.7, overlap = 0
PHY-3002 : Step(43): len = 2926.5, overlap = 0
PHY-3002 : Step(44): len = 2709.8, overlap = 0
PHY-3002 : Step(45): len = 2544, overlap = 0
PHY-3002 : Step(46): len = 2223.3, overlap = 0
PHY-3002 : Step(47): len = 2057, overlap = 0
PHY-3002 : Step(48): len = 1893.5, overlap = 0
PHY-3002 : Step(49): len = 1822, overlap = 0
PHY-3002 : Step(50): len = 1684.6, overlap = 0
PHY-3002 : Step(51): len = 1573.3, overlap = 0
PHY-3002 : Step(52): len = 1553.5, overlap = 0
PHY-3002 : Step(53): len = 531, overlap = 0
PHY-3002 : Step(54): len = 528.6, overlap = 0
PHY-3002 : Step(55): len = 526, overlap = 0
PHY-3001 : Legalization ...
PHY-3001 : End legalization; 0.003021s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Run with size of 4
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.000127427
PHY-3002 : Step(56): len = 522.2, overlap = 0
PHY-3002 : Step(57): len = 522.2, overlap = 0
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 5.78189e-05
PHY-3002 : Step(58): len = 519.4, overlap = 2.25
PHY-3002 : Step(59): len = 522, overlap = 2
PHY-3001 : :::1::: Try harder cell spreading with beta_ = 0.000115638
PHY-3002 : Step(60): len = 524.3, overlap = 2.25
PHY-3002 : Step(61): len = 532.6, overlap = 2
PHY-3001 : :::2::: Try harder cell spreading with beta_ = 0.000231276
PHY-3002 : Step(62): len = 533.4, overlap = 1.5
PHY-3002 : Step(63): len = 534.5, overlap = 1.5
PHY-3001 : Legalization ...
PHY-3001 : End legalization; 0.008829s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Run with size of 2
PHY-3001 : Cell area utilization is 0%, beta_incr = 0.998959
PHY-3001 : :::0::: Try harder cell spreading with beta_ = 0.0653217
PHY-3002 : Step(64): len = 855.9, overlap = 0.25
PHY-3002 : Step(65): len = 720.7, overlap = 0.25
PHY-3002 : Step(66): len = 673.6, overlap = 0.25
PHY-3002 : Step(67): len = 664.6, overlap = 0.25
PHY-3002 : Step(68): len = 654.6, overlap = 0.25
PHY-3001 : Legalization ...
PHY-3001 : End legalization; 0.004374s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-3001 : Legalized: Len = 750, Over = 0
PHY-3001 : Final: Len = 750, Over = 0
PHY-3001 : Improving timing with driver duplication.
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Global iterations in 12 thread ...
PHY-1002 : len = 712, over cnt = 4(0%), over = 6, worst = 2
PHY-1002 : len = 808, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End global iterations; 0.010152s wall, 0.015625s user + 0.000000s system = 0.015625s CPU (153.9%)
RUN-1003 : finish command "place" in 1.020049s wall, 1.265625s user + 0.750000s system = 2.015625s CPU (197.6%)
RUN-1004 : used memory is 177 MB, reserved memory is 265 MB, peak memory is 832 MB
RUN-1002 : start command "route"
RUN-1001 : Open license file C:/Anlogic/TD4.6.4/license/Anlogic.lic
PHY-1001 : Pin misalignment score is improved from 21 to 17
PHY-1001 : Pin misalignment score is improved from 17 to 17
PHY-1001 : Route runs in 12 thread(s)
RUN-1001 : There are total 25 instances
RUN-1001 : 9 mslices, 8 lslices, 5 pads, 0 brams, 0 dsps
RUN-1001 : There are total 63 nets
RUN-1001 : 33 nets have 2 pins
RUN-1001 : 27 nets have [3 - 5] pins
RUN-1001 : 2 nets have [11 - 20] pins
RUN-1001 : 1 nets have [21 - 99] pins
PHY-1001 : Start global routing ...
RUN-1001 : Generating global routing grids ...
PHY-1001 : Generate routing nets ...
PHY-1001 : Global iterations in 12 thread ...
PHY-1002 : len = 712, over cnt = 4(0%), over = 6, worst = 2
PHY-1002 : len = 808, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End global iterations; 0.010912s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-1001 : End global routing; 0.067689s wall, 0.109375s user + 0.000000s system = 0.109375s CPU (161.6%)
PHY-1001 : Start detail routing ...
PHY-1001 : Generate detailed routing grids ...
PHY-1001 : Generate nets ...
PHY-1001 : net clk_pad will be routed on clock mesh
PHY-1001 : Detail Route ...
PHY-1001 : ===== Detail Route Phase 1 =====
PHY-1001 : Routed 1% nets.
PHY-1002 : len = 1448, over cnt = 0(0%), over = 0, worst = 0
PHY-1001 : End Routed; 0.003288s wall, 0.000000s user + 0.000000s system = 0.000000s CPU (n/a%)
PHY-1001 : ===== Detail Route Phase 2 =====
PHY-1001 : Routed 1% nets.
PHY-1002 : len = 1448, over cnt = 0(0%), over = 0, worst = 0