From 83c29eb01d5a7a9fd1c1002db469a48bbb55fbcb Mon Sep 17 00:00:00 2001
From: ranvd <jordan1415926535@gmail.com>
Date: Wed, 3 Jul 2024 19:56:03 +0800
Subject: [PATCH] Fix interrupt handling priority inconsistent with specs

According to the specs. at 4.1.3
> Multiple simultaneous interrupts destined for supervisor mode are
> handled in the following decreasing priority order: SEI, SSI, STI.

In this commit, I switched the interrupt priority back to SEI at
the highest priority, which is the original implementation.
---
 riscv.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv.c b/riscv.c
index 732f181..eeba69e 100644
--- a/riscv.c
+++ b/riscv.c
@@ -331,7 +331,7 @@ static bool mmu_store(hart_t *vm,
     if (vm->error)
         return false;
 
-    if (unlikely(cond)){
+    if (unlikely(cond)) {
         if ((vm->lr_reservation != (addr | 1)))
             return false;
     }
@@ -805,7 +805,7 @@ void vm_step(hart_t *vm)
     vm->current_pc = vm->pc;
     if ((vm->sstatus_sie || !vm->s_mode) && (vm->sip & vm->sie)) {
         uint32_t applicable = (vm->sip & vm->sie);
-        uint8_t idx = ffs(applicable) - 1;
+        uint8_t idx = ilog2(applicable);
         if (idx == 1) {
             emu_state_t *data = PRIV(vm);
             data->clint.msip[vm->mhartid] = 0;