From af2dcb0a46168d5d1668aeefc7c591e74b2619b6 Mon Sep 17 00:00:00 2001 From: Yang Hau Date: Fri, 18 Oct 2024 00:05:04 +0200 Subject: [PATCH] Support RVV instructions --- src/decode.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/decode.c b/src/decode.c index c434b0fa..2c385a22 100644 --- a/src/decode.c +++ b/src/decode.c @@ -1791,6 +1791,50 @@ static inline bool op_cfsw(rv_insn_t *ir, const uint32_t insn) #define op_cflwsp OP_UNIMP #endif /* RV32_HAS(EXT_C) && RV32_HAS(EXT_F) */ +/* OP: RVV + * opcode is 0x57 + * 31 26 25 24 20 19 15 14 12 11 7 6 0 + * | funct6 |vm| vs2 | vs1 | funct3 | vd | opcode | + * refer https://blog.csdn.net/weixin_40198519/article/details/126662069 + */ +static inline bool op_v(rv_insn_t *ir, const uint32_t insn) +{ + uint32_t funct3_mask = 0x7000; + switch (insn & funct3_mask) { + case 0: + return op_ivv(ir, insn); + break; + case 1: + return op_fvv(ir, insn); + break; + case 2: + return op_mvv(ir, insn); + break; + case 3: + return op_ivi(ir, insn); + break; + case 4: + return op_ivx(ir, insn); + break; + case 5: + return op_fvf(ir, insn); + break; + case 6: + return op_mvx(ir, insn); + break; + default: + } + +} + +static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn) {} +static inline bool op_fvv(rv_insn_t *ir, const uint32_t insn) {} +static inline bool op_mvv(rv_insn_t *ir, const uint32_t insn) {} +static inline bool op_ivi(rv_insn_t *ir, const uint32_t insn) {} +static inline bool op_ivx(rv_insn_t *ir, const uint32_t insn) {} +static inline bool op_fvf(rv_insn_t *ir, const uint32_t insn) {} +static inline bool op_mvx(rv_insn_t *ir, const uint32_t insn) {} + /* handler for all unimplemented opcodes */ static inline bool op_unimp(rv_insn_t *ir UNUSED, uint32_t insn UNUSED) {