diff --git a/src/decode.c b/src/decode.c
index 8fbb9241..21fe1059 100644
--- a/src/decode.c
+++ b/src/decode.c
@@ -1959,7 +1959,7 @@ static inline bool op_mvx(rv_insn_t *ir, const uint32_t insn) {}
 static inline bool op_v(rv_insn_t *ir, const uint32_t insn)
 {
     uint32_t funct3_mask = 0x7000;
-    switch (insn & funct3_mask) {
+    switch ((insn & funct3_mask) >> 7) {
         case 0:
             return op_ivv(ir, insn);        
         case 1:
diff --git a/src/riscv.h b/src/riscv.h
index 24e036a7..385cf022 100644
--- a/src/riscv.h
+++ b/src/riscv.h
@@ -550,6 +550,10 @@ typedef struct {
      */
     uint32_t args_offset_size;
 
+    /* The max bits that RVV a single instruction can process
+     */
+    uint16_t vlen;
+
     /* arguments of emulation program */
     int argc;
     char **argv;
diff --git a/src/riscv_private.h b/src/riscv_private.h
index 43e0bb53..7f42cb7b 100644
--- a/src/riscv_private.h
+++ b/src/riscv_private.h
@@ -135,6 +135,10 @@ struct riscv_internal {
     uint32_t csr_fcsr;
 #endif
 
+#if RV32_HAS(EXT_RVV)
+    uint8_t vl; /* current vl size */
+#endif
+
     /* csr registers */
     uint64_t csr_cycle;     /* Machine cycle counter */
     uint32_t csr_time[2];   /* Performance counter */