1.2.16

Rebased with changes on Sourceforge

Numerous fixes an some small features:

• Create a source file list by right clicking in the hierarchy browser
• Create a dependancy list from the hierarchy browser
• When opening a declaration an multiple instances are found, it will list the path of the instances

Bugs fixed:

• Synchronization in between parser and hierarchy browser
• Handling records with identical named elements to an output value correctly for errors
• Fixed a parsing error on statements like signal a : std_logic_vector(3 downto 0) := (b-1 => '0', others => '1');

VHDL 2008 support

For now a test version on VHDL 2008 support, as provide by fpgadev

1.2.1.14

Improved scan time of encrypted Verilog files

1.2.1.12

Fix the annotations to work also with Eclipse CDT and do not rely on the annotations of JDT

1.2.1.11

Fix auto completion with records
Fixed external strings thet have gone missing, like "%perspective.name", that should have been "Verilog/VHDL"

1.2.1.9

• Use the Veditor occurences profile
• Verilog: Ignoring encrypted Verilog code, based on the protected pragma
• VHDL: Using the used packages in a file, when jumping to a declaration of this value in a package. This is avoid jumping to the wrong package when a constant is declared in multiple packages.
• VHDL: Upon detection of multiple implementations of the item you want to jump to, it provides you with a drop down menu with all the options

VHDL: Various syntax checks:

• Assigning a variable with <= instead of :=
• Assigning a signal with := instead of <=
• Using an output of an entity / procedure as input for a statement
• Assigning a value to an input or a constant