Feedback loop fix? #462
Replies: 8 comments 10 replies
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Hi @shibin2018, without seeing your code, I will assume that the DAG cycle is due to the framework believing data propagation from A -> B is 0 cycles and that the feedback signal from B -> A is also 0 cycles. The framework makes the assumption that the feedback signal from B to A will cause A to send data to B in the same cycle, and that B will then resend the feedback signal to A again causing a potential infinite loop:
Ways to fix this:
If you disable auto-precedence the framework will not make the assumption I mentioned above. Instead, the framework will now rely on the modeler to list the precedence rules between ports and events within the unit as well as between units. However, you now have the risk of introducing a DAG during simulation instead, so be mindful. BTW, I have a small presentation on how this works here. |
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ok, I will try it, Thank you very much! |
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Hi, @klingaard May I ask another question? |
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Both
The difference between the two is simply performance and one constraint. I re-read the documentation for these types of events and indeed it's not clear on the differentiation. I'll fix that. Thanks! |
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Hi, @klingaard, I come again! |
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Hi, @klingaard , How can I set the precedence beteween event and DataInPort if they are both in Tick phase?, I find that the callback function of dataInport will be called before the event automatically when data in, I need the opposite calling order. I try use >> opertator but it will generate compile error. And you mention that there is auto-precedence in sparta::Unit, what is the auto-precedence? Thank you for answering! |
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Hi, @klingaard , How can I set the precedence beteween event and DataInPort if they are both in Tick phase?, I find that the callback function of dataInport will be called before the event automatically when data in, I need the opposite calling order. I try use >> opertator but it will generate compile error. And you mention that there is auto-precedence in sparta::Unit, what is the auto-precedence? Thank you for answering! |
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ok |
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how I process the feedback?
for example, there are two modules A and B, A has outport bind to B, and A needs the feedback signal of B, when I make a outport from B to A, it will generate DAG CYCLE .
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