From a69a1c4d9e6c9ead0f65553893d4578200f79772 Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Fri, 5 Jul 2024 11:14:54 +0800 Subject: [PATCH] pinmux/pinctrl: use online xls directly Signed-off-by: Chen Wang --- SG200X/TRM/contents/cn/peripherals/saradc.rst | 2 +- .../contents/cn/pinmux-pinctrl/0.index.rst | 10 +- ...isters_configuration_information.table.rst | 769 ----- ...en_interface_and_signal_pin_fmux.table.rst | 2471 ----------------- ...in_control_registers_description.table.rst | 2301 --------------- .../pin_control_registers_overview.table.rst | 198 -- .../contents/cn/pinmux-pinctrl/pinctrl.rst | 12 - .../TRM/contents/cn/pinmux-pinctrl/pinmux.rst | 13 - SG200X/TRM/contents/en/peripherals/saradc.rst | 2 +- .../contents/en/pinmux-pinctrl/0.index.rst | 10 +- .../contents/en/pinmux-pinctrl/pinctrl.rst | 12 - .../TRM/contents/en/pinmux-pinctrl/pinmux.rst | 13 - 12 files changed, 14 insertions(+), 5799 deletions(-) delete mode 100644 SG200X/TRM/contents/cn/pinmux-pinctrl/fmux_registers_configuration_information.table.rst delete mode 100644 SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst delete mode 100644 SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_description.table.rst delete mode 100644 SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_overview.table.rst delete mode 100644 SG200X/TRM/contents/cn/pinmux-pinctrl/pinctrl.rst delete mode 100644 SG200X/TRM/contents/cn/pinmux-pinctrl/pinmux.rst delete mode 100644 SG200X/TRM/contents/en/pinmux-pinctrl/pinctrl.rst delete mode 100644 SG200X/TRM/contents/en/pinmux-pinctrl/pinmux.rst diff --git a/SG200X/TRM/contents/cn/peripherals/saradc.rst b/SG200X/TRM/contents/cn/peripherals/saradc.rst index d0336b4..398c47b 100644 --- a/SG200X/TRM/contents/cn/peripherals/saradc.rst +++ b/SG200X/TRM/contents/cn/peripherals/saradc.rst @@ -8,7 +8,7 @@ SARADC 为模拟信号数字转换控制器。本芯片有最多 2 个 SARADC .. only:: sg2002 - **注意：** 芯片并没有在管脚上为 Active Domain 下的控制器引出所有的 ADC 通道，具体参考 :ref:`table_inf_signal_pin_fmux_adc_sg2002`。 + **注意：** 芯片并没有在管脚上为 Active Domain 下的控制器引出所有的 ADC 通道，具体参考 :ref:`section_pinmux_pinctrl` 中 “功能信号表” 中 ADC 接口的描述。 特点 ~~~~ diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst index 106a219..78204b5 100644 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst +++ b/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst @@ -3,8 +3,10 @@ 管脚复用与控制 ============== -.. toctree:: - :maxdepth: 2 +.. only:: sg2002 - ./pinmux.rst - ./pinctrl.rst + 管脚复用和管脚控制的相关信息请直接参考在线表格: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/04_SG2002/04_SG2002_PINOUT.xlsx + +.. only:: sg2000 + + 管脚复用和管脚控制的相关信息请直接参考在线表格: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/03_SG2000/04_SG2000_PINOUT.xlsx diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/fmux_registers_configuration_information.table.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/fmux_registers_configuration_information.table.rst deleted file mode 100644 index e577d48..0000000 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/fmux_registers_configuration_information.table.rst +++ /dev/null @@ -1,769 +0,0 @@ -.. _table_fmux_info: -.. table:: FMUX Registers Configuration Information - :widths: 1 2 6 1 5 - - +---+------+------------------------+----+---------------------------+ - |Pin| Pin |Function_select_register|fmu\| Description | - |Num| Name | |x\_ | | - | | | |defa| | - | | | |ult | | - +===+======+========================+====+===========================+ - | 6 | SD0\ | FMUX_G\ | 0x0| IO SD0_CLK function | - | | _CLK | PIO_REG_IOCTRL_SD0_CLK | | select : | - | | | 0x0300_101C | | | - | | | | | - 0 : SDIO0_CLK (default) | - | | | | | - 1 : IIC1_SDA | - | | | | | - 2 : SPI0_SCK | - | | | | | - 3 : XGPIOA[7] | - | | | | | - 5 : PWM[15] | - | | | | | - 6 : EPHY_LNK_LED | - | | | | | - 7 : DBG[0] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 7 | SD0\ | FMUX_G\ | 0x0| IO SD0_CMD function | - | | _CMD | PIO_REG_IOCTRL_SD0_CMD | | select : | - | | | 0x0300_1020 | | | - | | | | | - 0 : SDIO0_CMD (default) | - | | | | | - 1 : IIC1_SCL | - | | | | | - 2 : SPI0_SDO | - | | | | | - 3 : XGPIOA[8] | - | | | | | - 5 : PWM[14] | - | | | | | - 6 : EPHY_SPD_LED | - | | | | | - 7 : DBG[1] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 8 | SD0\ | FMUX_G\ | 0x0| IO SD0_D0 function select:| - | | _D0 | PIO_REG_IOCTRL_SD0_D0 | | | - | | | 0x0300_1024 | | - 0 : SDIO0_D[0] (default)| - | | | | | - 1 : CAM_MCLK1 | - | | | | | - 2 : SPI0_SDI | - | | | | | - 3 : XGPIOA[9] | - | | | | | - 4 : UART3_TX | - | | | | | - 5 : PWM[13] | - | | | | | - 6 : WG0_D0 | - | | | | | - 7 : DBG[2] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 10| SD\ | FMUX_G\ | 0x0| IO SD0_D1 function select:| - | | 0_D1 | PIO_REG_IOCTRL_SD0_D1 | | | - | | | 0x0300_1028 | | - 0 : SDIO0_D[1] (default)| - | | | | | - 1 : IIC1_SDA | - | | | | | - 2 : AUX0 | - | | | | | - 3 : XGPIOA[10] | - | | | | | - 4 : UART1_TX | - | | | | | - 5 : PWM[12] | - | | | | | - 6 : WG0_D1 | - | | | | | - 7 : DBG[3] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 11| SD\ | FMUX_G\ | 0x0| IO SD0_D2 function select:| - | | 0_D2 | PIO_REG_IOCTRL_SD0_D2 | | | - | | | 0x0300_102C | | - 0 : SDIO0_D[2] (default)| - | | | | | - 1 : IIC1_SCL | - | | | | | - 2 : AUX1 | - | | | | | - 3 : XGPIOA[11] | - | | | | | - 4 : UART1_RX | - | | | | | - 5 : PWM[11] | - | | | | | - 6 : WG1_D0 | - | | | | | - 7 : DBG[4] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 12| SD\ | FMUX_G\ | 0x0| IO SD0_D3 function select:| - | | 0_D3 | PIO_REG_IOCTRL_SD0_D3 | | | - | | | 0x0300_1030 | | - 0 : SDIO0_D[3] (default)| - | | | | | - 1 : CAM_MCLK0 | - | | | | | - 2 : SPI0_CS_X | - | | | | | - 3 : XGPIOA[12] | - | | | | | - 4 : UART3_RX | - | | | | | - 5 : PWM[10] | - | | | | | - 6 : WG1_D1 | - | | | | | - 7 : DBG[5] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 14| SD\ |FMUX_GPIO_REG_IOCTRL\ | 0x0| IO SD0_CD function select:| - | | 0_CD |_SD0_CD | | | - | | |0x0300_1034 | | - 0 : SDIO0_CD (default) | - | | | | | - 3 : XGPIOA[13] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 15| SD | FMUX_GPIO | 0x3| IO SD0_PWR_EN function | - | | 0_PW | _REG_IOCTRL_SD0_PWR_EN | | select : | - | | R_EN | 0x0300_1038 | | | - | | | | | - 0 : SDIO0_PWR_EN | - | | | | | - 3 : XGPIOA[14] (default)| - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 17| SP\ | FMUX_G\ | 0x3| IO SPK_EN function select:| - | | K_EN | PIO_REG_IOCTRL_SPK_EN | | | - | | | 0x0300_103C | | - 3 : XGPIOA[15] (default)| - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 18| UART\| FMUX_GP | 0x0| IO UART0_TX function | - | | 0_TX | IO_REG_IOCTRL_UART0_TX | | select : | - | | | 0x0300_1040 | | | - | | | | | - 0 : UART0_TX (default) | - | | | | | - 1 : CAM_MCLK1 | - | | | | | - 2 : PWM[4] | - | | | | | - 3 : XGPIOA[16] | - | | | | | - 4 : UART1_TX | - | | | | | - 7 : DBG[6] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 19| UART\| FMUX_GP\ | 0x0| IO UART0_RX function | - | | 0_RX | IO_REG_IOCTRL_UART0_RX | | select : | - | | | 0x0300_1044 | | | - | | | | | - 0 : UART0_RX (default) | - | | | | | - 1 : CAM_MCLK0 | - | | | | | - 2 : PWM[5] | - | | | | | - 3 : XGPIOA[17] | - | | | | | - 4 : UART1_RX | - | | | | | - 5 : AUX0 | - | | | | | - 7 : DBG[7] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 20|EMMC\ |FMUX_GPIO_REG_IOCTRL | 0x1| IO EMMC_DAT2 function | - | |_DAT2 |_EMMC_DAT2 | | select : | - | | |0x0300_104C | | | - | | | | | - 0 : EMMC_DAT[2] | - | | | | | - 1 : SPINOR_HOLD_X\ | - | | | | | (default) | - | | | | | - 2 : SPINAND_HOLD | - | | | | | - 3 : XGPIOA[26] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 21| EMMC\| FMUX_GP | 0x1| IO EMMC_CLK function | - | | _CLK | IO_REG_IOCTRL_EMMC_CLK | | select : | - | | | 0x0300_1050 | | | - | | | | | - 0 : EMMC_CLK | - | | | | | - 1 : SPINOR_SCK (default)| - | | | | | - 2 : SPINAND_CLK | - | | | | | - 3 : XGPIOA[22] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 22| EMMC | FMUX_GPI | 0x1| IO EMMC_DAT0 function | - | | _DAT0| O_REG_IOCTRL_EMMC_DAT0 | | select : | - | | | 0x0300_1054 | | | - | | | | | - 0 : EMMC_DAT[0] | - | | | | | - 1 : SPINOR_MOSI(default)| - | | | | | - 2 : SPINAND_MOSI | - | | | | | - 3 : XGPIOA[25] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 23| EMMC | FMUX_GPI | 0x1|IO EMMC_DAT3 function | - | | _DAT3| O_REG_IOCTRL_EMMC_DAT3 | |select : | - | | | 0x0300_1058 | | | - | | | | |- 0 : EMMC_DAT[3] | - | | | | |- 1 : SPINOR_WP_X (default)| - | | | | |- 2 : SPINAND_WP | - | | | | |- 3 : XGPIOA[27] | - | | | | |- Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 24| EMMC | FMUX_GP | 0x1|IO EMMC_CMD function | - | | _CMD | IO_REG_IOCTRL_EMMC_CMD | |select : | - | | | 0x0300_105C | | | - | | | | |- 0 : EMMC_CMD | - | | | | |- 1 : SPINOR_MISO (default)| - | | | | |- 2 : SPINAND_MISO | - | | | | |- 3 : XGPIOA[23] | - | | | | |- Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 25|EMMC | FMUX_GPI | 0x1|IO EMMC_DAT1 function | - | |_DAT1 | O_REG_IOCTRL_EMMC_DAT1 | |select : | - | | | 0x0300_1060 | | | - | | | | |- 0 : EMMC_DAT[1] | - | | | | |- 1 : SPINOR_CS_X (default)| - | | | | |- 2 : SPINAND_CS | - | | | | |- 3 : XGPIOA[24] | - | | | | |- Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 26| JTAG | FMUX_GPIO_R | 0x0| IO JTAG_CPU_TMS function | - | | _CPU | EG_IOCTRL_JTAG_CPU_TMS | | select : | - | | _TMS | 0x0300_1064 | | | - | | _TMS | | | - 0 : CR_4WTMS (default) | - | | | | | - 1 : CAM_MCLK0 | - | | | | | - 2 : PWM[7] | - | | | | | - 3 : XGPIOA[19] | - | | | | | - 4 : UART1_RTS | - | | | | | - 5 : AUX0 | - | | | | | - 6 : UART1_TX | - | | | | | - 7 : VO_D[28] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 27| JTAG | FMUX_GPIO_R | 0x0| IO JTAG_CPU_TCK function | - | | _CPU | EG_IOCTRL_JTAG_CPU_TCK | | select : | - | | _TCK | 0x0300_1068 | | | - | | _TCK | | | - 0 : CR_4WTCK (default) | - | | | | | - 1 : CAM_MCLK1 | - | | | | | - 2 : PWM[6] | - | | | | | - 3 : XGPIOA[18] | - | | | | | - 4 : UART1_CTS | - | | | | | - 5 : AUX1 | - | | | | | - 6 : UART1_RX | - | | | | | - 7 : VO_D[29] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 28| IIC0\| FMUX_GP\ | 0x0| IO IIC0_SCL function | - | | _SCL | IO_REG_IOCTRL_IIC0_SCL | | select : | - | | | 0x0300_1070 | | | - | | | | | - 0 : CR_4WTDI (default) | - | | | | | - 1 : UART1_TX | - | | | | | - 2 : UART2_TX | - | | | | | - 3 : XGPIOA[28] | - | | | | | - 5 : WG0_D0 | - | | | | | - 7 : DBG[10] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 29| IIC0\| FMUX_GP\ | 0x0| IO IIC0_SDA function | - | | _SDA | IO_REG_IOCTRL_IIC0_SDA | | select : | - | | | 0x0300_1074 | | | - | | | | | - 0 : CR_4WTDO (default) | - | | | | | - 1 : UART1_RX | - | | | | | - 2 : UART2_RX | - | | | | | - 3 : XGPIOA[29] | - | | | | | - 5 : WG0_D1 | - | | | | | - 6 : WG1_D0 | - | | | | | - 7 : DBG[11] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 30| AUX0 | FMU\ | 0x3| IO AUX0 function select : | - | | | X_GPIO_REG_IOCTRL_AUX0 | | | - | | | 0x0300_1078 | | - 0 : AUX0 | - | | | | | - 3 : XGPIOA[30] (default)| - | | | | | - 4 : IIS1_MCLK | - | | | | | - 5 : VO_D[31] | - | | | | | - 6 : WG1_D1 | - | | | | | - 7 : DBG[12] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 38|PWR | FMUX_GPIO_R | 0x0| IO PWR_VBAT_DET function | - | |_VBAT | EG_IOCTRL_PWR_VBAT_DET | | select : | - | |_DET | | | | - | | | 0x0300_107C | | - 0 : PWR_VBAT_DET | - | | | | | (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 39|PWR\ | FMUX_GP\ | 0x0| IO PWR_RSTN function | - | |_RSTN | IO_REG_IOCTRL_PWR_RSTN | | select : | - | | | | | | - | | | 0x0300_1080 | | - 0 : PWR_RSTN (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 40|PWR\ | FMUX_GP\ | 0x0| IO PWR_SEQ1 function | - | |_SEQ1 | IO_REG_IOCTRL_PWR_SEQ1 | | select : | - | | | | | | - | | | 0x0300_1084 | | - 0 : PWR_SEQ1 (default) | - | | | | | - 3 : PWR_GPIO[3] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 41|PWR\ | FMUX_GP\ | 0x0| IO PWR_SEQ2 function | - | |_SEQ2 | IO_REG_IOCTRL_PWR_SEQ2 | | select : | - | | | | | | - | | | 0x0300_1088 | | - 0 : PWR_SEQ2 (default) | - | | | | | - 3 : PWR_GPIO[4] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 43|PWR |FMUX_GPIO_REG_IOCTRL | 0x0| IO PWR_WAKEUP0 function | - | |_WAK |_PWR_WAKEUP0 | | select : | - | |EUP0 |0x0300_1090 | | | - | | | | | - 0 : PWR_WAKEUP0(default)| - | | | | | - 1 : PWR_IR0 | - | | | | | - 2 : PWR_UART0_TX | - | | | | | - 3 : PWR_GPIO[6] | - | | | | | - 4 : UART1_TX | - | | | | | - 5 : IIC4_SCL | - | | | | | - 6 : EPHY_LNK_LED | - | | | | | - 7 : WG2_D0 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 44| PWR\ |FMUX_GPIO | 0x0| IO PWR_BUTTON1 function | - | | _BUT |_REG_IOCTRL_PWR_BUTTON1 | | select : | - | | TON1 |0x0300_1098 | | | - | | | | | - 0 : PWR_BUTTON1(default)| - | | | | | - 3 : PWR_GPIO[8] | - | | | | | - 4 : UART1_RX | - | | | | | - 5 : IIC4_SDA | - | | | | | - 6 : EPHY_SPD_LED | - | | | | | - 7 : WG2_D1 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 45| XTAL\| FMUX_GP\ | 0x0| IO XTAL_XIN function | - | | _XIN | IO_REG_IOCTRL_XTAL_XIN | | select : | - | | | | | | - | | | 0x0300_10A0 | | - 0 : PWR_XTAL_CLKIN\ | - | | | | | (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 47| PWR\ | FMUX_GPI | 0x0| IO PWR_GPIO0 function | - | | _\ | O_REG_IOCTRL_PWR_GPIO0 | | select : | - | | GPIO0| 0x0300_10A4 | | | - | | | | | - 0 : PWR_GPIO[0](default)| - | | | | | - 1 : UART2_TX | - | | | | | - 2 : PWR_UART0_RX | - | | | | | - 4 : PWM[8] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 48| PWR\ | FMUX_GPI | 0x0| IO PWR_GPIO1 function | - | | _\ | O_REG_IOCTRL_PWR_GPIO1 | | select : | - | | GPIO1| 0x0300_10A8 | | | - | | | | | - 0 : PWR_GPIO[1](default)| - | | | | | - 1 : UART2_RX | - | | | | | - 3 : EPHY_LNK_LED | - | | | | | - 4 : PWM[9] | - | | | | | - 5 : PWR_IIC_SCL | - | | | | | - 6 : IIC2_SCL | - | | | | | - 7 : CR_SDA0 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 49| PWR\ | FMUX_GPI | 0x0| IO PWR_GPIO2 function | - | | _\ | O_REG_IOCTRL_PWR_GPIO2 | | select : | - | | GPIO2| 0x0300_10AC | | | - | | | | | - 0 : PWR_GPIO[2](default)| - | | | | | - 2 : PWR_SECTICK | - | | | | | - 3 : EPHY_SPD_LED | - | | | | | - 4 : PWM[10] | - | | | | | - 5 : PWR_IIC_SDA | - | | | | | - 6 : IIC2_SDA | - | | | | | - 7 : CR_2WTCK | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 51| SD1\ |FMUX\ | 0x6| IO SD1_D3 function select | - | | _D3 |_GPIO_REG_IOCTRL_SD1_D3 | | : | - | | | | | | - | | |0x0300_10D0 | | - 0 : PWR_SD1_D3_VO32 | - | | | | | - 1 : SPI2_CS_X | - | | | | | - 2 : IIC1_SCL | - | | | | | - 3 : PWR_GPIO[18] | - | | | | | - 4 : CAM_MCLK0 | - | | | | | - 5 : UART3_CTS | - | | | | | - 6 : PWR_SPINOR1_CS_X | - | | | | | - (default) | - | | | | | - 7 : PWM[4] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 52| SD1\ |FMUX\ | 0x6| IO SD1_D2 function select | - | | _D2 |_GPIO_REG_IOCTRL_SD1_D2 | | : | - | | | | | | - | | |0x0300_10D4 | | - 0 : PWR_SD1_D2_VO33 | - | | | | | - 1 : IIC1_SCL | - | | | | | - 2 : UART2_TX | - | | | | | - 3 : PWR_GPIO[19] | - | | | | | - 4 : CAM_MCLK0 | - | | | | | - 5 : UART3_TX | - | | | | | - 6 : PWR_SPINOR1_HOLD_X | - | | | | | - (default) | - | | | | | - 7 : PWM[5] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 53| SD1\ |FMUX\ | 0x6| IO SD1_D1 function select | - | | _D1 |_GPIO_REG_IOCTRL_SD1_D1 | | : | - | | | | | | - | | |0x0300_10D8 | | - 0 : PWR_SD1_D1_VO34 | - | | | | | - 1 : IIC1_SDA | - | | | | | - 2 : UART2_RX | - | | | | | - 3 : PWR_GPIO[20] | - | | | | | - 4 : CAM_MCLK1 | - | | | | | - 5 : UART3_RX | - | | | | | - 6 : PWR_SPINOR1_WP_X | - | | | | | - (default) | - | | | | | - 7 : PWM[6] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 54| SD1\ |FMUX\ | 0x6| IO SD1_D0 function select | - | | _D0 |_GPIO_REG_IOCTRL_SD1_D0 | | : | - | | | | | | - | | |0x0300_10DC | | - 0 : PWR_SD1_D0_VO35 | - | | | | | - 1 : SPI2_SDI | - | | | | | - 2 : IIC1_SDA | - | | | | | - 3 : PWR_GPIO[21] | - | | | | | - 4 : CAM_MCLK1 | - | | | | | - 5 : UART3_RTS | - | | | | | - 6 : PWR_SPINOR1_MISO | - | | | | | - (default) | - | | | | | - 7 : PWM[7] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 55| SD1\ | FMUX_G\ | 0x6| IO SD1_CMD function | - | | _CMD | PIO_REG_IOCTRL_SD1_CMD | | select : | - | | | | | | - | | | 0x0300_10E0 | | - 0 : PWR_SD1_CMD_VO36 | - | | | | | - 1 : SPI2_SDO | - | | | | | - 2 : IIC3_SCL | - | | | | | - 3 : PWR_GPIO[22] | - | | | | | - 4 : CAM_VS0 | - | | | | | - 5 : EPHY_LNK_LED | - | | | | | - 6 : PWR_SPINOR1_MOSI | - | | | | | - (default) | - | | | | | - 7 : PWM[8] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 56|SD1\ | FMUX_G\ | 0x6| IO SD1_CLK function | - | |_CLK | PIO_REG_IOCTRL_SD1_CLK | | select : | - | | | | | | - | | | 0x0300_10E4 | | - 0 : PWR_SD1_CLK_VO37 | - | | | | | - 1 : SPI2_SCK | - | | | | | - 2 : IIC3_SDA | - | | | | | - 3 : PWR_GPIO[23] | - | | | | | - 4 : CAM_HS0 | - | | | | | - 5 : EPHY_SPD_LED | - | | | | | - 6 : PWR_SPINOR1_SCK | - | | | | | - (default) | - | | | | | - 7 : PWM[9] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 58|PWM0 | FMUX_GPI | 0x3| IO PWM0_BUCK function | - | |_BUCK | O_REG_IOCTRL_PWM0_BUCK | | select : | - | | | | | | - | | | 0x0300_10EC | | - 0 : PWM[0] | - | | | | | - 3 : XGPIOB[0] (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 59| ADC1 | FMU\ | 0x3| IO ADC1 function select : | - | | | X_GPIO_REG_IOCTRL_ADC1 | | | - | | | | | - 3 : XGPIOB[3] (default) | - | | | 0x0300_10F8 | | - 4 : KEY_COL2 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 60|USB | FMUX_GPIO_R | 0x0| IO USB_VBUS_DET function | - | |_VBUS | EG_IOCTRL_USB_VBUS_DET | | select : | - | |_DET | | | | - | | | 0x0300_1108 | | - 0 : USB_VBUS_DET | - | | | | | - (default) | - | | | | | - 3 : XGPIOB[6] | - | | | | | - 4 : CAM_MCLK0 | - | | | | | - 5 : CAM_MCLK1 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 62|PAD |FMUX_GPIO | 0x3| IO PAD_ETH_TXP function | - | |_ETH |_REG_IOCTRL_PAD_ETH_TXP | | select : | - | |_TXP | | | | - | |___ |0x0300_1124 | | - 1 : UART3_RX | - | |EPHY | | | - 2 : IIC1_SCL | - | |_RXN | | | - 3 : XGPIOB[25] (default)| - | | | | | - 4 : PWM[13] | - | | | | | - 5 : CAM_MCLK0 | - | | | | | - 6 : SPI1_SDO | - | | | | | - 7 : IIS2_LRCK | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 63|PAD |FMUX_GPIO | 0x3| IO PAD_ETH_TXM function | - | |_ETH |_REG_IOCTRL_PAD_ETH_TXM | | select : | - | |_TXM | | | | - | |___ |0x0300_1128 | | - 1 : UART3_RTS | - | |EPHY | | | - 2 : IIC1_SDA | - | |_RXP | | | - 3 : XGPIOB[24] (default)| - | | | | | - 4 : PWM[12] | - | | | | | - 5 : CAM_MCLK1 | - | | | | | - 6 : SPI1_SDI | - | | | | | - 7 : IIS2_BCLK | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 64|PAD |FMUX_GPIO | 0x3| IO PAD_ETH_RXP function | - | |_ETH |_REG_IOCTRL_PAD_ETH_RXP | | select : | - | |_RXP | | | | - | |___ |0x0300_112C | | - 1 : UART3_TX | - | |EPHY | | | - 2 : CAM_MCLK1 | - | |_TXN | | | - 3 : XGPIOB[27] (default)| - | | | | | - 4 : PWM[15] | - | | | | | - 5 : CAM_HS0 | - | | | | | - 6 : SPI1_SCK | - | | | | | - 7 : IIS2_DO | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 65|PAD | FMUX_GPIO | 0x3| IO PAD_ETH_RXM function | - | |_ETH | _REG_IOCTRL_PAD_ETH_RXM| | select : | - | |_RXM | | | | - | |___ | 0x0300_1130 | | - 1 : UART3_CTS | - | |EPHY | | | - 2 : CAM_MCLK0 | - | |_TXP | | | - 3 : XGPIOB[26] (default)| - | | | | | - 4 : PWM[14] | - | | | | | - 5 : CAM_VS0 | - | | | | | - 6 : SPI1_CS_X | - | | | | | - 7 : IIS2_DI | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 72|PAD | FMUX_GPIO_R | 0x0| IO PAD_MIPIRX4N function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX4N | | select : | - | |RX4N | 0x0300_116C | | | - | | | | | - 0 : CR_SCL0 (default) | - | | | | | - 1 : VI0_CLK | - | | | | | - 2 : VI1_D[13] | - | | | | | - 3 : XGPIOC[2] | - | | | | | - 4 : IIC1_SDA | - | | | | | - 5 : CAM_MCLK0 | - | | | | | - 6 : KEY_ROW0 | - | | | | | - 7 : MUX_SPI1_SCK | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 73|PAD | FMUX_GPIO_R | 0x0| IO PAD_MIPIRX4P function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX4P | | select : | - | |RX4P | 0x0300_1170 | | | - | | | | | - 0 : CR_SDA0 (default) | - | | | | | - 1 : VI0_D[0] | - | | | | | - 2 : VI1_D[14] | - | | | | | - 3 : XGPIOC[3] | - | | | | | - 4 : IIC1_SCL | - | | | | | - 5 : CAM_MCLK1 | - | | | | | - 6 : KEY_ROW1 | - | | | | | - 7 : MUX_SPI1_CS | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 74|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX3N function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX3N | | select : | - | |RX3N | 0x0300_1174 | | | - | | | | | - 0 : CR_2WTMS | - | | | | | - 1 : VI0_D[1] | - | | | | | - 2 : VI1_D[15] | - | | | | | - 3 : XGPIOC[4] (default) | - | | | | | - 4 : CAM_MCLK0 | - | | | | | - 7 : MUX_SPI1_MISO | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 75|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX3P function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX3P | | select : | - | |RX3P | 0x0300_1178 | | | - | | | | | - 0 : CR_2WTCK | - | | | | | - 1 : VI0_D[2] | - | | | | | - 2 : VI1_D[16] | - | | | | | - 3 : XGPIOC[5] (default) | - | | | | | - 7 : MUX_SPI1_MOSI | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 76|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX2N function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX2N | | select : | - | |RX2N | 0x0300_117C | | | - | | | | | - 1 : VI0_D[3] | - | | | | | - 2 : VO_D[10] | - | | | | | - 3 : XGPIOC[6] (default) | - | | | | | - 4 : VI1_D[17] | - | | | | | - 5 : IIC4_SCL | - | | | | | - 7 : DBG[6] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 77|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX2P function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX2P | | select : | - | |RX2P | 0x0300_1180 | | | - | | | | | - 1 : VI0_D[4] | - | | | | | - 2 : VO_D[9] | - | | | | | - 3 : XGPIOC[7] (default) | - | | | | | - 4 : VI1_D[18] | - | | | | | - 5 : IIC4_SDA | - | | | | | - 7 : DBG[7] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 78|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX1N function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX1N | | select : | - | |RX1N | 0x0300_1184 | | | - | | | | | - 1 : VI0_D[5] | - | | | | | - 2 : VO_D[8] | - | | | | | - 3 : XGPIOC[8] (default) | - | | | | | - 6 : KEY_ROW3 | - | | | | | - 7 : DBG[8] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 79|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX1P function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX1P | | select : | - | |RX1P | 0x0300_1188 | | | - | | | | | - 1 : VI0_D[6] | - | | | | | - 2 : VO_D[7] | - | | | | | - 3 : XGPIOC[9] (default) | - | | | | | - 4 : IIC1_SDA | - | | | | | - 6 : KEY_ROW2 | - | | | | | - 7 : DBG[9] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 80|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX0N function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX0N | | select : | - | |RX0N | 0x0300_118C | | | - | | | | | - 1 : VI0_D[7] | - | | | | | - 2 : VO_D[6] | - | | | | | - 3 : XGPIOC[10] (default)| - | | | | | - 4 : IIC1_SCL | - | | | | | - 5 : CAM_MCLK1 | - | | | | | - 7 : DBG[10] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 81|PAD | FMUX_GPIO_R | 0x3| IO PAD_MIPIRX0P function | - | |_MIPI | EG_IOCTRL_PAD_MIPIRX0P | | select : | - | |RX0P | 0x0300_1190 | | | - | | | | | - 1 : VI0_D[8] | - | | | | | - 2 : VO_D[5] | - | | | | | - 3 : XGPIOC[11] (default)| - | | | | | - 4 : CAM_MCLK0 | - | | | | | - 7 : DBG[11] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 83|PAD | FMUX_GPIO_RE | 0x3| IO PAD_MIPI_TXM2 function | - | |_MIPI | G_IOCTRL_PAD_MIPI_TXM2 | | select : | - | |_TXM2 | 0x0300_11A4 | | | - | | | | | - 0 : CR_SDA0 | - | | | | | - 1 : VI0_D[13] | - | | | | | - 2 : VO_D[0] | - | | | | | - 3 : XGPIOC[16] (default)| - | | | | | - 4 : IIC1_SDA | - | | | | | - 5 : PWM[8] | - | | | | | - 6 : SPI0_SCK | - | | | | | - 7 : SD1_D2 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 84|PAD | FMUX_GPIO_RE | 0x3| IO PAD_MIPI_TXP2 function | - | |_MIPI | G_IOCTRL_PAD_MIPI_TXP2 | | select : | - | |_TXP2 | 0x0300_11A8 | | | - | | | | | - 0 : CR_SCL0 | - | | | | | - 1 : VI0_D[14] | - | | | | | - 2 : VO_CLK0 | - | | | | | - 3 : XGPIOC[17] (default)| - | | | | | - 4 : IIC1_SCL | - | | | | | - 5 : PWM[9] | - | | | | | - 6 : SPI0_CS_X | - | | | | | - 7 : SD1_D3 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 85|PAD | FMUX_GPIO_RE | 0x3| IO PAD_MIPI_TXM1 function | - | |_MIPI | G_IOCTRL_PAD_MIPI_TXM1 | | select : | - | |_TXM1 | 0x0300_11AC | | | - | | | | | - 0 : CR_2WTMS | - | | | | | - 1 : VI0_D[11] | - | | | | | - 2 : VO_D[2] | - | | | | | - 3 : XGPIOC[14] (default)| - | | | | | - 4 : IIC2_SDA | - | | | | | - 5 : PWM[10] | - | | | | | - 6 : SPI0_SDO | - | | | | | - 7 : DBG[14] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 86|PAD | FMUX_GPIO_RE | 0x3| IO PAD_MIPI_TXP1 function | - | |_MIPI | G_IOCTRL_PAD_MIPI_TXP1 | | select : | - | |_TXP1 | 0x0300_11B0 | | | - | | | | | - 0 : CR_2WTCK | - | | | | | - 1 : VI0_D[12] | - | | | | | - 2 : VO_D[1] | - | | | | | - 3 : XGPIOC[15] (default)| - | | | | | - 4 : IIC2_SCL | - | | | | | - 5 : PWM[11] | - | | | | | - 6 : SPI0_SDI | - | | | | | - 7 : DBG[15] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 87|PAD | FMUX_GPIO_RE | 0x3| IO PAD_MIPI_TXM0 function | - | |_MIPI | G_IOCTRL_PAD_MIPI_TXM0 | | select : | - | |_TXM0 | 0x0300_11B4 | | | - | | | | | - 1 : VI0_D[9] | - | | | | | - 2 : VO_D[4] | - | | | | | - 3 : XGPIOC[12] (default)| - | | | | | - 4 : CAM_MCLK1 | - | | | | | - 5 : PWM[14] | - | | | | | - 6 : CAM_VS0 | - | | | | | - 7 : DBG[12] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 88|PAD | FMUX_GPIO_RE | 0x3| IO PAD_MIPI_TXP0 function | - | |_MIPI | G_IOCTRL_PAD_MIPI_TXP0 | | select : | - | |_TXP0 | 0x0300_11B8 | | | - | | | | | - 1 : VI0_D[10] | - | | | | | - 2 : VO_D[3] | - | | | | | - 3 : XGPIOC[13] (default)| - | | | | | - 4 : CAM_MCLK0 | - | | | | | - 5 : PWM[15] | - | | | | | - 6 : CAM_HS0 | - | | | | | - 7 : DBG[13] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 2 |PAD | FMUX_GPIO_REG_I | 0x3| IO PAD_AUD_AINL_MIC | - | |_AUD | OCTRL_PAD_AUD_AINL_MIC | | function select : | - | |_AINL | 0x0300_11BC | | | - | |_MIC | | | - 3 : XGPIOC[23] (default)| - | | | | | - 4 : IIS1_BCLK | - | | | | | - 5 : IIS2_BCLK | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 4 |PAD | FMUX_GPIO_RE | 0x3| IO PAD_AUD_AOUTR function | - | |_AUD | G_IOCTRL_PAD_AUD_AOUTR | | select : | - | |_AOUTR| 0x0300_11C8 | | | - | | | | | - 3 : XGPIOC[24] (default)| - | | | | | - 4 : IIS1_DI | - | | | | | - 5 : IIS2_DO | - | | | | | - 6 : IIS1_DO | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 67| GPIO | FMUX_GP | 0x3| IO GPIO_RTX function | - | | _RTX | IO_REG_IOCTRL_GPIO_RTX | | select : | - | | ___ | 0x0300_11CC | | | - | | EPHY | | | - 3 : XGPIOB[23] (default)| - | | _RTX | | | - 4 : PWM[1] | - | | | | | - 5 : CAM_MCLK0 | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | 35| GPIO | FMUX_G\ | 0x3| IO GPIO_ZQ function | - | | _ZQ | PIO_REG_IOCTRL_GPIO_ZQ | | select : | - | | ___ | 0x0300_11D0 | | | - | | PAD | | | - 3 : PWR_GPIO[24]\ | - | | _ZQ | | | (default) | - | | | | | - 4 : PWM[2] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|PKG | FMUX_GPI | 0x0| IO PKG_TYPE0 function | - | N\|_TYPE0| O_REG_IOCTRL_PKG_TYPE0 | | select : | - | /\| | 0x0300_1104 | | | - | A | | | | - 0 : PKG_TYPE0 (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|PKG | FMUX_GPI | 0x0| IO PKG_TYPE1 function | - | N\|_TYPE1| O_REG_IOCTRL_PKG_TYPE1 | | select : | - | /\| | 0x0300_110C | | | - | A | | | | - 0 : PKG_TYPE1 (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|PKG | FMUX_GPI | 0x0| IO PKG_TYPE2 function | - | N\|_TYPE2| O_REG_IOCTRL_PKG_TYPE2 | | select : | - | /\| | 0x0300_1110 | | | - | A | | | | - 0 : PKG_TYPE2 (default) | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|MUX | FMUX_GPIO_RE | 0x3| IO MUX_SPI1_MISO function | - | N\|_SPI1 | G_IOCTRL_MUX_SPI1_MISO | | select : | - | /\|_MISO | 0x0300_1114 | | | - | A | | | | - 1 : UART3_RTS | - | | | | | - 2 : IIC1_SDA | - | | | | | - 3 : XGPIOB[8] (default) | - | | | | | - 4 : PWM[9] | - | | | | | - 5 : KEY_COL1 | - | | | | | - 6 : SPI1_SDI | - | | | | | - 7 : DBG[14] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|MUX | FMUX_GPIO_RE | 0x3| IO MUX_SPI1_MOSI function | - | N\|_SPI1 | G_IOCTRL_MUX_SPI1_MOSI | | select : | - | /\|_MOSI | 0x0300_1118 | | | - | A | | | | - 1 : UART3_RX | - | | | | | - 2 : IIC1_SCL | - | | | | | - 3 : XGPIOB[7] (default) | - | | | | | - 4 : PWM[8] | - | | | | | - 5 : KEY_COL0 | - | | | | | - 6 : SPI1_SDO | - | | | | | - 7 : DBG[13] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|MUX | FMUX_GPIO | 0x3| IO MUX_SPI1_CS function | - | N\|_SPI1 | _REG_IOCTRL_MUX_SPI1_CS| | select : | - | /\|_CS | 0x0300_111C | | | - | A | | | | - 1 : UART3_CTS | - | | | | | - 2 : CAM_MCLK0 | - | | | | | - 3 : XGPIOB[10] (default)| - | | | | | - 4 : PWM[11] | - | | | | | - 5 : KEY_ROW3 | - | | | | | - 6 : SPI1_CS_X | - | | | | | - 7 : DBG[16] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ - | #\|MUX | FMUX_GPIO_R | 0x3| IO MUX_SPI1_SCK function | - | N\|_SPI1 | EG_IOCTRL_MUX_SPI1_SCK | | select : | - | /\|_SCK | 0x0300_1120 | | | - | A | | | | - 1 : UART3_TX | - | | | | | - 2 : CAM_MCLK1 | - | | | | | - 3 : XGPIOB[9] (default) | - | | | | | - 4 : PWM[10] | - | | | | | - 5 : KEY_ROW2 | - | | | | | - 6 : SPI1_SCK | - | | | | | - 7 : DBG[15] | - | | | | | - Others : Reserved | - +---+------+------------------------+----+---------------------------+ diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst deleted file mode 100644 index fe01ef6..0000000 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst +++ /dev/null @@ -1,2471 +0,0 @@ -ADC -^^^ - -.. only:: sg2002 - - .. _table_inf_signal_pin_fmux_adc_sg2002: - .. table:: ADC - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (ADC1) | I | ADC1 | 0 | FMUX\ | - | | | | | _GPIO_REG_IOCTRL_ADC1 | - | | | | | 0x0300_10F8 | - +---------+---------+---------+--------+-----------------------+ - -.. only:: sg2000 - - .. _table_inf_signal_pin_fmux_adc_sg2000: - .. table:: ADC - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (ADC1) | I | ADC1 | 0 | FMUX\ | - | | | | | _GPIO_REG_IOCTRL_ADC1 | - | | | | | 0x0300_10F8 | - +---------+---------+---------+--------+-----------------------+ - | (ADC2) | I | ADC2 | 0 | FMUX\ | - | | | | | _GPIO_REG_IOCTRL_ADC1 | - | | | | | 0x0300_10F8 | - +---------+---------+---------+--------+-----------------------+ - | (ADC3) | I | ADC3 | 0 | FMUX\ | - | | | | | _GPIO_REG_IOCTRL_ADC1 | - | | | | | 0x0300_10F8 | - +---------+---------+---------+--------+-----------------------+ - -No-die domain ADC -^^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_nodia_domain_adc: -.. table:: No-die domain ADC - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR\ | I | PW | 0 | FMUX_GPIO | - | _GPIO[2\| | R_GPIO2 | | _REG_IOCTRL_PWR_GPIO2 | - | ](PWRSA | | | | 0x0300_10AC | - | R.VIN1) | | | | | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I | PW | 0 | FMUX_GPIO | - | _GPIO[1\| | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | ](PWRSA | | | | 0x0300_10A8 | - | R1.VIN2)| | | | | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I | PWR_V | 0 | FMUX_GPIO_RE | - | _VBAT_DE| | BAT_DET | | G_IOCTRL_PWR_VBAT_DET | - | T(PWRSA | | | | 0x0300_107C | - | R.VIN3) | | | | | - +---------+---------+---------+--------+-----------------------+ - - -Audio -^^^^^ - -.. only:: sg2002 - - .. _table_inf_signal_pin_fmux_audio_sg2002: - .. table:: Audio - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (PAD\ | I | PA | 0 | FMUX_GPIO_REG_IO | - | _AUD_AI | | D_AUD_A | | CTRL_PAD_AUD_AINL_MIC | - | NL_MIC) | | INL_MIC | | 0x0300_11BC | - +---------+---------+---------+--------+-----------------------+ - | (\ | O | PAD_AU | 0 | FMUX_GPIO_REG_IO | - | PAD_AUD\| | D_AOUTR | | CTRL_PAD_AUD_AOUTR | - | _AOUTR) | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - -.. only:: sg2000 - - .. _table_inf_signal_pin_fmux_audio_sg2000: - .. table:: Audio - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (PAD\ | I | PA | 0 | FMUX_GPIO_REG_IO | - | _AUD_AI | | D_AUD_A | | CTRL_PAD_AUD_AINL_MIC | - | NL_MIC) | | INL_MIC | | 0x0300_11BC | - +---------+---------+---------+--------+-----------------------+ - | (PAD\ | I | PA | 0 | FMUX_GPIO_REG_IO | - | _AUD_AI | | D_AUD_A | | CTRL_PAD_AUD_AINR_MIC | - | NR_MIC) | | INR_MIC | | 0x0300_11BC | - +---------+---------+---------+--------+-----------------------+ - | (\ | O | PAD_AU | 0 | FMUX_GPIO_REG_IO | - | PAD_AUD\| | D_AOUTL | | CTRL_PAD_AUD_AOUTL | - | _AOUTL) | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - | (\ | O | PAD_AU | 0 | FMUX_GPIO_REG_IO | - | PAD_AUD\| | D_AOUTR | | CTRL_PAD_AUD_AOUTR | - | _AOUTR) | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - - -Ethernet -^^^^^^^^ - -.. _table_inf_signal_pin_fmux_ethernet: -.. table:: Ethernet - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (PAD_E\ | I/O | PAD | 0 | FMUX_GPIO_R | - | TH_RXM) | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | (PAD_E\ | I/O | PAD | 0 | FMUX_GPIO_R | - | TH_RXP) | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | (PAD_E\ | I/O | PAD | 0 | FMUX_GPIO_R | - | TH_TXM) | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | (PAD_E\ | I/O | PAD | 0 | FMUX_GPIO_R | - | TH_TXP) | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | SD0_CLK | 6 | FMUX_GP | - | _LNK_LED| | | | IO_REG_IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | PWR | 6 | FMUX_GPIO_R | - | _LNK_LED| | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | SD1_CMD | 5 | FMUX_GP | - | _LNK_LED| | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | PW | 3 | FMUX_GPIO | - | _LNK_LED| | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | SD0_CMD | 6 | FMUX_GP | - | _SPD_LED| | | | IO_REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | PWR | 6 | FMUX_GPIO_R | - | _SPD_LED| | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | SD1_CLK | 5 | FMUX_GP | - | _SPD_LED| | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | EPHY\ | O | PW | 3 | FMUX_GPIO | - | _SPD_LED| | R_GPIO2 | | _REG_IOCTRL_PWR_GPIO2 | - | | | | | 0x0300_10AC | - +---------+---------+---------+--------+-----------------------+ - -DSI/LVDS -^^^^^^^^ - -.. _table_inf_signal_pin_fmux_dsi_lvds: -.. table:: DSI/LVDS - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (\ | I/O | PAD_MI | 0 | FMUX_GPIO_REG_IO | - | PAD_MIP\| | PI_TXM0 | | CTRL_PAD_MIPI_TXM0 | - | I_TXM0) | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | (\ | I/O | PAD_MI | 0 | FMUX_GPIO_REG_IO | - | PAD_MIP\| | PI_TXP0 | | CTRL_PAD_MIPI_TXP0 | - | I_TXP0) | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | (\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | PAD_MIP\| | PI_TXM1 | | CTRL_PAD_MIPI_TXM1 | - | I_TXM1) | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | (\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | PAD_MIP\| | PI_TXP1 | | CTRL_PAD_MIPI_TXP1 | - | I_TXP1) | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | (\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | PAD_MIP\| | PI_TXM2 | | CTRL_PAD_MIPI_TXM2 | - | I_TXM2) | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | (\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | PAD_MIP\| | PI_TXP2 | | CTRL_PAD_MIPI_TXP2 | - | I_TXP2) | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - -CSI/sLVDS/HiSPI -^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_csi: -.. table:: CSI/sLVDS/HiSPI - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | (PAD_MI\| I/O | PAD_M | 0 | FMUX_GPIO_RE | - | PIRX0N) | | IPIRX0N | | G_IOCTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 0 | FMUX_GPIO_RE | - | PIRX0P) | | IPIRX0P | | G_IOCTRL_PAD_MIPIRX0P | - | | | | | 0x0300_1190 | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 0 | FMUX_GPIO_RE | - | PIRX1N) | | IPIRX1N | | G_IOCTRL_PAD_MIPIRX1N | - | | | | | 0x0300_1184 | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 0 | FMUX_GPIO_RE | - | PIRX1P) | | IPIRX1P | | G_IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 0 | FMUX_GPIO_RE | - | PIRX2N) | | IPIRX2N | | G_IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 0 | FMUX_GPIO_RE | - | PIRX2P) | | IPIRX2P | | G_IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIRX3N) | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIRX3P) | | IPIRX3P | | G_IOCTRL_PAD_MIPIRX3P | - | | | | | 0x0300_1178 | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIRX4N) | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | (PAD_MI\| I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIRX4P) | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - -Aux clockout -^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_aux_clockout: -.. table:: Aux clockout - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | AUX0 | O | AUX0 | 0 | FMUX | - | | | | | _GPIO_REG_IOCTRL_AUX0 | - | | | | | 0x0300_1078 | - +---------+---------+---------+--------+-----------------------+ - | AUX0 | O | SD0_D1 | 2 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | AUX0 | O | U | 5 | FMUX_GPI | - | | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | AUX0 | O | JTAG | 5 | FMUX_GPIO_RE | - | | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | AUX1 | O | SD0_D2 | 2 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | AUX1 | O | U | 5 | FMUX_GPI | - | | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | AUX1 | O | JTAG | 5 | FMUX_GPIO_RE | - | | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - - -Camera Interface -^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_camdra: -.. table:: Camera Interface - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | CAM_HS0 | O | SD1_CLK | 4 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | CAM_HS0 | O | PAD_MI | 6 | FMUX_GPIO_REG | - | | | PI_TXP0 | | _IOCTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | CAM_HS0 | O | PAD | 5 | FMUX_GPIO_R | - | | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_MI | 4 | FMUX_GPIO_REG | - | M_MCLK0 | | PI_TXP0 | | _IOCTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | SD0_D3 | 1 | FMUX_G | - | M_MCLK0 | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | U | 1 | FMUX_GPI | - | M_MCLK0 | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | JTAG | 1 | FMUX_GPIO_RE | - | M_MCLK0 | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | SD1_D3 | 4 | FMUX_G | - | M_MCLK0 | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | SD1_D2 | 4 | FMUX_G | - | M_MCLK0 | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | USB_V | 4 | FMUX_GPIO_RE | - | M_MCLK0 | | BUS_DET | | G_IOCTRL_USB_VBUS_DET | - | | | | | 0x0300_1108 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_M | 4 | FMUX_GPIO_RE | - | M_MCLK0 | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_M | 4 | FMUX_GPIO_RE | - | M_MCLK0 | | IPIRX0P | | G_IOCTRL_PAD_MIPIRX0P | - | | | | | 0x0300_1190 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | MUX | 2 | FMUX_GPIO_R | - | M_MCLK0 | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD | 2 | FMUX_GPIO_R | - | M_MCLK0 | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD | 5 | FMUX_GPIO_R | - | M_MCLK0 | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_M | 5 | FMUX_GPIO_RE | - | M_MCLK0 | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | GPIO_RT | 5 | FMUX_GPI | - | M_MCLK0 | | X\_\__E | | O_REG_IOCTRL_GPIO_RTX | - | | | PHY_RTX | | 0x0300_11CC | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | SD1_D1 | 4 | FMUX_G | - | M_MCLK1 | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | SD1_D0 | 4 | FMUX_G | - | M_MCLK1 | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_MI | 4 | FMUX_GPIO_REG | - | M_MCLK1 | | PI_TXM0 | | _IOCTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | MUX_S | 2 | FMUX_GPIO_RE | - | M_MCLK1 | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD | 2 | FMUX_GPIO_R | - | M_MCLK1 | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | USB_V | 5 | FMUX_GPIO_RE | - | M_MCLK1 | | BUS_DET | | G_IOCTRL_USB_VBUS_DET | - | | | | | 0x0300_1108 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD | 5 | FMUX_GPIO_R | - | M_MCLK1 | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_M | 5 | FMUX_GPIO_RE | - | M_MCLK1 | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | PAD_M | 5 | FMUX_GPIO_RE | - | M_MCLK1 | | IPIRX0N | | G_IOCTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | SD0_D0 | 1 | FMUX_G | - | M_MCLK1 | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | U | 1 | FMUX_GPI | - | M_MCLK1 | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | CA\ | O | JTAG | 1 | FMUX_GPIO_RE | - | M_MCLK1 | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | CAM_VS0 | O | SD1_CMD | 4 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | CAM_VS0 | O | PAD_MI | 6 | FMUX_GPIO_REG_IO | - | | | PI_TXM0 | | CTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | CAM_VS0 | O | PAD | 5 | FMUX_GPIO_R | - | | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - -Parallel Video Out -^^^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_parallel_videoout: -.. table:: Parallel Video Out - :widths: 1 1 2 1 5 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | VO_CLK0 | O | PAD_MI | 2 | FMUX_GPIO_REG | - | | | PI_TXP2 | | _IOCTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - | | | | | | - +---------+---------+---------+--------+-----------------------+ - | VO_D[0] | O | PAD_MI | 2 | FMUX_GPIO_REG | - | | | PI_TXM2 | | _IOCTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[1] | O | PAD_MI | 2 | FMUX_GPIO_REG | - | | | PI_TXP1 | | _IOCTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[2] | O | PAD_MI | 2 | FMUX_GPIO_REG | - | | | PI_TXM1 | | _IOCTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | VO_D[3] | O | PAD_MI | 2 | FMUX_GPIO_REG | - | | | PI_TXP0 | | _IOCTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[4] | O | PAD_MI | 2 | FMUX_GPIO_REG | - | | | PI_TXM0 | | _IOCTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[5] | O | PAD_M | 2 | FMUX_GPIO_RE | - | | | IPIRX0P | | G_IOCTRL_PAD_MIPIRX0P | - | | | | | 0x0300_1190 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[6] | O | PAD_M | 2 | FMUX_GPIO_RE | - | | | IPIRX0N | | G_IOCTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - | VO_D[7] | O | PAD_M | 2 | FMUX_GPIO_RE | - | | | IPIRX1P | | G_IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[8] | O | PAD_M | 2 | FMUX_GPIO_RE | - | | | IPIRX1N | | G_IOCTRL_PAD_MIPIRX1N | - | | | | | 0x0300_1184 | - +---------+---------+---------+--------+-----------------------+ - | VO_D[9] | O | PAD_M | 2 | FMUX_GPIO_RE | - | | | IPIRX2P | | G_IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - | V | O | PAD_M | 2 | FMUX_GPIO_RE | - | O_D[10] | | IPIRX2N | | G_IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - | V | O | JTAG | 7 | FMUX_GPIO_RE | - | O_D[28] | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | V | O | JTAG | 7 | FMUX_GPIO_RE | - | O_D[29] | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | V | O | AUX0 | 5 | FMUX | - | O_D[31] | | | | _GPIO_REG_IOCTRL_AUX0 | - | | | | | 0x0300_1078 | - +---------+---------+---------+--------+-----------------------+ - | V | O | SD1_D3 | 0 | FMUX_G | - | O_D[32] | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | V | O | SD1_D2 | 0 | FMUX_G | - | O_D[33] | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | V | O | SD1_D1 | 0 | FMUX_G | - | O_D[34] | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | V | O | SD1_D0 | 0 | FMUX_G | - | O_D[35] | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | V | O | SD1_CMD | 0 | FMUX_GP | - | O_D[36] | | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | V | O | SD1_CLK | 0 | FMUX_GP | - | O_D[37] | | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - -Parallel Video In -^^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_parallel_videoin: -.. table:: Parallel Video In - :widths: 1 1 1 1 5 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | VI0_CLK | I | PAD_M | 1 | FMUX_GPIO_RE | - | | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - | | | | | | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[0] | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[1] | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_MI | 1 | FMUX_GPIO_REG | - | 0_D[10] | | PI_TXP0 | | _IOCTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_MI | 1 | FMUX_GPIO_REG | - | 0_D[11] | | PI_TXM1 | | _IOCTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_MI | 1 | FMUX_GPIO_REG | - | 0_D[12] | | PI_TXP1 | | _IOCTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_MI | 1 | FMUX_GPIO_REG | - | 0_D[13] | | PI_TXM2 | | _IOCTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_MI | 1 | FMUX_GPIO_REG | - | 0_D[14] | | PI_TXP2 | | _IOCTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[2] | | IPIRX3P | | G_IOCTRL_PAD_MIPIRX3P | - | | | | | 0x0300_1178 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[3] | | IPIRX2N | | G_IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[4] | | IPIRX2P | | G_IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[5] | | IPIRX1N | | G_IOCTRL_PAD_MIPIRX1N | - | | | | | 0x0300_1184 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[6] | | IPIRX1P | | G_IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[7] | | IPIRX0N | | G_IOCTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_M | 1 | FMUX_GPIO_RE | - | I0_D[8] | | IPIRX0P | | G_IOCTRL_PAD_MIPIRX0P | - | | | | | 0x0300_1190 | - +---------+---------+---------+--------+-----------------------+ - | V | I | PAD_MI | 1 | FMUX_GPIO_REG | - | I0_D[9] | | PI_TXM0 | | _IOCTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_M | 2 | FMUX_GPIO_RE | - | 1_D[13] | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_M | 2 | FMUX_GPIO_RE | - | 1_D[14] | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_M | 2 | FMUX_GPIO_RE | - | 1_D[15] | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_M | 2 | FMUX_GPIO_RE | - | 1_D[16] | | IPIRX3P | | G_IOCTRL_PAD_MIPIRX3P | - | | | | | 0x0300_1178 | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_M | 4 | FMUX_GPIO_RE | - | 1_D[17] | | IPIRX2N | | G_IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - | VI | I | PAD_M | 4 | FMUX_GPIO_RE | - | 1_D[18] | | IPIRX2P | | G_IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - -eMMC -^^^^ - -.. _table_inf_signal_pin_fmux_emmc: -.. table:: eMMC - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | E\ | O | E | 0 | FMUX_GPI | - | MMC_CLK | | MMC_CLK | | O_REG_IOCTRL_EMMC_CLK | - | | | | | 0x0300_1050 | - +---------+---------+---------+--------+-----------------------+ - | E\ | I/O | E | 0 | FMUX_GPI | - | MMC_CMD | | MMC_CMD | | O_REG_IOCTRL_EMMC_CMD | - | | | | | 0x0300_105C | - +---------+---------+---------+--------+-----------------------+ - | EMMC\ | I/O | EM | 0 | FMUX_GPIO | - | _DAT[0] | | MC_DAT0 | | _REG_IOCTRL_EMMC_DAT0 | - | | | | | 0x0300_1054 | - +---------+---------+---------+--------+-----------------------+ - | EMMC\ | I/O | EM | 0 | FMUX_GPIO | - | _DAT[1] | | MC_DAT1 | | _REG_IOCTRL_EMMC_DAT1 | - | | | | | 0x0300_1060 | - +---------+---------+---------+--------+-----------------------+ - | EMMC\ | I/O | EM | 0 | FMUX_GPIO | - | _DAT[2] | | MC_DAT2 | | _REG_IOCTRL_EMMC_DAT2 | - | | | | | 0x0300_104C | - +---------+---------+---------+--------+-----------------------+ - | EMMC\ | I/O | EM | 0 | FMUX_GPIO | - | _DAT[3] | | MC_DAT3 | | _REG_IOCTRL_EMMC_DAT3 | - | | | | | 0x0300_1058 | - +---------+---------+---------+--------+-----------------------+ - - -SPI_NAND -^^^^^^^^ - -.. _table_inf_signal_pin_fmux_spi_nand: -.. table:: SPI_NAND - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | SPIN\ | O | E | 2 | FMUX_GPI | - | AND_CLK | | MMC_CLK | | O_REG_IOCTRL_EMMC_CLK | - | | | | | 0x0300_1050 | - +---------+---------+---------+--------+-----------------------+ - | SPI\ | O | EM | 2 | FMUX_GPIO | - | NAND_CS | | MC_DAT1 | | _REG_IOCTRL_EMMC_DAT1 | - | | | | | 0x0300_1060 | - +---------+---------+---------+--------+-----------------------+ - | SPINA\ | I/O | EM | 2 | FMUX_GPIO | - | ND_HOLD | | MC_DAT2 | | _REG_IOCTRL_EMMC_DAT2 | - | | | | | 0x0300_104C | - +---------+---------+---------+--------+-----------------------+ - | SPINA\ | I/O | E | 2 | FMUX_GPI | - | ND_MISO | | MMC_CMD | | O_REG_IOCTRL_EMMC_CMD | - | | | | | 0x0300_105C | - +---------+---------+---------+--------+-----------------------+ - | SPINA\ | I/O | EM | 2 | FMUX_GPIO | - | ND_MOSI | | MC_DAT0 | | _REG_IOCTRL_EMMC_DAT0 | - | | | | | 0x0300_1054 | - +---------+---------+---------+--------+-----------------------+ - | SPI\ | I/O | EM | 2 | FMUX_GPIO | - | NAND_WP | | MC_DAT3 | | _REG_IOCTRL_EMMC_DAT3 | - | | | | | 0x0300_1058 | - +---------+---------+---------+--------+-----------------------+ - -SPI_NOR -^^^^^^^ - -.. _table_inf_signal_pin_fmux_spi_nor: -.. table:: SPI_NOR - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | SPIN\ | O | EM | 1 | FMUX_GPIO | - | OR_CS_X | | MC_DAT1 | | _REG_IOCTRL_EMMC_DAT1 | - | | | | | 0x0300_1060 | - +---------+---------+---------+--------+-----------------------+ - | SPINOR\ | I/O | EM | 1 | FMUX_GPIO | - | _HOLD_X | | MC_DAT2 | | _REG_IOCTRL_EMMC_DAT2 | - | | | | | 0x0300_104C | - +---------+---------+---------+--------+-----------------------+ - | SPIN\ | I/O | E | 1 | FMUX_GPI | - | OR_MISO | | MMC_CMD | | O_REG_IOCTRL_EMMC_CMD | - | | | | | 0x0300_105C | - +---------+---------+---------+--------+-----------------------+ - | SPIN\ | I/O | EM | 1 | FMUX_GPIO | - | OR_MOSI | | MC_DAT0 | | _REG_IOCTRL_EMMC_DAT0 | - | | | | | 0x0300_1054 | - +---------+---------+---------+--------+-----------------------+ - | SPI\ | O | E | 1 | FMUX_GPI | - | NOR_SCK | | MMC_CLK | | O_REG_IOCTRL_EMMC_CLK | - | | | | | 0x0300_1050 | - +---------+---------+---------+--------+-----------------------+ - | SPIN\ | I/O | EM | 1 | FMUX_GPIO | - | OR_WP_X | | MC_DAT3 | | _REG_IOCTRL_EMMC_DAT3 | - | | | | | 0x0300_1058 | - +---------+---------+---------+--------+-----------------------+ - -I2C -^^^ - -.. _table_inf_signal_pin_fmux_i2c: -.. table:: I2C - :widths: 1 1 1 1 2 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - |IIC1_SCL | I/O | PAD_M | 4 | FMUX_GPIO_REG | - | | | IPIRX4P | | _IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | PAD_M | 4 | FMUX_GPIO_REG_IO | - | | | IPIRX0N | | CTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | SD0_CMD | 1 | FMUX_GPIO | - | | | | | _REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | SD0_D2 | 1 | FMUX_GPIO | - | | | | | _REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | PAD_MI | 4 | FMUX_GPIO_REG | - | | | PI_TXP2 | | _IOCTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | SD1_D3 | 2 | FMUX_GPIO | - | | | | | _REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | MUX_SP | 2 | FMUX_GPIO_REG | - | | | I1_MOSI | | _IOCTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | PAD | 2 | FMUX_GPIO_REG | - | | | _ETH_TX | | _IOCTRL_PAD_ETH_TXP | - | | | P___E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SCL | I/O | SD1_D2 | 1 | FMUX_GPIO | - | | | | | _REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | PAD_M | 4 | FMUX_GPIO_REG | - | | | IPIRX4N | | _IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - -To be continued ...... - - -.. _table_inf_signal_pin_fmux_i2c_2: -.. table:: I2C (continued) - :widths: 1 1 1 1 2 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - |IIC1_SDA | I/O | PAD_M | 4 | FMUX_GPIO_REG | - | | | IPIRX1P | | _IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | SD0_CLK | 1 | FMUX_GPIO_REG | - | | | | | _IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | SD0_D1 | 1 | FMUX_GPIO_REG | - | | | | | _IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | PAD_MI | 4 | FMUX_GPIO_REG | - | | | PI_TXM2 | | _IOCTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | SD1_D0 | 2 | FMUX_GPIO_REG | - | | | | | _IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | MUX_SP | 2 | FMUX_GPIO_REG | - | | | I1_MISO | | _IOCTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | PAD | 2 | FMUX_GPIO_REG | - | | | _ETH_TX | | _IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - |IIC1_SDA | I/O | SD1_D1 | 1 | FMUX_GPIO_REG | - | | | | | _IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - |IIC2_SCL | I/O | PAD_MI | 4 | FMUX_GPIO_REG | - | | | PI_TXP1 | | _IOCTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - |IIC2_SCL | I/O | PW | 6 | FMUX_GPIO_REG | - | | | R_GPIO1 | | _IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - |IIC2_SDA | I/O | PAD_MI | 4 | FMUX_GPIO_REG | - | | | PI_TXM1 | | _IOCTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - |IIC2_SDA | I/O | PW | 6 | FMUX_GPIO_REG | - | | | R_GPIO2 | | _IOCTRL_PWR_GPIO2 | - | | | | | 0x0300_10AC | - +---------+---------+---------+--------+-----------------------+ - |IIC3_SCL | I/O | SD1_CMD | 2 | FMUX_GPIO_REG | - | | | | | _IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - |IIC3_SDA | I/O | SD1_CLK | 2 | FMUX_GPIO_REG | - | | | | | _IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - |IIC4_SCL | I/O | PWR | 5 | FMUX_GPIO_REG | - | | | _WAKEUP0| | _IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - |IIC4_SCL | I/O | PAD_M | 5 | FMUX_GPIO_REG | - | | | IPIRX2N | | _IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - |IIC4_SDA | I/O | PWR | 5 | FMUX_GPIO_REG | - | | | _BUTTON1| | _IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - |IIC4_SDA | I/O | PAD_M | 5 | FMUX_GPIO_REG | - | | | IPIRX2P | | _IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - -No-die domain I2C -^^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_nodie_i2c: -.. table:: No-die domain I2C - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR\ | I/O | PW | 5 | FMUX_GPIO | - | _IIC_SCL| | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | PW | 5 | FMUX_GPIO | - | _IIC_SDA| | R_GPIO2 | | _REG_IOCTRL_PWR_GPIO2 | - | | | | | 0x0300_10AC | - +---------+---------+---------+--------+-----------------------+ - - -IIS -^^^ - -.. _table_inf_signal_pin_fmux_iis: -.. table:: IIS - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | II\ | I/O | PA | 4 | FMUX_GPIO_REG_IO | - | S1_BCLK | | D_AUD_A | | CTRL_PAD_AUD_AINL_MIC | - | | | INL_MIC | | 0x0300_11BC | - +---------+---------+---------+--------+-----------------------+ - | IIS1_DI | I | PAD_AU | 4 | FMUX_GPIO_REG_IO | - | | | D_AOUTR | | CTRL_PAD_AUD_AOUTR | - | | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - | IIS1_DO | O | PAD_AU | 6 | FMUX_GPIO_REG | - | | | D_AOUTR | | _IOCTRL_PAD_AUD_AOUTR | - | | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - | II\ | I/O | AUX0 | 4 | FMUX | - | S1_MCLK | | | | _GPIO_REG_IOCTRL_AUX0 | - | | | | | 0x0300_1078 | - +---------+---------+---------+--------+-----------------------+ - | II\ | I/O | PA | 5 | FMUX_GPIO_REG_IO | - | S2_BCLK | | D_AUD_A | | CTRL_PAD_AUD_AINL_MIC | - | | | INL_MIC | | 0x0300_11BC | - +---------+---------+---------+--------+-----------------------+ - | II\ | I/O | PAD | 7 | FMUX_GPIO_R | - | S2_BCLK | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | IIS2_DI | I | PAD | 7 | FMUX_GPIO_R | - | | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | IIS2_DO | O | PAD_AU | 5 | FMUX_GPIO_REG | - | | | D_AOUTR | | _IOCTRL_PAD_AUD_AOUTR | - | | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - | IIS2_DO | O | PAD | 7 | FMUX_GPIO_R | - | | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | II\ | I/O | PAD | 7 | FMUX_GPIO_R | - | S2_LRCK | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | MUX_SP | 5 | FMUX_GPIO_REG | - | EY_COL0 | | I1_MOSI | | _IOCTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | MUX_SP | 5 | FMUX_GPIO_REG | - | EY_COL1 | | I1_MISO | | _IOCTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | ADC1 | 4 | FMUX | - | EY_COL2 | | | | _GPIO_REG_IOCTRL_ADC1 | - | | | | | 0x0300_10F8 | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | PAD_M | 6 | FMUX_GPIO_RE | - | EY_ROW0 | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | PAD_M | 6 | FMUX_GPIO_RE | - | EY_ROW1 | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - -To be continued ...... - -.. _table_inf_signal_pin_fmux_iis_2: -.. table:: IIS (continued) - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | K\ | I/O | PAD_M | 6 | FMUX_GPIO_RE | - | EY_ROW2 | | IPIRX1P | | G_IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | MUX_S | 5 | FMUX_GPIO_RE | - | EY_ROW2 | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | PAD_M | 6 | FMUX_GPIO_RE | - | EY_ROW3 | | IPIRX1N | | G_IOCTRL_PAD_MIPIRX1N | - | | | | | 0x0300_1184 | - +---------+---------+---------+--------+-----------------------+ - | K\ | I/O | MUX | 5 | FMUX_GPIO_R | - | EY_ROW3 | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - -PWM -^^^ - -.. _table_inf_signal_pin_fmux_pwm: -.. table:: PWM - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWM[0] | I/O | PW | 0 | FMUX_GPIO | - | | | M0_BUCK | | _REG_IOCTRL_PWM0_BUCK | - | | | | | 0x0300_10EC | - +---------+---------+---------+--------+-----------------------+ - | PWM[1] | I/O | GPIO_RT | 4 | FMUX_GPI | - | | | X\_\__E | | O_REG_IOCTRL_GPIO_RTX | - | | | PHY_RTX | | 0x0300_11CC | - +---------+---------+---------+--------+-----------------------+ - | PWM[2] | I/O | GPIO | 4 | FMUX_GP | - | | | _ZQ\_\_ | | IO_REG_IOCTRL_GPIO_ZQ | - | | | _PAD_ZQ | | 0x0300_11D0 | - +---------+---------+---------+--------+-----------------------+ - | PWM[4] | I/O | U | 2 | FMUX_GPI | - | | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | PWM[4] | I/O | SD1_D3 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | PWM[5] | I/O | U | 2 | FMUX_GPI | - | | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | PWM[5] | I/O | SD1_D2 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | PWM[6] | I/O | JTAG | 2 | FMUX_GPIO_RE | - | | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | PWM[6] | I/O | SD1_D1 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | PWM[7] | I/O | JTAG | 2 | FMUX_GPIO_RE | - | | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | PWM[7] | I/O | SD1_D0 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | PWM[8] | I/O | PW | 4 | FMUX_GPIO | - | | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | PWM[8] | I/O | MUX_SP | 4 | FMUX_GPIO_REG_IO | - | | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | PWM[8] | I/O | SD1_CMD | 7 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | PWM[8] | I/O | PAD_MI | 5 | FMUX_GPIO_REG_IO | - | | | PI_TXM2 | | CTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | PWM[9] | I/O | PW | 4 | FMUX_GPIO | - | | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | PWM[9] | I/O | MUX_SP | 4 | FMUX_GPIO_REG_IO | - | | | I1_MISO | | CTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | PWM[9] | I/O | SD1_CLK | 7 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | PWM[9] | I/O | PAD_MI | 5 | FMUX_GPIO_REG_IO | - | | | PI_TXP2 | | CTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - | PWM[10] | I/O | PW | 4 | FMUX_GPIO | - | | | R_GPIO2 | | _REG_IOCTRL_PWR_GPIO2 | - | | | | | 0x0300_10AC | - +---------+---------+---------+--------+-----------------------+ - | PWM[10] | I/O | MUX_S | 4 | FMUX_GPIO_RE | - | | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | PWM[10] | I/O | SD0_D3 | 5 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | PWM[10] | I/O | PAD_MI | 5 | FMUX_GPIO_REG_IO | - | | | PI_TXM1 | | CTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | PWM[11] | I/O | MUX | 4 | FMUX_GPIO_R | - | | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | PWM[11] | I/O | SD0_D2 | 5 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | PWM[11] | I/O | PAD_MI | 5 | FMUX_GPIO_REG_IO | - | | | PI_TXP1 | | CTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | PWM[12] | I/O | PAD | 4 | FMUX_GPIO_R | - | | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | PWM[12] | I/O | SD0_D1 | 5 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | PWM[13] | I/O | PAD | 4 | FMUX_GPIO_R | - | | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | PWM[13] | I/O | SD0_D0 | 5 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | PWM[14] | I/O | PAD | 4 | FMUX_GPIO_R | - | | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | PWM[14] | I/O | SD0_CMD | 5 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - | PWM[14] | I/O | PAD_MI | 5 | FMUX_GPIO_REG_IO | - | | | PI_TXM0 | | CTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | PWM[15] | I/O | PAD | 4 | FMUX_GPIO_R | - | | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | PWM[15] | I/O | SD0_CLK | 5 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - | PWM[15] | I/O | PAD_MI | 5 | FMUX_GPIO_REG_IO | - | | | PI_TXP0 | | CTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - -CA53 JTAG(2W) RISCV JTAG(4W) I2C0 -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_ca53_rv_jtag_i2c0: -.. table:: CA53 JTAG(2W) RISCV JTAG(4W) I2C0 - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | C\ | I/O | JTAG | 0 | FMUX_GPIO_RE | - | R_4WTCK | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - | | | | | | - | | | | | | - | | | | | | - | | | | | | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | JTAG | 0 | FMUX_GPIO_RE | - | R_4WTMS | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | PAD_M | 0 | FMUX_GPIO_RE | - | R_2WTCK | | IPIRX3P | | G_IOCTRL_PAD_MIPIRX3P | - | | | | | 0x0300_1178 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | PAD_MI | 0 | FMUX_GPIO_REG_IO | - | R_2WTCK | | PI_TXP1 | | CTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | PW | 7 | FMUX_GPIO | - | R_2WTCK | | R_GPIO2 | | _REG_IOCTRL_PWR_GPIO2 | - | | | | | 0x0300_10AC | - +---------+---------+---------+--------+-----------------------+ - | CR_SCL0 | I/O | PAD_M | 0 | FMUX_GPIO_RE | - | | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | CR_SCL0 | I/O | PAD_MI | 0 | FMUX_GPIO_REG_IO | - | | | PI_TXP2 | | CTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | PAD_M | 0 | FMUX_GPIO_RE | - | R_2WTMS | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | PAD_MI | 0 | FMUX_GPIO_REG_IO | - | R_2WTMS | | PI_TXM1 | | CTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | CR_SDA0 | I/O | PAD_M | 0 | FMUX_GPIO_RE | - | | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - | CR_SDA0 | I/O | PAD_MI | 0 | FMUX_GPIO_REG_IO | - | | | PI_TXM2 | | CTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | CR_SDA0 | I/O | PW | 7 | FMUX_GPIO | - | | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | I | 0 | FMUX_GPI | - | R_4WTDI | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | C\ | I/O | I | 0 | FMUX_GPI | - | R_4WTDO | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - - -System -^^^^^^ - -.. _table_inf_signal_pin_fmux_system: -.. table:: System - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR\ | I | PWR | 0 | FMUX_GPIO_R | - | _BUTTON1| | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - | P\ | I | P | 0 | FMUX_GPI | - | WR_RSTN | | WR_RSTN | | O_REG_IOCTRL_PWR_RSTN | - | | | | | 0x0300_1080 | - +---------+---------+---------+--------+-----------------------+ - | P\ | O | P | 0 | FMUX_GPI | - | WR_SEQ1 | | WR_SEQ1 | | O_REG_IOCTRL_PWR_SEQ1 | - | | | | | 0x0300_1084 | - +---------+---------+---------+--------+-----------------------+ - | P\ | O | P | 0 | FMUX_GPI | - | WR_SEQ2 | | WR_SEQ2 | | O_REG_IOCTRL_PWR_SEQ2 | - | | | | | 0x0300_1088 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I | PWR | 0 | FMUX_GPIO_R | - | _WAKEUP0| | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | USB_V\ | I | USB_V | 0 | FMUX_GPIO_RE | - | BUS_DET | | BUS_DET | | G_IOCTRL_USB_VBUS_DET | - | | | | | 0x0300_1108 | - +---------+---------+---------+--------+-----------------------+ - - -No-die domain IR -^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_nodie_ir: -.. table:: No-die domain IR - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR_IR0 | I | PWR | 1 | FMUX_GPIO_R | - | | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - - -SPI_NOR1 -^^^^^^^^ - -.. _table_inf_signal_pin_fmux_spi_nor1: -.. table:: SPI_NOR1 - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PW\ | O | SD1_D3 | 6 | FMUX_G | - | R_SPINO\| | | | PIO_REG_IOCTRL_SD1_D3 | - | R1_CS_X | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | SD1_D2 | 6 | FMUX_G | - | _SPINOR\| | | | PIO_REG_IOCTRL_SD1_D2 | - | 1_HOLD_X| | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | PW\ | I/O | SD1_D0 | 6 | FMUX_G | - | R_SPINO\| | | | PIO_REG_IOCTRL_SD1_D0 | - | R1_MISO | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | PW\ | I/O | SD1_CMD | 6 | FMUX_GP | - | R_SPINO\| | | | IO_REG_IOCTRL_SD1_CMD | - | R1_MOSI | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | P\ | O | SD1_CLK | 6 | FMUX_GP | - | WR_SPIN\| | | | IO_REG_IOCTRL_SD1_CLK | - | OR1_SCK | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | PW\ | I/O | SD1_D1 | 6 | FMUX_G | - | R_SPINO\| | | | PIO_REG_IOCTRL_SD1_D1 | - | R1_WP_X | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - - -SD1 -^^^ - -.. _table_inf_signal_pin_fmux_sd1: -.. table:: SD1 - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR\ | O | SD1_CLK | 0 | FMUX_GP | - | _SD1_CLK| | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | SD1_CMD | 0 | FMUX_GP | - | _SD1_CMD| | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | SD1_D0 | 0 | FMUX_G | - | _SD1_D0 | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | SD1_D1 | 0 | FMUX_G | - | _SD1_D1 | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | SD1_D2 | 0 | FMUX_G | - | _SD1_D2 | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | SD1_D3 | 0 | FMUX_G | - | _SD1_D3 | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - - -SD0 -^^^ - -.. _table_inf_signal_pin_fmux_sd0: -.. table:: SD0 - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | S\ | I | SD0_CD | 0 | FMUX_G | - | DIO0_CD | | | | PIO_REG_IOCTRL_SD0_CD | - | | | | | 0x0300_1034 | - +---------+---------+---------+--------+-----------------------+ - | SD\ | O | SD0_CLK | 0 | FMUX_GP | - | IO0_CLK | | | | IO_REG_IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - | SD\ | I/O | SD0_CMD | 0 | FMUX_GP | - | IO0_CMD | | | | IO_REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - | SDI\ | I/O | SD0_D0 | 0 | FMUX_G | - | O0_D[0] | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | SDI\ | I/O | SD0_D1 | 0 | FMUX_G | - | O0_D[1] | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | SDI\ | I/O | SD0_D2 | 0 | FMUX_G | - | O0_D[2] | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | SDI\ | I/O | SD0_D3 | 0 | FMUX_G | - | O0_D[3] | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | SDIO0\ | O | SD0 | 0 | FMUX_GPIO | - | _PWR_EN | | _PWR_EN | | _REG_IOCTRL_SD0_PWR_EN| - | | | | | 0x0300_1038 | - +---------+---------+---------+--------+-----------------------+ - -SPI -^^^ - -.. _table_inf_signal_pin_fmux_spi: -.. table:: SPI - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | SP\ | O | SD0_D3 | 2 | FMUX_G | - | I0_CS_X | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | SP\ | O | PAD_MI | 6 | FMUX_GPIO_REG_IO | - | I0_CS_X | | PI_TXP2 | | CTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - | S\ | O | SD0_CLK | 2 | FMUX_GPIO | - | PI0_SCK | | | | _REG_IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - | S\ | O | PAD_MI | 6 | FMUX_GPIO_REG_IO | - | PI0_SCK | | PI_TXM2 | | CTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | S\ | I | SD0_D0 | 2 | FMUX_GPIO_REG_IO | - | PI0_SDI | | | | CTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | S\ | I | PAD_MI | 6 | FMUX_GPIO_REG_IO | - | PI0_SDI | | PI_TXP1 | | CTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | S\ | I/O | SD0_CMD | 2 | FMUX_GP | - | PI0_SDO | | | | IO_REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - | S\ | I/O | PAD_MI | 6 | FMUX_GPIO_REG_IO | - | PI0_SDO | | PI_TXM1 | | CTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | SP\ | O | MUX | 6 | FMUX_GPIO_R | - | I1_CS_X | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | SP\ | O | PAD | 6 | FMUX_GPIO_R | - | I1_CS_X | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | S\ | O | MUX_S | 6 | FMUX_GPIO_RE | - | PI1_SCK | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | S\ | O | PAD | 6 | FMUX_GPIO_R | - | PI1_SCK | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | S\ | I | MUX_SP | 6 | FMUX_GPIO_REG_IO | - | PI1_SDI | | I1_MISO | | CTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | S\ | I | PAD | 6 | FMUX_GPIO_R | - | PI1_SDI | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | S\ | I/O | MUX_SP | 6 | FMUX_GPIO_REG_IO | - | PI1_SDO | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - -To be continued ...... - -.. _table_inf_signal_pin_fmux_spi_2: -.. table:: SPI (continued) - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | S\ | I/O | PAD | 6 | FMUX_GPIO_R | - | PI1_SDO | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | SP\ | O | SD1_D3 | 1 | FMUX_G | - | I2_CS_X | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | S\ | O | SD1_CLK | 1 | FMUX_GP | - | PI2_SCK | | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | S\ | I | SD1_D0 | 1 | FMUX_G | - | PI2_SDI | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | S\ | I/O | SD1_CMD | 1 | FMUX_GP | - | PI2_SDO | | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - - -UART -^^^^ - -.. only:: sg2002 - - .. _table_inf_signal_pin_fmux_uart_sg2002: - .. table:: UART - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | U\ | I | U | 0 | FMUX_GPI | - | ART0_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | U | 0 | FMUX_GPI | - | ART0_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | JTAG | 4 | FMUX_GPIO_RE | - | RT1_CTS | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | JTAG | 4 | FMUX_GPIO_RE | - | RT1_RTS | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD0_D2 | 4 | FMUX_G | - | ART1_RX | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | U | 4 | FMUX_GPI | - | ART1_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PWR | 4 | FMUX_GPIO_R | - | ART1_RX | | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | JTAG | 6 | FMUX_GPIO_RE | - | ART1_RX | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | I | 1 | FMUX_GPI | - | ART1_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD0_D1 | 4 | FMUX_G | - | ART1_TX | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | U | 4 | FMUX_GPI | - | ART1_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PWR | 4 | FMUX_GPIO_R | - | ART1_TX | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | JTAG | 6 | FMUX_GPIO_RE | - | ART1_TX | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | I | 1 | FMUX_GPI | - | ART1_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | I | 2 | FMUX_GPI | - | ART2_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD1_D1 | 2 | FMUX_G | - | ART2_RX | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PW | 1 | FMUX_GPIO | - | ART2_RX | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | I | 2 | FMUX_GPI | - | ART2_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD1_D2 | 2 | FMUX_G | - | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PW | 1 | FMUX_GPIO | - | ART2_TX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | MUX | 1 | FMUX_GPIO_R | - | RT3_CTS | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | PAD | 1 | FMUX_GPIO_R | - | RT3_CTS | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | SD1_D3 | 5 | FMUX_G | - | RT3_CTS | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | MUX_SP | 1 | FMUX_GPIO_REG_IO | - | RT3_RTS | | I1_MISO | | CTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | PAD | 1 | FMUX_GPIO_R | - | RT3_RTS | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | SD1_D0 | 5 | FMUX_G | - | RT3_RTS | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD0_D3 | 4 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | MUX_SP | 1 | FMUX_GPIO_REG_IO | - | ART3_RX | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PAD | 1 | FMUX_GPIO_R | - | ART3_RX | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD1_D1 | 5 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD0_D0 | 4 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | MUX_S | 1 | FMUX_GPIO_RE | - | ART3_TX | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PAD | 1 | FMUX_GPIO_R | - | ART3_TX | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD1_D2 | 5 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - -.. only:: sg2000 - - .. _table_inf_signal_pin_fmux_uart_sg2000: - .. table:: UART - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | U\ | I | U | 0 | FMUX_GPI | - | ART0_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | U | 0 | FMUX_GPI | - | ART0_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | JTAG | 4 | FMUX_GPIO_RE | - | RT1_CTS | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | JTAG | 4 | FMUX_GPIO_RE | - | RT1_RTS | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD0_D2 | 4 | FMUX_G | - | ART1_RX | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | U | 4 | FMUX_GPI | - | ART1_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PWR | 4 | FMUX_GPIO_R | - | ART1_RX | | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PWR | 4 | FMUX_GPIO_R | - | ART1_RX | | _ON | | EG_IOCTRL_PWR_ON | - | | | | | 0x0300_109C | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | JTAG | 6 | FMUX_GPIO_RE | - | ART1_RX | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | I | 1 | FMUX_GPI | - | ART1_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD0_D1 | 4 | FMUX_G | - | ART1_TX | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | U | 4 | FMUX_GPI | - | ART1_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PWR | 4 | FMUX_GPIO_R | - | ART1_TX | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PWR | 4 | FMUX_GPIO_R | - | ART1_TX | | _WAKEUP1| | EG_IOCTRL_PWR_WAKEUP1 | - | | | | | 0x0300_1094 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | JTAG | 6 | FMUX_GPIO_RE | - | ART1_TX | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | I | 1 | FMUX_GPI | - | ART1_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | VIVO_D4 | 6 | FMUX_GPI | - | ART2_CTS| | | | O_REG_IOCTRL_VIVO_D4 | - | | | | | 0x0300_114C | - +---------+---------+---------+--------+-----------------------+ - | U\ | I |UART2_CTS| 0 | FMUX_GPI | - | ART2_CTS| | | | O_REG_IOCTRL_UART2_CTS| - | | | | | 0x0300_10CC | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | VIVO_D3 | 6 | FMUX_GPI | - | ART2_RTS| | | | O_REG_IOCTRL_VIVO_D3 | - | | | | | 0x0300_1150 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O |UART2_RTS| 0 | FMUX_GPI | - | ART2_RTS| | | | O_REG_IOCTRL_UART2_RTS| - | | | | | 0x0300_10C4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | UART2_RX| 0 | FMUX_GPI | - | ART2_RX | | | | O_REG_IOCTRL_UART2_RX | - | | | | | 0x0300_10C8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | IIC2_SCL| 4 | FMUX_GP | - | ART2_RX | | | | IO_REG_IOCTRL_IIC2_SCL| - | | | | | 0x0300_10B8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | I | 2 | FMUX_GPI | - | ART2_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD1_D1 | 2 | FMUX_G | - | ART2_RX | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | VIVO_D5 | 6 | FMUX_G | - | ART2_RX | | | | PIO_REG_IOCTRL_VIVO_D5| - | | | | | 0x0300_1148 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PW | 1 | FMUX_GPIO | - | ART2_RX | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | VIVO_D9 | 7 | FMUX_G | - | ART2_RX | | | | PIO_REG_IOCTRL_VIVO_D9| - | | | | | 0x0300_1138 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | VIVO_CLK| 7 | FMUX_GP | - | ART2_RX | | | | IO_REG_IOCTRL_VIVO_CLK| - | | | | | 0x0300_1160 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | UART2_TX| 0 | FMUX_GPI | - | ART2_TX | | | | O_REG_IOCTRL_UART2_TX | - | | | | | 0x0300_10C0 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | IIC2_SDA| 4 | FMUX_GPI | - | ART2_TX | | | | O_REG_IOCTRL_IIC2_SDA | - | | | | | 0x0300_10BC | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | IIC0_SCL| 2 | FMUX_GPI | - | ART2_TX | | | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD1_D2 | 2 | FMUX_G | - | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | VIVO_D6 | 6 | FMUX_G | - | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_1144 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PW | 1 | FMUX_GPIO | - | ART2_TX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | VIVO_D10| 7 | FMUX_GPIO | - | ART2_TX | | | | _REG_IOCTRL_VIVO_D10 | - | | | | | 0x0300_1134 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | VIVO_D2 | 7 | FMUX_GPIO | - | ART2_TX | | | | _REG_IOCTRL_VIVO_D2 | - | | | | | 0x0300_1154 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | MUX | 1 | FMUX_GPIO_R | - | RT3_CTS | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | PAD | 1 | FMUX_GPIO_R | - | RT3_CTS | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | SD1_D3 | 5 | FMUX_G | - | RT3_CTS | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | MUX_SP | 1 | FMUX_GPIO_REG_IO | - | RT3_RTS | | I1_MISO | | CTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | PAD | 1 | FMUX_GPIO_R | - | RT3_RTS | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | SD1_D0 | 5 | FMUX_G | - | RT3_RTS | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD0_D3 | 4 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | MUX_SP | 1 | FMUX_GPIO_REG_IO | - | ART3_RX | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PAD | 1 | FMUX_GPIO_R | - | ART3_RX | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD1_D1 | 5 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | ADC2 | 7 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_ADC2 | - | | | | | 0x0300_10F4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD0_D0 | 4 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | MUX_S | 1 | FMUX_GPIO_RE | - | ART3_TX | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PAD | 1 | FMUX_GPIO_R | - | ART3_TX | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD1_D2 | 5 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | ADC3 | 7 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_ADC3 | - | | | | | 0x0300_10F0 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I |UART2_CTS| 5 | FMUX_GPI | - | ART4_CTS| | | | O_REG_IOCTRL_UART2_CTS| - | | | | | 0x0300_10CC | - +---------+---------+---------+--------+-----------------------+ - | U\ | O |UART2_RTS| 5 | FMUX_GPI | - | ART4_RTS| | | | O_REG_IOCTRL_UART2_RTS| - | | | | | 0x0300_10C4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I |UART2_RX | 5 | FMUX_GPI | - | ART4_RX | | | | O_REG_IOCTRL_UART2_RX | - | | | | | 0x0300_10C8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I |UART2_TX | 5 | FMUX_GPI | - | ART4_TX | | | | O_REG_IOCTRL_UART2_TX | - | | | | | 0x0300_10C0 | - +---------+---------+---------+--------+-----------------------+ - -No-die domain UART -^^^^^^^^^^^^^^^^^^ - -.. only:: sg2002 - - .. _table_inf_signal_pin_fmux_nodie_uart_sg2002: - .. table:: No-die domain UART - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR_U\ | I | PW | 2 | FMUX_GPIO | - | ART0_RX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | PWR_U\ | O |PWR | 2 | FMUX_GPIO_R | - | ART0_TX | |_WAKEUP0 | | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - -.. only:: sg2000 - - .. _table_inf_signal_pin_fmux_nodie_uart_sg2000: - .. table:: No-die domain UART - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR_U\ | I | PW | 2 | FMUX_GPIO | - | ART0_RX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | PWR_U\ | O |PWR | 2 | FMUX_GPIO_R | - | ART0_TX | |_WAKEUP0 | | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | PWR_U\ | I | UART2_RX| 2 | FMUX_GPIO | - | ART1_RX | | | | _REG_IOCTRL_UART2_RX | - | | | | | 0x0300_10C8 | - +---------+---------+---------+--------+-----------------------+ - | PWR_U\ | O | UART2_TX| 2 | FMUX_GPIO_R | - | ART1_TX | | | | EG_IOCTRL_UART2_TX | - | | | | | 0x0300_10C0 | - +---------+---------+---------+--------+-----------------------+ - -Wiegand -^^^^^^^ - -.. _table_inf_signal_pin_fmux_wiegand: -.. table:: Wiegand - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | WG0_D0 | I/O | SD0_D0 | 6 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | WG0_D0 | I/O | I | 5 | FMUX_GPI | - | | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | WG0_D1 | I/O | SD0_D1 | 6 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | WG0_D1 | I/O | I | 5 | FMUX_GPI | - | | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | WG1_D0 | I/O | SD0_D2 | 6 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | WG1_D0 | I/O | I | 6 | FMUX_GPI | - | | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | WG1_D1 | I/O | SD0_D3 | 6 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | WG1_D1 | I/O | AUX0 | 6 | FMUX | - | | | | | _GPIO_REG_IOCTRL_AUX0 | - | | | | | 0x0300_1078 | - +---------+---------+---------+--------+-----------------------+ - | WG2_D0 | I/O | PWR | 7 | FMUX_GPIO_R | - | | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | WG2_D1 | I/O | PWR | 7 | FMUX_GPIO_R | - | | | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - - -GPIO -^^^^ - -.. _table_inf_signal_pin_fmux_gpio: -.. table:: GPIO - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | XG\ | I/O | SD0_CLK | 3 | FMUX_GP | - | PIOA[7] | | | | IO_REG_IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | SD0_CMD | 3 | FMUX_GP | - | PIOA[8] | | | | IO_REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | SD0_D0 | 3 | FMUX_G | - | PIOA[9] | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | SD0_D1 | 3 | FMUX_G | - | IOA[10] | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | SD0_D2 | 3 | FMUX_G | - | IOA[11] | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | SD0_D3 | 3 | FMUX_G | - | IOA[12] | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | SD0_CD | 3 | FMUX_G | - | IOA[13] | | | | PIO_REG_IOCTRL_SD0_CD | - | | | | | 0x0300_1034 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | SD0 | 3 | FMUX_GPIO | - | IOA[14] | | _PWR_EN | | _REG_IOCTRL_SD0_PWR_EN| - | | | | | 0x0300_1038 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | SPK_EN | 3 | FMUX_G | - | IOA[15] | | | | PIO_REG_IOCTRL_SPK_EN | - | | | | | 0x0300_103C | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | U | 3 | FMUX_GPI | - | IOA[16] | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | U | 3 | FMUX_GPI | - | IOA[17] | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | JTAG | 3 | FMUX_GPIO_RE | - | IOA[18] | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | JTAG | 3 | FMUX_GPIO_RE | - | IOA[19] | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | E | 3 | FMUX_GPI | - | IOA[22] | | MMC_CLK | | O_REG_IOCTRL_EMMC_CLK | - | | | | | 0x0300_1050 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | E | 3 | FMUX_GPI | - | IOA[23] | | MMC_CMD | | O_REG_IOCTRL_EMMC_CMD | - | | | | | 0x0300_105C | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | EM | 3 | FMUX_GPIO | - | IOA[24] | | MC_DAT1 | | _REG_IOCTRL_EMMC_DAT1 | - | | | | | 0x0300_1060 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | EM | 3 | FMUX_GPIO | - | IOA[25] | | MC_DAT0 | | _REG_IOCTRL_EMMC_DAT0 | - | | | | | 0x0300_1054 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | EM | 3 | FMUX_GPIO | - | IOA[26] | | MC_DAT2 | | _REG_IOCTRL_EMMC_DAT2 | - | | | | | 0x0300_104C | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | EM | 3 | FMUX_GPIO | - | IOA[27] | | MC_DAT3 | | _REG_IOCTRL_EMMC_DAT3 | - | | | | | 0x0300_1058 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | I | 3 | FMUX_GPI | - | IOA[28] | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | I | 3 | FMUX_GPI | - | IOA[29] | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | AUX0 | 3 | FMUX | - | IOA[30] | | | | _GPIO_REG_IOCTRL_AUX0 | - | | | | | 0x0300_1078 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PW | 3 | FMUX_GPIO | - | PIOB[0] | | M0_BUCK | | _REG_IOCTRL_PWM0_BUCK | - | | | | | 0x0300_10EC | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | MUX | 3 | FMUX_GPIO_R | - | IOB[10] | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | GPIO_RT | 3 | FMUX_GPI | - | IOB[23] | | X\_\__E | | O_REG_IOCTRL_GPIO_RTX | - | | | PHY_RTX | | 0x0300_11CC | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD | 3 | FMUX_GPIO_R | - | IOB[24] | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD | 3 | FMUX_GPIO_R | - | IOB[25] | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD | 3 | FMUX_GPIO_R | - | IOB[26] | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD | 3 | FMUX_GPIO_R | - | IOB[27] | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | ADC1 | 3 | FMUX | - | PIOB[3] | | | | _GPIO_REG_IOCTRL_ADC1 | - | | | | | 0x0300_10F8 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | USB_V | 3 | FMUX_GPIO_RE | - | PIOB[6] | | BUS_DET | | G_IOCTRL_USB_VBUS_DET | - | | | | | 0x0300_1108 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | MUX_SP | 3 | FMUX_GPIO_REG | - | PIOB[7] | | I1_MOSI | | _IOCTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | MUX_SP | 3 | FMUX_GPIO_REG | - | PIOB[8] | | I1_MISO | | _IOCTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | MUX_S | 3 | FMUX_GPIO_RE | - | PIOB[9] | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[2] | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[3] | | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[4] | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[5] | | IPIRX3P | | G_IOCTRL_PAD_MIPIRX3P | - | | | | | 0x0300_1178 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[6] | | IPIRX2N | | G_IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[7] | | IPIRX2P | | G_IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[8] | | IPIRX1N | | G_IOCTRL_PAD_MIPIRX1N | - | | | | | 0x0300_1184 | - +---------+---------+---------+--------+-----------------------+ - | XG\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | PIOC[9] | | IPIRX1P | | G_IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | IOC[10] | | IPIRX0N | | G_IOCTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_M | 3 | FMUX_GPIO_RE | - | IOC[11] | | IPIRX0P | | G_IOCTRL_PAD_MIPIRX0P | - | | | | | 0x0300_1190 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | IOC[12] | | PI_TXM0 | | CTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | IOC[13] | | PI_TXP0 | | CTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | IOC[14] | | PI_TXM1 | | CTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | IOC[15] | | PI_TXP1 | | CTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | IOC[16] | | PI_TXM2 | | CTRL_PAD_MIPI_TXM2 | - | | | | | 0x0300_11A4 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_MI | 3 | FMUX_GPIO_REG_IO | - | IOC[17] | | PI_TXP2 | | CTRL_PAD_MIPI_TXP2 | - | | | | | 0x0300_11A8 | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PA | 3 | FMUX_GPIO_REG_IO | - | IOC[23] | | D_AUD_A | | CTRL_PAD_AUD_AINL_MIC | - | | | INL_MIC | | 0x0300_11BC | - +---------+---------+---------+--------+-----------------------+ - | XGP\ | I/O | PAD_AU | 3 | FMUX_GPIO_REG_IO | - | IOC[24] | | D_AOUTR | | CTRL_PAD_AUD_AOUTR | - | | | | | 0x0300_11C8 | - +---------+---------+---------+--------+-----------------------+ - -No die domain GPIO -^^^^^^^^^^^^^^^^^^ - -.. _table_inf_signal_pin_fmux_nodie_domain_gpio: -.. table:: No die domain GPIO - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR\ | I/O | PW | 0 | FMUX_GPIO | - | _GPIO[0]| | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | P | 3 | FMUX_GPI | - | _GPIO[3]| | WR_SEQ1 | | O_REG_IOCTRL_PWR_SEQ1 | - | | | | | 0x0300_1084 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | P | 3 | FMUX_GPI | - | _GPIO[4]| | WR_SEQ2 | | O_REG_IOCTRL_PWR_SEQ2 | - | | | | | 0x0300_1088 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | PWR | 3 | FMUX_GPIO_R | - | PIO[6] | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | PWR\ | I/O | PWR | 3 | FMUX_GPIO_R | - | _GPIO[8]| | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | SD1_D3 | 3 | FMUX_G | - | PIO[18] | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | SD1_D2 | 3 | FMUX_G | - | PIO[19] | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | SD1_D1 | 3 | FMUX_G | - | PIO[20] | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | SD1_D0 | 3 | FMUX_G | - | PIO[21] | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | SD1_CMD | 3 | FMUX_GP | - | PIO[22] | | | | IO_REG_IOCTRL_SD1_CMD | - | | | | | 0x0300_10E0 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | SD1_CLK | 3 | FMUX_GP | - | PIO[23] | | | | IO_REG_IOCTRL_SD1_CLK | - | | | | | 0x0300_10E4 | - +---------+---------+---------+--------+-----------------------+ - | PWR_G\ | I/O | GPIO | 3 | FMUX_GP | - | PIO[24] | | _ZQ\_\_ | | IO_REG_IOCTRL_GPIO_ZQ | - | | | _PAD_ZQ | | 0x0300_11D0 | - +---------+---------+---------+--------+-----------------------+ - -Debug -^^^^^ - -.. _table_inf_signal_pin_fmux_debug: -.. table:: Debug - :widths: 1 1 1 1 4 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | DBG[0] | O | SD0_CLK | 7 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD0_CLK | - | | | | | 0x0300_101C | - +---------+---------+---------+--------+-----------------------+ - | DBG[1] | O | SD0_CMD | 7 | FMUX_GP | - | | | | | IO_REG_IOCTRL_SD0_CMD | - | | | | | 0x0300_1020 | - +---------+---------+---------+--------+-----------------------+ - | DBG[10] | O | I | 7 | FMUX_GPI | - | | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | DBG[10] | O | PAD_M | 7 | FMUX_GPIO_RE | - | | | IPIRX0N | | G_IOCTRL_PAD_MIPIRX0N | - | | | | | 0x0300_118C | - +---------+---------+---------+--------+-----------------------+ - | DBG[11] | O | I | 7 | FMUX_GPI | - | | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | DBG[11] | O | PAD_M | 7 | FMUX_GPIO_RE | - | | | IPIRX0P | | G_IOCTRL_PAD_MIPIRX0P | - | | | | | 0x0300_1190 | - +---------+---------+---------+--------+-----------------------+ - | DBG[12] | O | AUX0 | 7 | FMUX | - | | | | | _GPIO_REG_IOCTRL_AUX0 | - | | | | | 0x0300_1078 | - +---------+---------+---------+--------+-----------------------+ - | DBG[12] | O | PAD_MI | 7 | FMUX_GPIO_REG | - | | | PI_TXM0 | | _IOCTRL_PAD_MIPI_TXM0 | - | | | | | 0x0300_11B4 | - +---------+---------+---------+--------+-----------------------+ - | DBG[13] | O | MUX_SP | 7 | FMUX_GPIO_REG | - | | | I1_MOSI | | _IOCTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | DBG[13] | O | PAD_MI | 7 | FMUX_GPIO_REG | - | | | PI_TXP0 | | _IOCTRL_PAD_MIPI_TXP0 | - | | | | | 0x0300_11B8 | - +---------+---------+---------+--------+-----------------------+ - | DBG[14] | O | MUX_SP | 7 | FMUX_GPIO_REG | - | | | I1_MISO | | _IOCTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | DBG[14] | O | PAD_MI | 7 | FMUX_GPIO_REG | - | | | PI_TXM1 | | _IOCTRL_PAD_MIPI_TXM1 | - | | | | | 0x0300_11AC | - +---------+---------+---------+--------+-----------------------+ - | DBG[15] | O | MUX_S | 7 | FMUX_GPIO_RE | - | | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | DBG[15] | O | PAD_MI | 7 | FMUX_GPIO_REG | - | | | PI_TXP1 | | _IOCTRL_PAD_MIPI_TXP1 | - | | | | | 0x0300_11B0 | - +---------+---------+---------+--------+-----------------------+ - | DBG[16] | O | MUX | 7 | FMUX_GPIO_R | - | | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | DBG[2] | O | SD0_D0 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | DBG[3] | O | SD0_D1 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | DBG[4] | O | SD0_D2 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | DBG[5] | O | SD0_D3 | 7 | FMUX_G | - | | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | DBG[6] | O | U | 7 | FMUX_GPI | - | | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | DBG[6] | O | PAD_M | 7 | FMUX_GPIO_RE | - | | | IPIRX2N | | G_IOCTRL_PAD_MIPIRX2N | - | | | | | 0x0300_117C | - +---------+---------+---------+--------+-----------------------+ - | DBG[7] | O | U | 7 | FMUX_GPI | - | | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | DBG[7] | O | PAD_M | 7 | FMUX_GPIO_RE | - | | | IPIRX2P | | G_IOCTRL_PAD_MIPIRX2P | - | | | | | 0x0300_1180 | - +---------+---------+---------+--------+-----------------------+ - | DBG[8] | O | PAD_M | 7 | FMUX_GPIO_RE | - | | | IPIRX1N | | G_IOCTRL_PAD_MIPIRX1N | - | | | | | 0x0300_1184 | - +---------+---------+---------+--------+-----------------------+ - | DBG[9] | O | PAD_M | 7 | FMUX_GPIO_RE | - | | | IPIRX1P | | G_IOCTRL_PAD_MIPIRX1P | - | | | | | 0x0300_1188 | - +---------+---------+---------+--------+-----------------------+ - - -Others -^^^^^^ - -.. _table_inf_signal_pin_fmux_others: -.. table:: Others - :widths: 2 1 1 1 3 - - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | MUX\ | I/O | PAD_M | 7 | FMUX_GPIO_RE | - | _SPI1_CS| | IPIRX4P | | G_IOCTRL_PAD_MIPIRX4P | - | | | | | 0x0300_1170 | - +---------+---------+---------+--------+-----------------------+ - | MUX_SP\ | I/O | PAD_M | 7 | FMUX_GPIO_RE | - | I1_MISO | | IPIRX3N | | G_IOCTRL_PAD_MIPIRX3N | - | | | | | 0x0300_1174 | - +---------+---------+---------+--------+-----------------------+ - | MUX_SP\ | I/O | PAD_M | 7 | FMUX_GPIO_RE | - | I1_MOSI | | IPIRX3P | | G_IOCTRL_PAD_MIPIRX3P | - | | | | | 0x0300_1178 | - +---------+---------+---------+--------+-----------------------+ - | MUX_S\ | I/O | PAD_M | 7 | FMUX_GPIO_RE | - | PI1_SCK | | IPIRX4N | | G_IOCTRL_PAD_MIPIRX4N | - | | | | | 0x0300_116C | - +---------+---------+---------+--------+-----------------------+ - | PK\ | I | PK | 0 | FMUX_GPIO | - | G_TYPE0 | | G_TYPE0 | | _REG_IOCTRL_PKG_TYPE0 | - | | | | | 0x0300_1104 | - +---------+---------+---------+--------+-----------------------+ - | PK\ | I | PK | 0 | FMUX_GPIO | - | G_TYPE1 | | G_TYPE1 | | _REG_IOCTRL_PKG_TYPE1 | - | | | | | 0x0300_110C | - +---------+---------+---------+--------+-----------------------+ - | PK\ | I | PK | 0 | FMUX_GPIO | - | G_TYPE2 | | G_TYPE2 | | _REG_IOCTRL_PKG_TYPE2 | - | | | | | 0x0300_1110 | - +---------+---------+---------+--------+-----------------------+ diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_description.table.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_description.table.rst deleted file mode 100644 index 848bfdb..0000000 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_description.table.rst +++ /dev/null @@ -1,2301 +0,0 @@ -IOBLK_G1_REG_PWM0_BUCK -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g1_reg_pwm0_buck: -.. table:: IOBLK_G1_REG_PWM0_BUCK - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | G1_REG_PWM0_BUCK_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x0 | Pull-down resistor enable. | - | G1_REG_PWM0_BUCK_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 1_REG_PWM0_BUCK_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 1_REG_PWM0_BUCK_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 1_REG_PWM0_BUCK_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 9 | 0x0 | Input Schmitt trigger | - | 1_REG_PWM0_BUCK_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Weak level holder (Bus | - | G1_REG_PWM0_BUCK_HE | 0 | | holder) enable. 0=Disabled; | - | | | | 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G1_REG_PWM0_BUCK_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G1_REG_ADC1 -^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g1_reg_adc1: -.. table:: IOBLK_G1_REG_ADC1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | I\ | 2 | 0x0 | Pull-up resistor enable. | - | OBLK_G1_REG_ADC1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | I\ | 3 | 0x1 | Pull-down resistor enable. | - | OBLK_G1_REG_ADC1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IO\ | 5 | 0x0 | Output drive strength | - | BLK_G1_REG_ADC1_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IO\ | 6 | 0x1 | Output drive strength | - | BLK_G1_REG_ADC1_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IO\ | 8 | 0x0 | Input Schmitt trigger | - | BLK_G1_REG_ADC1_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IO\ | 9 | 0x0 | Input Schmitt trigger | - | BLK_G1_REG_ADC1_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-----------------------------+ - | I\ | 1\| 0x0 | Weak level holder (Bus | - | OBLK_G1_REG_ADC1_HE | 0 | | holder) enable. 0=Disabled; | - | | | | 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | I\ | 1\| 0x0 | Output level transition | - | OBLK_G1_REG_ADC1_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G1_REG_PKG_TYPE0 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g1_reg_pkg_type0: -.. table:: IOBLK_G1_REG_PKG_TYPE0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x1 | Pull-up resistor enable. | - | G1_REG_PKG_TYPE0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x0 | Pull-down resistor enable. | - | G1_REG_PKG_TYPE0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 1_REG_PKG_TYPE0_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 1_REG_PKG_TYPE0_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 1_REG_PKG_TYPE0_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 9 | 0x0 | Input Schmitt trigger | - | 1_REG_PKG_TYPE0_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Weak level holder (Bus | - | G1_REG_PKG_TYPE0_HE | 0 | | holder) enable. 0=Disabled; | - | | | | 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G1_REG_PKG_TYPE0_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G1_REG_USB_VBUS_DET -^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g1_reg_usb_vbus_det: -.. table:: IOBLK_G1_REG_USB_VBUS_DET - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G1\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_USB_VBUS_DET_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1\_\ | 3 | 0x0 | Pull-down resistor enable. | - | REG_USB_VBUS_DET_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_USB_VBUS_DET_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_USB_VBUS_DET_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1_R\ | 8 | 0x0 | Input Schmitt trigger strength | - | EG_USB_VBUS_DET_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1_R\ | 9 | 0x0 | Input Schmitt trigger strength | - | EG_USB_VBUS_DET_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_USB_VBUS_DET_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G1\_\ | 1\| 0x0 | Output level transition rate limit. | - | REG_USB_VBUS_DET_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G1_REG_PKG_TYPE1 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g1_reg_pkg_type1: -.. table:: IOBLK_G1_REG_PKG_TYPE1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x1 | Pull-up resistor enable. | - | G1_REG_PKG_TYPE1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x0 | Pull-down resistor enable. | - | G1_REG_PKG_TYPE1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 1_REG_PKG_TYPE1_DS0 | | | level bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 1_REG_PKG_TYPE1_DS1 | | | level bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 1_REG_PKG_TYPE1_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 9 | 0x0 | Input Schmitt trigger | - | 1_REG_PKG_TYPE1_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Weak level holder (Bus | - | G1_REG_PKG_TYPE1_HE | 0 | | holder) enable. 0=Disabled; | - | | | | 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G1_REG_PKG_TYPE1_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G1_REG_PKG_TYPE2 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g1_reg_pkg_type2: -.. table:: IOBLK_G1_REG_PKG_TYPE2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK_G1\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_USB_VBUS_DET_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1\_\ | 3 | 0x0 | Pull-down resistor enable. | - | REG_USB_VBUS_DET_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1_R\ | 5 | 0x0 | Output drive strength | - | EG_USB_VBUS_DET_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1_R\ | 6 | 0x1 | Output drive strength | - | EG_USB_VBUS_DET_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_USB_VBUS_DET_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_USB_VBUS_DET_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1\_\ | 1\| 0x0 | Weak level holder (Bus | - | REG_USB_VBUS_DET_HE | 0 | | holder) enable. 0=Disabled; | - | | | | 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G1\_\ | 1\| 0x0 | Output level transition | - | REG_USB_VBUS_DET_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_SD0_CD -^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_sd0_cd: -.. table:: IOBLK_G7_REG_SD0_CD - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOB\ | 2 | 0x1 | Pull-up resistor enable. | - | LK_G7_REG_SD0_CD_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOB\ | 3 | 0x0 | Pull-down resistor enable. | - | LK_G7_REG_SD0_CD_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 5 | 0x0 | Output drive strength | - | K_G7_REG_SD0_CD_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 6 | 0x1 | Output drive strength | - | K_G7_REG_SD0_CD_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 7 | 0x0 | Output drive strength | - | K_G7_REG_SD0_CD_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 8 | 0x0 | Input Schmitt trigger | - | K_G7_REG_SD0_CD_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOB\ | 1\| 0x0 | Output level transition | - | LK_G7_REG_SD0_CD_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_SD0_PWR_EN -^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_sd0_pwr_en: -.. table:: IOBLK_G7_REG_SD0_PWR_EN - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK_G\ | 2 | 0x0 | Pull-up resistor enable. | - | 7_REG_SD0_PWR_EN_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 3 | 0x1 | Pull-down resistor enable. | - | 7_REG_SD0_PWR_EN_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\ | 5 | 0x0 | Output drive strength | - | _REG_SD0_PWR_EN_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\ | 6 | 0x1 | Output drive strength | - | _REG_SD0_PWR_EN_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\ | 7 | 0x0 | Output drive strength | - | _REG_SD0_PWR_EN_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\ | 8 | 0x0 | Input Schmitt trigger | - | _REG_SD0_PWR_EN_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 1\| 0x0 | Output level transition | - | 7_REG_SD0_PWR_EN_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_SPK_EN -^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_spk_en: -.. table:: IOBLK_G7_REG_SPK_EN - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOB\ | 2 | 0x0 | Pull-up resistor enable. | - | LK_G7_REG_SPK_EN_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOB\ | 3 | 0x1 | Pull-down resistor enable. | - | LK_G7_REG_SPK_EN_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 5 | 0x0 | Output drive strength | - | K_G7_REG_SPK_EN_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 6 | 0x1 | Output drive strength | - | K_G7_REG_SPK_EN_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 7 | 0x0 | Output drive strength | - | K_G7_REG_SPK_EN_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 8 | 0x0 | Input Schmitt trigger | - | K_G7_REG_SPK_EN_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOB\ | 1\| 0x0 | Output level transition | - | LK_G7_REG_SPK_EN_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_UART0_TX -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_uart0_tx: -.. table:: IOBLK_G7_REG_UART0_TX - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x1 | Pull-up resistor enable. | - | _G7_REG_UART0_TX_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x0 | Pull-down resistor enable. | - | _G7_REG_UART0_TX_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G7_REG_UART0_TX_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G7_REG_UART0_TX_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G7_REG_UART0_TX_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_UART0_TX_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | _G7_REG_UART0_TX_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_UART0_RX -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_uart0_rx: -.. table:: IOBLK_G7_REG_UART0_RX - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x1 | Pull-up resistor enable. | - | _G7_REG_UART0_RX_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x0 | Pull-down resistor enable. | - | _G7_REG_UART0_RX_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G7_REG_UART0_RX_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G7_REG_UART0_RX_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G7_REG_UART0_RX_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_UART0_RX_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | _G7_REG_UART0_RX_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_EMMC_DAT2 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_emmc_dat2: -.. table:: IOBLK_G7_REG_EMMC_DAT2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | G7_REG_EMMC_DAT2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x1 | Pull-down resistor enable. | - | G7_REG_EMMC_DAT2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT2_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 7_REG_EMMC_DAT2_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 7 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT2_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 7_REG_EMMC_DAT2_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G7_REG_EMMC_DAT2_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_EMMC_CLK -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_emmc_clk: -.. table:: IOBLK_G7_REG_EMMC_CLK - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | _G7_REG_EMMC_CLK_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | _G7_REG_EMMC_CLK_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G7_REG_EMMC_CLK_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G7_REG_EMMC_CLK_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G7_REG_EMMC_CLK_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_EMMC_CLK_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | _G7_REG_EMMC_CLK_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_EMMC_DAT0 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_emmc_dat0: -.. table:: IOBLK_G7_REG_EMMC_DAT0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x1 | Pull-up resistor enable. | - | G7_REG_EMMC_DAT0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x0 | Pull-down resistor enable. | - | G7_REG_EMMC_DAT0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT0_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 7_REG_EMMC_DAT0_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 7 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT0_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 7_REG_EMMC_DAT0_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G7_REG_EMMC_DAT0_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_EMMC_DAT3 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_emmc_dat3: -.. table:: IOBLK_G7_REG_EMMC_DAT3 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x1 | Pull-up resistor enable. | - | G7_REG_EMMC_DAT3_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x0 | Pull-down resistor enable. | - | G7_REG_EMMC_DAT3_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT3_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 7_REG_EMMC_DAT3_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 7 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT3_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 7_REG_EMMC_DAT3_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G7_REG_EMMC_DAT3_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_EMMC_CMD -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_emmc_cmd: -.. table:: IOBLK_G7_REG_EMMC_CMD - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x1 | Pull-up resistor enable. | - | _G7_REG_EMMC_CMD_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x0 | Pull-down resistor enable. | - | _G7_REG_EMMC_CMD_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G7_REG_EMMC_CMD_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G7_REG_EMMC_CMD_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G7_REG_EMMC_CMD_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_EMMC_CMD_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | _G7_REG_EMMC_CMD_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_EMMC_DAT1 -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_emmc_dat1: -.. table:: IOBLK_G7_REG_EMMC_DAT1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | G7_REG_EMMC_DAT1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 3 | 0x1 | Pull-down resistor enable. | - | G7_REG_EMMC_DAT1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT1_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength | - | 7_REG_EMMC_DAT1_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 7 | 0x0 | Output drive strength | - | 7_REG_EMMC_DAT1_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger | - | 7_REG_EMMC_DAT1_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition | - | G7_REG_EMMC_DAT1_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_JTAG_CPU_TMS -^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_jtag_cpu_tms: -.. table:: IOBLK_G7_REG_JTAG_CPU_TMS - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK_G7\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_JTAG_CPU_TMS_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_JTAG_CPU_TMS_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 5 | 0x0 | Output drive strength | - | EG_JTAG_CPU_TMS_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 6 | 0x1 | Output drive strength | - | EG_JTAG_CPU_TMS_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 7 | 0x0 | Output drive strength | - | EG_JTAG_CPU_TMS_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_JTAG_CPU_TMS_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\_\ | 1\| 0x0 | Output level transition | - | REG_JTAG_CPU_TMS_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_JTAG_CPU_TCK -^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_jtag_cpu_tck: -.. table:: IOBLK_G7_REG_JTAG_CPU_TCK - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK_G7\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_JTAG_CPU_TCK_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_JTAG_CPU_TCK_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 5 | 0x0 | Output drive strength | - | EG_JTAG_CPU_TCK_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 6 | 0x1 | Output drive strength | - | EG_JTAG_CPU_TCK_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 7 | 0x0 | Output drive strength | - | EG_JTAG_CPU_TCK_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_JTAG_CPU_TCK_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK_G7\_\ | 1\| 0x0 | Output level transition | - | REG_JTAG_CPU_TCK_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_IIC0_SCL -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_iic0_scl: -.. table:: IOBLK_G7_REG_IIC0_SCL - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x1 | Pull-up resistor enable. | - | _G7_REG_IIC0_SCL_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x0 | Pull-down resistor enable. | - | _G7_REG_IIC0_SCL_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G7_REG_IIC0_SCL_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G7_REG_IIC0_SCL_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G7_REG_IIC0_SCL_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_IIC0_SCL_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | _G7_REG_IIC0_SCL_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_IIC0_SDA -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_iic0_sda: -.. table:: IOBLK_G7_REG_IIC0_SDA - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x1 | Pull-up resistor enable. | - | _G7_REG_IIC0_SDA_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x0 | Pull-down resistor enable. | - | _G7_REG_IIC0_SDA_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G7_REG_IIC0_SDA_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G7_REG_IIC0_SDA_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G7_REG_IIC0_SDA_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_IIC0_SDA_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | _G7_REG_IIC0_SDA_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G7_REG_AUX0 -^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g7_reg_aux0: -.. table:: IOBLK_G7_REG_AUX0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | G7_REG_AUX0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | G7_REG_AUX0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 5 | 0x0 | Output drive strength | - | G7_REG_AUX0_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 6 | 0x1 | Output drive strength | - | G7_REG_AUX0_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 7 | 0x0 | Output drive strength | - | G7_REG_AUX0_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 8 | 0x0 | Input Schmitt trigger | - | G7_REG_AUX0_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | G7_REG_AUX0_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G10_REG_SD0_CLK -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g10_reg_sd0_clk: -.. table:: IOBLK_G10_REG_SD0_CLK - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | G10_REG_SD0_CLK_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | G10_REG_SD0_CLK_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G10_REG_SD0_CLK_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G10_REG_SD0_CLK_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G10_REG_SD0_CLK_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G10_REG_SD0_CLK_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | G10_REG_SD0_CLK_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G10_REG_SD0_CMD -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g10_reg_sd0_cmd: -.. table:: IOBLK_G10_REG_SD0_CMD - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | G10_REG_SD0_CMD_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | G10_REG_SD0_CMD_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength | - | G10_REG_SD0_CMD_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength | - | G10_REG_SD0_CMD_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength | - | G10_REG_SD0_CMD_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger | - | G10_REG_SD0_CMD_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition | - | G10_REG_SD0_CMD_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G10_REG_SD0_D0 -^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g10_reg_sd0_d0: -.. table:: IOBLK_G10_REG_SD0_D0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBL\ | 2 | 0x0 | Pull-up resistor enable. | - | K_G10_REG_SD0_D0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 3 | 0x1 | Pull-down resistor enable. | - | K_G10_REG_SD0_D0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 5 | 0x0 | Output drive strength | - | _G10_REG_SD0_D0_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 6 | 0x1 | Output drive strength | - | _G10_REG_SD0_D0_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 7 | 0x0 | Output drive strength | - | _G10_REG_SD0_D0_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 8 | 0x0 | Input Schmitt trigger | - | _G10_REG_SD0_D0_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 1\| 0x0 | Output level transition | - | K_G10_REG_SD0_D0_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G10_REG_SD0_D1 -^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g10_reg_sd0_d1: -.. table:: IOBLK_G10_REG_SD0_D1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBL\ | 2 | 0x0 | Pull-up resistor enable. | - | K_G10_REG_SD0_D1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 3 | 0x1 | Pull-down resistor enable. | - | K_G10_REG_SD0_D1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 5 | 0x0 | Output drive strength | - | _G10_REG_SD0_D1_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 6 | 0x1 | Output drive strength | - | _G10_REG_SD0_D1_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 7 | 0x0 | Output drive strength | - | _G10_REG_SD0_D1_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 8 | 0x0 | Input Schmitt trigger | - | _G10_REG_SD0_D1_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 1\| 0x0 | Output level transition | - | K_G10_REG_SD0_D1_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G10_REG_SD0_D2 -^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g10_reg_sd0_d2: -.. table:: IOBLK_G10_REG_SD0_D2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBL\ | 2 | 0x0 | Pull-up resistor enable. | - | K_G10_REG_SD0_D2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 3 | 0x1 | Pull-down resistor enable. | - | K_G10_REG_SD0_D2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 5 | 0x0 | Output drive strength | - | _G10_REG_SD0_D2_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 6 | 0x1 | Output drive strength | - | _G10_REG_SD0_D2_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 7 | 0x0 | Output drive strength | - | _G10_REG_SD0_D2_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 8 | 0x0 | Input Schmitt trigger | - | _G10_REG_SD0_D2_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 1\| 0x0 | Output level transition | - | K_G10_REG_SD0_D2_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G10_REG_SD0_D3 -^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g10_reg_sd0_d3: -.. table:: IOBLK_G10_REG_SD0_D3 - :widths: 4 1 1 3 - - +---------------------+---+-------+-----------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=============================+ - | IOBL\ | 2 | 0x0 | Pull-up resistor enable. | - | K_G10_REG_SD0_D3_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 3 | 0x1 | Pull-down resistor enable. | - | K_G10_REG_SD0_D3_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 5 | 0x0 | Output drive strength | - | _G10_REG_SD0_D3_DS0 | | | level, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 6 | 0x1 | Output drive strength | - | _G10_REG_SD0_D3_DS1 | | | level, bit 1 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 7 | 0x0 | Output drive strength | - | _G10_REG_SD0_D3_DS2 | | | level, bit 2 | - +---------------------+---+-------+-----------------------------+ - | IOBLK\ | 8 | 0x0 | Input Schmitt trigger | - | _G10_REG_SD0_D3_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-----------------------------+ - | IOBL\ | 1\| 0x0 | Output level transition | - | K_G10_REG_SD0_D3_SL | 1 | | rate limit. 0=Disabled | - | | | | (faster); 1=Enabled (slower)| - +---------------------+---+-------+-----------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX4N -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx4n: -.. table:: IOBLK_G12_REG_PAD_MIPIRX4N - :widths: 4 1 1 3 - - +---------------------+---+-------+------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX4N_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX4N_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength | - | EG_PAD_MIPIRX4N_DS0 | | | level, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength | - | EG_PAD_MIPIRX4N_DS1 | | | level, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX4N_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX4N_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX4N_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit.| - | REG_PAD_MIPIRX4N_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX4P -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx4p: -.. table:: IOBLK_G12_REG_PAD_MIPIRX4P - :widths: 4 1 1 3 - - +---------------------+---+-------+------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX4P_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX4P_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength | - | EG_PAD_MIPIRX4P_DS0 | | | level, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength | - | EG_PAD_MIPIRX4P_DS1 | | | level, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX4P_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX4P_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX4P_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit.| - | REG_PAD_MIPIRX4P_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX3N -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx3n: -.. table:: IOBLK_G12_REG_PAD_MIPIRX3N - :widths: 4 1 1 3 - - +---------------------+---+-------+------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX3N_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX3N_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength | - | EG_PAD_MIPIRX3N_DS0 | | | level, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength | - | EG_PAD_MIPIRX3N_DS1 | | | level, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX3N_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX3N_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX3N_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit.| - | REG_PAD_MIPIRX3N_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX3P -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx3p: -.. table:: IOBLK_G12_REG_PAD_MIPIRX3P - :widths: 4 1 1 3 - - +---------------------+---+-------+------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX3P_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX3P_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PAD_MIPIRX3P_DS0 | | | | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PAD_MIPIRX3P_DS1 | | | | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX3P_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX3P_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX3P_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit.| - | REG_PAD_MIPIRX3P_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX2N -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx2n: -.. table:: IOBLK_G12_REG_PAD_MIPIRX2N - :widths: 4 1 1 3 - - +---------------------+---+-------+------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX2N_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX2N_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PAD_MIPIRX2N_DS0 | | | | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PAD_MIPIRX2N_DS1 | | | | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX2N_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX2N_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX2N_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit.| - | REG_PAD_MIPIRX2N_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX2P -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx2p: -.. table:: IOBLK_G12_REG_PAD_MIPIRX2P - :widths: 4 1 1 3 - - +---------------------+---+-------+------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX2P_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX2P_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PAD_MIPIRX2P_DS0 | | | | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PAD_MIPIRX2P_DS1 | | | | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX2P_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX2P_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX2P_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit.| - | REG_PAD_MIPIRX2P_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX1N -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx1n: -.. table:: IOBLK_G12_REG_PAD_MIPIRX1N - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX1N_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX1N_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PAD_MIPIRX1N_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PAD_MIPIRX1N_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger strength | - | EG_PAD_MIPIRX1N_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger strength | - | EG_PAD_MIPIRX1N_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX1N_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit. | - | REG_PAD_MIPIRX1N_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX1P -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx1p: -.. table:: IOBLK_G12_REG_PAD_MIPIRX1P - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX1P_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX1P_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PAD_MIPIRX1P_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PAD_MIPIRX1P_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX1P_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX1P_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX1P_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit. | - | REG_PAD_MIPIRX1P_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX0N -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx0n: -.. table:: IOBLK_G12_REG_PAD_MIPIRX0N - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX0N_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX0N_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PAD_MIPIRX0N_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PAD_MIPIRX0N_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX0N_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger | - | EG_PAD_MIPIRX0N_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX0N_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate limit. | - | REG_PAD_MIPIRX0N_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPIRX0P -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipirx0p: -.. table:: IOBLK_G12_REG_PAD_MIPIRX0P - :widths: 4 1 1 3 - - +---------------------+---+-------+--------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+================================+ - | IOBLK_G12\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PAD_MIPIRX0P_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12\_\ | 3 | 0x1 | Pull-down resistor enable. | - | REG_PAD_MIPIRX0P_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 5 | 0x0 | Output drive strength level, | - | EG_PAD_MIPIRX0P_DS0 | | | bit 0 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 6 | 0x1 | Output drive strength level, | - | EG_PAD_MIPIRX0P_DS1 | | | bit 1 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 8 | 0x0 | Input Schmitt trigger strength | - | EG_PAD_MIPIRX0P_ST0 | | | control, bit 0 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 9 | 0x0 | Input Schmitt trigger strength | - | EG_PAD_MIPIRX0P_ST1 | | | control, bit 1 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PAD_MIPIRX0P_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12\_\ | 1\| 0x0 | Output level transition rate | - | REG_PAD_MIPIRX0P_SL | 1 | | limit. 0=Disabled (faster); | - | | | | 1=Enabled (slower) | - +---------------------+---+-------+--------------------------------+ - - -IOBLK_G12_REG_PAD_MIPI_TXM2 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipi_txm2: -.. table:: IOBLK_G12_REG_PAD_MIPI_TXM2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12_R\ | 2 | 0x0 | Pull-up resistor enable. | - | EG_PAD_MIPI_TXM2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 3 | 0x1 | Pull-down resistor enable. | - | EG_PAD_MIPI_TXM2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 5 | 0x0 | Output drive strength level, bit 0 | - | G_PAD_MIPI_TXM2_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 6 | 0x1 | Output drive strength level, bit 1 | - | G_PAD_MIPI_TXM2_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 8 | 0x0 | Input Schmitt trigger | - | G_PAD_MIPI_TXM2_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 9 | 0x0 | Input Schmitt trigger | - | G_PAD_MIPI_TXM2_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Weak bus holder enable. | - | EG_PAD_MIPI_TXM2_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Output level transition rate limit. | - | EG_PAD_MIPI_TXM2_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPI_TXP2 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipi_txp2: -.. table:: IOBLK_G12_REG_PAD_MIPI_TXP2 - :widths: 4 1 1 3 - - +---------------------+---+-------+--------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+================================+ - | IOBLK_G12_R\ | 2 | 0x0 | Pull-up resistor enable. | - | EG_PAD_MIPI_TXP2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 3 | 0x1 | Pull-down resistor enable. | - | EG_PAD_MIPI_TXP2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_RE\ | 5 | 0x0 | Output drive strength level, | - | G_PAD_MIPI_TXP2_DS0 | | | bit 0 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_RE\ | 6 | 0x1 | Output drive strength level, | - | G_PAD_MIPI_TXP2_DS1 | | | bit 1 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_RE\ | 8 | 0x0 | Input Schmitt trigger | - | G_PAD_MIPI_TXP2_ST0 | | | strength control, bit 0 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_RE\ | 9 | 0x0 | Input Schmitt trigger | - | G_PAD_MIPI_TXP2_ST1 | | | strength control, bit 1 | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Weak bus holder enable. | - | EG_PAD_MIPI_TXP2_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+--------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Output level transition rate | - | EG_PAD_MIPI_TXP2_SL | 1 | | limit. 0=Disabled (faster); | - | | | | 1=Enabled (slower) | - +---------------------+---+-------+--------------------------------+ - -IOBLK_G12_REG_PAD_MIPI_TXM1 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipi_txm1: -.. table:: IOBLK_G12_REG_PAD_MIPI_TXM1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12_R\ | 2 | 0x0 | Pull-up resistor enable. | - | EG_PAD_MIPI_TXM1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 3 | 0x1 | Pull-down resistor enable. | - | EG_PAD_MIPI_TXM1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 5 | 0x0 | Output drive strength level, bit 0 | - | G_PAD_MIPI_TXM1_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 6 | 0x1 | Output drive strength level, bit 1 | - | G_PAD_MIPI_TXM1_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 8 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXM1_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 9 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXM1_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Weak bus holder enable. | - | EG_PAD_MIPI_TXM1_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Output level transition rate limit. | - | EG_PAD_MIPI_TXM1_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPI_TXP1 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipi_txp1: -.. table:: IOBLK_G12_REG_PAD_MIPI_TXP1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12_R\ | 2 | 0x0 | Pull-up resistor enable. | - | EG_PAD_MIPI_TXP1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 3 | 0x1 | Pull-down resistor enable. | - | EG_PAD_MIPI_TXP1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 5 | 0x0 | Output drive strength level, bit 0 | - | G_PAD_MIPI_TXP1_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 6 | 0x1 | Output drive strength level, bit 1 | - | G_PAD_MIPI_TXP1_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 8 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXP1_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 9 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXP1_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Weak bus holder enable. | - | EG_PAD_MIPI_TXP1_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Output level transition rate limit. | - | EG_PAD_MIPI_TXP1_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPI_TXM0 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipi_txm0: -.. table:: IOBLK_G12_REG_PAD_MIPI_TXM0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12_R\ | 2 | 0x0 | Pull-up resistor enable. | - | EG_PAD_MIPI_TXM0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 3 | 0x1 | Pull-down resistor enable. | - | EG_PAD_MIPI_TXM0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 5 | 0x0 | Output drive strength level, bit 0 | - | G_PAD_MIPI_TXM0_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 6 | 0x1 | Output drive strength level, bit 1 | - | G_PAD_MIPI_TXM0_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 8 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXM0_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 9 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXM0_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Weak bus holder enable. | - | EG_PAD_MIPI_TXM0_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Output level transition rate limit. | - | EG_PAD_MIPI_TXM0_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_PAD_MIPI_TXP0 -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_pad_mipi_txp0: -.. table:: IOBLK_G12_REG_PAD_MIPI_TXP0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G12_R\ | 2 | 0x0 | Pull-up resistor enable. | - | EG_PAD_MIPI_TXP0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 3 | 0x1 | Pull-down resistor enable. | - | EG_PAD_MIPI_TXP0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 5 | 0x0 | Output drive strength level, bit 0 | - | G_PAD_MIPI_TXP0_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 6 | 0x1 | Output drive strength level, bit 1 | - | G_PAD_MIPI_TXP0_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 8 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXP0_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_RE\ | 9 | 0x0 | Input Schmitt trigger strength | - | G_PAD_MIPI_TXP0_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Weak bus holder enable. | - | EG_PAD_MIPI_TXP0_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G12_R\ | 1\| 0x0 | Output level transition rate limit. | - | EG_PAD_MIPI_TXP0_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_G12_REG_GPIO_RTX -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_g12_reg_gpio_rtx: -.. table:: IOBLK_G12_REG_GPIO_RTX - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | G12_REG_GPIO_RTX_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 3 | 0x1 | Pull-down resistor enable. | - | G12_REG_GPIO_RTX_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength level, bit 0 | - | 12_REG_GPIO_RTX_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength level, bit 1 | - | 12_REG_GPIO_RTX_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger strength | - | 12_REG_GPIO_RTX_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 9 | 0x0 | Input Schmitt trigger strength | - | 12_REG_GPIO_RTX_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 1\| 0x0 | Weak bus holder enable. | - | G12_REG_GPIO_RTX_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition rate limit. | - | G12_REG_GPIO_RTX_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_VBAT_DET -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_vbat_det: -.. table:: IOBLK_GRTC_REG_PWR_VBAT_DET - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GRTC\_\ | 2 | 0x0 | Pull-up resistor enable. | - | REG_PWR_VBAT_DET_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 3 | 0x0 | Pull-down resistor enable. | - | REG_PWR_VBAT_DET_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC_R\ | 5 | 0x0 | Output drive strength level, bit 0 | - | EG_PWR_VBAT_DET_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC_R\ | 6 | 0x1 | Output drive strength level, bit 1 | - | EG_PWR_VBAT_DET_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC_R\ | 8 | 0x0 | Input Schmitt trigger strength | - | EG_PWR_VBAT_DET_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC_R\ | 9 | 0x0 | Input Schmitt trigger strength | - | EG_PWR_VBAT_DET_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 1\| 0x0 | Weak bus holder enable. | - | REG_PWR_VBAT_DET_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 1\| 0x0 | Output level transition rate limit. | - | REG_PWR_VBAT_DET_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_RSTN -^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_rstn: -.. table:: IOBLK_GRTC_REG_PWR_RSTN - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G\ | 2 | 0x1 | Pull-up resistor enable. | - | RTC_REG_PWR_RSTN_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 3 | 0x0 | Pull-down resistor enable. | - | RTC_REG_PWR_RSTN_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 5 | 0x0 | Output drive strength level, bit 0 | - | TC_REG_PWR_RSTN_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 6 | 0x1 | Output drive strength level, bit 1 | - | TC_REG_PWR_RSTN_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 8 | 0x0 | Input Schmitt trigger strength | - | TC_REG_PWR_RSTN_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 9 | 0x0 | Input Schmitt trigger strength | - | TC_REG_PWR_RSTN_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 1\| 0x0 | Weak bus holder enable. | - | RTC_REG_PWR_RSTN_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 1\| 0x0 | Output level transition rate limit. | - | RTC_REG_PWR_RSTN_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_SEQ1 -^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_seq1: -.. table:: IOBLK_GRTC_REG_PWR_SEQ1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G\ | 2 | 0x0 | Pull-up resistor enable. | - | RTC_REG_PWR_SEQ1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 3 | 0x1 | Pull-down resistor enable. | - | RTC_REG_PWR_SEQ1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 5 | 0x0 | Output drive strength level, bit 0 | - | TC_REG_PWR_SEQ1_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 6 | 0x1 | Output drive strength level, bit 1 | - | TC_REG_PWR_SEQ1_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 8 | 0x0 | Input Schmitt trigger strength | - | TC_REG_PWR_SEQ1_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 9 | 0x0 | Input Schmitt trigger strength | - | TC_REG_PWR_SEQ1_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 1\| 0x0 | Weak bus holder enable. | - | RTC_REG_PWR_SEQ1_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 1\| 0x0 | Output level transition rate limit. | - | RTC_REG_PWR_SEQ1_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_SEQ2 -^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_seq2: -.. table:: IOBLK_GRTC_REG_PWR_SEQ2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_G\ | 2 | 0x0 | Pull-up resistor enable. | - | RTC_REG_PWR_SEQ2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 3 | 0x1 | Pull-down resistor enable. | - | RTC_REG_PWR_SEQ2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 5 | 0x0 | Output drive strength level, bit 0 | - | TC_REG_PWR_SEQ2_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 6 | 0x1 | Output drive strength level, bit 1 | - | TC_REG_PWR_SEQ2_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 8 | 0x0 | Input Schmitt trigger strength | - | TC_REG_PWR_SEQ2_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 9 | 0x0 | Input Schmitt trigger strength | - | TC_REG_PWR_SEQ2_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 1\| 0x0 | Weak bus holder enable. | - | RTC_REG_PWR_SEQ2_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 1\| 0x0 | Output level transition rate limit. | - | RTC_REG_PWR_SEQ2_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PTEST -^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_ptest: -.. table:: IOBLK_GRTC_REG_PTEST - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBL\ | 2 | 0x0 | Pull-up resistor enable. | - | K_GRTC_REG_PTEST_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBL\ | 3 | 0x1 | Pull-down resistor enable. | - | K_GRTC_REG_PTEST_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 5 | 0x0 | Output drive strength level, bit 0 | - | _GRTC_REG_PTEST_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 6 | 0x1 | Output drive strength level, bit 1 | - | _GRTC_REG_PTEST_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 8 | 0x0 | Input Schmitt trigger strength | - | _GRTC_REG_PTEST_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 9 | 0x0 | Input Schmitt trigger strength | - | _GRTC_REG_PTEST_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBL\ | 1\| 0x0 | Weak bus holder enable. | - | K_GRTC_REG_PTEST_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBL\ | 1\| 0x0 | Output level transition rate limit. | - | K_GRTC_REG_PTEST_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_WAKEUP0 -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_wakeup0: -.. table:: IOBLK_GRTC_REG_PWR_WAKEUP0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GRTC\ | 2 | 0x0 | Pull-up resistor enable. | - | _REG_PWR_WAKEUP0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\ | 3 | 0x1 | Pull-down resistor enable. | - | _REG_PWR_WAKEUP0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 5 | 0x0 | Output drive strength level, bit 0 | - | REG_PWR_WAKEUP0_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 6 | 0x1 | Output drive strength level, bit 1 | - | REG_PWR_WAKEUP0_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 8 | 0x0 | Input Schmitt trigger strength | - | REG_PWR_WAKEUP0_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 9 | 0x0 | Input Schmitt trigger strength | - | REG_PWR_WAKEUP0_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\ | 1\| 0x0 | Weak bus holder enable. | - | _REG_PWR_WAKEUP0_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\ | 1\| 0x0 | Output level transition rate limit. | - | _REG_PWR_WAKEUP0_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_BUTTON1 -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_button1: -.. table:: IOBLK_GRTC_REG_PWR_BUTTON1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GRTC\ | 2 | 0x1 | Pull-up resistor enable. | - | _REG_PWR_BUTTON1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\ | 3 | 0x0 | Pull-down resistor enable. | - | _REG_PWR_BUTTON1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 5 | 0x0 | Output drive strength level, bit 0 | - | REG_PWR_BUTTON1_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 6 | 0x1 | Output drive strength level, bit 1 | - | REG_PWR_BUTTON1_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 8 | 0x0 | Input Schmitt trigger strength | - | REG_PWR_BUTTON1_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\_\ | 9 | 0x0 | Input Schmitt trigger strength | - | REG_PWR_BUTTON1_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\ | 1\| 0x0 | Weak bus holder enable. | - | _REG_PWR_BUTTON1_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRTC\ | 1\| 0x0 | Output level transition rate limit. | - | _REG_PWR_BUTTON1_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_XTAL_XIN -^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_xtal_xin: -.. table:: IOBLK_GRTC_REG_XTAL_XIN - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GRT\ | 1 | 0x0 | Crystal oscillator output | - | C_REG_XTAL_XIN_XDS0 | 4 | | drive strength level, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 1 | 0x0 | Crystal oscillator output | - | C_REG_XTAL_XIN_XDS1 | 5 | | drive strength level, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 1 | 0x1 | Crystal oscillator output | - | C_REG_XTAL_XIN_XDS2 | 6 | | drive strength level, bit 2 | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_GPIO0 -^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_gpio0: -.. table:: IOBLK_GRTC_REG_PWR_GPIO0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GR\ | 2 | 0x0 | Pull-up resistor enable. | - | TC_REG_PWR_GPIO0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 3 | 0x1 | Pull-down resistor enable. | - | TC_REG_PWR_GPIO0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 5 | 0x0 | Output drive strength level, bit 0 | - | C_REG_PWR_GPIO0_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 6 | 0x1 | Output drive strength level, bit 1 | - | C_REG_PWR_GPIO0_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 8 | 0x0 | Input Schmitt trigger strength | - | C_REG_PWR_GPIO0_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 9 | 0x0 | Input Schmitt trigger strength | - | C_REG_PWR_GPIO0_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 1\| 0x0 | Weak bus holder enable. | - | TC_REG_PWR_GPIO0_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 1\| 0x0 | Output level transition rate limit. | - | TC_REG_PWR_GPIO0_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_GPIO1 -^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_gpio1: -.. table:: IOBLK_GRTC_REG_PWR_GPIO1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GR\ | 2 | 0x0 | Pull-up resistor enable. | - | TC_REG_PWR_GPIO1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 3 | 0x1 | Pull-down resistor enable. | - | TC_REG_PWR_GPIO1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 5 | 0x0 | Output drive strength level, bit 0 | - | C_REG_PWR_GPIO1_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 6 | 0x1 | Output drive strength level, bit 1 | - | C_REG_PWR_GPIO1_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 8 | 0x0 | Input Schmitt trigger strength | - | C_REG_PWR_GPIO1_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 9 | 0x0 | Input Schmitt trigger strength | - | C_REG_PWR_GPIO1_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 1\| 0x0 | Weak bus holder enable. | - | TC_REG_PWR_GPIO1_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 1\| 0x0 | Output level transition rate limit. | - | TC_REG_PWR_GPIO1_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_PWR_GPIO2 -^^^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_pwr_gpio2: -.. table:: IOBLK_GRTC_REG_PWR_GPIO2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK_GR\ | 2 | 0x0 | Pull-up resistor enable. | - | TC_REG_PWR_GPIO2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 3 | 0x1 | Pull-down resistor enable. | - | TC_REG_PWR_GPIO2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 5 | 0x0 | Output drive strength level, bit 0 | - | C_REG_PWR_GPIO2_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 6 | 0x1 | Output drive strength level, bit 1 | - | C_REG_PWR_GPIO2_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 8 | 0x0 | Input Schmitt trigger strength | - | C_REG_PWR_GPIO2_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GRT\ | 9 | 0x0 | Input Schmitt trigger strength | - | C_REG_PWR_GPIO2_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 1\| 0x0 | Weak bus holder enable. | - | TC_REG_PWR_GPIO2_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_GR\ | 1\| 0x0 | Output level transition rate limit. | - | TC_REG_PWR_GPIO2_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - - -IOBLK_GRTC_REG_SD1_D3 -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_sd1_d3: -.. table:: IOBLK_GRTC_REG_SD1_D3 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | _GRTC_REG_SD1_D3_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | _GRTC_REG_SD1_D3_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength level, bit 0 | - | GRTC_REG_SD1_D3_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength level, bit 1 | - | GRTC_REG_SD1_D3_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength level, bit 2 | - | GRTC_REG_SD1_D3_DS2 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger strength | - | GRTC_REG_SD1_D3_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition rate limit. | - | _GRTC_REG_SD1_D3_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_SD1_D2 -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_sd1_d2: -.. table:: IOBLK_GRTC_REG_SD1_D2 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | _GRTC_REG_SD1_D2_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | _GRTC_REG_SD1_D2_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength level, bit 0 | - | GRTC_REG_SD1_D2_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength level, bit 1 | - | GRTC_REG_SD1_D2_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength level, bit 2 | - | GRTC_REG_SD1_D2_DS2 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger strength | - | GRTC_REG_SD1_D2_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition rate limit. | - | _GRTC_REG_SD1_D2_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_SD1_D1 -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_sd1_d1: -.. table:: IOBLK_GRTC_REG_SD1_D1 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | _GRTC_REG_SD1_D1_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | _GRTC_REG_SD1_D1_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength level, bit 0 | - | GRTC_REG_SD1_D1_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength level, bit 1 | - | GRTC_REG_SD1_D1_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength level, bit 2 | - | GRTC_REG_SD1_D1_DS2 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger strength | - | GRTC_REG_SD1_D1_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition rate limit. | - | _GRTC_REG_SD1_D1_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_SD1_D0 -^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_sd1_d0: -.. table:: IOBLK_GRTC_REG_SD1_D0 - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\ | 2 | 0x0 | Pull-up resistor enable. | - | _GRTC_REG_SD1_D0_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 3 | 0x1 | Pull-down resistor enable. | - | _GRTC_REG_SD1_D0_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 5 | 0x0 | Output drive strength level, bit 0 | - | GRTC_REG_SD1_D0_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 6 | 0x1 | Output drive strength level, bit 1 | - | GRTC_REG_SD1_D0_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 7 | 0x0 | Output drive strength level, bit 2 | - | GRTC_REG_SD1_D0_DS2 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 8 | 0x0 | Input Schmitt trigger strength | - | GRTC_REG_SD1_D0_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\ | 1\| 0x0 | Output level transition rate limit. | - | _GRTC_REG_SD1_D0_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_SD1_CMD -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_sd1_cmd: -.. table:: IOBLK_GRTC_REG_SD1_CMD - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | GRTC_REG_SD1_CMD_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 3 | 0x1 | Pull-down resistor enable. | - | GRTC_REG_SD1_CMD_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength level, bit 0 | - | RTC_REG_SD1_CMD_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength level, bit 1 | - | RTC_REG_SD1_CMD_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 7 | 0x0 | Output drive strength level, bit 2 | - | RTC_REG_SD1_CMD_DS2 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger strength | - | RTC_REG_SD1_CMD_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition rate limit. | - | GRTC_REG_SD1_CMD_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_SD1_CLK -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_sd1_clk: -.. table:: IOBLK_GRTC_REG_SD1_CLK - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | GRTC_REG_SD1_CLK_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 3 | 0x1 | Pull-down resistor enable. | - | GRTC_REG_SD1_CLK_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength level, bit 0 | - | RTC_REG_SD1_CLK_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength level, bit 1 | - | RTC_REG_SD1_CLK_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 7 | 0x0 | Output drive strength level, bit 2 | - | RTC_REG_SD1_CLK_DS2 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger strength | - | RTC_REG_SD1_CLK_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition rate limit. | - | GRTC_REG_SD1_CLK_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - -IOBLK_GRTC_REG_GPIO_ZQ -^^^^^^^^^^^^^^^^^^^^^^ - -.. _table_pincontrol_ioblk_grtc_reg_gpio_zq: -.. table:: IOBLK_GRTC_REG_GPIO_ZQ - :widths: 4 1 1 3 - - +---------------------+---+-------+-------------------------------------+ - | Field Name | B\| Defa\ | Field\ | - | | i\| ult | Description | - | | t | | | - +=====================+===+=======+=====================================+ - | IOBLK\_\ | 2 | 0x0 | Pull-up resistor enable. | - | GRTC_REG_GPIO_ZQ_PU | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 3 | 0x1 | Pull-down resistor enable. | - | GRTC_REG_GPIO_ZQ_PD | | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 5 | 0x0 | Output drive strength level, bit 0 | - | RTC_REG_GPIO_ZQ_DS0 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 6 | 0x1 | Output drive strength level, bit 1 | - | RTC_REG_GPIO_ZQ_DS1 | | | | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 8 | 0x0 | Input Schmitt trigger strength | - | RTC_REG_GPIO_ZQ_ST0 | | | control, bit 0 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK_G\ | 9 | 0x0 | Input Schmitt trigger strength | - | RTC_REG_GPIO_ZQ_ST1 | | | control, bit 1 | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 1\| 0x0 | Weak bus holder enable. | - | GRTC_REG_GPIO_ZQ_HE | 0 | | 0=Disabled; 1=Enabled | - +---------------------+---+-------+-------------------------------------+ - | IOBLK\_\ | 1\| 0x0 | Output level transition rate limit. | - | GRTC_REG_GPIO_ZQ_SL | 1 | | 0=Disabled (faster); 1=Enabled | - | | | | (slower) | - +---------------------+---+-------+-------------------------------------+ - diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_overview.table.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_overview.table.rst deleted file mode 100644 index 466f50c..0000000 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/pin_control_registers_overview.table.rst +++ /dev/null @@ -1,198 +0,0 @@ -.. _table_pin_control_registers_overview: -.. table:: Pine Control Registers Overview - :widths: 1 4 5 2 - - +------+------------------+-----------------------+------------------+ - | Pin\ | Pin Name | IO_cfg_register | Address | - | Num | | | | - +======+==================+=======================+==================+ - | 6 | SD0_CLK | IOBLK_G10_REG_SD0_CLK | 0x0300_1A00 | - +------+------------------+-----------------------+------------------+ - | 7 | SD0_CMD | IOBLK_G10_REG_SD0_CMD | 0x0300_1A04 | - +------+------------------+-----------------------+------------------+ - | 8 | SD0_D0 | IOBLK_G10_REG_SD0_D0 | 0x0300_1A08 | - +------+------------------+-----------------------+------------------+ - | 10 | SD0_D1 | IOBLK_G10_REG_SD0_D1 | 0x0300_1A0C | - +------+------------------+-----------------------+------------------+ - | 11 | SD0_D2 | IOBLK_G10_REG_SD0_D2 | 0x0300_1A10 | - +------+------------------+-----------------------+------------------+ - | 12 | SD0_D3 | IOBLK_G10_REG_SD0_D3 | 0x0300_1A14 | - +------+------------------+-----------------------+------------------+ - | 14 | SD0_CD | IOBLK_G7_REG_SD0_CD | 0x0300_1900 | - +------+------------------+-----------------------+------------------+ - | 15 | SD0_PWR_EN | IO\ | 0x0300_1904 | - | | | BLK_G7_REG_SD0_PWR_EN | | - +------+------------------+-----------------------+------------------+ - | 17 | SPK_EN | IOBLK_G7_REG_SPK_EN | 0x0300_1908 | - +------+------------------+-----------------------+------------------+ - | 18 | UART0_TX | IOBLK_G7_REG_UART0_TX | 0x0300_190C | - +------+------------------+-----------------------+------------------+ - | 19 | UART0_RX | IOBLK_G7_REG_UART0_RX | 0x0300_1910 | - +------+------------------+-----------------------+------------------+ - | 20 | EMMC_DAT2 | I\ | 0x0300_1918 | - | | | OBLK_G7_REG_EMMC_DAT2 | | - +------+------------------+-----------------------+------------------+ - | 21 | EMMC_CLK | IOBLK_G7_REG_EMMC_CLK | 0x0300_191C | - +------+------------------+-----------------------+------------------+ - | 22 | EMMC_DAT0 | I\ | 0x0300_1920 | - | | | OBLK_G7_REG_EMMC_DAT0 | | - +------+------------------+-----------------------+------------------+ - | 23 | EMMC_DAT3 | I\ | 0x0300_1924 | - | | | OBLK_G7_REG_EMMC_DAT3 | | - +------+------------------+-----------------------+------------------+ - | 24 | EMMC_CMD | IOBLK_G7_REG_EMMC_CMD | 0x0300_1928 | - +------+------------------+-----------------------+------------------+ - | 25 | EMMC_DAT1 | I\ | 0x0300_192C | - | | | OBLK_G7_REG_EMMC_DAT1 | | - +------+------------------+-----------------------+------------------+ - | 26 | JTAG_CPU_TMS | IOBL\ | 0x0300_1930 | - | | | K_G7_REG_JTAG_CPU_TMS | | - +------+------------------+-----------------------+------------------+ - | 27 | JTAG_CPU_TCK | IOBL\ | 0x0300_1934 | - | | | K_G7_REG_JTAG_CPU_TCK | | - +------+------------------+-----------------------+------------------+ - | 28 | IIC0_SCL | IOBLK_G7_REG_IIC0_SCL | 0x0300_193C | - +------+------------------+-----------------------+------------------+ - | 29 | IIC0_SDA | IOBLK_G7_REG_IIC0_SDA | 0x0300_1940 | - +------+------------------+-----------------------+------------------+ - | 30 | AUX0 | IOBLK_G7_REG_AUX0 | 0x0300_1944 | - +------+------------------+-----------------------+------------------+ - | 38 | PWR_VBAT_DET | IOBLK\_\ | 0x0502_7000 | - | | | GRTC_REG_PWR_VBAT_DET | | - +------+------------------+-----------------------+------------------+ - | 39 | PWR_RSTN | IO\ | 0x0502_7004 | - | | | BLK_GRTC_REG_PWR_RSTN | | - +------+------------------+-----------------------+------------------+ - | 40 | PWR_SEQ1 | IO\ | 0x0502_7008 | - | | | BLK_GRTC_REG_PWR_SEQ1 | | - +------+------------------+-----------------------+------------------+ - | 41 | PWR_SEQ2 | IO\ | 0x0502_700C | - | | | BLK_GRTC_REG_PWR_SEQ2 | | - +------+------------------+-----------------------+------------------+ - | 43 | PWR_WAKEUP0 | IOBLK\ | 0x0502_7018 | - | | | _GRTC_REG_PWR_WAKEUP0 | | - +------+------------------+-----------------------+------------------+ - | 44 | PWR_BUTTON1 | IOBLK\ | 0x0502_7020 | - | | | _GRTC_REG_PWR_BUTTON1 | | - +------+------------------+-----------------------+------------------+ - | 45 | XTAL_XIN | IO\ | 0x0502_7028 | - | | | BLK_GRTC_REG_XTAL_XIN | | - +------+------------------+-----------------------+------------------+ - | 47 | PWR_GPIO0 | IOB\ | 0x0502_702C | - | | | LK_GRTC_REG_PWR_GPIO0 | | - +------+------------------+-----------------------+------------------+ - | 48 | PWR_GPIO1 | IOB\ | 0x0502_7030 | - | | | LK_GRTC_REG_PWR_GPIO1 | | - +------+------------------+-----------------------+------------------+ - | 49 | PWR_GPIO2 | IOB\ | 0x0502_7034 | - | | | LK_GRTC_REG_PWR_GPIO2 | | - +------+------------------+-----------------------+------------------+ - | 51 | SD1_D3 | IOBLK_GRTC_REG_SD1_D3 | 0x0502_7058 | - +------+------------------+-----------------------+------------------+ - | 52 | SD1_D2 | IOBLK_GRTC_REG_SD1_D2 | 0x0502_705C | - +------+------------------+-----------------------+------------------+ - | 53 | SD1_D1 | IOBLK_GRTC_REG_SD1_D1 | 0x0502_7060 | - +------+------------------+-----------------------+------------------+ - | 54 | SD1_D0 | IOBLK_GRTC_REG_SD1_D0 | 0x0502_7064 | - +------+------------------+-----------------------+------------------+ - | 55 | SD1_CMD | I\ | 0x0502_7068 | - | | | OBLK_GRTC_REG_SD1_CMD | | - +------+------------------+-----------------------+------------------+ - | 56 | SD1_CLK | I\ | 0x0502_706C | - | | | OBLK_GRTC_REG_SD1_CLK | | - +------+------------------+-----------------------+------------------+ - | 58 | PWM0_BUCK | I\ | 0x0300_1804 | - | | | OBLK_G1_REG_PWM0_BUCK | | - +------+------------------+-----------------------+------------------+ - | 59 | ADC1 | IOBLK_G1_REG_ADC1 | 0x0300_1810 | - +------+------------------+-----------------------+------------------+ - | 60 | USB_VBUS_DET | IOBL\ | 0x0300_1820 | - | | | K_G1_REG_USB_VBUS_DET | | - +------+------------------+-----------------------+------------------+ - | 62 | PAD_ETH\_\ | #N/A | #N/A | - | | TXP___EPHY_RXN | | | - +------+------------------+-----------------------+------------------+ - | 63 | PAD_ETH\_\ | #N/A | #N/A | - | | TXM___EPHY_RXP | | | - +------+------------------+-----------------------+------------------+ - | 64 | PAD_ETH\_\ | #N/A | #N/A | - | | RXP___EPHY_TXN | | | - +------+------------------+-----------------------+------------------+ - | 65 | PAD_ETH\_\ | #N/A | #N/A | - | | RXM___EPHY_TXP | | | - +------+------------------+-----------------------+------------------+ - | 72 | PAD_MIPIRX4N | IOBLK\ | 0x0300_1C38 | - | | | _G12_REG_PAD_MIPIRX4N | | - +------+------------------+-----------------------+------------------+ - | 73 | PAD_MIPIRX4P | IOBLK\ | 0x0300_1C3C | - | | | _G12_REG_PAD_MIPIRX4P | | - +------+------------------+-----------------------+------------------+ - | 74 | PAD_MIPIRX3N | IOBLK\ | 0x0300_1C40 | - | | | _G12_REG_PAD_MIPIRX3N | | - +------+------------------+-----------------------+------------------+ - | 75 | PAD_MIPIRX3P | IOBLK\ | 0x0300_1C44 | - | | | _G12_REG_PAD_MIPIRX3P | | - +------+------------------+-----------------------+------------------+ - | 76 | PAD_MIPIRX2N | IOBLK\ | 0x0300_1C48 | - | | | _G12_REG_PAD_MIPIRX2N | | - +------+------------------+-----------------------+------------------+ - | 77 | PAD_MIPIRX2P | IOBLK\ | 0x0300_1C4C | - | | | _G12_REG_PAD_MIPIRX2P | | - +------+------------------+-----------------------+------------------+ - | 78 | PAD_MIPIRX1N | IOBLK\ | 0x0300_1C50 | - | | | _G12_REG_PAD_MIPIRX1N | | - +------+------------------+-----------------------+------------------+ - | 79 | PAD_MIPIRX1P | IOBLK\ | 0x0300_1C54 | - | | | _G12_REG_PAD_MIPIRX1P | | - +------+------------------+-----------------------+------------------+ - | 80 | PAD_MIPIRX0N | IOBLK\ | 0x0300_1C58 | - | | | _G12_REG_PAD_MIPIRX0N | | - +------+------------------+-----------------------+------------------+ - | 81 | PAD_MIPIRX0P | IOBLK\ | 0x0300_1C5C | - | | | _G12_REG_PAD_MIPIRX0P | | - +------+------------------+-----------------------+------------------+ - | 83 | PAD_MIPI_TXM2 | IOBLK\_\ | 0x0300_1C70 | - | | | G12_REG_PAD_MIPI_TXM2 | | - +------+------------------+-----------------------+------------------+ - | 84 | PAD_MIPI_TXP2 | IOBLK\_\ | 0x0300_1C74 | - | | | G12_REG_PAD_MIPI_TXP2 | | - +------+------------------+-----------------------+------------------+ - | 85 | PAD_MIPI_TXM1 | IOBLK\_\ | 0x0300_1C78 | - | | | G12_REG_PAD_MIPI_TXM1 | | - +------+------------------+-----------------------+------------------+ - | 86 | PAD_MIPI_TXP1 | IOBLK\_\ | 0x0300_1C7C | - | | | G12_REG_PAD_MIPI_TXP1 | | - +------+------------------+-----------------------+------------------+ - | 87 | PAD_MIPI_TXM0 | IOBLK\_\ | 0x0300_1C80 | - | | | G12_REG_PAD_MIPI_TXM0 | | - +------+------------------+-----------------------+------------------+ - | 88 | PAD_MIPI_TXP0 | IOBLK\_\ | 0x0300_1C84 | - | | | G12_REG_PAD_MIPI_TXP0 | | - +------+------------------+-----------------------+------------------+ - | 2 | PAD_AUD_AINL_MIC | #N/A | #N/A | - +------+------------------+-----------------------+------------------+ - | 4 | PAD_AUD_AOUTR | #N/A | #N/A | - +------+------------------+-----------------------+------------------+ - | 67 | GPIO\_\ | I\ | 0x0300_1C8C | - | | RTX___EPHY_RTX | OBLK_G12_REG_GPIO_RTX | | - +------+------------------+-----------------------+------------------+ - | 35 | GP\ | I\ | 0x0502_70E0 | - | | IO_ZQ\_\__PAD_ZQ | OBLK_GRTC_REG_GPIO_ZQ | | - +------+------------------+-----------------------+------------------+ - | #N/A | PKG_TYPE0 | I\ | 0x0300_181C | - | | | OBLK_G1_REG_PKG_TYPE0 | | - +------+------------------+-----------------------+------------------+ - | #N/A | PKG_TYPE1 | I\ | 0x0300_1824 | - | | | OBLK_G1_REG_PKG_TYPE1 | | - +------+------------------+-----------------------+------------------+ - | #N/A | PKG_TYPE2 | I\ | 0x0300_1828 | - | | | OBLK_G1_REG_PKG_TYPE2 | | - +------+------------------+-----------------------+------------------+ - | #N/A | MUX_SPI1_MISO | #N/A | #N/A | - +------+------------------+-----------------------+------------------+ - | #N/A | MUX_SPI1_MOSI | #N/A | #N/A | - +------+------------------+-----------------------+------------------+ - | #N/A | MUX_SPI1_CS | #N/A | #N/A | - +------+------------------+-----------------------+------------------+ - | #N/A | MUX_SPI1_SCK | #N/A | #N/A | - +------+------------------+-----------------------+------------------+ diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/pinctrl.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/pinctrl.rst deleted file mode 100644 index 89ab523..0000000 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/pinctrl.rst +++ /dev/null @@ -1,12 +0,0 @@ -管脚控制 PINCTRL ----------------- - -引脚控制寄存器概览 -~~~~~~~~~~~~~~~~~~ - -.. include:: ./pin_control_registers_overview.table.rst - -PINCTRL 寄存器描述 -~~~~~~~~~~~~~~~~~~ - -.. include:: ./pin_control_registers_description.table.rst diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/pinmux.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/pinmux.rst deleted file mode 100644 index b4de92f..0000000 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/pinmux.rst +++ /dev/null @@ -1,13 +0,0 @@ -管脚复用 PINMUX ---------------- - -接口功能与信号/引脚/FMUX寄存器的对应关系 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. include:: ./mapping_between_interface_and_signal_pin_fmux.table.rst - - -FMUX 寄存器描述 -~~~~~~~~~~~~~~~ - -.. include:: ./fmux_registers_configuration_information.table.rst diff --git a/SG200X/TRM/contents/en/peripherals/saradc.rst b/SG200X/TRM/contents/en/peripherals/saradc.rst index 2ce1733..3320a59 100644 --- a/SG200X/TRM/contents/en/peripherals/saradc.rst +++ b/SG200X/TRM/contents/en/peripherals/saradc.rst @@ -8,7 +8,7 @@ SARADC is an analog signal to digital conversion controller. This chip has up to .. only:: sg2002 - **Note:** The chip does not bring out all ADC channels on the pins for the controller under Active Domain. For details, please refer to :ref:`table_inf_signal_pin_fmux_adc_sg2002`. + **Note:** The chip does not bring out all ADC channels on the pins for the controller under Active Domain. For details, please refer to the description of the ADC interface in the “Function Signal Table” in :ref:`section_pinmux_pinctrl`. Features ~~~~~~~~ diff --git a/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst b/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst index cca2b5c..cdc41ec 100644 --- a/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst +++ b/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst @@ -3,8 +3,10 @@ PinMux and PinCtrl ================== -.. toctree:: - :maxdepth: 2 +.. only:: sg2002 - ./pinmux.rst - ./pinctrl.rst + For information on pin multiplexing and pin control, please refer directly to the online table: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/04_SG2002/04_SG2002_PINOUT.xlsx + +.. only:: sg2000 + + For information on pin multiplexing and pin control, please refer directly to the online table: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/03_SG2000/04_SG2000_PINOUT.xlsx diff --git a/SG200X/TRM/contents/en/pinmux-pinctrl/pinctrl.rst b/SG200X/TRM/contents/en/pinmux-pinctrl/pinctrl.rst deleted file mode 100644 index 1b989a2..0000000 --- a/SG200X/TRM/contents/en/pinmux-pinctrl/pinctrl.rst +++ /dev/null @@ -1,12 +0,0 @@ -Pin Control (PINCTRL) ---------------------- - -Pin Control Register Overview -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. include:: ../../contents-share/pinmux-pinctrl/pin_control_registers_overview.table.rst - -Pin Control Register Description -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. include:: ../../contents-share/pinmux-pinctrl/pin_control_registers_description.table.rst diff --git a/SG200X/TRM/contents/en/pinmux-pinctrl/pinmux.rst b/SG200X/TRM/contents/en/pinmux-pinctrl/pinmux.rst deleted file mode 100644 index dc318a5..0000000 --- a/SG200X/TRM/contents/en/pinmux-pinctrl/pinmux.rst +++ /dev/null @@ -1,13 +0,0 @@ -Pin Multiplexing (PINMUX) -------------------------- - -Mapping between interface functions and signals/pins/FMUX registers -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. include:: ../../contents-share/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst - - -FMUX Registers Description -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -.. include:: ../../contents-share/pinmux-pinctrl/fmux_registers_configuration_information.table.rst