diff --git a/SG200X/TRM/contents/cn/peripherals/saradc.rst b/SG200X/TRM/contents/cn/peripherals/saradc.rst index db4a540..d0336b4 100644 --- a/SG200X/TRM/contents/cn/peripherals/saradc.rst +++ b/SG200X/TRM/contents/cn/peripherals/saradc.rst @@ -30,6 +30,8 @@ SARADC 为模拟信号数字转换控制器。本芯片有最多 2 个 SARADC CPU 配置扫描信道，每个 SARADC 控制器可同时配置 3 个信道，启动 SARADC 进行通道扫描。通道扫描完成所有使能通道后, 通过中断通知系统扫描完成, CPU 可以获取转换结果。 +系统上电后，为确保 SARADC 测量精度，建议对芯片的 SARADC 模块进行校准。校准通过离线方式执行，具体方法是先设置 saradc_test.reg_saradc_vrefsel 为 external 方式，然后手动反复调整 saradc_trim.reg_saradc_trim, 直至实际读出采样值经换算后与外部参考电压值比较接近至满足精度要求。校准完成后将 saradc_trim.reg_saradc_trim 的值记录下来，每次上电时通过软件设置 saradc_test.reg_saradc_vrefsel 为 external 方式后再将该记录的值设置到 saradc_trim.reg_saradc_trim 即可。 + .. _section_saradc_register_overview: SARADC 寄存器概览 @@ -53,7 +55,7 @@ No-die Domain 下 1 组（RTCSYS_SARADC），Base address：0x0502C000 +======================+=========+====================================+ | saradc_ctrl | 0x004 | control register | +----------------------+---------+------------------------------------+ - | saradc_status | 0x008 | staus register | + | saradc_status | 0x008 | status register | +----------------------+---------+------------------------------------+ | saradc_cyc_set | 0x00c | saradc waveform setting register | +----------------------+---------+------------------------------------+ @@ -71,6 +73,10 @@ No-die Domain 下 1 组（RTCSYS_SARADC），Base address：0x0502C000 +----------------------+---------+------------------------------------+ | saradc_intr_raw | 0x02c | interrupt raw status register | +----------------------+---------+------------------------------------+ + | saradc_test | 0x030 | test register | + +----------------------+---------+------------------------------------+ + | saradc_trim | 0x034 | trim register | + +----------------------+---------+------------------------------------+ SARADC 寄存器描述 ~~~~~~~~~~~~~~~~~ diff --git a/SG200X/TRM/contents/cn/peripherals/saradc_registers_description.table.rst b/SG200X/TRM/contents/cn/peripherals/saradc_registers_description.table.rst index 5e4d49b..81d93df 100644 --- a/SG200X/TRM/contents/cn/peripherals/saradc_registers_description.table.rst +++ b/SG200X/TRM/contents/cn/peripherals/saradc_registers_description.table.rst @@ -227,3 +227,45 @@ saradc_intr_raw +------+----------------------+-------+------------------------+------+ | 31:1 | Reserved | | | | +------+----------------------+-------+------------------------+------+ + +saradc_test +^^^^^^^^^^^ + +.. _table_saradc_test: +.. table:: saradc_test, Offset Address: 0x030 + :widths: 1 2 1 4 1 + + +------+----------------------+-------+------------------------+------+ + | Bits | Name | Access| Description | Reset| + +======+======================+=======+========================+======+ + | 0:1 | Reserved | | | | + +------+----------------------+-------+------------------------+------+ + | 2 | reg_saradc_vrefsel | RW | 1'b0:internal | 0 | + | | | | | | + | | | | 1'b1:external(from | | + | | | | VDD18A) | | + +------+----------------------+-------+------------------------+------+ + | 31:3 | Reserved | | | | + +------+----------------------+-------+------------------------+------+ + +saradc_trim +^^^^^^^^^^^ + +.. _table_saradc_trim: +.. table:: saradc_trim, Offset Address: 0x034 + :widths: 1 2 1 4 1 + + +------+----------------------+-------+------------------------+------+ + | Bits | Name | Access| Description | Reset| + +======+======================+=======+========================+======+ + | 3:0 | reg_saradc_trim | RW | bit[0:2]: The larger | 0x0 | + | | | | the value, the smaller | | + | | | | the vref, and the | | + | | | | larger the reading. | | + | | | | | | + | | | | bit[3]: reverse, | | + | | | | from b1000 to b0111 | | + | | | | vref decreases | | + +------+----------------------+-------+------------------------+------+ + | 31:4 | Reserved | | | | + +------+----------------------+-------+------------------------+------+ diff --git a/SG200X/TRM/contents/cn/peripherals/uart.rst b/SG200X/TRM/contents/cn/peripherals/uart.rst index adf7905..16f1024 100644 --- a/SG200X/TRM/contents/cn/peripherals/uart.rst +++ b/SG200X/TRM/contents/cn/peripherals/uart.rst @@ -6,41 +6,41 @@ UART UART (Universal Asynchronous Receiver Transmitter) 是一个非同步串行的通信接口, 主要功能是将来自外围设备的资料进行串并转换之后传入内部总线, 以及将资料进行并串转换之后输出到外部设备。UART 的主要功能是和外部芯片的 UART 进行对接，从而实现两芯片间的通信。 -本芯片提供 5 个 UART 控制器，相关概述如下表， +本芯片提供 5 个 UART 控制器，相关概述如下表。注意：使用前以具体的引脚输出定义为准。因为芯片不同的封装（QFN/BGA），某些功能可能未导出。引脚定义参考 :ref:`section_pinmux_pinctrl`。 .. 这个表比较小，就不单独文件 include 了 .. _table_uart_io_infodescribe: .. table:: UART IO pin information - :widths: 1 1 3 - - +------------+-------------+----------------------------------------------+ - | Controller | Mode | IO Pin | - +============+=============+==============================================+ - | UART0 | 2-line UART | UART0_TX/UART0_RX | - +------------+-------------+----------------------------------------------+ - | UART1 |2/4-line UART| UART1_TX/UART1_RX/UART1_CTS/UART1_RTS | - | | +----------------------------------------------+ - | | | XGPIOA[20]/ XGPIOA[21]/ XGPIOA[22]/ | - | | | XGPIOA[26] | - +------------+-------------+----------------------------------------------+ - | UART2 |2/4-line UART| UART2_TX/UART2_RX/UART2_CTS/UART2_RTS | - | | +----------------------------------------------+ - | | | XGPIOA[20]/ XGPIOA[21]/ XGPIOA[22]/ | - | | | XGPIOA[26] | - | | +----------------------------------------------+ - | | | IIC2_SDA/IIC2_SCL | - +------------+-------------+----------------------------------------------+ - | UART3 |2/4-line UART| SPI0_CS_X/SPI0_SCK/SPI0_SDI/SPI0_SDO | - | | +----------------------------------------------+ - | | | VI_DATA22/VI_DATA21/VI_DATA24/VI_DATA23 | - | | +----------------------------------------------+ - | | | PWM3/PWM2 | - +------------+-------------+----------------------------------------------+ - | UART4 | 2-line UART | XGPIOA[22]/ XGPIOA[26] | - | | +----------------------------------------------+ - | | | UART1_RTS/UART1_CTS | - +------------+-------------+----------------------------------------------+ + :widths: 1 1 + + +------------+-------------+ + | Controller | Mode | + +============+=============+ + | UART0 | 2-line UART | + +------------+-------------+ + | UART1 |2/4-line UART| + | | + + | | | + | | | + +------------+-------------+ + | UART2 |2/4-line UART| + | | + + | | | + | | | + | | + + | | | + +------------+-------------+ + | UART3 |2/4-line UART| + | | + + | | | + | | + + | | | + +------------+-------------+ + | UART4 | 2-line UART | + | | + + | | | + +------------+-------------+ 特点 ~~~~ diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst index d07fdd5..106a219 100644 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst +++ b/SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst @@ -1,3 +1,5 @@ +.. _section_pinmux_pinctrl: + 管脚复用与控制 ============== diff --git a/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst b/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst index ef526dd..fe01ef6 100644 --- a/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst +++ b/SG200X/TRM/contents/cn/pinmux-pinctrl/mapping_between_interface_and_signal_pin_fmux.table.rst @@ -1541,175 +1541,444 @@ To be continued ...... UART ^^^^ -.. _table_inf_signal_pin_fmux_uart: -.. table:: UART - :widths: 2 1 1 1 3 +.. only:: sg2002 - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | U\ | I | U | 0 | FMUX_GPI | - | ART0_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | U | 0 | FMUX_GPI | - | ART0_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | JTAG | 4 | FMUX_GPIO_RE | - | RT1_CTS | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | JTAG | 4 | FMUX_GPIO_RE | - | RT1_RTS | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD0_D2 | 4 | FMUX_G | - | ART1_RX | | | | PIO_REG_IOCTRL_SD0_D2 | - | | | | | 0x0300_102C | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | U | 4 | FMUX_GPI | - | ART1_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | - | | | | | 0x0300_1044 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PWR | 4 | FMUX_GPIO_R | - | ART1_RX | | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | - | | | | | 0x0300_1098 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | JTAG | 6 | FMUX_GPIO_RE | - | ART1_RX | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | - | | | | | 0x0300_1068 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | I | 1 | FMUX_GPI | - | ART1_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD0_D1 | 4 | FMUX_G | - | ART1_TX | | | | PIO_REG_IOCTRL_SD0_D1 | - | | | | | 0x0300_1028 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | U | 4 | FMUX_GPI | - | ART1_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | - | | | | | 0x0300_1040 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PWR | 4 | FMUX_GPIO_R | - | ART1_TX | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | JTAG | 6 | FMUX_GPIO_RE | - | ART1_TX | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | - | | | | | 0x0300_1064 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | I | 1 | FMUX_GPI | - | ART1_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | I | 2 | FMUX_GPI | - | ART2_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | - | | | | | 0x0300_1074 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD1_D1 | 2 | FMUX_G | - | ART2_RX | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PW | 1 | FMUX_GPIO | - | ART2_RX | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | - | | | | | 0x0300_10A8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | I | 2 | FMUX_GPI | - | ART2_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | - | | | | | 0x0300_1070 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD1_D2 | 2 | FMUX_G | - | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PW | 1 | FMUX_GPIO | - | ART2_TX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | MUX | 1 | FMUX_GPIO_R | - | RT3_CTS | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | - | | | | | 0x0300_111C | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | PAD | 1 | FMUX_GPIO_R | - | RT3_CTS | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | - | | | M\_\__E | | 0x0300_1130 | - | | | PHY_TXP | | | - +---------+---------+---------+--------+-----------------------+ - | UA\ | I | SD1_D3 | 5 | FMUX_G | - | RT3_CTS | | | | PIO_REG_IOCTRL_SD1_D3 | - | | | | | 0x0300_10D0 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | MUX_SP | 1 | FMUX_GPIO_REG_IO | - | RT3_RTS | | I1_MISO | | CTRL_MUX_SPI1_MISO | - | | | | | 0x0300_1114 | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | PAD | 1 | FMUX_GPIO_R | - | RT3_RTS | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | - | | | M\_\__E | | 0x0300_1128 | - | | | PHY_RXP | | | - +---------+---------+---------+--------+-----------------------+ - | UA\ | O | SD1_D0 | 5 | FMUX_G | - | RT3_RTS | | | | PIO_REG_IOCTRL_SD1_D0 | - | | | | | 0x0300_10DC | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD0_D3 | 4 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_SD0_D3 | - | | | | | 0x0300_1030 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | MUX_SP | 1 | FMUX_GPIO_REG_IO | - | ART3_RX | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | - | | | | | 0x0300_1118 | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | PAD | 1 | FMUX_GPIO_R | - | ART3_RX | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | - | | | P\_\__E | | 0x0300_1124 | - | | | PHY_RXN | | | - +---------+---------+---------+--------+-----------------------+ - | U\ | I | SD1_D1 | 5 | FMUX_G | - | ART3_RX | | | | PIO_REG_IOCTRL_SD1_D1 | - | | | | | 0x0300_10D8 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD0_D0 | 4 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_SD0_D0 | - | | | | | 0x0300_1024 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | MUX_S | 1 | FMUX_GPIO_RE | - | ART3_TX | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | - | | | | | 0x0300_1120 | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | PAD | 1 | FMUX_GPIO_R | - | ART3_TX | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | - | | | P\_\__E | | 0x0300_112C | - | | | PHY_TXN | | | - +---------+---------+---------+--------+-----------------------+ - | U\ | O | SD1_D2 | 5 | FMUX_G | - | ART3_TX | | | | PIO_REG_IOCTRL_SD1_D2 | - | | | | | 0x0300_10D4 | - +---------+---------+---------+--------+-----------------------+ + .. _table_inf_signal_pin_fmux_uart_sg2002: + .. table:: UART + :widths: 2 1 1 1 3 + + +---------+---------+---------+--------+-----------------------+ + | Signal |Direction| PinName |Function| Function select | + | Name | | |Number | register | + +=========+=========+=========+========+=======================+ + | U\ | I | U | 0 | FMUX_GPI | + | ART0_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | + | | | | | 0x0300_1044 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | U | 0 | FMUX_GPI | + | ART0_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | + | | | | | 0x0300_1040 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | JTAG | 4 | FMUX_GPIO_RE | + | RT1_CTS | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | + | | | | | 0x0300_1068 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | JTAG | 4 | FMUX_GPIO_RE | + | RT1_RTS | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | + | | | | | 0x0300_1064 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD0_D2 | 4 | FMUX_G | + | ART1_RX | | | | PIO_REG_IOCTRL_SD0_D2 | + | | | | | 0x0300_102C | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | U | 4 | FMUX_GPI | + | ART1_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | + | | | | | 0x0300_1044 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PWR | 4 | FMUX_GPIO_R | + | ART1_RX | | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | + | | | | | 0x0300_1098 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | JTAG | 6 | FMUX_GPIO_RE | + | ART1_RX | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | + | | | | | 0x0300_1068 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | I | 1 | FMUX_GPI | + | ART1_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | + | | | | | 0x0300_1074 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD0_D1 | 4 | FMUX_G | + | ART1_TX | | | | PIO_REG_IOCTRL_SD0_D1 | + | | | | | 0x0300_1028 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | U | 4 | FMUX_GPI | + | ART1_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | + | | | | | 0x0300_1040 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PWR | 4 | FMUX_GPIO_R | + | ART1_TX | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | + | | | | | 0x0300_1090 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | JTAG | 6 | FMUX_GPIO_RE | + | ART1_TX | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | + | | | | | 0x0300_1064 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | I | 1 | FMUX_GPI | + | ART1_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | + | | | | | 0x0300_1070 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | I | 2 | FMUX_GPI | + | ART2_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | + | | | | | 0x0300_1074 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD1_D1 | 2 | FMUX_G | + | ART2_RX | | | | PIO_REG_IOCTRL_SD1_D1 | + | | | | | 0x0300_10D8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PW | 1 | FMUX_GPIO | + | ART2_RX | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | + | | | | | 0x0300_10A8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | I | 2 | FMUX_GPI | + | ART2_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | + | | | | | 0x0300_1070 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD1_D2 | 2 | FMUX_G | + | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | + | | | | | 0x0300_10D4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PW | 1 | FMUX_GPIO | + | ART2_TX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | + | | | | | 0x0300_10A4 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | MUX | 1 | FMUX_GPIO_R | + | RT3_CTS | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | + | | | | | 0x0300_111C | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | PAD | 1 | FMUX_GPIO_R | + | RT3_CTS | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | + | | | M\_\__E | | 0x0300_1130 | + | | | PHY_TXP | | | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | SD1_D3 | 5 | FMUX_G | + | RT3_CTS | | | | PIO_REG_IOCTRL_SD1_D3 | + | | | | | 0x0300_10D0 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | MUX_SP | 1 | FMUX_GPIO_REG_IO | + | RT3_RTS | | I1_MISO | | CTRL_MUX_SPI1_MISO | + | | | | | 0x0300_1114 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | PAD | 1 | FMUX_GPIO_R | + | RT3_RTS | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | + | | | M\_\__E | | 0x0300_1128 | + | | | PHY_RXP | | | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | SD1_D0 | 5 | FMUX_G | + | RT3_RTS | | | | PIO_REG_IOCTRL_SD1_D0 | + | | | | | 0x0300_10DC | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD0_D3 | 4 | FMUX_G | + | ART3_RX | | | | PIO_REG_IOCTRL_SD0_D3 | + | | | | | 0x0300_1030 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | MUX_SP | 1 | FMUX_GPIO_REG_IO | + | ART3_RX | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | + | | | | | 0x0300_1118 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PAD | 1 | FMUX_GPIO_R | + | ART3_RX | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | + | | | P\_\__E | | 0x0300_1124 | + | | | PHY_RXN | | | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD1_D1 | 5 | FMUX_G | + | ART3_RX | | | | PIO_REG_IOCTRL_SD1_D1 | + | | | | | 0x0300_10D8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD0_D0 | 4 | FMUX_G | + | ART3_TX | | | | PIO_REG_IOCTRL_SD0_D0 | + | | | | | 0x0300_1024 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | MUX_S | 1 | FMUX_GPIO_RE | + | ART3_TX | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | + | | | | | 0x0300_1120 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PAD | 1 | FMUX_GPIO_R | + | ART3_TX | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | + | | | P\_\__E | | 0x0300_112C | + | | | PHY_TXN | | | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD1_D2 | 5 | FMUX_G | + | ART3_TX | | | | PIO_REG_IOCTRL_SD1_D2 | + | | | | | 0x0300_10D4 | + +---------+---------+---------+--------+-----------------------+ + +.. only:: sg2000 + + .. _table_inf_signal_pin_fmux_uart_sg2000: + .. table:: UART + :widths: 2 1 1 1 3 + + +---------+---------+---------+--------+-----------------------+ + | Signal |Direction| PinName |Function| Function select | + | Name | | |Number | register | + +=========+=========+=========+========+=======================+ + | U\ | I | U | 0 | FMUX_GPI | + | ART0_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | + | | | | | 0x0300_1044 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | U | 0 | FMUX_GPI | + | ART0_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | + | | | | | 0x0300_1040 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | JTAG | 4 | FMUX_GPIO_RE | + | RT1_CTS | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | + | | | | | 0x0300_1068 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | JTAG | 4 | FMUX_GPIO_RE | + | RT1_RTS | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | + | | | | | 0x0300_1064 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD0_D2 | 4 | FMUX_G | + | ART1_RX | | | | PIO_REG_IOCTRL_SD0_D2 | + | | | | | 0x0300_102C | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | U | 4 | FMUX_GPI | + | ART1_RX | | ART0_RX | | O_REG_IOCTRL_UART0_RX | + | | | | | 0x0300_1044 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PWR | 4 | FMUX_GPIO_R | + | ART1_RX | | _BUTTON1| | EG_IOCTRL_PWR_BUTTON1 | + | | | | | 0x0300_1098 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PWR | 4 | FMUX_GPIO_R | + | ART1_RX | | _ON | | EG_IOCTRL_PWR_ON | + | | | | | 0x0300_109C | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | JTAG | 6 | FMUX_GPIO_RE | + | ART1_RX | | _CPU_TCK| | G_IOCTRL_JTAG_CPU_TCK | + | | | | | 0x0300_1068 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | I | 1 | FMUX_GPI | + | ART1_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | + | | | | | 0x0300_1074 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD0_D1 | 4 | FMUX_G | + | ART1_TX | | | | PIO_REG_IOCTRL_SD0_D1 | + | | | | | 0x0300_1028 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | U | 4 | FMUX_GPI | + | ART1_TX | | ART0_TX | | O_REG_IOCTRL_UART0_TX | + | | | | | 0x0300_1040 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PWR | 4 | FMUX_GPIO_R | + | ART1_TX | | _WAKEUP0| | EG_IOCTRL_PWR_WAKEUP0 | + | | | | | 0x0300_1090 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PWR | 4 | FMUX_GPIO_R | + | ART1_TX | | _WAKEUP1| | EG_IOCTRL_PWR_WAKEUP1 | + | | | | | 0x0300_1094 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | JTAG | 6 | FMUX_GPIO_RE | + | ART1_TX | | _CPU_TMS| | G_IOCTRL_JTAG_CPU_TMS | + | | | | | 0x0300_1064 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | I | 1 | FMUX_GPI | + | ART1_TX | | IC0_SCL | | O_REG_IOCTRL_IIC0_SCL | + | | | | | 0x0300_1070 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | VIVO_D4 | 6 | FMUX_GPI | + | ART2_CTS| | | | O_REG_IOCTRL_VIVO_D4 | + | | | | | 0x0300_114C | + +---------+---------+---------+--------+-----------------------+ + | U\ | I |UART2_CTS| 0 | FMUX_GPI | + | ART2_CTS| | | | O_REG_IOCTRL_UART2_CTS| + | | | | | 0x0300_10CC | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | VIVO_D3 | 6 | FMUX_GPI | + | ART2_RTS| | | | O_REG_IOCTRL_VIVO_D3 | + | | | | | 0x0300_1150 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O |UART2_RTS| 0 | FMUX_GPI | + | ART2_RTS| | | | O_REG_IOCTRL_UART2_RTS| + | | | | | 0x0300_10C4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | UART2_RX| 0 | FMUX_GPI | + | ART2_RX | | | | O_REG_IOCTRL_UART2_RX | + | | | | | 0x0300_10C8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | IIC2_SCL| 4 | FMUX_GP | + | ART2_RX | | | | IO_REG_IOCTRL_IIC2_SCL| + | | | | | 0x0300_10B8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | I | 2 | FMUX_GPI | + | ART2_RX | | IC0_SDA | | O_REG_IOCTRL_IIC0_SDA | + | | | | | 0x0300_1074 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD1_D1 | 2 | FMUX_G | + | ART2_RX | | | | PIO_REG_IOCTRL_SD1_D1 | + | | | | | 0x0300_10D8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | VIVO_D5 | 6 | FMUX_G | + | ART2_RX | | | | PIO_REG_IOCTRL_VIVO_D5| + | | | | | 0x0300_1148 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PW | 1 | FMUX_GPIO | + | ART2_RX | | R_GPIO1 | | _REG_IOCTRL_PWR_GPIO1 | + | | | | | 0x0300_10A8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | VIVO_D9 | 7 | FMUX_G | + | ART2_RX | | | | PIO_REG_IOCTRL_VIVO_D9| + | | | | | 0x0300_1138 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | VIVO_CLK| 7 | FMUX_GP | + | ART2_RX | | | | IO_REG_IOCTRL_VIVO_CLK| + | | | | | 0x0300_1160 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | UART2_TX| 0 | FMUX_GPI | + | ART2_TX | | | | O_REG_IOCTRL_UART2_TX | + | | | | | 0x0300_10C0 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | IIC2_SDA| 4 | FMUX_GPI | + | ART2_TX | | | | O_REG_IOCTRL_IIC2_SDA | + | | | | | 0x0300_10BC | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | IIC0_SCL| 2 | FMUX_GPI | + | ART2_TX | | | | O_REG_IOCTRL_IIC0_SCL | + | | | | | 0x0300_1070 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD1_D2 | 2 | FMUX_G | + | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | + | | | | | 0x0300_10D4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | VIVO_D6 | 6 | FMUX_G | + | ART2_TX | | | | PIO_REG_IOCTRL_SD1_D2 | + | | | | | 0x0300_1144 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PW | 1 | FMUX_GPIO | + | ART2_TX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | + | | | | | 0x0300_10A4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | VIVO_D10| 7 | FMUX_GPIO | + | ART2_TX | | | | _REG_IOCTRL_VIVO_D10 | + | | | | | 0x0300_1134 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | VIVO_D2 | 7 | FMUX_GPIO | + | ART2_TX | | | | _REG_IOCTRL_VIVO_D2 | + | | | | | 0x0300_1154 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | MUX | 1 | FMUX_GPIO_R | + | RT3_CTS | | _SPI1_CS| | EG_IOCTRL_MUX_SPI1_CS | + | | | | | 0x0300_111C | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | PAD | 1 | FMUX_GPIO_R | + | RT3_CTS | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXM | + | | | M\_\__E | | 0x0300_1130 | + | | | PHY_TXP | | | + +---------+---------+---------+--------+-----------------------+ + | UA\ | I | SD1_D3 | 5 | FMUX_G | + | RT3_CTS | | | | PIO_REG_IOCTRL_SD1_D3 | + | | | | | 0x0300_10D0 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | MUX_SP | 1 | FMUX_GPIO_REG_IO | + | RT3_RTS | | I1_MISO | | CTRL_MUX_SPI1_MISO | + | | | | | 0x0300_1114 | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | PAD | 1 | FMUX_GPIO_R | + | RT3_RTS | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXM | + | | | M\_\__E | | 0x0300_1128 | + | | | PHY_RXP | | | + +---------+---------+---------+--------+-----------------------+ + | UA\ | O | SD1_D0 | 5 | FMUX_G | + | RT3_RTS | | | | PIO_REG_IOCTRL_SD1_D0 | + | | | | | 0x0300_10DC | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD0_D3 | 4 | FMUX_G | + | ART3_RX | | | | PIO_REG_IOCTRL_SD0_D3 | + | | | | | 0x0300_1030 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | MUX_SP | 1 | FMUX_GPIO_REG_IO | + | ART3_RX | | I1_MOSI | | CTRL_MUX_SPI1_MOSI | + | | | | | 0x0300_1118 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | PAD | 1 | FMUX_GPIO_R | + | ART3_RX | | _ETH_TX | | EG_IOCTRL_PAD_ETH_TXP | + | | | P\_\__E | | 0x0300_1124 | + | | | PHY_RXN | | | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | SD1_D1 | 5 | FMUX_G | + | ART3_RX | | | | PIO_REG_IOCTRL_SD1_D1 | + | | | | | 0x0300_10D8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I | ADC2 | 7 | FMUX_G | + | ART3_RX | | | | PIO_REG_IOCTRL_ADC2 | + | | | | | 0x0300_10F4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD0_D0 | 4 | FMUX_G | + | ART3_TX | | | | PIO_REG_IOCTRL_SD0_D0 | + | | | | | 0x0300_1024 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | MUX_S | 1 | FMUX_GPIO_RE | + | ART3_TX | | PI1_SCK | | G_IOCTRL_MUX_SPI1_SCK | + | | | | | 0x0300_1120 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | PAD | 1 | FMUX_GPIO_R | + | ART3_TX | | _ETH_RX | | EG_IOCTRL_PAD_ETH_RXP | + | | | P\_\__E | | 0x0300_112C | + | | | PHY_TXN | | | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | SD1_D2 | 5 | FMUX_G | + | ART3_TX | | | | PIO_REG_IOCTRL_SD1_D2 | + | | | | | 0x0300_10D4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | O | ADC3 | 7 | FMUX_G | + | ART3_TX | | | | PIO_REG_IOCTRL_ADC3 | + | | | | | 0x0300_10F0 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I |UART2_CTS| 5 | FMUX_GPI | + | ART4_CTS| | | | O_REG_IOCTRL_UART2_CTS| + | | | | | 0x0300_10CC | + +---------+---------+---------+--------+-----------------------+ + | U\ | O |UART2_RTS| 5 | FMUX_GPI | + | ART4_RTS| | | | O_REG_IOCTRL_UART2_RTS| + | | | | | 0x0300_10C4 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I |UART2_RX | 5 | FMUX_GPI | + | ART4_RX | | | | O_REG_IOCTRL_UART2_RX | + | | | | | 0x0300_10C8 | + +---------+---------+---------+--------+-----------------------+ + | U\ | I |UART2_TX | 5 | FMUX_GPI | + | ART4_TX | | | | O_REG_IOCTRL_UART2_TX | + | | | | | 0x0300_10C0 | + +---------+---------+---------+--------+-----------------------+ No-die domain UART ^^^^^^^^^^^^^^^^^^ -.. _table_inf_signal_pin_fmux_nodie_uart: -.. table:: No-die domain UART - :widths: 2 1 1 1 3 +.. only:: sg2002 - +---------+---------+---------+--------+-----------------------+ - | Signal |Direction| PinName |Function| Function select | - | Name | | |Number | register | - +=========+=========+=========+========+=======================+ - | PWR_U\ | I | PW | 2 | FMUX_GPIO | - | ART0_RX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | - | | | | | 0x0300_10A4 | - +---------+---------+---------+--------+-----------------------+ - | PWR_U\ | O |PWR | 2 | FMUX_GPIO_R | - | ART0_TX | |_WAKEUP0 | | EG_IOCTRL_PWR_WAKEUP0 | - | | | | | 0x0300_1090 | - +---------+---------+---------+--------+-----------------------+ + .. _table_inf_signal_pin_fmux_nodie_uart_sg2002: + .. table:: No-die domain UART + :widths: 2 1 1 1 3 + + +---------+---------+---------+--------+-----------------------+ + | Signal |Direction| PinName |Function| Function select | + | Name | | |Number | register | + +=========+=========+=========+========+=======================+ + | PWR_U\ | I | PW | 2 | FMUX_GPIO | + | ART0_RX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | + | | | | | 0x0300_10A4 | + +---------+---------+---------+--------+-----------------------+ + | PWR_U\ | O |PWR | 2 | FMUX_GPIO_R | + | ART0_TX | |_WAKEUP0 | | EG_IOCTRL_PWR_WAKEUP0 | + | | | | | 0x0300_1090 | + +---------+---------+---------+--------+-----------------------+ + +.. only:: sg2000 + .. _table_inf_signal_pin_fmux_nodie_uart_sg2000: + .. table:: No-die domain UART + :widths: 2 1 1 1 3 + + +---------+---------+---------+--------+-----------------------+ + | Signal |Direction| PinName |Function| Function select | + | Name | | |Number | register | + +=========+=========+=========+========+=======================+ + | PWR_U\ | I | PW | 2 | FMUX_GPIO | + | ART0_RX | | R_GPIO0 | | _REG_IOCTRL_PWR_GPIO0 | + | | | | | 0x0300_10A4 | + +---------+---------+---------+--------+-----------------------+ + | PWR_U\ | O |PWR | 2 | FMUX_GPIO_R | + | ART0_TX | |_WAKEUP0 | | EG_IOCTRL_PWR_WAKEUP0 | + | | | | | 0x0300_1090 | + +---------+---------+---------+--------+-----------------------+ + | PWR_U\ | I | UART2_RX| 2 | FMUX_GPIO | + | ART1_RX | | | | _REG_IOCTRL_UART2_RX | + | | | | | 0x0300_10C8 | + +---------+---------+---------+--------+-----------------------+ + | PWR_U\ | O | UART2_TX| 2 | FMUX_GPIO_R | + | ART1_TX | | | | EG_IOCTRL_UART2_TX | + | | | | | 0x0300_10C0 | + +---------+---------+---------+--------+-----------------------+ Wiegand ^^^^^^^ diff --git a/SG200X/TRM/contents/cn/reset/reset_control.rst b/SG200X/TRM/contents/cn/reset/reset_control.rst index 633d63e..789c4a0 100644 --- a/SG200X/TRM/contents/cn/reset/reset_control.rst +++ b/SG200X/TRM/contents/cn/reset/reset_control.rst @@ -1,51 +1,32 @@ 复位控制 -------- +芯片内部存在三个层级的复位管理模块对整个芯片、子系统，各个功能模块的复位进行管理。 + .. _diagram_reset_block: .. figure:: ../../../../media/image6.png :align: center 复位管理模块框图 -上电复位 -~~~~~~~~ - -上电复位 (POR) 由实时时钟模块配合全局电源管理与晶振时序生成。详情参照章节 :ref:`section_rtc`。 - -系统硬复位 -~~~~~~~~~~ - -系统硬复位 (System Hard Reset) 由 Reset Ctrl Level2 生成，对芯片全局包含子系统及各功能模块进行硬复位，来源由以下途径： +Reset Ctrl Level 1 电路负责系统上电复位功能。上电复位 (POR) 由实时时钟模块配合全局电源管理与晶振时序生成。详情参照章节 :ref:`section_rtc`。来源由以下途径： - 上电复位 -- 看门狗复位 - - 过热保护复位 -- 外部复位管脚 (RSTN) +- 看门狗复位。RCT_CTRL0.hw_wdg_rst_en 为 1, (见 :ref:`table_rtc_ctrl0`) 且 sys_ctrl_reg.reg_sw_root_reset_en 的 bit[0] 为 0 (见 :ref:`table_sys_ctrl_reg`) 情况下 Watchdog 定时器超时触发系统复位。 - - 内建去抖动电路，RSTN 高低电平有效信号须达 6.56ms。 +Reset Ctrl Level 2 电路负责产生系统硬复位 (System Hard Reset)，对芯片全局包含子系统及各功能模块进行硬复位，来源由以下途径： -软复位 -~~~~~~ +- 看门狗复位, sys_ctrl_reg.reg_sw_root_reset_en 的 bit[0] 为 1 (见 :ref:`table_sys_ctrl_reg`) 情况下 Watchdog 定时器超时触发系统复位。 -软复位控制通过配置相应的复位配置寄存器 (Reset CRG)，由 Reset Ctrl Level3实现，包含： +- 外部复位管脚 (RSTN)，内建去抖动电路 (Debounce), RSTN 高低电平有效信号须达 6.56ms。 -- 系统软复位 : 复位全芯片，除少部分电路及 RTC 内部电路。 +Reset Ctrl Level 3 电路负责提供实现软复位控制相应的复位配置寄存器 (Reset CRG)，具体参考 :ref:`section_reset_configure_registers`。包含： -- 处理器子系统复位 : 复位处理器及处理器子系统。 - -- 功能子系统复位 : 复位各功能子系统及功能模块。 - -- 功能模块复位 : 复位各功能模块。 - -处理器子系统软复位 -~~~~~~~~~~~~~~~~~~ - -操作寄存器 SOFT_AC_RSTN_0 可对处理器及子系统做软复位，配置寄存器写 0 后，复位控制器会等待 24us 延时后才触发相应处理器复位。这段期间处理器应结束对总线之访问，以避免复位后总线挂死。触发复位后对应之复位信号会持续 8us 后自动解除，处理器及处理器子系统完成复位并开始启动。 +- 系统软复位 : 复位全芯片，除少部分电路及 RTC 内部电路。 -功能子系统及功能模块软复位 -~~~~~~~~~~~~~~~~~~~~~~~~~~ +- 处理器子系统复位 : 复位处理器及处理器子系统。操作寄存器 SOFT_CPUAC_RSTN 可对处理器及子系统做软复位，配置寄存器写 0 后，复位控制器会等待 24us 延时后才触发相应处理器复位。这段期间处理器应结束对总线之访问，以避免复位后总线挂死。触发复位后对应之复位信号会持续 8us 后自动解除，处理器及处理器子系统完成复位并开始启动。 -操作寄存器 SOFT_RSTN_0 ~ 3，可对各功能模块进行软复位。复位配置为低电平有效，复位信号并不会自动清除，故软件配置相应寄存器为 0 触发复位后，亦需配置为 1 解除复位。复位前须确保各功能模块及功能子系统内置 DMA 对总线访问与处理器对模块之访问处于闲置状态。否则将使复位失败易造成系统挂死。 +- 功能子系统及功能模块复位: 复位各功能子系统及功能模块。操作寄存器 SOFT_RSTN_0 ~ 3，可对各功能模块进行软复位。复位配置为低电平有效，复位信号并不会自动清除，故软件配置相应寄存器为 0 触发复位后，亦需配置为 1 解除复位。复位前须确保各功能模块及功能子系统内置 DMA 对总线访问与处理器对模块之访问处于闲置状态。否则将使复位失败易造成系统挂死。 diff --git a/SG200X/TRM/contents/cn/reset/reset_registers.rst b/SG200X/TRM/contents/cn/reset/reset_registers.rst index 22cdaaf..2440afe 100644 --- a/SG200X/TRM/contents/cn/reset/reset_registers.rst +++ b/SG200X/TRM/contents/cn/reset/reset_registers.rst @@ -1,3 +1,5 @@ +.. _section_reset_configure_registers: + 复位配置寄存器 -------------- diff --git a/SG200X/TRM/contents/cn/watchdog/functionalities.rst b/SG200X/TRM/contents/cn/watchdog/functionalities.rst index de96c18..c0c90de 100644 --- a/SG200X/TRM/contents/cn/watchdog/functionalities.rst +++ b/SG200X/TRM/contents/cn/watchdog/functionalities.rst @@ -14,11 +14,8 @@ 功能原理 ~~~~~~~~ -WatchDog 的计数初值由寄存器 WDT_TORR 载入，运行基于 1个 32bit 减法计数器。 +WatchDog 运行基于 1个 32bit 减法计数器。其计数初值有两个来源，分别从 WDT_ITORR 和 WDT_TORR 载入，并依据 ITOR_MODE 的值计算得到（具体计算方法参考 :ref:`table_wdt_torr` 中的描述）。WDT_ITORR 用于上电后 WatchDog 的第一次定时器计数，其后的定时器计数基于 WDT_TORR 得到。 在 WatchDog 时钟使能情况下，计数值在每个计数时钟的上升沿减 1。当计数值递减到 0, WatchDog 将产生一个中断。然后在下一个计数时钟上升沿，计数器又从寄存器 WDT_TORR 中重新载入计数初值，开始递减计数。 -如果计数器的计数值第二次计数递减到 0 时, CPU还没有清除 WatchDog 中断，则 WatchDog 将发出复位信号WDT_SYS_RST, 计数器停止计数。 - -用户可以通过设置寄存器 WDT_CR[1] 决定是否在计数器的计数值第一次计数递减到 0 时立刻发出复位信号 WDT_SYS_RST。 - +用户可以通过设置寄存器 WDT_CR[1] 决定是否在计数器的计数值第一次计数递减到 0 时立刻发出复位信号 WDT_SYS_RST，如果设置为 0 则立即发出复位信号，否则如果为 1 则产生一个中断，并开始第二次计数，如果第二次计数递减到 0 时, CPU 还没有清除 WatchDog 中断，则 WatchDog 将发出复位信号 WDT_SYS_RST, 计数器停止计数。 diff --git a/SG200X/TRM/contents/en/peripherals/saradc.rst b/SG200X/TRM/contents/en/peripherals/saradc.rst index f53c83e..2ce1733 100644 --- a/SG200X/TRM/contents/en/peripherals/saradc.rst +++ b/SG200X/TRM/contents/en/peripherals/saradc.rst @@ -30,6 +30,8 @@ Way of Working The CPU configures the scanning channel. Each SARADC controller can configure 3 channels at the same time and start SARADC for channel scanning. After the channel scan completes all enabled channels, the system is notified of the completion of the scan through an interrupt, and the CPU can obtain the conversion results. +After the system is powered on, in order to ensure the SARADC measurement accuracy, it is recommended to calibrate the SARADC module of the chip. The calibration is performed offline. The specific method is to first set saradc_test.reg_saradc_vrefsel to external mode, and then manually adjust saradc_trim.reg_saradc_trim repeatedly until the actual read sampling value is close to the external reference voltage value after conversion to meet the accuracy requirements. After the calibration is completed, record the value of saradc_trim.reg_saradc_trim. Then each time the power is turned on, through software programming, set saradc_test.reg_saradc_vrefsel to external mode and then set the recorded value to saradc_trim.reg_saradc_trim. + .. _section_saradc_register_overview: SARADC Register Overview @@ -53,7 +55,7 @@ Each set of registers has the same definition, taking RTCSYS_SARADC as an exampl +======================+=========+====================================+ | saradc_ctrl | 0x004 | control register | +----------------------+---------+------------------------------------+ - | saradc_status | 0x008 | staus register | + | saradc_status | 0x008 | status register | +----------------------+---------+------------------------------------+ | saradc_cyc_set | 0x00c | saradc waveform setting register | +----------------------+---------+------------------------------------+ @@ -71,6 +73,11 @@ Each set of registers has the same definition, taking RTCSYS_SARADC as an exampl +----------------------+---------+------------------------------------+ | saradc_intr_raw | 0x02c | interrupt raw status register | +----------------------+---------+------------------------------------+ + | saradc_test | 0x030 | test register | + +----------------------+---------+------------------------------------+ + | saradc_trim | 0x034 | trim register | + +----------------------+---------+------------------------------------+ + SARADC Register Description ~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/SG200X/TRM/contents/en/peripherals/uart.rst b/SG200X/TRM/contents/en/peripherals/uart.rst index eb33440..56e01bc 100644 --- a/SG200X/TRM/contents/en/peripherals/uart.rst +++ b/SG200X/TRM/contents/en/peripherals/uart.rst @@ -6,41 +6,41 @@ Overview UART (Universal Asynchronous Receiver Transmitter) is an asynchronous serial communication interface. Its main function is to convert data from peripheral devices to serial and then transfer it to the internal bus, and to convert data from parallel to serial and then output it to external devices. The main function of UART is to interface with the UART of an external chip to achieve communication between the two chips. -This chip provides 5 UART controllers. The relevant overview is as follows: +This chip provides 5 UART controllers. The relevant overview is as follows. Note: Please refer to the specific pin output definition before use. Due to different chip packages (QFN/BGA), some functions may not be exported. For pin definition, refer to :ref:`section_pinmux_pinctrl`. .. This table is relatively small, so there is no need to include a separate file. .. _table_uart_io_infodescribe: .. table:: UART IO pin information - :widths: 1 1 3 - - +------------+-------------+----------------------------------------------+ - | Controller | Mode | IO Pin | - +============+=============+==============================================+ - | UART0 | 2-line UART | UART0_TX/UART0_RX | - +------------+-------------+----------------------------------------------+ - | UART1 |2/4-line UART| UART1_TX/UART1_RX/UART1_CTS/UART1_RTS | - | | +----------------------------------------------+ - | | | XGPIOA[20]/ XGPIOA[21]/ XGPIOA[22]/ | - | | | XGPIOA[26] | - +------------+-------------+----------------------------------------------+ - | UART2 |2/4-line UART| UART2_TX/UART2_RX/UART2_CTS/UART2_RTS | - | | +----------------------------------------------+ - | | | XGPIOA[20]/ XGPIOA[21]/ XGPIOA[22]/ | - | | | XGPIOA[26] | - | | +----------------------------------------------+ - | | | IIC2_SDA/IIC2_SCL | - +------------+-------------+----------------------------------------------+ - | UART3 |2/4-line UART| SPI0_CS_X/SPI0_SCK/SPI0_SDI/SPI0_SDO | - | | +----------------------------------------------+ - | | | VI_DATA22/VI_DATA21/VI_DATA24/VI_DATA23 | - | | +----------------------------------------------+ - | | | PWM3/PWM2 | - +------------+-------------+----------------------------------------------+ - | UART4 | 2-line UART | XGPIOA[22]/ XGPIOA[26] | - | | +----------------------------------------------+ - | | | UART1_RTS/UART1_CTS | - +------------+-------------+----------------------------------------------+ + :widths: 1 1 + + +------------+-------------+ + | Controller | Mode | + +============+=============+ + | UART0 | 2-line UART | + +------------+-------------+ + | UART1 |2/4-line UART| + | | + + | | | + | | | + +------------+-------------+ + | UART2 |2/4-line UART| + | | + + | | | + | | | + | | + + | | | + +------------+-------------+ + | UART3 |2/4-line UART| + | | + + | | | + | | + + | | | + +------------+-------------+ + | UART4 | 2-line UART | + | | + + | | | + +------------+-------------+ Features ~~~~~~~~ diff --git a/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst b/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst index e53dfdb..cca2b5c 100644 --- a/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst +++ b/SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst @@ -1,3 +1,5 @@ +.. _section_pinmux_pinctrl: + PinMux and PinCtrl ================== diff --git a/SG200X/TRM/contents/en/reset/reset_control.rst b/SG200X/TRM/contents/en/reset/reset_control.rst index 2faad8a..f46ae7f 100644 --- a/SG200X/TRM/contents/en/reset/reset_control.rst +++ b/SG200X/TRM/contents/en/reset/reset_control.rst @@ -1,51 +1,32 @@ Reset Control ------------- +There are three levels of reset management modules inside the chip to manage the reset of the entire chip, subsystems, and various functional modules. + .. _diagram_reset_block: .. figure:: ../../../../media/image6.png :align: center Reset management module block diagram -Power On Reset -~~~~~~~~~~~~~~ - -A Power-On-Reset (POR) is generated by the real-time clock module in conjunction with global power management and crystal timing. See section :ref:`section_rtc` for details. - -System Hard Reset -~~~~~~~~~~~~~~~~~ - -System Hard Reset is generated by Reset Ctrl Level2. It performs a hard reset on the global chip including subsystems and functional modules. The source is from the following channels: +The Reset Ctrl Level 1 circuit is responsible for the system power-on reset function. The power-on reset (POR) is generated by the real-time clock module in conjunction with the global power management and crystal timing. For details, refer to the section :ref:`section_rtc`. Level 1 Reset can be triggered in the following ways: - Power on reset -- Watchdog reset - - Overheat protection reset -- External reset pin (RSTN) +- Watchdog reset: When RCT_CTRL0.hw_wdg_rst_en is 1 (see :ref:`table_rtc_ctrl0`) and bit[0] of sys_ctrl_reg.reg_sw_root_reset_en is 0 (see :ref:`table_sys_ctrl_reg`), the watchdog timer times out and triggers a system reset. - - Built-in debounce circuit, RSTN high and low level effective signals must reach 6.56ms. +The Reset Ctrl Level 2 circuit is responsible for generating a System Hard Reset, which performs a hard reset on the chip globally including subsystems and functional modules. Level 2 Reset can be triggered in the following ways: -Soft Reset -~~~~~~~~~~ +- Watchdog reset: When bit[0] of sys_ctrl_reg.reg_sw_root_reset_en is 1 (see :ref:`table_sys_ctrl_reg`), the watchdog timer times out and triggers a system reset. -Soft Reset control is implemented by Reset Ctrl Level3 by configuring the corresponding reset configuration register (Reset CRG), including: +- External reset pin (RSTN), which has beuilt-in debounce circuit, RSTN high and low level effective signals must reach 6.56ms. -- System soft reset: Reset the entire chip, except for a few circuits and RTC internal circuits. +The Reset Ctrl Level 3 circuit is responsible for providing the reset configuration register (Reset CRG) corresponding to the soft reset control. For details, refer to :ref:`section_reset_configure_registers`. It includes: -- Processor subsystem reset: Resets the processor and processor subsystem. - -- Functional subsystem reset: Reset each functional subsystem and functional modules. - -- Function module reset: Reset each function module. - -Processor subsystem soft reset -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Programming of register SOFT_AC_RSTN_0 can soft reset the processor and subsystem. After writing 0 to the configuration register, the reset controller will wait for a 24us delay before triggering the corresponding processor reset. During this period, the processor should end access to the bus to avoid the bus hanging after reset. After triggering the reset, the corresponding reset signal will last for 8us and then be automatically released. The processor and processor subsystem will complete the reset and start booting. +- System soft reset: Reset the entire chip, except for a few circuits and RTC internal circuits. -Soft reset of functional subsystems and functional modules -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +- Processor subsystem reset: Resets the processor and processor subsystem. Programming of register SOFT_CPUAC_RSTN can soft reset the processor and subsystem. After writing 0 to the configuration register, the reset controller will wait for a 24us delay before triggering the corresponding processor reset. During this period, the processor should end access to the bus to avoid the bus hanging after reset. After triggering the reset, the corresponding reset signal will last for 8us and then be automatically released. The processor and processor subsystem will complete the reset and start booting. -Programming of register SOFT_RSTN_0 ~ 3 can soft reset each functional module. The reset configuration is active low, and the reset signal will not be cleared automatically. Therefore, after the software configures the corresponding register to 0 to trigger the reset, it also needs to be configured to 1 to release the reset. Before resetting, make sure that the built-in DMA of each functional module and functional subsystem to the bus and the processor to the module are idle. Otherwise, the reset will fail and the system may hang. +- Functional subsystem and modules reset: Reset each functional subsystem and functional modules. Programming of register SOFT_RSTN_0 ~ 3 can soft reset each functional module. The reset configuration is active low, and the reset signal will not be cleared automatically. Therefore, after the software configures the corresponding register to 0 to trigger the reset, it also needs to be configured to 1 to release the reset. Before resetting, make sure that the built-in DMA of each functional module and functional subsystem to the bus and the processor to the module are idle. Otherwise, the reset will fail and the system may hang. diff --git a/SG200X/TRM/contents/en/reset/reset_registers.rst b/SG200X/TRM/contents/en/reset/reset_registers.rst index 9e07aa9..65d2547 100644 --- a/SG200X/TRM/contents/en/reset/reset_registers.rst +++ b/SG200X/TRM/contents/en/reset/reset_registers.rst @@ -1,3 +1,5 @@ +.. _section_reset_configure_registers: + Reset configuration register ---------------------------- diff --git a/SG200X/TRM/contents/en/watchdog/functionalities.rst b/SG200X/TRM/contents/en/watchdog/functionalities.rst index 4f4bd38..07c7739 100644 --- a/SG200X/TRM/contents/en/watchdog/functionalities.rst +++ b/SG200X/TRM/contents/en/watchdog/functionalities.rst @@ -14,10 +14,8 @@ Application Block Diagram Functional Principle ~~~~~~~~~~~~~~~~~~~~ -The initial counting value of WatchDog is loaded from the register WDT_TORR, and the operation is based on a 32-bit subtraction counter. +WatchDog runs based on a 32-bit down counter. Its initial count value has two sources, loaded from WDT_ITORR and WDT_TORR respectively, and calculated based on the value of ITOR_MODE (for specific calculation methods, refer to the description in :ref:`table_wdt_torr`). WDT_ITORR is used for the first timer count of WatchDog after power-on, and subsequent timer counts are based on WDT_TORR. When the WatchDog clock is enabled, the count value is decremented by 1 on the rising edge of each count clock. When the count value decreases to 0, WatchDog will generate an interrupt. Then at the next rising edge of the counting clock, the counter reloads the initial counting value from the register WDT_TORR and starts counting down. -If the count value of the counter decreases to 0 for the second time and the CPU has not cleared the WatchDog interrupt, WatchDog will issue a reset signal WDT_SYS_RST and the counter will stop counting. - -The user can decide whether to send the reset signal WDT_SYS_RST immediately when the counter's count value decreases to 0 for the first time by setting the register WDT_CR[1]. +The user can set the register WDT_CR[1] to decide whether to send a reset signal WDT_SYS_RST immediately when the counter count value decreases to 0 for the first time. If it is set to 0, a reset signal is sent immediately. Otherwise, if it is 1, an interrupt is generated and the second count starts. If the CPU has not cleared the WatchDog interrupt when the second count decreases to 0, WatchDog will send a reset signal WDT_SYS_RST and the counter will stop counting. diff --git a/SG200X/TRM/media/image6.png b/SG200X/TRM/media/image6.png index 9c694f3..73d0780 100644 Binary files a/SG200X/TRM/media/image6.png and b/SG200X/TRM/media/image6.png differ diff --git a/SG200X/TRM/sg2000_cn/Makefile b/SG200X/TRM/sg2000_cn/Makefile index d68207c..44b1a29 100644 --- a/SG200X/TRM/sg2000_cn/Makefile +++ b/SG200X/TRM/sg2000_cn/Makefile @@ -11,8 +11,8 @@ BUILDDIR = build PROJECT = sg2000 DOC_TYPE = trm DOC_LANG = cn -RELEASE = 1.0-beta -RELEASE_DATE = 2024-03-22 +RELEASE = 1.0 +RELEASE_DATE = 2024-06-17 COPYRIGHT = "2024 SOPHGO Co., Ltd" AUTHOR = Sophgo diff --git a/SG200X/TRM/sg2000_cn/source/index.rst b/SG200X/TRM/sg2000_cn/source/index.rst index 70844b8..57c527d 100644 --- a/SG200X/TRM/sg2000_cn/source/index.rst +++ b/SG200X/TRM/sg2000_cn/source/index.rst @@ -12,6 +12,7 @@ SG2000 技术参考手册 =============== ============ ===================================== 1.0-alpha 2023/11/23 初稿 1.0-beta 2024/03/22 转化为 reStructuredText 格式 + 1.0 2024/06/17 修复累积问题，正式发布 v1.0 =============== ============ ===================================== diff --git a/SG200X/TRM/sg2000_en/Makefile b/SG200X/TRM/sg2000_en/Makefile index 5194c75..dc508fe 100644 --- a/SG200X/TRM/sg2000_en/Makefile +++ b/SG200X/TRM/sg2000_en/Makefile @@ -11,8 +11,8 @@ BUILDDIR = build PROJECT = sg2000 DOC_TYPE = trm DOC_LANG = en -RELEASE = 1.0-beta -RELEASE_DATE = 2024-03-22 +RELEASE = 1.0 +RELEASE_DATE = 2024-06-17 COPYRIGHT = "2024 SOPHGO Co., Ltd" AUTHOR = Sophgo diff --git a/SG200X/TRM/sg2000_en/source/index.rst b/SG200X/TRM/sg2000_en/source/index.rst index 95af128..9a88137 100644 --- a/SG200X/TRM/sg2000_en/source/index.rst +++ b/SG200X/TRM/sg2000_en/source/index.rst @@ -12,6 +12,7 @@ SG2000 Technical Reference Manual =============== ============ ===================================== 1.0-alpha 2023/11/23 Initial Version 1.0-beta 2024/03/22 Converted to reStructuredText + 1.0 2024/06/17 Fixed cumulative issues and officially released v1.0 =============== ============ ===================================== diff --git a/SG200X/TRM/sg2002_cn/Makefile b/SG200X/TRM/sg2002_cn/Makefile index 9813b6e..a5aa8a8 100644 --- a/SG200X/TRM/sg2002_cn/Makefile +++ b/SG200X/TRM/sg2002_cn/Makefile @@ -11,8 +11,8 @@ BUILDDIR = build PROJECT = sg2002 DOC_TYPE = trm DOC_LANG = cn -RELEASE = 1.0-beta -RELEASE_DATE = 2024-02-26 +RELEASE = 1.0 +RELEASE_DATE = 2024-06-17 COPYRIGHT = "2023 SOPHGO Co., Ltd" AUTHOR = Sophgo diff --git a/SG200X/TRM/sg2002_cn/source/index.rst b/SG200X/TRM/sg2002_cn/source/index.rst index 3b074d6..35aa66e 100644 --- a/SG200X/TRM/sg2002_cn/source/index.rst +++ b/SG200X/TRM/sg2002_cn/source/index.rst @@ -12,6 +12,7 @@ SG2002 技术参考手册 =============== ============ ===================================== 1.0-alpha 2023/11/23 初稿 1.0-beta 2024/02/26 转化为 reStructuredText 格式 + 1.0 2024/06/17 修复累积问题，正式发布 v1.0 =============== ============ ===================================== diff --git a/SG200X/TRM/sg2002_en/Makefile b/SG200X/TRM/sg2002_en/Makefile index 3c40e3d..f008760 100644 --- a/SG200X/TRM/sg2002_en/Makefile +++ b/SG200X/TRM/sg2002_en/Makefile @@ -11,8 +11,8 @@ BUILDDIR = build PROJECT = sg2002 DOC_TYPE = trm DOC_LANG = en -RELEASE = 1.0-beta -RELEASE_DATE = 2024-02-26 +RELEASE = 1.0 +RELEASE_DATE = 2024-06-17 COPYRIGHT = "2024 SOPHGO Co., Ltd" AUTHOR = Sophgo diff --git a/SG200X/TRM/sg2002_en/source/index.rst b/SG200X/TRM/sg2002_en/source/index.rst index 135a9d8..be62f25 100644 --- a/SG200X/TRM/sg2002_en/source/index.rst +++ b/SG200X/TRM/sg2002_en/source/index.rst @@ -12,6 +12,7 @@ SG2002 Technical Reference Manual =============== ============ ===================================== 1.0-alpha 2023/11/23 Initial Version 1.0-beta 2024/02/26 Converted to reStructuredText + 1.0 2024/06/17 Fixed cumulative issues and officially released v1.0 =============== ============ =====================================