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fuse.log
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fuse.log
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Running: D:\xilinx\xilinx_installations\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o D:/activeHdlProjects/mips-alu/ALU/datapath_tb_isim_beh.exe -prj D:/activeHdlProjects/mips-alu/ALU/datapath_tb_beh.prj work.datapath_tb work.glbl
ISim P.20131013 (signature 0x7708f090)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Analyzing Verilog file "D:/activeHdlProjects/mips-alu/ALU/register_file.v" into library work
Analyzing Verilog file "D:/activeHdlProjects/mips-alu/ALU/control_unit.v" into library work
Analyzing Verilog file "D:/activeHdlProjects/mips-alu/ALU/alu.v" into library work
Analyzing Verilog file "D:/activeHdlProjects/mips-alu/ALU/datapath.v" into library work
WARNING:HDLCompiler:35 - "D:/activeHdlProjects/mips-alu/ALU/datapath.v" Line 25: <ALUCtrl> is already implicitly declared earlier.
WARNING:HDLCompiler:35 - "D:/activeHdlProjects/mips-alu/ALU/datapath.v" Line 53: <readData1> is already implicitly declared earlier.
Analyzing Verilog file "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" into library work
WARNING:HDLCompiler:568 - "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" Line 38: Constant value is truncated to fit in <8> bits.
WARNING:HDLCompiler:568 - "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" Line 40: Constant value is truncated to fit in <8> bits.
WARNING:HDLCompiler:568 - "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" Line 42: Constant value is truncated to fit in <8> bits.
WARNING:HDLCompiler:568 - "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" Line 44: Constant value is truncated to fit in <8> bits.
WARNING:HDLCompiler:568 - "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" Line 46: Constant value is truncated to fit in <8> bits.
WARNING:HDLCompiler:568 - "D:/activeHdlProjects/mips-alu/ALU/datapath_tb.v" Line 48: Constant value is truncated to fit in <8> bits.
Analyzing Verilog file "D:/xilinx/xilinx_installations/14.7/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
WARNING:HDLCompiler:189 - "D:/activeHdlProjects/mips-alu/ALU/datapath.v" Line 21: Size mismatch in connection of port <result>. Formal port size is 32-bit while actual signal size is 1-bit.
Completed static elaboration
Compiling module alu
Compiling module control_unit
Compiling module register_file
Compiling module datapath
Compiling module datapath_tb
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 Verilog Units
Built simulation executable D:/activeHdlProjects/mips-alu/ALU/datapath_tb_isim_beh.exe
Fuse Memory Usage: 28972 KB
Fuse CPU Usage: 656 ms