Ubuntu packaging for the SiFive kernel for the HiFive Premier P550 board #6
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dts, dtsi and include files for HiFive Premier P550 boards based on EIC7700 SoC. Signed-off-by: linmin <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: linmin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: huangyifeng <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
- Added wfe and iomb functions for riscv - Added memory port to system port and system port to memory port conversion macros to access uncached memory through system port - Modified pte_pfn and pfn_pte functions To access uncache memory, we need to remap physical address to system port address. System port pfn address will be stored in pte if uncached bit is set. Signed-off-by: linmin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Add arch_dma_set_uncached and arch_dma_clear_uncached Signed-off-by: linmin <[email protected]> Signed-off-by: Pritesh Patel <[email protected]>
Signed-off-by: linmin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Clearing interrupt bits from interrupt handler because interrupt mode of smmu is oneshot but plic only support high level mode Signed-off-by: linmin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: linmin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
The EIC7700 has non-coherent DMAs but predate the standard RISC-V Zicbom extension, so instead we need to use this cache controller for non-standard cache management operations Reference: torvalds/linux@0d5701d Signed-off-by: Emil Renner Berthing <[email protected]> Signed-off-by: Conor Dooley <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Enabled all available cache ways to be used as cache. This change is required for CPU performance improvement. Out of reset, only way 0 is enabled and the disabled ways are addressable in L2-LIM(Loosely Integrated Memory). Signed-off-by: Pritesh Patel <[email protected]>
- Removed cfgr clock as aon dma has separate cfg clk register bit while dma0 havn't. Since dma cfg clk is default on we do not need to control it - Add arst and prst reset control - Power on tbu and configure sid from hw init Signed-off-by: xuxiang <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: liangshuang <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: huangyifeng <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: ningyu <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: luyulin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: Yang Wei <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: Yang Wei <[email protected]> Signed-off-by: Pritesh Patel <[email protected]>
Signed-off-by: fanglifei <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: xuxiang <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: ningyu <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: luyulin <[email protected]> Signed-off-by: Pritesh Patel <[email protected]>
Add custom ES8328 audio codec driver for hifive premier p550 board Add eswin i2s driver Signed-off-by: denglei <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: xuxiang <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]> Signed-off-by: Pritesh Patel <[email protected]>
Signed-off-by: luyulin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
Signed-off-by: luyulin <[email protected]> Signed-off-by: Darshan Prajapati <[email protected]> Signed-off-by: Pinkesh Vaghela <[email protected]>
HENVCFG register is not present in EIC7700 SOC. So disabled writing this register Signed-off-by: Pritesh Patel <[email protected]>
Signed-off-by: Yang Wei <[email protected]> Signed-off-by: Pritesh Patel <[email protected]>
Signed-off-by: huangyifeng <[email protected]> Signed-off-by: Pritesh Patel <[email protected]>
The SiFive Performance P550 core features an out-of-order microarchitecture which exposes the same PMU events as Bullet, plus events for UTLB hits and PTE cache misses/hits. Signed-off-by: Eric Lin <[email protected]> Co-developed-by: Samuel Holland <[email protected]> Signed-off-by: Samuel Holland <[email protected]>
Signed-off-by: Icenowy Zheng <[email protected]>
We add SBI debug console extension related defines/enum to the asm/sbi.h header. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Signed-off-by: Anup Patel <[email protected]>
Let us provide SBI debug console helper routines which can be shared by serial/earlycon-riscv-sbi.c and hvc/hvc_riscv_sbi.c. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
We extend the existing RISC-V SBI earlycon support to use the new RISC-V SBI debug console extension. Signed-off-by: Anup Patel <[email protected]> Reviewed-by: Andrew Jones <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Pritesh Patel <[email protected]>
Removed 1.5GHz to 1.8GHz cpu freq from opp-table as the max supported freq for CPU is 1.4GHz Signed-off-by: Pinkesh Vaghela <[email protected]>
Updated kernel command line - Removed stale command lines - Moved serial console configs to extlinux conf file Signed-off-by: Pritesh Patel <[email protected]>
- use eswin/eic7700-hifive-premier-p550.dtb as device-tree name - use "sifive,hifive-premier-p550", "eswin,eic7700" as compatible strings Signed-off-by: Pritesh Patel <[email protected]> Signed-off-by: Heinrich Schuchardt <[email protected]>
With these changes Docker and Ubuntu Firewall are functional. Signed-off-by: Pritesh Patel <[email protected]> Signed-off-by: Heinrich Schuchardt <[email protected]>
Enabled HDMI sound related configs Signed-off-by: Pritesh Patel <[email protected]>
Memory size will be passed through kernel command line based on the RAM detected by U-Boot Signed-off-by: Pritesh Patel <[email protected]>
This fixes the following section mismatch error:
WARNING: modpost: drivers/ata/ahci_eswin: section mismatch in reference: \
ahci_probe+0x38 (section: .text) -> eswin_reset (section: .init.text)
ERROR: modpost: Section mismatches detected.
Set CONFIG_SECTION_MISMATCH_WARN_ONLY=y to allow them.
Fixes: 06d67c2 ("drivers: ata: Add ESWIN sata driver")
Signed-off-by: Emil Renner Berthing <[email protected]>
When compiling with gcc version 14.0.0 20231220 (experimental)
and W=1, I've noticed the following warning:
fs/btrfs/send.c: In function 'btrfs_ioctl_send':
fs/btrfs/send.c:8208:44: warning: 'kvcalloc' sizes specified with 'sizeof'
in the earlier argument and not in the later argument [-Wcalloc-transposed-args]
8208 | sctx->clone_roots = kvcalloc(sizeof(*sctx->clone_roots),
| ^
Since 'n' and 'size' arguments of 'kvcalloc()' are multiplied to
calculate the final size, their actual order doesn't affect the result
and so this is not a bug. But it's still worth to fix it.
Signed-off-by: Dmitry Antipov <[email protected]>
Reviewed-by: David Sterba <[email protected]>
Signed-off-by: David Sterba <[email protected]>
(cherry picked from commit 6ff09b6)
Signed-off-by: Emil Renner Berthing <[email protected]>
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Signed-off-by: Emil Renner Berthing <[email protected]>
On riscv, it appears that all kernel modules are generated with an excesive amount of local symbols and assembly automatic generated symbols increasing the size of stripped .ko modules multiple times over similar ones on other architectures. When stripping .ko on riscv, discard these local symbols too, which should make our module sizes somewhat more reasonable. BugLink: https://bugs.launchpad.net/bugs/1964335 Signed-off-by: Andy Whitcroft <[email protected]> Signed-off-by: Dimitri John Ledkov <[email protected]> Acked-by: Andrea Righi <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]>
This also limits the annotations to the riscv64 architecture. Signed-off-by: Emil Renner Berthing <[email protected]>
The ESWIN EIC7700 SoC has non-coherent peripheral DMAs and handles it in a non-standard way, so unfortunately this kernel cannot be built to support multiple SoCs. Hence we disable support for other platforms and enable drivers for the EIC7700. Signed-off-by: Emil Renner Berthing <[email protected]>
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