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This repository has been archived by the owner on Mar 2, 2021. It is now read-only.
@mcd500 Hello, first of all, thanks for adding support for the no-PCIe version on vc707. I generate Verilog and bitstreams using the following command successfully.
make -j16 CONFIG=DevKitU500FPGADesign_WithDevKit100MHz MODEL=VC707BaseShell -f Makefile.vc707-u500devkit verilog
make -j16 CONFIG=DevKitU500FPGADesign_WithDevKit100MHz MODEL=VC707BaseShell -f Makefile.vc707-u500devkit mcs
And now, I want to make some changes to the Chisel code. In rocket-chip, the "CONFIG=xxx" refers to a class in "src/main/scala/system/Configs.scala", so I can change it easily. But in this repository, I can't find a class named "DevKitU500FPGADesign_WithDevKit100MHz".
I'm confused about this, can you give me some advice? Thanks a lot!
The text was updated successfully, but these errors were encountered:
@mcd500 Hello, first of all, thanks for adding support for the no-PCIe version on vc707. I generate Verilog and bitstreams using the following command successfully.
And now, I want to make some changes to the Chisel code. In rocket-chip, the "CONFIG=xxx" refers to a class in "src/main/scala/system/Configs.scala", so I can change it easily. But in this repository, I can't find a class named "DevKitU500FPGADesign_WithDevKit100MHz".
I'm confused about this, can you give me some advice? Thanks a lot!
The text was updated successfully, but these errors were encountered: