From 9901454ab4c74e1b66cb7812e61baa1001eb58bd Mon Sep 17 00:00:00 2001 From: Alwin Joshy Date: Tue, 10 Sep 2024 17:46:44 +1000 Subject: [PATCH] bench/riscv: enable configuration of benchmark options Applies patch from https://github.com/seL4/sel4bench/pull/20. This was not merged previously as RISC-V did not implement the hardware and fault benchmarks, but this is no longer the case. Signed-off-by: Alwin Joshy --- apps/sel4bench/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/apps/sel4bench/CMakeLists.txt b/apps/sel4bench/CMakeLists.txt index 97ef2df9..93a291f7 100644 --- a/apps/sel4bench/CMakeLists.txt +++ b/apps/sel4bench/CMakeLists.txt @@ -39,6 +39,7 @@ if( (KernelArchX86 AND KernelExportPMCUser AND KernelX86DangerousMSR) OR (KernelArchARM AND KernelArmExportPMUUser) OR (KernelArchArmCortexA8 AND KernelDangerousCodeInjection) + OR (KernelArchRiscV) ) set(DefaultBenchDeps TRUE) else()