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feat/impl riscv ADD instruction #85

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19 changes: 19 additions & 0 deletions singer-utils/src/chip_handler.rs
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@ pub mod global_state;
pub mod memory;
pub mod ram_handler;
pub mod range;
pub mod register;
pub mod rom_handler;
pub mod stack;

Expand Down Expand Up @@ -50,6 +51,24 @@ pub trait StackChipOperations<Ext: ExtensionField>: OAMOperations<Ext> {
);
}

pub trait RegisterChipOperations<Ext: ExtensionField>: OAMOperations<Ext> {
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fn register_read(
&mut self,
circuit_builder: &mut CircuitBuilder<Ext>,
register_id: &[CellId],
timestamp: &[CellId],
values: &[CellId],
);

fn register_store(
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&mut self,
circuit_builder: &mut CircuitBuilder<Ext>,
register_id: &[CellId],
timestamp: &[CellId],
values: &[CellId],
);
}

pub trait RangeChipOperations<Ext: ExtensionField>: ROMOperations<Ext> {
fn range_check_stack_top(
&mut self,
Expand Down
48 changes: 48 additions & 0 deletions singer-utils/src/chip_handler/register.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,48 @@
use ark_std::iterable::Iterable;
use ff_ext::ExtensionField;
use itertools::Itertools;
use simple_frontend::structs::{CellId, CircuitBuilder, MixedCell};

use crate::structs::{RAMHandler, RAMType};

use super::{OAMOperations, RegisterChipOperations};

impl<Ext: ExtensionField> RegisterChipOperations<Ext> for RAMHandler<Ext> {
fn register_read(
&mut self,
circuit_builder: &mut CircuitBuilder<Ext>,
register_id: &[CellId],
timestamp: &[CellId],
values: &[CellId],
) {
let key = [
vec![MixedCell::Constant(Ext::BaseField::from(
RAMType::Memory as u64,
))],
register_id.iter().map(|&x| x.into()).collect_vec(),
]
.concat();
let timestamp = timestamp.iter().map(|&x| MixedCell::Cell(x)).collect_vec();
let values = values.iter().map(|&x| MixedCell::Cell(x)).collect_vec();
self.oam_load_mixed(circuit_builder, &timestamp, &key, &values);
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}

fn register_store(
&mut self,
circuit_builder: &mut CircuitBuilder<Ext>,
register_id: &[CellId],
timestamp: &[CellId],
values: &[CellId],
) {
let key = [
vec![MixedCell::Constant(Ext::BaseField::from(
RAMType::Memory as u64,
))],
register_id.iter().map(|&x| x.into()).collect_vec(),
]
.concat();
let timestamp = timestamp.iter().map(|&x| x.into()).collect_vec();
let values = values.iter().map(|&x| x.into()).collect_vec();
self.oam_load_mixed(circuit_builder, &timestamp, &key, &values);
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}
}
21 changes: 21 additions & 0 deletions singer-utils/src/constants.rs
Original file line number Diff line number Diff line change
Expand Up @@ -27,4 +27,25 @@ pub enum OpcodeType {
SWAP2 = 0x91,
SWAP4 = 0x93,
RETURN = 0xf3,

// risc-v
RV_ADD = 0x33,
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}

// l

// impl RV64Opcode {
// // Type R
// pub const ADD: RV64Opcode = RV64Opcode::R;
// pub const SUB: RV64Opcode = RV64Opcode::R;
// pub const SLL: RV64Opcode = RV64Opcode::R;
// pub const SLT: RV64Opcode = RV64Opcode::R;
// pub const SLTU: RV64Opcode = RV64Opcode::R;
// pub const XOR: RV64Opcode = RV64Opcode::R;
// pub const SRL: RV64Opcode = RV64Opcode::R;
// pub const SRA: RV64Opcode = RV64Opcode::R;
// pub const OR: RV64Opcode = RV64Opcode::R;
// pub const AND: RV64Opcode = RV64Opcode::R;
// // Type I
// pub const ADDI: RV64Opcode = RV64Opcode::I_ARITH;
// }
2 changes: 2 additions & 0 deletions singer-utils/src/structs.rs
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ pub enum RAMType {
Stack,
Memory,
GlobalState,
Register,
}

#[derive(Clone, Debug, Copy, EnumIter)]
Expand Down Expand Up @@ -56,3 +57,4 @@ pub type UInt64 = UInt<64, VALUE_BIT_WIDTH>;
pub type PCUInt = UInt64;
pub type TSUInt = UInt<56, 56>;
pub type StackUInt = UInt<{ EVM_STACK_BIT_WIDTH as usize }, { VALUE_BIT_WIDTH as usize }>;
pub type RegisterUInt = UInt64;
5 changes: 4 additions & 1 deletion singer/src/instructions.rs
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ use self::{
add::AddInstruction, calldataload::CalldataloadInstruction, dup::DupInstruction,
gt::GtInstruction, jump::JumpInstruction, jumpdest::JumpdestInstruction,
jumpi::JumpiInstruction, mstore::MstoreInstruction, pop::PopInstruction, push::PushInstruction,
ret::ReturnInstruction, swap::SwapInstruction,
ret::ReturnInstruction, riscv_add::RVAddInstruction, swap::SwapInstruction,
};

// arithmetic
Expand All @@ -41,6 +41,9 @@ pub mod mstore;
// system
pub mod calldataload;

// riscv
pub mod riscv_add;
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Few advices to isolated different ISA implementation

  • define a new package riscv for all riscv instruction, whcih can be under singer/src/instructions/riscv/
  • this mod can be toggle on/off via a feature flat riscv

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fixed in d8b52ba


#[derive(Clone, Debug)]
pub struct SingerCircuitBuilder<E: ExtensionField> {
/// Opcode circuits
Expand Down
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