feat/impl riscv ADD instruction

[KimiWu123]

Description

Implemented RISC-V ADD instruction. The implemenation is basically the same as ADD operation in EVM. The only difference is replacing stack operations with register operations. Another change is to isolate RISC-V instruction enumerations.

Changes

• added Register gadget to manage register operations.
• added risc-v related files to avoid touching existing code.
  • two enums,RV64IOpcode and RvInstructions in riscv_constant.rs
  • instructions_riscv_ext.rs to handle RISC-V related logic

Benchmark

Minor performance improved

EVM ADD  time:    [1.8772 s 1.8873 s 1.8961 s]
RISC-V ADD time:  [1.6199 s 1.6339 s 1.6495 s]
          change: [-14.351% -13.428% -12.589%]

[hero78119]

Just left few comments :)

also discussed with @KimiWu123 that we can add benchmarks for riscv add to have a insightful on evm_add 256 bits stack operation vs riscv64 register operation comparison

[hero78119]

Few advices to isolated different ISA implementation

• define a new package riscv for all riscv instruction, whcih can be under singer/src/instructions/riscv/
• this mod can be toggle on/off via a feature flat riscv

[KimiWu123]

fixed in d8b52ba

[hero78119]

few suggested comments for naming

[KimiWu123]

Lint errors has been addressed. To make review easier, I'll commit it after this PR is approved

[hero78119]

Hi, just recalled and left few comment related to offline memory checking protocol correctness

[hero78119]

Except for a nitpick, other LGTM!

[KimiWu123]

Lint errors has been addressed. To make review easier, I'll commit it after this PR is approved

Format error has been fixed in cfe21fc, but still are some clippy errors. I think we can fix it in later PR.

[hero78119]

Thanks for @kunxian-xia to point out that rs1, rs2, rd might be the same registers follow riscv specs, so we should bump next_memory_ts accordingly within opcode. See the discussion #91 (comment)

[KimiWu123]

close it due to having new design #129