From d48c4d2c49033e74b584ccb0f3b5d933cb17edaf Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Fri, 25 Oct 2024 14:53:59 +0800 Subject: [PATCH 1/5] Remove dead code --- ceno_emul/src/rv32im.rs | 2 -- ceno_zkvm/src/chip_handler.rs | 2 -- ceno_zkvm/src/chip_handler/memory.rs | 1 - ceno_zkvm/src/expression/monomial.rs | 5 ----- 4 files changed, 10 deletions(-) diff --git a/ceno_emul/src/rv32im.rs b/ceno_emul/src/rv32im.rs index a150918e3..6273e0f48 100644 --- a/ceno_emul/src/rv32im.rs +++ b/ceno_emul/src/rv32im.rs @@ -88,7 +88,6 @@ pub struct Emulator { } #[derive(Debug)] -#[allow(dead_code)] pub enum TrapCause { InstructionAddressMisaligned, InstructionAccessFault, @@ -218,7 +217,6 @@ impl DecodedInstruction { } } - #[allow(dead_code)] pub fn from_raw(kind: InsnKind, rs1: u32, rs2: u32, rd: u32) -> Self { // limit the range of inputs let rs2 = rs2 & 0x1f; // 5bits mask diff --git a/ceno_zkvm/src/chip_handler.rs b/ceno_zkvm/src/chip_handler.rs index dc1422a73..8d16f342d 100644 --- a/ceno_zkvm/src/chip_handler.rs +++ b/ceno_zkvm/src/chip_handler.rs @@ -55,7 +55,6 @@ pub type AddressExpr = Expression; pub type MemoryExpr = Expression; pub trait MemoryChipOperations, N: FnOnce() -> NR> { - #[allow(dead_code)] fn memory_read( &mut self, name_fn: N, @@ -66,7 +65,6 @@ pub trait MemoryChipOperations, N: FnOnce() ) -> Result<(Expression, AssertLTConfig), ZKVMError>; #[allow(clippy::too_many_arguments)] - #[allow(dead_code)] fn memory_write( &mut self, name_fn: N, diff --git a/ceno_zkvm/src/chip_handler/memory.rs b/ceno_zkvm/src/chip_handler/memory.rs index b89bb4078..9a58c8a04 100644 --- a/ceno_zkvm/src/chip_handler/memory.rs +++ b/ceno_zkvm/src/chip_handler/memory.rs @@ -12,7 +12,6 @@ use ff_ext::ExtensionField; impl<'a, E: ExtensionField, NR: Into, N: FnOnce() -> NR> MemoryChipOperations for CircuitBuilder<'a, E> { - #[allow(dead_code)] fn memory_read( &mut self, name_fn: N, diff --git a/ceno_zkvm/src/expression/monomial.rs b/ceno_zkvm/src/expression/monomial.rs index fa030595f..4c73c557b 100644 --- a/ceno_zkvm/src/expression/monomial.rs +++ b/ceno_zkvm/src/expression/monomial.rs @@ -136,11 +136,6 @@ impl PartialOrd for Expression { } } -#[allow(dead_code)] -fn cmp_field(a: &F, b: &F) -> Ordering { - a.to_canonical_u64().cmp(&b.to_canonical_u64()) -} - fn cmp_ext(a: &E, b: &E) -> Ordering { let a = a.as_bases().iter().map(|f| f.to_canonical_u64()); let b = b.as_bases().iter().map(|f| f.to_canonical_u64()); From ab5c59fd7b2e090d6e3c32000cd026a5dbf62708 Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Fri, 25 Oct 2024 14:55:41 +0800 Subject: [PATCH 2/5] More dead code --- ceno_zkvm/src/instructions/riscv/b_insn.rs | 2 -- ceno_zkvm/src/instructions/riscv/memory/store.rs | 9 +++------ ceno_zkvm/src/instructions/riscv/shift.rs | 2 +- 3 files changed, 4 insertions(+), 9 deletions(-) diff --git a/ceno_zkvm/src/instructions/riscv/b_insn.rs b/ceno_zkvm/src/instructions/riscv/b_insn.rs index b7c74543f..399798398 100644 --- a/ceno_zkvm/src/instructions/riscv/b_insn.rs +++ b/ceno_zkvm/src/instructions/riscv/b_insn.rs @@ -1,5 +1,3 @@ -#![allow(dead_code)] // TODO: remove after BLT, BEQ, … - use ceno_emul::{InsnKind, StepRecord}; use ff_ext::ExtensionField; diff --git a/ceno_zkvm/src/instructions/riscv/memory/store.rs b/ceno_zkvm/src/instructions/riscv/memory/store.rs index fc8f0455f..898d4df86 100644 --- a/ceno_zkvm/src/instructions/riscv/memory/store.rs +++ b/ceno_zkvm/src/instructions/riscv/memory/store.rs @@ -38,8 +38,7 @@ impl RIVInstruction for SWOp { const INST_KIND: InsnKind = InsnKind::SW; } -// this is actually used in test -#[allow(dead_code)] +#[cfg_attr(not(test), allow(dead_code))] pub type SwInstruction = StoreInstruction; pub struct SHOp; @@ -48,8 +47,7 @@ impl RIVInstruction for SHOp { const INST_KIND: InsnKind = InsnKind::SH; } -// this is actually used in test -#[allow(dead_code)] +#[cfg_attr(not(test), allow(dead_code))] pub type ShInstruction = StoreInstruction; pub struct SBOp; @@ -58,8 +56,7 @@ impl RIVInstruction for SBOp { const INST_KIND: InsnKind = InsnKind::SB; } -// this is actually used in test -#[allow(dead_code)] +#[cfg_attr(not(test), allow(dead_code))] pub type SbInstruction = StoreInstruction; impl Instruction diff --git a/ceno_zkvm/src/instructions/riscv/shift.rs b/ceno_zkvm/src/instructions/riscv/shift.rs index 189811dd2..8c99d3d1b 100644 --- a/ceno_zkvm/src/instructions/riscv/shift.rs +++ b/ceno_zkvm/src/instructions/riscv/shift.rs @@ -31,7 +31,7 @@ pub struct ShiftConfig { pub struct ShiftLogicalInstruction(PhantomData<(E, I)>); -#[allow(dead_code)] +#[cfg_attr(not(test), allow(dead_code))] struct SllOp; impl RIVInstruction for SllOp { const INST_KIND: InsnKind = InsnKind::SLL; From 20db9fa58e4e24bccdd66c72fdf30b6723f871b9 Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Fri, 25 Oct 2024 15:08:04 +0800 Subject: [PATCH 3/5] Remove dead code --- ceno_zkvm/src/instructions/riscv/shift.rs | 2 +- ceno_zkvm/src/instructions/riscv/slt.rs | 2 +- ceno_zkvm/src/instructions/riscv/sltu.rs | 2 +- ceno_zkvm/src/scheme/mock_prover.rs | 5 ++-- ceno_zkvm/src/scheme/utils.rs | 4 +-- ceno_zkvm/src/uint.rs | 1 - ceno_zkvm/src/utils.rs | 30 -------------------- ceno_zkvm/src/witness.rs | 1 - gkr-graph/src/structs.rs | 2 +- gkr/src/circuit.rs | 20 ------------- multilinear_extensions/src/virtual_poly.rs | 33 +--------------------- singer/src/scheme.rs | 17 +---------- singer/src/utils.rs | 10 ------- sumcheck/src/structs.rs | 1 - 14 files changed, 11 insertions(+), 119 deletions(-) diff --git a/ceno_zkvm/src/instructions/riscv/shift.rs b/ceno_zkvm/src/instructions/riscv/shift.rs index 8c99d3d1b..f97f23103 100644 --- a/ceno_zkvm/src/instructions/riscv/shift.rs +++ b/ceno_zkvm/src/instructions/riscv/shift.rs @@ -37,7 +37,7 @@ impl RIVInstruction for SllOp { const INST_KIND: InsnKind = InsnKind::SLL; } -#[allow(dead_code)] +#[cfg_attr(not(test), allow(dead_code))] struct SrlOp; impl RIVInstruction for SrlOp { const INST_KIND: InsnKind = InsnKind::SRL; diff --git a/ceno_zkvm/src/instructions/riscv/slt.rs b/ceno_zkvm/src/instructions/riscv/slt.rs index c70f3bdb0..6e0880af4 100644 --- a/ceno_zkvm/src/instructions/riscv/slt.rs +++ b/ceno_zkvm/src/instructions/riscv/slt.rs @@ -17,7 +17,7 @@ pub struct SltConfig { rs1_read: UInt, rs2_read: UInt, - #[allow(dead_code)] + #[cfg_attr(not(test), allow(dead_code))] rd_written: UInt, signed_lt: SignedLtConfig, diff --git a/ceno_zkvm/src/instructions/riscv/sltu.rs b/ceno_zkvm/src/instructions/riscv/sltu.rs index 64d73869a..067375194 100644 --- a/ceno_zkvm/src/instructions/riscv/sltu.rs +++ b/ceno_zkvm/src/instructions/riscv/sltu.rs @@ -21,7 +21,7 @@ pub struct ArithConfig { rs1_read: UInt, rs2_read: UInt, - #[allow(dead_code)] + #[cfg_attr(not(test), allow(dead_code))] rd_written: UInt, is_lt: IsLtConfig, diff --git a/ceno_zkvm/src/scheme/mock_prover.rs b/ceno_zkvm/src/scheme/mock_prover.rs index 6c325573a..b518e4207 100644 --- a/ceno_zkvm/src/scheme/mock_prover.rs +++ b/ceno_zkvm/src/scheme/mock_prover.rs @@ -701,10 +701,12 @@ mod tests { use multilinear_extensions::mle::{IntoMLE, IntoMLEs}; #[derive(Debug)] - #[allow(dead_code)] struct AssertZeroCircuit { + #[allow(dead_code)] pub a: WitIn, + #[allow(dead_code)] pub b: WitIn, + #[allow(dead_code)] pub c: WitIn, } @@ -832,7 +834,6 @@ mod tests { assert_eq!(err[0].inst_id(), 0); } - #[allow(dead_code)] #[derive(Debug)] struct AssertLtCircuit { pub a: WitIn, diff --git a/ceno_zkvm/src/scheme/utils.rs b/ceno_zkvm/src/scheme/utils.rs index e09e70574..fc4b7a444 100644 --- a/ceno_zkvm/src/scheme/utils.rs +++ b/ceno_zkvm/src/scheme/utils.rs @@ -352,7 +352,7 @@ pub(crate) fn wit_infer_by_expr<'a, E: ExtensionField, const N: usize>( ) } -#[allow(dead_code)] +#[cfg(test)] pub(crate) fn eval_by_expr( witnesses: &[E], challenges: &[E], @@ -361,7 +361,7 @@ pub(crate) fn eval_by_expr( eval_by_expr_with_fixed(&[], witnesses, challenges, expr) } -#[allow(dead_code)] +#[cfg(test)] pub(crate) fn eval_by_expr_with_fixed( fixed: &[E], witnesses: &[E], diff --git a/ceno_zkvm/src/uint.rs b/ceno_zkvm/src/uint.rs index fef0c80bc..24786064c 100644 --- a/ceno_zkvm/src/uint.rs +++ b/ceno_zkvm/src/uint.rs @@ -631,7 +631,6 @@ impl ValueMul { } pub struct Value<'a, T: Into + From + Copy + Default> { - #[allow(dead_code)] val: T, pub limbs: Cow<'a, [u16]>, } diff --git a/ceno_zkvm/src/utils.rs b/ceno_zkvm/src/utils.rs index 119b13439..66c74b18d 100644 --- a/ceno_zkvm/src/utils.rs +++ b/ceno_zkvm/src/utils.rs @@ -4,13 +4,6 @@ use goldilocks::SmallField; use itertools::Itertools; use transcript::Transcript; -/// convert ext field element to u64, assume it is inside the range -#[allow(dead_code)] -pub fn ext_to_u64(x: &E) -> u64 { - let bases = x.as_bases(); - bases[0].to_canonical_u64() -} - pub fn i64_to_base(x: i64) -> F { if x >= 0 { F::from(x as u64) @@ -19,20 +12,6 @@ pub fn i64_to_base(x: i64) -> F { } } -/// This is helper function to convert witness of u8 limb into u16 limb -/// TODO: need a better way to keep consistency of LIMB_BITS -#[allow(dead_code)] -pub fn limb_u8_to_u16(input: &[u8]) -> Vec { - input - .chunks(2) - .map(|chunk| { - let low = chunk[0] as u16; - let high = if chunk.len() > 1 { chunk[1] as u16 } else { 0 }; - high * 256 + low - }) - .collect() -} - pub fn split_to_u8>(value: u32) -> Vec { (0..(u32::BITS / 8)) .scan(value, |acc, _| { @@ -71,15 +50,6 @@ pub(crate) fn add_one_to_big_num(limb_modulo: F, limbs: &[F]) -> Vec(x: i64) -> E::BaseField { - if x >= 0 { - E::BaseField::from(x as u64) - } else { - -E::BaseField::from((-x) as u64) - } -} - /// derive challenge from transcript and return all pows result pub fn get_challenge_pows( size: usize, diff --git a/ceno_zkvm/src/witness.rs b/ceno_zkvm/src/witness.rs index bdffa2ec6..41306a8ed 100644 --- a/ceno_zkvm/src/witness.rs +++ b/ceno_zkvm/src/witness.rs @@ -133,7 +133,6 @@ pub struct LkMultiplicity { multiplicity: Arc; mem::variant_count::()]>>>, } -#[allow(dead_code)] impl LkMultiplicity { /// assert within range #[inline(always)] diff --git a/gkr-graph/src/structs.rs b/gkr-graph/src/structs.rs index 00bb4bfb3..4e206ee2a 100644 --- a/gkr-graph/src/structs.rs +++ b/gkr-graph/src/structs.rs @@ -45,7 +45,7 @@ pub enum PredType { #[derive(Clone, Debug)] pub struct CircuitNode { pub(crate) id: usize, - // TODO(Matthias): See whether we can remove this field. + // Note: only for debug output. #[allow(dead_code)] pub(crate) label: &'static str, pub(crate) circuit: Arc>, diff --git a/gkr/src/circuit.rs b/gkr/src/circuit.rs index 5e8c1ec93..d5459f328 100644 --- a/gkr/src/circuit.rs +++ b/gkr/src/circuit.rs @@ -42,14 +42,6 @@ where in_eq_vec: &[E], challenges: &HashMap>, ) -> E; - // TODO(Matthias, by 2024-11-01): review whether we need this function after all. - #[allow(dead_code)] - fn fix_out_variables( - &self, - in_size: usize, - out_eq_vec: &[E], - challenges: &HashMap>, - ) -> Vec; } impl EvaluateGate1In for &[Gate1In>] @@ -68,18 +60,6 @@ where * gate.scalar.eval(challenges) }) } - fn fix_out_variables( - &self, - in_size: usize, - out_eq_vec: &[E], - challenges: &HashMap>, - ) -> Vec { - let mut ans = vec![E::ZERO; in_size]; - for gate in self.iter() { - ans[gate.idx_in[0]] += out_eq_vec[gate.idx_out] * gate.scalar.eval(challenges); - } - ans - } } pub trait EvaluateGate2In diff --git a/multilinear_extensions/src/virtual_poly.rs b/multilinear_extensions/src/virtual_poly.rs index a5468ad90..ed29ef4e6 100644 --- a/multilinear_extensions/src/virtual_poly.rs +++ b/multilinear_extensions/src/virtual_poly.rs @@ -8,7 +8,7 @@ use ark_std::{end_timer, iterable::Iterable, rand::Rng, start_timer}; use ff::{Field, PrimeField}; use ff_ext::ExtensionField; use rayon::{ - iter::{IntoParallelIterator, IntoParallelRefIterator}, + iter::IntoParallelIterator, prelude::{IndexedParallelIterator, ParallelIterator}, slice::ParallelSliceMut, }; @@ -479,37 +479,6 @@ pub fn build_eq_x_r_vec(r: &[E]) -> Vec { } } -/// A helper function to build eq(x, r) via dynamic programing tricks. -/// This function takes 2^num_var iterations, and per iteration with 1 multiplication. -#[allow(dead_code)] -fn build_eq_x_r_helper(r: &[E], buf: &mut [Vec; 2]) { - buf[0][0] = E::ONE; - if r.is_empty() { - buf[0].resize(1, E::ZERO); - return; - } - for (i, r) in r.iter().rev().enumerate() { - let [current, next] = buf; - let (cur_size, next_size) = (1 << i, 1 << (i + 1)); - // suppose at the previous step we processed buf [0..size] - // for the current step we are populating new buf[0..2*size] - // for j travese 0..size - // buf[2*j + 1] = r * buf[j] - // buf[2*j] = (1 - r) * buf[j] - current[0..cur_size] - .par_iter() - .zip_eq(next[0..next_size].par_chunks_mut(2)) - .with_min_len(64) - .for_each(|(prev_val, next_vals)| { - assert!(next_vals.len() == 2); - let tmp = *r * prev_val; - next_vals[1] = tmp; - next_vals[0] = *prev_val - tmp; - }); - buf.swap(0, 1); // swap rolling buffer - } -} - #[cfg(test)] mod tests { use crate::virtual_poly::{build_eq_x_r_vec, build_eq_x_r_vec_sequential}; diff --git a/singer/src/scheme.rs b/singer/src/scheme.rs index d3b5e847d..6c5448e2e 100644 --- a/singer/src/scheme.rs +++ b/singer/src/scheme.rs @@ -1,30 +1,15 @@ use ff_ext::ExtensionField; // TODO: to be changed to a real PCS scheme. -type BatchedPCSProof = Vec>; -type Commitment = Vec; pub mod prover; pub mod verifier; -pub struct CommitPhaseProof { - // TODO(Matthias): Check whether we need this field. - #[allow(dead_code)] - commitments: Vec>, -} - pub type GKRGraphProof = gkr_graph::structs::IOPProof; pub type GKRGraphProverState = gkr_graph::structs::IOPProverState; pub type GKRGraphVerifierState = gkr_graph::structs::IOPVerifierState; -pub struct OpenPhaseProof { - // TODO(Matthias): Check whether we need this field. - #[allow(dead_code)] - pcs_proof: BatchedPCSProof, -} - pub struct SingerProof { - // commitment_phase_proof: CommitPhaseProof, + // TODO: restore and implement `commitment_phase_proof` and `open_phase_proof` gkr_phase_proof: GKRGraphProof, - // open_phase_proof: OpenPhaseProof, } diff --git a/singer/src/utils.rs b/singer/src/utils.rs index 02df9a112..c9cca791c 100644 --- a/singer/src/utils.rs +++ b/singer/src/utils.rs @@ -3,16 +3,6 @@ use ff_ext::ExtensionField; use itertools::izip; use simple_frontend::structs::{CellId, CircuitBuilder}; -// TODO(Matthias): Check whether we need this function. -#[allow(dead_code)] -pub(crate) fn i64_to_base_field(x: i64) -> E::BaseField { - if x >= 0 { - E::BaseField::from(x as u64) - } else { - -E::BaseField::from((-x) as u64) - } -} - pub(crate) fn add_assign_each_cell( circuit_builder: &mut CircuitBuilder, dest: &[CellId], diff --git a/sumcheck/src/structs.rs b/sumcheck/src/structs.rs index 2397a9cb8..a6089722a 100644 --- a/sumcheck/src/structs.rs +++ b/sumcheck/src/structs.rs @@ -14,7 +14,6 @@ pub struct IOPProof { pub proofs: Vec>, } impl IOPProof { - #[allow(dead_code)] pub fn extract_sum(&self) -> E { self.proofs[0].evaluations[0] + self.proofs[0].evaluations[1] } From d89ddc204cee6b3ff05ba4c977a7f2918646867a Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Fri, 25 Oct 2024 15:10:19 +0800 Subject: [PATCH 4/5] Simpler --- ceno_zkvm/src/instructions/riscv/memory/store.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/ceno_zkvm/src/instructions/riscv/memory/store.rs b/ceno_zkvm/src/instructions/riscv/memory/store.rs index 898d4df86..ddf76d0fd 100644 --- a/ceno_zkvm/src/instructions/riscv/memory/store.rs +++ b/ceno_zkvm/src/instructions/riscv/memory/store.rs @@ -38,7 +38,7 @@ impl RIVInstruction for SWOp { const INST_KIND: InsnKind = InsnKind::SW; } -#[cfg_attr(not(test), allow(dead_code))] +#[cfg(test)] pub type SwInstruction = StoreInstruction; pub struct SHOp; @@ -47,7 +47,7 @@ impl RIVInstruction for SHOp { const INST_KIND: InsnKind = InsnKind::SH; } -#[cfg_attr(not(test), allow(dead_code))] +#[cfg(test)] pub type ShInstruction = StoreInstruction; pub struct SBOp; @@ -56,7 +56,7 @@ impl RIVInstruction for SBOp { const INST_KIND: InsnKind = InsnKind::SB; } -#[cfg_attr(not(test), allow(dead_code))] +#[cfg(test)] pub type SbInstruction = StoreInstruction; impl Instruction From 5b75bdb3bfe596d166a76fb6bbdf65a982ca788a Mon Sep 17 00:00:00 2001 From: Matthias Goergens Date: Fri, 25 Oct 2024 15:11:22 +0800 Subject: [PATCH 5/5] Simpler --- ceno_zkvm/src/instructions/riscv/shift.rs | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/ceno_zkvm/src/instructions/riscv/shift.rs b/ceno_zkvm/src/instructions/riscv/shift.rs index f97f23103..41f2d5b20 100644 --- a/ceno_zkvm/src/instructions/riscv/shift.rs +++ b/ceno_zkvm/src/instructions/riscv/shift.rs @@ -31,14 +31,16 @@ pub struct ShiftConfig { pub struct ShiftLogicalInstruction(PhantomData<(E, I)>); -#[cfg_attr(not(test), allow(dead_code))] +#[cfg(test)] struct SllOp; +#[cfg(test)] impl RIVInstruction for SllOp { const INST_KIND: InsnKind = InsnKind::SLL; } -#[cfg_attr(not(test), allow(dead_code))] +#[cfg(test)] struct SrlOp; +#[cfg(test)] impl RIVInstruction for SrlOp { const INST_KIND: InsnKind = InsnKind::SRL; }