diff --git a/ceno_emul/src/rv32im.rs b/ceno_emul/src/rv32im.rs
index e1f1f2946..e78635584 100644
--- a/ceno_emul/src/rv32im.rs
+++ b/ceno_emul/src/rv32im.rs
@@ -226,8 +226,9 @@ impl DecodedInstruction {
         self.opcode
     }
 
-    /// Get the register destination, or RD_NULL if the instruction does not write to a register or writes to x0.
-    pub fn rd_or_null(&self) -> u32 {
+    /// The internal register destination. It is either the regular rd, or an internal RD_NULL if
+    /// the instruction does not write to a register or writes to x0.
+    pub fn rd_internal(&self) -> u32 {
         match self.codes().format {
             R | I | U | J if self.rd != 0 => self.rd,
             _ => Self::RD_NULL,
@@ -690,7 +691,7 @@ impl Emulator {
         if !new_pc.is_aligned() {
             return ctx.trap(TrapCause::InstructionAddressMisaligned);
         }
-        ctx.store_register(decoded.rd_or_null() as usize, out)?;
+        ctx.store_register(decoded.rd_internal() as usize, out)?;
         ctx.set_pc(new_pc);
         Ok(true)
     }
@@ -777,7 +778,7 @@ impl Emulator {
             }
             _ => unreachable!(),
         };
-        ctx.store_register(decoded.rd_or_null() as usize, out)?;
+        ctx.store_register(decoded.rd_internal() as usize, out)?;
         ctx.set_pc(ctx.get_pc() + WORD_SIZE);
         Ok(true)
     }
diff --git a/ceno_emul/src/tracer.rs b/ceno_emul/src/tracer.rs
index c26538460..d17e410a5 100644
--- a/ceno_emul/src/tracer.rs
+++ b/ceno_emul/src/tracer.rs
@@ -215,7 +215,7 @@ impl StepRecord {
             }),
             rd: rd.map(|rd| WriteOp {
                 addr: CENO_PLATFORM
-                    .register_vma(insn.rd_or_null() as RegIdx)
+                    .register_vma(insn.rd_internal() as RegIdx)
                     .into(),
                 value: rd,
                 previous_cycle,
diff --git a/ceno_zkvm/src/instructions/riscv/insn_base.rs b/ceno_zkvm/src/instructions/riscv/insn_base.rs
index 42d1b9cbd..64ac91b12 100644
--- a/ceno_zkvm/src/instructions/riscv/insn_base.rs
+++ b/ceno_zkvm/src/instructions/riscv/insn_base.rs
@@ -223,7 +223,7 @@ impl<E: ExtensionField> WriteRD<E> {
         lk_multiplicity: &mut LkMultiplicity,
         step: &StepRecord,
     ) -> Result<(), ZKVMError> {
-        set_val!(instance, self.id, step.insn().rd_or_null() as u64);
+        set_val!(instance, self.id, step.insn().rd_internal() as u64);
         set_val!(instance, self.prev_ts, step.rd().unwrap().previous_cycle);
 
         // Register state
diff --git a/ceno_zkvm/src/tables/program.rs b/ceno_zkvm/src/tables/program.rs
index f0b2f5bbf..60f2e1e91 100644
--- a/ceno_zkvm/src/tables/program.rs
+++ b/ceno_zkvm/src/tables/program.rs
@@ -87,7 +87,7 @@ impl InsnRecord<u32> {
         InsnRecord([
             pc,
             insn.opcode(),
-            insn.rd_or_null(),
+            insn.rd_internal(),
             insn.funct3_or_zero(),
             insn.rs1_or_zero(),
             insn.rs2_or_zero(),