From 948b16361b8dcc13417edfbf26801465af5721a5 Mon Sep 17 00:00:00 2001
From: KimiWu <leonhartwu@gmail.com>
Date: Wed, 16 Oct 2024 14:09:49 +0800
Subject: [PATCH] apply to r instruction

---
 ceno_emul/src/tracer.rs                       | 23 +------
 ceno_zkvm/src/instructions/riscv/arith.rs     | 60 ++++++++++++-------
 ceno_zkvm/src/instructions/riscv/divu.rs      | 11 ++--
 .../src/instructions/riscv/logic/test.rs      | 28 +++++----
 ceno_zkvm/src/instructions/riscv/mulh.rs      | 12 ++--
 ceno_zkvm/src/instructions/riscv/shift.rs     | 25 +++++---
 ceno_zkvm/src/instructions/riscv/sltu.rs      | 13 ++--
 ceno_zkvm/src/scheme/mock_prover.rs           |  2 +
 8 files changed, 92 insertions(+), 82 deletions(-)

diff --git a/ceno_emul/src/tracer.rs b/ceno_emul/src/tracer.rs
index ee5c6f3f9..1350479c6 100644
--- a/ceno_emul/src/tracer.rs
+++ b/ceno_emul/src/tracer.rs
@@ -3,7 +3,7 @@ use std::{collections::HashMap, fmt, mem};
 use crate::{
     addr::{ByteAddr, Cycle, RegIdx, Word, WordAddr},
     rv32im::DecodedInstruction,
-    InsnKind, CENO_PLATFORM, PC_STEP_SIZE,
+    CENO_PLATFORM, PC_STEP_SIZE,
 };
 
 /// An instruction and its context in an execution trace. That is concrete values of registers and memory.
@@ -54,27 +54,6 @@ pub type WriteOp = MemOp<Change<Word>>;
 
 impl StepRecord {
     pub fn new_r_instruction(
-        cycle: Cycle,
-        pc: ByteAddr,
-        insn_code: Word,
-        rs1_read: Word,
-        rs2_read: Word,
-        rd: Change<Word>,
-        prev_cycle: Cycle,
-    ) -> StepRecord {
-        let pc = Change::new(pc, pc + PC_STEP_SIZE);
-        StepRecord::new_insn(
-            cycle,
-            pc,
-            insn_code,
-            Some(rs1_read),
-            Some(rs2_read),
-            Some(rd),
-            prev_cycle,
-        )
-    }
-
-    pub fn new_r_instruction2(
         cycle: Cycle,
         pc: ByteAddr,
         insn_code: u32,
diff --git a/ceno_zkvm/src/instructions/riscv/arith.rs b/ceno_zkvm/src/instructions/riscv/arith.rs
index b5be382e7..1ab507dd0 100644
--- a/ceno_zkvm/src/instructions/riscv/arith.rs
+++ b/ceno_zkvm/src/instructions/riscv/arith.rs
@@ -171,7 +171,7 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for ArithInstruction<E
 
 #[cfg(test)]
 mod test {
-    use ceno_emul::{Change, StepRecord};
+    use ceno_emul::{Change, EncodedInstruction, StepRecord};
     use goldilocks::GoldilocksExt2;
     use itertools::Itertools;
     use multilinear_extensions::mle::IntoMLEs;
@@ -180,7 +180,7 @@ mod test {
     use crate::{
         circuit_builder::{CircuitBuilder, ConstraintSystem},
         instructions::Instruction,
-        scheme::mock_prover::{MockProver, MOCK_PC_ADD, MOCK_PC_MUL, MOCK_PC_SUB, MOCK_PROGRAM},
+        scheme::mock_prover::{MockProver, MOCK_PC_START},
     };
 
     #[test]
@@ -198,13 +198,14 @@ mod test {
             .unwrap()
             .unwrap();
 
+        let insn_code = EncodedInstruction::encode(InsnKind::ADD, 2, 3, 4, 0);
         let (raw_witin, _) = AddInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_ADD,
-                MOCK_PROGRAM[0],
+                MOCK_PC_START,
+                insn_code,
                 11,
                 0xfffffffe,
                 Change::new(0, 11_u32.wrapping_add(0xfffffffe)),
@@ -224,7 +225,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -232,6 +233,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
@@ -251,13 +253,14 @@ mod test {
             .unwrap()
             .unwrap();
 
+        let insn_code = EncodedInstruction::encode(InsnKind::ADD, 2, 3, 4, 0);
         let (raw_witin, _) = AddInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_ADD,
-                MOCK_PROGRAM[0],
+                MOCK_PC_START,
+                insn_code,
                 u32::MAX - 1,
                 u32::MAX - 1,
                 Change::new(0, (u32::MAX - 1).wrapping_add(u32::MAX - 1)),
@@ -277,7 +280,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -285,6 +288,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
@@ -304,13 +308,14 @@ mod test {
             .unwrap()
             .unwrap();
 
+        let insn_code = EncodedInstruction::encode(InsnKind::SUB, 2, 3, 4, 0);
         let (raw_witin, _) = SubInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_SUB,
-                MOCK_PROGRAM[1],
+                MOCK_PC_START,
+                insn_code,
                 11,
                 2,
                 Change::new(0, 11_u32.wrapping_sub(2)),
@@ -330,7 +335,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -338,6 +343,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
@@ -357,13 +363,14 @@ mod test {
             .unwrap()
             .unwrap();
 
+        let insn_code = EncodedInstruction::encode(InsnKind::SUB, 2, 3, 4, 0);
         let (raw_witin, _) = SubInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_SUB,
-                MOCK_PROGRAM[1],
+                MOCK_PC_START,
+                insn_code,
                 3,
                 11,
                 Change::new(0, 3_u32.wrapping_sub(11)),
@@ -383,7 +390,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -391,6 +398,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
@@ -405,13 +413,14 @@ mod test {
             .unwrap();
 
         // values assignment
+        let insn_code = EncodedInstruction::encode(InsnKind::MUL, 2, 3, 4, 0);
         let (raw_witin, _) = MulInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_MUL,
-                MOCK_PROGRAM[2],
+                MOCK_PC_START,
+                insn_code,
                 11,
                 2,
                 Change::new(0, 22),
@@ -428,7 +437,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -436,6 +445,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
@@ -450,13 +460,14 @@ mod test {
             .unwrap();
 
         // values assignment
+        let insn_code = EncodedInstruction::encode(InsnKind::MUL, 2, 3, 4, 0);
         let (raw_witin, _) = MulInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_MUL,
-                MOCK_PROGRAM[2],
+                MOCK_PC_START,
+                insn_code,
                 u32::MAX / 2 + 1,
                 2,
                 Change::new(0, 0),
@@ -472,7 +483,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -480,6 +491,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
@@ -499,13 +511,14 @@ mod test {
         let c_limb = ret.limbs;
 
         // values assignment
+        let insn_code = EncodedInstruction::encode(InsnKind::MUL, 2, 3, 4, 0);
         let (raw_witin, _) = MulInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_MUL,
-                MOCK_PROGRAM[2],
+                MOCK_PC_START,
+                insn_code,
                 a.as_u64() as u32,
                 b.as_u64() as u32,
                 Change::new(
@@ -524,7 +537,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -532,6 +545,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
diff --git a/ceno_zkvm/src/instructions/riscv/divu.rs b/ceno_zkvm/src/instructions/riscv/divu.rs
index c29795608..a288fdf82 100644
--- a/ceno_zkvm/src/instructions/riscv/divu.rs
+++ b/ceno_zkvm/src/instructions/riscv/divu.rs
@@ -156,10 +156,7 @@ mod test {
 
     mod divu {
 
-        use ceno_emul::{
-            ByteAddr, Change, DecodedInstruction, EncodedInstruction, InsnFormat, InsnKind,
-            StepRecord, Word, CENO_PLATFORM,
-        };
+        use ceno_emul::{Change, EncodedInstruction, InsnKind, StepRecord, Word};
         use goldilocks::GoldilocksExt2;
         use itertools::Itertools;
         use multilinear_extensions::mle::IntoMLEs;
@@ -171,7 +168,7 @@ mod test {
                 riscv::{constants::UInt, divu::DivUInstruction},
                 Instruction,
             },
-            scheme::mock_prover::MockProver,
+            scheme::mock_prover::{MockProver, MOCK_PC_START},
             Value,
         };
 
@@ -197,9 +194,9 @@ mod test {
             let (raw_witin, _) = DivUInstruction::assign_instances(
                 &config,
                 cb.cs.num_witin as usize,
-                vec![StepRecord::new_r_instruction2(
+                vec![StepRecord::new_r_instruction(
                     3,
-                    ByteAddr(CENO_PLATFORM.pc_start()),
+                    MOCK_PC_START,
                     insn_code,
                     dividend,
                     divisor,
diff --git a/ceno_zkvm/src/instructions/riscv/logic/test.rs b/ceno_zkvm/src/instructions/riscv/logic/test.rs
index 8eb6282eb..7c9edd71c 100644
--- a/ceno_zkvm/src/instructions/riscv/logic/test.rs
+++ b/ceno_zkvm/src/instructions/riscv/logic/test.rs
@@ -1,4 +1,4 @@
-use ceno_emul::{Change, StepRecord, Word};
+use ceno_emul::{Change, EncodedInstruction, StepRecord, Word};
 use goldilocks::GoldilocksExt2;
 use itertools::Itertools;
 use multilinear_extensions::mle::IntoMLEs;
@@ -6,7 +6,7 @@ use multilinear_extensions::mle::IntoMLEs;
 use crate::{
     circuit_builder::{CircuitBuilder, ConstraintSystem},
     instructions::{riscv::constants::UInt8, Instruction},
-    scheme::mock_prover::{MockProver, MOCK_PC_AND, MOCK_PC_OR, MOCK_PC_XOR, MOCK_PROGRAM},
+    scheme::mock_prover::{MockProver, MOCK_PC_START},
     utils::split_to_u8,
     ROMType,
 };
@@ -33,13 +33,14 @@ fn test_opcode_and() {
         .unwrap()
         .unwrap();
 
+    let insn_code = EncodedInstruction::encode(InsnKind::AND, 2, 3, 4, 0);
     let (raw_witin, lkm) = AndInstruction::assign_instances(
         &config,
         cb.cs.num_witin as usize,
         vec![StepRecord::new_r_instruction(
             3,
-            MOCK_PC_AND,
-            MOCK_PROGRAM[3],
+            MOCK_PC_START,
+            insn_code,
             A,
             B,
             Change::new(0, A & B),
@@ -58,7 +59,7 @@ fn test_opcode_and() {
         .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
         .unwrap();
 
-    MockProver::assert_satisfied(
+    MockProver::assert_satisfied_with_program(
         &mut cb,
         &raw_witin
             .de_interleaving()
@@ -66,6 +67,7 @@ fn test_opcode_and() {
             .into_iter()
             .map(|v| v.into())
             .collect_vec(),
+        &[insn_code],
         None,
     );
 }
@@ -85,13 +87,14 @@ fn test_opcode_or() {
         .unwrap()
         .unwrap();
 
+    let insn_code = EncodedInstruction::encode(InsnKind::OR, 2, 3, 4, 0);
     let (raw_witin, lkm) = OrInstruction::assign_instances(
         &config,
         cb.cs.num_witin as usize,
         vec![StepRecord::new_r_instruction(
             3,
-            MOCK_PC_OR,
-            MOCK_PROGRAM[4],
+            MOCK_PC_START,
+            insn_code,
             A,
             B,
             Change::new(0, A | B),
@@ -110,7 +113,7 @@ fn test_opcode_or() {
         .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
         .unwrap();
 
-    MockProver::assert_satisfied(
+    MockProver::assert_satisfied_with_program(
         &mut cb,
         &raw_witin
             .de_interleaving()
@@ -118,6 +121,7 @@ fn test_opcode_or() {
             .into_iter()
             .map(|v| v.into())
             .collect_vec(),
+        &[insn_code],
         None,
     );
 }
@@ -137,13 +141,14 @@ fn test_opcode_xor() {
         .unwrap()
         .unwrap();
 
+    let insn_code = EncodedInstruction::encode(InsnKind::XOR, 2, 3, 4, 0);
     let (raw_witin, lkm) = XorInstruction::assign_instances(
         &config,
         cb.cs.num_witin as usize,
         vec![StepRecord::new_r_instruction(
             3,
-            MOCK_PC_XOR,
-            MOCK_PROGRAM[5],
+            MOCK_PC_START,
+            insn_code,
             A,
             B,
             Change::new(0, A ^ B),
@@ -162,7 +167,7 @@ fn test_opcode_xor() {
         .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
         .unwrap();
 
-    MockProver::assert_satisfied(
+    MockProver::assert_satisfied_with_program(
         &mut cb,
         &raw_witin
             .de_interleaving()
@@ -170,6 +175,7 @@ fn test_opcode_xor() {
             .into_iter()
             .map(|v| v.into())
             .collect_vec(),
+        &[insn_code],
         None,
     );
 }
diff --git a/ceno_zkvm/src/instructions/riscv/mulh.rs b/ceno_zkvm/src/instructions/riscv/mulh.rs
index e583a7bcd..e8cafc9eb 100644
--- a/ceno_zkvm/src/instructions/riscv/mulh.rs
+++ b/ceno_zkvm/src/instructions/riscv/mulh.rs
@@ -117,7 +117,7 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for MulhInstruction<E,
 
 #[cfg(test)]
 mod test {
-    use ceno_emul::{Change, StepRecord};
+    use ceno_emul::{Change, EncodedInstruction, StepRecord};
     use goldilocks::GoldilocksExt2;
     use itertools::Itertools;
     use multilinear_extensions::mle::IntoMLEs;
@@ -127,7 +127,7 @@ mod test {
         chip_handler::test::DebugIndex,
         circuit_builder::{CircuitBuilder, ConstraintSystem},
         instructions::Instruction,
-        scheme::mock_prover::{MockProver, MOCK_PC_MULHU, MOCK_PROGRAM},
+        scheme::mock_prover::{MockProver, MOCK_PC_START},
     };
 
     #[test]
@@ -150,13 +150,14 @@ mod test {
         let value_mul = a.mul_hi(&b, &mut LkMultiplicity::default(), true);
 
         // values assignment
+        let insn_code = EncodedInstruction::encode(InsnKind::MULHU, 2, 3, 4, 0);
         let (raw_witin, _) = MulhuInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_MULHU,
-                MOCK_PROGRAM[18],
+                MOCK_PC_START,
+                insn_code,
                 a.as_u64() as u32,
                 b.as_u64() as u32,
                 Change::new(0, value_mul.as_hi_value::<u32>().as_u32()),
@@ -175,7 +176,7 @@ mod test {
         )
         .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &cb,
             &raw_witin
                 .de_interleaving()
@@ -183,6 +184,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
diff --git a/ceno_zkvm/src/instructions/riscv/shift.rs b/ceno_zkvm/src/instructions/riscv/shift.rs
index 3b9692411..488159e49 100644
--- a/ceno_zkvm/src/instructions/riscv/shift.rs
+++ b/ceno_zkvm/src/instructions/riscv/shift.rs
@@ -183,7 +183,7 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for ShiftLogicalInstru
 
 #[cfg(test)]
 mod tests {
-    use ceno_emul::{Change, InsnKind, StepRecord};
+    use ceno_emul::{Change, EncodedInstruction, InsnKind, StepRecord};
     use goldilocks::GoldilocksExt2;
     use itertools::Itertools;
     use multilinear_extensions::mle::IntoMLEs;
@@ -194,7 +194,7 @@ mod tests {
             riscv::{constants::UInt, RIVInstruction},
             Instruction,
         },
-        scheme::mock_prover::{MockProver, MOCK_PC_SLL, MOCK_PC_SRL, MOCK_PROGRAM},
+        scheme::mock_prover::{MockProver, MOCK_PC_START},
         Value,
     };
 
@@ -232,9 +232,17 @@ mod tests {
         let mut cb = CircuitBuilder::new(&mut cs);
 
         let shift = rs2_read & 0b11111;
-        let (prefix, mock_pc, mock_program_op, rd_written) = match I::INST_KIND {
-            InsnKind::SLL => ("SLL", MOCK_PC_SLL, MOCK_PROGRAM[19], rs1_read << shift),
-            InsnKind::SRL => ("SRL", MOCK_PC_SRL, MOCK_PROGRAM[20], rs1_read >> shift),
+        let (prefix, insn_code, rd_written) = match I::INST_KIND {
+            InsnKind::SLL => (
+                "SLL",
+                EncodedInstruction::encode(InsnKind::SLL, 2, 3, 4, 0),
+                rs1_read << shift,
+            ),
+            InsnKind::SRL => (
+                "SRL",
+                EncodedInstruction::encode(InsnKind::SRL, 2, 3, 4, 0),
+                rs1_read >> shift,
+            ),
             _ => unreachable!(),
         };
 
@@ -268,8 +276,8 @@ mod tests {
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                mock_pc,
-                mock_program_op,
+                MOCK_PC_START,
+                insn_code,
                 rs1_read,
                 rs2_read,
                 Change::new(0, rd_written),
@@ -278,7 +286,7 @@ mod tests {
         )
         .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &cb,
             &raw_witin
                 .de_interleaving()
@@ -286,6 +294,7 @@ mod tests {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
diff --git a/ceno_zkvm/src/instructions/riscv/sltu.rs b/ceno_zkvm/src/instructions/riscv/sltu.rs
index 7919733c1..605ea7b63 100644
--- a/ceno_zkvm/src/instructions/riscv/sltu.rs
+++ b/ceno_zkvm/src/instructions/riscv/sltu.rs
@@ -105,7 +105,7 @@ impl<E: ExtensionField, I: RIVInstruction> Instruction<E> for ArithInstruction<E
 
 #[cfg(test)]
 mod test {
-    use ceno_emul::{Change, StepRecord, Word, CENO_PLATFORM};
+    use ceno_emul::{Change, EncodedInstruction, StepRecord, Word};
     use goldilocks::GoldilocksExt2;
     use itertools::Itertools;
     use multilinear_extensions::mle::IntoMLEs;
@@ -115,7 +115,7 @@ mod test {
     use crate::{
         circuit_builder::{CircuitBuilder, ConstraintSystem},
         instructions::Instruction,
-        scheme::mock_prover::{MockProver, MOCK_PC_SLTU, MOCK_PROGRAM},
+        scheme::mock_prover::{MockProver, MOCK_PC_START},
     };
 
     fn verify(name: &'static str, rs1: Word, rs2: Word, rd: Word) {
@@ -132,14 +132,14 @@ mod test {
             .unwrap()
             .unwrap();
 
-        let idx = (MOCK_PC_SLTU.0 - CENO_PLATFORM.pc_start()) / 4;
+        let insn_code = EncodedInstruction::encode(InsnKind::SLTU, 2, 3, 4, 0);
         let (raw_witin, _) = SltuInstruction::assign_instances(
             &config,
             cb.cs.num_witin as usize,
             vec![StepRecord::new_r_instruction(
                 3,
-                MOCK_PC_SLTU,
-                MOCK_PROGRAM[idx as usize],
+                MOCK_PC_START,
+                insn_code,
                 rs1,
                 rs2,
                 Change::new(0, rd),
@@ -156,7 +156,7 @@ mod test {
             .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written)
             .unwrap();
 
-        MockProver::assert_satisfied(
+        MockProver::assert_satisfied_with_program(
             &mut cb,
             &raw_witin
                 .de_interleaving()
@@ -164,6 +164,7 @@ mod test {
                 .into_iter()
                 .map(|v| v.into())
                 .collect_vec(),
+            &[insn_code],
             None,
         );
     }
diff --git a/ceno_zkvm/src/scheme/mock_prover.rs b/ceno_zkvm/src/scheme/mock_prover.rs
index d6b6f6a14..ff414ced1 100644
--- a/ceno_zkvm/src/scheme/mock_prover.rs
+++ b/ceno_zkvm/src/scheme/mock_prover.rs
@@ -25,6 +25,8 @@ use std::{
     sync::OnceLock,
 };
 
+pub const MOCK_PC_START: ByteAddr = ByteAddr(CENO_PLATFORM.pc_start());
+
 pub const MOCK_RS1: u32 = 2;
 pub const MOCK_RS2: u32 = 3;
 pub const MOCK_RD: u32 = 4;