diff --git a/ceno_zkvm/src/instructions/riscv/arith.rs b/ceno_zkvm/src/instructions/riscv/arith.rs index 1d0d2146a..0b0a287e6 100644 --- a/ceno_zkvm/src/instructions/riscv/arith.rs +++ b/ceno_zkvm/src/instructions/riscv/arith.rs @@ -171,8 +171,6 @@ impl Instruction for ArithInstruction Instruction for AddiInstruction { mod test { use ceno_emul::{Change, InsnKind, PC_STEP_SIZE, StepRecord, encode_rv32}; use goldilocks::GoldilocksExt2; - use itertools::Itertools; - use multilinear_extensions::mle::IntoMLEs; use crate::{ circuit_builder::{CircuitBuilder, ConstraintSystem}, @@ -124,18 +122,7 @@ mod test { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -168,17 +155,6 @@ mod test { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } } diff --git a/ceno_zkvm/src/instructions/riscv/branch/test.rs b/ceno_zkvm/src/instructions/riscv/branch/test.rs index 36746fff3..9847c66d5 100644 --- a/ceno_zkvm/src/instructions/riscv/branch/test.rs +++ b/ceno_zkvm/src/instructions/riscv/branch/test.rs @@ -1,7 +1,5 @@ use ceno_emul::{ByteAddr, Change, PC_STEP_SIZE, StepRecord, Word, encode_rv32}; use goldilocks::GoldilocksExt2; -use itertools::Itertools; -use multilinear_extensions::mle::IntoMLEs; use super::*; use crate::{ @@ -49,18 +47,7 @@ fn impl_opcode_beq(equal: bool) { ]) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -98,18 +85,7 @@ fn impl_opcode_bne(equal: bool) { ]) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -150,18 +126,7 @@ fn impl_bltu_circuit(taken: bool, a: u32, b: u32) -> Result<(), ZKVMError> { ]) .unwrap(); - MockProver::assert_satisfied( - &circuit_builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm)); Ok(()) } @@ -202,18 +167,7 @@ fn impl_bgeu_circuit(taken: bool, a: u32, b: u32) -> Result<(), ZKVMError> { ]) .unwrap(); - MockProver::assert_satisfied( - &circuit_builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm)); Ok(()) } @@ -255,18 +209,7 @@ fn impl_blt_circuit(taken: bool, a: i32, b: i32) -> Result<(), ZKVMError> { ]) .unwrap(); - MockProver::assert_satisfied( - &circuit_builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm)); Ok(()) } @@ -308,17 +251,6 @@ fn impl_bge_circuit(taken: bool, a: i32, b: i32) -> Result<(), ZKVMError> { ]) .unwrap(); - MockProver::assert_satisfied( - &circuit_builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&circuit_builder, raw_witin, &[insn_code], None, Some(lkm)); Ok(()) } diff --git a/ceno_zkvm/src/instructions/riscv/jump/test.rs b/ceno_zkvm/src/instructions/riscv/jump/test.rs index a1b17e911..887db8da3 100644 --- a/ceno_zkvm/src/instructions/riscv/jump/test.rs +++ b/ceno_zkvm/src/instructions/riscv/jump/test.rs @@ -1,7 +1,5 @@ use ceno_emul::{ByteAddr, Change, InsnKind, PC_STEP_SIZE, StepRecord, Word, encode_rv32}; use goldilocks::GoldilocksExt2; -use itertools::Itertools; -use multilinear_extensions::mle::IntoMLEs; use crate::{ circuit_builder::{CircuitBuilder, ConstraintSystem}, @@ -45,18 +43,7 @@ fn test_opcode_jal() { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -93,18 +80,7 @@ fn test_opcode_jalr() { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -137,18 +113,7 @@ fn test_opcode_lui() { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -181,16 +146,5 @@ fn test_opcode_auipc() { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } diff --git a/ceno_zkvm/src/instructions/riscv/logic/test.rs b/ceno_zkvm/src/instructions/riscv/logic/test.rs index 50d73751e..b35c12bcb 100644 --- a/ceno_zkvm/src/instructions/riscv/logic/test.rs +++ b/ceno_zkvm/src/instructions/riscv/logic/test.rs @@ -1,7 +1,5 @@ use ceno_emul::{Change, StepRecord, Word, encode_rv32}; use goldilocks::GoldilocksExt2; -use itertools::Itertools; -use multilinear_extensions::mle::IntoMLEs; use crate::{ circuit_builder::{CircuitBuilder, ConstraintSystem}, @@ -52,18 +50,7 @@ fn test_opcode_and() { .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -103,18 +90,7 @@ fn test_opcode_or() { .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] @@ -154,16 +130,5 @@ fn test_opcode_xor() { .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } diff --git a/ceno_zkvm/src/instructions/riscv/logic_imm/logic_imm_circuit.rs b/ceno_zkvm/src/instructions/riscv/logic_imm/logic_imm_circuit.rs index 8972766f5..7fb061b5c 100644 --- a/ceno_zkvm/src/instructions/riscv/logic_imm/logic_imm_circuit.rs +++ b/ceno_zkvm/src/instructions/riscv/logic_imm/logic_imm_circuit.rs @@ -126,8 +126,6 @@ impl LogicConfig { mod test { use ceno_emul::{Change, InsnKind, PC_STEP_SIZE, StepRecord, encode_rv32}; use goldilocks::GoldilocksExt2; - use itertools::Itertools; - use multilinear_extensions::mle::IntoMLEs; use crate::{ chip_handler::test::DebugIndex, @@ -205,17 +203,6 @@ mod test { cb.require_equal(|| "assert_rd_written", rd_written_expr, expected.value()) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } } diff --git a/ceno_zkvm/src/instructions/riscv/memory/test.rs b/ceno_zkvm/src/instructions/riscv/memory/test.rs index ad4ee4b3e..6243f197b 100644 --- a/ceno_zkvm/src/instructions/riscv/memory/test.rs +++ b/ceno_zkvm/src/instructions/riscv/memory/test.rs @@ -19,8 +19,6 @@ use crate::{ use ceno_emul::{ByteAddr, Change, InsnKind, ReadOp, StepRecord, Word, WriteOp, encode_rv32}; use ff_ext::ExtensionField; use goldilocks::GoldilocksExt2; -use itertools::Itertools; -use multilinear_extensions::mle::IntoMLEs; use std::hash::Hash; fn sb(prev: Word, rs2: Word, shift: u32) -> Word { @@ -121,18 +119,7 @@ fn impl_opcode_store>(imm: u32) { @@ -176,18 +163,7 @@ fn impl_opcode_load Instruction for MulhInstruction Instruction for ShiftLogicalInstru mod tests { use ceno_emul::{Change, InsnKind, StepRecord, encode_rv32}; use goldilocks::GoldilocksExt2; - use itertools::Itertools; - use multilinear_extensions::mle::IntoMLEs; use crate::{ Value, @@ -294,17 +292,6 @@ mod tests { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } } diff --git a/ceno_zkvm/src/instructions/riscv/shift_imm.rs b/ceno_zkvm/src/instructions/riscv/shift_imm.rs index d1af0871b..81688089e 100644 --- a/ceno_zkvm/src/instructions/riscv/shift_imm.rs +++ b/ceno_zkvm/src/instructions/riscv/shift_imm.rs @@ -179,8 +179,6 @@ impl Instruction for ShiftImmInstructio mod test { use ceno_emul::{Change, InsnKind, PC_STEP_SIZE, StepRecord, encode_rv32}; use goldilocks::GoldilocksExt2; - use itertools::Itertools; - use multilinear_extensions::mle::IntoMLEs; use super::{ShiftImmInstruction, SlliOp, SraiOp, SrliOp}; use crate::{ @@ -300,17 +298,6 @@ mod test { ) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } } diff --git a/ceno_zkvm/src/instructions/riscv/slt.rs b/ceno_zkvm/src/instructions/riscv/slt.rs index fb138f2aa..4576736f7 100644 --- a/ceno_zkvm/src/instructions/riscv/slt.rs +++ b/ceno_zkvm/src/instructions/riscv/slt.rs @@ -90,8 +90,6 @@ mod test { use ceno_emul::{Change, StepRecord, Word, encode_rv32}; use goldilocks::GoldilocksExt2; - use itertools::Itertools; - use multilinear_extensions::mle::IntoMLEs; use rand::Rng; use super::*; @@ -137,18 +135,7 @@ mod test { .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] diff --git a/ceno_zkvm/src/instructions/riscv/slti.rs b/ceno_zkvm/src/instructions/riscv/slti.rs index a0db3fbc0..4ba2ced3a 100644 --- a/ceno_zkvm/src/instructions/riscv/slti.rs +++ b/ceno_zkvm/src/instructions/riscv/slti.rs @@ -122,8 +122,6 @@ mod test { use ceno_emul::{Change, PC_STEP_SIZE, StepRecord, Word, encode_rv32}; use goldilocks::GoldilocksExt2; - use itertools::Itertools; - use multilinear_extensions::mle::IntoMLEs; use rand::Rng; use super::*; @@ -168,18 +166,7 @@ mod test { .require_equal(|| "assert_rd_written", &mut cb, &expected_rd_written) .unwrap(); - MockProver::assert_satisfied( - &cb, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), - &[insn_code], - None, - Some(lkm), - ); + MockProver::assert_satisfied_raw(&cb, raw_witin, &[insn_code], None, Some(lkm)); } #[test] diff --git a/ceno_zkvm/src/instructions/riscv/sltu.rs b/ceno_zkvm/src/instructions/riscv/sltu.rs index 71ffd9f09..3fe8e8ed1 100644 --- a/ceno_zkvm/src/instructions/riscv/sltu.rs +++ b/ceno_zkvm/src/instructions/riscv/sltu.rs @@ -107,8 +107,6 @@ impl Instruction for ArithInstruction, + raw_witin: RowMajorMatrix, + programs: &[u32], + challenge: Option<[E; 2]>, + lkm: Option, + ) { + let wits_in = raw_witin + .de_interleaving() + .into_mles() + .into_iter() + .map(|v| v.into()) + .collect_vec(); + Self::assert_satisfied(cb, &wits_in, programs, challenge, lkm); + } pub fn assert_satisfied( cb: &CircuitBuilder, wits_in: &[ArcMultilinearExtension<'a, E>], @@ -698,7 +713,7 @@ mod tests { }; use ff::Field; use goldilocks::{Goldilocks, GoldilocksExt2}; - use multilinear_extensions::mle::{IntoMLE, IntoMLEs}; + use multilinear_extensions::mle::IntoMLE; #[derive(Debug)] #[allow(dead_code)] @@ -905,14 +920,9 @@ mod tests { ) .unwrap(); - MockProver::assert_satisfied( + MockProver::assert_satisfied_raw( &builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), + raw_witin, &[], Some([1.into(), 1000.into()]), None, @@ -943,14 +953,9 @@ mod tests { ) .unwrap(); - MockProver::assert_satisfied( + MockProver::assert_satisfied_raw( &builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), + raw_witin, &[], Some([1.into(), 1000.into()]), None, @@ -1029,14 +1034,9 @@ mod tests { ) .unwrap(); - MockProver::assert_satisfied( + MockProver::assert_satisfied_raw( &builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), + raw_witin, &[], Some([1.into(), 1000.into()]), None, @@ -1068,14 +1068,9 @@ mod tests { ) .unwrap(); - MockProver::assert_satisfied( + MockProver::assert_satisfied_raw( &builder, - &raw_witin - .de_interleaving() - .into_mles() - .into_iter() - .map(|v| v.into()) - .collect_vec(), + raw_witin, &[], Some([1.into(), 1000.into()]), None,