Rename RelaxedSimd to TernaryOp

src/ir/mod.rs

@@ -314,6 +314,13 @@ pub enum Instr {
         value: Value,
     },
 
+    /// Ternary operations, those requiring three operands
+    TernOp {
+        /// The operation being performed
+        #[walrus(skip_visit)]
+        op: TernaryOp,
+    },
+
     /// Binary operations, those requiring two operands
     Binop {
         /// The operation being performed
@@ -605,13 +612,6 @@ pub enum Instr {
         /// The table which `func` below is indexing into
         table: TableId,
     },
-
-    /// Various relaxed SIMD instructions.
-    RelaxedSimd {
-        /// The relaxed SIMD operation being performed
-        #[walrus(skip_visit)]
-        op: RelaxedSimdOp,
-    },
 }
 
 /// Argument in `V128Shuffle` of lane indices to select
@@ -644,6 +644,21 @@ impl fmt::Display for Value {
     }
 }
 
+/// Possible ternary operations in wasm
+#[allow(missing_docs)]
+#[derive(Copy, Clone, Debug)]
+pub enum TernaryOp {
+    F32x4RelaxedMadd,
+    F32x4RelaxedNmadd,
+    F64x2RelaxedMadd,
+    F64x2RelaxedNmadd,
+    I8x16RelaxedLaneselect,
+    I16x8RelaxedLaneselect,
+    I32x4RelaxedLaneselect,
+    I64x2RelaxedLaneselect,
+    I32x4RelaxedDotI8x16I7x16AddS,
+}
+
 /// Possible binary operations in wasm
 #[allow(missing_docs)]
 #[derive(Copy, Clone, Debug)]
@@ -1240,21 +1255,6 @@ impl AtomicWidth {
     }
 }
 
-/// The different kinds of atomic rmw operations
-#[derive(Debug, Copy, Clone)]
-#[allow(missing_docs)]
-pub enum RelaxedSimdOp {
-    F32x4RelaxedMadd,
-    F32x4RelaxedNmadd,
-    F64x2RelaxedMadd,
-    F64x2RelaxedNmadd,
-    I8x16RelaxedLaneselect,
-    I16x8RelaxedLaneselect,
-    I32x4RelaxedLaneselect,
-    I64x2RelaxedLaneselect,
-    I32x4RelaxedDotI8x16I7x16AddS,
-}
-
 impl Instr {
     /// Are any instructions that follow this instruction's instruction (within
     /// the current block) unreachable?
@@ -1282,6 +1282,7 @@ impl Instr {
             | Instr::GlobalGet(..)
             | Instr::GlobalSet(..)
             | Instr::Const(..)
+            | Instr::TernOp(..)
             | Instr::Binop(..)
             | Instr::Unop(..)
             | Instr::Select(..)
@@ -1316,8 +1317,7 @@ impl Instr {
             | Instr::TableInit(..)
             | Instr::TableCopy(..)
             | Instr::ElemDrop(..)
-            | Instr::Drop(..)
-            | Instr::RelaxedSimd(..) => false,
+            | Instr::Drop(..) => false,
         }
     }
 }

src/module/functions/local_function/emit.rs

@@ -187,6 +187,22 @@ impl<'instr> Visitor<'instr> for Emit<'_> {
                 Instruction::MemoryFill(idx)
             }
 
+            TernOp(e) => {
+                use crate::ir::TernaryOp::*;
+
+                match e.op {
+                    F32x4RelaxedMadd => Instruction::F32x4RelaxedMadd,
+                    F32x4RelaxedNmadd => Instruction::F32x4RelaxedNmadd,
+                    F64x2RelaxedMadd => Instruction::F64x2RelaxedMadd,
+                    F64x2RelaxedNmadd => Instruction::F64x2RelaxedNmadd,
+                    I8x16RelaxedLaneselect => Instruction::I8x16RelaxedLaneselect,
+                    I16x8RelaxedLaneselect => Instruction::I16x8RelaxedLaneselect,
+                    I32x4RelaxedLaneselect => Instruction::I32x4RelaxedLaneselect,
+                    I64x2RelaxedLaneselect => Instruction::I64x2RelaxedLaneselect,
+                    I32x4RelaxedDotI8x16I7x16AddS => Instruction::I32x4RelaxedDotI8x16I7x16AddS,
+                }
+            }
+
             Binop(e) => {
                 use crate::ir::BinaryOp::*;
 
@@ -867,19 +883,6 @@ impl<'instr> Visitor<'instr> for Emit<'_> {
                     table_index,
                 }
             }
-            RelaxedSimd(e) => match e.op {
-                RelaxedSimdOp::F32x4RelaxedMadd => Instruction::F32x4RelaxedMadd,
-                RelaxedSimdOp::F32x4RelaxedNmadd => Instruction::F32x4RelaxedNmadd,
-                RelaxedSimdOp::F64x2RelaxedMadd => Instruction::F64x2RelaxedMadd,
-                RelaxedSimdOp::F64x2RelaxedNmadd => Instruction::F64x2RelaxedNmadd,
-                RelaxedSimdOp::I8x16RelaxedLaneselect => Instruction::I8x16RelaxedLaneselect,
-                RelaxedSimdOp::I16x8RelaxedLaneselect => Instruction::I16x8RelaxedLaneselect,
-                RelaxedSimdOp::I32x4RelaxedLaneselect => Instruction::I32x4RelaxedLaneselect,
-                RelaxedSimdOp::I64x2RelaxedLaneselect => Instruction::I64x2RelaxedLaneselect,
-                RelaxedSimdOp::I32x4RelaxedDotI8x16I7x16AddS => {
-                    Instruction::I32x4RelaxedDotI8x16I7x16AddS
-                }
-            },
         });
     }
 }

src/module/functions/local_function/mod.rs

@@ -317,6 +317,9 @@ fn append_instruction(ctx: &mut ValidationContext, inst: Operator, loc: InstrLoc
     let binop = |ctx: &mut ValidationContext, op| {
         ctx.alloc_instr(Binop { op }, loc);
     };
+    let ternop = |ctx: &mut ValidationContext, op| {
+        ctx.alloc_instr(TernOp { op }, loc);
+    };
 
     let mem_arg = |ctx: &mut ValidationContext, arg: &wasmparser::MemArg| -> (MemoryId, MemArg) {
         (
@@ -360,10 +363,6 @@ fn append_instruction(ctx: &mut ValidationContext, inst: Operator, loc: InstrLoc
         let (memory, arg) = mem_arg(ctx, &arg);
         ctx.alloc_instr(LoadSimd { memory, arg, kind }, loc);
     };
-
-    let relaxed_simd = |ctx: &mut ValidationContext, op| {
-        ctx.alloc_instr(RelaxedSimd { op }, loc);
-    };
     match inst {
         Operator::Call { function_index } => {
             let func = ctx.indices.get_func(function_index).unwrap();
@@ -1339,30 +1338,22 @@ fn append_instruction(ctx: &mut ValidationContext, inst: Operator, loc: InstrLoc
         Operator::I32x4RelaxedTruncF32x4U => unop(ctx, UnaryOp::I32x4RelaxedTruncF32x4U),
         Operator::I32x4RelaxedTruncF64x2SZero => unop(ctx, UnaryOp::I32x4RelaxedTruncF64x2SZero),
         Operator::I32x4RelaxedTruncF64x2UZero => unop(ctx, UnaryOp::I32x4RelaxedTruncF64x2UZero),
-        Operator::F32x4RelaxedMadd => relaxed_simd(ctx, RelaxedSimdOp::F32x4RelaxedMadd),
-        Operator::F32x4RelaxedNmadd => relaxed_simd(ctx, RelaxedSimdOp::F32x4RelaxedNmadd),
-        Operator::F64x2RelaxedMadd => relaxed_simd(ctx, RelaxedSimdOp::F64x2RelaxedMadd),
-        Operator::F64x2RelaxedNmadd => relaxed_simd(ctx, RelaxedSimdOp::F64x2RelaxedNmadd),
-        Operator::I8x16RelaxedLaneselect => {
-            relaxed_simd(ctx, RelaxedSimdOp::I8x16RelaxedLaneselect)
-        }
-        Operator::I16x8RelaxedLaneselect => {
-            relaxed_simd(ctx, RelaxedSimdOp::I16x8RelaxedLaneselect)
-        }
-        Operator::I32x4RelaxedLaneselect => {
-            relaxed_simd(ctx, RelaxedSimdOp::I32x4RelaxedLaneselect)
-        }
-        Operator::I64x2RelaxedLaneselect => {
-            relaxed_simd(ctx, RelaxedSimdOp::I64x2RelaxedLaneselect)
-        }
+        Operator::F32x4RelaxedMadd => ternop(ctx, TernaryOp::F32x4RelaxedMadd),
+        Operator::F32x4RelaxedNmadd => ternop(ctx, TernaryOp::F32x4RelaxedNmadd),
+        Operator::F64x2RelaxedMadd => ternop(ctx, TernaryOp::F64x2RelaxedMadd),
+        Operator::F64x2RelaxedNmadd => ternop(ctx, TernaryOp::F64x2RelaxedNmadd),
+        Operator::I8x16RelaxedLaneselect => ternop(ctx, TernaryOp::I8x16RelaxedLaneselect),
+        Operator::I16x8RelaxedLaneselect => ternop(ctx, TernaryOp::I16x8RelaxedLaneselect),
+        Operator::I32x4RelaxedLaneselect => ternop(ctx, TernaryOp::I32x4RelaxedLaneselect),
+        Operator::I64x2RelaxedLaneselect => ternop(ctx, TernaryOp::I64x2RelaxedLaneselect),
         Operator::F32x4RelaxedMin => binop(ctx, BinaryOp::F32x4RelaxedMin),
         Operator::F32x4RelaxedMax => binop(ctx, BinaryOp::F32x4RelaxedMax),
         Operator::F64x2RelaxedMin => binop(ctx, BinaryOp::F64x2RelaxedMin),
         Operator::F64x2RelaxedMax => binop(ctx, BinaryOp::F64x2RelaxedMax),
         Operator::I16x8RelaxedQ15mulrS => binop(ctx, BinaryOp::I16x8RelaxedQ15mulrS),
         Operator::I16x8RelaxedDotI8x16I7x16S => binop(ctx, BinaryOp::I16x8RelaxedDotI8x16I7x16S),
         Operator::I32x4RelaxedDotI8x16I7x16AddS => {
-            relaxed_simd(ctx, RelaxedSimdOp::I32x4RelaxedDotI8x16I7x16AddS)
+            ternop(ctx, TernaryOp::I32x4RelaxedDotI8x16I7x16AddS)
         }
 
         // List all unimplmented operators instead of have a catch-all arm.