-
Notifications
You must be signed in to change notification settings - Fork 152
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
TPIU: LAR
and FFCR
not part of ARMv7-M standard
#390
Comments
old openocd debug notes regarding
|
|
While not part of seemingly any Cortex-M standard, we better implement |
cortex-m/src/peripheral/tpiu.rs
Lines 10 to 34 in 92552c7
c.f. https://developer.arm.com/documentation/ddi0403/d/Debug-Architecture/ARMv7-M-Debug/Trace-Port-Interface-Unit/TPIU-registers-summary
Both
lar
andffcr
introduced in c6ed9ef.lar
is unused, butffcr
utilized in 720282f and refactored in fb604a7.LAR
is likely a part of the CoreSight standard, unsure aboutFFCR
at the moment. Access to there registers should be gated if backing documentation can be found, otherwise removed.I want to recall figuring
FFCR
out when I debugged openocd for an STM32 last year, but I need to verify that.The text was updated successfully, but these errors were encountered: