I think this will create confusion since each operand of an instruction can have a different EEW and EMUL. Maybe something like "the EEW and EMUL of the instruction's widest operand". It's true that whether you pick the widest or narrowest operand doesn't matter, since the EEW:EMUL ratio is the same... I'm just trying to figure out how to phrase it to minimize the number of questions we'll get.

How about "the EEW and EMUL of any vector operand"?

Hmm... does the "any vector operand" approach lead to confusion around mask operands? Suppose we have SEW=8 LMUL=1/8 and the instruction is masked. If we say that EEW:EMUL ratio is the same for all operands, that would imply the mask operand (which has EEW=1) has EMUL=1/64. That might be definitionally true, but since normally we don't talk about LMUL < 1/8, it could lead to additional confusion.

Does "the EEW and EMUL of the instruction's widest vector operand" avoid that concern without introducing any additional definitional problems?

In the case of mask logical instructions, the widest operand is a mask. What is the EEW or EMUL of a mask operand?

In this case, I think the intent is that EEW = EMUL = 1, but I can't find any text that supports that unambiguously.

For mask-logical instructions, the existing text (respect vtype) does the right thing.

I'm starting to wonder if we should leave the text as-is, instead calling out the special cases where it doesn't apply (whole-register loads/stores/moves).

I'm starting to wonder if we should leave the text as-is, instead calling out the special cases where it doesn't apply (whole-register loads/stores/moves).

It may be easier to understand, yeah.

But EMUL=1/64 for mask operands doesn't sound confusing to me. After all, EEW=1 is clearly not a supported SEW, and yet it is used in the text. It's "effectively" 1/64 sometimes.

Yeah, valid point.

When I have some spare time, I'll try writing up my alternative version, and we can decide which is easier to understand.