From f91dac1a14f50f3dd4e8dcf7d5c9591cdf154b05 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Fri, 26 Jan 2024 16:19:23 -0800 Subject: [PATCH] Fix trailing whitespace This was done automatically with `pre-commit run --all-files`. --- CONTRIBUTING.md | 2 +- LICENSE | 3 +-- src/cheri-pte-ext.adoc | 1 - src/csv/CHERI_CSR.csv | 2 +- src/csv/CHERI_ISA.csv | 2 +- src/debug-integration.adoc | 1 - src/img/mtvalreg.edn | 1 - src/img/stvalreg.edn | 1 - src/insns/atomic_exceptions.adoc | 2 +- src/insns/candperm_32bit.adoc | 1 - src/insns/cbo.clean.adoc | 1 - src/insns/cbuildcap_32bit.adoc | 1 - src/insns/cgethigh_32bit.adoc | 1 - src/insns/cgetperm_32bit.adoc | 1 - src/insns/cgettag_32bit.adoc | 1 - src/insns/cincoffset_32bit.adoc | 1 - src/insns/cj_j_16bit.adoc | 1 - src/insns/cjal_jal_16bit.adoc | 1 - src/insns/cjal_jal_common.adoc | 1 - src/insns/cjalr_jalr_16bit.adoc | 1 - src/insns/cjalr_jalr_32bit.adoc | 1 - src/insns/cjr_jr_16bit.adoc | 1 - src/insns/cmove_32bit.adoc | 1 - src/insns/condbr_16bit.adoc | 1 - src/insns/cram_32bit.adoc | 1 - src/insns/cseal_32bit.adoc | 1 - src/insns/csetaddr_32bit.adoc | 1 - src/insns/csetequalexact_32bit.adoc | 1 - src/insns/csethigh_32bit.adoc | 1 - src/insns/csetmode_32bit.adoc | 1 - src/insns/ctestsubset_32bit.adoc | 1 - src/insns/load_16bit.adoc | 2 -- src/insns/load_16bit_Zcb.adoc | 2 -- src/insns/load_16bit_fp_dp.adoc | 1 - src/insns/load_16bit_fp_sp.adoc | 1 - src/insns/load_16bit_sprel.adoc | 2 -- src/insns/load_exceptions.adoc | 2 +- src/insns/new_encoding_note.adoc | 1 - src/insns/sh4adduw_32bit.adoc | 1 - src/insns/store_16bit.adoc | 1 - src/insns/store_16bit_cap_sprel.adoc | 1 - src/insns/store_16bit_fp_dp.adoc | 1 - src/insns/store_16bit_fp_sp.adoc | 1 - src/insns/store_16bit_sprel.adoc | 1 - src/insns/wavedrom/c-cb-format-ls.adoc | 1 - src/insns/wavedrom/c-ciw.adoc | 1 - src/insns/wavedrom/c-cj-format-ls.adoc | 3 --- src/insns/wavedrom/c-cjal-format-ls.adoc | 3 --- src/insns/wavedrom/c-cjalr-format-ls.adoc | 1 - src/insns/wavedrom/c-clc-clcsp.adoc | 1 - src/insns/wavedrom/c-cr-format-ls.adoc | 1 - src/insns/wavedrom/c-cs-format-ls.adoc | 2 -- src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc | 3 --- src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc | 3 --- src/insns/wavedrom/c-sp-load-css-fp.adoc | 2 +- src/insns/wavedrom/c-sp-load-store-css.adoc | 3 --- src/insns/wavedrom/c-sp-load-store-fp.adoc | 2 +- src/insns/wavedrom/c-sp-load-store.adoc | 2 +- src/insns/wavedrom/c-sp-store-cap.adoc | 2 +- src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc | 3 --- src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc | 3 --- src/insns/wavedrom/c-sp-store-css-fp.adoc | 2 +- src/insns/wavedrom/c_mv.adoc | 2 +- src/insns/wavedrom/cincoffset.adoc | 1 - src/insns/wavedrom/ct-unconditional.adoc | 1 - src/insns/wavedrom/dret.adoc | 2 +- src/insns/wavedrom/fpload.adoc | 3 --- src/insns/wavedrom/fpstore.adoc | 1 - src/insns/wavedrom/modeswitch_16bit.adoc | 1 - src/insns/wavedrom/reg-based-ldnstr.adoc | 1 - src/insns/wavedrom/trap-return.adoc | 2 +- src/introduction.adoc | 1 - src/riscv-cheri.bib | 1 - src/riscv-integration.adoc | 1 - src/riscv-legacy-integration.adoc | 2 +- src/scripts/generate_tables.py | 2 +- src/tables.adoc | 1 - 77 files changed, 16 insertions(+), 98 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 3c79557a..1d98c72b 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -55,4 +55,4 @@ You can manually add the DCO text to your commit body or include either -s or -- Note: -Ensure that the name and email address associated with your GitHub account match the name and email address in the Signed-off-by line of your commit message. \ No newline at end of file +Ensure that the name and email address associated with your GitHub account match the name and email address in the Signed-off-by line of your commit message. diff --git a/LICENSE b/LICENSE index 53883b1c..2f244ac8 100644 --- a/LICENSE +++ b/LICENSE @@ -49,7 +49,7 @@ exhaustive, and do not form part of our licenses. such as asking that all changes be marked or described. Although not required by our licenses, you are encouraged to respect those requests where reasonable. More_considerations - for the public: + for the public: wiki.creativecommons.org/Considerations_for_licensees ======================================================================= @@ -393,4 +393,3 @@ the avoidance of doubt, this paragraph does not form part of the public licenses. Creative Commons may be contacted at creativecommons.org. - diff --git a/src/cheri-pte-ext.adoc b/src/cheri-pte-ext.adoc index b770c579..f7fdca10 100644 --- a/src/cheri-pte-ext.adoc +++ b/src/cheri-pte-ext.adoc @@ -97,4 +97,3 @@ bit is available for S-mode address translation. When CDE=0, the implementation behaves as though the CD bit were not implemented. If CD is not implemented, CDE is read-only zero. If CD is implemented although not configurable, CDE is read-only one. - diff --git a/src/csv/CHERI_CSR.csv b/src/csv/CHERI_CSR.csv index 764d7d29..5b7aec65 100644 --- a/src/csv/CHERI_CSR.csv +++ b/src/csv/CHERI_CSR.csv @@ -30,4 +30,4 @@ direct write if address didn't change","✔","","","✔","✔","Zcmt","Jump Vect "stdc","0x163","","","S","SRW, <>","<>","","","","","","✔","","S-mode","Supervisor Trap Data Capability (scratch register)","","","","","","","","","","","","","","","","","","","","","" "ddc","0x416","","","U","URW","<>","","","","","","✔","","none","User Default Data Capability","","","","","","","","","","","","","","","","","","","","","" "pcc","0xcb0","","","U","URO","<> -(address = boot address)","","","✔","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","","" \ No newline at end of file +(address = boot address)","","","✔","","","✔","✔","none","User Program Counter Capability (to allow reading in legacy mode)","","","","","","","","","","","","","","","","","","","","","" diff --git a/src/csv/CHERI_ISA.csv b/src/csv/CHERI_ISA.csv index b89637a1..9634f44f 100644 --- a/src/csv/CHERI_ISA.csv +++ b/src/csv/CHERI_ISA.csv @@ -173,4 +173,4 @@ "SH4ADD","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","","" "SH4ADD.UW","","✔","","","","✔","","Legacy","","","","","","","","","","","","","","","","OP","","","","shift and add","","","","","","","","" "CSH4ADD","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD","SH4ADD","shift and add, representability check on the result","","","","","","","","" -"CSH4ADD.UW","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD.UW","SH4ADD.UW","shift and add, representability check on the result","","","","","","","","" \ No newline at end of file +"CSH4ADD.UW","","✔","","","","","✔","Capability","","","","","","","","","","","","","","","","OP","","SH4ADD.UW","SH4ADD.UW","shift and add, representability check on the result","","","","","","","","" diff --git a/src/debug-integration.adoc b/src/debug-integration.adoc index f6623ee0..88cbffc4 100644 --- a/src/debug-integration.adoc +++ b/src/debug-integration.adoc @@ -103,4 +103,3 @@ The <> register is a CLEN-bit plus tag bit extension to .Debug scratch 1 capability register include::img/dscratch1creg.edn[] - diff --git a/src/img/mtvalreg.edn b/src/img/mtvalreg.edn index ea6b2963..575ad9b5 100644 --- a/src/img/mtvalreg.edn +++ b/src/img/mtvalreg.edn @@ -18,4 +18,3 @@ (draw-box "12" {:span 12 :borders {}}) (draw-box "4" {:span 4 :borders {}}) ---- - diff --git a/src/img/stvalreg.edn b/src/img/stvalreg.edn index 31642298..bdcad87c 100644 --- a/src/img/stvalreg.edn +++ b/src/img/stvalreg.edn @@ -18,4 +18,3 @@ (draw-box "12" {:span 12 :borders {}}) (draw-box "4" {:span 4 :borders {}}) ---- - diff --git a/src/insns/atomic_exceptions.adoc b/src/insns/atomic_exceptions.adoc index 2a3d8862..5f2fa825 100644 --- a/src/insns/atomic_exceptions.adoc +++ b/src/insns/atomic_exceptions.adoc @@ -30,4 +30,4 @@ reported in the CAUSE field of <> or <>: | Length violation | At least one byte accessed is outside the authority capability bounds |============================================================================== -:!cap_atomic: \ No newline at end of file +:!cap_atomic: diff --git a/src/insns/candperm_32bit.adoc b/src/insns/candperm_32bit.adoc index 5cc0e716..b8ba55b7 100644 --- a/src/insns/candperm_32bit.adoc +++ b/src/insns/candperm_32bit.adoc @@ -46,4 +46,3 @@ Operation:: -- TODO: Sail does not have the new encoding of the permissions field. -- - diff --git a/src/insns/cbo.clean.adoc b/src/insns/cbo.clean.adoc index 7b97acb0..91b6d93a 100644 --- a/src/insns/cbo.clean.adoc +++ b/src/insns/cbo.clean.adoc @@ -53,4 +53,3 @@ Operation:: -- TBD -- - diff --git a/src/insns/cbuildcap_32bit.adoc b/src/insns/cbuildcap_32bit.adoc index 23c3e924..64b727c8 100644 --- a/src/insns/cbuildcap_32bit.adoc +++ b/src/insns/cbuildcap_32bit.adoc @@ -45,4 +45,3 @@ Operation:: -- TODO: Original Sail looks at otype field, etc that don't exist -- - diff --git a/src/insns/cgethigh_32bit.adoc b/src/insns/cgethigh_32bit.adoc index d47de6e1..f2805de3 100644 --- a/src/insns/cgethigh_32bit.adoc +++ b/src/insns/cgethigh_32bit.adoc @@ -25,4 +25,3 @@ Operation:: TODO #this is correct but capToMemBits is redundant, as it's now XOR -- TODO -- - diff --git a/src/insns/cgetperm_32bit.adoc b/src/insns/cgetperm_32bit.adoc index cddbf7c5..dc55a9af 100644 --- a/src/insns/cgetperm_32bit.adoc +++ b/src/insns/cgetperm_32bit.adoc @@ -29,4 +29,3 @@ Operation:: -- TODO: The encoding of permissions changed. -- - diff --git a/src/insns/cgettag_32bit.adoc b/src/insns/cgettag_32bit.adoc index deafca63..4d755c49 100644 --- a/src/insns/cgettag_32bit.adoc +++ b/src/insns/cgettag_32bit.adoc @@ -23,4 +23,3 @@ Operation:: -- TODO -- - diff --git a/src/insns/cincoffset_32bit.adoc b/src/insns/cincoffset_32bit.adoc index 6ae8dadb..3b76149f 100644 --- a/src/insns/cincoffset_32bit.adoc +++ b/src/insns/cincoffset_32bit.adoc @@ -52,4 +52,3 @@ Operation (CINCOFFSETIMM):: -- TODO -- - diff --git a/src/insns/cj_j_16bit.adoc b/src/insns/cj_j_16bit.adoc index 54c740e4..3b056e4b 100644 --- a/src/insns/cj_j_16bit.adoc +++ b/src/insns/cj_j_16bit.adoc @@ -45,4 +45,3 @@ Prerequisites for C.J:: Operation (after expansion to 32-bit encodings):: See <>, <> - diff --git a/src/insns/cjal_jal_16bit.adoc b/src/insns/cjal_jal_16bit.adoc index 3fe93147..1a8daa3f 100644 --- a/src/insns/cjal_jal_16bit.adoc +++ b/src/insns/cjal_jal_16bit.adoc @@ -42,4 +42,3 @@ Prerequisites for C.JAL:: Operation (after expansion to 32-bit encodings):: See <>, <> - diff --git a/src/insns/cjal_jal_common.adoc b/src/insns/cjal_jal_common.adoc index 43ec6fe2..2260840e 100644 --- a/src/insns/cjal_jal_common.adoc +++ b/src/insns/cjal_jal_common.adoc @@ -5,4 +5,3 @@ Link the next linear <> to `cd` and seal. Jump to <>.address+offset. Legacy Mode Description:: Set the next PC and link to `rd` according to the standard <> definition. Check a minimum length instruction is in <> bounds at the target PC, take a CHERI Length Violation exception on error. - diff --git a/src/insns/cjalr_jalr_16bit.adoc b/src/insns/cjalr_jalr_16bit.adoc index 809c233c..bcfd4afa 100644 --- a/src/insns/cjalr_jalr_16bit.adoc +++ b/src/insns/cjalr_jalr_16bit.adoc @@ -42,4 +42,3 @@ Prerequisites C.JALR:: Operation (after expansion to 32-bit encodings):: See <>, <> - diff --git a/src/insns/cjalr_jalr_32bit.adoc b/src/insns/cjalr_jalr_32bit.adoc index 19624b7f..6ab8beb6 100644 --- a/src/insns/cjalr_jalr_32bit.adoc +++ b/src/insns/cjalr_jalr_32bit.adoc @@ -72,4 +72,3 @@ JALR Operation:: -- TBD -- - diff --git a/src/insns/cjr_jr_16bit.adoc b/src/insns/cjr_jr_16bit.adoc index 320ac7ca..770f196d 100644 --- a/src/insns/cjr_jr_16bit.adoc +++ b/src/insns/cjr_jr_16bit.adoc @@ -48,4 +48,3 @@ Prerequisites for C.JALR:: Operation (after expansion to 32-bit encodings):: See <>, <> - diff --git a/src/insns/cmove_32bit.adoc b/src/insns/cmove_32bit.adoc index e9efcd42..df903f19 100644 --- a/src/insns/cmove_32bit.adoc +++ b/src/insns/cmove_32bit.adoc @@ -28,4 +28,3 @@ Operation:: -- TODO -- - diff --git a/src/insns/condbr_16bit.adoc b/src/insns/condbr_16bit.adoc index 48689631..3d21337a 100644 --- a/src/insns/condbr_16bit.adoc +++ b/src/insns/condbr_16bit.adoc @@ -23,4 +23,3 @@ C or Zca Operation (after expansion to 32-bit encodings):: See <> - diff --git a/src/insns/cram_32bit.adoc b/src/insns/cram_32bit.adoc index c9ed212f..b51c881a 100644 --- a/src/insns/cram_32bit.adoc +++ b/src/insns/cram_32bit.adoc @@ -25,4 +25,3 @@ Operation:: -- TODO -- - diff --git a/src/insns/cseal_32bit.adoc b/src/insns/cseal_32bit.adoc index 1a5242a3..e0e26374 100644 --- a/src/insns/cseal_32bit.adoc +++ b/src/insns/cseal_32bit.adoc @@ -26,4 +26,3 @@ Operation:: -- TODO: The SAIL definition for CSEAL writes the OTYPE which does not exist anymore. -- - diff --git a/src/insns/csetaddr_32bit.adoc b/src/insns/csetaddr_32bit.adoc index df546a30..bbd64140 100644 --- a/src/insns/csetaddr_32bit.adoc +++ b/src/insns/csetaddr_32bit.adoc @@ -28,4 +28,3 @@ Operation:: -- TODO -- - diff --git a/src/insns/csetequalexact_32bit.adoc b/src/insns/csetequalexact_32bit.adoc index f60401bb..8e5c9bf7 100644 --- a/src/insns/csetequalexact_32bit.adoc +++ b/src/insns/csetequalexact_32bit.adoc @@ -26,4 +26,3 @@ Operation:: -- TODO -- - diff --git a/src/insns/csethigh_32bit.adoc b/src/insns/csethigh_32bit.adoc index 24f511f8..7e1756da 100644 --- a/src/insns/csethigh_32bit.adoc +++ b/src/insns/csethigh_32bit.adoc @@ -26,4 +26,3 @@ Operation:: TODO #this is correct but capToMemBits is redundant, as it's now XOR -- TODO -- - diff --git a/src/insns/csetmode_32bit.adoc b/src/insns/csetmode_32bit.adoc index a97e8649..5a6f4b87 100644 --- a/src/insns/csetmode_32bit.adoc +++ b/src/insns/csetmode_32bit.adoc @@ -30,4 +30,3 @@ Operation :: -- TODO -- - diff --git a/src/insns/ctestsubset_32bit.adoc b/src/insns/ctestsubset_32bit.adoc index d0f992f5..708ccb49 100644 --- a/src/insns/ctestsubset_32bit.adoc +++ b/src/insns/ctestsubset_32bit.adoc @@ -29,4 +29,3 @@ Operation:: -- TODO -- - diff --git a/src/insns/load_16bit.adoc b/src/insns/load_16bit.adoc index b6c6b1d8..957cf452 100644 --- a/src/insns/load_16bit.adoc +++ b/src/insns/load_16bit.adoc @@ -70,5 +70,3 @@ Prerequisites C.LW:: Operation (after expansion to 32-bit encodings):: See <>, <>, <>, <> - - diff --git a/src/insns/load_16bit_Zcb.adoc b/src/insns/load_16bit_Zcb.adoc index 0647e75b..25609a19 100644 --- a/src/insns/load_16bit_Zcb.adoc +++ b/src/insns/load_16bit_Zcb.adoc @@ -63,5 +63,3 @@ Prerequisites C.LH, C.LHU, C.LBU:: Operation (after expansion to 32-bit encodings):: See <>, <>, <>, <>, <>, <> - - diff --git a/src/insns/load_16bit_fp_dp.adoc b/src/insns/load_16bit_fp_dp.adoc index 825d20de..2ccede80 100644 --- a/src/insns/load_16bit_fp_dp.adoc +++ b/src/insns/load_16bit_fp_dp.adoc @@ -61,4 +61,3 @@ Prerequisites for C.FLD, C.FLDSP:: Operation (after expansion to 32-bit encodings):: See <> - diff --git a/src/insns/load_16bit_fp_sp.adoc b/src/insns/load_16bit_fp_sp.adoc index db2c24fa..382e0b14 100644 --- a/src/insns/load_16bit_fp_sp.adoc +++ b/src/insns/load_16bit_fp_sp.adoc @@ -31,4 +31,3 @@ Prerequisites:: Operation (after expansion to 32-bit encodings):: See <> - diff --git a/src/insns/load_16bit_sprel.adoc b/src/insns/load_16bit_sprel.adoc index 08360b3b..49b5af16 100644 --- a/src/insns/load_16bit_sprel.adoc +++ b/src/insns/load_16bit_sprel.adoc @@ -73,5 +73,3 @@ Prerequisites for C.LWSP:: Operation (after expansion to 32-bit encodings):: See <>, <>, <>, <> - - diff --git a/src/insns/load_exceptions.adoc b/src/insns/load_exceptions.adoc index 82cf64f2..d0bbda2f 100644 --- a/src/insns/load_exceptions.adoc +++ b/src/insns/load_exceptions.adoc @@ -22,4 +22,4 @@ listed below; in this case, _CHERI data fault_ is reported in the <> or |============================================================================== :!load_res: -:!has_cap_data: \ No newline at end of file +:!has_cap_data: diff --git a/src/insns/new_encoding_note.adoc b/src/insns/new_encoding_note.adoc index 83905e7d..f9320c0a 100644 --- a/src/insns/new_encoding_note.adoc +++ b/src/insns/new_encoding_note.adoc @@ -1,4 +1,3 @@ ifdef::cheri_v9_annotations[] NOTE: *CHERI v9 Note:* This page has *new* encodings. endif::[] - diff --git a/src/insns/sh4adduw_32bit.adoc b/src/insns/sh4adduw_32bit.adoc index 1ea70eca..5a4bccd6 100644 --- a/src/insns/sh4adduw_32bit.adoc +++ b/src/insns/sh4adduw_32bit.adoc @@ -53,4 +53,3 @@ Legacy Mode Operation:: -- TBD -- - diff --git a/src/insns/store_16bit.adoc b/src/insns/store_16bit.adoc index d09adc19..43c86b96 100644 --- a/src/insns/store_16bit.adoc +++ b/src/insns/store_16bit.adoc @@ -73,4 +73,3 @@ Prerequisites for C.SW:: Operation (after expansion to 32-bit encodings):: See <>, <>, <>, <> - diff --git a/src/insns/store_16bit_cap_sprel.adoc b/src/insns/store_16bit_cap_sprel.adoc index c961246a..a4f27f00 100644 --- a/src/insns/store_16bit_cap_sprel.adoc +++ b/src/insns/store_16bit_cap_sprel.adoc @@ -37,4 +37,3 @@ Prerequisites:: Operation (after expansion to 32-bit encodings):: See <> - diff --git a/src/insns/store_16bit_fp_dp.adoc b/src/insns/store_16bit_fp_dp.adoc index d9452091..21ae42aa 100644 --- a/src/insns/store_16bit_fp_dp.adoc +++ b/src/insns/store_16bit_fp_dp.adoc @@ -61,4 +61,3 @@ Prerequisites for C.FSD, C.FSDSP:: Operation (after expansion to 32-bit encodings):: See <>, <> - diff --git a/src/insns/store_16bit_fp_sp.adoc b/src/insns/store_16bit_fp_sp.adoc index 92b1abde..09a4ead1 100644 --- a/src/insns/store_16bit_fp_sp.adoc +++ b/src/insns/store_16bit_fp_sp.adoc @@ -34,4 +34,3 @@ Prerequisites for C.FSW, C.FSWSP:: Operation (after expansion to 32-bit encodings):: See <> - diff --git a/src/insns/store_16bit_sprel.adoc b/src/insns/store_16bit_sprel.adoc index 4f42d2dd..f7557ff6 100644 --- a/src/insns/store_16bit_sprel.adoc +++ b/src/insns/store_16bit_sprel.adoc @@ -73,4 +73,3 @@ Prerequisites for C.SWSP:: Operation (after expansion to 32-bit encodings):: See <>, <>, <>, <> - diff --git a/src/insns/wavedrom/c-cb-format-ls.adoc b/src/insns/wavedrom/c-cb-format-ls.adoc index 63b783e3..2b31fac8 100644 --- a/src/insns/wavedrom/c-cb-format-ls.adoc +++ b/src/insns/wavedrom/c-cb-format-ls.adoc @@ -10,4 +10,3 @@ {bits: 3, name: 'funct3',type: 8, attr: ['3','C.BEQZ', 'C.BNEZ'],}, ], config: {bits: 16}} .... - diff --git a/src/insns/wavedrom/c-ciw.adoc b/src/insns/wavedrom/c-ciw.adoc index 2aa675d1..75a2e5e9 100644 --- a/src/insns/wavedrom/c-ciw.adoc +++ b/src/insns/wavedrom/c-ciw.adoc @@ -9,4 +9,3 @@ {bits: 3, name: 'funct3',type: 5, attr: ['3','cap: C.CINCOFFSET4CSPN=000','leg: C.ADDI4SPN=000']}, ], config: {bits: 16}} .... - diff --git a/src/insns/wavedrom/c-cj-format-ls.adoc b/src/insns/wavedrom/c-cj-format-ls.adoc index 3f59bbb5..54ef3c56 100644 --- a/src/insns/wavedrom/c-cj-format-ls.adoc +++ b/src/insns/wavedrom/c-cj-format-ls.adoc @@ -6,6 +6,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3','cap: C.CJ=101','leg: C.J=101']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-cjal-format-ls.adoc b/src/insns/wavedrom/c-cjal-format-ls.adoc index f7279c8a..8c1120f2 100644 --- a/src/insns/wavedrom/c-cjal-format-ls.adoc +++ b/src/insns/wavedrom/c-cjal-format-ls.adoc @@ -6,6 +6,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3','cap rv32: C.CJAL=001','leg rv32: C.JAL=001']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-cjalr-format-ls.adoc b/src/insns/wavedrom/c-cjalr-format-ls.adoc index 01ae1acf..444e7133 100644 --- a/src/insns/wavedrom/c-cjalr-format-ls.adoc +++ b/src/insns/wavedrom/c-cjalr-format-ls.adoc @@ -9,4 +9,3 @@ {bits: 4, name: 'funct4', type: 8, attr: ['4', 'cap: C.CJALR=1001', 'leg: C.JALR=1001']}, ], config: {bits: 16}} .... - diff --git a/src/insns/wavedrom/c-clc-clcsp.adoc b/src/insns/wavedrom/c-clc-clcsp.adoc index e5878477..2f4a277f 100644 --- a/src/insns/wavedrom/c-clc-clcsp.adoc +++ b/src/insns/wavedrom/c-clc-clcsp.adoc @@ -21,4 +21,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3','cap rv64: C.CLCSP=001']}, ], config: {bits: 16}} .... - diff --git a/src/insns/wavedrom/c-cr-format-ls.adoc b/src/insns/wavedrom/c-cr-format-ls.adoc index 0df02f21..d08181ea 100644 --- a/src/insns/wavedrom/c-cr-format-ls.adoc +++ b/src/insns/wavedrom/c-cr-format-ls.adoc @@ -9,4 +9,3 @@ {bits: 4, name: 'funct4', type: 8, attr: ['4','cap: C.CJR=1000', 'leg: C.JR=1000']}, ], config: {bits: 16}} .... - diff --git a/src/insns/wavedrom/c-cs-format-ls.adoc b/src/insns/wavedrom/c-cs-format-ls.adoc index ead88c3b..3ff42b56 100644 --- a/src/insns/wavedrom/c-cs-format-ls.adoc +++ b/src/insns/wavedrom/c-cs-format-ls.adoc @@ -12,5 +12,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3', 'cap: C.CSW=110', 'leg: C.SW=110', 'cap rv64: C.CSD=111', 'leg rv64: C.SD=111']}, ], config: {bits: 16}} .... - - diff --git a/src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc b/src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc index ded26743..455337e8 100644 --- a/src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc +++ b/src/insns/wavedrom/c-sp-load-css-dp-sprel.adoc @@ -8,6 +8,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg: C.FLDSP=001', 'cap rv32: C.CFLDSP=001']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc b/src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc index 9bd5c1c4..eb16ba59 100644 --- a/src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc +++ b/src/insns/wavedrom/c-sp-load-css-fp-sprel.adoc @@ -8,6 +8,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FLWSP=011']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-sp-load-css-fp.adoc b/src/insns/wavedrom/c-sp-load-css-fp.adoc index 5350f39b..f93dd077 100644 --- a/src/insns/wavedrom/c-sp-load-css-fp.adoc +++ b/src/insns/wavedrom/c-sp-load-css-fp.adoc @@ -9,4 +9,4 @@ {bits: 3, name: 'imm', types:3, attr: ['3', 'offset[5:3]']}, {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FLW=011']}, ], config: {bits: 16}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/c-sp-load-store-css.adoc b/src/insns/wavedrom/c-sp-load-store-css.adoc index 2d1da543..d08a13c9 100644 --- a/src/insns/wavedrom/c-sp-load-store-css.adoc +++ b/src/insns/wavedrom/c-sp-load-store-css.adoc @@ -9,6 +9,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3', 'cap rv64: C.CSDSP=111', 'leg rv64: C.SDSP=111', 'cap: C.CSWSP=110', 'leg: C.SWSP=110']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-sp-load-store-fp.adoc b/src/insns/wavedrom/c-sp-load-store-fp.adoc index 518e4a79..9e3a2849 100644 --- a/src/insns/wavedrom/c-sp-load-store-fp.adoc +++ b/src/insns/wavedrom/c-sp-load-store-fp.adoc @@ -10,4 +10,4 @@ {bits: 1, name: 'imm', type: 1, attr: ['1','[5]']}, {bits: 3, name: 'funct3', type: 3, attr: ['3', 'leg rv32: C.FLWSP=011']}, ], config: {bits: 16}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/c-sp-load-store.adoc b/src/insns/wavedrom/c-sp-load-store.adoc index 0ddf2f44..e95921b3 100644 --- a/src/insns/wavedrom/c-sp-load-store.adoc +++ b/src/insns/wavedrom/c-sp-load-store.adoc @@ -11,4 +11,4 @@ {bits: 1, name: 'imm', type: 1, attr: ['1','[5]']}, {bits: 3, name: 'funct3', type: 3, attr: ['3', 'cap: C.CLWSP=010', 'leg: C.LWSP=010', 'cap rv64: C.CLDSP=011', 'leg rv64: C.LDSP=011']}, ], config: {bits: 16}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/c-sp-store-cap.adoc b/src/insns/wavedrom/c-sp-store-cap.adoc index 5e4e5ced..986cabba 100644 --- a/src/insns/wavedrom/c-sp-store-cap.adoc +++ b/src/insns/wavedrom/c-sp-store-cap.adoc @@ -18,4 +18,4 @@ {bits: 3, name: 'imm', types:3, attr: ['3', 'offset[5:3]','offset[5:4|8]']}, {bits: 3, name: 'funct3', type: 8, attr: ['3', 'cap rv32: C.CSC=111','cap rv64: C.CSC=101']}, ], config: {bits: 16}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc b/src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc index 458d5ea8..4c4de14c 100644 --- a/src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc +++ b/src/insns/wavedrom/c-sp-store-css-fp-dp-sprel.adoc @@ -9,6 +9,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3', 'int C.FSDSP=101', 'cap rv32: C.CFSDSP=101']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc b/src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc index ee42c839..e5a5adb5 100644 --- a/src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc +++ b/src/insns/wavedrom/c-sp-store-css-fp-sprel.adoc @@ -9,6 +9,3 @@ {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FSWSP=111']}, ], config: {bits: 16}} .... - - - diff --git a/src/insns/wavedrom/c-sp-store-css-fp.adoc b/src/insns/wavedrom/c-sp-store-css-fp.adoc index 0ee51f97..b3c3962e 100644 --- a/src/insns/wavedrom/c-sp-store-css-fp.adoc +++ b/src/insns/wavedrom/c-sp-store-css-fp.adoc @@ -9,4 +9,4 @@ {bits: 3, name: 'uimm', types:3, attr: ['3', 'offset[5:3]']}, {bits: 3, name: 'funct3', type: 8, attr: ['3', 'leg rv32: C.FSW=111']}, ], config: {bits: 16}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/c_mv.adoc b/src/insns/wavedrom/c_mv.adoc index 27bc94c8..9dea19cd 100644 --- a/src/insns/wavedrom/c_mv.adoc +++ b/src/insns/wavedrom/c_mv.adoc @@ -8,4 +8,4 @@ {bits: 5, name: 'rd/cd', type: 7, attr: ['5', 'dest!=0'],}, {bits: 4, name: 'funct4', type: 8, attr: ['4', 'leg: C.MV=1000', 'cap: C.CMove=1000'],}, ], config: {bits: 16}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/cincoffset.adoc b/src/insns/wavedrom/cincoffset.adoc index 6ecdf1d4..ff9c8e62 100644 --- a/src/insns/wavedrom/cincoffset.adoc +++ b/src/insns/wavedrom/cincoffset.adoc @@ -21,4 +21,3 @@ {bits: 12, name: 'imm', attr: ['12','imm'], type: 4}, ]} .... - diff --git a/src/insns/wavedrom/ct-unconditional.adoc b/src/insns/wavedrom/ct-unconditional.adoc index 06b53fcb..1a2aba73 100644 --- a/src/insns/wavedrom/ct-unconditional.adoc +++ b/src/insns/wavedrom/ct-unconditional.adoc @@ -12,4 +12,3 @@ {bits: 1, name: '[20]', attr: ['1'], type: 3}, ], config:{fontsize: 12}} .... - diff --git a/src/insns/wavedrom/dret.adoc b/src/insns/wavedrom/dret.adoc index 69a34cb5..3b524f25 100644 --- a/src/insns/wavedrom/dret.adoc +++ b/src/insns/wavedrom/dret.adoc @@ -10,4 +10,4 @@ {bits: 5, name: 'rs1', attr: ['5','0'], type: 4}, {bits: 12, name: 'funct12', attr: ['12','DRET=011110110010'], type: 8}, ], config: {bits: 32}} -.... \ No newline at end of file +.... diff --git a/src/insns/wavedrom/fpload.adoc b/src/insns/wavedrom/fpload.adoc index 557ab888..e8d91838 100644 --- a/src/insns/wavedrom/fpload.adoc +++ b/src/insns/wavedrom/fpload.adoc @@ -9,6 +9,3 @@ {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'], type: 3}, ]} .... - - - diff --git a/src/insns/wavedrom/fpstore.adoc b/src/insns/wavedrom/fpstore.adoc index 9a2f31c6..d45bbbbd 100644 --- a/src/insns/wavedrom/fpstore.adoc +++ b/src/insns/wavedrom/fpstore.adoc @@ -10,4 +10,3 @@ {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'], type: 3}, ]} .... - diff --git a/src/insns/wavedrom/modeswitch_16bit.adoc b/src/insns/wavedrom/modeswitch_16bit.adoc index 7dde7997..bc725154 100644 --- a/src/insns/wavedrom/modeswitch_16bit.adoc +++ b/src/insns/wavedrom/modeswitch_16bit.adoc @@ -11,4 +11,3 @@ { bits: 3, name: 0x4, attr: ['3', 'FUNCT3'] }, ],config:{bits:16}} .... - diff --git a/src/insns/wavedrom/reg-based-ldnstr.adoc b/src/insns/wavedrom/reg-based-ldnstr.adoc index 0216fbf3..11e4a8e8 100644 --- a/src/insns/wavedrom/reg-based-ldnstr.adoc +++ b/src/insns/wavedrom/reg-based-ldnstr.adoc @@ -11,4 +11,3 @@ {bits: 3, name: 'funct3', attr: ['3', 'cap: C.CLW=010', 'leg: C.LW=010', 'cap rv64: C.CLD=011', 'leg rv64: C.LD=011'], type: 8}, ], config: {bits: 16}} .... - diff --git a/src/insns/wavedrom/trap-return.adoc b/src/insns/wavedrom/trap-return.adoc index 04f510cb..fdbc8e23 100644 --- a/src/insns/wavedrom/trap-return.adoc +++ b/src/insns/wavedrom/trap-return.adoc @@ -10,4 +10,4 @@ {bits: 5, name: 'rs1', attr: ['5','0'],type: 4}, {bits: 12, name: 'funct12', attr: ['12','MRET=001100000010','SRET=000100000010',], type: 8}, ], config: {bits: 32}} -.... \ No newline at end of file +.... diff --git a/src/introduction.adoc b/src/introduction.adoc index 08a010b5..7eb5941f 100644 --- a/src/introduction.adoc +++ b/src/introduction.adoc @@ -201,4 +201,3 @@ maintenance in systems software like Linux (which occurs very infrequently in real-world code) more difficult to understand without additional context ** Both options could be supported by using assembler aliases - diff --git a/src/riscv-cheri.bib b/src/riscv-cheri.bib index 934c4374..33d911a1 100644 --- a/src/riscv-cheri.bib +++ b/src/riscv-cheri.bib @@ -64,4 +64,3 @@ @misc{riscv-code-size-spec note = {Version 1.0.4-3}, url = {https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.4-3/Zc-1.0.4-3.pdf} } - diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index ff97747a..4af24e86 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -1141,4 +1141,3 @@ behaves otherwise (see <> and <>). Also notes that <> is available in a read-only CSR. It can be written with <> instruction which automatically unseals the capability _before_ the invalid address conversion above. - diff --git a/src/riscv-legacy-integration.adoc b/src/riscv-legacy-integration.adoc index 5e633172..d401471c 100644 --- a/src/riscv-legacy-integration.adoc +++ b/src/riscv-legacy-integration.adoc @@ -190,7 +190,7 @@ When the XLEN-bit alias is used by <>: field. ** The tag and metadata are updated as specified in <>. * Only XLEN bits are read from the capability address field, which are extended -to XLENMAX bits according to cite:[riscv-priv-spec] _(3.1.6.2. Base ISA Control in +to XLENMAX bits according to cite:[riscv-priv-spec] _(3.1.6.2. Base ISA Control in mstatus Register)_ and are then written to the destination *x* register. When the CLEN-bit alias is used by <>: diff --git a/src/scripts/generate_tables.py b/src/scripts/generate_tables.py index 52c30067..d6afad47 100755 --- a/src/scripts/generate_tables.py +++ b/src/scripts/generate_tables.py @@ -796,4 +796,4 @@ def parse_cmdline_args(): for row in reader: for t in tables: - t.update(row) \ No newline at end of file + t.update(row) diff --git a/src/tables.adoc b/src/tables.adoc index 7276481b..822b8702 100644 --- a/src/tables.adoc +++ b/src/tables.adoc @@ -159,4 +159,3 @@ NOTE: <> and <> only exist in capability mode if legacy m |============================================================================== include::generated/illegal_insns_table_body.adoc[] |============================================================================== -