From 219b51303248e2a4ae72eaa32a2ea21c698ebc07 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Thu, 5 Dec 2024 14:42:16 +0000 Subject: [PATCH] Deleted incorrect statement about ASR needed for all M and S mode CSRs --- src/riscv-integration.adoc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/riscv-integration.adoc b/src/riscv-integration.adoc index 2672b3ce..c7989749 100644 --- a/src/riscv-integration.adoc +++ b/src/riscv-integration.adoc @@ -425,8 +425,7 @@ include::generated/csr_renamed_purecap_mode_u_table_body.adoc[] === Machine-Level CSRs {cheri_base_ext_name} extends some M-mode CSRs to hold capabilities or -otherwise add new functions. <> must grant <> to access M-mode -CSRs regardless of the RISC-V privilege mode. +otherwise add new functions. [#mstatus,reftext="mstatus"] ==== Machine Status Registers (mstatus and mstatush) @@ -832,8 +831,7 @@ CHERI violations have the following order in priority: === Supervisor-Level CSRs {cheri_base_ext_name} extends some of the existing RISC-V CSRs to be able to -hold capabilities or with other new functions. <> must grant <> -to access S-mode CSRs regardless of the RISC-V privilege mode. +hold capabilities or with other new functions. [#stvec,reftext="stvec"] ==== Supervisor Trap Vector Base Address Register (stvec)