From 8f9e442a84335b58f441aa6caa2f1b880a75534e Mon Sep 17 00:00:00 2001 From: Shobhit Date: Thu, 31 Oct 2024 19:51:16 +0530 Subject: [PATCH] Resolve conflicts between PR #152 and branch master (#211) Signed-off-by: danbone Co-authored-by: Daniel Bone Co-authored-by: danbone --- core/CMakeLists.txt | 1 + core/CPUFactories.hpp | 9 +- core/CPUTopology.cpp | 40 ++- core/DCache.cpp | 14 +- core/DCache.hpp | 21 +- core/Fetch.cpp | 238 +++++++++++++---- core/Fetch.hpp | 73 +++++- core/FusionDecode.cpp | 7 + core/ICache.cpp | 241 ++++++++++++++++++ core/ICache.hpp | 144 +++++++++++ core/Inst.cpp | 3 +- core/Inst.hpp | 42 ++- core/InstGenerator.cpp | 1 + core/MemoryAccessInfo.hpp | 42 ++- mss/BIU.cpp | 29 +-- mss/BIU.hpp | 20 +- mss/L2Cache.cpp | 44 ++-- mss/L2Cache.hpp | 36 +-- test/CMakeLists.txt | 1 + test/core/dcache/Dcache_test.cpp | 2 +- .../expected_output/arbitrate.out.EXPECTED | 86 +++---- .../expected_output/big_core.out.EXPECTED | 202 +++++++-------- .../expected_output/medium_core.out.EXPECTED | 210 +++++++-------- .../expected_output/small_core.out.EXPECTED | 220 ++++++++-------- test/core/icache/CMakeLists.txt | 8 + test/core/icache/ICacheChecker.hpp | 192 ++++++++++++++ test/core/icache/ICacheSink.hpp | 155 +++++++++++ test/core/icache/ICacheSource.hpp | 121 +++++++++ test/core/icache/ICache_test.cpp | 185 ++++++++++++++ .../test_cores/test_big_core_full.yaml | 7 +- test/core/l2cache/BIUSinkUnit.hpp | 8 +- test/core/l2cache/L2Cache_test.cpp | 12 +- test/core/l2cache/L2SourceUnit.hpp | 23 +- .../expected_output/hit_case.out.EXPECTED | 70 ++--- .../single_access.out.EXPECTED | 46 ++-- test/core/lsu/Lsu_test.cpp | 2 +- .../lsu/test_cores/test_small_core_full.yaml | 4 +- test/core/rename/Rename_test.cpp | 10 +- .../expected_output/big_core.out.EXPECTED | 40 +-- .../big_core_small_rename.out.EXPECTED | 38 +-- .../expected_output/medium_core.out.EXPECTED | 40 +-- .../expected_output/small_core.out.EXPECTED | 40 +-- .../test_cores/test_medium_core_full.yaml | 6 +- .../test_cores/test_small_core_full.yaml | 4 +- 44 files changed, 2026 insertions(+), 711 deletions(-) create mode 100644 core/ICache.cpp create mode 100644 core/ICache.hpp create mode 100644 test/core/icache/CMakeLists.txt create mode 100644 test/core/icache/ICacheChecker.hpp create mode 100644 test/core/icache/ICacheSink.hpp create mode 100644 test/core/icache/ICacheSource.hpp create mode 100644 test/core/icache/ICache_test.cpp diff --git a/core/CMakeLists.txt b/core/CMakeLists.txt index 32743498..47657c75 100644 --- a/core/CMakeLists.txt +++ b/core/CMakeLists.txt @@ -3,6 +3,7 @@ add_library(core FusionDecode.cpp Core.cpp SimpleBranchPred.cpp + ICache.cpp Fetch.cpp Decode.cpp VectorUopGenerator.cpp diff --git a/core/CPUFactories.hpp b/core/CPUFactories.hpp index 1a875ea9..2947ba89 100644 --- a/core/CPUFactories.hpp +++ b/core/CPUFactories.hpp @@ -5,6 +5,7 @@ #include "sparta/simulation/ResourceFactory.hpp" #include "Core.hpp" +#include "ICache.hpp" #include "Fetch.hpp" #include "Decode.hpp" #include "VectorUopGenerator.hpp" @@ -40,6 +41,10 @@ namespace olympia{ sparta::ResourceFactory core_rf; + //! \brief Resource Factory to build an Instruction Cache Unit + sparta::ResourceFactory icache_rf; + //! \brief Resource Factory to build a Fetch Unit sparta::ResourceFactory fetch_rf; @@ -61,7 +66,7 @@ namespace olympia{ //! \brief Resource Factory to build a Execute Unit ExecuteFactory execute_rf; - //! \brief Resource Factory to build a MMU Unit + //! \brief Resource Factory to build a Data Cache Unit sparta::ResourceFactory dcache_rf; @@ -104,7 +109,7 @@ namespace olympia{ // //! \brief Resource Factory to build a IssueQueue Unit // sparta::ResourceFactory issue_queue_rf; - + //! \brief Set up the Mavis Decode functional unit MavisFactory mavis_rf; }; // struct CPUFactories diff --git a/core/CPUTopology.cpp b/core/CPUTopology.cpp index d8fdb0a1..c2fc310a 100644 --- a/core/CPUTopology.cpp +++ b/core/CPUTopology.cpp @@ -27,6 +27,14 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ sparta::TreeNode::GROUP_IDX_NONE, &factories->flushmanager_rf }, + { + "icache", + "cpu.core*", + "Instruction Cache Unit", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + &factories->icache_rf + }, { "fetch", "cpu.core*", @@ -160,6 +168,18 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ //! Instantiating ports of this topology port_connections = { + { + "cpu.core*.fetch.ports.out_fetch_icache_req", + "cpu.core*.icache.ports.in_fetch_req" + }, + { + "cpu.core*.fetch.ports.in_icache_fetch_resp", + "cpu.core*.icache.ports.out_fetch_resp" + }, + { + "cpu.core*.fetch.ports.in_icache_fetch_credits", + "cpu.core*.icache.ports.out_fetch_credit" + }, { "cpu.core*.fetch.ports.out_fetch_queue_write", "cpu.core*.decode.ports.in_fetch_queue_write" @@ -221,20 +241,32 @@ olympia::CoreTopologySimple::CoreTopologySimple(){ "cpu.core*.l2cache.ports.in_dcache_l2cache_req" }, { - "cpu.core*.dcache.ports.in_l2cache_ack", - "cpu.core*.l2cache.ports.out_l2cache_dcache_ack" + "cpu.core*.dcache.ports.in_l2cache_credits", + "cpu.core*.l2cache.ports.out_l2cache_dcache_credits" }, { "cpu.core*.dcache.ports.in_l2cache_resp", "cpu.core*.l2cache.ports.out_l2cache_dcache_resp" }, + { + "cpu.core*.icache.ports.out_l2cache_req", + "cpu.core*.l2cache.ports.in_icache_l2cache_req" + }, + { + "cpu.core*.icache.ports.in_l2cache_credits", + "cpu.core*.l2cache.ports.out_l2cache_icache_credits" + }, + { + "cpu.core*.icache.ports.in_l2cache_resp", + "cpu.core*.l2cache.ports.out_l2cache_icache_resp" + }, { "cpu.core*.l2cache.ports.out_l2cache_biu_req", "cpu.core*.biu.ports.in_biu_req" }, { - "cpu.core*.biu.ports.out_biu_ack", - "cpu.core*.l2cache.ports.in_biu_l2cache_ack" + "cpu.core*.biu.ports.out_biu_credits", + "cpu.core*.l2cache.ports.in_biu_l2cache_credits" }, { "cpu.core*.biu.ports.out_biu_resp", diff --git a/core/DCache.cpp b/core/DCache.cpp index 1bd811b8..9b0b1b7a 100644 --- a/core/DCache.cpp +++ b/core/DCache.cpp @@ -22,8 +22,8 @@ namespace olympia in_l2cache_resp_.registerConsumerHandler( CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveRespFromL2Cache_, MemoryAccessInfoPtr)); - in_l2cache_ack_.registerConsumerHandler( - CREATE_SPARTA_HANDLER_WITH_DATA(DCache, receiveAckFromL2Cache_, uint32_t)); + in_l2cache_credits_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(DCache, getCreditsFromL2Cache_, uint32_t)); in_lsu_lookup_req_.registerConsumerEvent(in_l2_cache_resp_receive_event_); in_l2cache_resp_.registerConsumerEvent(in_l2_cache_resp_receive_event_); @@ -291,14 +291,8 @@ namespace olympia in_l2_cache_resp_receive_event_.schedule(); } - void DCache::receiveAckFromL2Cache_(const uint32_t & ack) - { - // When DCache sends the request to L2Cache for a miss, - // This bool will be set to false, and Dcache should wait for ack from - // L2Cache notifying DCache that there is space in it's dcache request buffer - // - // Set it to true so that the following misses from DCache can be sent out to L2Cache. - dcache_l2cache_credits_ = ack; + void DCache::getCreditsFromL2Cache_(const uint32_t &ack) { + dcache_l2cache_credits_ += ack; } // MSHR Entry allocation in case of miss diff --git a/core/DCache.hpp b/core/DCache.hpp index d3d87b4f..e3c3de8e 100644 --- a/core/DCache.hpp +++ b/core/DCache.hpp @@ -1,5 +1,6 @@ #pragma once +#include "sparta/simulation/Unit.hpp" #include "sparta/ports/DataPort.hpp" #include "sparta/ports/SignalPort.hpp" #include "sparta/resources/Pipeline.hpp" @@ -34,6 +35,16 @@ namespace olympia DCache(sparta::TreeNode* n, const CacheParameterSet* p); private: + bool dataLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr); + + void reloadCache_(uint64_t phy_addr); + + void getInstsFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr); + + void getCreditsFromL2Cache_(const uint32_t &); + + void getRespFromL2Cache_(const MemoryAccessInfoPtr & memory_access_info_ptr); + //////////////////////////////////////////////////////////////////////////////// // L1 Data Cache Handling //////////////////////////////////////////////////////////////////////////////// @@ -49,10 +60,6 @@ namespace olympia void setupL1Cache_(const CacheParameterSet* p); - bool dataLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr); - - void reloadCache_(uint64_t phy_addr); - uint64_t getBlockAddr(const MemoryAccessInfoPtr & mem_access_info_ptr) const; using MSHREntryInfoPtr = sparta::SpartaSharedPointer; @@ -99,10 +106,10 @@ namespace olympia sparta::DataInPort in_lsu_lookup_req_{&unit_port_set_, "in_lsu_lookup_req", 0}; - sparta::DataInPort in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1}; + sparta::DataInPort in_l2cache_credits_{&unit_port_set_, "in_l2cache_credits", 1}; - sparta::DataInPort in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp", - 1}; + sparta::DataInPort in_l2cache_resp_{&unit_port_set_, + "in_l2cache_resp", 1}; //////////////////////////////////////////////////////////////////////////////// // Output Ports diff --git a/core/Fetch.cpp b/core/Fetch.cpp index 3c27deb1..fbd784f0 100644 --- a/core/Fetch.cpp +++ b/core/Fetch.cpp @@ -9,7 +9,9 @@ #include "Fetch.hpp" #include "InstGenerator.hpp" #include "MavisUnit.hpp" +#include "OlympiaAllocators.hpp" +#include "sparta/utils/MathUtils.hpp" #include "sparta/utils/LogUtils.hpp" #include "sparta/events/StartupEvent.hpp" @@ -19,9 +21,14 @@ namespace olympia Fetch::Fetch(sparta::TreeNode* node, const FetchParameterSet* p) : sparta::Unit(node), + my_clk_(getClock()), num_insts_to_fetch_(p->num_to_fetch), skip_nonuser_mode_(p->skip_nonuser_mode), - my_clk_(getClock()) + icache_block_shift_(sparta::utils::floor_log2(p->block_width.getValue())), + ibuf_capacity_(std::ceil(p->block_width / 2)), // buffer up instructions read from trace + fetch_buffer_capacity_(p->fetch_buffer_size), + memory_access_allocator_(sparta::notNull(OlympiaAllocators::getOlympiaAllocators(node)) + ->memory_access_allocator) { in_fetch_queue_credits_.registerConsumerHandler( CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveFetchQueueCredits_, uint32_t)); @@ -29,10 +36,25 @@ namespace olympia in_fetch_flush_redirect_.registerConsumerHandler( CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, flushFetch_, FlushManager::FlushingCriteria)); - fetch_inst_event_.reset(new sparta::SingleCycleUniqueEvent<>( - &unit_event_set_, "fetch_random", CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); + in_icache_fetch_resp_. + registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveCacheResponse_, MemoryAccessInfoPtr)); + + in_icache_fetch_credits_. + registerConsumerHandler(CREATE_SPARTA_HANDLER_WITH_DATA(Fetch, receiveCacheCredit_, uint32_t)); + + ev_fetch_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "fetch_instruction_data", + CREATE_SPARTA_HANDLER(Fetch, fetchInstruction_))); + + ev_send_insts.reset(new sparta::SingleCycleUniqueEvent<>(&unit_event_set_, "send_instructions_out", + CREATE_SPARTA_HANDLER(Fetch, sendInstructions_))); + // Schedule a single event to start reading from a trace file sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(Fetch, initialize_)); + + // Capture when the simulation is stopped prematurely by the ROB i.e. hitting retire limit + node->getParent()->registerForNotification( + this, "rob_stopped_notif_channel", false /* ROB maybe not be constructed yet */); + } Fetch::~Fetch() {} @@ -40,79 +62,177 @@ namespace olympia void Fetch::initialize_() { // Get the CPU Node - auto cpu_node = getContainer()->getParent()->getParent(); - auto extension = sparta::notNull(cpu_node->getExtension("simulation_configuration")); - auto workload = extension->getParameters()->getParameter("workload"); - inst_generator_ = InstGenerator::createGenerator( - getMavis(getContainer()), workload->getValueAsString(), skip_nonuser_mode_); + auto cpu_node = getContainer()->getParent()->getParent(); + auto extension = sparta::notNull(cpu_node->getExtension("simulation_configuration")); + auto workload = extension->getParameters()->getParameter("workload"); + inst_generator_ = InstGenerator::createGenerator(getMavis(getContainer()), + workload->getValueAsString(), + skip_nonuser_mode_); - fetch_inst_event_->schedule(1); + ev_fetch_insts->schedule(1); } + void Fetch::fetchInstruction_() { - const uint32_t upper = std::min(credits_inst_queue_, num_insts_to_fetch_); - - // Nothing to send. Don't need to schedule this again. - if (upper == 0) + // Prefill the ibuf with some instructions read from the tracefile + // keeping enough capacity to group them into cache block accesses. + for (uint32_t i = ibuf_.size(); i < ibuf_capacity_; ++i) { - return; + const auto & inst_ptr = inst_generator_->getNextInst(my_clk_); + if (SPARTA_EXPECT_TRUE(nullptr != inst_ptr)) { + ibuf_.emplace_back(inst_ptr); + } + else { + break; + } } - InstGroupPtr insts_to_send = - sparta::allocate_sparta_shared_pointer(instgroup_allocator); + if (credits_icache_ == 0 || ibuf_.empty() || fetch_buffer_.size() > fetch_buffer_capacity_) { return; } + + // Gather instructions going to the same cacheblock + // NOTE: This doesn't deal with instructions straddling the blocks, + // they should be placed into the next group + auto different_blocks = [this](const auto &lhs, const auto &rhs) { + return (lhs->getPC() >> icache_block_shift_) != (rhs->getPC() >> icache_block_shift_) || + lhs->isTakenBranch() || + rhs->isCoF(); + }; + + auto block_end = std::adjacent_find(ibuf_.begin(), ibuf_.end(), different_blocks); + if (block_end != ibuf_.end()) { + ++block_end; + } + + // Send to ICache + auto memory_access_ptr = sparta::allocate_sparta_shared_pointer(memory_access_allocator_, + ibuf_.front()->getPC()); + + InstGroupPtr fetch_group_ptr = sparta::allocate_sparta_shared_pointer(instgroup_allocator); + + // Place in fetch group for the memory access, and place in fetch buffer for later processing. + for (auto iter = ibuf_.begin(); iter != block_end; iter++) { + fetch_group_ptr->emplace_back(*iter); + fetch_buffer_.emplace_back(*iter); + } + + // Set the last in block + fetch_buffer_.back()->setLastInFetchBlock(true); + + // Associate the icache transaction with the instructions + memory_access_ptr->setFetchGroup(fetch_group_ptr); + + ILOG("requesting: " << fetch_group_ptr); + + out_fetch_icache_req_.send(memory_access_ptr); + --credits_icache_; + + // We want to track blocks, not instructions. + ++fetch_buffer_occupancy_; + + ibuf_.erase(ibuf_.begin(), block_end); + if (!ibuf_.empty() && credits_icache_ > 0 && fetch_buffer_occupancy_ < fetch_buffer_capacity_) { + ev_fetch_insts->schedule(1); + } + } + + // Read instructions from the fetch buffer and send them to decode + void Fetch::sendInstructions_() + { + const uint32_t upper = std::min({credits_inst_queue_, num_insts_to_fetch_, + static_cast(fetch_buffer_.size())}); + + // Nothing to send. Don't need to schedule this again. + if (upper == 0) { return ; } + + InstGroupPtr insts_to_send = sparta::allocate_sparta_shared_pointer(instgroup_allocator); for (uint32_t i = 0; i < upper; ++i) { - InstPtr ex_inst = inst_generator_->getNextInst(my_clk_); - if (SPARTA_EXPECT_TRUE(nullptr != ex_inst)) - { - ex_inst->setSpeculative(speculative_path_); - insts_to_send->emplace_back(ex_inst); - ILOG("Sending: " << ex_inst << " down the pipe"); + const auto entry = fetch_buffer_.front(); + + // Can't send instructions that still waiting for ICache data + if (entry->getStatus() != Inst::Status::FETCHED) { + break; + } + + // Don't group instructions where there has been a change of flow + if (entry->isCoF() && insts_to_send->size() > 0) { + break; + } + + // Send instruction to decode + entry->setSpeculative(speculative_path_); + insts_to_send->emplace_back(entry); + ILOG("Sending: " << entry << " down the pipe") + fetch_buffer_.pop_front(); + + if (entry->isLastInFetchBlock()) { + --fetch_buffer_occupancy_; } - else - { + + // Only one taken branch per group + if (entry->isTakenBranch()) { break; } } - if (false == insts_to_send->empty()) - { - out_fetch_queue_write_.send(insts_to_send); + credits_inst_queue_ -= static_cast(insts_to_send->size()); + out_fetch_queue_write_.send(insts_to_send); - credits_inst_queue_ -= static_cast(insts_to_send->size()); + if (!fetch_buffer_.empty() && credits_inst_queue_ > 0) { + ev_send_insts->schedule(1); + } - if ((credits_inst_queue_ > 0) && (false == inst_generator_->isDone())) - { - fetch_inst_event_->schedule(1); - } + ev_fetch_insts->schedule(1); - if (SPARTA_EXPECT_FALSE(info_logger_)) - { - info_logger_ << "Fetch: send num_inst=" << insts_to_send->size() - << " instructions, remaining credit=" << credits_inst_queue_; + } + + void Fetch::receiveCacheResponse_(const MemoryAccessInfoPtr &response) + { + const auto & fetched_insts = response->getFetchGroup(); + sparta_assert(fetched_insts != nullptr, "no instructions set for cache request"); + if (response->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + ILOG("Cache hit response recieved for insts: " << fetched_insts); + // Mark instructions as fetched + for(auto & inst : *fetched_insts) { + inst->setStatus(Inst::Status::FETCHED); } + ev_send_insts->schedule(sparta::Clock::Cycle(0)); } - else if (SPARTA_EXPECT_FALSE(info_logger_)) - { - info_logger_ << "Fetch: no instructions from trace"; + + // Log misses + if (SPARTA_EXPECT_FALSE(info_logger_) && + response->getCacheState() == MemoryAccessInfo::CacheState::MISS) { + ILOG("Cache miss on insts: " << fetched_insts); } } + // Called when ICache has room + void Fetch::receiveCacheCredit_(const uint32_t &dat) + { + credits_icache_ += dat; + + ILOG("Fetch: receive num_credits_icache=" << dat + << ", total credits_icache=" << credits_icache_); + + // Schedule a fetch event this cycle + ev_fetch_insts->schedule(sparta::Clock::Cycle(0)); + } + // Called when decode has room void Fetch::receiveFetchQueueCredits_(const uint32_t & dat) { credits_inst_queue_ += dat; - ILOG("Fetch: receive num_decode_credits=" << dat << ", total decode_credits=" - << credits_inst_queue_); + ILOG("Fetch: receive num_decode_credits=" << dat + << ", total decode_credits=" << credits_inst_queue_); // Schedule a fetch event this cycle - fetch_inst_event_->schedule(sparta::Clock::Cycle(0)); + ev_send_insts->schedule(sparta::Clock::Cycle(0)); } // Called from FlushManager via in_fetch_flush_redirect_port - void Fetch::flushFetch_(const FlushManager::FlushingCriteria & criteria) + void Fetch::flushFetch_(const FlushManager::FlushingCriteria &criteria) { ILOG("Fetch: received flush " << criteria); @@ -131,8 +251,38 @@ namespace olympia // Cancel all previously sent instructions on the outport out_fetch_queue_write_.cancel(); + // Cancel any ICache request + out_fetch_icache_req_.cancel(); + + // Clear internal buffers + ibuf_.clear(); + fetch_buffer_.clear(); + // No longer speculative // speculative_path_ = false; } -} // namespace olympia + void Fetch::onROBTerminate_(const bool & stopped) + { + rob_stopped_simulation_ = stopped; + } + + void Fetch::dumpDebugContent_(std::ostream & output) const + { + output << "Fetch Buffer Contents" << std::endl; + for (const auto & entry : fetch_buffer_) + { + output << '\t' << entry << std::endl; + } + } + + void Fetch::onStartingTeardown_() + { + if ((false == rob_stopped_simulation_) && (false == fetch_buffer_.empty())) + { + dumpDebugContent_(std::cerr); + sparta_assert(false, "fetch buffer has pending instructions"); + } + } + +} diff --git a/core/Fetch.hpp b/core/Fetch.hpp index 1538bb17..8eb46c38 100644 --- a/core/Fetch.hpp +++ b/core/Fetch.hpp @@ -19,6 +19,7 @@ #include "CoreTypes.hpp" #include "InstGroup.hpp" #include "FlushManager.hpp" +#include "MemoryAccessInfo.hpp" namespace olympia { @@ -56,6 +57,8 @@ namespace olympia PARAMETER(uint32_t, num_to_fetch, 4, "Number of instructions to fetch") PARAMETER(bool, skip_nonuser_mode, false, "For STF traces, skip system instructions if present") + PARAMETER(uint32_t, block_width, 16, "Block width of memory read requests, in bytes") + PARAMETER(uint32_t, fetch_buffer_size, 8, "Size of fetch buffer in blocks") }; /** @@ -88,8 +91,23 @@ namespace olympia sparta::DataInPort in_fetch_flush_redirect_ {&unit_port_set_, "in_fetch_flush_redirect", sparta::SchedulingPhase::Flush, 1}; + // Instruction Cache Request + sparta::DataOutPort out_fetch_icache_req_ + {&unit_port_set_, "out_fetch_icache_req"}; + + // Instruction Cache Response + sparta::DataInPort in_icache_fetch_resp_ + {&unit_port_set_, "in_icache_fetch_resp", sparta::SchedulingPhase::Tick, 1}; + + // Instruction Cache Credit + sparta::DataInPort in_icache_fetch_credits_ + {&unit_port_set_, "in_icache_fetch_credits", sparta::SchedulingPhase::Tick, 0}; + //////////////////////////////////////////////////////////////////////////////// // Instruction fetch + + // Unit's clock + const sparta::Clock * my_clk_ = nullptr; // Number of instructions to fetch const uint32_t num_insts_to_fetch_; @@ -99,16 +117,45 @@ namespace olympia // Number of credits from decode that fetch has uint32_t credits_inst_queue_ = 0; - // Unit's clock - const sparta::Clock * my_clk_ = nullptr; + // Number of credits available in the ICache + uint32_t credits_icache_ = 0; + + // Amount to left shift an Instructions PC to get the ICache block number + const uint32_t icache_block_shift_; + + // Buffers up instructions read from the tracefile + std::deque ibuf_; + + // Size of trace buffer (must be sized >= L1ICache bandwidth / 2B) + const uint32_t ibuf_capacity_; + + // Fetch buffer: Holds a queue of instructions that are either + // waiting for an ICache hit response, or they're ready to be + // send to decode + std::deque fetch_buffer_; + + // Size of fetch buffer, tracked separately as it sized + // in terms of icache block requests, not instructions. + const uint32_t fetch_buffer_capacity_; + uint32_t fetch_buffer_occupancy_ = 0; + + // allocator for ICache transactions + MemoryAccessInfoAllocator & memory_access_allocator_; + + // ROB terminated simulation + bool rob_stopped_simulation_ {false}; // Instruction generation std::unique_ptr inst_generator_; - // Fetch instruction event, triggered when there are credits - // from decode. The callback set is either to fetch random - // instructions or a perfect IPC set - std::unique_ptr> fetch_inst_event_; + // Fetch instruction event, the callback is set to request + // instructions from the instruction cache and place them in the + // fetch buffer. + std::unique_ptr> ev_fetch_insts; + + // Send instructions event, the callback is set to read instructions + // from the fetch buffer and send them to the decode unit + std::unique_ptr> ev_send_insts; //////////////////////////////////////////////////////////////////////////////// // Callbacks @@ -122,9 +169,23 @@ namespace olympia // Read data from a trace void fetchInstruction_(); + // Read instructions from the fetch buffer and send them to decode + void sendInstructions_(); + // Receive flush from FlushManager void flushFetch_(const FlushManager::FlushingCriteria &); + // Receieve the number of free credits from the instruction cache + void receiveCacheCredit_(const uint32_t &); + + // Receive read data from the instruction cache + void receiveCacheResponse_(const MemoryAccessInfoPtr &); + + // Debug callbacks, used to log fetch buffer contents + void onROBTerminate_(const bool&); + void onStartingTeardown_() override; + void dumpDebugContent_(std::ostream&) const override final; + // Are we fetching a speculative path? bool speculative_path_ = false; }; diff --git a/core/FusionDecode.cpp b/core/FusionDecode.cpp index ef1f3f3c..3b0296c8 100644 --- a/core/FusionDecode.cpp +++ b/core/FusionDecode.cpp @@ -126,6 +126,13 @@ namespace olympia { auto & fGrp = fgPair.second; size_t grpSize = fGrp.uids().size(); + + // grpSize should be less than the input for matching fusion pairs + if(grpSize > inputUids.size()) + { + continue; + } + hcache_.buildHashCacheEntry(inputUids, grpSize); } diff --git a/core/ICache.cpp b/core/ICache.cpp new file mode 100644 index 00000000..b78b8a58 --- /dev/null +++ b/core/ICache.cpp @@ -0,0 +1,241 @@ +// -*- C++ -*- + +//! +//! \file ICache.cpp +//! \brief Implementation of the CoreModel ICache unit +//! + + +#include "ICache.hpp" + +#include "OlympiaAllocators.hpp" + + +namespace olympia { + const char ICache::name[] = "icache"; + + ICache::ICache(sparta::TreeNode *node, const ICacheParameterSet *p) : + sparta::Unit(node), + l1_always_hit_(p->l1_always_hit), + cache_latency_(p->cache_latency), + pending_miss_buffer_("pending_miss_buffer", fetch_queue_size_, getClock()), + memory_access_allocator_( + sparta::notNull(olympia::OlympiaAllocators::getOlympiaAllocators(node))-> + memory_access_allocator) + { + + in_fetch_req_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getRequestFromFetch_, MemoryAccessInfoPtr)); + + in_l2cache_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getCreditsFromL2Cache_, uint32_t)); + + in_l2cache_resp_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICache, getRespFromL2Cache_, MemoryAccessInfoPtr)); + + // IL1 cache config + const uint32_t l1_line_size = p->l1_line_size; + const uint32_t l1_size_kb = p->l1_size_kb; + const uint32_t l1_associativity = p->l1_associativity; + std::unique_ptr repl(new sparta::cache::TreePLRUReplacement + (l1_associativity)); + l1_cache_.reset(new CacheFuncModel(getContainer(), l1_size_kb, l1_line_size, *repl)); + sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(ICache, sendInitialCredits_)); + + + } + + void ICache::sendInitialCredits_() + { + out_fetch_credit_.send(fetch_queue_size_); + } + + // Access ICache + bool ICache::lookupCache_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + uint64_t phyAddr = mem_access_info_ptr->getPhyAddr(); + + bool cache_hit = false; + + if (l1_always_hit_) { + cache_hit = true; + } + else { + auto cache_line = l1_cache_->peekLine(phyAddr); + cache_hit = (cache_line != nullptr) && cache_line->isValid(); + + // Update MRU replacement state if ICache HIT + if (cache_hit) { + l1_cache_->touchMRU(*cache_line); + } + } + + if (l1_always_hit_) { + ILOG("IL1 Cache HIT all the time: phyAddr=0x" << std::hex << phyAddr); + il1_cache_hits_++; + } + else if (cache_hit) { + ILOG("IL1 Cache HIT: phyAddr=0x" << std::hex << phyAddr); + il1_cache_hits_++; + } + else { + ILOG("IL1 Cache MISS: phyAddr=0x" << std::hex << phyAddr); + il1_cache_misses_++; + } + + return cache_hit; + } + + void ICache::reloadCache_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + + auto const decoder = l1_cache_->getAddrDecoder(); + auto const reload_addr = mem_access_info_ptr->getPhyAddr(); + auto const reload_block = decoder->calcBlockAddr(reload_addr); + + auto l1_cache_line = &l1_cache_->getLineForReplacementWithInvalidCheck(reload_addr); + l1_cache_->allocateWithMRUUpdate(*l1_cache_line, reload_addr); + + // Move pending misses into the replay queue + DLOG("finding misses to replay"); + auto iter = pending_miss_buffer_.begin(); + while (iter != pending_miss_buffer_.end()) { + auto delete_iter = iter++; + + if (decoder->calcBlockAddr((*delete_iter)->getPhyAddr()) == reload_block) { + DLOG("scheduling for replay " << *delete_iter); + replay_buffer_.emplace_back(*delete_iter); + pending_miss_buffer_.erase(delete_iter); + } + } + + // Schedule next cycle + DLOG("reload completed"); + ev_arbitrate_.schedule(1); + } + + void ICache::doArbitration_() + { + if (!l2cache_resp_queue_.empty()) { + // Do a linefill + auto const mem_access_info_ptr = l2cache_resp_queue_.front(); + ILOG("doing reload " << mem_access_info_ptr); + reloadCache_(mem_access_info_ptr); + l2cache_resp_queue_.pop_front(); + } + + // Priotize replays over fetches, replays can run in parallel with a fill. + // NOTE: Ideally we'd want to prioritize demand fetches over lingering misses + // from a speculative search + if (!replay_buffer_.empty()) { + // Replay miss + auto const mem_access_info_ptr = replay_buffer_.front(); + ILOG("doing replay for fetch request " << mem_access_info_ptr); + ev_replay_ready_.preparePayload(mem_access_info_ptr) + ->schedule(sparta::Clock::Cycle(cache_latency_)); + replay_buffer_.pop_front(); + + } + else if (!fetch_req_queue_.empty()) { + // Do a read access + auto const mem_access_info_ptr = fetch_req_queue_.front(); + ILOG("doing lookup for fetch request " << mem_access_info_ptr); + if (lookupCache_(mem_access_info_ptr)) { + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + } + else { + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::MISS); + addToMissQueue_(mem_access_info_ptr); + } + ev_respond_.preparePayload(mem_access_info_ptr) + ->schedule(sparta::Clock::Cycle(cache_latency_)); + fetch_req_queue_.pop_front(); + } + + if (!l2cache_resp_queue_.empty() || !replay_buffer_.empty() || !fetch_req_queue_.empty()) { + ev_arbitrate_.schedule(1); + } + } + + void ICache::addToMissQueue_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Don't make requests to cachelines that are already pending + auto const decoder = l1_cache_->getAddrDecoder(); + auto missed_block = decoder->calcBlockAddr(mem_access_info_ptr->getPhyAddr()); + auto same_line = [decoder, missed_block] (auto other) { + return decoder->calcBlockAddr(other->getPhyAddr()) == missed_block; + }; + auto it = std::find_if(pending_miss_buffer_.begin(), pending_miss_buffer_.end(), same_line); + if (it == pending_miss_buffer_.end()) { + DLOG("appending miss to l2 miss queue: " << mem_access_info_ptr); + miss_queue_.emplace_back(mem_access_info_ptr); + makeL2CacheRequest_(); + } + ILOG("miss request queued for replay: " << mem_access_info_ptr); + pending_miss_buffer_.push_back(mem_access_info_ptr); + } + + void ICache::getRequestFromFetch_(const MemoryAccessInfoPtr &mem_access_info_ptr) + { + ILOG("received fetch request " << mem_access_info_ptr); + fetch_req_queue_.emplace_back(mem_access_info_ptr); + ev_arbitrate_.schedule(sparta::Clock::Cycle(0)); + } + + void ICache::getRespFromL2Cache_(const MemoryAccessInfoPtr &mem_access_info_ptr) + { + ILOG("received fill response " << mem_access_info_ptr); + if (mem_access_info_ptr->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + l2cache_resp_queue_.emplace_back(mem_access_info_ptr); + ev_arbitrate_.schedule(sparta::Clock::Cycle(0)); + } + } + + void ICache::getCreditsFromL2Cache_(const uint32_t &ack) + { + l2cache_credits_ += ack; + if (!miss_queue_.empty()) { + ev_l2cache_request_.schedule(sparta::Clock::Cycle(0)); + } + } + + // Respond misses + void ICache::sendReplay_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Delayed change to hit state until we're ready to send it back + mem_access_info_ptr->setCacheState(MemoryAccessInfo::CacheState::HIT); + out_fetch_resp_.send(mem_access_info_ptr); + out_fetch_credit_.send(1); + } + + void ICache::sendResponse_(const MemoryAccessInfoPtr & mem_access_info_ptr) + { + out_fetch_resp_.send(mem_access_info_ptr); + if (mem_access_info_ptr->getCacheState() == MemoryAccessInfo::CacheState::HIT) { + out_fetch_credit_.send(1); + } + } + + void ICache::makeL2CacheRequest_() + { + if (l2cache_credits_ == 0 || miss_queue_.empty()) { + return; + } + + // Create new MemoryAccessInfo to avoid propagating changes made by L2 back to the core + const auto &l2cache_req = sparta::allocate_sparta_shared_pointer( + memory_access_allocator_, *(miss_queue_.front())); + + // Forward miss to next cache level + ILOG("requesting linefill for " << l2cache_req); + out_l2cache_req_.send(l2cache_req); + --l2cache_credits_; + + miss_queue_.pop_front(); + + // Schedule another + if (l2cache_credits_ > 0 && !miss_queue_.empty()) { + ev_l2cache_request_.schedule(1); + } + } +} diff --git a/core/ICache.hpp b/core/ICache.hpp new file mode 100644 index 00000000..ed18b962 --- /dev/null +++ b/core/ICache.hpp @@ -0,0 +1,144 @@ +// -*- C++ -*- + +//! +//! \file Fetch.hpp +//! \brief Definition of the CoreModel ICache unit +//! + +#pragma once + +#include "sparta/simulation/Unit.hpp" +#include "sparta/ports/DataPort.hpp" +#include "sparta/ports/SignalPort.hpp" +#include "sparta/simulation/ParameterSet.hpp" +#include "sparta/resources/Buffer.hpp" +#include "sparta/utils/LogUtils.hpp" + +#include "CacheFuncModel.hpp" +#include "Inst.hpp" +#include "cache/TreePLRUReplacement.hpp" +#include "MemoryAccessInfo.hpp" + +namespace olympia +{ + + /** + * @file ICache.hpp + * @brief The L1 Instruction Cache block -- L1 Cache unit for instruction code + * + * This is an L1 Instruction Cache that features: + * - Hit and miss under miss + * - Pipelining of requests + * - Automatic miss replay following a linefill + * Both interfaces use a credit protocol. + */ + class ICache : public sparta::Unit + { + public: + class ICacheParameterSet : public sparta::ParameterSet + { + public: + ICacheParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {} + + // Parameters for the IL1 cache + PARAMETER(uint32_t, l1_line_size, 64, "IL1 line size (power of 2)") + PARAMETER(uint32_t, l1_size_kb, 32, "Size of IL1 in KB (power of 2)") + PARAMETER(uint32_t, l1_associativity, 8, "IL1 associativity (power of 2)") + PARAMETER(uint32_t, cache_latency, 1, "Assumed latency of the memory system") + PARAMETER(bool, l1_always_hit, false, "IL1 will always hit") + }; + + static const char name[]; + ICache(sparta::TreeNode* n, const ICacheParameterSet* p); + + private: + + void doArbitration_(); + void sendReplay_(const MemoryAccessInfoPtr &); + void sendResponse_(const MemoryAccessInfoPtr &); + void addToMissQueue_(const MemoryAccessInfoPtr &); + void makeL2CacheRequest_(); + void reloadCache_(const MemoryAccessInfoPtr&); + bool lookupCache_(const MemoryAccessInfoPtr &); + + void sendInitialCredits_(); + + // Callbacks + void getRequestFromFetch_(const MemoryAccessInfoPtr &); + void getCreditsFromL2Cache_(const uint32_t &); + void getRespFromL2Cache_(const MemoryAccessInfoPtr &); + + using L1Handle = CacheFuncModel::Handle; + L1Handle l1_cache_; + const bool l1_always_hit_; + const uint32_t cache_latency_ = 0; + const uint32_t fetch_queue_size_ = 8; + + std::deque l2cache_resp_queue_; + std::deque fetch_req_queue_; + std::deque replay_buffer_; + std::deque miss_queue_; + + sparta::Buffer pending_miss_buffer_; + + // Credits for sending miss request to L2Cache + uint32_t l2cache_credits_ = 0; + + olympia::MemoryAccessInfoAllocator & memory_access_allocator_; + + //////////////////////////////////////////////////////////////////////////////// + // Input Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataInPort in_fetch_req_{&unit_port_set_, + "in_fetch_req", 1}; + + sparta::DataInPort in_l2cache_credits_{&unit_port_set_, "in_l2cache_credits", 1}; + + sparta::DataInPort in_l2cache_resp_{&unit_port_set_, + "in_l2cache_resp", 1}; + + //////////////////////////////////////////////////////////////////////////////// + // Output Ports + //////////////////////////////////////////////////////////////////////////////// + + sparta::DataOutPort out_fetch_credit_{&unit_port_set_, + "out_fetch_credit", 0}; + + sparta::DataOutPort out_fetch_resp_{&unit_port_set_, + "out_fetch_resp", 0}; + + sparta::DataOutPort out_l2cache_req_{&unit_port_set_, + "out_l2cache_req", 0}; + + //////////////////////////////////////////////////////////////////////////////// + // Events + //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> ev_arbitrate_{&unit_event_set_, "ev_arbitrate", + CREATE_SPARTA_HANDLER(ICache, doArbitration_)}; + + sparta::UniqueEvent<> ev_l2cache_request_{&unit_event_set_, "ev_l2cache_request", + CREATE_SPARTA_HANDLER(ICache, makeL2CacheRequest_)}; + + + sparta::PayloadEvent ev_respond_{ + &unit_event_set_, "ev_respond", + CREATE_SPARTA_HANDLER_WITH_DATA(ICache, sendResponse_, MemoryAccessInfoPtr)}; + + sparta::PayloadEvent ev_replay_ready_{ + &unit_event_set_, "ev_replay_ready", + CREATE_SPARTA_HANDLER_WITH_DATA(ICache, sendReplay_, MemoryAccessInfoPtr)}; + + //////////////////////////////////////////////////////////////////////////////// + // Counters + //////////////////////////////////////////////////////////////////////////////// + sparta::Counter il1_cache_hits_{getStatisticSet(), "IL1_cache_hits", + "Number of IL1 cache hits", sparta::Counter::COUNT_NORMAL}; + + sparta::Counter il1_cache_misses_{getStatisticSet(), "IL1_cache_misses", + "Number of IL1 cache misses", + sparta::Counter::COUNT_NORMAL}; + + friend class ICacheTester; + }; + class ICacheTester; +} // namespace olympia diff --git a/core/Inst.cpp b/core/Inst.cpp index a171c815..229fd4c4 100644 --- a/core/Inst.cpp +++ b/core/Inst.cpp @@ -6,6 +6,7 @@ namespace olympia { const std::unordered_map Inst::status2String = { + { Inst::Status::BEFORE_FETCH,"BEFORE_FETCH" }, { Inst::Status::FETCHED, "FETCHED" }, { Inst::Status::DECODED, "DECODED" }, { Inst::Status::RENAMED, "RENAMED" }, @@ -71,7 +72,7 @@ namespace olympia is_vector_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::VECTOR)), is_return_(isReturnInstruction(opcode_info)), has_immediate_(opcode_info_->hasImmediate()), - status_state_(Status::FETCHED) + status_state_(Status::BEFORE_FETCH) { sparta_assert(inst_arch_info_ != nullptr, "Mavis decoded the instruction, but Olympia has no uarch data for it: " diff --git a/core/Inst.hpp b/core/Inst.hpp index 9f62e06c..78f8afb1 100644 --- a/core/Inst.hpp +++ b/core/Inst.hpp @@ -85,8 +85,9 @@ namespace olympia enum class Status : std::uint16_t { - FETCHED = 0, - __FIRST = FETCHED, + BEFORE_FETCH = 0, + __FIRST = BEFORE_FETCH, + FETCHED, DECODED, RENAMED, DISPATCHED, @@ -116,6 +117,12 @@ namespace olympia // implement it and let the compiler do it for us for speed. Inst(const Inst & other) = default; + const Status & getStatus() const { return status_state_; } + + bool getCompletedStatus() const { return getStatus() == olympia::Inst::Status::COMPLETED; } + + bool getFlushedStatus() const { return getStatus() == olympia::Inst::Status::FLUSHED; } + void setStatus(Status status) { sparta_assert(status_state_ != status, @@ -133,17 +140,6 @@ namespace olympia } } - const Status & getStatus() const { return status_state_; } - - bool getCompletedStatus() const { return getStatus() == olympia::Inst::Status::COMPLETED; } - - bool getFlushedStatus() const { return getStatus() == olympia::Inst::Status::FLUSHED; } - - void setMispredicted() { is_mispredicted_ = true; } - - // Is this branch instruction mispredicted? - bool isMispredicted() const { return is_mispredicted_; } - const Status & getExtendedStatus() const { return extended_status_state_; } void setExtendedStatus(Status status) @@ -216,6 +212,7 @@ namespace olympia // Set the instruction's target PC (branch target or load/store target) void setTargetVAddr(sparta::memory::addr_t target_vaddr) { target_vaddr_ = target_vaddr; } + sparta::memory::addr_t getTargetVAddr() const { return target_vaddr_; } void setVectorConfig(const VectorConfigPtr input_vector_config) @@ -238,9 +235,17 @@ namespace olympia // Branch instruction was taken (always set for JAL/JALR) void setTakenBranch(bool taken) { is_taken_branch_ = taken; } + // Is this branch instruction mispredicted? + bool isMispredicted() const { return is_mispredicted_; } + void setMispredicted() { is_mispredicted_ = true; } + // TBD -- add branch prediction void setSpeculative(bool spec) { is_speculative_ = spec; } + // Last instruction within the cache block fetched from the ICache + void setLastInFetchBlock(bool last) { last_in_fetch_block_ = last; } + bool isLastInFetchBlock() const { return last_in_fetch_block_; } + // Opcode information std::string getMnemonic() const { return opcode_info_->getMnemonic(); } @@ -339,6 +344,9 @@ namespace olympia bool isVector() const { return is_vector_; } + void setCoF(const bool &cof) { is_cof_ = cof; } + bool isCoF() const { return is_cof_; } + // Rename information core_types::RegisterBitMask & getSrcRegisterBitMask(const core_types::RegFile rf) { @@ -432,6 +440,8 @@ namespace olympia const bool is_csr_; const bool is_vector_; const bool is_return_; + // Is this instruction a change of flow? + bool is_cof_ = false; const bool has_immediate_; VectorConfigPtr vector_config_{new VectorConfig}; @@ -446,6 +456,7 @@ namespace olympia // Did this instruction mispredict? bool is_mispredicted_ = false; bool is_taken_branch_ = false; + bool last_in_fetch_block_ = false; // This is the last instruction in the fetch block sparta::Scheduleable* ev_retire_ = nullptr; Status status_state_; Status extended_status_state_{Inst::Status::UNMOD}; @@ -471,6 +482,9 @@ namespace olympia { switch (status) { + case Inst::Status::BEFORE_FETCH: + os << "BEFORE_FETCH"; + break; case Inst::Status::FETCHED: os << "FETCHED"; break; @@ -517,7 +531,7 @@ namespace olympia // - any changes here will break EXPECT inline std::ostream & operator<<(std::ostream & os, const Inst & inst) { - os << "uid:" << inst.getUniqueID() << std::setw(10) << inst.getStatus() << " " + os << "uid:" << inst.getUniqueID() << " " << std::setw(10) << inst.getStatus() << " " << std::hex << inst.getPC() << std::dec << " pid:" << inst.getProgramID() << " uopid:" << inst.getUOpID() << " '" << inst.getDisasm() << "' "; return os; diff --git a/core/InstGenerator.cpp b/core/InstGenerator.cpp index 73772c8c..385b66f8 100644 --- a/core/InstGenerator.cpp +++ b/core/InstGenerator.cpp @@ -252,6 +252,7 @@ namespace olympia // For misaligns, more than 1 address is provided // inst->setVAddrVector(std::move(addrs)); } + inst->setCoF(next_it_->isCoF()); if (next_it_->isBranch()) { inst->setTakenBranch(next_it_->isTakenBranch()); diff --git a/core/MemoryAccessInfo.hpp b/core/MemoryAccessInfo.hpp index f0d2cf6b..0c92c434 100644 --- a/core/MemoryAccessInfo.hpp +++ b/core/MemoryAccessInfo.hpp @@ -8,6 +8,7 @@ #include "sparta/utils/SpartaSharedPointer.hpp" #include "sparta/utils/SpartaSharedPointerAllocator.hpp" #include "Inst.hpp" +#include "InstGroup.hpp" namespace olympia { @@ -72,6 +73,19 @@ namespace olympia MemoryAccessInfo(const MemoryAccessInfo &rhs) = default; + MemoryAccessInfo(const uint64_t addr) : + ldst_inst_ptr_(nullptr), + phy_addr_ready_(true), + mmu_access_state_(MMUState::NO_ACCESS), + cache_access_state_(CacheState::NO_ACCESS), + cache_data_ready_(false), + src_(ArchUnit::NO_ACCESS), + dest_(ArchUnit::NO_ACCESS), + vaddr_(addr), + paddr_(addr) + {} + + MemoryAccessInfo(const InstPtr & inst_ptr) : ldst_inst_ptr_(inst_ptr), phy_addr_ready_(false), @@ -82,7 +96,9 @@ namespace olympia cache_data_ready_(false), is_refill_(false), src_(ArchUnit::NO_ACCESS), - dest_(ArchUnit::NO_ACCESS) + dest_(ArchUnit::NO_ACCESS), + vaddr_(inst_ptr->getTargetVAddr()), + paddr_(inst_ptr->getRAdr()) { } @@ -110,9 +126,9 @@ namespace olympia bool getPhyAddrStatus() const { return phy_addr_ready_; } - uint64_t getPhyAddr() const { return ldst_inst_ptr_->getRAdr(); } + uint64_t getPhyAddr() const { return paddr_; } - sparta::memory::addr_t getVAddr() const { return ldst_inst_ptr_->getTargetVAddr(); } + sparta::memory::addr_t getVAddr() const { return vaddr_; } void setSrcUnit(const ArchUnit & src_unit) { src_ = src_unit; } @@ -140,6 +156,9 @@ namespace olympia void setDataReady(bool is_ready) { cache_data_ready_ = is_ready; } + void setFetchGroup(const InstGroupPtr &group) { fetch_group_ = group; } + const InstGroupPtr & getFetchGroup() const { return fetch_group_; } + const LoadStoreInstIterator getIssueQueueIterator() const { return issue_queue_iterator_; } bool isRefill() const { return is_refill_; } @@ -173,7 +192,7 @@ namespace olympia private: // load/store instruction pointer - InstPtr ldst_inst_ptr_; + const InstPtr ldst_inst_ptr_; // Indicate MMU address translation status bool phy_addr_ready_; @@ -191,11 +210,21 @@ namespace olympia ArchUnit src_ = ArchUnit::NO_ACCESS; ArchUnit dest_ = ArchUnit::NO_ACCESS; + // Virtual Address + const uint64_t vaddr_; + + // Physical Address + const uint64_t paddr_; + // Pointer to next request for DEBUG/TRACK // (Note : Currently used only to track request with same cacheline in L2Cache // Not for functional/performance purpose) MemoryAccessInfoPtr next_req_ = nullptr; + // Instructions that this memory access is fetching + // *USED* only for instruction fetch + InstGroupPtr fetch_group_; + LoadStoreInstIterator issue_queue_iterator_; LoadStoreInstIterator replay_queue_iterator_; MSHREntryInfoIterator mshr_entry_info_iterator_; @@ -279,7 +308,10 @@ namespace olympia inline std::ostream & operator<<(std::ostream & os, const olympia::MemoryAccessInfo & mem) { - os << "memptr: " << mem.getInstPtr(); + os << "memptr: " << std::hex << mem.getPhyAddr() << std::dec; + if (mem.getInstPtr() != nullptr) { + os << " " << mem.getInstPtr(); + } return os; } diff --git a/mss/BIU.cpp b/mss/BIU.cpp index 82452e1f..47aea104 100644 --- a/mss/BIU.cpp +++ b/mss/BIU.cpp @@ -27,6 +27,8 @@ namespace olympia_mss sparta::StartupEvent(node, CREATE_SPARTA_HANDLER(BIU, sendInitialCredits_)); ILOG("BIU construct: #" << node->getGroupIdx()); + + ev_handle_mss_ack_ >> ev_handle_biu_req_; } @@ -36,7 +38,7 @@ namespace olympia_mss // Sending Initial credits to L2Cache void BIU::sendInitialCredits_() { - out_biu_ack_.send(biu_req_queue_size_); + out_biu_credits_.send(biu_req_queue_size_); ILOG("Sending initial credits to L2Cache : " << biu_req_queue_size_); } @@ -64,28 +66,24 @@ namespace olympia_mss } // Handle BIU request - void BIU::handle_BIU_Req_() + void BIU::handleBIUReq_() { biu_busy_ = true; out_mss_req_sync_.send(biu_req_queue_.front(), biu_latency_); - if (biu_req_queue_.size() < biu_req_queue_size_) { - // Send out the ack to L2Cache if there is space in biu_req_queue_ - ev_handle_biu_l2cache_ack_.schedule(sparta::Clock::Cycle(0)); - } - ILOG("BIU request is sent to MSS!"); } // Handle MSS Ack - void BIU::handle_MSS_Ack_() + void BIU::handleMSSAck_() { out_biu_resp_.send(biu_req_queue_.front(), biu_latency_); biu_req_queue_.pop_front(); - // Send out the ack to L2Cache through , we just created space in biu_req_queue_ - ev_handle_biu_l2cache_ack_.schedule(sparta::Clock::Cycle(0)); + // Send out a credit to L2Cache, as we just created space in biu_req_queue_ + out_biu_credits_.send(1); + biu_busy_ = false; // Schedule BIU request handling event only when: @@ -94,7 +92,7 @@ namespace olympia_mss ev_handle_biu_req_.schedule(sparta::Clock::Cycle(0)); } - ILOG("MSS Ack is sent to LSU!"); + ILOG("BIU response sent back!"); } // Receive MSS access acknowledge @@ -112,15 +110,6 @@ namespace olympia_mss sparta_assert(false, "MSS is NOT done!"); } - // Handle ack backto L2Cache - void BIU::handle_BIU_L2Cache_Ack_() - { - uint32_t available_slots = biu_req_queue_size_ - biu_req_queue_.size(); - out_biu_ack_.send(available_slots); - - ILOG("BIU->L2Cache : Ack is sent."); - } - //////////////////////////////////////////////////////////////////////////////// // Regular Function/Subroutine Call //////////////////////////////////////////////////////////////////////////////// diff --git a/mss/BIU.hpp b/mss/BIU.hpp index 55a84acd..ca7aa5ad 100644 --- a/mss/BIU.hpp +++ b/mss/BIU.hpp @@ -67,8 +67,8 @@ namespace olympia_mss // Output Ports //////////////////////////////////////////////////////////////////////////////// - sparta::DataOutPort out_biu_ack_ - {&unit_port_set_, "out_biu_ack"}; + sparta::DataOutPort out_biu_credits_ + {&unit_port_set_, "out_biu_credits"}; sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; @@ -96,16 +96,11 @@ namespace olympia_mss // Event to handle BIU request from L2Cache sparta::UniqueEvent<> ev_handle_biu_req_ - {&unit_event_set_, "handle_biu_req", CREATE_SPARTA_HANDLER(BIU, handle_BIU_Req_)}; + {&unit_event_set_, "handle_biu_req", CREATE_SPARTA_HANDLER(BIU, handleBIUReq_)}; // Event to handle MSS Ack sparta::UniqueEvent<> ev_handle_mss_ack_ - {&unit_event_set_, "handle_mss_ack", CREATE_SPARTA_HANDLER(BIU, handle_MSS_Ack_)}; - - // Event to handleBIU ack for L2Cache - sparta::UniqueEvent<> ev_handle_biu_l2cache_ack_ - {&unit_event_set_, "ev_handle_biu_l2cache_ack", CREATE_SPARTA_HANDLER(BIU, handle_BIU_L2Cache_Ack_)}; - + {&unit_event_set_, "handle_mss_ack", CREATE_SPARTA_HANDLER(BIU, handleMSSAck_)}; //////////////////////////////////////////////////////////////////////////////// // Callbacks @@ -115,13 +110,10 @@ namespace olympia_mss void receiveReqFromL2Cache_(const olympia::MemoryAccessInfoPtr &); // Handle BIU request - void handle_BIU_Req_(); + void handleBIUReq_(); // Handle MSS Ack - void handle_MSS_Ack_(); - - // Handle ack backto L2Cache - void handle_BIU_L2Cache_Ack_(); + void handleMSSAck_(); // Receive MSS access acknowledge // Q: Does the argument list has to be "const DataType &" ? diff --git a/mss/L2Cache.cpp b/mss/L2Cache.cpp index 55c877d6..b04aa2e7 100644 --- a/mss/L2Cache.cpp +++ b/mss/L2Cache.cpp @@ -96,8 +96,8 @@ namespace olympia_mss in_biu_resp_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getRespFromBIU_, olympia::MemoryAccessInfoPtr)); - in_biu_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getAckFromBIU_, uint32_t)); + in_biu_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(L2Cache, getCreditsFromBIU_, uint32_t)); // Pipeline collection config l2cache_pipeline_.enableCollection(node); @@ -134,12 +134,12 @@ namespace olympia_mss // Sending Initial credits to I/D-Cache void L2Cache::sendInitialCredits_() { if (is_icache_connected_) { - out_l2cache_icache_ack_.send(icache_req_queue_size_); + out_l2cache_icache_credits_.send(icache_req_queue_size_); ILOG("Sending initial credits to ICache : " << icache_req_queue_size_); } if (is_dcache_connected_) { - out_l2cache_dcache_ack_.send(dcache_req_queue_size_); + out_l2cache_dcache_credits_.send(dcache_req_queue_size_); ILOG("Sending initial credits to DCache : " << dcache_req_queue_size_); } } @@ -184,16 +184,16 @@ namespace olympia_mss } } - // Handle BIU ack - void L2Cache::getAckFromBIU_(const uint32_t & ack) { + // Handle BIU Credits + void L2Cache::getCreditsFromBIU_(const uint32_t & credits) { // Update the biu credits - l2cache_biu_credits_ = ack; + l2cache_biu_credits_ += credits; // Kickstart the pipeline issueing ev_issue_req_.schedule(1); - ILOG("Ack received from BIU on the port : Current BIU credit available = " << l2cache_biu_credits_); + ILOG("Credits received from BIU on the port : Current BIU credit available = " << l2cache_biu_credits_); } // Handle L2Cache request from DCache @@ -236,24 +236,6 @@ namespace olympia_mss } } - // Returning ack to DCache - void L2Cache::handle_L2Cache_DCache_Ack_() { - uint32_t available_slots = dcache_req_queue_size_ - dcache_req_queue_.size(); - out_l2cache_dcache_ack_.send(available_slots); - ++num_acks_to_dcache_; - - ILOG("L2Cache->DCache : Ack is sent."); - } - - // Returning resp to ICache - void L2Cache::handle_L2Cache_ICache_Ack_() { - uint32_t available_slots = icache_req_queue_size_ - icache_req_queue_.size(); - out_l2cache_icache_ack_.send(available_slots); - ++num_acks_to_icache_; - - ILOG("L2Cache->ICache : Ack is sent."); - } - // Returning resp to DCache void L2Cache::handle_L2Cache_DCache_Resp_() { out_l2cache_dcache_resp_.send(dcache_resp_queue_.front()); @@ -337,7 +319,10 @@ namespace olympia_mss icache_req_queue_.erase(icache_req_queue_.begin()); // Send out the ack to ICache for credit management - ev_handle_l2cache_icache_ack_.schedule(sparta::Clock::Cycle(1)); + out_l2cache_icache_credits_.send(1, 1); + ILOG("L2Cache->ICache : Credit is sent."); + ++num_acks_to_icache_; + } else if (arbitration_winner == Channel::DCACHE) { @@ -353,7 +338,10 @@ namespace olympia_mss dcache_req_queue_.erase(dcache_req_queue_.begin()); // Send out the ack to DCache for credit management - ev_handle_l2cache_dcache_ack_.schedule(sparta::Clock::Cycle(1)); + out_l2cache_dcache_credits_.send(1, 1); + ILOG("L2Cache->DCache : Credit is sent."); + ++num_acks_to_dcache_; + } else if (arbitration_winner == Channel::NO_ACCESS) { // Schedule a ev_create_req_ event again to see if the the new request diff --git a/mss/L2Cache.hpp b/mss/L2Cache.hpp index a5fb1610..f367d373 100644 --- a/mss/L2Cache.hpp +++ b/mss/L2Cache.hpp @@ -57,7 +57,7 @@ namespace olympia_mss PARAMETER(bool, l2_always_hit, false, "L2 will always hit") PARAMETER(uint32_t, l2cache_latency, 10, "Cache Lookup HIT latency") - PARAMETER(bool, is_icache_connected, false, "Does this unit have ICache connected to it") + PARAMETER(bool, is_icache_connected, true, "Does this unit have ICache connected to it") PARAMETER(bool, is_dcache_connected, true, "Does this unit have DCache connected to it") }; @@ -107,8 +107,8 @@ namespace olympia_mss sparta::DataInPort in_biu_resp_ {&unit_port_set_, "in_biu_l2cache_resp", 1}; - sparta::DataInPort in_biu_ack_ - {&unit_port_set_, "in_biu_l2cache_ack", 1}; + sparta::DataInPort in_biu_credits_ + {&unit_port_set_, "in_biu_l2cache_credits", 1}; //////////////////////////////////////////////////////////////////////////////// @@ -124,11 +124,11 @@ namespace olympia_mss sparta::DataOutPort out_l2cache_dcache_resp_ {&unit_port_set_, "out_l2cache_dcache_resp"}; - sparta::DataOutPort out_l2cache_icache_ack_ - {&unit_port_set_, "out_l2cache_icache_ack"}; + sparta::DataOutPort out_l2cache_icache_credits_ + {&unit_port_set_, "out_l2cache_icache_credits"}; - sparta::DataOutPort out_l2cache_dcache_ack_ - {&unit_port_set_, "out_l2cache_dcache_ack"}; + sparta::DataOutPort out_l2cache_dcache_credits_ + {&unit_port_set_, "out_l2cache_dcache_credits"}; //////////////////////////////////////////////////////////////////////////////// @@ -248,14 +248,6 @@ namespace olympia_mss sparta::UniqueEvent<> ev_handle_biu_l2cache_resp_ {&unit_event_set_, "ev_handle_biu_l2cache_resp", CREATE_SPARTA_HANDLER(L2Cache, handle_BIU_L2Cache_Resp_)}; - // Event to handle L2Cache ack for ICache - sparta::UniqueEvent<> ev_handle_l2cache_icache_ack_ - {&unit_event_set_, "ev_handle_l2cache_icache_ack", CREATE_SPARTA_HANDLER(L2Cache, handle_L2Cache_ICache_Ack_)}; - - // Event to handle L2Cache ack for DCache - sparta::UniqueEvent<> ev_handle_l2cache_dcache_ack_ - {&unit_event_set_, "ev_handle_l2cache_dcache_ack", CREATE_SPARTA_HANDLER(L2Cache, handle_L2Cache_DCache_Ack_)}; - // Event to create request for pipeline and feed it to the pipeline_req_queue_ sparta::UniqueEvent ev_create_req_ {&unit_event_set_, "create_req", CREATE_SPARTA_HANDLER(L2Cache, create_Req_)}; @@ -277,8 +269,8 @@ namespace olympia_mss // Receive BIU access Response void getRespFromBIU_(const olympia::MemoryAccessInfoPtr &); - // Receive BIU ack Response - void getAckFromBIU_(const uint32_t &); + // Receive BIU credits Response + void getCreditsFromBIU_(const uint32_t &); // Handle L2Cache request from DCache void handle_DCache_L2Cache_Req_(); @@ -289,18 +281,12 @@ namespace olympia_mss // Handle L2Cache request to BIU void handle_L2Cache_BIU_Req_(); - // Handle L2Cahe resp for ICache + // Handle L2Cache resp for ICache void handle_L2Cache_ICache_Resp_(); - // Handle L2Cahe resp for DCache + // Handle L2Cache resp for DCache void handle_L2Cache_DCache_Resp_(); - // Handle L2Cahe ack for ICache - void handle_L2Cache_ICache_Ack_(); - - // Handle L2Cahe ack for DCache - void handle_L2Cache_DCache_Ack_(); - // Handle BIU resp to L2Cache void handle_BIU_L2Cache_Resp_(); diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index f715dbd5..41d1472b 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -32,6 +32,7 @@ add_subdirectory(core/l2cache) add_subdirectory(core/rename) add_subdirectory(core/lsu) add_subdirectory(core/issue_queue) +add_subdirectory(core/icache) add_subdirectory(core/branch_pred) add_subdirectory(core/dcache) add_subdirectory(core/vector) diff --git a/test/core/dcache/Dcache_test.cpp b/test/core/dcache/Dcache_test.cpp index 42101d04..77a32d76 100644 --- a/test/core/dcache/Dcache_test.cpp +++ b/test/core/dcache/Dcache_test.cpp @@ -78,7 +78,7 @@ class DCacheSim : public sparta::app::Simulation sparta::bind(root_node->getChildAs("next_lvl.ports.out_biu_resp"), root_node->getChildAs("dcache.ports.in_l2cache_resp")); sparta::bind(root_node->getChildAs("next_lvl.ports.out_biu_ack"), - root_node->getChildAs("dcache.ports.in_l2cache_ack")); + root_node->getChildAs("dcache.ports.in_l2cache_credits")); } std::unique_ptr allocators_tn_; diff --git a/test/core/dcache/expected_output/arbitrate.out.EXPECTED b/test/core/dcache/expected_output/arbitrate.out.EXPECTED index 56419b63..fb2b71ae 100644 --- a/test/core/dcache/expected_output/arbitrate.out.EXPECTED +++ b/test/core/dcache/expected_output/arbitrate.out.EXPECTED @@ -3,70 +3,70 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:49:19 2024 -#Elapsed: 0.00278s -{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Requested -{0000000000 00000000 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000000 00000000 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +#Start: Saturday Sat Oct 19 15:35:23 2024 +#Elapsed: 0.002073s +{0000000000 00000000 top.lsu info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' Requested +{0000000000 00000000 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000000 00000000 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000001 00000001 top.dcache info} handleLookup_: Lookup stage -{0000000001 00000001 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in Lookup stage +{0000000001 00000001 top.dcache info} handleLookup_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in Lookup stage {0000000001 00000001 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeadbeef -{0000000001 00000001 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' performing lookup 0 -{0000000001 00000001 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000001 00000001 top.dcache info} handleLookup_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' performing lookup 0 +{0000000001 00000001 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000001 00000001 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeadbee0 -{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Received +{0000000001 00000001 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' Received {0000000001 00000001 top.dcache info} mshrRequest_: Send mshr req -{0000000001 00000001 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000002 00000002 top.next_lvl info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' sinked +{0000000001 00000001 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000002 00000002 top.next_lvl info} sinkInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' sinked {0000000002 00000002 top.dcache info} handleDataRead_: Data Read stage -{0000000002 00000002 top.dcache info} handleDataRead_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in read stage -{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' ' Received +{0000000002 00000002 top.dcache info} handleDataRead_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in read stage +{0000000002 00000002 top.lsu info} ReceiveAck_: Ack: 'memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' ' Received {0000000003 00000003 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000003 00000003 top.dcache info} handleDeallocate_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in deallocate stage -{0000000003 00000003 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000003 00000003 top.dcache info} handleDeallocate_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in deallocate stage +{0000000003 00000003 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000003 00000003 top.dcache info} mshrRequest_: Send mshr req -{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000007 00000007 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} receiveRespFromL2Cache_: Removing mshr entry for memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000007 00000007 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000008 00000008 top.dcache info} handleLookup_: Lookup stage -{0000000008 00000008 top.dcache info} handleLookup_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in Lookup stage -{0000000008 00000008 top.dcache info} handleLookup_: Incoming cache refill memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' -{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Requested -{0000000008 00000008 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000008 00000008 top.dcache info} handleLookup_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in Lookup stage +{0000000008 00000008 top.dcache info} handleLookup_: Incoming cache refill memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' +{0000000008 00000008 top.lsu info} req_inst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Requested +{0000000008 00000008 top.dcache info} receiveMemReqFromLSU_: Received memory access request from LSU memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000008 00000008 top.dcache info} mshrRequest_: Send mshr req -{0000000008 00000008 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000008 00000008 top.dcache info} arbitrateL2LsuReq_: Received LSU request memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000009 00000009 top.dcache info} handleLookup_: Lookup stage -{0000000009 00000009 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in Lookup stage +{0000000009 00000009 top.dcache info} handleLookup_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in Lookup stage {0000000009 00000009 top.dcache info} dataLookup_: DL1 DCache MISS: phyAddr=0xdeedbeef -{0000000009 00000009 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' performing lookup 0 -{0000000009 00000009 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000009 00000009 top.dcache info} handleLookup_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' performing lookup 0 +{0000000009 00000009 top.dcache info} handleLookup_: Creating new MSHR Entry memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000009 00000009 top.dcache info} handleLookup_: Load miss inst to LMQ; block address:0xdeedbee0 -{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000009 00000009 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Received {0000000009 00000009 top.dcache info} handleDataRead_: Data Read stage -{0000000009 00000009 top.dcache info} handleDataRead_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in read stage +{0000000009 00000009 top.dcache info} handleDataRead_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in read stage {0000000009 00000009 top.dcache info} reloadCache_: DCache reload complete! {0000000009 00000009 top.dcache info} mshrRequest_: Send mshr req -{0000000009 00000009 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' -{0000000010 00000010 top.next_lvl info} sinkInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' sinked +{0000000009 00000009 top.dcache info} mshrRequest_: Sending mshr request when not busy memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' +{0000000010 00000010 top.next_lvl info} sinkInst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' sinked {0000000010 00000010 top.dcache info} handleDataRead_: Data Read stage -{0000000010 00000010 top.dcache info} handleDataRead_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in read stage -{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDataRead_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in read stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Received {0000000010 00000010 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000010 00000010 top.dcache info} handleDeallocate_: memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' in deallocate stage -{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' ' Received -{0000000010 00000010 top.dcache info} handleDeallocate_: Removing mshr entry for memptr: uid:0 FETCHED 0 pid:1 uopid:0 'lw 5,3' +{0000000010 00000010 top.dcache info} handleDeallocate_: memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' in deallocate stage +{0000000010 00000010 top.lsu info} ReceiveAck_: Ack: 'memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' ' Received +{0000000010 00000010 top.dcache info} handleDeallocate_: Removing mshr entry for memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'lw 5,3' {0000000011 00000011 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000011 00000011 top.dcache info} handleDeallocate_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in deallocate stage -{0000000011 00000011 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000011 00000011 top.dcache info} handleDeallocate_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in deallocate stage +{0000000011 00000011 top.dcache info} handleDeallocate_: Deallocating pipeline for memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000011 00000011 top.dcache info} mshrRequest_: Send mshr req -{0000000015 00000015 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' -{0000000015 00000015 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000015 00000015 top.dcache info} receiveRespFromL2Cache_: Received cache refill memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' +{0000000015 00000015 top.dcache info} arbitrateL2LsuReq_: Received Refill request memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000016 00000016 top.dcache info} handleLookup_: Lookup stage -{0000000016 00000016 top.dcache info} handleLookup_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in Lookup stage -{0000000016 00000016 top.dcache info} handleLookup_: Incoming cache refill memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' +{0000000016 00000016 top.dcache info} handleLookup_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in Lookup stage +{0000000016 00000016 top.dcache info} handleLookup_: Incoming cache refill memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' {0000000016 00000016 top.dcache info} mshrRequest_: Send mshr req {0000000017 00000017 top.dcache info} handleDataRead_: Data Read stage -{0000000017 00000017 top.dcache info} handleDataRead_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in read stage +{0000000017 00000017 top.dcache info} handleDataRead_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in read stage {0000000017 00000017 top.dcache info} reloadCache_: DCache reload complete! {0000000018 00000018 top.dcache info} handleDeallocate_: Data Dellocate stage -{0000000018 00000018 top.dcache info} handleDeallocate_: memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3' in deallocate stage +{0000000018 00000018 top.dcache info} handleDeallocate_: memptr: deedbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3' in deallocate stage diff --git a/test/core/dispatch/expected_output/big_core.out.EXPECTED b/test/core/dispatch/expected_output/big_core.out.EXPECTED index b54f664a..b6b0ad67 100644 --- a/test/core/dispatch/expected_output/big_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:46:24 2024 -#Elapsed: 0.00175s +#Start: Saturday Sat Oct 19 16:01:55 2024 +#Elapsed: 0.001359s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,18 +51,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -70,182 +70,182 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq2 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq2: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq2 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer -{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq2 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq2: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq2 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000004 00000004 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq2 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq2: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq2 of target type: INT {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer -{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000005 00000005 top.execute.iq2 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe2 -{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe2 +{0000000005 00000005 top.execute.exe2 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 4 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add, 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add, 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000006 00000006 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe4 -{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 +{0000000006 00000006 top.execute.exe2 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.exe2 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe4 +{0000000007 00000007 top.execute.exe4 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe4 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.exe4 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe2 -{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe2 +{0000000011 00000011 top.execute.exe2 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' -{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe4 -{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe2 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe2 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe4 +{0000000013 00000013 top.execute.exe4 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 7 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' -{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe4 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe4 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe2 -{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe2 +{0000000017 00000017 top.execute.exe2 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' -{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe4 -{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe2 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe2 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq2 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe4 +{0000000019 00000019 top.execute.exe4 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq2 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' -{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe4 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe4 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/medium_core.out.EXPECTED b/test/core/dispatch/expected_output/medium_core.out.EXPECTED index b999934f..617d2ed0 100644 --- a/test/core/dispatch/expected_output/medium_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:46:24 2024 -#Elapsed: 0.001696s +#Start: Saturday Sat Oct 19 16:01:55 2024 +#Elapsed: 0.001281s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -44,18 +44,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -63,191 +63,191 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq1: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq1 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' -{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq1 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq1: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq1 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer -{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000004 00000004 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq1 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq1 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 4 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add, 0x00000000 UID(23) PID(0) add, 0x00000000 UID(24) PID(0) add, 0x00000000 UID(25) PID(0) add -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer -{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000005 00000005 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add, 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe1 -{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe1 +{0000000005 00000005 top.execute.exe1 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} acceptInst: iq1: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq1 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 2 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add, 0x00000000 UID(27) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer -{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000006 00000006 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000006 00000006 top.execute.exe1 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq1 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} acceptInst: iq1: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq1 of target type: INT {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 2 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add, 0x00000000 UID(29) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer -{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000007 00000007 top.execute.iq1 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe1 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000007 00000007 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe1 -{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe1 +{0000000009 00000009 top.execute.exe1 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 +{0000000010 00000010 top.execute.exe1 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.exe1 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000011 00000011 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe1 -{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe1 +{0000000013 00000013 top.execute.exe1 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 6 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' -{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe1 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe1 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe1 -{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe1 +{0000000017 00000017 top.execute.exe1 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 7 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' -{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe1 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe1 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe1 -{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq1 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe1 +{0000000021 00000021 top.execute.exe1 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq1 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' -{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' +{0000000022 00000022 top.execute.exe1 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe1 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/dispatch/expected_output/small_core.out.EXPECTED b/test/core/dispatch/expected_output/small_core.out.EXPECTED index c5889fc6..f1f7eb08 100644 --- a/test/core/dispatch/expected_output/small_core.out.EXPECTED +++ b/test/core/dispatch/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:46:24 2024 -#Elapsed: 0.002685s +#Start: Saturday Sat Oct 19 16:01:55 2024 +#Elapsed: 0.001895s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -38,18 +38,18 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add, 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add, 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [0,3] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [5,32] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [7,33] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard @@ -57,218 +57,218 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add, 0x00000000 UID(12) PID(0) add, 0x00000000 UID(13) PID(0) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(0) add, 0x00000000 UID(1) PID(0) add, 0x00000000 UID(2) PID(0) add, 0x00000000 UID(3) PID(0) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' stall: INT_BUSY +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' stall: INT_BUSY {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [9,34] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [35] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [11,35] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [36] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [13,36] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [37] for 'integer' scoreboard -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [15,37] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [38] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 4 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(14) PID(0) add, 0x00000000 UID(15) PID(0) add, 0x00000000 UID(16) PID(0) add, 0x00000000 UID(17) PID(0) add -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(4) PID(0) add, 0x00000000 UID(5) PID(0) add, 0x00000000 UID(6) PID(0) add, 0x00000000 UID(7) PID(0) add -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:0 uopid:0 'add 2,0,1' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq0 of target type: INT -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' stall: INT_BUSY {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [17,38] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [39] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [19,39] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [40] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:10 RENAMED 0 pid:0 uopid:0 'add 22,20,21' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [21,40] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [41] for 'integer' scoreboard -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:11 RENAMED 0 pid:0 uopid:0 'add 24,22,23' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [23,41] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [42] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 4 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(18) PID(0) add, 0x00000000 UID(19) PID(0) add, 0x00000000 UID(20) PID(0) add, 0x00000000 UID(21) PID(0) add -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' Bits needed:[0,3] rf: integer {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(8) PID(0) add, 0x00000000 UID(9) PID(0) add, 0x00000000 UID(10) PID(0) add, 0x00000000 UID(11) PID(0) add -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:0 uopid:0 'add 2,0,1' {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' stall: INT_BUSY +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to iq0 of target type: INT +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' stall: INT_BUSY {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:12 RENAMED 0 pid:0 uopid:0 'add 26,24,25' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [25,42] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [43] for 'integer' scoreboard {0000000004 00000004 top.decode info} inCredits: Got credits from dut: 1 {0000000004 00000004 top.decode info} Sending group: 0x00000000 UID(22) PID(0) add -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' -{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' +{0000000005 00000005 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' Bits needed:[5,32] rf: integer {0000000005 00000005 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(12) PID(0) add -{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' -{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:1DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe0 -{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 +{0000000005 00000005 top.execute.exe0 info} completeInst_: Completing inst: uid:0 COMPLETED 0 pid:0 uopid:0 'add 2,0,1' +{0000000005 00000005 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:1 DISPATCHED 0 pid:0 uopid:0 'add 4,2,3' to exe_pipe exe0 +{0000000005 00000005 top.execute.exe0 info} insertInst: Executing: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' for 6 {0000000005 00000005 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000005 00000005 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT -{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY +{0000000005 00000005 top.dispatch info} acceptInst: iq0: dispatching uid:3 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Sending instruction: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to iq0 of target type: INT +{0000000005 00000005 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' stall: INT_BUSY {0000000005 00000005 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' +{0000000005 00000005 top.rename info} renameInstructions_: sending inst to dispatch: uid:13 RENAMED 0 pid:0 uopid:0 'add 28,26,27' {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup source register bit mask [27,43] for 'integer' scoreboard {0000000005 00000005 top.rename info} renameInstructions_: setup destination register bit mask [44] for 'integer' scoreboard {0000000005 00000005 top.decode info} inCredits: Got credits from dut: 1 {0000000005 00000005 top.decode info} Sending group: 0x00000000 UID(23) PID(0) add -{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer +{0000000006 00000006 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' Bits needed:[7,33] rf: integer {0000000006 00000006 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(13) PID(0) add -{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' +{0000000006 00000006 top.execute.exe0 info} executeInst_: Executed inst: uid:1 SCHEDULED 0 pid:0 uopid:0 'add 4,2,3' {0000000006 00000006 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT -{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' stall: INT_BUSY +{0000000006 00000006 top.dispatch info} acceptInst: iq0: dispatching uid:4 RENAMED 0 pid:0 uopid:0 'add 10,8,9' +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Sending instruction: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to iq0 of target type: INT +{0000000006 00000006 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' stall: INT_BUSY {0000000006 00000006 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' +{0000000006 00000006 top.rename info} renameInstructions_: sending inst to dispatch: uid:14 RENAMED 0 pid:0 uopid:0 'add 30,28,29' {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup source register bit mask [29,44] for 'integer' scoreboard {0000000006 00000006 top.rename info} renameInstructions_: setup destination register bit mask [45] for 'integer' scoreboard {0000000006 00000006 top.decode info} inCredits: Got credits from dut: 1 {0000000006 00000006 top.decode info} Sending group: 0x00000000 UID(24) PID(0) add -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' -{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' +{0000000007 00000007 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' Bits needed:[9,34] rf: integer {0000000007 00000007 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(14) PID(0) add -{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' -{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 -{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 +{0000000007 00000007 top.execute.exe0 info} completeInst_: Completing inst: uid:1 COMPLETED 0 pid:0 uopid:0 'add 4,2,3' +{0000000007 00000007 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:2 DISPATCHED 0 pid:0 uopid:0 'add 6,4,5' to exe_pipe exe0 +{0000000007 00000007 top.execute.exe0 info} insertInst: Executing: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' for 8 {0000000007 00000007 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000007 00000007 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq0 of target type: INT -{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY +{0000000007 00000007 top.dispatch info} acceptInst: iq0: dispatching uid:5 RENAMED 0 pid:0 uopid:0 'add 12,10,11' +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Sending instruction: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to iq0 of target type: INT +{0000000007 00000007 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' stall: INT_BUSY {0000000007 00000007 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' +{0000000007 00000007 top.rename info} renameInstructions_: sending inst to dispatch: uid:15 RENAMED 0 pid:0 uopid:0 'add 0,30,31' {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [45] for 'integer' scoreboard {0000000007 00000007 top.rename info} renameInstructions_: setup source register bit mask [31,45] for 'integer' scoreboard {0000000007 00000007 top.decode info} inCredits: Got credits from dut: 1 {0000000007 00000007 top.decode info} Sending group: 0x00000000 UID(25) PID(0) add -{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer +{0000000008 00000008 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' Bits needed:[11,35] rf: integer {0000000008 00000008 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(15) PID(0) add -{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' +{0000000008 00000008 top.execute.exe0 info} executeInst_: Executed inst: uid:2 SCHEDULED 0 pid:0 uopid:0 'add 6,4,5' {0000000008 00000008 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT -{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' stall: INT_BUSY +{0000000008 00000008 top.dispatch info} acceptInst: iq0: dispatching uid:6 RENAMED 0 pid:0 uopid:0 'add 14,12,13' +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Sending instruction: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to iq0 of target type: INT +{0000000008 00000008 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' stall: INT_BUSY {0000000008 00000008 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' +{0000000008 00000008 top.rename info} renameInstructions_: sending inst to dispatch: uid:16 RENAMED 0 pid:0 uopid:0 'add 2,0,1' {0000000008 00000008 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000008 00000008 top.rename info} renameInstructions_: setup destination register bit mask [46] for 'integer' scoreboard {0000000008 00000008 top.decode info} inCredits: Got credits from dut: 1 {0000000008 00000008 top.decode info} Sending group: 0x00000000 UID(26) PID(0) add -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' -{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' +{0000000009 00000009 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' Bits needed:[13,36] rf: integer {0000000009 00000009 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(16) PID(0) add -{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' -{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 -{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 +{0000000009 00000009 top.execute.exe0 info} completeInst_: Completing inst: uid:2 COMPLETED 0 pid:0 uopid:0 'add 6,4,5' +{0000000009 00000009 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:3 DISPATCHED 0 pid:0 uopid:0 'add 8,6,7' to exe_pipe exe0 +{0000000009 00000009 top.execute.exe0 info} insertInst: Executing: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' for 10 {0000000009 00000009 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000009 00000009 top.dispatch info} dispatchInstructions_: Num to dispatch: 3 -{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq0 of target type: INT -{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY +{0000000009 00000009 top.dispatch info} acceptInst: iq0: dispatching uid:7 RENAMED 0 pid:0 uopid:0 'add 16,14,15' +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Sending instruction: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to iq0 of target type: INT +{0000000009 00000009 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' stall: INT_BUSY {0000000009 00000009 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' +{0000000009 00000009 top.rename info} renameInstructions_: sending inst to dispatch: uid:17 RENAMED 0 pid:0 uopid:0 'add 4,2,3' {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup source register bit mask [3,46] for 'integer' scoreboard {0000000009 00000009 top.rename info} renameInstructions_: setup destination register bit mask [47] for 'integer' scoreboard {0000000009 00000009 top.decode info} inCredits: Got credits from dut: 1 {0000000009 00000009 top.decode info} Sending group: 0x00000000 UID(27) PID(0) add -{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer +{0000000010 00000010 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' Bits needed:[15,37] rf: integer {0000000010 00000010 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(17) PID(0) add -{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' +{0000000010 00000010 top.execute.exe0 info} executeInst_: Executed inst: uid:3 SCHEDULED 0 pid:0 uopid:0 'add 8,6,7' {0000000010 00000010 top.dispatch info} dispatchInstructions_: Num to dispatch: 2 -{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT -{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' stall: INT_BUSY +{0000000010 00000010 top.dispatch info} acceptInst: iq0: dispatching uid:8 RENAMED 0 pid:0 uopid:0 'add 18,16,17' +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Sending instruction: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to iq0 of target type: INT +{0000000010 00000010 top.dispatch info} dispatchInstructions_: Could not dispatch: uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' stall: INT_BUSY {0000000010 00000010 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' +{0000000010 00000010 top.rename info} renameInstructions_: sending inst to dispatch: uid:18 RENAMED 0 pid:0 uopid:0 'add 6,4,5' {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup source register bit mask [5,47] for 'integer' scoreboard {0000000010 00000010 top.rename info} renameInstructions_: setup destination register bit mask [48] for 'integer' scoreboard {0000000010 00000010 top.decode info} inCredits: Got credits from dut: 1 {0000000010 00000010 top.decode info} Sending group: 0x00000000 UID(28) PID(0) add -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' -{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' +{0000000011 00000011 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' Bits needed:[17,38] rf: integer {0000000011 00000011 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(18) PID(0) add -{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' -{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 -{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 +{0000000011 00000011 top.execute.exe0 info} completeInst_: Completing inst: uid:3 COMPLETED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:4 DISPATCHED 0 pid:0 uopid:0 'add 10,8,9' to exe_pipe exe0 +{0000000011 00000011 top.execute.exe0 info} insertInst: Executing: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' for 12 {0000000011 00000011 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000011 00000011 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' -{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT +{0000000011 00000011 top.dispatch info} acceptInst: iq0: dispatching uid:9 RENAMED 0 pid:0 uopid:0 'add 20,18,19' +{0000000011 00000011 top.dispatch info} dispatchInstructions_: Sending instruction: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to iq0 of target type: INT {0000000011 00000011 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' +{0000000011 00000011 top.rename info} renameInstructions_: sending inst to dispatch: uid:19 RENAMED 0 pid:0 uopid:0 'add 8,6,7' {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup source register bit mask [7,48] for 'integer' scoreboard {0000000011 00000011 top.rename info} renameInstructions_: setup destination register bit mask [49] for 'integer' scoreboard {0000000011 00000011 top.decode info} inCredits: Got credits from dut: 1 {0000000011 00000011 top.decode info} Sending group: 0x00000000 UID(29) PID(0) add -{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer +{0000000012 00000012 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' Bits needed:[19,39] rf: integer {0000000012 00000012 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(19) PID(0) add {0000000012 00000012 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' -{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' -{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:5DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe0 -{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 +{0000000012 00000012 top.execute.exe0 info} executeInst_: Executed inst: uid:4 SCHEDULED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' +{0000000013 00000013 top.execute.exe0 info} completeInst_: Completing inst: uid:4 COMPLETED 0 pid:0 uopid:0 'add 10,8,9' +{0000000013 00000013 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:5 DISPATCHED 0 pid:0 uopid:0 'add 12,10,11' to exe_pipe exe0 +{0000000013 00000013 top.execute.exe0 info} insertInst: Executing: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' for 14 {0000000013 00000013 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 4 {0000000013 00000013 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' -{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' -{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 -{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 +{0000000014 00000014 top.execute.exe0 info} executeInst_: Executed inst: uid:5 SCHEDULED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' +{0000000015 00000015 top.execute.exe0 info} completeInst_: Completing inst: uid:5 COMPLETED 0 pid:0 uopid:0 'add 12,10,11' +{0000000015 00000015 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:6 DISPATCHED 0 pid:0 uopid:0 'add 14,12,13' to exe_pipe exe0 +{0000000015 00000015 top.execute.exe0 info} insertInst: Executing: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' for 16 {0000000015 00000015 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 5 {0000000015 00000015 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' -{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' -{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:7DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe0 -{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 +{0000000016 00000016 top.execute.exe0 info} executeInst_: Executed inst: uid:6 SCHEDULED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' +{0000000017 00000017 top.execute.exe0 info} completeInst_: Completing inst: uid:6 COMPLETED 0 pid:0 uopid:0 'add 14,12,13' +{0000000017 00000017 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:7 DISPATCHED 0 pid:0 uopid:0 'add 16,14,15' to exe_pipe exe0 +{0000000017 00000017 top.execute.exe0 info} insertInst: Executing: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' for 18 {0000000017 00000017 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 6 {0000000017 00000017 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' -{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' -{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 -{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 +{0000000018 00000018 top.execute.exe0 info} executeInst_: Executed inst: uid:7 SCHEDULED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' +{0000000019 00000019 top.execute.exe0 info} completeInst_: Completing inst: uid:7 COMPLETED 0 pid:0 uopid:0 'add 16,14,15' +{0000000019 00000019 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:8 DISPATCHED 0 pid:0 uopid:0 'add 18,16,17' to exe_pipe exe0 +{0000000019 00000019 top.execute.exe0 info} insertInst: Executing: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' for 20 {0000000019 00000019 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 7 {0000000019 00000019 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' -{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' -{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 -{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 +{0000000020 00000020 top.execute.exe0 info} executeInst_: Executed inst: uid:8 SCHEDULED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' +{0000000021 00000021 top.execute.exe0 info} completeInst_: Completing inst: uid:8 COMPLETED 0 pid:0 uopid:0 'add 18,16,17' +{0000000021 00000021 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:9 DISPATCHED 0 pid:0 uopid:0 'add 20,18,19' to exe_pipe exe0 +{0000000021 00000021 top.execute.exe0 info} insertInst: Executing: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' for 22 {0000000021 00000021 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000021 00000021 top.dispatch info} scheduleDispatchSession: no rob credits or no instructions to process -{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' -{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' +{0000000022 00000022 top.execute.exe0 info} executeInst_: Executed inst: uid:9 SCHEDULED 0 pid:0 uopid:0 'add 20,18,19' +{0000000023 00000023 top.execute.exe0 info} completeInst_: Completing inst: uid:9 COMPLETED 0 pid:0 uopid:0 'add 20,18,19' diff --git a/test/core/icache/CMakeLists.txt b/test/core/icache/CMakeLists.txt new file mode 100644 index 00000000..0e3acda2 --- /dev/null +++ b/test/core/icache/CMakeLists.txt @@ -0,0 +1,8 @@ +project(ICache_test) + +add_executable(ICache_test ICache_test.cpp) +target_link_libraries(ICache_test core common_test mss mavis SPARTA::sparta) + +sparta_named_test(ICache_test_single_access ICache_test --testname single_access --seed 1) +sparta_named_test(ICache_test_simple ICache_test --testname simple --seed 1) +sparta_named_test(ICache_test_random ICache_test --testname random --seed 1 -p top.sink.params.miss_rate 100) diff --git a/test/core/icache/ICacheChecker.hpp b/test/core/icache/ICacheChecker.hpp new file mode 100644 index 00000000..4019bbb8 --- /dev/null +++ b/test/core/icache/ICacheChecker.hpp @@ -0,0 +1,192 @@ +#pragma once + + +#include "core/MemoryAccessInfo.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/events/SingleCycleUniqueEvent.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/LogUtils.hpp" +#include "ICache.hpp" + +#include +#include +#include + +// Basically just a way of getting to the address decoder so that the checker can +// calculate set index or block addresses +class olympia::ICacheTester +{ +public: + void setDUT(olympia::ICache *dut) { dut_ = dut; } + + uint64_t getSetIdx(uint64_t addr) + { + auto decoder = dut_->l1_cache_->getAddrDecoder(); + return decoder->calcIdx(addr); + } + + uint64_t getTag(uint64_t addr) + { + auto decoder = dut_->l1_cache_->getAddrDecoder(); + return decoder->calcTag(addr); + } + + uint64_t getBlockAddress(uint64_t addr) + { + auto decoder = dut_->l1_cache_->getAddrDecoder(); + return decoder->calcBlockAddr(addr); + } + + uint32_t getNumWays() + { + return dut_->l1_cache_->getNumWays(); + } + +private: + olympia::ICache * dut_ = nullptr; +}; + +namespace icache_test +{ + class ICacheChecker : public sparta::Unit, public olympia::ICacheTester + { + public: + static constexpr char name[] = "instruction cache checker"; + + using ICacheCheckerParameters = sparta::ParameterSet; + ICacheChecker(sparta::TreeNode * node, const ICacheCheckerParameters *p) : sparta::Unit(node) + { + + in_fetch_req_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getRequestFromFetch_, olympia::MemoryAccessInfoPtr)); + in_fetch_resp_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getResponseToFetch_, olympia::MemoryAccessInfoPtr)); + in_l2cache_req_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getRequestToL2Cache_, olympia::MemoryAccessInfoPtr)); + in_l2cache_resp_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(ICacheChecker, getResponseFromL2Cache_, olympia::MemoryAccessInfoPtr)); + } + + uint32_t getICacheHitCount() const { return icache_hits_;} + uint32_t getICacheMissCount() const { return icache_misses_;} + uint32_t getL2CacheHitCount() const { return l2cache_hits_;} + uint32_t getL2CacheMissCount() const { return l2cache_misses_;} + + private: + + void getRequestFromFetch_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + fetch_pending_queue_.push_back(mem_access_info_ptr); + } + + void getResponseToFetch_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Should only be a HIT or MISS response + const auto cache_state = mem_access_info_ptr->getCacheState(); + if (cache_state != olympia::MemoryAccessInfo::CacheState::HIT) { + sparta_assert(cache_state == olympia::MemoryAccessInfo::CacheState::MISS); + } + + // Search for the original request + const auto fetch_req = std::find(fetch_pending_queue_.begin(), fetch_pending_queue_.end(), mem_access_info_ptr); + sparta_assert(fetch_req != fetch_pending_queue_.end(), "response received without a corresponding request"); + + auto tag = getTag(mem_access_info_ptr->getPhyAddr()); + auto set = getSetIdx(mem_access_info_ptr->getPhyAddr()); + + if (cache_state == olympia::MemoryAccessInfo::CacheState::HIT) { + auto block = getBlockAddress(mem_access_info_ptr->getPhyAddr()); + + // Check that we don't have an outstanding L2 request on this block + sparta_assert(pending_l2cache_reqs_.count(block) == 0); + + // Check that we've filled this block at least once.. + sparta_assert(filled_blocks_.count(block)); + + // Track the last tag to hit on this set + last_access_tracker_[set] = tag; + + ILOG("removing fetch request") + fetch_pending_queue_.erase(fetch_req); + + ++icache_hits_; + } + else { + // We cannot miss if we hit on this set last time with this tag + if (auto itr = last_access_tracker_.find(set); itr != last_access_tracker_.end()) { + sparta_assert(itr->second != tag); + } + + ++icache_misses_; + } + } + + void getRequestToL2Cache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + + auto block = getBlockAddress(mem_access_info_ptr->getPhyAddr()); + auto matches_block = [this, block](auto req) { return block == getBlockAddress(req->getPhyAddr()); }; + + // Check that fetch has tried to request this address + const auto fetch_req = std::find_if(fetch_pending_queue_.begin(), fetch_pending_queue_.end(), matches_block); + sparta_assert(fetch_req != fetch_pending_queue_.end(), "response received without a corresponding request"); + + // Check that we don't have another l2cache request inflight for the same block + sparta_assert(pending_l2cache_reqs_.count(block) == 0); + pending_l2cache_reqs_.insert(block); + } + + void getResponseFromL2Cache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + if (mem_access_info_ptr->getCacheState() == olympia::MemoryAccessInfo::CacheState::HIT) { + auto block = getBlockAddress(mem_access_info_ptr->getPhyAddr()); + + // Flag that we've filled this block atleast once + filled_blocks_.insert(block); + + // Shouldn't have received a response if we didn't request it? + sparta_assert(pending_l2cache_reqs_.erase(block)); + + ++l2cache_hits_; + } + else { + ++l2cache_misses_; + } + } + + void onStartingTeardown_() override final + { + sparta_assert(fetch_pending_queue_.empty()); + sparta_assert(pending_l2cache_reqs_.size() == 0); + } + + //////////////////////////////////////////////////////////////////////////////// + // Variables + //////////////////////////////////////////////////////////////////////////////// + + uint32_t icache_hits_ = 0; + uint32_t icache_misses_ = 0; + uint32_t l2cache_hits_ = 0; + uint32_t l2cache_misses_ = 0; + + // Track pending fetch requests + std::vector fetch_pending_queue_; + + // Track pending l2cache reqs - icache shouldn't request them again, and fetch cannot hit on them + std::set pending_l2cache_reqs_; + + // Track blocks which have been filled atleast once - fetch cannot hit on them until they're filled + std::set filled_blocks_; + + // Track the tags of the last hits on each set - fetch cannot miss on them + std::map last_access_tracker_; + + //////////////////////////////////////////////////////////////////////////////// + // Input Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataInPort in_fetch_req_ {&unit_port_set_, "in_fetch_req", 1}; + sparta::DataInPort in_fetch_resp_ {&unit_port_set_, "in_fetch_resp", 1}; + sparta::DataInPort in_l2cache_req_ {&unit_port_set_, "in_l2cache_req", 1}; + sparta::DataInPort in_l2cache_resp_ {&unit_port_set_, "in_l2cache_resp", 1}; + }; +} \ No newline at end of file diff --git a/test/core/icache/ICacheSink.hpp b/test/core/icache/ICacheSink.hpp new file mode 100644 index 00000000..a7264d4c --- /dev/null +++ b/test/core/icache/ICacheSink.hpp @@ -0,0 +1,155 @@ +// ICacheSink.hpp +#pragma once + +#include "core/MemoryAccessInfo.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/ports/DataPort.hpp" +#include "sparta/events/SingleCycleUniqueEvent.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/LogUtils.hpp" + + +namespace icache_test +{ + class ICacheSink : public sparta::Unit + { + public: + static constexpr char name[] = "icache_sink_unit"; + + class ICacheSinkParameters : public sparta::ParameterSet + { + public: + ICacheSinkParameters(sparta::TreeNode *n) : sparta::ParameterSet(n) + {} + PARAMETER(double, miss_rate, 0, "miss rate per 1k requests") + PARAMETER(uint32_t, latency, 8, "hit latency") + PARAMETER(uint32_t, miss_penalty, 32, "miss latency") + + }; + + struct ICacheResponse { + uint64_t scheduled_time; + olympia::MemoryAccessInfo::CacheState hit_state; + olympia::MemoryAccessInfoPtr access; + }; + + + ICacheSink(sparta::TreeNode *n, const ICacheSinkParameters *params) : + sparta::Unit(n), + latency_(params->latency), + miss_penalty_(params->miss_penalty), + miss_distribution_({1000, params->miss_rate}), + gen_(1) + { + in_icache_req_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ICacheSink, getRequestFromICache_, olympia::MemoryAccessInfoPtr)); + + sparta::StartupEvent(n, CREATE_SPARTA_HANDLER(ICacheSink, sendInitialCredits_)); + ev_respond_.setContinuing(true); + + } + + void setRandomSeed(uint32_t seed) + { + gen_.seed(seed); + } + + + private: + + //////////////////////////////////////////////////////////////////////////////// + // Methods + //////////////////////////////////////////////////////////////////////////////// + + void sendInitialCredits_() + { + out_icache_credit_.send(8); + } + + void getRequestFromICache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Hit's are removed from the pending queue + // Misses are retained. + // Randomly choose to miss, and also randomly generate a latency + ILOG("received request " << mem_access_info_ptr); + ICacheResponse resp; + resp.access = mem_access_info_ptr; + resp.scheduled_time = getClock()->currentCycle() + latency_; + if (miss_distribution_(gen_)) { + resp.hit_state = olympia::MemoryAccessInfo::CacheState::MISS; + } + else { + resp.hit_state = olympia::MemoryAccessInfo::CacheState::HIT; + } + response_queue_.emplace_back(resp); + // mem_access_info_ptr->setCacheState(olympia::MemoryAccessInfo::CacheState::HIT); + // ev_respond_.preparePayload(mem_access_info_ptr)->schedule(10); + ev_respond_.schedule(latency_); + out_icache_credit_.send(1); + } + + void sendResponse_() + { + // Find first response that's ready + auto response_ready = [this](ICacheResponse resp){ + return resp.scheduled_time <= getClock()->currentCycle(); + }; + auto resp_iter = std::find_if(response_queue_.begin(), response_queue_.end(), response_ready); + if (resp_iter == response_queue_.end()) { + ev_respond_.schedule(1); + return; + } + + ILOG("sending response " << resp_iter->access); + out_icache_resp_.send(resp_iter->access); + + // Replay the miss later + resp_iter->access->setCacheState(resp_iter->hit_state); + if (resp_iter->hit_state == olympia::MemoryAccessInfo::CacheState::MISS) { + resp_iter->hit_state = olympia::MemoryAccessInfo::CacheState::HIT; + resp_iter->scheduled_time = getClock()->currentCycle() + miss_penalty_; + ev_respond_.schedule(1); + } + else { + response_queue_.erase(resp_iter); + } + } + + void onStartingTeardown_() override final + { + sparta_assert(response_queue_.empty()); + } + + + //////////////////////////////////////////////////////////////////////////////// + // Variables + //////////////////////////////////////////////////////////////////////////////// + + const uint32_t latency_; + const uint32_t miss_penalty_; + + std::vector response_queue_; + + std::discrete_distribution<> miss_distribution_; + std::mt19937 gen_; + + //////////////////////////////////////////////////////////////////////////////// + // Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataInPort in_icache_req_{&unit_port_set_, + "in_icache_req", 0}; + + sparta::DataOutPort out_icache_resp_{&unit_port_set_, + "out_icache_resp", 0}; + + sparta::DataOutPort out_icache_credit_{&unit_port_set_, + "out_icache_credit", 0}; + + //////////////////////////////////////////////////////////////////////////////// + // Events + //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> ev_respond_{ + &unit_event_set_, "ev_respond", + CREATE_SPARTA_HANDLER(ICacheSink, sendResponse_)}; + }; +} \ No newline at end of file diff --git a/test/core/icache/ICacheSource.hpp b/test/core/icache/ICacheSource.hpp new file mode 100644 index 00000000..9afc7dd0 --- /dev/null +++ b/test/core/icache/ICacheSource.hpp @@ -0,0 +1,121 @@ +// Source for ICache +#pragma once + +#include "core/MemoryAccessInfo.hpp" +#include "sparta/simulation/TreeNode.hpp" +#include "sparta/ports/DataPort.hpp" +#include "sparta/events/SingleCycleUniqueEvent.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/LogUtils.hpp" + +#include "OlympiaAllocators.hpp" + +namespace icache_test +{ + class ICacheSource : public sparta::Unit + { + public: + static constexpr char name[] = "icache_source_unit"; + + class ICacheSourceParameters : public sparta::ParameterSet + { + public: + ICacheSourceParameters(sparta::TreeNode *n) : sparta::ParameterSet(n) + {} + }; + + ICacheSource(sparta::TreeNode *n, const ICacheSourceParameters *params) : + sparta::Unit(n), + memory_access_allocator_( + sparta::notNull(olympia::OlympiaAllocators::getOlympiaAllocators(n))-> + memory_access_allocator) + { + in_icache_resp_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ICacheSource, getResponseFromICache_, olympia::MemoryAccessInfoPtr)); + in_icache_credit_.registerConsumerHandler( + CREATE_SPARTA_HANDLER_WITH_DATA(ICacheSource, getCreditFromICache_, uint32_t)); + } + + // Queue up an ICache request for the address given + void queueRequest(const uint64_t & addr) + { + request_queue_.emplace_back(addr); + ev_send_requests_.schedule(sparta::Clock::Cycle(1)); + } + + + private: + + //////////////////////////////////////////////////////////////////////////////// + // Methods + //////////////////////////////////////////////////////////////////////////////// + + void sendRequests_() + { + if (!request_queue_.empty()) { + if (icache_credits_ > 0) { + auto addr = request_queue_.front(); + auto memory_access_info_ptr = + sparta::allocate_sparta_shared_pointer( + memory_access_allocator_, addr); + ILOG("sending " << memory_access_info_ptr); + out_icache_req_.send(memory_access_info_ptr); + icache_credits_--; + request_queue_.pop_front(); + ++outstanding_reqs_; + } + ev_send_requests_.schedule(1); + } + } + + void getResponseFromICache_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) + { + // Hit's are removed from the pending queue + // Misses are retained. + ILOG("received response " << mem_access_info_ptr); + if (mem_access_info_ptr->getCacheState() == olympia::MemoryAccessInfo::CacheState::HIT) { + --outstanding_reqs_; + } + } + + void getCreditFromICache_(const uint32_t & credits) + { + icache_credits_ += credits; + } + + void onStartingTeardown_() override final + { + sparta_assert(outstanding_reqs_ == 0); + } + + + //////////////////////////////////////////////////////////////////////////////// + // Variables + //////////////////////////////////////////////////////////////////////////////// + + olympia::MemoryAccessInfoAllocator & memory_access_allocator_; + uint32_t icache_credits_ = 0; + std::deque request_queue_; + + uint32_t outstanding_reqs_ = 0; + + //////////////////////////////////////////////////////////////////////////////// + // Ports + //////////////////////////////////////////////////////////////////////////////// + sparta::DataOutPort out_icache_req_{&unit_port_set_, + "out_icache_req", 0}; + + sparta::DataInPort in_icache_resp_{&unit_port_set_, + "in_icache_resp", 0}; + + sparta::DataInPort in_icache_credit_{&unit_port_set_, + "in_icache_credit", 0}; + + //////////////////////////////////////////////////////////////////////////////// + // Events + //////////////////////////////////////////////////////////////////////////////// + sparta::UniqueEvent<> ev_send_requests_{&unit_event_set_, "ev_send_requests", + CREATE_SPARTA_HANDLER(ICacheSource, sendRequests_)}; + + }; +} \ No newline at end of file diff --git a/test/core/icache/ICache_test.cpp b/test/core/icache/ICache_test.cpp new file mode 100644 index 00000000..790fe3df --- /dev/null +++ b/test/core/icache/ICache_test.cpp @@ -0,0 +1,185 @@ +// ICache test + +#include "sparta/sparta.hpp" +#include "sparta/app/Simulation.hpp" +#include "sparta/app/CommandLineSimulator.hpp" +#include "sparta/simulation/ClockManager.hpp" +#include "sparta/kernel/Scheduler.hpp" +#include "sparta/utils/SpartaTester.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" +#include "sparta/utils/SpartaTester.hpp" + +#include "test/core/icache/ICacheSink.hpp" +#include "test/core/icache/ICacheSource.hpp" +#include "test/core/icache/ICacheChecker.hpp" + +#include "ICache.hpp" +#include "OlympiaAllocators.hpp" + +#include + +class ICacheSim : public sparta::app::Simulation{ +public: + ICacheSim(sparta::Scheduler *sched) : + sparta::app::Simulation("Test_special_params", sched){} + + virtual ~ICacheSim(){ + getRoot()->enterTeardown(); + } +private: + void buildTree_() override + { + auto rtn = getRoot(); + + allocators_tn_.reset(new olympia::OlympiaAllocators(rtn)); + + // ICache + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "icache", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Instruction Cache", + &icache_fact)); + + // Source + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "source", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Source", + &source_fact)); + // Sink + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "sink", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Sink", + &sink_fact)); + + tns_to_delete_.emplace_back(new sparta::ResourceTreeNode(rtn, + "checker", + sparta::TreeNode::GROUP_NAME_NONE, + sparta::TreeNode::GROUP_IDX_NONE, + "Checker", + &checker_fact)); + + }; + void configureTree_() override{}; + void bindTree_() override + { + auto * root_node = getRoot(); + // Bind up source + sparta::bind(root_node->getChildAs("icache.ports.in_fetch_req"), + root_node->getChildAs("source.ports.out_icache_req")); + sparta::bind(root_node->getChildAs("icache.ports.out_fetch_credit"), + root_node->getChildAs("source.ports.in_icache_credit")); + sparta::bind(root_node->getChildAs("icache.ports.out_fetch_resp"), + root_node->getChildAs("source.ports.in_icache_resp")); + + // Bind up sink + sparta::bind(root_node->getChildAs("icache.ports.out_l2cache_req"), + root_node->getChildAs("sink.ports.in_icache_req")); + sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_resp"), + root_node->getChildAs("sink.ports.out_icache_resp")); + sparta::bind(root_node->getChildAs("icache.ports.in_l2cache_credits"), + root_node->getChildAs("sink.ports.out_icache_credit")); + + // Bind up checker + sparta::bind(root_node->getChildAs("source.ports.out_icache_req"), + root_node->getChildAs("checker.ports.in_fetch_req")); + sparta::bind(root_node->getChildAs("icache.ports.out_fetch_resp"), + root_node->getChildAs("checker.ports.in_fetch_resp")); + sparta::bind(root_node->getChildAs("icache.ports.out_l2cache_req"), + root_node->getChildAs("checker.ports.in_l2cache_req")); + sparta::bind(root_node->getChildAs("sink.ports.out_icache_resp"), + root_node->getChildAs("checker.ports.in_l2cache_resp")); + }; + + std::unique_ptr allocators_tn_; + + sparta::ResourceFactory icache_fact; + sparta::ResourceFactory source_fact; + sparta::ResourceFactory sink_fact; + sparta::ResourceFactory checker_fact; + + std::vector> tns_to_delete_; + +}; + +const char USAGE[] = + "Usage:\n" + " \n" + "\n"; + +sparta::app::DefaultValues DEFAULTS; + +int main(int argc, char **argv) +{ + + std::string testname; + uint32_t seed = 1; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto & app_opts = cls.getApplicationOptions(); + app_opts.add_options() + ("testname", + sparta::app::named_value("TESTNAME", &testname)->default_value(""), + "Provide a testname to run", + "Test to run") + ("seed", + sparta::app::named_value("SEED", &seed)->default_value(1), + "Provide a value to seed the random generators", + "random seed"); + + int err_code = 0; + if(!cls.parse(argc, argv, err_code)){ + sparta_assert(false, "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta::Scheduler sched; + ICacheSim sim(&sched); + cls.populateSimulation(&sim); + sparta::RootTreeNode* root = sim.getRoot(); + + icache_test::ICacheChecker *checker = root->getChild("checker")->getResourceAs(); + checker->setDUT(root->getChild("icache")->getResourceAs()); + + icache_test::ICacheSource *source = root->getChild("source")->getResourceAs(); + + icache_test::ICacheSink *sink = root->getChild("sink")->getResourceAs(); + sink->setRandomSeed(seed); + + if (testname == "single_access") { + source->queueRequest(1); + cls.runSimulator(&sim, 100); + } + else if (testname == "simple") { + for (int i = 0; i < 4; i++) { + for (int j = 0; j < 8; j++) { + source->queueRequest(8 << j); + } + } + cls.runSimulator(&sim, 1000); + } + else if (testname == "random") { + std::mt19937 gen(seed); + std::lognormal_distribution<> d(2.0, 1.0); + std::vector addrs = {1}; + for (int i = 0; i < 256; ++i) { + auto addr = addrs.back() + uint64_t(d(gen)); + addrs.push_back(addr); + } + for (int i = 0; i < 2048; ++i) { + auto idx = uint32_t(d(gen)) % addrs.size(); + source->queueRequest(addrs[idx]); + if (i % 128 == 0) { + std::shuffle(addrs.begin(), addrs.end(), gen); + } + } + cls.runSimulator(&sim, 100000); + } + else { + sparta_assert(false, "Must provide a valid testname"); + } + return 0; +} \ No newline at end of file diff --git a/test/core/issue_queue/test_cores/test_big_core_full.yaml b/test/core/issue_queue/test_cores/test_big_core_full.yaml index 18315cad..fbac2fda 100644 --- a/test/core/issue_queue/test_cores/test_big_core_full.yaml +++ b/test/core/issue_queue/test_cores/test_big_core_full.yaml @@ -1,3 +1,6 @@ +top.cpu.core0.icache.params.l1_always_hit: true +top.cpu.core0.icache.params.cache_latency: 0 + # # Set up the pipeline for a 8-wide machine # @@ -10,14 +13,14 @@ top.cpu.core0.extension.core_extensions: ["int", "mul", "i2f", "cmov"], ["int"], ["int"], - ["float", "faddsub", "fmac"], + ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], ["br"], ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: - [ + [ ["0", "1"], ["2", "3"], ["4", "5"], diff --git a/test/core/l2cache/BIUSinkUnit.hpp b/test/core/l2cache/BIUSinkUnit.hpp index 47e2b044..fe52c3df 100644 --- a/test/core/l2cache/BIUSinkUnit.hpp +++ b/test/core/l2cache/BIUSinkUnit.hpp @@ -43,23 +43,21 @@ namespace l2cache_test // Sending Initial credits to L2Cache void sendInitialCredits_() { uint32_t biu_req_queue_size_ = 32; - out_biu_ack_.send(biu_req_queue_size_); + out_biu_credits_.send(biu_req_queue_size_); ILOG("Sending initial credits to L2Cache : " << biu_req_queue_size_); } void sinkInst_(const olympia::MemoryAccessInfoPtr & mem_access_info_ptr) { ILOG("Instruction: '" << mem_access_info_ptr->getInstPtr() << "' sinked"); - uint32_t biu_req_queue_size_ = 32; - - out_biu_ack_.send(biu_req_queue_size_, sink_latency_); + out_biu_credits_.send(1, sink_latency_); out_biu_resp_.send(mem_access_info_ptr, 2*sink_latency_); } sparta::DataInPort in_biu_req_ {&unit_port_set_, "in_biu_req", sparta::SchedulingPhase::Tick, 1}; sparta::DataOutPort out_biu_resp_ {&unit_port_set_, "out_biu_resp"}; - sparta::DataOutPort out_biu_ack_ {&unit_port_set_, "out_biu_ack"}; + sparta::DataOutPort out_biu_credits_ {&unit_port_set_, "out_biu_credits"}; std::string purpose_; sparta::Clock::Cycle sink_latency_; diff --git a/test/core/l2cache/L2Cache_test.cpp b/test/core/l2cache/L2Cache_test.cpp index 76a6a169..dee33a85 100644 --- a/test/core/l2cache/L2Cache_test.cpp +++ b/test/core/l2cache/L2Cache_test.cpp @@ -134,22 +134,22 @@ class L2CacheSim : public sparta::app::Simulation root_node->getChildAs("l2cache.ports.in_dcache_l2cache_req")); sparta::bind(root_node->getChildAs("dcache.ports.in_source_resp"), root_node->getChildAs("l2cache.ports.out_l2cache_dcache_resp")); - sparta::bind(root_node->getChildAs("dcache.ports.in_source_ack"), - root_node->getChildAs("l2cache.ports.out_l2cache_dcache_ack")); + sparta::bind(root_node->getChildAs("dcache.ports.in_source_credits"), + root_node->getChildAs("l2cache.ports.out_l2cache_dcache_credits")); sparta::bind(root_node->getChildAs("icache.ports.out_source_req"), root_node->getChildAs("l2cache.ports.in_icache_l2cache_req")); sparta::bind(root_node->getChildAs("icache.ports.in_source_resp"), root_node->getChildAs("l2cache.ports.out_l2cache_icache_resp")); - sparta::bind(root_node->getChildAs("icache.ports.in_source_ack"), - root_node->getChildAs("l2cache.ports.out_l2cache_icache_ack")); + sparta::bind(root_node->getChildAs("icache.ports.in_source_credits"), + root_node->getChildAs("l2cache.ports.out_l2cache_icache_credits")); sparta::bind(root_node->getChildAs("biu.ports.in_biu_req"), root_node->getChildAs("l2cache.ports.out_l2cache_biu_req")); sparta::bind(root_node->getChildAs("biu.ports.out_biu_resp"), root_node->getChildAs("l2cache.ports.in_biu_l2cache_resp")); - sparta::bind(root_node->getChildAs("biu.ports.out_biu_ack"), - root_node->getChildAs("l2cache.ports.in_biu_l2cache_ack")); + sparta::bind(root_node->getChildAs("biu.ports.out_biu_credits"), + root_node->getChildAs("l2cache.ports.in_biu_l2cache_credits")); } // Allocators. Last thing to delete std::unique_ptr allocators_tn_; diff --git a/test/core/l2cache/L2SourceUnit.hpp b/test/core/l2cache/L2SourceUnit.hpp index 05aab52f..64c87c81 100644 --- a/test/core/l2cache/L2SourceUnit.hpp +++ b/test/core/l2cache/L2SourceUnit.hpp @@ -43,8 +43,8 @@ namespace l2cache_test in_source_resp_.registerConsumerHandler (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveInst_, olympia::MemoryAccessInfoPtr)); - in_source_ack_.registerConsumerHandler - (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveAck_, uint32_t)); + in_source_credits_.registerConsumerHandler + (CREATE_SPARTA_HANDLER_WITH_DATA(L2SourceUnit, ReceiveCredits_, uint32_t)); if(params->input_file != "") { inst_generator_ = olympia::InstGenerator::createGenerator(mavis_facade_, params->input_file, false); @@ -58,7 +58,7 @@ namespace l2cache_test void onStartingTeardown_() override { sparta_assert(unit_enable_ == true && pending_reqs_ == 0, "pending_reqs remaining in the L2SourceUnit"); - sparta_assert(unit_enable_ == true && pending_acks_ == 0, "pending_acks remaining in the L2SourceUnit"); + sparta_assert(unit_enable_ == true && pending_credits_ == 0, "pending_credits remaining in the L2SourceUnit"); } private: @@ -88,7 +88,7 @@ namespace l2cache_test ILOG("Instruction: '" << req_inst_queue_.front()->getInstPtr() << "' Requested"); pending_reqs_++; - pending_acks_++; + pending_credits_++; out_source_req_.send(req_inst_queue_.front()); req_inst_queue_.erase(req_inst_queue_.begin()); @@ -99,18 +99,17 @@ namespace l2cache_test ILOG("Instruction: '" << mem_info_ptr->getInstPtr() << "' Received"); } - void ReceiveAck_(const uint32_t & ack) { - pending_acks_--; - ILOG("Ack: '" << ack << "' Received"); + void ReceiveCredits_(const uint32_t & credits) { + pending_credits_--; + ILOG("Ack: '" << credits << "' Received"); } - sparta::DataInPort in_source_resp_ {&unit_port_set_, "in_source_resp", + sparta::DataInPort in_source_resp_ {&unit_port_set_, "in_source_resp", sparta::SchedulingPhase::Tick, 1}; - sparta::DataInPort in_source_ack_ {&unit_port_set_, "in_source_ack"}; + sparta::DataInPort in_source_credits_ {&unit_port_set_, "in_source_credits"}; + sparta::DataOutPort out_source_req_ {&unit_port_set_, "out_source_req"}; - sparta::DataOutPort out_source_req_ {&unit_port_set_, "out_source_req"}; - - uint32_t pending_acks_ = 1; + uint32_t pending_credits_ = 1; uint32_t pending_reqs_ = 0; uint32_t unique_id_ = 0; diff --git a/test/core/l2cache/expected_output/hit_case.out.EXPECTED b/test/core/l2cache/expected_output/hit_case.out.EXPECTED index 94443f92..9d54cecf 100644 --- a/test/core/l2cache/expected_output/hit_case.out.EXPECTED +++ b/test/core/l2cache/expected_output/hit_case.out.EXPECTED @@ -3,43 +3,43 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:48:48 2024 -#Elapsed: 0.00378s +#Start: Saturday Sat Oct 19 15:35:23 2024 +#Elapsed: 0.002228s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 -{0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000001 00000001 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000001 00000001 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000001 00000001 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000001 00000001 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000002 00000002 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000002 00000002 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000001 00000001 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000002 00000002 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000002 00000002 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000002 00000002 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000002 00000002 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ -{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port {0000000034 00000034 top.l2cache info} appendBIURespQueue_: Append BIU->L2Cache resp queue! {0000000034 00000034 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU @@ -48,44 +48,44 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received -{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Requested -{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Requested +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received +{0000000050 00000050 top.dcache info} req_inst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Requested +{0000000050 00000050 top.icache info} req_inst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Requested {0000000051 00000051 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000051 00000051 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000051 00000051 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000051 00000051 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000051 00000051 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000051 00000051 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000052 00000052 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000052 00000052 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000051 00000051 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000052 00000052 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000052 00000052 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000052 00000052 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000052 00000052 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000053 00000053 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000053 00000053 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000052 00000052 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000053 00000053 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000053 00000053 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000061 00000061 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000061 00000061 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000062 00000062 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000062 00000062 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000062 00000062 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Received -{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' +{0000000063 00000063 top.icache info} ReceiveInst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Received +{0000000063 00000063 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' {0000000063 00000063 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000063 00000063 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid:1 FETCHED 0 pid:2 uopid:0 'lw 5,3,4' ' Received +{0000000064 00000064 top.dcache info} ReceiveInst_: Instruction: 'uid:1 BEFORE_FETCH 0 pid:2 uopid:0 'lw 5,3,4' ' Received diff --git a/test/core/l2cache/expected_output/single_access.out.EXPECTED b/test/core/l2cache/expected_output/single_access.out.EXPECTED index 9aa80273..0305e07a 100644 --- a/test/core/l2cache/expected_output/single_access.out.EXPECTED +++ b/test/core/l2cache/expected_output/single_access.out.EXPECTED @@ -3,43 +3,43 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:48:48 2024 -#Elapsed: 0.00446s +#Start: Saturday Sat Oct 19 15:35:23 2024 +#Elapsed: 0.00223s {0000000000 00000000 top.l2cache info} L2Cache: L2Cache construct: #4294967295 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to ICache : 8 {0000000000 00000000 top.l2cache info} sendInitialCredits_: Sending initial credits to DCache : 8 {0000000000 00000000 top.biu info} sendInitialCredits_: Sending initial credits to L2Cache : 32 -{0000000000 00000000 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Requested -{0000000001 00000001 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000000 00000000 top.icache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} ReceiveCredits_: Ack: '8' Received +{0000000000 00000000 top.dcache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000000 00000000 top.icache info} req_inst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Requested +{0000000001 00000001 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000001 00000001 top.l2cache info} getReqFromDCache_: Request received from DCache on the port {0000000001 00000001 top.l2cache info} appendDCacheReqQueue_: Append DCache->L2Cache request queue! {0000000001 00000001 top.l2cache info} getReqFromICache_: Request received from ICache on the port {0000000001 00000001 top.l2cache info} appendICacheReqQueue_: Append ICache->L2Cache request queue! {0000000001 00000001 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - ICache {0000000001 00000001 top.l2cache info} create_Req_: ICache request is sent to Pipeline_req_Q! -{0000000002 00000002 top.icache info} ReceiveAck_: Ack: '8' Received -{0000000002 00000002 top.l2cache info} handle_L2Cache_ICache_Ack_: L2Cache->ICache : Ack is sent. +{0000000001 00000001 top.l2cache info} create_Req_: L2Cache->ICache : Credit is sent. +{0000000002 00000002 top.icache info} ReceiveCredits_: Ack: '1' Received {0000000002 00000002 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : ICACHE {0000000002 00000002 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - DCache {0000000002 00000002 top.l2cache info} create_Req_: DCache request is sent to Pipeline_req_Q! -{0000000003 00000003 top.dcache info} ReceiveAck_: Ack: '8' Received -{0000000003 00000003 top.l2cache info} handle_L2Cache_DCache_Ack_: L2Cache->DCache : Ack is sent. +{0000000002 00000002 top.l2cache info} create_Req_: L2Cache->DCache : Credit is sent. +{0000000003 00000003 top.dcache info} ReceiveCredits_: Ack: '1' Received {0000000003 00000003 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : DCACHE -{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000011 00000011 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000011 00000011 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef -{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000012 00000012 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ {0000000012 00000012 top.l2cache info} appendBIUReqQueue_: Append L2Cache->BIU req queue {0000000012 00000012 top.l2cache info} handle_L2Cache_BIU_Req_: L2Cache Request sent to BIU : Current BIU credit available = 31 -{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' sinked -{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000013 00000013 top.biu info} sinkInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' sinked +{0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000013 00000013 top.l2cache info} handleCacheAccessResult_: Storing the CACHE MISS in miss_pending_buffer_ -{0000000024 00000024 top.l2cache info} getAckFromBIU_: Ack received from BIU on the port : Current BIU credit available = 32 +{0000000024 00000024 top.l2cache info} getCreditsFromBIU_: Credits received from BIU on the port : Current BIU credit available = 32 {0000000034 00000034 top.l2cache info} getRespFromBIU_: Response received from BIU on the port {0000000034 00000034 top.l2cache info} appendBIURespQueue_: Append BIU->L2Cache resp queue! {0000000034 00000034 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU @@ -48,16 +48,16 @@ {0000000035 00000035 top.l2cache info} arbitrateL2CacheAccessReqs_: Arbitration winner - BIU {0000000035 00000035 top.l2cache info} create_Req_: Request found in miss_pending_buffer_ with SrcUnit : DCACHE {0000000036 00000036 top.l2cache info} issue_Req_: Request is sent to Pipeline! SrcUnit : BIU -{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000044 00000044 top.l2cache info} cacheLookup_: Cache MISS: phyAddr=0xdeadbeef {0000000044 00000044 top.l2cache info} handleCacheAccessRequest_: Reload Complete: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessRequest_: Pipeline stage CACHE_LOOKUP : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} cacheLookup_: Cache HIT: phyAddr=0xdeadbeef -{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000045 00000045 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000045 00000045 top.l2cache info} appendICacheRespQueue_: Append L2Cache->ICache resp queue! {0000000045 00000045 top.l2cache info} handle_L2Cache_ICache_Resp_: L2Cache Resp is sent to ICache! -{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received -{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' +{0000000046 00000046 top.icache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received +{0000000046 00000046 top.l2cache info} handleCacheAccessResult_: Pipeline stage HIT_MISS_HANDLING : memptr: deadbeef uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' {0000000046 00000046 top.l2cache info} appendDCacheRespQueue_: Append L2Cache->DCache resp queue! {0000000046 00000046 top.l2cache info} handle_L2Cache_DCache_Resp_: L2Cache Resp is sent to DCache! -{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 FETCHED 0 pid:1 uopid:0 'sw 3' ' Received +{0000000047 00000047 top.dcache info} ReceiveInst_: Instruction: 'uid:0 BEFORE_FETCH 0 pid:1 uopid:0 'sw 3' ' Received diff --git a/test/core/lsu/Lsu_test.cpp b/test/core/lsu/Lsu_test.cpp index a4dfe5dd..a71cfcf3 100644 --- a/test/core/lsu/Lsu_test.cpp +++ b/test/core/lsu/Lsu_test.cpp @@ -107,7 +107,7 @@ void runTest(int argc, char **argv) olympia::LSU *my_lsu = root_node->getChild("cpu.core0.lsu")->getResourceAs(); olympia::LSUTester lsupipe_tester; lsupipe_tester.test_pipeline_stages(*my_lsu); - cls.runSimulator(&sim, 7); + cls.runSimulator(&sim, 9); lsupipe_tester.test_inst_issue(*my_lsu, 2); // Loads operand dependency meet cls.runSimulator(&sim, 52); lsupipe_tester.test_replay_issue_abort(*my_lsu, 3); // Loads operand dependency meet diff --git a/test/core/lsu/test_cores/test_small_core_full.yaml b/test/core/lsu/test_cores/test_small_core_full.yaml index 6ff1c99c..864ed793 100644 --- a/test/core/lsu/test_cores/test_small_core_full.yaml +++ b/test/core/lsu/test_cores/test_small_core_full.yaml @@ -4,6 +4,8 @@ top.cpu.core0: fetch.params.num_to_fetch: 2 + icache.params.l1_always_hit: true + icache.params.cache_latency: 0 decode.params.num_to_decode: 2 rename.params.num_to_rename: 2 dispatch.params.num_to_dispatch: 2 @@ -27,7 +29,7 @@ top.cpu.core0.extension.core_extensions: ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: - [ + [ ["0"], ["1"], ["2"], diff --git a/test/core/rename/Rename_test.cpp b/test/core/rename/Rename_test.cpp index 12b289d1..ca3c7225 100644 --- a/test/core/rename/Rename_test.cpp +++ b/test/core/rename/Rename_test.cpp @@ -426,7 +426,7 @@ void runTest(int argc, char **argv) { root_node->getChild("cpu.core0.execute.iq1") ->getResourceAs(); olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 7); + cls.runSimulator(&sim, 8); issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); issuequeue_tester.test_dependent_integer_second_instruction( *my_issuequeue1); @@ -437,7 +437,9 @@ void runTest(int argc, char **argv) { ->getResourceAs(); olympia::RenameTester rename_tester; - cls.runSimulator(&sim, 4); + // Must stop the simulation before it retires the i2f instructions, + // otherwise the register would have been moved back into the freelist + cls.runSimulator(&sim, 8); rename_tester.test_float(*my_rename); } else if (input_file == "raw_int_lsu.json") { // testing RAW dependency for address operand @@ -451,7 +453,7 @@ void runTest(int argc, char **argv) { root_node->getChild("cpu.core0.execute.iq0") ->getResourceAs(); olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 7); + cls.runSimulator(&sim, 8); issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); lsu_tester.test_dependent_lsu_instruction(*my_lsu); lsu_tester.clear_entries(*my_lsu); @@ -468,7 +470,7 @@ void runTest(int argc, char **argv) { root_node->getChild("cpu.core0.execute.iq1") ->getResourceAs(); olympia::IssueQueueTester issuequeue_tester; - cls.runSimulator(&sim, 6); + cls.runSimulator(&sim, 8); issuequeue_tester.test_dependent_integer_first_instruction(*my_issuequeue); lsu_tester.test_dependent_lsu_instruction(*my_lsu); lsu_tester.clear_entries(*my_lsu); diff --git a/test/core/rename/expected_output/big_core.out.EXPECTED b/test/core/rename/expected_output/big_core.out.EXPECTED index 02c33544..7a820eb1 100644 --- a/test/core/rename/expected_output/big_core.out.EXPECTED +++ b/test/core/rename/expected_output/big_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:17 2024 -#Elapsed: 0.002245s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.002659s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,7 +51,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -59,43 +59,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED index f98a7fc0..f2a7c9d7 100644 --- a/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED +++ b/test/core/rename/expected_output/big_core_small_rename.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:54 2024 -#Elapsed: 0.003636s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.003002s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: DIViq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq1 @@ -51,7 +51,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -59,39 +59,39 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq1: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq1 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NO_RENAMES diff --git a/test/core/rename/expected_output/medium_core.out.EXPECTED b/test/core/rename/expected_output/medium_core.out.EXPECTED index 710dddf4..efdddaf0 100644 --- a/test/core/rename/expected_output/medium_core.out.EXPECTED +++ b/test/core/rename/expected_output/medium_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:05 2024 -#Elapsed: 0.003742s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.002592s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -44,7 +44,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -52,43 +52,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/expected_output/small_core.out.EXPECTED b/test/core/rename/expected_output/small_core.out.EXPECTED index 36d8a20b..7f7f3329 100644 --- a/test/core/rename/expected_output/small_core.out.EXPECTED +++ b/test/core/rename/expected_output/small_core.out.EXPECTED @@ -3,8 +3,8 @@ #Exe: #SimulatorVersion: #Repro: -#Start: Tuesday Tue Oct 8 16:47:26 2024 -#Elapsed: 0.003386s +#Start: Saturday Sat Oct 19 16:27:18 2024 +#Elapsed: 0.002441s {0000000000 00000000 top.dispatch info} Dispatch: mapping target: INTiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: MULiq0 {0000000000 00000000 top.dispatch info} Dispatch: mapping target: I2Fiq0 @@ -38,7 +38,7 @@ {0000000000 00000000 top.decode info} inCredits: Got credits from dut: 10 {0000000000 00000000 top.decode info} Sending group: 0x00000000 UID(0) PID(1) add {0000000001 00000001 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000001 00000001 top.rename info} renameInstructions_: sending inst to dispatch: uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup source register bit mask [1-2] for 'integer' scoreboard {0000000001 00000001 top.rename info} renameInstructions_: setup destination register bit mask [0] for 'integer' scoreboard @@ -46,43 +46,43 @@ {0000000001 00000001 top.decode info} Sending group: 0x00000000 UID(1) PID(2) add {0000000002 00000002 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(0) PID(1) add {0000000002 00000002 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' -{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT +{0000000002 00000002 top.dispatch info} acceptInst: iq0: dispatching uid:0 RENAMED 0 pid:1 uopid:0 'add 3,1,2' +{0000000002 00000002 top.dispatch info} dispatchInstructions_: Sending instruction: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to iq0 of target type: INT {0000000002 00000002 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000002 00000002 top.rename info} renameInstructions_: sending inst to dispatch: uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup source register bit mask [0,2] for 'integer' scoreboard {0000000002 00000002 top.rename info} renameInstructions_: setup destination register bit mask [32] for 'integer' scoreboard {0000000002 00000002 top.decode info} inCredits: Got credits from dut: 1 {0000000002 00000002 top.decode info} Sending group: 0x00000000 UID(2) PID(3) mul -{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} handleOperandIssueCheck_: Sending to issue queue uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.rob info} robAppended_: retire appended: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' {0000000003 00000003 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(1) PID(2) add {0000000003 00000003 top.rob info} retireInstructions_: num to retire: 1 -{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' -{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 -{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 +{0000000003 00000003 top.rob info} retireInstructions_: set oldest: uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' +{0000000003 00000003 top.execute.iq0 info} sendReadyInsts_: Sending instruction uid:0 DISPATCHED 0 pid:1 uopid:0 'add 3,1,2' to exe_pipe exe0 +{0000000003 00000003 top.execute.exe0 info} insertInst: Executing: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' for 4 {0000000003 00000003 top.dispatch info} receiveCredits_: iq0 got 1 credits, total: 8 {0000000003 00000003 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' -{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT +{0000000003 00000003 top.dispatch info} acceptInst: iq0: dispatching uid:1 RENAMED 0 pid:2 uopid:0 'add 4,3,2' +{0000000003 00000003 top.dispatch info} dispatchInstructions_: Sending instruction: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' to iq0 of target type: INT {0000000003 00000003 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000003 00000003 top.rename info} renameInstructions_: sending inst to dispatch: uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup source register bit mask [11-12] for 'integer' scoreboard {0000000003 00000003 top.rename info} renameInstructions_: setup destination register bit mask [33] for 'integer' scoreboard {0000000003 00000003 top.decode info} inCredits: Got credits from dut: 1 {0000000003 00000003 top.decode info} Sending group: 0x00000000 UID(3) PID(4) sub -{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer -{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' +{0000000004 00000004 top.execute.iq0 info} handleOperandIssueCheck_: Instruction NOT ready: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' Bits needed:[0,2] rf: integer +{0000000004 00000004 top.rob info} robAppended_: retire appended: uid:1 DISPATCHED 0 pid:2 uopid:0 'add 4,3,2' {0000000004 00000004 top.dispatch info} dispatchQueueAppended_: queue appended: 0x00000000 UID(2) PID(3) mul -{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' +{0000000004 00000004 top.execute.exe0 info} executeInst_: Executed inst: uid:0 SCHEDULED 0 pid:1 uopid:0 'add 3,1,2' {0000000004 00000004 top.rob info} retireInstructions_: num to retire: 2 {0000000004 00000004 top.dispatch info} dispatchInstructions_: Num to dispatch: 1 -{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' -{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL +{0000000004 00000004 top.dispatch info} acceptInst: iq0: dispatching uid:2 RENAMED 0 pid:3 uopid:0 'mul 13,12,11' +{0000000004 00000004 top.dispatch info} dispatchInstructions_: Sending instruction: uid:2 DISPATCHED 0 pid:3 uopid:0 'mul 13,12,11' to iq0 of target type: MUL {0000000004 00000004 top.rename info} scheduleRenaming_: current stall: NOT_STALLED -{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' +{0000000004 00000004 top.rename info} renameInstructions_: sending inst to dispatch: uid:3 RENAMED 0 pid:4 uopid:0 'sub 14,13,12' {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup source register bit mask [12,33] for 'integer' scoreboard {0000000004 00000004 top.rename info} renameInstructions_: setup destination register bit mask [34] for 'integer' scoreboard diff --git a/test/core/rename/test_cores/test_medium_core_full.yaml b/test/core/rename/test_cores/test_medium_core_full.yaml index 36e40fe3..a4fd0849 100644 --- a/test/core/rename/test_cores/test_medium_core_full.yaml +++ b/test/core/rename/test_cores/test_medium_core_full.yaml @@ -6,6 +6,8 @@ top.cpu.core0: fetch.params.num_to_fetch: 3 + icache.params.l1_always_hit: true + icache.params.cache_latency: 0 decode.params.num_to_decode: 3 rename.params.num_to_rename: 3 dispatch.params.num_to_dispatch: 3 @@ -19,13 +21,13 @@ top.cpu.core0.extension.core_extensions: ["int", "mul", "i2f", "cmov"], ["int", "div"], ["int"], - ["float", "faddsub", "fmac"], + ["float", "faddsub", "fmac"], ["float", "f2i"], ["br"], ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: - [ + [ ["0"], ["1", "2"], ["3", "4"], diff --git a/test/core/rename/test_cores/test_small_core_full.yaml b/test/core/rename/test_cores/test_small_core_full.yaml index 927db2d4..0c0e29d2 100644 --- a/test/core/rename/test_cores/test_small_core_full.yaml +++ b/test/core/rename/test_cores/test_small_core_full.yaml @@ -4,6 +4,8 @@ top.cpu.core0: fetch.params.num_to_fetch: 2 + icache.params.l1_always_hit: true + icache.params.cache_latency: 0 decode.params.num_to_decode: 2 rename.params.num_to_rename: 2 dispatch.params.num_to_dispatch: 2 @@ -24,7 +26,7 @@ top.cpu.core0.extension.core_extensions: ["vint", "vset", "vdiv", "vmul"] ] issue_queue_to_pipe_map: - [ + [ ["0"], ["1"], ["2"],