diff --git a/core/LSU.cpp b/core/LSU.cpp index 7503cf3e..e2f8f151 100644 --- a/core/LSU.cpp +++ b/core/LSU.cpp @@ -17,10 +17,6 @@ namespace olympia sparta::Unit(node), ldst_inst_queue_("lsu_inst_queue", p->ldst_inst_queue_size, getClock()), ldst_inst_queue_size_(p->ldst_inst_queue_size), - load_queue_("load_queue", p->ld_queue_size, getClock()), - load_queue_size_(p->ld_queue_size), - store_queue_("store_queue", p->st_queue_size, getClock()), - store_queue_size_(p->st_queue_size), replay_buffer_("replay_buffer", p->replay_buffer_size, getClock()), replay_buffer_size_(p->replay_buffer_size), replay_issue_delay_(p->replay_issue_delay), @@ -30,7 +26,6 @@ namespace olympia memory_access_allocator), ldst_pipeline_("LoadStorePipeline", static_cast(p->mmu_lookup_stage_length + p->cache_lookup_stage_length + p->cache_read_stage_length + 2), getClock()), - stall_pipeline_on_miss_(p->stall_pipeline_on_miss), allow_speculative_load_exec_(p->allow_speculative_load_exec) { setupPipelineLength(p); @@ -39,8 +34,6 @@ namespace olympia ldst_pipeline_.enableCollection(node); ldst_inst_queue_.enableCollection(node); - load_queue_.enableCollection(node); - store_queue_.enableCollection(node); replay_buffer_.enableCollection(node); // Startup handler for sending initial credits @@ -105,7 +98,6 @@ namespace olympia (static_cast(COMPLETE), CREATE_SPARTA_HANDLER(LSU, completeInst_)); - uev_pipe_stall_ >> uev_issue_inst_; // NOTE: // To resolve the race condition when: // Both cache and MMU try to drive the single BIU port at the same cycle @@ -117,8 +109,13 @@ namespace olympia LSU::~LSU() { - DLOG(getContainer()->getLocation() << ": " << load_store_info_allocator_.getNumAllocated() << " LoadStoreInstInfo objects allocated/created"); - DLOG(getContainer()->getLocation() << ": " << memory_access_allocator_.getNumAllocated() << " MemoryAccessInfo objects allocated/created"); + DLOG( + getContainer()->getLocation() + << ": " << load_store_info_allocator_.getNumAllocated() << " LoadStoreInstInfo objects allocated/created" + ); + DLOG( + getContainer()->getLocation() + << ": " << memory_access_allocator_.getNumAllocated() << " MemoryAccessInfo objects allocated/created"); } void LSU::setupPipelineLength(const LSU::LSUParameterSet* p) { @@ -355,7 +352,7 @@ namespace olympia << " " << updated_memory_access_info_ptr); mmu_hit_ = updated_memory_access_info_ptr->getPhyAddrStatus(); - if(mmu_hit_ && allow_speculative_load_exec_){ + if(updated_memory_access_info_ptr->getInstPtr()->isStoreInst() && mmu_hit_ && allow_speculative_load_exec_){ ILOG("Aborting speculative loads " << updated_memory_access_info_ptr); abortYoungerLoads(updated_memory_access_info_ptr); } @@ -685,10 +682,6 @@ namespace olympia // instruction issue arbitration should always succeed, even when flush happens. // Otherwise, assertion error is fired inside arbitrateInstIssue_() } - - void LSU::pipeStall_() - {} - void LSU::replayReady_(const InstPtr & replay_inst_ptr) { ILOG("Replay inst ready " << replay_inst_ptr); @@ -702,7 +695,10 @@ namespace olympia { load_store_info_ptr->setState(LoadStoreInstInfo::IssueState::READY); } - load_store_info_ptr->setPriority(LoadStoreInstInfo::IssuePriority::HIGHEST); + auto issue_priority = load_store_info_ptr->getMemoryAccessInfoPtr()->getPhyAddrStatus() + ? LoadStoreInstInfo::IssuePriority::CACHE_PENDING + : LoadStoreInstInfo::IssuePriority::MMU_PENDING; + load_store_info_ptr->setPriority(issue_priority); } } if (isReadyToIssueInsts_()) @@ -782,6 +778,7 @@ namespace olympia return true; } + // Only called if allow_spec_load_exec is true void LSU::readyDependentLoads(const LoadStoreInstInfoPtr &store_inst_ptr){ bool found = false; for(auto &ldst_inst_ptr: ldst_inst_queue_){ @@ -792,7 +789,6 @@ namespace olympia // Only ready loads which have register operands ready if(inst_ptr->getStatus() == Inst::Status::DISPATCHED && -// inst_ptr->getTargetVAddr() == store_inst_ptr->getInstPtr()->getTargetVAddr() && scoreboard_views_[core_types::RF_INTEGER]->isSet(inst_ptr->getSrcRegisterBitMask(core_types::RF_INTEGER))){ ILOG("Updating inst to schedule " << inst_ptr << " " << ldst_inst_ptr); updateIssuePriorityAfterNewDispatch_(inst_ptr); @@ -836,25 +832,27 @@ namespace olympia } } } - - ILOG("Age of the oldest instruction " << min_inst_age << " for " << inst_ptr); + if(min_inst_age == UINT64_MAX){ + ILOG("No younger instruction to deallocate"); + return; + } + ILOG("Age of the oldest instruction " << min_inst_age << " for " << inst_ptr << inst_ptr->getTargetVAddr()); // Remove instructions younger than the oldest load that was removed - for (auto iter = queue.begin(); iter != queue.end(); iter++) { - if(!iter.isValid()){ - break; - } + auto iter = queue.begin(); + while(iter != queue.end()){ if((*iter)->getInstPtr() == inst_ptr){ + ++iter; continue; } - - if ((*iter)->getInstUniqueID() > min_inst_age){ + if ((*iter)->getInstUniqueID() >= min_inst_age){ (*iter)->setState(LoadStoreInstInfo::IssueState::READY); - ILOG("Aborted younger load " << *iter); + ILOG("Aborted younger load " << *iter << (*iter)->getInstPtr()->getTargetVAddr()); invalidatePipeline((*iter)->getInstPtr()); - queue.erase(iter); + queue.erase(iter++); + }else{ + ++iter; } } - ILOG("Done"); } void LSU::invalidatePipeline(const InstPtr & inst_ptr){ @@ -862,6 +860,7 @@ namespace olympia auto mmu_stage_id = static_cast(MMU_LOOKUP); auto cache_lookup_stage_id = static_cast(CACHE_LOOKUP); auto cache_read_stage_id = static_cast(CACHE_READ); + auto complete_stage_id = static_cast(COMPLETE); if(ldst_pipeline_.isValid(ac_stage_id)){ auto &pipeline_inst = ldst_pipeline_[ac_stage_id]->getInstPtr(); @@ -887,6 +886,12 @@ namespace olympia ldst_pipeline_.invalidateStage(cache_read_stage_id); } } + if(ldst_pipeline_.isValid(complete_stage_id)){ + auto &pipeline_inst = ldst_pipeline_[complete_stage_id]->getInstPtr(); + if(pipeline_inst == inst_ptr){ + ldst_pipeline_.invalidateStage(complete_stage_id); + } + } } // Append new load/store instruction into issue queue void LSU::appendIssueQueue_(const LoadStoreInstInfoPtr & inst_info_ptr) @@ -1058,7 +1063,10 @@ namespace olympia if (inst_info_ptr->getInstPtr() == inst_ptr) { // Update issue priority for this outstanding TLB miss - inst_info_ptr->setState(LoadStoreInstInfo::IssueState::READY); + if(inst_info_ptr->getState() != LoadStoreInstInfo::IssueState::ISSUED) + { + inst_info_ptr->setState(LoadStoreInstInfo::IssueState::READY); + } inst_info_ptr->setPriority(LoadStoreInstInfo::IssuePriority::MMU_RELOAD); // NOTE: @@ -1098,7 +1106,10 @@ namespace olympia if (inst_info_ptr->getInstPtr() == inst_ptr) { // Update issue priority for this outstanding cache miss - inst_info_ptr->setState(LoadStoreInstInfo::IssueState::READY); + if(inst_info_ptr->getState() != LoadStoreInstInfo::IssueState::ISSUED) + { + inst_info_ptr->setState(LoadStoreInstInfo::IssueState::READY); + } inst_info_ptr->setPriority(LoadStoreInstInfo::IssuePriority::CACHE_RELOAD); // NOTE: diff --git a/core/LSU.hpp b/core/LSU.hpp index f40f6900..88e59471 100644 --- a/core/LSU.hpp +++ b/core/LSU.hpp @@ -49,12 +49,9 @@ namespace olympia // Parameters for ldst_inst_queue PARAMETER(uint32_t, ldst_inst_queue_size, 8, "LSU ldst inst queue size") - PARAMETER(uint32_t, st_queue_size, ldst_inst_queue_size, "Store Queue size") - PARAMETER(uint32_t, ld_queue_size, ldst_inst_queue_size, "Load Queue size") PARAMETER(uint32_t, replay_buffer_size, ldst_inst_queue_size, "Replay buffer size") PARAMETER(uint32_t, replay_issue_delay, 3, "Replay Issue delay") // LSU microarchitecture parameters - PARAMETER(bool, stall_pipeline_on_miss, false, "Stall pipeline on miss event") PARAMETER(bool, allow_speculative_load_exec, true, "Allow loads to proceed speculatively before all older store addresses are known") // Pipeline length PARAMETER(uint32_t, mmu_lookup_stage_length, 1, "Length of the mmu lookup stage") @@ -77,6 +74,7 @@ namespace olympia static const char name[]; + //////////////////////////////////////////////////////////////////////////////// // Type Name/Alias Declaration //////////////////////////////////////////////////////////////////////////////// @@ -258,12 +256,6 @@ namespace olympia LoadStoreIssueQueue ldst_inst_queue_; const uint32_t ldst_inst_queue_size_; - sparta::Buffer load_queue_; - const uint32_t load_queue_size_; - - sparta::Buffer store_queue_; - const uint32_t store_queue_size_; - sparta::Buffer replay_buffer_; const uint32_t replay_buffer_size_; @@ -303,7 +295,6 @@ namespace olympia uint32_t COMPLETE = 4; // LSU Microarchitecture parameters - const bool stall_pipeline_on_miss_; const bool allow_speculative_load_exec_; //////////////////////////////////////////////////////////////////////////////// @@ -317,9 +308,6 @@ namespace olympia sparta::PayloadEvent uev_replay_ready_{&unit_event_set_, "replay_ready", CREATE_SPARTA_HANDLER_WITH_DATA(LSU, replayReady_, InstPtr)}; - sparta::UniqueEvent<> uev_pipe_stall_{&unit_event_set_, "pipe_stall", - CREATE_SPARTA_HANDLER(LSU, pipeStall_)}; - //////////////////////////////////////////////////////////////////////////////// // Callbacks //////////////////////////////////////////////////////////////////////////////// @@ -359,9 +347,6 @@ namespace olympia // Handle instruction flush in LSU void handleFlush_(const FlushCriteria &); - // Perform pipeline stall - void pipeStall_(); - // Instructions in the replay ready to issue void replayReady_(const InstPtr &); diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 7f0a617d..aa6a5d28 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -29,3 +29,4 @@ add_subdirectory(sim) add_subdirectory(core/common) add_subdirectory(core/dispatch) add_subdirectory(core/rename) +add_subdirectory(core/lsu) diff --git a/test/core/lsu/CMakeLists.txt b/test/core/lsu/CMakeLists.txt new file mode 100644 index 00000000..3aea767a --- /dev/null +++ b/test/core/lsu/CMakeLists.txt @@ -0,0 +1,14 @@ +project(Lsu_test) + +target_link_libraries(core mss) + +add_executable(Lsu_test Lsu_test.cpp ${SIM_BASE}/sim/OlympiaSim.cpp) + +target_link_libraries (Lsu_test core common_test ${STF_LINK_LIBS} SPARTA::sparta) + +file(CREATE_LINK ${SIM_BASE}/mavis/json ${CMAKE_CURRENT_BINARY_DIR}/mavis_isa_files SYMBOLIC) +file(CREATE_LINK ${SIM_BASE}/arches ${CMAKE_CURRENT_BINARY_DIR}/arches SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/test_cores ${CMAKE_CURRENT_BINARY_DIR}/test_cores SYMBOLIC) +file(CREATE_LINK ${CMAKE_CURRENT_SOURCE_DIR}/raw.json ${CMAKE_CURRENT_BINARY_DIR}/raw.json SYMBOLIC) + +sparta_named_test(Lsu_test_raw Lsu_test small_core.out -c test_cores/test_small_core.yaml --input-file raw.json) \ No newline at end of file diff --git a/test/core/lsu/Lsu_test.cpp b/test/core/lsu/Lsu_test.cpp new file mode 100644 index 00000000..0a60e1e2 --- /dev/null +++ b/test/core/lsu/Lsu_test.cpp @@ -0,0 +1,116 @@ + +#include "Dispatch.hpp" +#include "MavisUnit.hpp" +#include "CoreUtils.hpp" +#include "Rename.hpp" +#include "ExecutePipe.hpp" +#include "LSU.hpp" +#include "sim/OlympiaSim.hpp" +#include "OlympiaAllocators.hpp" + +#include "test/core/common/SourceUnit.hpp" +#include "test/core/common/SinkUnit.hpp" +#include "test/core/rename/ROBSinkUnit.hpp" + +#include "sparta/app/CommandLineSimulator.hpp" +#include "sparta/utils/SpartaTester.hpp" +#include "sparta/resources/Buffer.hpp" +#include "sparta/sparta.hpp" +#include "sparta/simulation/ClockManager.hpp" +#include "sparta/kernel/Scheduler.hpp" +#include "sparta/utils/SpartaTester.hpp" +#include "sparta/statistics/StatisticSet.hpp" +#include "sparta/report/Report.hpp" +#include "sparta/events/UniqueEvent.hpp" +#include "sparta/app/Simulation.hpp" +#include "sparta/utils/SpartaSharedPointer.hpp" + +#include +#include +#include +#include +#include + +TEST_INIT + +class olympia::LSUTester +{ + public: + void test_dependent_lsu_instruction(olympia::LSU & lsu){ + // testing RAW dependency for LSU + // we have an ADD instruction before we destination register 3 + // and then a subsequent STORE instruction to register 3 + // we can't STORE until the add instruction runs, so we test + // while the ADD instruction is running, the STORE instruction should NOT issue + EXPECT_TRUE(lsu.lsu_insts_issued_ == 0); + } + + void test_inst_issue(olympia::LSU &lsu, int count){ + EXPECT_EQUAL(lsu.lsu_insts_issued_, count); + } +}; + +const char USAGE[] = + "Usage:\n" + " \n" + "\n"; + +sparta::app::DefaultValues DEFAULTS; + +// The main tester of Rename. The test is encapsulated in the +// parameter test_type of the Source unit. +void runTest(int argc, char **argv) +{ + DEFAULTS.auto_summary_default = "off"; + std::vector datafiles; + std::string input_file; + + sparta::app::CommandLineSimulator cls(USAGE, DEFAULTS); + auto & app_opts = cls.getApplicationOptions(); + app_opts.add_options() + ("output_file", + sparta::app::named_value>("output_file", &datafiles), + "Specifies the output file") + ("input-file", + sparta::app::named_value("INPUT_FILE", &input_file)->default_value(""), + "Provide a JSON instruction stream", + "Provide a JSON file with instructions to run through Execute"); + + po::positional_options_description& pos_opts = cls.getPositionalOptions(); + pos_opts.add("output_file", -1); // example, look for the at the end + + int err_code = 0; + if(!cls.parse(argc, argv, err_code)){ + sparta_assert(false, "Command line parsing failed"); // Any errors already printed to cerr + } + + sparta_assert(false == datafiles.empty(), "Need an output file as the last argument of the test"); + + sparta::Scheduler scheduler; + uint64_t ilimit = 0; + uint32_t num_cores = 1; + bool show_factories = false; + OlympiaSim sim("simple", + scheduler, + num_cores, // cores + input_file, + ilimit, + show_factories); + + cls.populateSimulation(&sim); + sparta::RootTreeNode* root_node = sim.getRoot(); + + olympia::LSU *my_lsu = root_node->getChild("cpu.core0.lsu")->getResourceAs(); + olympia::LSUTester lsupipe_tester; + cls.runSimulator(&sim, 7); + lsupipe_tester.test_inst_issue(*my_lsu, 2); + cls.runSimulator(&sim); +} + +int main(int argc, char **argv) +{ + runTest(argc, argv); + + REPORT_ERROR; + return (int)ERROR_CODE; +} diff --git a/test/core/lsu/raw.json b/test/core/lsu/raw.json new file mode 100644 index 00000000..d5a268f5 --- /dev/null +++ b/test/core/lsu/raw.json @@ -0,0 +1,38 @@ +[ + { + "mnemonic": "lw", + "rs1": 5, + "rs2": 6, + "vaddr": "0xdeeebeef" + }, + { + "mnemonic": "lw", + "rs1": 5, + "rs2": 6, + "vaddr": "0xdeeebeef" + }, + { + "mnemonic": "lw", + "rs1": 5, + "rs2": 6, + "vaddr": "0xdeeebeef" + }, + { + "mnemonic": "sw", + "rs1": 2, + "rs2": 0, + "vaddr" : "0xdeadbeef" + }, + { + "mnemonic": "lw", + "rs1": 0, + "rd": 1, + "vaddr" : "0xdeadbeef" + }, + { + "mnemonic": "lw", + "rs1": 3, + "rd": 4, + "vaddr" : "0xdeadbeef" + } +] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_big_core.yaml b/test/core/lsu/test_cores/test_big_core.yaml new file mode 100644 index 00000000..c749ab18 --- /dev/null +++ b/test/core/lsu/test_cores/test_big_core.yaml @@ -0,0 +1,41 @@ + +# +# Set up the pipeline for a 2-wide machine +# +#top.cpu: +# dispatch.num_to_dispatch: 2 + +top.extension.core_extensions: + execution_topology: + [["alu", "10"], + ["fpu", "10"], + ["br", "10"]] +top.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1"], # <-- TO + ["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]] + + float.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1"], # <-- TO + ["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_big_core_small_rename.yaml b/test/core/lsu/test_cores/test_big_core_small_rename.yaml new file mode 100644 index 00000000..a569387b --- /dev/null +++ b/test/core/lsu/test_cores/test_big_core_small_rename.yaml @@ -0,0 +1,44 @@ + +# +# Set up the pipeline for a 2-wide machine +# +#top.cpu: +# dispatch.num_to_dispatch: 2 + top: + rename.params.num_integer_renames: 34 + rename.params.num_float_renames: 34 + +top.extension.core_extensions: + execution_topology: + [["alu", "10"], + ["fpu", "10"], + ["br", "10"]] +top.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1"], # <-- TO + ["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]] + + float.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "alu3", "alu4", "alu5", "fpu0", "fpu1", "br0", "br1"], # <-- TO + ["alu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu3", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu4", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["alu5", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"], + ["br1", "1", "1", "1", "1", "1", "1", "1", "1", "1", "1"]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core.yaml b/test/core/lsu/test_cores/test_medium_core.yaml new file mode 100644 index 00000000..9904c632 --- /dev/null +++ b/test/core/lsu/test_cores/test_medium_core.yaml @@ -0,0 +1,33 @@ + +# +# Set up the pipeline for a 2-wide machine +# +#top.cpu: +# dispatch.num_to_dispatch: 2 + +top.extension.core_extensions: + execution_topology: + [["alu", "2"], + ["fpu", "2"], + ["br", "2"]] +top.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0"], # <-- TO + ["alu0", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1"]] + + float.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0"], # <-- TO + ["alu0", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1"]] \ No newline at end of file diff --git a/test/core/lsu/test_cores/test_medium_core_full.yaml b/test/core/lsu/test_cores/test_medium_core_full.yaml new file mode 100644 index 00000000..f07bbd83 --- /dev/null +++ b/test/core/lsu/test_cores/test_medium_core_full.yaml @@ -0,0 +1,46 @@ +# +# Set up the pipeline for a 3-wide machine +# + +# Build on top of a small core + +top.cpu.core0: + fetch.params.num_to_fetch: 3 + decode.params.num_to_decode: 3 + rename.params.num_to_rename: 3 + dispatch.params.num_to_dispatch: 3 + rob.params.num_to_retire: 3 + dcache.params: + l1_size_kb: 32 + +top.cpu.core0.extension.core_extensions: + execution_topology: + [["alu", "3"], + ["fpu", "2"], + ["br", "1"]] + +top.cpu.core0.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0", "lsu"], + ["alu0", "1", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1", "1"], + ["lsu", "1", "1", "1", "1", "1", "1", "1"]] + + + float.params.latency_matrix: | + [["", "alu0", "alu1", "alu2", "fpu0", "fpu1", "br0", "lsu"], + ["alu0", "1", "1", "1", "1", "1", "1", "1"], + ["alu1", "1", "1", "1", "1", "1", "1", "1"], + ["alu2", "1", "1", "1", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1", "1", "1", "1"], + ["fpu1", "1", "1", "1", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1", "1", "1", "1"], + ["lsu", "1", "1", "1", "1", "1", "1", "1"]] + diff --git a/test/core/lsu/test_cores/test_small_core.yaml b/test/core/lsu/test_cores/test_small_core.yaml new file mode 100644 index 00000000..7494e180 --- /dev/null +++ b/test/core/lsu/test_cores/test_small_core.yaml @@ -0,0 +1,27 @@ + +# +# Set up the pipeline for a 2-wide machine +# +#top.cpu: +# dispatch.num_to_dispatch: 2 + +top.extension.core_extensions: + execution_topology: + [["alu", "1"], + ["fpu", "1"], + ["br", "1"]] +top.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "alu0", "fpu0", "br0"], # <-- TO + ["alu0", "1", "1", "1"], + ["fpu0", "1", "1", "1"], + ["br0", "1", "1", "1"]] + + float.params.latency_matrix: | + [["", "alu0", "fpu0", "br0"], + ["alu0", "1", "1", "1"], + ["fpu0", "1", "1", "1"], + ["br0", "1", "1", "1"]] diff --git a/test/core/lsu/test_cores/test_small_core_full.yaml b/test/core/lsu/test_cores/test_small_core_full.yaml new file mode 100644 index 00000000..44b8eae2 --- /dev/null +++ b/test/core/lsu/test_cores/test_small_core_full.yaml @@ -0,0 +1,36 @@ +# +# Set up the pipeline for a 2-wide machine +# + +top.cpu.core0: + fetch.params.num_to_fetch: 2 + decode.params.num_to_decode: 2 + rename.params.num_to_rename: 2 + dispatch.params.num_to_dispatch: 2 + rob.params.num_to_retire: 2 + dcache.params: + l1_size_kb: 16 + +top.cpu.core0.extension.core_extensions: + execution_topology: + [["alu", "1"], + ["fpu", "1"], + ["br", "1"]] + +top.cpu.core0.rename.scoreboards: + # From + # | + # V + integer.params.latency_matrix: | + [["", "alu0", "fpu0", "br0", "lsu"], # <-- TO + ["alu0", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1"], + ["lsu", "1", "1", "1", "1"]] + + float.params.latency_matrix: | + [["", "alu0", "fpu0", "br0", "lsu"], # <-- TO + ["alu0", "1", "1", "1", "1"], + ["fpu0", "1", "1", "1", "1"], + ["br0", "1", "1", "1", "1"], + ["lsu", "1", "1", "1", "1"]]