Merge pull request #1860 from XYenChi/master

Fix formatting of assembly code within comments
riscv-software-src · Nov 20, 2024 · eb0a3e2 · eb0a3e2
2 parents 2c67071 + 5cc162c
commit eb0a3e2
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Showing 8 changed files with 8 additions and 8 deletions.
diff --git a/riscv/insns/vmulhu_vv.h b/riscv/insns/vmulhu_vv.h
@@ -1,4 +1,4 @@
-// vmulhu vd ,vs2, vs1
+// vmulhu vd, vs2, vs1
 VI_VV_ULOOP
 ({
   vd = ((uint128_t)vs2 * vs1) >> sew;

diff --git a/riscv/insns/vredand_vs.h b/riscv/insns/vredand_vs.h
@@ -1,4 +1,4 @@
-// vredand.vs vd, vs2 ,vs1
+// vredand.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res &= vs2;

diff --git a/riscv/insns/vredmaxu_vs.h b/riscv/insns/vredmaxu_vs.h
@@ -1,4 +1,4 @@
-// vredmaxu.vs vd, vs2 ,vs1
+// vredmaxu.vs vd, vs2, vs1
 VI_VV_ULOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res >= vs2) ? vd_0_res : vs2;

diff --git a/riscv/insns/vredmin_vs.h b/riscv/insns/vredmin_vs.h
@@ -1,4 +1,4 @@
-// vredmin.vs vd, vs2 ,vs1
+// vredmin.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;

diff --git a/riscv/insns/vredminu_vs.h b/riscv/insns/vredminu_vs.h
@@ -1,4 +1,4 @@
-// vredminu.vs vd, vs2 ,vs1
+// vredminu.vs vd, vs2, vs1
 VI_VV_ULOOP_REDUCTION
 ({
   vd_0_res = (vd_0_res <= vs2) ? vd_0_res : vs2;

diff --git a/riscv/insns/vredor_vs.h b/riscv/insns/vredor_vs.h
@@ -1,4 +1,4 @@
-// vredor.vs vd, vs2 ,vs1
+// vredor.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res |= vs2;

diff --git a/riscv/insns/vredsum_vs.h b/riscv/insns/vredsum_vs.h
@@ -1,4 +1,4 @@
-// vredsum.vs vd, vs2 ,vs1
+// vredsum.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res += vs2;

diff --git a/riscv/insns/vredxor_vs.h b/riscv/insns/vredxor_vs.h
@@ -1,4 +1,4 @@
-// vredxor.vs vd, vs2 ,vs1
+// vredxor.vs vd, vs2, vs1
 VI_VV_LOOP_REDUCTION
 ({
   vd_0_res ^= vs2;