Public Review Feedback for RISC-V Server SoC Specification

[anpar123]

(Posting on behalf of different contributors at Google.)

Please find aggregate feedback on the proposed RISC-V Server SoC Specification below:

[2.3] - Nested IO translations (i.e. two stage translations gIOVA → GPA → SPA) is becoming a must have requirement, so it may be better to call out this feature as a must. It is also preferable if the Guest(unprivileged user) can issue invalidation in the gIOVA address when we are using two-level page tables.
[2.4.4] - [ADR_040] Peer-to-peer access across devices through CPUs root-complex/IOMMU is quite common, so making this a required feature may be beneficial.
[2.4.9] -It is beneficial to consider specifying the Firmware first flows to export these errors via. an out-of-band mechanism to BMC. Such mechanisms SHOULD not have any impact on the performance and be resilient to marginal links creating large numbers of correctable errors.
[2.6] - For this comment - “The count of RCID and MCID that can be used in the SoC should scale with the number of RISC-V harts in the SoC”

• Can we make this a requirement instead of a suggestion?
• Can we include a notion of a collection of RCID/MCID which could be monitored/controlled as a unit at a higher granularity (think monitoring/controlling a VM instead of each hart within a VM).

Can we add a requirement in section [2.8] to scale the monitoring ability to support all available RCID/MCID.
[2.6] - For this comment - “The method employed by the SoC for bandwidth throttling and control is specific to its implementation. It is advisable for the implementation to utilize a scheme that results in a deviation of no more than +/- 10 % from the target set by system software through the CBQRI interface.”

• Can we add requirements to provide mechanisms to monitor bandwidth throttling and control irrespective of the implementation?

[2.6] - [QOS_070] and [QOS_080] - Can we add other end points like PCIE, CXL, cross socket, die, etc.?
[2.7] - [MNG_020] - Can we add/recommend I3C (no IPMI) support as well?
[2.8] - Please add performance monitoring for IOMMU as well. Could start with the following

• Hit/Miss rates for different page sizes
• Hit/Miss rates separately for first and second level
• #Memory access by IOMMU for page walk

[2.8] - [SPM_010] - Please specify cache lookup and misses for read and write traffic separately.
[2.8] - [SPM_030] - Can we add P2P traffic accounting as well?
[2.8] - [SPM_050] - Can we add separation per target, in other words specific remote memory v/s any remote memory?
[2.9] - [SEC_020] - Can we add a recommendation to support CMA/SPDM?
[2.1] - Can we define a notion of maximum permissible clock skew across the distribution network?