diff --git a/src/server_soc.bib b/src/server_soc.bib
index 067d71d..c742f2e 100644
--- a/src/server_soc.bib
+++ b/src/server_soc.bib
@@ -23,6 +23,11 @@ @electronic{PCI
   url = {https://pcisig.com/pci-express-6.0-specification},
   year = {}
 }
+@electronic{PCI_PREF,
+  title = {Removing Prefetchable Terminology ECN},
+  url = {https://pcisig.com/specifications?field_revision_value%5B%5D=6&field_document_type_value%5B%5D=ecn&speclib=},
+  year = {}
+}
 @electronic{CXL,
   title = {Compute Express® Link (CXL) Specification Revision 3.0},
   url = {https://www.computeexpresslink.org/download-the-specification},
diff --git a/src/server_soc_intro.adoc b/src/server_soc_intro.adoc
index 30b6b6a..bc5b357 100644
--- a/src/server_soc_intro.adoc
+++ b/src/server_soc_intro.adoc
@@ -195,12 +195,11 @@ if they are not in this table).
 | PLDM             | Follows DMTF standard. Platform Level Data Model.
 | PMA              | Physical Memory Attributes.
 | PMP              | Physical Memory Protection.
-| Prefetchable
-  Non-prefetchable | Follows PCI Express. Defines the property of the memory
-                     space used by a device. For details see the PCIe Base
-                     Specification. Broadly, non-prefetchable space covers any
-                     locations where reads have side effects or where writes
-                     cannot be merged.
+| Significant Cache| A large cache that might have significant impact on
+                     performance. This specification recommendeds that a cache
+                     with a capacity larger than 32 KiB be considered a
+                     significant cache if it has a significant impact on
+                     performance.
 | SMBIOS           | System Management BIOS.
 | SoC              | System on a chip, also referred as system-on-a-chip and
                      system-on-chip.
diff --git a/src/server_soc_requirements.adoc b/src/server_soc_requirements.adoc
index d68d98d..27a02e6 100644
--- a/src/server_soc_requirements.adoc
+++ b/src/server_soc_requirements.adoc
@@ -516,7 +516,14 @@ hierarchy domain originating at each PCIe root port.
 
 2+| _The ranges suitable for mapping using 32-bit BARs are also sometimes termed
      as the low MMIO ranges and those suitable for use with 64-bit BARs termed
-     as high MMIO ranges._
+     as high MMIO ranges.                                                      +
+                                                                               +
+    _The bit 3 of the Base Address Register used to called the “Prefetchable”
+     bit and required PCIe functions to support 64-bit addressing for any BAR
+     that requested "Prefetchable" memory space. The "Removing Prefetchable
+     Terminology" ECN <<PCI_PREF>> reworks the PCIe Base Specification to
+     remove Prefetchable terminology to more accurately reflect modern device
+     and system requirements._
 
 | MMS_030 a| The system physical address ranges designated for mapping endpoint
              memory spaces have the following physical memory attribute (PMAs)
@@ -551,8 +558,8 @@ hierarchy domain originating at each PCIe root port.
              TRUE:
 
              * Address is not within any of the following address ranges:
-               ** Address range defined by memory base/limit or prefetchable
-                  memory base/limit registers of any root port.
+               ** Address range defined by memory base/limit or 64-bit memory
+                  base/limit registers of any root port.
                ** BAR (including when EA capability is used) mapped range of
                   any RCiEP.
                ** BAR (including when EA capability is used) mapped range of
@@ -564,6 +571,20 @@ hierarchy domain originating at each PCIe root port.
              * A UR or a CA response is received from the completer.
              * A completion timeout occurs.
 
+2+| _The 64-bit memory base/limit register was previously called Prefetchable
+     Memory Base/Limit. The concept of “Prefetchable” MMIO was originally needed
+     to control PCI-PCI Bridges, which were allowed/encouraged to prefetch
+     Memory Read data in prefetchable regions. The original intent of the
+     Prefetchable/Non-Prefetchable distinction was focused on PCI behaviors,
+     and was not intended for software use in determining memory attributes
+     and/or coding techniques. The "Removing Prefetchable Terminology" ECN
+     <<PCI_PREF>> reworks the PCIe Base Specification to remove Prefetchable
+     terminology._                                                             +
+                                                                               +
+    _See also the implementation note on optimizations based on restricted
+     programming mode in section 2.3.1 of PCIe specification 6.0._
+
+
 | MMS_050 a| A store from a RISC-V application processor hart to memory ranges
              designated for mapping memory space of endpoints or RCiEP MUST
              be dropped (silently ignored or discarded) and MUST NOT lead to any
@@ -571,8 +592,8 @@ hierarchy domain originating at each PCIe root port.
              following are TRUE:
 
              * Address is not within any of the following address ranges:
-               ** Address range defined by memory base/limit or prefetchable
-                  memory base/limit registers of any root port.
+               ** Address range defined by memory base/limit or 64-bit memory
+                  base/limit registers of any root port.
                ** BAR (including when EA capability is used) mapped range of
                   any RCiEP.
                ** BAR (including when EA capability is used) mapped range of