From b12948b4793b26f96cdc853f62b290b15a92f444 Mon Sep 17 00:00:00 2001 From: "Shaolin.Xie" Date: Mon, 6 Nov 2023 17:09:30 +0800 Subject: [PATCH] Changes to be committed: modified: server_soc_requirements.adoc Fix the typoes: Change the Cache and Coherence requirement ID from "CCA_###" to "CCS_###". --- server_soc_requirements.adoc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/server_soc_requirements.adoc b/server_soc_requirements.adoc index 90c72ec..3e4c6a9 100644 --- a/server_soc_requirements.adoc +++ b/server_soc_requirements.adoc @@ -745,14 +745,14 @@ messages or completions. [%header, cols="5,25"] |=== | ID# ^| Requirement -| CCA_010 | The host bridge MUST enforce PCIe memory ordering rules and SHOULD +| CCS_010 | The host bridge MUST enforce PCIe memory ordering rules and SHOULD support the relaxed ordering (RO) and ID-based ordering (IDO). 2+| _An implementation may occassionally or never permit the relaxations allowed by RO and/or IDO attributes. Such implementations will result in a more conservative interpretation of the ordering rules, but they will not result in a violation of the ordering rules._ -| CCA_020 | Writes to host or device memory using the RO attribute set to 0 +| CCS_020 | Writes to host or device memory using the RO attribute set to 0 MUST be observed by other harts and bus mastering devices in the order in which the write was received by the PCIe root port or the host bridge such that all previous writes are globally observed