updates

src/server_soc_requirements.adoc

@@ -551,7 +551,7 @@ devices, and SR-IOV capable devices.
 |===
 | ID#     ^| Requirement
 | ACS_010 a| PCIe root ports and SoC integrated downstream switch ports MUST
-             support the following PCIe access control services (ACS) controls
+             support the following PCIe access control services (ACS) controls:
 
              * ACS source validation.
              * ACS translation blocking.
@@ -663,7 +663,7 @@ space of an endpoint or RCiEP.
 ==== ID Routed Transactions
 
 The rules in this section apply to treatment in the root complex of TLPs that
-are routed by ID. Such requests may be ID Configuration requests, ID routed
+are routed by ID. Such requests may be Configuration requests, ID routed
 messages or completions.
 
 [width=100%]
@@ -766,9 +766,10 @@ mechanism in PCIe.
 
 | MSI_020  | SoC MUST NOT require any further action from the operating system
              besides configuring the MSI address register in devices with the
-             address of an IMSIC interrupt register file (or a virtual interrupt
-             file) and the MSI data register in devices with an external
-             interrupt identity to enable the use of MSI or MSI-X.
+             address of an IMSIC interrupt file -- a supervisor-level interrupt
+             file or a guest interrupt file -- and the MSI data register in
+             devices with an external interrupt identity to enable the use of
+             MSI or MSI-X.
 
 | MSI_030  | SoC MUST NOT support INTx virtual wire based interrupt signaling.
 2+| _PCIe supports INTx emulation to support legacy PCI interrupt mechanisms.
@@ -892,9 +893,9 @@ mechanism in PCIe.
      participate in RAS frameworks like data poisoning and AER, power management,
      etc._
 
-| SID_020  | SoC-integrated PCIe devices MUST NOT use legacy PCI capabilities.
-             They MUST NOT require the use of I/O space, I/O transactions, or
-             the INTx virtual wire interrupt signaling mechanism.
+| SID_020  | SoC-integrated PCIe devices MUST NOT require the use of I/O space,
+             I/O transactions, or the INTx virtual wire interrupt signaling
+             mechanism.
 
 | SID_030  | SoC integrated PCIe devices that cache address translations MUST
              implement the PCIe ATS capability if the address translation cache
@@ -997,7 +998,7 @@ mechanism in PCIe.
                                                                                +
    _Data poisoning also empowers the implementation of error containment
     features supported by industry standards like PCIe and CXL._               +
-
+                                                                               +
    _For more detailed discussions on the treatment of faults and errors, refer
     to the RISC-V RERI specification._
 
@@ -1236,7 +1237,7 @@ data centers and enterprises.
              of counting:
 
              * Cache lookup
-             * Cache miss                                                      +
+             * Cache miss
                                                                                +
              If the SoC supports NUMA configurations, then the HPM SHOULD
              support filtering the counting based on whether the request
@@ -1248,7 +1249,7 @@ data centers and enterprises.
              capable of counting:
 
              * Read bandwidth
-             * Write bandwidth                                                 +
+             * Write bandwidth
                                                                                +
              If the SoC supports NUMA configurations, then the HPM SHOULD
              support filtering the counting based on whether the request
@@ -1284,7 +1285,7 @@ data centers and enterprises.
 | SEC_005 a| The Server SoC MUST comply with the requirements and guidelines
              detailed in Reference Model, Ecosystem Security Objectives, and
              the Cryptography sections of the RISC-V Security Model Version
-             1.0 cite:[SEC].  The Server SoC is classified as a complex
+             1.0 cite:[SEC]. The Server SoC is classified as a complex
              security system for the purposes of SR_ROT_001 and SR_ATT_002.
 
 | SEC_006 a| The Server SoC MUST support the Generic System Without Supervisor
@@ -1294,7 +1295,7 @@ data centers and enterprises.
              Blocks section of the RISC-V Security Model specification.
 
 | SEC_007 a| The Server SoC MAY support the Confidential Computing on RISC-V
-             (CoVE) use detailed in the RISC-V Security Model Version 1.0. The
+             (CoVE) use case detailed in the RISC-V Security Model Version 1.0. The
              building blocks used to implement this use case MUST comply with
              the requirements specified in the RISC-V Security Building Blocks
              section of the RISC-V Security Model specification.
@@ -1316,7 +1317,7 @@ data centers and enterprises.
              encryption SHOULD comply with security requirements specified by
              standards such as FIPS 140-3.
 
-| SEC_040  | The SoC SHOULD have the capability interfacing with a Trusted
+| SEC_040  | The SoC SHOULD have the capability of interfacing with a Trusted
              Platform Module (TPM) that adheres to the TPM 2.0 Library
              specification cite:[TPM20].
 2+| _A TPM enhances security by providing secure storage for sensitive