diff --git a/agendas/2024-05-02.adoc b/agendas/2024-05-02.adoc
index b569bc5..d7b36b1 100644
--- a/agendas/2024-05-02.adoc
+++ b/agendas/2024-05-02.adoc
@@ -27,7 +27,7 @@ Derek Hower, Qualcomm
 == Load/store pair
 
  * Recall: ARC authorized Zilsd (RV32 load/store double into sequential registers) fast-track extension
- * ARC has requested that flexible load/store pairs (independent dst regs), included in the SE SIG charter, be considered for consistency.
+ * Apps & Tools HC has requested that flexible load/store pairs (independent dst regs), included in the SE SIG charter, be considered for consistency and to reduce burden on toolchains.
  * Two proposals:
 
 |===
@@ -54,7 +54,7 @@ h| % SROS total | 0.0815% | 0.1353% | 1.0416%
 h| Implicit offset shift | 2*data size (aligned to pair) | data size (aligned to single) | 0
 h| Offset bits | 2 | 5 | 12
 h| Offset reach (doubleword) | 64 bytes | 256 bytes | 4096 bytes
-h| SPEC 2006, clang 16, -O3 static code size reduction | | 1.98% Avg +
+h| SPEC 2006, RVA23 clang 16, -O3 static code size reduction | | 1.98% Avg +
 5.51% Max |
 h| % Avg Reduction / % SROS | | 14.63 |
 |===
@@ -83,4 +83,3 @@ h| % Avg Reduction / % SROS | | 14.63 |
 == Processor classes
 
  * https://github.com/riscv-admin/riscv-scalar-efficiency/blob/main/work%20product/processor_classes.adoc[See Draft]
- 
\ No newline at end of file
diff --git a/agendas/2024-05-02.pdf b/agendas/2024-05-02.pdf
new file mode 100644
index 0000000..fa72f05
Binary files /dev/null and b/agendas/2024-05-02.pdf differ
diff --git a/bin/do.rake b/bin/do.rake
index a985ebf..584a0c4 100644
--- a/bin/do.rake
+++ b/bin/do.rake
@@ -26,43 +26,44 @@ namespace :inst do
     puts 'Instruction database OK'
   end
 
-  desc 'Generate documentation for the instruction schema'
-  task :schema_doc do
-    s = JSON.parse(File.read("#{ROOT}/insts/inst_schema.json"))
+  namespace :render do
 
-    t = ERB.new(<<~TEMPLATE, trim_mode: '-'
-      = <%= title %>
+    desc 'Generate documentation for the instruction schema'
+    task :schema_doc do
+      s = JSON.parse(File.read("#{ROOT}/insts/inst_schema.json"))
 
-      <%= description %>
+      t = ERB.new(<<~TEMPLATE, trim_mode: '-'
+        = <%= title %>
 
-      == Properties
+        <%= description %>
 
-      [cols="1,2,2"]
-      |===
-      | Name | Description | Attributes
+        == Properties
 
-      <% items['properties'].each do |name, attr| %>
-      a| `<%= name %>`
+        [cols="1,2,2"]
+        |===
+        | Name | Description | Attributes
 
-      | <%= attr['description'] %>
+        <% items['properties'].each do |name, attr| %>
+        a| `<%= name %>`
 
-      a|
-      [horizontal]
-      Type:: <%= attr['type'] %>
-      <%- if attr.key?('examples') -%>
-      Examples:: <%= attr['examples'].join(', ') %>
-      <%- end -%>
-      Required?:: <%= items['required_properties'].any?(key) %>
+        | <%= attr['description'] %>
 
-      <% end %>
-    TEMPLATE
-    )
+        a|
+        [horizontal]
+        Type:: <%= attr['type'] %>
+        <%- if attr.key?('examples') -%>
+        Examples:: <%= attr['examples'].join(', ') %>
+        <%- end -%>
+        Required?:: <%= items['required_properties'].any?(key) %>
 
-    puts 'Writing documentation to insts/inst_schema.adoc'
-    File.write "#{ROOT}/insts/inst_schema.adoc", t.result(OpenStruct.new(s).instance_eval { binding })
-  end
+        <% end %>
+      TEMPLATE
+      )
+
+      puts 'Writing documentation to insts/inst_schema.adoc'
+      File.write "#{ROOT}/insts/inst_schema.adoc", t.result(OpenStruct.new(s).instance_eval { binding })
+    end
 
-  namespace :render do
     desc 'Generate Asciidoc table view of instruction database'
     task :adoc do
       insts = Dir.glob("#{ROOT}/insts/*.yaml").map { |f| YAML.load(File.read(f)) }.flatten
diff --git a/convert.rb b/convert.rb
new file mode 100644
index 0000000..110b565
--- /dev/null
+++ b/convert.rb
@@ -0,0 +1,56 @@
+require 'yaml'
+
+file = File.realpath(ARGV[0])
+
+lines = File.readlines(file)
+
+keys = lines[0].split(',')
+
+objs = []
+
+keymap = {
+  'Instruction' => 'mnemonic',
+  'Enc Size' => 'enc_size',
+  'Base' => 'base',
+  'Processor Class' => 'class',
+  'Donated by' => 'donator',
+  'Known impl?' => 'implemented',
+  'Description' => 'description',
+  'free bits' => 'free_bits',
+  'Notes' => 'notes'
+}
+
+lines[1..-1].each do |line|
+  values = line.split(',')
+  obj = {}
+  keys.each_index do |idx|
+    break if idx > 0 && (keys[idx-1] == "Notes")
+    if keys[idx] == "Enc Size" || keys[idx] == 'free bits'
+      obj[keymap[keys[idx]]] = values[idx].to_i
+    elsif keys[idx] == 'Known impl?'
+      obj['implemented'] = values[idx] == 'No' ? false : true
+    elsif keys[idx] == "Category"
+      obj['categories'] = []
+      values[idx].split(' ').each do |cat|
+        obj['categories'] << cat[1..-1]
+      end
+    elsif keys[idx] == "# srcs"
+      obj['srcs'] = values[idx].to_i
+    elsif keys[idx] == "# dsts"
+      obj['dsts'] = values[idx].to_i
+    elsif keys[idx] == "% 32-bit SROS" || keys[idx] == "% of remaining 32-bit SROS" || keys[idx] == "R-type Equiv"
+      # skip
+    else
+      if keymap.key?(keys[idx])
+        obj[keymap[keys[idx]]] = values[idx]
+      else
+        obj[keys[idx]] = values[idx]
+      end
+    end
+  end
+  objs << obj if !values[0].nil? && !values[0].empty?
+end
+
+
+puts "# yaml-language-server: $schema=inst_schema.json"
+puts YAML.dump(objs)
\ No newline at end of file
diff --git a/minutes/2024-05-02.adoc b/minutes/2024-05-02.adoc
new file mode 100644
index 0000000..3cdf212
--- /dev/null
+++ b/minutes/2024-05-02.adoc
@@ -0,0 +1,41 @@
+= Minutes for April 18, 2024
+
+== Attendees
+
+ * Derek Hower (Qualcomm)
+ * Phillip Tomsich (VRULL)
+ * Ved Shanbhogue (Rivos)
+ * James Ball (Qualcomm)
+ * Al Martin (Akeana)
+ * Allen Baum (Esperanto)
+ * Ana Pazos (Qualcomm)
+ * Christian Herber (NXP)
+ * David Weaver (Akeana)
+ * Greg Favor (Ventana)
+ * Paul Sherman (Individual)
+ * Shashank Nemawarkar (Individual)
+
+== Artifacts
+
+ * https://github.com/riscv-admin/riscv-scalar-efficiency/blob/main/agendas/2024-05-02.pdf[slides]
+
+== Topics
+
+Process::
+
+ * Call for Chairs out, nominations due May 10, 2024
+
+Load/Store Pair::
+
+ * Apps & Tools HC requested we investigate feasibility of merging SE proposals for load/store pair with RV32 load double, currently a fast-track (Zilsd)
+ ** No conclusion reached in this meeting
+ * Compared two extant proposals:
+ ** Alibaba T-Head
+ ** Qualcomm
+ * AI: Derek will collect additional data on Qualcomm version
+ ** Breakdown in use of variants
+ ** Breakdown by workload
+ ** Verify data vs. C extension
+ * AI: Verify with Alibaba that there is no alignment constraint on their version
+ * AI: VRULL will provide data on Aliababa extension to SE mailing list
+ * Discussed exception/consistency semantics for load/store pair; see slides
\ No newline at end of file