Error in CPL File of PCB production

[RaW79]

Hi

just wanted to have a lool and uploaded your production files to JCLPCB but it stops with an error for the CPL file which seams to be the designations.csv in the git folder.

Guess the error is caused by the entry "REF**:1" in line 23

I was not able to figure out what component should be in there instead and kindly ask if anybody can support/correct the designations.csv file

Big thanks!

[revk]

Uh, you load the gerbers (zip), bom.csv, and positions.csv

Not designators.csv

[RaW79]

Without CPL JCLPCB offers no way to go on

[revk]

The CPL file is positions.csv - upload it!

[RaW79]

hello @revk are there also production files available for the faikin+ module?

[revk]

I make a dual interface one, that should be on here.

[RaW79]

Is it under developement or online? I´m looking around for the information about faikin+ module but could not find it anymore. Looking for a connection board to analyze S21 protocol. Thx!

[revk]

OK "Faikin+" has been the "next board" a bit.

I also made a dual input/output board for a while. But no, it is no longer in the repository. You can find in history, but it was just a test board.

There is no real Faikin+ as such now.